Model { Name "wlan_phy_rx_pmd" Version 7.8 MdlSubVersion 0 GraphicalInterface { NumRootInports 0 NumRootOutports 0 ParameterArgumentNames "" ComputedModelVersion "1.994" NumModelReferences 0 NumTestPointedSignals 0 } SavedCharacterEncoding "windows-1252" PostLoadFcn "wlan_phy_rx_init" SaveDefaultBlockParams on ScopeRefreshTime 0.035000 OverrideScopeRefreshTime on DisableAllScopes off DataTypeOverride "UseLocalSettings" DataTypeOverrideAppliesTo "AllNumericTypes" MinMaxOverflowLogging "UseLocalSettings" MinMaxOverflowArchiveMode "Overwrite" FPTRunName "Run 1" MaxMDLFileLineLength 120 InitFcn "wlan_phy_rx_init" StartFcn "wlan_phy_rx_init" Created "Fri Jan 15 15:32:18 2016" Creator "murphpo" UpdateHistory "UpdateHistoryNever" ModifiedByFormat "%" LastModifiedBy "murphpo" ModifiedDateFormat "%" LastModifiedDate "Wed Feb 26 16:21:49 2020" RTWModifiedTimeStamp 504634358 ModelVersionFormat "1.%" ConfigurationManager "None" SampleTimeColors off SampleTimeAnnotations off LibraryLinkDisplay "disabled" WideLines off ShowLineDimensions off ShowPortDataTypes on ShowDesignRanges off ShowLoopsOnError on IgnoreBidirectionalLines off ShowStorageClass off ShowTestPointIcons on ShowSignalResolutionIcons on ShowViewerIcons on SortedOrder off ExecutionContextIcon off ShowLinearizationAnnotations on BlockNameDataTip off BlockParametersDataTip off BlockDescriptionStringDataTip off ToolBar on StatusBar on BrowserShowLibraryLinks off BrowserLookUnderMasks off SimulationMode "normal" LinearizationMsg "none" Profile off ParamWorkspaceSource "MATLABWorkspace" AccelSystemTargetFile "accel.tlc" AccelTemplateMakefile "accel_default_tmf" AccelMakeCommand "make_rtw" TryForcingSFcnDF off Object { $PropName "DataLoggingOverride" $ObjectID 1 $ClassName "Simulink.SimulationData.ModelLoggingInfo" model_ "wlan_phy_rx_pmd" overrideMode_ [0.0] Array { Type "Cell" Dimension 1 Cell "wlan_phy_rx_pmd" PropName "logAsSpecifiedByModels_" } Array { Type "Cell" Dimension 1 Cell [] PropName "logAsSpecifiedByModelsSSIDs_" } } RecordCoverage off CovPath "/" CovSaveName "covdata" CovMetricSettings "dw" CovNameIncrementing off CovHtmlReporting on CovForceBlockReductionOff on covSaveCumulativeToWorkspaceVar on CovSaveSingleToWorkspaceVar on CovCumulativeVarName "covCumulativeData" CovCumulativeReport off CovReportOnPause on CovModelRefEnable "Off" CovExternalEMLEnable off ExtModeBatchMode off ExtModeEnableFloating on ExtModeTrigType "manual" ExtModeTrigMode "normal" ExtModeTrigPort "1" ExtModeTrigElement "any" ExtModeTrigDuration 1000 ExtModeTrigDurationFloating "auto" ExtModeTrigHoldOff 0 ExtModeTrigDelay 0 ExtModeTrigDirection "rising" ExtModeTrigLevel 0 ExtModeArchiveMode "off" ExtModeAutoIncOneShot off ExtModeIncDirWhenArm off ExtModeAddSuffixToVar off ExtModeWriteAllDataToWs off ExtModeArmWhenConnect on ExtModeSkipDownloadWhenConnect off ExtModeLogAll on ExtModeAutoUpdateStatusClock on BufferReuse on ShowModelReferenceBlockVersion off ShowModelReferenceBlockIO off Array { Type "Handle" Dimension 1 Simulink.ConfigSet { $ObjectID 2 Version "1.11.1" Array { Type "Handle" Dimension 8 Simulink.SolverCC { $ObjectID 3 Version "1.11.1" StartTime "0.0" StopTime "rx_sim.sim_time" AbsTol "auto" FixedStep "auto" InitialStep "auto" MaxNumMinSteps "-1" MaxOrder 5 ZcThreshold "auto" ConsecutiveZCsStepRelTol "10*128*eps" MaxConsecutiveZCs "1000" ExtrapolationOrder 4 NumberNewtonIterations 1 MaxStep "auto" MinStep "auto" MaxConsecutiveMinStep "1" RelTol "1e-3" SolverMode "SingleTasking" ConcurrentTasks off Solver "VariableStepDiscrete" SolverName "VariableStepDiscrete" SolverJacobianMethodControl "auto" ShapePreserveControl "DisableAll" ZeroCrossControl "UseLocalSettings" ZeroCrossAlgorithm "Nonadaptive" AlgebraicLoopSolver "TrustRegion" SolverResetMethod "Fast" PositivePriorityOrder off AutoInsertRateTranBlk off SampleTimeConstraint "Unconstrained" InsertRTBMode "Whenever possible" } Simulink.DataIOCC { $ObjectID 4 Version "1.11.1" Decimation "1" ExternalInput "[t, u]" FinalStateName "xFinal" InitialState "xInitial" LimitDataPoints on MaxDataPoints "1000" LoadExternalInput off LoadInitialState off SaveFinalState off SaveCompleteFinalSimState off SaveFormat "Array" SignalLoggingSaveFormat "ModelDataLogs" SaveOutput on SaveState off SignalLogging on DSMLogging on InspectSignalLogs off SaveTime on ReturnWorkspaceOutputs off StateSaveName "xout" TimeSaveName "tout" OutputSaveName "yout" SignalLoggingName "logsout" DSMLoggingName "dsmout" OutputOption "RefineOutputTimes" OutputTimes "[]" ReturnWorkspaceOutputsName "out" Refine "1" } Simulink.OptimizationCC { $ObjectID 5 Version "1.11.1" Array { Type "Cell" Dimension 8 Cell "BooleansAsBitfields" Cell "PassReuseOutputArgsAs" Cell "PassReuseOutputArgsThreshold" Cell "ZeroExternalMemoryAtStartup" Cell "ZeroInternalMemoryAtStartup" Cell "OptimizeModelRefInitCode" Cell "NoFixptDivByZeroProtection" Cell "UseSpecifiedMinMax" PropName "DisabledProps" } BlockReduction on BooleanDataType on ConditionallyExecuteInputs on InlineParams on UseIntDivNetSlope off UseFloatMulNetSlope off UseSpecifiedMinMax off InlineInvariantSignals off OptimizeBlockIOStorage on BufferReuse on EnhancedBackFolding off StrengthReduction off ExpressionFolding on BooleansAsBitfields off BitfieldContainerType "uint_T" EnableMemcpy on MemcpyThreshold 64 PassReuseOutputArgsAs "Structure reference" ExpressionDepthLimit 2147483647 FoldNonRolledExpr on LocalBlockOutputs on RollThreshold 5 SystemCodeInlineAuto off StateBitsets off DataBitsets off UseTempVars off ZeroExternalMemoryAtStartup on ZeroInternalMemoryAtStartup on InitFltsAndDblsToZero off NoFixptDivByZeroProtection off EfficientFloat2IntCast off EfficientMapNaN2IntZero on OptimizeModelRefInitCode off LifeSpan "inf" MaxStackSize "Inherit from target" BufferReusableBoundary on SimCompilerOptimization "Off" AccelVerboseBuild off AccelParallelForEachSubsystem on } Simulink.DebuggingCC { $ObjectID 6 Version "1.11.1" RTPrefix "error" ConsistencyChecking "none" ArrayBoundsChecking "none" SignalInfNanChecking "none" SignalRangeChecking "none" ReadBeforeWriteMsg "UseLocalSettings" WriteAfterWriteMsg "UseLocalSettings" WriteAfterReadMsg "UseLocalSettings" AlgebraicLoopMsg "warning" ArtificialAlgebraicLoopMsg "warning" SaveWithDisabledLinksMsg "warning" SaveWithParameterizedLinksMsg "warning" CheckSSInitialOutputMsg on UnderspecifiedInitializationDetection "Classic" MergeDetectMultiDrivingBlocksExec "none" CheckExecutionContextPreStartOutputMsg off CheckExecutionContextRuntimeOutputMsg off SignalResolutionControl "UseLocalSettings" BlockPriorityViolationMsg "warning" MinStepSizeMsg "warning" TimeAdjustmentMsg "none" MaxConsecutiveZCsMsg "error" MaskedZcDiagnostic "warning" IgnoredZcDiagnostic "warning" SolverPrmCheckMsg "warning" InheritedTsInSrcMsg "warning" DiscreteInheritContinuousMsg "warning" MultiTaskDSMMsg "error" MultiTaskCondExecSysMsg "error" MultiTaskRateTransMsg "error" SingleTaskRateTransMsg "none" TasksWithSamePriorityMsg "warning" SigSpecEnsureSampleTimeMsg "warning" CheckMatrixSingularityMsg "none" IntegerOverflowMsg "warning" Int32ToFloatConvMsg "warning" ParameterDowncastMsg "error" ParameterOverflowMsg "error" ParameterUnderflowMsg "none" ParameterPrecisionLossMsg "warning" ParameterTunabilityLossMsg "warning" FixptConstUnderflowMsg "none" FixptConstOverflowMsg "none" FixptConstPrecisionLossMsg "none" UnderSpecifiedDataTypeMsg "none" UnnecessaryDatatypeConvMsg "none" VectorMatrixConversionMsg "none" InvalidFcnCallConnMsg "error" FcnCallInpInsideContextMsg "Enable All" SignalLabelMismatchMsg "none" UnconnectedInputMsg "none" UnconnectedOutputMsg "none" UnconnectedLineMsg "none" SFcnCompatibilityMsg "none" FrameProcessingCompatibilityMsg "warning" UniqueDataStoreMsg "none" BusObjectLabelMismatch "warning" RootOutportRequireBusObject "warning" AssertControl "UseLocalSettings" EnableOverflowDetection off ModelReferenceIOMsg "none" ModelReferenceMultiInstanceNormalModeStructChecksumCheck "error" ModelReferenceVersionMismatchMessage "none" ModelReferenceIOMismatchMessage "none" ModelReferenceCSMismatchMessage "none" UnknownTsInhSupMsg "warning" ModelReferenceDataLoggingMessage "warning" ModelReferenceSymbolNameMessage "warning" ModelReferenceExtraNoncontSigs "error" StateNameClashWarn "warning" SimStateInterfaceChecksumMismatchMsg "warning" SimStateOlderReleaseMsg "error" InitInArrayFormatMsg "warning" StrictBusMsg "ErrorLevel1" BusNameAdapt "WarnAndRepair" NonBusSignalsTreatedAsBus "none" LoggingUnavailableSignals "error" BlockIODiagnostic "none" SFUnusedDataAndEventsDiag "warning" SFUnexpectedBacktrackingDiag "warning" SFInvalidInputDataAccessInChartInitDiag "warning" SFNoUnconditionalDefaultTransitionDiag "warning" SFTransitionOutsideNaturalParentDiag "warning" SFUnconditionalTransitionShadowingDiag "warning" } Simulink.HardwareCC { $ObjectID 7 Version "1.11.1" ProdBitPerChar 8 ProdBitPerShort 16 ProdBitPerInt 32 ProdBitPerLong 32 ProdBitPerFloat 32 ProdBitPerDouble 64 ProdBitPerPointer 32 ProdLargestAtomicInteger "Char" ProdLargestAtomicFloat "None" ProdIntDivRoundTo "Undefined" ProdEndianess "Unspecified" ProdWordSize 32 ProdShiftRightIntArith on ProdHWDeviceType "32-bit Generic" TargetBitPerChar 8 TargetBitPerShort 16 TargetBitPerInt 32 TargetBitPerLong 32 TargetBitPerFloat 32 TargetBitPerDouble 64 TargetBitPerPointer 32 TargetLargestAtomicInteger "Char" TargetLargestAtomicFloat "None" TargetShiftRightIntArith on TargetIntDivRoundTo "Undefined" TargetEndianess "Unspecified" TargetWordSize 32 TargetTypeEmulationWarnSuppressLevel 0 TargetPreprocMaxBitsSint 32 TargetPreprocMaxBitsUint 32 TargetHWDeviceType "Specified" TargetUnknown off ProdEqTarget on } Simulink.ModelReferenceCC { $ObjectID 8 Version "1.11.1" UpdateModelReferenceTargets "IfOutOfDateOrStructuralChange" CheckModelReferenceTargetMessage "error" EnableParallelModelReferenceBuilds off ParallelModelReferenceErrorOnInvalidPool on ParallelModelReferenceMATLABWorkerInit "None" ModelReferenceNumInstancesAllowed "Multi" PropagateVarSize "Infer from blocks in model" ModelReferencePassRootInputsByReference on ModelReferenceMinAlgLoopOccurrences off PropagateSignalLabelsOutOfModel off SupportModelReferenceSimTargetCustomCode off } Simulink.SFSimCC { $ObjectID 9 Version "1.11.1" SFSimEnableDebug on SFSimOverflowDetection on SFSimEcho on SimBlas on SimCtrlC on SimExtrinsic on SimIntegrity on SimUseLocalCustomCode off SimParseCustomCode on SimBuildMode "sf_incremental_build" } Simulink.RTWCC { $BackupClass "Simulink.RTWCC" $ObjectID 10 Version "1.11.1" Array { Type "Cell" Dimension 8 Cell "IncludeHyperlinkInReport" Cell "GenerateTraceInfo" Cell "GenerateTraceReport" Cell "GenerateTraceReportSl" Cell "GenerateTraceReportSf" Cell "GenerateTraceReportEml" Cell "GenerateSLWebview" Cell "GenerateCodeMetricsReport" PropName "DisabledProps" } SystemTargetFile "grt.tlc" GenCodeOnly off MakeCommand "make_rtw" GenerateMakefile on TemplateMakefile "grt_default_tmf" GenerateReport off SaveLog off RTWVerbose on RetainRTWFile off ProfileTLC off TLCDebug off TLCCoverage off TLCAssert off ProcessScriptMode "Default" ConfigurationMode "Optimized" ConfigAtBuild off RTWUseLocalCustomCode off RTWUseSimCustomCode off IncludeHyperlinkInReport off LaunchReport off TargetLang "C" IncludeBusHierarchyInRTWFileBlockHierarchyMap off IncludeERTFirstTime off GenerateTraceInfo off GenerateTraceReport off GenerateTraceReportSl off GenerateTraceReportSf off GenerateTraceReportEml off GenerateCodeInfo off GenerateSLWebview off GenerateCodeMetricsReport off RTWCompilerOptimization "Off" CheckMdlBeforeBuild "Off" CustomRebuildMode "OnUpdate" Array { Type "Handle" Dimension 2 Simulink.CodeAppCC { $ObjectID 11 Version "1.11.1" Array { Type "Cell" Dimension 21 Cell "IgnoreCustomStorageClasses" Cell "IgnoreTestpoints" Cell "InsertBlockDesc" Cell "InsertPolySpaceComments" Cell "SFDataObjDesc" Cell "MATLABFcnDesc" Cell "SimulinkDataObjDesc" Cell "DefineNamingRule" Cell "SignalNamingRule" Cell "ParamNamingRule" Cell "InlinedPrmAccess" Cell "CustomSymbolStr" Cell "CustomSymbolStrGlobalVar" Cell "CustomSymbolStrType" Cell "CustomSymbolStrField" Cell "CustomSymbolStrFcn" Cell "CustomSymbolStrFcnArg" Cell "CustomSymbolStrBlkIO" Cell "CustomSymbolStrTmpVar" Cell "CustomSymbolStrMacro" Cell "ReqsInCode" PropName "DisabledProps" } ForceParamTrailComments off GenerateComments on IgnoreCustomStorageClasses on IgnoreTestpoints off IncHierarchyInIds off MaxIdLength 31 PreserveName off PreserveNameWithParent off ShowEliminatedStatement off IncAutoGenComments off SimulinkDataObjDesc off SFDataObjDesc off MATLABFcnDesc off IncDataTypeInIds off MangleLength 1 CustomSymbolStrGlobalVar "$R$N$M" CustomSymbolStrType "$N$R$M" CustomSymbolStrField "$N$M" CustomSymbolStrFcn "$R$N$M$F" CustomSymbolStrFcnArg "rt$I$N$M" CustomSymbolStrBlkIO "rtb_$N$M" CustomSymbolStrTmpVar "$N$M" CustomSymbolStrMacro "$R$N$M" DefineNamingRule "None" ParamNamingRule "None" SignalNamingRule "None" InsertBlockDesc off InsertPolySpaceComments off SimulinkBlockComments on MATLABSourceComments off EnableCustomComments off InlinedPrmAccess "Literals" ReqsInCode off UseSimReservedNames off } Simulink.GRTTargetCC { $BackupClass "Simulink.TargetCC" $ObjectID 12 Version "1.11.1" Array { Type "Cell" Dimension 16 Cell "GeneratePreprocessorConditionals" Cell "IncludeMdlTerminateFcn" Cell "CombineOutputUpdateFcns" Cell "SuppressErrorStatus" Cell "ERTCustomFileBanners" Cell "GenerateSampleERTMain" Cell "GenerateTestInterfaces" Cell "ModelStepFunctionPrototypeControlCompliant" Cell "CPPClassGenCompliant" Cell "MultiInstanceERTCode" Cell "PurelyIntegerCode" Cell "SupportComplex" Cell "SupportAbsoluteTime" Cell "SupportContinuousTime" Cell "SupportNonInlinedSFcns" Cell "PortableWordSizes" PropName "DisabledProps" } TargetFcnLib "ansi_tfl_table_tmw.mat" TargetLibSuffix "" TargetPreCompLibLocation "" TargetFunctionLibrary "ANSI_C" UtilityFuncGeneration "Auto" ERTMultiwordTypeDef "System defined" CodeExecutionProfiling off ERTMultiwordLength 256 MultiwordLength 2048 GenerateFullHeader on GenerateSampleERTMain off GenerateTestInterfaces off IsPILTarget off ModelReferenceCompliant on ParMdlRefBuildCompliant on CompOptLevelCompliant on ConcurrentExecutionCompliant on IncludeMdlTerminateFcn on GeneratePreprocessorConditionals "Disable all" CombineOutputUpdateFcns off CombineSignalStateStructs off SuppressErrorStatus off ERTFirstTimeCompliant off IncludeFileDelimiter "Auto" ERTCustomFileBanners off SupportAbsoluteTime on LogVarNameModifier "rt_" MatFileLogging on MultiInstanceERTCode off SupportNonFinite on SupportComplex on PurelyIntegerCode off SupportContinuousTime on SupportNonInlinedSFcns on SupportVariableSizeSignals off EnableShiftOperators on ParenthesesLevel "Nominal" PortableWordSizes off ModelStepFunctionPrototypeControlCompliant off CPPClassGenCompliant off AutosarCompliant off UseMalloc off ExtMode off ExtModeStaticAlloc off ExtModeTesting off ExtModeStaticAllocSize 1000000 ExtModeTransport 0 ExtModeMexFile "ext_comm" ExtModeIntrfLevel "Level1" RTWCAPISignals off RTWCAPIParams off RTWCAPIStates off RTWCAPIRootIO off GenerateASAP2 off } PropName "Components" } } PropName "Components" } Name "Configuration" CurrentDlgPage "Solver" ConfigPrmDlgPosition [ 840, 485, 1720, 1115 ] } PropName "ConfigurationSets" } Simulink.ConfigSet { $PropName "ActiveConfigurationSet" $ObjectID 2 } BlockDefaults { ForegroundColor "black" BackgroundColor "white" DropShadow off NamePlacement "normal" FontName "Helvetica" FontSize 10 FontWeight "normal" FontAngle "normal" ShowName on BlockRotation 0 BlockMirror off } AnnotationDefaults { HorizontalAlignment "center" VerticalAlignment "middle" ForegroundColor "black" BackgroundColor "white" DropShadow off FontName "Helvetica" FontSize 10 FontWeight "normal" FontAngle "normal" UseDisplayTextAsClickCallback off } LineDefaults { FontName "Helvetica" FontSize 9 FontWeight "normal" FontAngle "normal" } BlockParameterDefaults { Block { BlockType Abs ZeroCross on SampleTime "-1" OutMin "[]" OutMax "[]" OutDataTypeStr "Inherit: Same as input" LockScale off RndMeth "Floor" SaturateOnIntegerOverflow on } Block { BlockType BusCreator Inputs "4" DisplayOption "none" OutDataTypeStr "Inherit: auto" NonVirtualBus off } Block { BlockType BusSelector OutputAsBus off } Block { BlockType ComplexToRealImag Output "Real and imag" SampleTime "-1" } Block { BlockType Constant Value "1" VectorParams1D on SamplingMode "Sample based" OutMin "[]" OutMax "[]" OutDataTypeStr "Inherit: Inherit from 'Constant value'" LockScale off SampleTime "inf" FramePeriod "inf" PreserveConstantTs off } Block { BlockType DiscretePulseGenerator PulseType "Sample based" TimeSource "Use simulation time" Amplitude "1" Period "2" PulseWidth "1" PhaseDelay "0" SampleTime "1" VectorParams1D on } Block { BlockType Display Format "short" Decimation "10" Floating off SampleTime "-1" } Block { BlockType From IconDisplay "Tag" TagVisibility "local" } Block { BlockType FromWorkspace VariableName "simulink_input" SampleTime "-1" Interpolate on ZeroCross off OutputAfterFinalValue "Extrapolation" } Block { BlockType Goto IconDisplay "Tag" } Block { BlockType GotoTagVisibility GotoTag "A" } Block { BlockType Inport Port "1" OutputFunctionCall off OutMin "[]" OutMax "[]" OutDataTypeStr "Inherit: auto" LockScale off BusOutputAsStruct off PortDimensions "-1" VarSizeSig "Inherit" SampleTime "-1" SignalType "auto" SamplingMode "auto" LatchByDelayingOutsideSignal off LatchInputForFeedbackSignals off Interpolate on } Block { BlockType Outport Port "1" OutMin "[]" OutMax "[]" OutDataTypeStr "Inherit: auto" LockScale off BusOutputAsStruct off PortDimensions "-1" VarSizeSig "Inherit" SampleTime "-1" SignalType "auto" SamplingMode "auto" SourceOfInitialOutputValue "Dialog" OutputWhenDisabled "held" InitialOutput "[]" } Block { BlockType Product Inputs "2" Multiplication "Element-wise(.*)" CollapseMode "All dimensions" CollapseDim "1" InputSameDT on OutMin "[]" OutMax "[]" OutDataTypeStr "Inherit: Same as first input" LockScale off RndMeth "Zero" SaturateOnIntegerOverflow on SampleTime "-1" } Block { BlockType RealImagToComplex Input "Real and imag" ConstantPart "0" SampleTime "-1" } Block { BlockType Scope ModelBased off TickLabels "OneTimeTick" ZoomMode "on" Grid "on" TimeRange "auto" YMin "-5" YMax "5" SaveToWorkspace off SaveName "ScopeData" LimitDataPoints on MaxDataPoints "5000" Decimation "1" SampleInput off SampleTime "-1" } Block { BlockType Signum ZeroCross on SampleTime "-1" } Block { BlockType SubSystem ShowPortLabels "FromPortIcon" Permissions "ReadWrite" PermitHierarchicalResolution "All" TreatAsAtomicUnit off CheckFcnCallInpInsideContextMsg off SystemSampleTime "-1" RTWFcnNameOpts "Auto" RTWFileNameOpts "Auto" RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" SimViewingDevice off DataTypeOverride "UseLocalSettings" DataTypeOverrideAppliesTo "AllNumericTypes" MinMaxOverflowLogging "UseLocalSettings" SFBlockType "NONE" Variant off GeneratePreprocessorConditionals off } Block { BlockType Sum IconShape "rectangular" Inputs "++" CollapseMode "All dimensions" CollapseDim "1" InputSameDT on AccumDataTypeStr "Inherit: Inherit via internal rule" OutMin "[]" OutMax "[]" OutDataTypeStr "Inherit: Same as first input" LockScale off RndMeth "Floor" SaturateOnIntegerOverflow on SampleTime "-1" } Block { BlockType Terminator } Block { BlockType ToWorkspace VariableName "simulink_output" MaxDataPoints "1000" Decimation "1" SampleTime "0" FixptAsFi off NumInputs "1" } Block { BlockType ZeroOrderHold SampleTime "1" } } System { Name "wlan_phy_rx_pmd" Location [202, 70, 1808, 1180] Open on ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "126" ReportName "simulink-default.rpt" SIDHighWatermark "18166" Block { BlockType Reference Name " System Generator" SID "1" Tag "genX" Ports [] Position [427, 282, 477, 332] ShowName off AttributesFormatString "System\\nGenerator" LibraryVersion "1.2" UserDataPersistent on UserData "DataTag0" SourceBlock "xbsIndex_r4/ System Generator" SourceType "Xilinx System Generator Block" infoedit " System Generator" xilinxfamily "virtex6" part "xc6vlx240t" speed "-2" package "ff1156" synthesis_tool "XST" clock_wrapper "Clock Enables" directory "./pcore_rx_v402a" proj_type "Project Navigator" Synth_file "XST Defaults" Impl_file "ISE Defaults" testbench off simulink_period "1" sysclk_period "6.25" dcm_input_clock_period "10" incr_netlist off trim_vbits "Everywhere in SubSystem" dbl_ovrd "According to Block Masks" core_generation "According to Block Masks" run_coregen off deprecated_control off eval_field "0" has_advanced_control "0" sggui_pos "766,488,464,470" block_type "sysgen" sg_icon_stat "50,50,0,0,token,white,0,58c5b5770fe5f7c311f53dbc6e73f0f6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 50 50 0 ],[1 1 1 ]" ");\npatch([1.6375 16.81 27.31 37.81 48.31 27.31 12.1375 1.6375 ],[36.655 36.655 47.155 36.655 47.155 47.155 47.1" "55 36.655 ],[0.933333 0.203922 0.141176 ]);\npatch([12.1375 27.31 16.81 1.6375 12.1375 ],[26.155 26.155 36.655 3" "6.655 26.155 ],[0.698039 0.0313725 0.219608 ]);\npatch([1.6375 16.81 27.31 12.1375 1.6375 ],[15.655 15.655 26.15" "5 26.155 15.655 ],[0.933333 0.203922 0.141176 ]);\npatch([12.1375 48.31 37.81 27.31 16.81 1.6375 12.1375 ],[5.15" "5 5.155 15.655 5.155 15.655 15.655 5.155 ],[0.698039 0.0313725 0.219608 ]);\nfprintf('','COMMENT: end icon graph" "ics');\nfprintf('','COMMENT: begin icon text');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "CFO & Samp Buffer" SID "2" Ports [7, 4] Position [375, 142, 495, 228] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "CFO & Samp Buffer" Location [88, 301, 2330, 1285] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "110" Block { BlockType Inport Name "FFT tready" SID "3" Position [1060, 543, 1090, 557] IconDisplay "Port number" } Block { BlockType Inport Name "Rx I" SID "4" Position [155, 393, 185, 407] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "Rx Q" SID "5" Position [120, 413, 150, 427] NamePlacement "alternate" Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "IQ Valid" SID "6" Position [80, 433, 110, 447] NamePlacement "alternate" Port "4" IconDisplay "Port number" } Block { BlockType Inport Name "Pkt Det" SID "7" Position [80, 353, 110, 367] NamePlacement "alternate" Port "5" IconDisplay "Port number" } Block { BlockType Inport Name "LTS Sync" SID "8" Position [340, 503, 370, 517] Port "6" IconDisplay "Port number" } Block { BlockType Inport Name "Reset" SID "9" Position [340, 563, 370, 577] NamePlacement "alternate" Port "7" IconDisplay "Port number" } Block { BlockType Scope Name "ADC/Corr" SID "10" Ports [8] Position [855, 178, 890, 307] ZOrder -3 Floating off Location [705, 125, 1643, 1184] Open off NumInputPorts "8" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" } List { ListType ScopeGraphics FigureColor "[0.5 0.5 0.5]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "10000 " YMin "-1~-1~0~-1~-1~-1~-1~-1" YMax "1~1~1~1~1~1~1~1" SaveName "ScopeData8" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType SubSystem Name "CFO\nCorrection" SID "11" Ports [7, 4] Position [890, 349, 955, 521] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "CFO\nCorrection" Location [88, 301, 2330, 1301] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "178" Block { BlockType Inport Name "I " SID "12" Position [245, 248, 275, 262] IconDisplay "Port number" } Block { BlockType Inport Name "Q " SID "13" Position [245, 228, 275, 242] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "DDS Run" SID "14" Position [120, 503, 150, 517] NamePlacement "alternate" Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "Valid" SID "15" Position [245, 273, 275, 287] Port "4" IconDisplay "Port number" } Block { BlockType Inport Name "tlast" SID "16" Position [245, 313, 275, 327] Port "5" IconDisplay "Port number" } Block { BlockType Inport Name "CFO Est" SID "17" Position [185, 388, 215, 402] Port "6" IconDisplay "Port number" } Block { BlockType Inport Name "Reset" SID "14922" Position [120, 428, 150, 442] Port "7" IconDisplay "Port number" } Block { BlockType Scope Name "CFO Corr" SID "18" Ports [9] Position [1085, 111, 1120, 269] ZOrder -3 Floating off Location [1, 45, 1833, 1199] Open off NumInputPorts "9" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" axes9 "%" } List { ListType ScopeGraphics FigureColor "[0.5 0.5 0.5]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "35000" YMin "0~-0.4~0~-1~0~0~-0.4~0~-5" YMax "1~0.4~1~2~1~1~0.4~1~5" SaveName "ScopeData3" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType Reference Name "Complex Multiplier 5.0 " SID "19" Ports [7, 4] Position [675, 298, 860, 402] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Complex Multiplier 5.0 " SourceType "Xilinx Complex Multiplier 5.0 Block" hasatlast off hasatuser on atuserwidth "1" hasbtlast off hasbtuser off btuserwidth "1" multtype "Use_Mults" optimizegoal "Performance" flowcontrol "NonBlocking" outputwidth "16" roundmode "Truncate" hasctrltlast off hasctrltuser off ctrltuserwidth "1" outtlastbehv "Null" latencyconfig "Manual" minimumlatency "2" aclken off aresetn off trim_axipin_name on aportwidth "63" bportwidth "63" ip_name "Complex Multiplier" ip_version "5.0" dsptool_ready "true" ipcore_usecache "true" ipcore_useipmodelcache "true" ipcore_verbose "false" ipcore_latency_parameter "'minimumlatency'" wrapper_available "true" port_translation_map "{ 'aclken' => 'en', 'aresetn' => 'rst'}" structural_sim "false" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "cmpy_v5_0" sg_icon_stat "185,104,7,4,white,blue,0,18f8c464,right,,[2 2 2 2 3 3 3 ],[4 4 4 4 ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 0 3 3 ],[103 46 46 103 ],[6.025000" "e-001 6.400000e-001 7.075000e-001 ]);\npatch([0 0 3 3 ],[43 1 1 43 ],[4.350000e-001 4.600000e-001 5.050000e-001" " ]);\npatch([182 182 185 185 ],[96 3 3 96 ],[2.675000e-001 2.800000e-001 3.025000e-001 ]);\npatch([3 181 181 3 " "3 ],[0 0 104 104 0 ],[7.700000e-001 8.200000e-001 9.100000e-001 ]);\nplot([3 181 181 3 3 ],[0 0 104 104 0 ]);\n" "\n\npatch([60.85 81.08 95.08 109.08 123.08 95.08 74.85 60.85 ],[67.54 67.54 81.54 67.54 81.54 81.54 81.54 67.54" " ],[1 1 1 ]);\npatch([74.85 95.08 81.08 60.85 74.85 ],[53.54 53.54 67.54 67.54 53.54 ],[0.931 0.946 0.973 ]);\n" "patch([60.85 81.08 95.08 74.85 60.85 ],[39.54 39.54 53.54 53.54 39.54 ],[1 1 1 ]);\npatch([74.85 123.08 109.08 " "95.08 81.08 60.85 74.85 ],[25.54 25.54 39.54 25.54 39.54 39.54 25.54 ],[0.931 0.946 0.973 ]);\nfprintf('','COMM" "ENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' a_tv" "alid ');\ncolor('black');port_label('input',2,' a_tdata_imag ');\ncolor('black');port_label('input',3,' a_t" "data_real ');\ncolor('black');port_label('input',4,' a_tuser ');\ncolor('black');port_label('input',5,' b_t" "valid ');\ncolor('black');port_label('input',6,' b_tdata_imag ');\ncolor('black');port_label('input',7,' b_" "tdata_real ');\ncolor('black');port_label('output',1,' dout_tvalid ');\ncolor('black');port_label('output',2" ",' dout_tdata_imag ');\ncolor('black');port_label('output',3,' dout_tdata_real ');\ncolor('black');port_lab" "el('output',4,' dout_tuser ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant1" SID "20" Ports [0, 1] Position [300, 349, 330, 371] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Boolean" arith_type "Boolean" n_bits "16" bin_pt "14" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "8" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,22,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 22 22 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 22 22 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[" "14.33 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[11.33 1" "1.33 14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[8.33 8.33 11.33 11.33" " 8.33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ]," "[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncol" "or('black');port_label('output',1,'1');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant2" SID "21" Ports [0, 1] Position [555, 494, 585, 516] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "16" bin_pt "15" preci_type "Single" exp_width "8" frac_width "24" explicit_period on period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,22,0,1,white,blue,0,170720a6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 22 22 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 22 22 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[" "14.33 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[11.33 1" "1.33 14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[8.33 8.33 11.33 11.33" " 8.33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ]," "[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncol" "or('black');port_label('output',1,'0.999969482421875');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant3" SID "22" Ports [0, 1] Position [555, 469, 585, 491] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "16" bin_pt "15" preci_type "Single" exp_width "8" frac_width "24" explicit_period on period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,22,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 22 22 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 22 22 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[" "14.33 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[11.33 1" "1.33 14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[8.33 8.33 11.33 11.33" " 8.33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ]," "[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncol" "or('black');port_label('output',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant5" SID "23" Ports [0, 1] Position [580, 354, 610, 376] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Boolean" arith_type "Boolean" n_bits "16" bin_pt "14" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "8" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,22,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 22 22 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 22 22 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[" "14.33 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[11.33 1" "1.33 14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[8.33 8.33 11.33 11.33" " 8.33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ]," "[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncol" "or('black');port_label('output',1,'1');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "24" Ports [1, 1] Position [930, 356, 955, 374] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do" " not." gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "16" bin_pt "15" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.2" "2 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 " "11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);" "\npatch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label" "('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "25" Ports [1, 1] Position [930, 331, 955, 349] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do" " not." gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "16" bin_pt "15" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.2" "2 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 " "11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);" "\npatch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label" "('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert3" SID "26" Ports [1, 1] Position [275, 386, 300, 404] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do" " not." gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "26" bin_pt "26" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Flag as error" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.2" "2 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 " "11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);" "\npatch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label" "('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert4" SID "27" Ports [1, 1] Position [300, 311, 325, 329] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do" " not." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Flag as error" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.2" "2 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 " "11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);" "\npatch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label" "('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert5" SID "28" Ports [1, 1] Position [930, 381, 955, 399] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do" " not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Flag as error" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.2" "2 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 " "11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);" "\npatch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label" "('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "DDS Compiler 4.0" SID "29" Ports [4, 3] Position [410, 343, 495, 452] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/DDS Compiler 4.0 " SourceType "Xilinx DDS Compiler 4.0 Block" partspresent "Phase_Generator_and_SIN_COS_LUT" dds_clock_rate "160" channels "1" parameter_entry "Hardware_Parameters" spurious_free_dynamic_range "36" frequency_resolution "0.4" noise_shaping "None" phase_width "26" output_width "16" output_selection "Sine_and_Cosine" negative_sine off negative_cosine off amplitude_mode "Full_Range" memory_type "Auto" optimization_goal "Auto" dsp48_use "Minimal" latency_configuration "Auto" latency "6" has_phase_out off sclr_pin on clock_enable on rfd off rdy on channel_pin off explicit_period off period "1" phase_increment "Programmable" output_frequency1 "0" output_frequency2 "0" output_frequency3 "0" output_frequency4 "0" output_frequency5 "0" output_frequency6 "0" output_frequency7 "0" output_frequency8 "0" output_frequency9 "0" output_frequency10 "0" output_frequency11 "0" output_frequency12 "0" output_frequency13 "0" output_frequency14 "0" output_frequency15 "0" output_frequency16 "0" pinc1 "'0'" pinc2 "'0'" pinc3 "'0'" pinc4 "'0'" pinc5 "'0'" pinc6 "'0'" pinc7 "'0'" pinc8 "'0'" pinc9 "'0'" pinc10 "'0'" pinc11 "'0'" pinc12 "'0'" pinc13 "'0'" pinc14 "'0'" pinc15 "'0'" pinc16 "'0'" phase_offset "None" phase_offset_angles1 "0" phase_offset_angles2 "0" phase_offset_angles3 "0" phase_offset_angles4 "0" phase_offset_angles5 "0" phase_offset_angles6 "0" phase_offset_angles7 "0" phase_offset_angles8 "0" phase_offset_angles9 "0" phase_offset_angles10 "0" phase_offset_angles11 "0" phase_offset_angles12 "0" phase_offset_angles13 "0" phase_offset_angles14 "0" phase_offset_angles15 "0" phase_offset_angles16 "0" poff1 "'0'" poff2 "'0'" poff3 "'0'" poff4 "'0'" poff5 "'0'" poff6 "'0'" poff7 "'0'" poff8 "'0'" poff9 "'0'" poff10 "'0'" poff11 "'0'" poff12 "'0'" poff13 "'0'" poff14 "'0'" poff15 "'0'" poff16 "'0'" por_mode "false" gui_behaviour "Sysgen" ip_name "DDS Compiler" ip_version "4.0" dsptool_ready "true" wrapper_available "true" port_translation_map "{ 'ce' => 'en', 'sclr' => 'rst' }" ipcore_xco_need_fpga_part "true" ipcore_fpga_part "xlipgetpartsetting(gcb, {'virtex4', 'xc4vsx35', '-10', 'ff668'})" ipcore_usecache "true" ipcore_useipmodelcache "true" ipcore_verbose "false" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "dds_compiler_v4_0" sg_icon_stat "85,109,4,3,white,blue,0,37cfbb6d,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 85 85 0 0 ],[0 0 109 109 0 ],[0.77" " 0.82 0.91 ]);\nplot([0 85 85 0 0 ],[0 0 109 109 0 ]);\npatch([15.3 32.64 44.64 56.64 68.64 44.64 27.3 15.3 ],[" "67.32 67.32 79.32 67.32 79.32 79.32 79.32 67.32 ],[1 1 1 ]);\npatch([27.3 44.64 32.64 15.3 27.3 ],[55.32 55.32 " "67.32 67.32 55.32 ],[0.931 0.946 0.973 ]);\npatch([15.3 32.64 44.64 27.3 15.3 ],[43.32 43.32 55.32 55.32 43.32 " "],[1 1 1 ]);\npatch([27.3 68.64 56.64 44.64 32.64 15.3 27.3 ],[31.32 31.32 43.32 31.32 43.32 43.32 31.32 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'we');\ncolor('black');port_label('input',2,'data');\ncolor('black');port_label('i" "nput',3,'rst');\ncolor('black');port_label('input',4,'en');\ncolor('black');port_label('output',1,'rdy');\ncolo" "r('black');port_label('output',2,'sine');\ncolor('black');port_label('output',3,'cosine');\nfprintf('','COMMENT" ": end icon text');" } Block { BlockType Reference Name "Gateway Out1" SID "31" Ports [1, 1] Position [935, 139, 970, 151] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "I In" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out17" SID "32" Ports [1, 1] Position [935, 124, 970, 136] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "DDS En" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "33" Ports [1, 1] Position [935, 154, 970, 166] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "IQ Valid In" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "34" Ports [1, 1] Position [935, 169, 970, 181] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "DDS Q" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "35" Ports [1, 1] Position [935, 184, 970, 196] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "tlast In" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "36" Ports [1, 1] Position [935, 199, 970, 211] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Mult tvalid out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "37" Ports [1, 1] Position [935, 214, 970, 226] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Mult Q" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "38" Ports [1, 1] Position [935, 229, 970, 241] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Mult tlast" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "14923" Ports [1, 1] Position [935, 244, 970, 256] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "DDS Reset" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType SubSystem Name "Reset-En Logic" SID "14924" Ports [2, 2] Position [225, 440, 315, 500] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Reset-En Logic" Location [-890, 709, -213, 1055] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "125" Block { BlockType Inport Name "Reset" SID "14925" Position [265, 43, 295, 57] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "DDS Run" SID "14927" Position [265, 218, 295, 232] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Delay" SID "14936" Ports [1, 1] Position [600, 190, 635, 220] BlockMirror on NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "8" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,30,1,1,white,blue,0,e47f993a,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 30 30 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[19.44 19.44 23.4" "4 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[15.44 15.44 19.44 19.44 15.44 ]," "[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([12.1" " 25.88 21.88 17.88 13.88 8.1 12.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-8}','texmode'," "'on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From2" SID "14929" Position [105, 71, 235, 89] ShowName off CloseFcn "tagdialog Close" GotoTag "RX_GLOBAL_RESET" TagVisibility "global" } Block { BlockType Reference Name "Logical1" SID "14921" Ports [3, 1] Position [365, 36, 405, 124] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,88,3,1,white,blue,0,a2abe52d,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 88 88 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 88 88 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[49.55 49.55 54." "55 49.55 54.55 54.55 54.55 49.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[44.55 44.55 49.55 49.55 44." "55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[39.55 39.55 44.55 44.55 39.55 ],[1 1 1 ]);\npa" "tch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[34.55 34.55 39.55 34.55 39.55 39.55 34.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\ncolor('black');disp(" "'or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "39" Ports [2, 1] Position [695, 155, 735, 250] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,95,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 95 95 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 95 95 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[52.55 52.55 57." "55 52.55 57.55 57.55 57.55 52.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[47.55 47.55 52.55 52.55 47." "55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[42.55 42.55 47.55 47.55 42.55 ],[1 1 1 ]);\npa" "tch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[37.55 37.55 42.55 37.55 42.55 42.55 37.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('o" "r');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "S-R Latch1" SID "14938" Ports [2, 1] Position [600, 133, 635, 162] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "S-R Latch1" Location [351, 366, 2001, 1172] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "14939" Position [140, 103, 170, 117] IconDisplay "Port number" } Block { BlockType Inport Name "R" SID "14940" Position [140, 88, 170, 102] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "14941" Ports [0, 1] Position [195, 71, 210, 89] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "15,18,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11.22 " "13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 9.22 " "],[0.931 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([4.55 " "11.44 9.44 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "14942" Ports [1, 1] Position [210, 86, 235, 104] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('outpu" "t',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "14943" Ports [1, 1] Position [210, 101, 235, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('outpu" "t',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "14944" Ports [3, 1] Position [255, 71, 300, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "14945" Position [325, 88, 355, 102] IconDisplay "Port number" } Line { SrcBlock "S" SrcPort 1 DstBlock "Convert2" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "Convert2" SrcPort 1 DstBlock "Register2" DstPort 3 } } } Block { BlockType SubSystem Name "Sim Reset" SID "40" Ports [0, 1] Position [190, 95, 235, 125] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Sim Reset" Location [177, 931, 726, 1168] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Reference Name "Constant4" SID "41" Ports [0, 1] Position [320, 169, 350, 191] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Boolean" arith_type "Boolean" n_bits "16" bin_pt "14" preci_type "Single" exp_width "8" frac_width "24" explicit_period on period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,22,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 22 22 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[14.3" "3 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[11.33 11.33 " "14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[8.33 8.33 11.33 11.33 8.33 " "],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('blac" "k');port_label('output',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Simulation Multiplexer" SID "42" Ports [2, 1] Position [415, 122, 465, 173] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Simulation Multiplexer" SourceType "Xilinx Simulation Multiplexer Block" infoedit "Distinguish input subsystems as \"simulation only\" and \"generation only\". The input specified" " For Simulation will be used during Simulink simulation. The input specified For Generation will be used during" " code generation. This block will typically be used on the output of a HW Co-Simulation, Black Box, or ModelSim" " subsystem.

Hardware Notes: This block costs nothing." sim_sel "1" hw_sel "2" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "simmux" sg_icon_stat "50,51,2,1,white,blue,0,4170dd71,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 51 51 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 51 51 0 ]);\npatch([9.425 19.54 26.54 33.54 40.54 26.54 16.425 9.425 ],[32.7" "7 32.77 39.77 32.77 39.77 39.77 39.77 32.77 ],[1 1 1 ]);\npatch([16.425 26.54 19.54 9.425 16.425 ],[25.77 25.77 " "32.77 32.77 25.77 ],[0.931 0.946 0.973 ]);\npatch([9.425 19.54 26.54 16.425 9.425 ],[18.77 18.77 25.77 25.77 18." "77 ],[1 1 1 ]);\npatch([16.425 40.54 33.54 26.54 19.54 9.425 16.425 ],[11.77 11.77 18.77 11.77 18.77 18.77 11.77" " ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n" "\n\nfprintf('','COMMENT: end icon text');color('red');\nplot(swLineX,simSwLineY);\ncolor('black');\nplot(swLineX" ",hwSwLineY);\n" } Block { BlockType SubSystem Name "Subsystem" SID "43" Ports [0, 1] Position [210, 85, 250, 145] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Subsystem" Location [386, 369, 716, 654] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Reference Name "Disregard Subsystem" SID "44" Tag "discardX" Ports [] Position [228, 177, 286, 235] ShowName off AttributesFormatString "Disregard Subsystem\\nFor Generation" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Disregard Subsystem" SourceType "Xilinx Disregard Subsystem For Generation Block" infoedit "Place this block into a subsystem to have System Generator ignore the subsystem during code gener" "ation. This block can be used in combination with the Simulation Multiplexer block to provide an alternative sim" "ulation model for another subsystem (e.g., to provide a simulation model for a black box)." has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "disregard" sg_icon_stat "58,58,-1,-1,darkgray,black,0,07734,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 58 58 0 0 ],[0 0 58 58 0 ],[0.1 0.1 0" ".1 ]);\nplot([0 58 58 0 0 ],[0 0 58 58 0 ]);\npatch([11.2 22.76 30.76 38.76 46.76 30.76 19.2 11.2 ],[37.88 37.88" " 45.88 37.88 45.88 45.88 45.88 37.88 ],[0.33 0.33 0.33 ]);\npatch([19.2 30.76 22.76 11.2 19.2 ],[29.88 29.88 37." "88 37.88 29.88 ],[0.261 0.261 0.261 ]);\npatch([11.2 22.76 30.76 19.2 11.2 ],[21.88 21.88 29.88 29.88 21.88 ],[0" ".33 0.33 0.33 ]);\npatch([19.2 46.76 38.76 30.76 22.76 11.2 19.2 ],[13.88 13.88 21.88 13.88 21.88 21.88 13.88 ]," "[0.261 0.261 0.261 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nfpri" "ntf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway In" SID "45" Ports [1, 1] Position [105, 40, 170, 60] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to X" "ilinx fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top level" " input ports." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "16" bin_pt "14" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0.93" " 0.65 ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12.22" " 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 12." "22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1" " 1 1 ]);\npatch([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 " "0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');po" "rt_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfpri" "ntf('','COMMENT: end icon text');" } Block { BlockType DiscretePulseGenerator Name "Pulse\nGenerator" SID "46" Ports [0, 1] Position [25, 29, 55, 61] ZOrder -13 Period "1e9" PulseWidth "16" PhaseDelay "1" } Block { BlockType Outport Name "Out1" SID "47" Position [195, 43, 225, 57] IconDisplay "Port number" } Line { SrcBlock "Pulse\nGenerator" SrcPort 1 Points [15, 0; 0, 5] DstBlock "Gateway In" DstPort 1 } Line { SrcBlock "Gateway In" SrcPort 1 DstBlock "Out1" DstPort 1 } } } Block { BlockType Outport Name "Out1" SID "48" Position [490, 143, 520, 157] IconDisplay "Port number" } Line { SrcBlock "Subsystem" SrcPort 1 Points [0, 20] DstBlock "Simulation Multiplexer" DstPort 1 } Line { SrcBlock "Constant4" SrcPort 1 Points [20, 0; 0, -20] DstBlock "Simulation Multiplexer" DstPort 2 } Line { SrcBlock "Simulation Multiplexer" SrcPort 1 DstBlock "Out1" DstPort 1 } } } Block { BlockType SubSystem Name "negedge" SID "14930" Ports [1, 1] Position [465, 128, 520, 152] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "negedge" Location [88, 301, 2330, 1301] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "14931" Position [275, 178, 305, 192] IconDisplay "Port number" } Block { BlockType Reference Name "Delay" SID "14932" Ports [1, 1] Position [425, 153, 460, 177] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. " "If register retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[15" ".33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.33 12." "33 15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 12.33 " "9.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\nc" "olor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "14933" Ports [1, 1] Position [490, 181, 515, 199] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "14934" Ports [2, 1] Position [540, 151, 585, 204] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,53,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 53 53 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 53 53 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[32.66 3" "2.66 38.66 32.66 38.66 38.66 38.66 32.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[26.66 26.66 32.66 " "32.66 26.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[20.66 20.66 26.66 26.66 20.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[14.66 14.66 20.66 14.66 20.66 20.66 14.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('" "black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "14935" Position [610, 173, 640, 187] IconDisplay "Port number" } Line { SrcBlock "D" SrcPort 1 Points [75, 0; 0, 5] Branch { Points [0, -25] DstBlock "Delay" DstPort 1 } Branch { DstBlock "Inverter" DstPort 1 } } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "Delay" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical1" DstPort 2 } } } Block { BlockType Outport Name "Rst" SID "14926" Position [755, 73, 785, 87] IconDisplay "Port number" } Block { BlockType Outport Name "En" SID "14928" Position [755, 198, 785, 212] Port "2" IconDisplay "Port number" } Line { SrcBlock "DDS Run" SrcPort 1 DstBlock "Logical2" DstPort 2 } Line { SrcBlock "Reset" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Logical1" SrcPort 1 Points [30, 0] Branch { DstBlock "Rst" DstPort 1 } Branch { Points [0, 60] DstBlock "negedge" DstPort 1 } } Line { SrcBlock "Logical2" SrcPort 1 DstBlock "En" DstPort 1 } Line { SrcBlock "From2" SrcPort 1 DstBlock "Logical1" DstPort 2 } Line { SrcBlock "Sim Reset" SrcPort 1 DstBlock "Logical1" DstPort 3 } Line { SrcBlock "negedge" SrcPort 1 DstBlock "S-R Latch1" DstPort 1 } Line { SrcBlock "Delay" SrcPort 1 Points [-20, 0; 0, -50] DstBlock "S-R Latch1" DstPort 2 } Line { SrcBlock "S-R Latch1" SrcPort 1 Points [20, 0; 0, 30] Branch { DstBlock "Logical2" DstPort 1 } Branch { Points [0, 25] DstBlock "Delay" DstPort 1 } } Annotation { Name "DDS requires >4(?) cycle EN early to get setup after\nconfig and after every reset event.\nOtherwise its" " outputs are invalid for a few cycles,\nleading to invalid FFT outputs. It is not clear what\nhappens in hardware," " but in sim this post-rst invalid\nstate breaks Rx entirely." Position [442, 381] } } } Block { BlockType Outport Name "valid" SID "49" Position [1015, 308, 1045, 322] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Outport Name "I" SID "50" Position [1015, 358, 1045, 372] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "Q" SID "51" Position [1015, 333, 1045, 347] NamePlacement "alternate" Port "3" IconDisplay "Port number" } Block { BlockType Outport Name " tlast" SID "52" Position [1015, 383, 1045, 397] Port "4" IconDisplay "Port number" } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "DDS Compiler 4.0" DstPort 1 } Line { SrcBlock "CFO Est" SrcPort 1 DstBlock "Convert3" DstPort 1 } Line { SrcBlock "Complex Multiplier 5.0 " SrcPort 2 Points [20, 0] Branch { DstBlock "Convert2" DstPort 1 } Branch { Points [0, -120] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "Complex Multiplier 5.0 " SrcPort 3 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "I " SrcPort 1 Points [205, 0] Branch { Points [125, 0; 0, 80] DstBlock "Complex Multiplier 5.0 " DstPort 3 } Branch { Points [0, -110] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "Q " SrcPort 1 Points [335, 0; 0, 85] DstBlock "Complex Multiplier 5.0 " DstPort 2 } Line { Name "DDS En" Labels [0, 0] SrcBlock "Gateway Out17" SrcPort 1 DstBlock "CFO Corr" DstPort 1 } Line { Name "I In" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 DstBlock "CFO Corr" DstPort 2 } Line { Name "IQ Valid In" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 DstBlock "CFO Corr" DstPort 3 } Line { Name "DDS Q" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 DstBlock "CFO Corr" DstPort 4 } Line { Name "tlast In" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 DstBlock "CFO Corr" DstPort 5 } Line { SrcBlock "DDS Compiler 4.0" SrcPort 2 Points [0, -5; 20, 0] Branch { Points [120, 0; 0, -15] DstBlock "Complex Multiplier 5.0 " DstPort 6 } Branch { Points [0, -220] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "Valid" SrcPort 1 Points [220, 0] Branch { Points [130, 0; 0, 25] DstBlock "Complex Multiplier 5.0 " DstPort 1 } Branch { Points [0, -120] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "I" DstPort 1 } Line { SrcBlock "Convert2" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "Complex Multiplier 5.0 " SrcPort 1 Points [15, 0] Branch { DstBlock "valid" DstPort 1 } Branch { Points [0, -110] DstBlock "Gateway Out5" DstPort 1 } } Line { SrcBlock "DDS Compiler 4.0" SrcPort 3 Points [160, 0] DstBlock "Complex Multiplier 5.0 " DstPort 7 } Line { SrcBlock "Reset-En Logic" SrcPort 2 Points [50, 0; 0, -50] Branch { Points [0, -305] DstBlock "Gateway Out17" DstPort 1 } Branch { DstBlock "DDS Compiler 4.0" DstPort 4 } } Line { SrcBlock "Convert3" SrcPort 1 Points [90, 0] DstBlock "DDS Compiler 4.0" DstPort 2 } Line { SrcBlock "Constant5" SrcPort 1 DstBlock "Complex Multiplier 5.0 " DstPort 5 } Line { SrcBlock "tlast" SrcPort 1 DstBlock "Convert4" DstPort 1 } Line { SrcBlock "Complex Multiplier 5.0 " SrcPort 4 Points [25, 0] Branch { Points [0, -155] DstBlock "Gateway Out7" DstPort 1 } Branch { DstBlock "Convert5" DstPort 1 } } Line { Name "Mult tvalid out" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 DstBlock "CFO Corr" DstPort 6 } Line { Name "Mult Q" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 DstBlock "CFO Corr" DstPort 7 } Line { Name "Mult tlast" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 DstBlock "CFO Corr" DstPort 8 } Line { SrcBlock "Convert4" SrcPort 1 Points [205, 0] Branch { Points [55, 0; 0, 30] DstBlock "Complex Multiplier 5.0 " DstPort 4 } Branch { Points [0, -130] DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "Convert5" SrcPort 1 DstBlock " tlast" DstPort 1 } Line { SrcBlock "Reset-En Logic" SrcPort 1 Points [40, 0; 0, -45] Branch { DstBlock "DDS Compiler 4.0" DstPort 3 } Branch { Points [0, -160] DstBlock "Gateway Out8" DstPort 1 } } Line { Name "DDS Reset" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 DstBlock "CFO Corr" DstPort 9 } Line { SrcBlock "Reset" SrcPort 1 Points [10, 0; 0, 20] DstBlock "Reset-En Logic" DstPort 1 } Line { SrcBlock "DDS Run" SrcPort 1 Points [10, 0; 0, -25] DstBlock "Reset-En Logic" DstPort 2 } Annotation { Name "\n\nDDS updates once per input sample\nSince the FFT only consumes 64 samples\nper OFDM symbol (ig" "noring the CP),\nthe DDS keeps running after each FFT \nframe is loaded. This is fine, since the FFT is\nconfig" "ured for non-streaming (it ignores its\nI/Q inputs while computing a transform)" Position [452, 594] } } } Block { BlockType SubSystem Name "CFO Estimation" SID "53" Ports [5, 1] Position [700, 502, 775, 578] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "CFO Estimation" Location [442, 320, 2429, 1372] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "112" Block { BlockType Inport Name "LTS_Sync" SID "54" Position [140, 533, 170, 547] IconDisplay "Port number" } Block { BlockType Inport Name "rx_I" SID "55" Position [140, 223, 170, 237] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "rx_Q" SID "56" Position [140, 253, 170, 267] NamePlacement "alternate" Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "rx_valid" SID "57" Position [140, 193, 170, 207] NamePlacement "alternate" Port "4" IconDisplay "Port number" } Block { BlockType Inport Name "Reset" SID "14918" Position [140, 603, 170, 617] Port "5" IconDisplay "Port number" } Block { BlockType Scope Name "CFO Est" SID "58" Ports [10] Position [1370, 45, 1405, 255] ZOrder -3 Floating off Location [6, 40, 1841, 1194] Open off NumInputPorts "10" ZoomMode "yonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" axes9 "%" axes10 "%" } List { ListType ScopeGraphics FigureColor "[0.5 0.5 0.5]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "10000" YMin "-1~-1~-0.25~-1~-10~-2.5~-1~0~0~-1" YMax "1~1~2~2~50~15~1~1~0.001~1" SaveName "ScopeData1" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType SubSystem Name "Conj Mult" SID "59" Ports [5, 3] Position [480, 180, 540, 340] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Conj Mult" Location [227, 108, 1983, 1242] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Valid" SID "60" Position [150, 293, 180, 307] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "A I" SID "61" Position [150, 333, 180, 347] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "A Q" SID "62" Position [150, 418, 180, 432] NamePlacement "alternate" Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "B I" SID "63" Position [150, 363, 180, 377] NamePlacement "alternate" Port "4" IconDisplay "Port number" } Block { BlockType Inport Name "B Q" SID "64" Position [150, 448, 180, 462] NamePlacement "alternate" Port "5" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub" SID "65" Ports [2, 1] Position [490, 351, 520, 409] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "1" precision "User Defined" arith_type "Signed (2's comp)" n_bits "17" bin_pt "14" quantization "Truncate" overflow "Flag as error" dbl_ovrd off use_behavioral_HDL off hw_selection "Fabric" pipelined off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" sg_icon_stat "30,58,2,1,white,blue,0,e85d8a90,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 58 58 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 58 58 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[33.44 33.44 37.4" "4 33.44 37.44 37.44 37.44 33.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[29.44 29.44 33.44 33.44 29.44 ]," "[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[25.44 25.44 29.44 29.44 25.44 ],[1 1 1 ]);\npatch([10.1" " 23.88 19.88 15.88 11.88 6.1 10.1 ],[21.44 21.44 25.44 21.44 25.44 25.44 21.44 ],[0.931 0.946 0.973 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'a'" ");\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bf{a + b}','texmode','on');" "\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\newline\\bf{}','texmode','on');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub1" SID "66" Ports [2, 1] Position [490, 546, 520, 604] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Subtraction" use_carryin off use_carryout off en off latency "1" precision "User Defined" arith_type "Signed (2's comp)" n_bits "17" bin_pt "14" quantization "Truncate" overflow "Flag as error" dbl_ovrd off use_behavioral_HDL off hw_selection "Fabric" pipelined off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" sg_icon_stat "30,58,2,1,white,blue,0,8a00a986,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 58 58 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 58 58 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[33.44 33.44 37.4" "4 33.44 37.44 37.44 37.44 33.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[29.44 29.44 33.44 33.44 29.44 ]," "[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[25.44 25.44 29.44 29.44 25.44 ],[1 1 1 ]);\npatch([10.1" " 23.88 19.88 15.88 11.88 6.1 10.1 ],[21.44 21.44 25.44 21.44 25.44 25.44 21.44 ],[0.931 0.946 0.973 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'a'" ");\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bf{a - b}','texmode','on');" "\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\newline\\bf{}','texmode','on');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay" SID "67" Ports [1, 1] Position [430, 286, 465, 314] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "5" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,28,1,1,white,blue,0,ec356abf,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 28 28 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 28 28 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[18.44 18.44 22.4" "4 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[14.44 14.44 18.44 18.44 14.44 ]," "[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\npatch([12.1" " 25.88 21.88 17.88 13.88 8.1 12.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-5}','texmode'," "'on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mult" SID "68" Ports [2, 1] Position [360, 334, 395, 396] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mult" SourceType "Xilinx Multiplier Block" infoedit "Hardware notes: To check for the optimum internal pipeline stages of the dedicated multiplier you mus" "t select 'Test for optimum pipelining'.

Optimization Goal: For implementation into device fabric (LUTs), th" "e Speed or Area optimization will take effect only if it's supported by IP for the particular device family. Other" "wise, the results will be identical regardless of the selection." precision "User Defined" arith_type "Signed (2's comp)" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Flag as error" en off latency "3" dbl_ovrd off use_behavioral_HDL off opt "Speed" use_embedded on optimum_pipeline on xl_use_area off xl_area "[0,0,0,0,0,0,0]" pipeline "on" use_rpm "on" placement_style "Triangular" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mult" sg_icon_stat "35,62,2,1,white,blue,0,7028354c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 62 62 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 62 62 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[36.55 36.55 41." "55 36.55 41.55 41.55 41.55 36.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[31.55 31.55 36.55 36.55 31." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[26.55 26.55 31.55 31.55 26.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[21.55 21.55 26.55 21.55 26.55 26.55 21.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i" "nput',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa \\times b','" "texmode','on');\ncolor('black');disp('z^{-3}\\newline ','texmode','on');\ncolor('black');disp(' \\n ');\nfprintf('" "','COMMENT: end icon text');" } Block { BlockType Reference Name "Mult1" SID "14844" Ports [2, 1] Position [360, 419, 395, 481] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mult" SourceType "Xilinx Multiplier Block" infoedit "Hardware notes: To check for the optimum internal pipeline stages of the dedicated multiplier you mus" "t select 'Test for optimum pipelining'.

Optimization Goal: For implementation into device fabric (LUTs), th" "e Speed or Area optimization will take effect only if it's supported by IP for the particular device family. Other" "wise, the results will be identical regardless of the selection." precision "User Defined" arith_type "Signed (2's comp)" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Flag as error" en off latency "3" dbl_ovrd off use_behavioral_HDL off opt "Speed" use_embedded on optimum_pipeline on xl_use_area off xl_area "[0,0,0,0,0,0,0]" pipeline "on" use_rpm "on" placement_style "Triangular" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mult" sg_icon_stat "35,62,2,1,white,blue,0,7028354c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 62 62 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 62 62 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[36.55 36.55 41." "55 36.55 41.55 41.55 41.55 36.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[31.55 31.55 36.55 36.55 31." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[26.55 26.55 31.55 31.55 26.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[21.55 21.55 26.55 21.55 26.55 26.55 21.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i" "nput',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa \\times b','" "texmode','on');\ncolor('black');disp('z^{-3}\\newline ','texmode','on');\ncolor('black');disp(' \\n ');\nfprintf('" "','COMMENT: end icon text');" } Block { BlockType Reference Name "Mult2" SID "14845" Ports [2, 1] Position [360, 529, 395, 591] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mult" SourceType "Xilinx Multiplier Block" infoedit "Hardware notes: To check for the optimum internal pipeline stages of the dedicated multiplier you mus" "t select 'Test for optimum pipelining'.

Optimization Goal: For implementation into device fabric (LUTs), th" "e Speed or Area optimization will take effect only if it's supported by IP for the particular device family. Other" "wise, the results will be identical regardless of the selection." precision "User Defined" arith_type "Signed (2's comp)" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Flag as error" en off latency "3" dbl_ovrd off use_behavioral_HDL off opt "Speed" use_embedded on optimum_pipeline on xl_use_area off xl_area "[0,0,0,0,0,0,0]" pipeline "on" use_rpm "on" placement_style "Triangular" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mult" sg_icon_stat "35,62,2,1,white,blue,0,7028354c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 62 62 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 62 62 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[36.55 36.55 41." "55 36.55 41.55 41.55 41.55 36.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[31.55 31.55 36.55 36.55 31." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[26.55 26.55 31.55 31.55 26.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[21.55 21.55 26.55 21.55 26.55 26.55 21.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i" "nput',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa \\times b','" "texmode','on');\ncolor('black');disp('z^{-3}\\newline ','texmode','on');\ncolor('black');disp(' \\n ');\nfprintf('" "','COMMENT: end icon text');" } Block { BlockType Reference Name "Mult3" SID "14846" Ports [2, 1] Position [360, 599, 395, 661] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mult" SourceType "Xilinx Multiplier Block" infoedit "Hardware notes: To check for the optimum internal pipeline stages of the dedicated multiplier you mus" "t select 'Test for optimum pipelining'.

Optimization Goal: For implementation into device fabric (LUTs), th" "e Speed or Area optimization will take effect only if it's supported by IP for the particular device family. Other" "wise, the results will be identical regardless of the selection." precision "User Defined" arith_type "Signed (2's comp)" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Flag as error" en off latency "3" dbl_ovrd off use_behavioral_HDL off opt "Speed" use_embedded on optimum_pipeline on xl_use_area off xl_area "[0,0,0,0,0,0,0]" pipeline "on" use_rpm "on" placement_style "Triangular" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mult" sg_icon_stat "35,62,2,1,white,blue,0,7028354c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 62 62 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 62 62 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[36.55 36.55 41." "55 36.55 41.55 41.55 41.55 36.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[31.55 31.55 36.55 36.55 31." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[26.55 26.55 31.55 31.55 26.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[21.55 21.55 26.55 21.55 26.55 26.55 21.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i" "nput',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa \\times b','" "texmode','on');\ncolor('black');disp('z^{-3}\\newline ','texmode','on');\ncolor('black');disp(' \\n ');\nfprintf('" "','COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "72" Ports [2, 1] Position [230, 333, 260, 362] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,29,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 29 29 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 29 29 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 18.44 22.4" "4 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 18.44 14.44 ]," "[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\npatch([10.1" " 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\n" "color('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1" "}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "73" Ports [2, 1] Position [230, 363, 260, 392] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,29,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 29 29 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 29 29 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 18.44 22.4" "4 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 18.44 14.44 ]," "[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\npatch([10.1" " 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\n" "color('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1" "}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register3" SID "74" Ports [2, 1] Position [230, 418, 260, 447] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,29,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 29 29 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 29 29 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 18.44 22.4" "4 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 18.44 14.44 ]," "[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\npatch([10.1" " 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\n" "color('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1" "}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register4" SID "75" Ports [2, 1] Position [230, 448, 260, 477] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,29,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 29 29 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 29 29 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 18.44 22.4" "4 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 18.44 14.44 ]," "[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\npatch([10.1" " 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\n" "color('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1" "}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name " Valid" SID "76" Position [815, 293, 845, 307] IconDisplay "Port number" } Block { BlockType Outport Name " I" SID "77" Position [630, 373, 660, 387] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name " Q" SID "78" Position [630, 568, 660, 582] Port "3" IconDisplay "Port number" } Line { SrcBlock "B Q" SrcPort 1 DstBlock "Register4" DstPort 1 } Line { SrcBlock "Valid" SrcPort 1 Points [15, 0] Branch { DstBlock "Delay" DstPort 1 } Branch { Points [0, 55] Branch { DstBlock "Register1" DstPort 2 } Branch { Points [0, 30] Branch { DstBlock "Register2" DstPort 2 } Branch { Points [0, 55] Branch { DstBlock "Register3" DstPort 2 } Branch { Points [0, 30] DstBlock "Register4" DstPort 2 } } } } } Line { SrcBlock "A I" SrcPort 1 DstBlock "Register1" DstPort 1 } Line { SrcBlock "B I" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "Mult" SrcPort 1 DstBlock "AddSub" DstPort 1 } Line { SrcBlock "Mult1" SrcPort 1 Points [15, 0; 0, -55] DstBlock "AddSub" DstPort 2 } Line { SrcBlock "AddSub" SrcPort 1 DstBlock " I" DstPort 1 } Line { SrcBlock "Delay" SrcPort 1 DstBlock " Valid" DstPort 1 } Line { SrcBlock "AddSub1" SrcPort 1 DstBlock " Q" DstPort 1 } Line { SrcBlock "Register1" SrcPort 1 Points [65, 0] Branch { DstBlock "Mult" DstPort 1 } Branch { Points [0, 195] DstBlock "Mult2" DstPort 1 } } Line { SrcBlock "Register2" SrcPort 1 Points [50, 0] Branch { DstBlock "Mult" DstPort 2 } Branch { Points [0, 235] DstBlock "Mult3" DstPort 1 } } Line { SrcBlock "Register3" SrcPort 1 Points [40, 0] Branch { DstBlock "Mult1" DstPort 1 } Branch { Points [0, 210] DstBlock "Mult3" DstPort 2 } } Line { SrcBlock "Register4" SrcPort 1 Points [60, 0] Branch { DstBlock "Mult1" DstPort 2 } Branch { Points [0, 110] DstBlock "Mult2" DstPort 2 } } Line { SrcBlock "A Q" SrcPort 1 DstBlock "Register3" DstPort 1 } Line { SrcBlock "Mult2" SrcPort 1 DstBlock "AddSub1" DstPort 1 } Line { SrcBlock "Mult3" SrcPort 1 Points [35, 0; 0, -40] DstBlock "AddSub1" DstPort 2 } } } Block { BlockType Reference Name "Constant" SID "9539" Ports [0, 1] Position [1335, 627, 1390, 653] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "-1e-4" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "21" bin_pt "20" preci_type "Single" exp_width "8" frac_width "24" explicit_period on period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "55,26,0,1,white,blue,0,cd5eb3c2,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\npatch([20.325 24.66 27.66 30.66 33.66 27.66 23.325 20.325 ]" ",[16.33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([23.325 27.66 24.66 20.325 23.325 ],[13.3" "3 13.33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([20.325 24.66 27.66 23.325 20.325 ],[10.33 10.33 13.3" "3 13.33 10.33 ],[1 1 1 ]);\npatch([23.325 33.66 30.66 27.66 24.66 20.325 23.325 ],[7.33 7.33 10.33 7.33 10.33 1" "0.33 7.33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon " "text');\ncolor('black');port_label('output',1,'-0.00010013580322265625');\nfprintf('','COMMENT: end icon text')" ";" } Block { BlockType Reference Name "Convert1" SID "15035" Ports [1, 1] Position [1250, 441, 1285, 459] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do" " not." gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "21" bin_pt "13" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Flag as error" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "35,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 18 18 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[1" "1.22 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[9.22 9.22 " "11.22 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[7.22 7.22 9.22 9.22 7.22 ],[" "1 1 1 ]);\npatch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black" "');port_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "79" Ports [1, 1] Position [1250, 546, 1285, 564] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do" " not." gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "21" bin_pt "13" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Flag as error" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "35,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 18 18 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[1" "1.22 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[9.22 9.22 " "11.22 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[7.22 7.22 9.22 9.22 7.22 ],[" "1 1 1 ]);\npatch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black" "');port_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay" SID "14843" Ports [2, 1] Position [745, 541, 785, 579] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en on latency "2" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "40,38,2,1,white,blue,0,3e0a7e79,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 38 38 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 38 38 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[24.55" " 24.55 29.55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[19.55 19.55 24" ".55 24.55 19.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[14.55 14.55 19.55 19.55 14.55 " "],[1 1 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('b" "lack');port_label('input',2,'en');\n\ncolor('black');disp('z^{-2}','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "Delay1" SID "81" Ports [2, 1] Position [395, 310, 430, 330] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en on latency "64" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[7 14 0 14 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,20,2,1,white,blue,0,bf433b8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 20 20 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 20 20 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[1" "2.22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[10.22 10.2" "2 12.22 12.22 10.22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[8.22 8.22 10.22 10.22 8.2" "2 ],[1 1 1 ]);\npatch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931" " 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('" "black');port_label('input',2,'en');\n\ncolor('black');disp('z^{-64}','texmode','on');\nfprintf('','COMMENT: end" " icon text');" } Block { BlockType Reference Name "Delay2" SID "82" Ports [2, 1] Position [395, 280, 430, 300] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en on latency "64" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[7 14 0 14 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,20,2,1,white,blue,0,bf433b8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 20 20 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 20 20 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[1" "2.22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[10.22 10.2" "2 12.22 12.22 10.22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[8.22 8.22 10.22 10.22 8.2" "2 ],[1 1 1 ]);\npatch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931" " 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('" "black');port_label('input',2,'en');\n\ncolor('black');disp('z^{-64}','texmode','on');\nfprintf('','COMMENT: end" " icon text');" } Block { BlockType From Name "From2" SID "84" Position [880, 616, 1010, 634] ShowName off CloseFcn "tagdialog Close" GotoTag "regRx_BYPASS_CFO_EST" TagVisibility "global" } Block { BlockType Reference Name "Gateway Out" SID "85" Ports [1, 1] Position [1195, 55, 1225, 65] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 10 10 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ]" ",[6.11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[5.11 5.11 6." "11 6.11 5.11 ],[0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1" " 1 1 ]);\npatch([13.775 17.22 16.22 15.22 14.22 12.775 13.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "ADC I" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out1" SID "86" Ports [1, 1] Position [1195, 75, 1225, 85] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 10 10 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ]" ",[6.11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[5.11 5.11 6." "11 6.11 5.11 ],[0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1" " 1 1 ]);\npatch([13.775 17.22 16.22 15.22 14.22 12.775 13.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "ADC Q" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "87" Ports [1, 1] Position [1195, 95, 1225, 105] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 10 10 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ]" ",[6.11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[5.11 5.11 6." "11 6.11 5.11 ],[0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1" " 1 1 ]);\npatch([13.775 17.22 16.22 15.22 14.22 12.775 13.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Conj Prod I" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "88" Ports [1, 1] Position [1195, 115, 1225, 125] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 10 10 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ]" ",[6.11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[5.11 5.11 6." "11 6.11 5.11 ],[0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1" " 1 1 ]);\npatch([13.775 17.22 16.22 15.22 14.22 12.775 13.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Conj Prod Q" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "89" Ports [1, 1] Position [1195, 135, 1225, 145] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 10 10 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ]" ",[6.11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[5.11 5.11 6." "11 6.11 5.11 ],[0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1" " 1 1 ]);\npatch([13.775 17.22 16.22 15.22 14.22 12.775 13.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Sum I" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "90" Ports [1, 1] Position [1195, 155, 1225, 165] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 10 10 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ]" ",[6.11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[5.11 5.11 6." "11 6.11 5.11 ],[0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1" " 1 1 ]);\npatch([13.775 17.22 16.22 15.22 14.22 12.775 13.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Sum Q" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "91" Ports [1, 1] Position [1195, 175, 1225, 185] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 10 10 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ]" ",[6.11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[5.11 5.11 6." "11 6.11 5.11 ],[0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1" " 1 1 ]);\npatch([13.775 17.22 16.22 15.22 14.22 12.775 13.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Phase(Sum)" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "92" Ports [1, 1] Position [1195, 195, 1225, 205] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 10 10 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ]" ",[6.11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[5.11 5.11 6." "11 6.11 5.11 ],[0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1" " 1 1 ]);\npatch([13.775 17.22 16.22 15.22 14.22 12.775 13.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "LTS Sync" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "93" Ports [1, 1] Position [1195, 215, 1225, 225] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 10 10 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ]" ",[6.11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[5.11 5.11 6." "11 6.11 5.11 ],[0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1" " 1 1 ]);\npatch([13.775 17.22 16.22 15.22 14.22 12.775 13.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "CFO Est Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Goto Name "Goto" SID "94" Position [1440, 440, 1575, 460] ZOrder -10 ShowName off GotoTag "regRx_CFO_Estimate" TagVisibility "global" } Block { BlockType Reference Name "Logical" SID "14919" Ports [2, 1] Position [1060, 602, 1090, 633] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "30,31,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 31 31 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 31 31 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 " "19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 1" "9.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');" "disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Phase" SID "95" Ports [3, 2] Position [830, 231, 905, 289] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Phase" Location [1206, 455, 1593, 700] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Valid" SID "96" Position [210, 228, 240, 242] IconDisplay "Port number" } Block { BlockType Inport Name "Re" SID "97" Position [95, 338, 125, 352] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "Im" SID "98" Position [95, 283, 125, 297] Port "3" IconDisplay "Port number" } Block { BlockType Reference Name "CORDIC 5.0 " SID "99" Ports [3, 2] Position [430, 207, 605, 373] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/CORDIC 5.0 " SourceType "Xilinx CORDIC 5.0 Block" infoedit "CORDIC 5.0" functional_selection "Arc_Tan" architectural_configuration "Parallel" pipelining_mode "Optimal" data_format "SignedFraction" phase_format "Scaled_Radians" input_width "18" output_width "18" round_mode "Truncate" iterations "0" precision "0" compensation_scaling "No_Scale_Compensation" coarse_rotation on aclken off aresetn off out_tready off cartesian_has_tuser off cartesian_has_tlast off cartesian_tuser_width "1" phase_has_tuser off phase_has_tlast off phase_tuser_width "1" out_tlast_behv "Null" flow_control "NonBlocking" optimize_goal "Performance" trim_axipin_name on xl_use_area off xl_area "[0,0,0,0,0,0,0]" ip_name "CORDIC" ip_version "5.0" dsptool_ready "true" ipcore_usecache "true" ipcore_useipmodelcache "true" wrapper_available "true" port_translation_map "{ 'aclken' => 'en', 'aresetn' => 'rst' }" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "cordic_v5_0" sg_icon_stat "175,166,3,2,white,blue,0,219bdc80,right,,[2 2 2 ],[3 3 ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 0 3 3 ],[157 9 9 157 ],[5.466667e-001 5.8" "00000e-001 6.400000e-001 ]);\npatch([172 172 175 175 ],[152 9 9 152 ],[3.233333e-001 3.400000e-001 3.700000e-001 ]" ");\npatch([3 171 171 3 3 ],[0 0 166 166 0 ],[7.700000e-001 8.200000e-001 9.100000e-001 ]);\nplot([3 171 171 3 3 ]," "[0 0 166 166 0 ]);\n\n\npatch([35.825 69.06 92.06 115.06 138.06 92.06 58.825 35.825 ],[108.53 108.53 131.53 108.53" " 131.53 131.53 131.53 108.53 ],[1 1 1 ]);\npatch([58.825 92.06 69.06 35.825 58.825 ],[85.53 85.53 108.53 108.53 85" ".53 ],[0.931 0.946 0.973 ]);\npatch([35.825 69.06 92.06 58.825 35.825 ],[62.53 62.53 85.53 85.53 62.53 ],[1 1 1 ])" ";\npatch([58.825 138.06 115.06 92.06 69.06 35.825 58.825 ],[39.53 39.53 62.53 39.53 62.53 62.53 39.53 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');p" "ort_label('input',1,' cartesian_tvalid ');\ncolor('black');port_label('input',2,' cartesian_tdata_imag ');\nco" "lor('black');port_label('input',3,' cartesian_tdata_real ');\ncolor('black');port_label('output',1,' dout_tvali" "d ');\ncolor('black');port_label('output',2,' dout_tdata_phase ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert" SID "100" Ports [1, 1] Position [185, 281, 220, 299] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "18" bin_pt "12" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "35,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 18 18 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[11.22 11.22" " 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[9.22 9.22 11.22 11.22 9" ".22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch" "([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output'" ",1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "101" Ports [1, 1] Position [185, 336, 220, 354] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "18" bin_pt "12" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "35,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 18 18 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[11.22 11.22" " 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[9.22 9.22 11.22 11.22 9" ".22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch" "([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output'" ",1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out" SID "102" Ports [1, 1] Position [670, 505, 700, 515] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 10 10 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ],[6.11 6.1" "1 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[5.11 5.11 6.11 6.11 5.11 " "],[0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]);\npatch(" "[13.775 17.22 16.22 15.22 14.22 12.775 13.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "Gateway Out1" SID "103" Ports [1, 1] Position [670, 525, 700, 535] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 10 10 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ],[6.11 6.1" "1 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[5.11 5.11 6.11 6.11 5.11 " "],[0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]);\npatch(" "[13.775 17.22 16.22 15.22 14.22 12.775 13.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "Gateway Out2" SID "104" Ports [1, 1] Position [670, 545, 700, 555] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 10 10 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ],[6.11 6.1" "1 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[5.11 5.11 6.11 6.11 5.11 " "],[0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]);\npatch(" "[13.775 17.22 16.22 15.22 14.22 12.775 13.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "Gateway Out3" SID "105" Ports [1, 1] Position [670, 565, 700, 575] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 10 10 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ],[6.11 6.1" "1 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[5.11 5.11 6.11 6.11 5.11 " "],[0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]);\npatch(" "[13.775 17.22 16.22 15.22 14.22 12.775 13.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "Gateway Out4" SID "106" Ports [1, 1] Position [670, 585, 700, 595] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 10 10 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ],[6.11 6.1" "1 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[5.11 5.11 6.11 6.11 5.11 " "],[0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]);\npatch(" "[13.775 17.22 16.22 15.22 14.22 12.775 13.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "Gateway Out5" SID "107" Ports [1, 1] Position [670, 605, 700, 615] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 10 10 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ],[6.11 6.1" "1 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[5.11 5.11 6.11 6.11 5.11 " "],[0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]);\npatch(" "[13.775 17.22 16.22 15.22 14.22 12.775 13.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "Gateway Out6" SID "108" Ports [1, 1] Position [670, 625, 700, 635] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 10 10 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ],[6.11 6.1" "1 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[5.11 5.11 6.11 6.11 5.11 " "],[0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]);\npatch(" "[13.775 17.22 16.22 15.22 14.22 12.775 13.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Scope Name "Phase " SID "109" Ports [7] Position [765, 499, 795, 641] ZOrder -3 Floating off Location [97, 316, 1777, 1320] Open off NumInputPorts "7" ZoomMode "yonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" } TimeRange "10000" YMin "-2~-5~-2~-5~-0.4~-1~-1" YMax "4~15~4~15~0.4~2~1" SaveName "ScopeData35" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType Reference Name "Scale" SID "110" Ports [1, 1] Position [305, 278, 340, 302] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Scale" SourceType "Xilinx Input Scaler Block" infoedit "Scales input by a power of two by adjusting the binary point position.

Hardware notes: In hard" "ware this block costs nothing." scale_factor "-4" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,336,191" block_type "scale" block_version "10.1.2" sg_icon_stat "35,24,1,1,white,blue,0,df643265,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[15.33 15" ".33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.33 12.33 15.33" " 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 " "1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');" "disp('\\bf{2^{-4}}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Scale1" SID "111" Ports [1, 1] Position [305, 333, 340, 357] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Scale" SourceType "Xilinx Input Scaler Block" infoedit "Scales input by a power of two by adjusting the binary point position.

Hardware notes: In hard" "ware this block costs nothing." scale_factor "-4" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,336,191" block_type "scale" block_version "10.1.2" sg_icon_stat "35,24,1,1,white,blue,0,df643265,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[15.33 15" ".33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.33 12.33 15.33" " 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 " "1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');" "disp('\\bf{2^{-4}}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name " Valid" SID "112" Position [680, 243, 710, 257] IconDisplay "Port number" } Block { BlockType Outport Name "Phase" SID "113" Position [680, 323, 710, 337] Port "2" IconDisplay "Port number" } Line { SrcBlock "Convert1" SrcPort 1 Points [35, 0] Branch { DstBlock "Scale1" DstPort 1 } Branch { Points [0, 225] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "Valid" SrcPort 1 DstBlock "CORDIC 5.0 " DstPort 1 } Line { SrcBlock "CORDIC 5.0 " SrcPort 1 DstBlock " Valid" DstPort 1 } Line { SrcBlock "CORDIC 5.0 " SrcPort 2 Points [15, 0] Branch { DstBlock "Phase" DstPort 1 } Branch { Points [0, 300] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "Convert" SrcPort 1 Points [45, 0] Branch { DstBlock "Scale" DstPort 1 } Branch { Points [0, 260] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "Scale" SrcPort 1 Points [45, 0] Branch { DstBlock "CORDIC 5.0 " DstPort 2 } Branch { Points [0, 300] DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "Scale1" SrcPort 1 Points [40, 0] Branch { DstBlock "CORDIC 5.0 " DstPort 3 } Branch { Points [0, 265] DstBlock "Gateway Out5" DstPort 1 } } Line { SrcBlock "Im" SrcPort 1 Points [30, 0] Branch { DstBlock "Convert" DstPort 1 } Branch { Points [0, 220] DstBlock "Gateway Out" DstPort 1 } } Line { SrcBlock "Re" SrcPort 1 Points [25, 0] Branch { DstBlock "Convert1" DstPort 1 } Branch { Points [0, 185] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "Gateway Out3" SrcPort 1 DstBlock "Phase " DstPort 4 } Line { SrcBlock "Gateway Out2" SrcPort 1 DstBlock "Phase " DstPort 3 } Line { SrcBlock "Gateway Out1" SrcPort 1 DstBlock "Phase " DstPort 2 } Line { SrcBlock "Gateway Out" SrcPort 1 DstBlock "Phase " DstPort 1 } Line { SrcBlock "Gateway Out4" SrcPort 1 DstBlock "Phase " DstPort 5 } Line { SrcBlock "Gateway Out5" SrcPort 1 DstBlock "Phase " DstPort 6 } Line { SrcBlock "Gateway Out6" SrcPort 1 DstBlock "Phase " DstPort 7 } } } Block { BlockType SubSystem Name "Posedge3" SID "114" Ports [1, 1] Position [865, 548, 920, 572] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Posedge3" Location [88, 301, 2330, 1301] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "115" Position [200, 253, 230, 267] IconDisplay "Port number" } Block { BlockType Reference Name "Delay" SID "116" Ports [1, 1] Position [425, 153, 460, 177] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. If r" "egister retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[15.33 15" ".33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.33 12.33 15.33" " 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 " "1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');" "disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "117" Ports [1, 1] Position [490, 156, 515, 174] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "118" Ports [2, 1] Position [540, 151, 585, 204] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,53,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 53 53 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 53 53 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[32.66 32.66 3" "8.66 32.66 38.66 38.66 38.66 32.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[26.66 26.66 32.66 32.66 26" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[20.66 20.66 26.66 26.66 20.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[14.66 14.66 20.66 14.66 20.66 20.66 14.66 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('" "and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "119" Position [610, 173, 640, 187] IconDisplay "Port number" } Line { SrcBlock "D" SrcPort 1 Points [150, 0; 0, -70] Branch { DstBlock "Logical1" DstPort 2 } Branch { Points [0, -25] DstBlock "Delay" DstPort 1 } } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Delay" SrcPort 1 DstBlock "Inverter" DstPort 1 } Annotation { Name "Rising Edge Detection" Position [500, 112] } } } Block { BlockType Reference Name "Register" SID "120" Ports [3, 1] Position [1145, 516, 1190, 594] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "45,78,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 78 78 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 78 78 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[45." "66 45.66 51.66 45.66 51.66 51.66 51.66 45.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[39.66 39.66 4" "5.66 45.66 39.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[33.66 33.66 39.66 39.66 33.66 " "],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[27.66 27.66 33.66 27.66 33.66 33.66 27.66 ],[0" ".931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor" "('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('i" "nput',3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfpri" "ntf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "14920" Ports [2, 1] Position [1145, 411, 1190, 489] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "45,78,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 78 78 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 78 78 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[45." "66 45.66 51.66 45.66 51.66 51.66 51.66 45.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[39.66 39.66 4" "5.66 45.66 39.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[33.66 33.66 39.66 39.66 33.66 " "],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[27.66 27.66 33.66 27.66 33.66 33.66 27.66 ],[0" ".931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor" "('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('ou" "tput',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Running Sum" SID "121" Ports [2, 2] Position [610, 243, 675, 267] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Running Sum" Location [227, 108, 1983, 1242] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "En" SID "122" Position [195, 183, 225, 197] IconDisplay "Port number" } Block { BlockType Inport Name "D" SID "123" Position [195, 123, 225, 137] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Accum1" SID "124" Ports [2, 1] Position [485, 131, 535, 184] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Accumulator" SourceType "Xilinx Accumulator Block" infoedit "Adder or subtracter-based accumulator. Output type and binary point position match the input.
Hardware notes: When \"Reinitialize with input 'b' on reset\" is selected, the accumulator is forced to run at t" "he system rate even if the input 'b' is running at a slower rate." operation "Add" n_bits "25" overflow "Flag as error" scale "1" rst off infoeditControl "reset for floating point data type must be asserted for a minimum of 2 cycles" hasbypass off en on latency "0" dbl_ovrd off msb_inp "100" msb "100" lsb "-100" use_behavioral_HDL on implementation "Fabric" xl_use_area off xl_area "[12 23 0 22 0 0 0]" has_advanced_control "0" sggui_pos "20,20,367,457" block_type "accum" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,53,2,1,white,blue,0,debef366,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 53 53 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 50 50 0 0 ],[0 0 53 53 0 ]);\npatch([9.425 19.54 26.54 33.54 40.54 26.54 16.425 9.425 ],[33.77 33.7" "7 40.77 33.77 40.77 40.77 40.77 33.77 ],[1 1 1 ]);\npatch([16.425 26.54 19.54 9.425 16.425 ],[26.77 26.77 33.77 33" ".77 26.77 ],[0.931 0.946 0.973 ]);\npatch([9.425 19.54 26.54 16.425 9.425 ],[19.77 19.77 26.77 26.77 19.77 ],[1 1 " "1 ]);\npatch([16.425 40.54 33.54 26.54 19.54 9.425 16.425 ],[12.77 12.77 19.77 12.77 19.77 19.77 12.77 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('input',1,'b');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'\\bf" "+=b','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub1" SID "125" Ports [2, 1] Position [360, 117, 410, 168] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Subtraction" use_carryin off use_carryout off en off latency "1" precision "Full" arith_type "Signed (2's comp)" n_bits "36" bin_pt "28" quantization "Truncate" overflow "Saturate" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[9 18 0 17 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,344" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,51,2,1,white,blue,0,8a00a986,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 51 51 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 50 50 0 0 ],[0 0 51 51 0 ]);\npatch([9.425 19.54 26.54 33.54 40.54 26.54 16.425 9.425 ],[32.77 32.7" "7 39.77 32.77 39.77 39.77 39.77 32.77 ],[1 1 1 ]);\npatch([16.425 26.54 19.54 9.425 16.425 ],[25.77 25.77 32.77 32" ".77 25.77 ],[0.931 0.946 0.973 ]);\npatch([9.425 19.54 26.54 16.425 9.425 ],[18.77 18.77 25.77 25.77 18.77 ],[1 1 " "1 ]);\npatch([16.425 40.54 33.54 26.54 19.54 9.425 16.425 ],[11.77 11.77 18.77 11.77 18.77 18.77 11.77 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bf{" "a - b}','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\newline" "\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay" SID "126" Ports [1, 1] Position [375, 178, 400, 202] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[7 14 0 14 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 24 24 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 24 24 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[15.33 15.33 " "18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[12.33 12.33 15.33 15.33 1" "2.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 1 1 ]);\npat" "ch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 0.973 ]);\nfprin" "tf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay1" SID "127" Ports [1, 1] Position [495, 198, 520, 222] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[7 14 0 14 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 24 24 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 24 24 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[15.33 15.33 " "18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[12.33 12.33 15.33 15.33 1" "2.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 1 1 ]);\npat" "ch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 0.973 ]);\nfprin" "tf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay2" SID "128" Ports [1, 1] Position [605, 198, 630, 222] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[7 14 0 14 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 24 24 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 24 24 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[15.33 15.33 " "18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[12.33 12.33 15.33 15.33 1" "2.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 1 1 ]);\npat" "ch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 0.973 ]);\nfprin" "tf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay6" SID "129" Ports [2, 1] Position [265, 143, 300, 167] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en on latency "64" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[9 17 0 17 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,24,2,1,white,blue,0,bf433b8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[15.33 15" ".33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.33 12.33 15.33" " 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 " "1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');po" "rt_label('input',2,'en');\n\ncolor('black');disp('z^{-64}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register" SID "130" Ports [1, 1] Position [600, 142, 635, 178] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,36,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 36 36 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 36 36 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[23.55 23.55 28." "55 23.55 28.55 28.55 28.55 23.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[18.55 18.55 23.55 23.55 18." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[13.55 13.55 18.55 18.55 13.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[8.55 8.55 13.55 8.55 13.55 13.55 8.55 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input" "',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','" "COMMENT: end icon text');" } Block { BlockType Outport Name "Valid" SID "131" Position [710, 203, 740, 217] IconDisplay "Port number" } Block { BlockType Outport Name "Sum" SID "132" Position [710, 153, 740, 167] Port "2" IconDisplay "Port number" } Line { SrcBlock "Delay6" SrcPort 1 DstBlock "AddSub1" DstPort 2 } Line { SrcBlock "AddSub1" SrcPort 1 DstBlock "Accum1" DstPort 1 } Line { SrcBlock "D" SrcPort 1 Points [0, 0; 15, 0] Branch { DstBlock "AddSub1" DstPort 1 } Branch { Points [0, 20] DstBlock "Delay6" DstPort 1 } } Line { SrcBlock "Accum1" SrcPort 1 DstBlock "Register" DstPort 1 } Line { SrcBlock "Register" SrcPort 1 DstBlock "Sum" DstPort 1 } Line { SrcBlock "En" SrcPort 1 Points [10, 0] Branch { Points [0, -30] DstBlock "Delay6" DstPort 2 } Branch { DstBlock "Delay" DstPort 1 } } Line { SrcBlock "Delay" SrcPort 1 Points [50, 0] Branch { Points [0, -20] DstBlock "Accum1" DstPort 2 } Branch { Points [0, 20] DstBlock "Delay1" DstPort 1 } } Line { SrcBlock "Delay1" SrcPort 1 DstBlock "Delay2" DstPort 1 } Line { SrcBlock "Delay2" SrcPort 1 DstBlock "Valid" DstPort 1 } } } Block { BlockType SubSystem Name "Running Sum1" SID "133" Ports [2, 2] Position [610, 298, 675, 322] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Running Sum1" Location [442, 320, 2429, 1372] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "En" SID "134" Position [195, 183, 225, 197] IconDisplay "Port number" } Block { BlockType Inport Name "D" SID "135" Position [195, 123, 225, 137] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Accum1" SID "136" Ports [2, 1] Position [485, 131, 535, 184] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Accumulator" SourceType "Xilinx Accumulator Block" infoedit "Adder or subtracter-based accumulator. Output type and binary point position match the input.
Hardware notes: When \"Reinitialize with input 'b' on reset\" is selected, the accumulator is forced to run at t" "he system rate even if the input 'b' is running at a slower rate." operation "Add" n_bits "25" overflow "Flag as error" scale "1" rst off infoeditControl "reset for floating point data type must be asserted for a minimum of 2 cycles" hasbypass off en on latency "0" dbl_ovrd off msb_inp "100" msb "100" lsb "-100" use_behavioral_HDL on implementation "Fabric" xl_use_area off xl_area "[12 23 0 22 0 0 0]" has_advanced_control "0" sggui_pos "20,20,367,457" block_type "accum" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,53,2,1,white,blue,0,debef366,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 53 53 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 50 50 0 0 ],[0 0 53 53 0 ]);\npatch([9.425 19.54 26.54 33.54 40.54 26.54 16.425 9.425 ],[33.77 33.7" "7 40.77 33.77 40.77 40.77 40.77 33.77 ],[1 1 1 ]);\npatch([16.425 26.54 19.54 9.425 16.425 ],[26.77 26.77 33.77 33" ".77 26.77 ],[0.931 0.946 0.973 ]);\npatch([9.425 19.54 26.54 16.425 9.425 ],[19.77 19.77 26.77 26.77 19.77 ],[1 1 " "1 ]);\npatch([16.425 40.54 33.54 26.54 19.54 9.425 16.425 ],[12.77 12.77 19.77 12.77 19.77 19.77 12.77 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('input',1,'b');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'\\bf" "+=b','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub1" SID "137" Ports [2, 1] Position [360, 117, 410, 168] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Subtraction" use_carryin off use_carryout off en off latency "1" precision "Full" arith_type "Signed (2's comp)" n_bits "36" bin_pt "28" quantization "Truncate" overflow "Saturate" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[9 18 0 17 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,344" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,51,2,1,white,blue,0,8a00a986,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 51 51 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 50 50 0 0 ],[0 0 51 51 0 ]);\npatch([9.425 19.54 26.54 33.54 40.54 26.54 16.425 9.425 ],[32.77 32.7" "7 39.77 32.77 39.77 39.77 39.77 32.77 ],[1 1 1 ]);\npatch([16.425 26.54 19.54 9.425 16.425 ],[25.77 25.77 32.77 32" ".77 25.77 ],[0.931 0.946 0.973 ]);\npatch([9.425 19.54 26.54 16.425 9.425 ],[18.77 18.77 25.77 25.77 18.77 ],[1 1 " "1 ]);\npatch([16.425 40.54 33.54 26.54 19.54 9.425 16.425 ],[11.77 11.77 18.77 11.77 18.77 18.77 11.77 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bf{" "a - b}','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\newline" "\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay" SID "138" Ports [1, 1] Position [375, 178, 400, 202] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[7 14 0 14 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 24 24 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 24 24 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[15.33 15.33 " "18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[12.33 12.33 15.33 15.33 1" "2.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 1 1 ]);\npat" "ch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 0.973 ]);\nfprin" "tf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay1" SID "139" Ports [1, 1] Position [495, 198, 520, 222] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[7 14 0 14 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 24 24 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 24 24 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[15.33 15.33 " "18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[12.33 12.33 15.33 15.33 1" "2.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 1 1 ]);\npat" "ch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 0.973 ]);\nfprin" "tf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay2" SID "140" Ports [1, 1] Position [605, 198, 630, 222] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[7 14 0 14 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 24 24 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 24 24 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[15.33 15.33 " "18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[12.33 12.33 15.33 15.33 1" "2.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 1 1 ]);\npat" "ch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 0.973 ]);\nfprin" "tf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay6" SID "141" Ports [2, 1] Position [265, 143, 300, 167] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en on latency "64" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[9 17 0 17 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,24,2,1,white,blue,0,bf433b8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[15.33 15" ".33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.33 12.33 15.33" " 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 " "1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');po" "rt_label('input',2,'en');\n\ncolor('black');disp('z^{-64}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register" SID "142" Ports [1, 1] Position [600, 142, 635, 178] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,36,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 36 36 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 36 36 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[23.55 23.55 28." "55 23.55 28.55 28.55 28.55 23.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[18.55 18.55 23.55 23.55 18." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[13.55 13.55 18.55 18.55 13.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[8.55 8.55 13.55 8.55 13.55 13.55 8.55 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input" "',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','" "COMMENT: end icon text');" } Block { BlockType Outport Name "Valid" SID "143" Position [710, 203, 740, 217] IconDisplay "Port number" } Block { BlockType Outport Name "Sum" SID "144" Position [710, 153, 740, 167] Port "2" IconDisplay "Port number" } Line { SrcBlock "Delay2" SrcPort 1 DstBlock "Valid" DstPort 1 } Line { SrcBlock "Delay1" SrcPort 1 DstBlock "Delay2" DstPort 1 } Line { SrcBlock "Delay" SrcPort 1 Points [50, 0] Branch { Points [0, 20] DstBlock "Delay1" DstPort 1 } Branch { Points [0, -20] DstBlock "Accum1" DstPort 2 } } Line { SrcBlock "En" SrcPort 1 Points [10, 0] Branch { DstBlock "Delay" DstPort 1 } Branch { Points [0, -30] DstBlock "Delay6" DstPort 2 } } Line { SrcBlock "Register" SrcPort 1 DstBlock "Sum" DstPort 1 } Line { SrcBlock "Accum1" SrcPort 1 DstBlock "Register" DstPort 1 } Line { SrcBlock "D" SrcPort 1 Points [0, 0; 15, 0] Branch { Points [0, 20] DstBlock "Delay6" DstPort 1 } Branch { DstBlock "AddSub1" DstPort 1 } } Line { SrcBlock "AddSub1" SrcPort 1 DstBlock "Accum1" DstPort 1 } Line { SrcBlock "Delay6" SrcPort 1 DstBlock "AddSub1" DstPort 2 } } } Block { BlockType SubSystem Name "S-R Latch2" SID "14891" Ports [2, 1] Position [640, 533, 675, 562] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "S-R Latch2" Location [351, 366, 2001, 1172] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "14892" Position [140, 103, 170, 117] IconDisplay "Port number" } Block { BlockType Inport Name "R" SID "14893" Position [140, 88, 170, 102] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "14894" Ports [0, 1] Position [195, 71, 210, 89] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "15,18,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11.22 13.22 " "11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 9.22 ],[0.931" " 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([4.55 11.44 9.44" " 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon" " graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "14895" Ports [1, 1] Position [230, 86, 255, 104] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cast');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "14896" Ports [1, 1] Position [230, 101, 255, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cast');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "14897" Ports [3, 1] Position [300, 71, 345, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 30.66 3" "6.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 30.66 24" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('" "input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'en');\ncolor('bl" "ack');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon te" "xt');" } Block { BlockType Outport Name "Q" SID "14898" Position [370, 88, 400, 102] IconDisplay "Port number" } Line { SrcBlock "Convert2" SrcPort 1 DstBlock "Register2" DstPort 3 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "S" SrcPort 1 DstBlock "Convert2" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Register2" DstPort 1 } } } Block { BlockType Reference Name "Scale" SID "153" Ports [1, 1] Position [1345, 543, 1380, 567] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Scale" SourceType "Xilinx Input Scaler Block" infoedit "Scales input by a power of two by adjusting the binary point position.

Hardware notes: " "In hardware this block costs nothing." scale_factor "-7" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,336,191" block_type "scale" block_version "10.1.2" sg_icon_stat "35,24,1,1,white,blue,0,6cf58983,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ]" ",[15.33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.3" "3 12.33 15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 " "12.33 9.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\n\n\ncolor('black');disp('\\bf{2^{-7}}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Scale1" SID "15036" Ports [1, 1] Position [1345, 438, 1380, 462] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Scale" SourceType "Xilinx Input Scaler Block" infoedit "Scales input by a power of two by adjusting the binary point position.

Hardware notes: " "In hardware this block costs nothing." scale_factor "-7" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,336,191" block_type "scale" block_version "10.1.2" sg_icon_stat "35,24,1,1,white,blue,0,6cf58983,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ]" ",[15.33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.3" "3 12.33 15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 " "12.33 9.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\n\n\ncolor('black');disp('\\bf{2^{-7}}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "CFO" SID "154" Position [1495, 548, 1525, 562] IconDisplay "Port number" } Line { Name "Sum Q" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 DstBlock "CFO Est" DstPort 6 } Line { Name "Sum I" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 DstBlock "CFO Est" DstPort 5 } Line { Name "Conj Prod Q" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 DstBlock "CFO Est" DstPort 4 } Line { Name "Conj Prod I" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 DstBlock "CFO Est" DstPort 3 } Line { Name "ADC Q" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 DstBlock "CFO Est" DstPort 2 } Line { Name "ADC I" Labels [0, 0] SrcBlock "Gateway Out" SrcPort 1 DstBlock "CFO Est" DstPort 1 } Line { SrcBlock "rx_valid" SrcPort 1 Points [105, 0] Branch { Points [75, 0] Branch { DstBlock "Conj Mult" DstPort 1 } Branch { Points [0, 95] Branch { DstBlock "Delay2" DstPort 2 } Branch { Points [0, 30] DstBlock "Delay1" DstPort 2 } } } Branch { Points [0, 370] DstBlock "Delay" DstPort 2 } } Line { SrcBlock "rx_I" SrcPort 1 Points [115, 0] Branch { Points [75, 0] Branch { DstBlock "Conj Mult" DstPort 2 } Branch { Points [0, 55] DstBlock "Delay2" DstPort 1 } } Branch { Points [0, -170] DstBlock "Gateway Out" DstPort 1 } } Line { SrcBlock "rx_Q" SrcPort 1 Points [120, 0] Branch { Points [65, 0] Branch { DstBlock "Conj Mult" DstPort 3 } Branch { Points [0, 55] DstBlock "Delay1" DstPort 1 } } Branch { Points [0, -180] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "Delay2" SrcPort 1 DstBlock "Conj Mult" DstPort 4 } Line { SrcBlock "Delay1" SrcPort 1 DstBlock "Conj Mult" DstPort 5 } Line { SrcBlock "Conj Mult" SrcPort 2 Points [35, 0] Branch { DstBlock "Running Sum" DstPort 2 } Branch { Points [0, -160] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "Conj Mult" SrcPort 1 Points [25, 0; 0, 45] Branch { DstBlock "Running Sum" DstPort 1 } Branch { Points [0, 55] DstBlock "Running Sum1" DstPort 1 } } Line { SrcBlock "Conj Mult" SrcPort 3 Points [40, 0] Branch { DstBlock "Running Sum1" DstPort 2 } Branch { Points [0, -195] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "Running Sum" SrcPort 1 Points [15, 0; 0, -10] DstBlock "Phase" DstPort 1 } Line { SrcBlock "Phase" SrcPort 2 Points [150, 0] Branch { Points [0, -95] DstBlock "Gateway Out6" DstPort 1 } Branch { Points [0, 155] Branch { Points [0, 100] DstBlock "Register" DstPort 1 } Branch { DstBlock "Register1" DstPort 1 } } } Line { Name "Phase(Sum)" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 DstBlock "CFO Est" DstPort 7 } Line { SrcBlock "Register" SrcPort 1 DstBlock "Convert2" DstPort 1 } Line { SrcBlock "Convert2" SrcPort 1 DstBlock "Scale" DstPort 1 } Line { SrcBlock "Scale" SrcPort 1 Points [20, 0] Branch { Points [0, -235; -275, 0; 0, -100] DstBlock "Gateway Out8" DstPort 1 } Branch { DstBlock "CFO" DstPort 1 } } Line { Name "LTS Sync" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 DstBlock "CFO Est" DstPort 8 } Line { Name "CFO Est Out" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 DstBlock "CFO Est" DstPort 9 } Line { Points [1230, 240] DstBlock "CFO Est" DstPort 10 } Line { SrcBlock "Delay" SrcPort 1 DstBlock "Posedge3" DstPort 1 } Line { SrcBlock "Posedge3" SrcPort 1 Points [50, 0] Branch { Points [0, -50; -370, 0; 0, 45] DstBlock "S-R Latch2" DstPort 2 } Branch { Points [140, 0] Branch { Points [0, 20] DstBlock "Register" DstPort 3 } Branch { Points [0, -90] Branch { Points [0, -270] DstBlock "Gateway Out7" DstPort 1 } Branch { DstBlock "Register1" DstPort 2 } } } } Line { SrcBlock "Running Sum" SrcPort 2 Points [50, 0] Branch { DstBlock "Phase" DstPort 2 } Branch { Points [0, -120] DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "Running Sum1" SrcPort 2 Points [60, 0; 0, -35] Branch { DstBlock "Phase" DstPort 3 } Branch { Points [0, -120] DstBlock "Gateway Out5" DstPort 1 } } Line { SrcBlock "LTS_Sync" SrcPort 1 DstBlock "S-R Latch2" DstPort 1 } Line { SrcBlock "S-R Latch2" SrcPort 1 DstBlock "Delay" DstPort 1 } Line { SrcBlock "From2" SrcPort 1 DstBlock "Logical" DstPort 2 } Line { SrcBlock "Reset" SrcPort 1 DstBlock "Logical" DstPort 1 } Line { SrcBlock "Logical" SrcPort 1 Points [30, 0; 0, -65] DstBlock "Register" DstPort 2 } Line { SrcBlock "Register1" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Scale1" DstPort 1 } Line { SrcBlock "Scale1" SrcPort 1 DstBlock "Goto" DstPort 1 } Annotation { Name "(1/2) for normalization of phase\n(1/64) for number of summed elements" Position [1368, 584] } Annotation { Name "Delay LTS sync to capture phase sum output from end\nof LTF, maximizing multipath tolerance in the" " CFO est\n\nLatch captures 1-cycle pulse" Position [654, 649] } } } Block { BlockType Scope Name "FFT in FIFO Ctrl" SID "155" Ports [7] Position [1465, 218, 1500, 312] ZOrder -3 Floating off Location [6, 40, 1838, 1194] Open off NumInputPorts "7" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" } List { ListType ScopeGraphics FigureColor "[0.5 0.5 0.5]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "30000" YMin "0~0~0~-0.1~0~-0.1~-0.1" YMax "300~300~1~1.1~4000~1.1~1.1" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType SubSystem Name "FIFO" SID "156" Ports [5, 5] Position [1135, 334, 1245, 596] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "FIFO" Location [88, 301, 2330, 1301] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "data tvalid" SID "157" Position [525, 333, 555, 347] IconDisplay "Port number" } Block { BlockType Inport Name "I" SID "158" Position [325, 353, 355, 367] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "Q" SID "159" Position [325, 378, 355, 392] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "data tlast" SID "160" Position [525, 403, 555, 417] Port "4" IconDisplay "Port number" } Block { BlockType Inport Name "FFT tready" SID "161" Position [525, 298, 555, 312] Port "5" IconDisplay "Port number" } Block { BlockType Reference Name "AXI FIFO" SID "162" Ports [4, 5] Position [625, 283, 825, 427] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AXI FIFO" SourceType "Xilinx AXI FIFO Block Block" input_depth_axis "128" actual_fifo_depth_label "130" enable_tdata on enable_tdest off enable_tstrb off enable_tready on enable_tid off enable_tuser off enable_tkeep off enable_tlast on has_aresetn off enable_data_counts_axis on fifo_implementation_type_axis "Common Clock Block RAM" trim_axipin_name on programmable_full_type_axis "Full" full_threshold_assert_value_axis "0" programmable_empty_type_axis "Empty" empty_threshold_assert_value_axis "1022" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "axi_fifo" sg_icon_stat "200,144,4,5,white,blue,0,c7b89414,right,,[2 3 3 3 ],[2 2 2 3 1 ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 0 4 4 ],[134 110 110 134 ],[5.4666" "67e-001 5.800000e-001 6.400000e-001 ]);\npatch([0 0 4 4 ],[99 5 5 99 ],[3.233333e-001 3.400000e-001 3.700000e-0" "01 ]);\npatch([196 196 200 200 ],[143 61 61 143 ],[5.466667e-001 5.800000e-001 6.400000e-001 ]);\npatch([196 19" "6 200 200 ],[53 31 31 53 ],[3.233333e-001 3.400000e-001 3.700000e-001 ]);\npatch([196 196 200 200 ],[23 1 1 23 " "],[7.700000e-001 8.200000e-001 9.100000e-001 ]);\npatch([4 195 195 4 4 ],[0 0 144 144 0 ],[7.700000e-001 8.2000" "00e-001 9.100000e-001 ]);\nplot([4 195 195 4 4 ],[0 0 144 144 0 ]);\n\n\npatch([55.5 84.4 104.4 124.4 144.4 104" ".4 75.5 55.5 ],[94.2 94.2 114.2 94.2 114.2 114.2 114.2 94.2 ],[1 1 1 ]);\npatch([75.5 104.4 84.4 55.5 75.5 ],[7" "4.2 74.2 94.2 94.2 74.2 ],[0.931 0.946 0.973 ]);\npatch([55.5 84.4 104.4 75.5 55.5 ],[54.2 54.2 74.2 74.2 54.2 " "],[1 1 1 ]);\npatch([75.5 144.4 124.4 104.4 84.4 55.5 75.5 ],[34.2 34.2 54.2 34.2 54.2 54.2 34.2 ],[0.931 0.946" " 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('input',1,' tready ');\ncolor('black');port_label('input',2,' tvalid ');\ncolor('black');port_la" "bel('input',3,' tdata ');\ncolor('black');port_label('input',4,' tlast ');\ncolor('black');port_label('outp" "ut',1,' tvalid ');\ncolor('black');port_label('output',2,' tdata ');\ncolor('black');port_label('output',3," "' tlast ');\ncolor('black');port_label('output',4,' tready ');\ncolor('black');port_label('output',5,' dat" "a_count ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Scope Name "FIFO" SID "163" Ports [9] Position [1535, 181, 1570, 319] ZOrder -3 Floating off Location [246, 238, 2456, 1582] Open off NumInputPorts "9" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" axes9 "%" } List { ListType ScopeGraphics FigureColor "[0.5 0.5 0.5]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "14580 " YMin "0.95~-1~-1~-1~0.95~-1~-1~-1~-1" YMax "1.05~1~1~1~1.05~1~1~1~1" SaveName "ScopeData20" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType Reference Name "Gateway Out1" SID "164" Ports [1, 1] Position [1375, 199, 1410, 211] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "FIFO out valid" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "165" Ports [1, 1] Position [1375, 214, 1410, 226] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Q out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "166" Ports [1, 1] Position [1375, 229, 1410, 241] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "tlast out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "167" Ports [1, 1] Position [1375, 244, 1410, 256] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "FIFO ready" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "168" Ports [1, 1] Position [1375, 259, 1410, 271] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "valid in" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "169" Ports [1, 1] Position [1375, 274, 1410, 286] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "tlast in" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "170" Ports [1, 1] Position [1375, 184, 1410, 196] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "FFT ready" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out9" SID "171" Ports [1, 1] Position [1375, 304, 1410, 316] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "FIFO Occ" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType SubSystem Name "I/Q Concat" SID "172" Ports [2, 1] Position [420, 347, 460, 398] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "I/Q Concat" Location [522, 447, 879, 615] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "I" SID "173" Position [105, 123, 135, 137] IconDisplay "Port number" } Block { BlockType Inport Name "Q" SID "174" Position [105, 158, 135, 172] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Concat" SID "175" Ports [2, 1] Position [315, 110, 350, 185] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point at z" "ero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "35,75,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 75 75 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 75 75 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[42.55 42.55 47." "55 42.55 47.55 47.55 47.55 42.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[37.55 37.55 42.55 42.55 37." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[32.55 32.55 37.55 37.55 32.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[27.55 27.55 32.55 27.55 32.55 32.55 27.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i" "nput',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fontsize{20}\\}','texmode','o" "n');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Reinterpret" SID "176" Ports [1, 1] Position [205, 119, 245, 141] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can change the signal between s" "igned and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.
Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsig" "ned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111" "000 in binary)." force_arith_type on arith_type "Unsigned" force_bin_pt on bin_pt "0" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "reinterpret" sg_icon_stat "40,22,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 22 22 0 ]);\npatch([13.325 17.66 20.66 23.66 26.66 20.66 16.325 13.325 ],[14.33 14" ".33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([16.325 20.66 17.66 13.325 16.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([13.325 17.66 20.66 16.325 13.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 " "1 1 ]);\npatch([16.325 26.66 23.66 20.66 17.66 13.325 16.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');" "disp('reinterpret');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Reinterpret1" SID "177" Ports [1, 1] Position [205, 154, 245, 176] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can change the signal between s" "igned and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.
Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsig" "ned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111" "000 in binary)." force_arith_type on arith_type "Unsigned" force_bin_pt on bin_pt "0" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "reinterpret" sg_icon_stat "40,22,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 22 22 0 ]);\npatch([13.325 17.66 20.66 23.66 26.66 20.66 16.325 13.325 ],[14.33 14" ".33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([16.325 20.66 17.66 13.325 16.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([13.325 17.66 20.66 16.325 13.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 " "1 1 ]);\npatch([16.325 26.66 23.66 20.66 17.66 13.325 16.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');" "disp('reinterpret');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "IQ" SID "178" Position [420, 143, 450, 157] IconDisplay "Port number" } Line { SrcBlock "Reinterpret" SrcPort 1 DstBlock "Concat" DstPort 1 } Line { SrcBlock "Reinterpret1" SrcPort 1 DstBlock "Concat" DstPort 2 } Line { SrcBlock "I" SrcPort 1 DstBlock "Reinterpret" DstPort 1 } Line { SrcBlock "Concat" SrcPort 1 DstBlock "IQ" DstPort 1 } Line { SrcBlock "Q" SrcPort 1 DstBlock "Reinterpret1" DstPort 1 } } } Block { BlockType SubSystem Name "I/Q Slice" SID "179" Ports [1, 2] Position [955, 305, 1005, 340] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "I/Q Slice" Location [1155, 565, 1558, 696] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "IQ" SID "180" Position [190, 123, 220, 137] IconDisplay "Port number" } Block { BlockType Reference Name "Reinterpret2" SID "181" Ports [1, 1] Position [350, 119, 390, 141] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can change the signal between s" "igned and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.
Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsig" "ned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111" "000 in binary)." force_arith_type on arith_type "Signed (2's comp)" force_bin_pt on bin_pt "15" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "reinterpret" sg_icon_stat "40,22,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 22 22 0 ]);\npatch([13.325 17.66 20.66 23.66 26.66 20.66 16.325 13.325 ],[14.33 14" ".33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([16.325 20.66 17.66 13.325 16.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([13.325 17.66 20.66 16.325 13.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 " "1 1 ]);\npatch([16.325 26.66 23.66 20.66 17.66 13.325 16.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');" "disp('reinterpret');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Reinterpret3" SID "182" Ports [1, 1] Position [350, 144, 390, 166] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can change the signal between s" "igned and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.
Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsig" "ned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111" "000 in binary)." force_arith_type on arith_type "Signed (2's comp)" force_bin_pt on bin_pt "15" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "reinterpret" sg_icon_stat "40,22,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 22 22 0 ]);\npatch([13.325 17.66 20.66 23.66 26.66 20.66 16.325 13.325 ],[14.33 14" ".33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([16.325 20.66 17.66 13.325 16.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([13.325 17.66 20.66 16.325 13.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 " "1 1 ]);\npatch([16.325 26.66 23.66 20.66 17.66 13.325 16.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');" "disp('reinterpret');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Slice" SID "183" Ports [1, 1] Position [265, 119, 300, 141] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type" " is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardw" "are notes: In hardware this block costs nothing." nbits "16" boolean_output off mode "Upper Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "35,22,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 22 22 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[14.33 14" ".33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 " "1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');po" "rt_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Slice1" SID "184" Ports [1, 1] Position [265, 144, 300, 166] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type" " is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardw" "are notes: In hardware this block costs nothing." nbits "16" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "35,22,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 22 22 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[14.33 14" ".33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 " "1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');po" "rt_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "I" SID "185" Position [450, 123, 480, 137] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Outport Name "Q" SID "186" Position [450, 148, 480, 162] Port "2" IconDisplay "Port number" } Line { SrcBlock "Reinterpret3" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "Reinterpret2" SrcPort 1 DstBlock "I" DstPort 1 } Line { SrcBlock "IQ" SrcPort 1 Points [15, 0] Branch { DstBlock "Slice" DstPort 1 } Branch { Points [0, 25] DstBlock "Slice1" DstPort 1 } } Line { SrcBlock "Slice1" SrcPort 1 DstBlock "Reinterpret3" DstPort 1 } Line { SrcBlock "Slice" SrcPort 1 DstBlock "Reinterpret2" DstPort 1 } } } Block { BlockType Reference Name "Logical2" SID "187" Ports [2, 1] Position [900, 334, 930, 361] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "30,27,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 27 27 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 27 27 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[" "16.33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 1" "3.33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13." "33 10.33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\n\n\n\ncolor('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "FFT tvalid" SID "188" Position [900, 288, 930, 302] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Outport Name "FFT tdata_re" SID "189" Position [1075, 308, 1105, 322] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "FFT tdata_im" SID "190" Position [1075, 323, 1105, 337] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "FFT tlast" SID "191" Position [1325, 343, 1355, 357] Port "4" IconDisplay "Port number" } Block { BlockType Outport Name "FIFO tready" SID "192" Position [900, 378, 930, 392] Port "5" IconDisplay "Port number" } Line { SrcBlock "AXI FIFO" SrcPort 2 DstBlock "I/Q Slice" DstPort 1 } Line { SrcBlock "AXI FIFO" SrcPort 1 Points [30, 0] Branch { DstBlock "FFT tvalid" DstPort 1 } Branch { Points [0, -90] DstBlock "Gateway Out1" DstPort 1 } Branch { Points [0, 45] DstBlock "Logical2" DstPort 1 } } Line { SrcBlock "AXI FIFO" SrcPort 3 DstBlock "Logical2" DstPort 2 } Line { Name "FFT ready" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 DstBlock "FIFO" DstPort 1 } Line { SrcBlock "I/Q Slice" SrcPort 1 DstBlock "FFT tdata_re" DstPort 1 } Line { SrcBlock "I/Q Slice" SrcPort 2 Points [10, 0] Branch { DstBlock "FFT tdata_im" DstPort 1 } Branch { Points [0, -110] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "FFT tready" SrcPort 1 Points [30, 0] Branch { Points [0, -115] DstBlock "Gateway Out8" DstPort 1 } Branch { DstBlock "AXI FIFO" DstPort 1 } } Line { SrcBlock "data tvalid" SrcPort 1 Points [40, 0] Branch { Points [0, 165; 550, 0; 0, -240] DstBlock "Gateway Out5" DstPort 1 } Branch { DstBlock "AXI FIFO" DstPort 2 } } Line { SrcBlock "data tlast" SrcPort 1 Points [30, 0] Branch { Points [0, 80; 575, 0; 0, -210] DstBlock "Gateway Out6" DstPort 1 } Branch { DstBlock "AXI FIFO" DstPort 4 } } Line { SrcBlock "AXI FIFO" SrcPort 4 Points [25, 0] Branch { DstBlock "FIFO tready" DstPort 1 } Branch { Points [0, 55; 285, 0; 0, -190] DstBlock "Gateway Out4" DstPort 1 } } Line { Name "FIFO out valid" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 DstBlock "FIFO" DstPort 2 } Line { Name "Q out" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 DstBlock "FIFO" DstPort 3 } Line { Name "tlast out" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 DstBlock "FIFO" DstPort 4 } Line { Name "FIFO ready" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 DstBlock "FIFO" DstPort 5 } Line { Name "valid in" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 DstBlock "FIFO" DstPort 6 } Line { Name "tlast in" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 DstBlock "FIFO" DstPort 7 } Line { SrcBlock "Logical2" SrcPort 1 Points [360, 0] Branch { DstBlock "FFT tlast" DstPort 1 } Branch { Points [0, -115] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "I" SrcPort 1 DstBlock "I/Q Concat" DstPort 1 } Line { SrcBlock "Q" SrcPort 1 DstBlock "I/Q Concat" DstPort 2 } Line { SrcBlock "I/Q Concat" SrcPort 1 DstBlock "AXI FIFO" DstPort 3 } Line { Name "Reset" Labels [0, 0] Points [1415, 295] DstBlock "FIFO" DstPort 8 } Line { Name "FIFO Occ" Labels [0, 0] SrcBlock "Gateway Out9" SrcPort 1 DstBlock "FIFO" DstPort 9 } Line { SrcBlock "AXI FIFO" SrcPort 5 Points [530, 0] DstBlock "Gateway Out9" DstPort 1 } Annotation { Name "AND not strictly necessary, since FFT\nonly honors tlast when tvalid is asserted.\nExplicit AND he" "re makes scopes\nmuch easier to understand." Position [959, 576] } Annotation { Name "This FIFO aids in synchronizing sample generation\nand feeding the FFT. It would be possible to de" "sign\nthe sample buffer control logic not to require\nthis FIFO, but then the logic would need tweaking\nif the" " FFT timing or sample processing timing\never change. This FIFO isolates those blocks,\nat the cost of a little" " memory and 1 clock cyle latency\n(assuming the FFT consumes samples faster than\nthey're received)" Position [723, 91] } } } Block { BlockType Reference Name "Gateway Out1" SID "193" Ports [1, 1] Position [1315, 244, 1350, 256] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.88" " ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.11 " "8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 ],[" "0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([15." "775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" Port { PortNumber 1 Name "FIFO Out: valid" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out10" SID "194" Ports [1, 1] Position [725, 229, 760, 241] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.88" " ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.11 " "8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 ],[" "0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([15." "775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" Port { PortNumber 1 Name "Pkt Det" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out17" SID "195" Ports [1, 1] Position [725, 184, 760, 196] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.88" " ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.11 " "8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 ],[" "0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([15." "775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" Port { PortNumber 1 Name "ADC I" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "196" Ports [1, 1] Position [1315, 259, 1350, 271] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.88" " ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.11 " "8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 ],[" "0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([15." "775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" Port { PortNumber 1 Name "FIFO Out: tlast" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "197" Ports [1, 1] Position [1315, 214, 1350, 226] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.88" " ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.11 " "8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 ],[" "0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([15." "775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" Port { PortNumber 1 Name "FIFO IN: tlast" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "198" Ports [1, 1] Position [1315, 229, 1350, 241] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.88" " ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.11 " "8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 ],[" "0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([15." "775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" Port { PortNumber 1 Name "FIFO IN: valid" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "199" Ports [1, 1] Position [725, 214, 760, 226] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.88" " ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.11 " "8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 ],[" "0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([15." "775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" Port { PortNumber 1 Name "ADC Valid" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "200" Ports [1, 1] Position [1320, 304, 1355, 316] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.88" " ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.11 " "8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 ],[" "0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([15." "775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" Port { PortNumber 1 Name "Reset" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "201" Ports [1, 1] Position [725, 199, 760, 211] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.88" " ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.11 " "8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 ],[" "0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([15." "775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" Port { PortNumber 1 Name "ADC Q" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out9" SID "202" Ports [1, 1] Position [1315, 274, 1350, 286] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.88" " ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.11 " "8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 ],[" "0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([15." "775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" Port { PortNumber 1 Name "FFT in: tready" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType SubSystem Name "Samp Buffer" SID "203" Ports [7, 5] Position [695, 349, 780, 491] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Samp Buffer" Location [589, 321, 2367, 1501] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "108" Block { BlockType Inport Name "Pkt Det" SID "204" Position [15, 238, 45, 252] IconDisplay "Port number" } Block { BlockType Inport Name "Pkt Done" SID "205" Position [190, 268, 220, 282] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "rx I" SID "206" Position [450, 333, 480, 347] NamePlacement "alternate" Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "rx Q" SID "207" Position [450, 348, 480, 362] Port "4" IconDisplay "Port number" } Block { BlockType Inport Name "IQ valid" SID "208" Position [15, 363, 45, 377] Port "5" IconDisplay "Port number" } Block { BlockType Inport Name "LTS Sync 2" SID "209" Position [190, 628, 220, 642] NamePlacement "alternate" Port "6" IconDisplay "Port number" } Block { BlockType Inport Name "FIFO tready" SID "210" Position [300, 488, 330, 502] NamePlacement "alternate" Port "7" IconDisplay "Port number" } Block { BlockType Reference Name "Circular Sample\nBuffer" SID "211" Ports [6, 2] Position [715, 317, 805, 443] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Dual Port RAM" SourceType "Xilinx Dual Port Random Access Memory Block" depth "preFFT_sampBuff_numSamps" initVector "1 * repmat([0:63], 1, 4)" distributed_mem "Block RAM" init_a "0" init_b "0" rst_a off rst_b off en_a off en_b off latency "1" write_mode_A "Read After Write" write_mode_B "Read After Write" dbl_ovrd off optimize "Area" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "dpram" sg_icon_stat "90,126,6,2,white,blue,0,28af736d,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 90 90 0 0 ],[0 0 126 126 0 ],[0.77" " 0.82 0.91 ]);\nplot([0 90 90 0 0 ],[0 0 126 126 0 ]);\npatch([18.3 35.64 47.64 59.64 71.64 47.64 30.3 18.3 ],[" "76.32 76.32 88.32 76.32 88.32 88.32 88.32 76.32 ],[1 1 1 ]);\npatch([30.3 47.64 35.64 18.3 30.3 ],[64.32 64.32 " "76.32 76.32 64.32 ],[0.931 0.946 0.973 ]);\npatch([18.3 35.64 47.64 30.3 18.3 ],[52.32 52.32 64.32 64.32 52.32 " "],[1 1 1 ]);\npatch([30.3 71.64 59.64 47.64 35.64 18.3 30.3 ],[40.32 40.32 52.32 40.32 52.32 52.32 40.32 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'addra');\ncolor('black');port_label('input',2,'dina');\ncolor('black');port_label" "('input',3,'wea');\ncolor('black');port_label('input',4,'addrb');\ncolor('black');port_label('input',5,'dinb');" "\ncolor('black');port_label('input',6,'web');\ncolor('black');port_label('output',1,'A');\ncolor('black');port_" "label('output',2,'B');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Concat" SID "212" Ports [2, 1] Position [535, 330, 585, 365] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Concat" Location [522, 447, 879, 615] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "I" SID "213" Position [105, 123, 135, 137] IconDisplay "Port number" } Block { BlockType Inport Name "Q" SID "214" Position [105, 158, 135, 172] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Concat" SID "215" Ports [2, 1] Position [315, 110, 350, 185] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point at z" "ero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "35,75,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 75 75 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 75 75 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[42.55 42.55 47." "55 42.55 47.55 47.55 47.55 42.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[37.55 37.55 42.55 42.55 37." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[32.55 32.55 37.55 37.55 32.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[27.55 27.55 32.55 27.55 32.55 32.55 27.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i" "nput',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fontsize{20}\\}','texmode','o" "n');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Reinterpret" SID "216" Ports [1, 1] Position [205, 119, 245, 141] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can change the signal between s" "igned and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.
Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsig" "ned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111" "000 in binary)." force_arith_type on arith_type "Unsigned" force_bin_pt on bin_pt "0" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "reinterpret" sg_icon_stat "40,22,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 22 22 0 ]);\npatch([13.325 17.66 20.66 23.66 26.66 20.66 16.325 13.325 ],[14.33 14" ".33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([16.325 20.66 17.66 13.325 16.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([13.325 17.66 20.66 16.325 13.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 " "1 1 ]);\npatch([16.325 26.66 23.66 20.66 17.66 13.325 16.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');" "disp('reinterpret');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Reinterpret1" SID "217" Ports [1, 1] Position [205, 154, 245, 176] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can change the signal between s" "igned and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.
Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsig" "ned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111" "000 in binary)." force_arith_type on arith_type "Unsigned" force_bin_pt on bin_pt "0" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "reinterpret" sg_icon_stat "40,22,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 22 22 0 ]);\npatch([13.325 17.66 20.66 23.66 26.66 20.66 16.325 13.325 ],[14.33 14" ".33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([16.325 20.66 17.66 13.325 16.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([13.325 17.66 20.66 16.325 13.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 " "1 1 ]);\npatch([16.325 26.66 23.66 20.66 17.66 13.325 16.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');" "disp('reinterpret');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "IQ" SID "218" Position [495, 143, 525, 157] IconDisplay "Port number" } Line { SrcBlock "Reinterpret" SrcPort 1 DstBlock "Concat" DstPort 1 } Line { SrcBlock "Reinterpret1" SrcPort 1 DstBlock "Concat" DstPort 2 } Line { SrcBlock "I" SrcPort 1 DstBlock "Reinterpret" DstPort 1 } Line { SrcBlock "Concat" SrcPort 1 DstBlock "IQ" DstPort 1 } Line { SrcBlock "Q" SrcPort 1 DstBlock "Reinterpret1" DstPort 1 } } } Block { BlockType Reference Name "Constant3" SID "219" Ports [0, 1] Position [655, 401, 680, 419] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "8" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,18,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.2" "2 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 " "11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);" "\npatch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('" "output',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant4" SID "220" Ports [0, 1] Position [655, 421, 680, 439] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Boolean" arith_type "Boolean" n_bits "6" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "8" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,18,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.2" "2 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 " "11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);" "\npatch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('" "output',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Counter" SID "221" Ports [1, 1] Position [320, 279, 385, 311] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited co" "unter is implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "Inf" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "ceil(log2(preFFT_sampBuff_numSamps))" bin_pt "0" load_pin off rst off en on explicit_period "off" period "8" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "counter" sg_icon_stat "65,32,1,1,white,blue,0,b089e9c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 32 32 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 65 65 0 0 ],[0 0 32 32 0 ]);\npatch([23.1 28.88 32.88 36.88 40.88 32.88 27.1 23.1 ],[20.4" "4 20.44 24.44 20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([27.1 32.88 28.88 23.1 27.1 ],[16.44 16.44 20.4" "4 20.44 16.44 ],[0.931 0.946 0.973 ]);\npatch([23.1 28.88 32.88 27.1 23.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1" " 1 1 ]);\npatch([27.1 40.88 36.88 32.88 28.88 23.1 27.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946" " 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('input',1,'en');\n\ncolor('black');disp('{\\fontsize{14}\\bf++}','texmode','on');\nfprintf('','COMME" "NT: end icon text');" } Block { BlockType Reference Name "Delay" SID "222" Ports [1, 1] Position [715, 510, 745, 530] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "30,20,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 20 20 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 20 20 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[1" "2.22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[10.22 10.2" "2 12.22 12.22 10.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[8.22 8.22 10.22 10.22 8.2" "2 ],[1 1 1 ]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931" " 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor" "('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay2" SID "223" Ports [1, 1] Position [715, 490, 745, 510] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "30,20,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 20 20 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 20 20 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[1" "2.22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[10.22 10.2" "2 12.22 12.22 10.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[8.22 8.22 10.22 10.22 8.2" "2 ],[1 1 1 ]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931" " 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor" "('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "FFT Load Ctrl" SID "224" Ports [6, 5] Position [515, 470, 630, 565] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "FFT Load Ctrl" Location [88, 301, 2330, 1301] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "139" Block { BlockType Inport Name "Wr Addr" SID "225" Position [490, 288, 520, 302] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "data tready" SID "226" Position [170, 503, 200, 517] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "LTS Sync" SID "227" Position [490, 318, 520, 332] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "Skip Sel" SID "228" Position [765, 403, 795, 417] NamePlacement "alternate" Port "4" IconDisplay "Port number" } Block { BlockType Inport Name "FFT LTS Load" SID "229" Position [170, 593, 200, 607] Port "5" IconDisplay "Port number" } Block { BlockType Inport Name "FFT Load" SID "230" Position [170, 538, 200, 552] Port "6" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub4" SID "231" Ports [2, 1] Position [1085, 390, 1135, 425] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Unsigned" n_bits "ceil(log2(preFFT_sampBuff_numSamps))" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL off hw_selection "Fabric" pipelined off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" sg_icon_stat "50,35,2,1,white,blue,0,e139daf6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 35 35 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 50 50 0 0 ],[0 0 35 35 0 ]);\npatch([13.875 21.1 26.1 31.1 36.1 26.1 18.875 13.875 ],[22.55 22.55 2" "7.55 22.55 27.55 27.55 27.55 22.55 ],[1 1 1 ]);\npatch([18.875 26.1 21.1 13.875 18.875 ],[17.55 17.55 22.55 22.55 " "17.55 ],[0.931 0.946 0.973 ]);\npatch([13.875 21.1 26.1 18.875 13.875 ],[12.55 12.55 17.55 17.55 12.55 ],[1 1 1 ])" ";\npatch([18.875 36.1 31.1 26.1 21.1 13.875 18.875 ],[7.55 7.55 12.55 7.55 12.55 12.55 7.55 ],[0.931 0.946 0.973 ]" ");\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label(" "'input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bf{a + b}','te" "xmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "232" Ports [1, 1] Position [265, 501, 290, 519] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cast');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Count-To Calc" SID "233" Ports [1, 2] Position [915, 391, 975, 429] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Count-To Calc" Location [904, 1040, 1324, 1205] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Skip Sel" SID "234" Position [245, 253, 275, 267] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub1" SID "235" Ports [2, 1] Position [480, 280, 530, 315] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Unsigned" n_bits "ceil(log2(preFFT_sampBuff_numSamps))" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL off hw_selection "Fabric" pipelined off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" sg_icon_stat "50,35,2,1,white,blue,0,e139daf6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 35 35 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 35 35 0 ]);\npatch([13.875 21.1 26.1 31.1 36.1 26.1 18.875 13.875 ],[22.55 2" "2.55 27.55 22.55 27.55 27.55 27.55 22.55 ],[1 1 1 ]);\npatch([18.875 26.1 21.1 13.875 18.875 ],[17.55 17.55 22.5" "5 22.55 17.55 ],[0.931 0.946 0.973 ]);\npatch([13.875 21.1 26.1 18.875 13.875 ],[12.55 12.55 17.55 17.55 12.55 ]" ",[1 1 1 ]);\npatch([18.875 36.1 31.1 26.1 21.1 13.875 18.875 ],[7.55 7.55 12.55 7.55 12.55 12.55 7.55 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'" "\\bf{a + b}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant4" SID "236" Ports [0, 1] Position [305, 281, 330, 299] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "8" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,18,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output'" ",1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Display Name "Display" SID "237" Ports [1] Position [530, 410, 620, 440] ZOrder -1 ShowName off Decimation "1" Lockdown off } Block { BlockType Display Name "Display1" SID "238" Ports [1] Position [530, 445, 620, 475] ZOrder -1 ShowName off Decimation "1" Lockdown off } Block { BlockType From Name "From2" SID "239" Position [210, 313, 340, 327] ShowName off CloseFcn "tagdialog Close" GotoTag "regRx_CP_LEN" TagVisibility "global" } Block { BlockType From Name "From3" SID "240" Position [210, 343, 340, 357] ShowName off CloseFcn "tagdialog Close" GotoTag "regRx_NUM_SC" TagVisibility "global" } Block { BlockType Reference Name "Gateway Out" SID "241" Ports [1, 1] Position [425, 418, 465, 432] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "40,14,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9.22 " "9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22 9.22" " 7.22 ],[0.964 0.964 0.964 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\np" "atch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.964 0.964 0.964 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i" "nput',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMEN" "T: end icon text');" } Block { BlockType Reference Name "Gateway Out1" SID "242" Ports [1, 1] Position [425, 453, 465, 467] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "40,14,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9.22 " "9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22 9.22" " 7.22 ],[0.964 0.964 0.964 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\np" "atch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.964 0.964 0.964 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i" "nput',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMEN" "T: end icon text');" } Block { BlockType Reference Name "Mux" SID "243" Ports [3, 1] Position [390, 244, 420, 336] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "30,92,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 13.1429 78.8571 92 0 ]" ",[0.77 0.82 0.91 ]);\nplot([0 30 30 0 0 ],[0 13.1429 78.8571 92 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 " "10.1 6.1 ],[50.44 50.44 54.44 50.44 54.44 54.44 54.44 50.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[46" ".44 46.44 50.44 50.44 46.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[42.44 42.44 46.44 46.44" " 42.44 ],[1 1 1 ]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[38.44 38.44 42.44 38.44 42.44 42.44 38.44 ]" ",[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncol" "or('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label(" "'input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Samp+Skip" SID "244" Position [605, 293, 635, 307] IconDisplay "Port number" } Block { BlockType Outport Name "Samp" SID "245" Position [605, 353, 635, 367] Port "2" IconDisplay "Port number" } Line { SrcBlock "From2" SrcPort 1 Points [15, 0] Branch { DstBlock "Mux" DstPort 3 } Branch { Points [0, 105] DstBlock "Gateway Out" DstPort 1 } } Line { SrcBlock "Skip Sel" SrcPort 1 DstBlock "Mux" DstPort 1 } Line { SrcBlock "Constant4" SrcPort 1 DstBlock "Mux" DstPort 2 } Line { SrcBlock "Mux" SrcPort 1 DstBlock "AddSub1" DstPort 1 } Line { SrcBlock "AddSub1" SrcPort 1 DstBlock "Samp+Skip" DstPort 1 } Line { SrcBlock "From3" SrcPort 1 Points [10, 0] Branch { Points [85, 0] Branch { Points [0, -45] DstBlock "AddSub1" DstPort 2 } Branch { Points [0, 10] DstBlock "Samp" DstPort 1 } } Branch { Points [0, 110] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "Gateway Out" SrcPort 1 DstBlock "Display" DstPort 1 } Line { SrcBlock "Gateway Out1" SrcPort 1 DstBlock "Display1" DstPort 1 } } } Block { BlockType Scope Name "Ctrl" SID "246" Ports [7] Position [1540, 143, 1575, 237] ZOrder -3 Floating off Location [1389, 159, 2380, 1503] Open off NumInputPorts "7" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" } List { ListType ScopeGraphics FigureColor "[0.5 0.5 0.5]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "1322.580645161291" YMin "-1~70~59.85~166.25~-1~-1~166.25" YMax "1~135~66.15~183.75~1~1~183.75" SaveName "ScopeData5" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType Reference Name "Delay" SID "247" Ports [1, 1] Position [655, 455, 685, 485] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "30,30,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 30 30 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 19.44 23.4" "4 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 19.44 15.44 ]," "[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([10.1" " 23.88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-1}','texmode'," "'on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "First Samp\nCalc" SID "248" Ports [2, 1] Position [635, 280, 710, 340] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "First Samp\nCalc" Location [677, 751, 1183, 937] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Wr Addr" SID "249" Position [220, 193, 250, 207] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "LTS Sync" SID "250" Position [220, 213, 250, 227] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub2" SID "251" Ports [2, 1] Position [585, 179, 620, 306] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Subtraction" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Unsigned" n_bits "ceil(log2(preFFT_sampBuff_numSamps))" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL off hw_selection "Fabric" pipelined off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" sg_icon_stat "35,127,2,1,white,blue,0,32e1f85f,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 127 127 0 ],[0.77 0." "82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 127 127 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[68.55" " 68.55 73.55 68.55 73.55 73.55 73.55 68.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[63.55 63.55 68." "55 68.55 63.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[58.55 58.55 63.55 63.55 58.55 ]," "[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[53.55 53.55 58.55 53.55 58.55 58.55 53.55 ],[0.931" " 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bla" "ck');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1" ",'\\bf{a - b}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub3" SID "252" Ports [2, 1] Position [440, 247, 485, 303] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Unsigned" n_bits "ceil(log2(preFFT_sampBuff_numSamps))" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL off hw_selection "Fabric" pipelined off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" sg_icon_stat "45,56,2,1,white,blue,0,e139daf6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 56 56 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 56 56 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[34.66 3" "4.66 40.66 34.66 40.66 40.66 40.66 34.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[28.66 28.66 34.66 " "34.66 28.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[22.66 22.66 28.66 28.66 22.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[16.66 16.66 22.66 16.66 22.66 22.66 16.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bf{a + b}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From1" SID "253" Position [170, 253, 300, 267] ShowName off CloseFcn "tagdialog Close" GotoTag "regRx_NUM_SC" TagVisibility "global" } Block { BlockType From Name "From2" SID "254" Position [170, 283, 300, 297] ShowName off CloseFcn "tagdialog Close" GotoTag "regRx_FFT_OFFSET" TagVisibility "global" } Block { BlockType Reference Name "Register" SID "255" Ports [2, 1] Position [405, 192, 445, 228] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "40,36,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 36 36 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 36 36 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[23.55 23." "55 28.55 23.55 28.55 28.55 28.55 23.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[18.55 18.55 23.55 2" "3.55 18.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[13.55 13.55 18.55 18.55 13.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[8.55 8.55 13.55 8.55 13.55 13.55 8.55 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');por" "t_label('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\n" "color('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Shift" SID "256" Ports [1, 1] Position [355, 246, 405, 274] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Shift" SourceType "Xilinx Binary Shift Operator Block" infoedit "Hardware notes: In hardware this block costs nothing if full output precision is used." shift_dir "Left" shift_bits "1" en off latency "0" precision "Full" arith_type "Signed (2's comp)" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "shift" sg_icon_stat "50,28,1,1,white,blue,0,6c6aa2df,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 28 28 0 ]);\npatch([16.1 21.88 25.88 29.88 33.88 25.88 20.1 16.1 ],[18.44 18" ".44 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([20.1 25.88 21.88 16.1 20.1 ],[14.44 14.44 18.44 18." "44 14.44 ],[0.931 0.946 0.973 ]);\npatch([16.1 21.88 25.88 20.1 16.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]" ");\npatch([20.1 33.88 29.88 25.88 21.88 16.1 20.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 " "]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp" "('\\bf{X << 1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Samp Addr" SID "257" Position [695, 238, 725, 252] IconDisplay "Port number" } Line { SrcBlock "From1" SrcPort 1 DstBlock "Shift" DstPort 1 } Line { SrcBlock "Shift" SrcPort 1 DstBlock "AddSub3" DstPort 1 } Line { SrcBlock "AddSub3" SrcPort 1 DstBlock "AddSub2" DstPort 2 } Line { SrcBlock "Register" SrcPort 1 DstBlock "AddSub2" DstPort 1 } Line { SrcBlock "Wr Addr" SrcPort 1 DstBlock "Register" DstPort 1 } Line { SrcBlock "AddSub2" SrcPort 1 DstBlock "Samp Addr" DstPort 1 } Line { SrcBlock "LTS Sync" SrcPort 1 DstBlock "Register" DstPort 2 } Line { SrcBlock "From2" SrcPort 1 DstBlock "AddSub3" DstPort 2 } Annotation { Name "NUM_SC = length(LTS), so 2*NUM_SC points to first sample of first LTS\nFFT_OFFSET adjusts this pointe" "r into the 32-sample cyclic prefix\nin front of the first LTS." Position [236, 382] HorizontalAlignment "left" } } } Block { BlockType Reference Name "Gateway Out1" SID "258" Ports [1, 1] Position [1395, 139, 1430, 151] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "LTS Sync" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "259" Ports [1, 1] Position [1395, 154, 1430, 166] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Rx Samp Ind" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "260" Ports [1, 1] Position [1395, 169, 1430, 181] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Init Samp Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "261" Ports [1, 1] Position [1395, 184, 1430, 196] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Rd Counter" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "262" Ports [1, 1] Position [1395, 214, 1430, 226] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "FFT tvalid" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "263" Ports [1, 1] Position [1395, 229, 1430, 241] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Rd Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "264" Ports [1, 1] Position [1395, 199, 1430, 211] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Samp Counter" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Inverter" SID "265" Ports [1, 1] Position [600, 606, 625, 624] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Logical" SID "266" Ports [2, 1] Position [285, 534, 325, 576] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,42,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 42 42 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 42 42 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[26.55 26.55 31." "55 26.55 31.55 31.55 31.55 26.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[21.55 21.55 26.55 26.55 21." "55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[16.55 16.55 21.55 21.55 16.55 ],[1 1 1 ]);\npa" "tch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[11.55 11.55 16.55 11.55 16.55 16.55 11.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('a" "nd');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "267" Ports [2, 1] Position [845, 494, 875, 521] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "30,27,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 27 27 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 27 27 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[16.33 16.3" "3 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 13.33 16.33 16" ".33 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 " "1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black'" ");disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "268" Ports [2, 1] Position [1205, 569, 1245, 611] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,42,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 42 42 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 42 42 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[26.55 26.55 31." "55 26.55 31.55 31.55 31.55 26.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[21.55 21.55 26.55 26.55 21." "55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[16.55 16.55 21.55 21.55 16.55 ],[1 1 1 ]);\npa" "tch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[11.55 11.55 16.55 11.55 16.55 16.55 11.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('a" "nd');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical3" SID "269" Ports [2, 1] Position [355, 544, 395, 586] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,42,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 42 42 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 42 42 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[26.55 26.55 31." "55 26.55 31.55 31.55 31.55 26.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[21.55 21.55 26.55 26.55 21." "55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[16.55 16.55 21.55 21.55 16.55 ],[1 1 1 ]);\npa" "tch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[11.55 11.55 16.55 11.55 16.55 16.55 11.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('o" "r');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical4" SID "270" Ports [3, 1] Position [665, 504, 705, 546] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,42,3,1,white,blue,0,98d76266,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 42 42 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 42 42 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[26.55 26.55 31." "55 26.55 31.55 31.55 31.55 26.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[21.55 21.55 26.55 26.55 21." "55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[16.55 16.55 21.55 21.55 16.55 ],[1 1 1 ]);\npa" "tch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[11.55 11.55 16.55 11.55 16.55 16.55 11.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\ncolor('black');disp(" "'and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Posedge" SID "271" Ports [1, 1] Position [1265, 733, 1320, 757] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Posedge" Location [384, 656, 940, 879] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "272" Position [200, 253, 230, 267] IconDisplay "Port number" } Block { BlockType Reference Name "Delay" SID "273" Ports [1, 1] Position [425, 153, 460, 177] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. " "If register retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[15" ".33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.33 12." "33 15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 12.33 " "9.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\nc" "olor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "274" Ports [1, 1] Position [490, 156, 515, 174] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "275" Ports [2, 1] Position [540, 151, 585, 204] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,53,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 53 53 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 53 53 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[32.66 3" "2.66 38.66 32.66 38.66 38.66 38.66 32.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[26.66 26.66 32.66 " "32.66 26.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[20.66 20.66 26.66 26.66 20.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[14.66 14.66 20.66 14.66 20.66 20.66 14.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('" "black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "276" Position [610, 173, 640, 187] IconDisplay "Port number" } Line { SrcBlock "D" SrcPort 1 Points [150, 0; 0, -70] Branch { DstBlock "Logical1" DstPort 2 } Branch { Points [0, -25] DstBlock "Delay" DstPort 1 } } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Delay" SrcPort 1 DstBlock "Inverter" DstPort 1 } Annotation { Name "Rising Edge Detection" Position [500, 112] } } } Block { BlockType Reference Name "Rd Counter" SID "277" Ports [3, 1] Position [915, 463, 975, 517] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited counter i" "s implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "Inf" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "ceil(log2(preFFT_sampBuff_numSamps))" bin_pt "0" load_pin on rst off en on explicit_period "off" period "8" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "counter" sg_icon_stat "60,54,3,1,white,blue,0,4f561634,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 54 54 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 60 60 0 0 ],[0 0 54 54 0 ]);\npatch([14.425 24.54 31.54 38.54 45.54 31.54 21.425 14.425 ],[34.77 34" ".77 41.77 34.77 41.77 41.77 41.77 34.77 ],[1 1 1 ]);\npatch([21.425 31.54 24.54 14.425 21.425 ],[27.77 27.77 34.77" " 34.77 27.77 ],[0.931 0.946 0.973 ]);\npatch([14.425 24.54 31.54 21.425 14.425 ],[20.77 20.77 27.77 27.77 20.77 ]," "[1 1 1 ]);\npatch([21.425 45.54 38.54 31.54 24.54 14.425 21.425 ],[13.77 13.77 20.77 13.77 20.77 20.77 13.77 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,'load');\ncolor('black');port_label('input',2,'din');\ncolor('black');port_label('input" "',3,'en');\n\ncolor('black');disp('{\\fontsize{14}\\bf++}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational1" SID "278" Ports [2, 1] Position [1225, 379, 1270, 421] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "45,42,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 42 42 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 42 42 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[27.66 27.66 3" "3.66 27.66 33.66 33.66 33.66 27.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[21.66 21.66 27.66 27.66 21" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[15.66 15.66 21.66 21.66 15.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[9.66 9.66 15.66 9.66 15.66 15.66 9.66 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('inpu" "t',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa = b','texmode'," "'on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational2" SID "279" Ports [2, 1] Position [1045, 624, 1090, 666] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "45,42,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 42 42 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 42 42 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[27.66 27.66 3" "3.66 27.66 33.66 33.66 33.66 27.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[21.66 21.66 27.66 27.66 21" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[15.66 15.66 21.66 21.66 15.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[9.66 9.66 15.66 9.66 15.66 15.66 9.66 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('inpu" "t',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa = b','texmode'," "'on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational3" SID "280" Ports [2, 1] Position [1045, 534, 1090, 576] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a<=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "45,42,2,1,white,blue,0,52e4b236,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 42 42 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 42 42 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[27.66 27.66 3" "3.66 27.66 33.66 33.66 33.66 27.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[21.66 21.66 27.66 27.66 21" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[15.66 15.66 21.66 21.66 15.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[9.66 9.66 15.66 9.66 15.66 15.66 9.66 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('inpu" "t',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa \\leq b','texmo" "de','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational4" SID "281" Ports [2, 1] Position [1045, 579, 1090, 621] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a>b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "45,42,2,1,white,blue,0,b5131c97,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 42 42 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 42 42 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[27.66 27.66 3" "3.66 27.66 33.66 33.66 33.66 27.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[21.66 21.66 27.66 27.66 21" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[15.66 15.66 21.66 21.66 15.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[9.66 9.66 15.66 9.66 15.66 15.66 9.66 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('inpu" "t',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa > b','texmode'," "'on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "S-R Latch1" SID "282" Ports [2, 1] Position [570, 558, 605, 587] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "S-R Latch1" Location [351, 366, 2001, 1172] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "283" Position [140, 103, 170, 117] IconDisplay "Port number" } Block { BlockType Inport Name "R" SID "284" Position [140, 88, 170, 102] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "285" Ports [0, 1] Position [195, 71, 210, 89] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "15,18,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11.22 " "13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 9.22 " "],[0.931 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([4.55 " "11.44 9.44 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "286" Ports [1, 1] Position [210, 86, 235, 104] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('outpu" "t',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "287" Ports [1, 1] Position [210, 101, 235, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('outpu" "t',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "288" Ports [3, 1] Position [255, 71, 300, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "289" Position [325, 88, 355, 102] IconDisplay "Port number" } Line { SrcBlock "S" SrcPort 1 DstBlock "Convert2" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "Convert2" SrcPort 1 DstBlock "Register2" DstPort 3 } } } Block { BlockType Reference Name "Samp Counter" SID "290" Ports [2, 1] Position [915, 537, 975, 588] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited counter i" "s implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "Inf" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "ceil(log2(MAX_NUM_SC+MAX_CP_LEN))" bin_pt "0" load_pin off rst on en on explicit_period "off" period "8" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "counter" sg_icon_stat "60,51,2,1,white,blue,0,ae3608d6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 51 51 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 60 60 0 0 ],[0 0 51 51 0 ]);\npatch([14.425 24.54 31.54 38.54 45.54 31.54 21.425 14.425 ],[32.77 32" ".77 39.77 32.77 39.77 39.77 39.77 32.77 ],[1 1 1 ]);\npatch([21.425 31.54 24.54 14.425 21.425 ],[25.77 25.77 32.77" " 32.77 25.77 ],[0.931 0.946 0.973 ]);\npatch([14.425 24.54 31.54 21.425 14.425 ],[18.77 18.77 25.77 25.77 18.77 ]," "[1 1 1 ]);\npatch([21.425 45.54 38.54 31.54 24.54 14.425 21.425 ],[11.77 11.77 18.77 11.77 18.77 18.77 11.77 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,'rst');\ncolor('black');port_label('input',2,'en');\n\ncolor('black');disp('{\\fontsize" "{14}\\bf++}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Rd Addr" SID "291" Position [1265, 483, 1295, 497] IconDisplay "Port number" } Block { BlockType Outport Name "Reading" SID "292" Position [1195, 773, 1225, 787] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "FFT tvalid" SID "293" Position [1420, 583, 1450, 597] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "FFT tlast" SID "294" Position [1420, 638, 1450, 652] Port "4" IconDisplay "Port number" } Block { BlockType Outport Name "FFT Load Done" SID "295" Position [1420, 738, 1450, 752] Port "5" IconDisplay "Port number" } Line { SrcBlock "Posedge" SrcPort 1 DstBlock "FFT Load Done" DstPort 1 } Line { SrcBlock "data tready" SrcPort 1 DstBlock "Convert2" DstPort 1 } Line { SrcBlock "Wr Addr" SrcPort 1 Points [60, 0] Branch { Labels [0, 0] DstBlock "First Samp\nCalc" DstPort 1 } Branch { Points [0, -30] Branch { Points [565, 0; 0, 125] DstBlock "Relational1" DstPort 1 } Branch { Points [0, -105] DstBlock "Gateway Out2" DstPort 1 } } } Line { SrcBlock "First Samp\nCalc" SrcPort 1 Points [115, 0] Branch { Points [0, 180] DstBlock "Rd Counter" DstPort 2 } Branch { Points [0, -135] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "Rd Counter" SrcPort 1 Points [15, 0] Branch { Points [65, 0] Branch { Points [0, -75] DstBlock "AddSub4" DstPort 2 } Branch { Points [140, 0] Branch { DstBlock "Rd Addr" DstPort 1 } Branch { Points [0, -255] DstBlock "Gateway Out6" DstPort 1 } } } Branch { Points [0, -300] DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "Skip Sel" SrcPort 1 DstBlock "Count-To Calc" DstPort 1 } Line { SrcBlock "Count-To Calc" SrcPort 1 Points [40, 0] Branch { DstBlock "AddSub4" DstPort 1 } Branch { Points [0, 145] DstBlock "Relational3" DstPort 1 } } Line { SrcBlock "AddSub4" SrcPort 1 DstBlock "Relational1" DstPort 2 } Line { SrcBlock "Logical4" SrcPort 1 Points [75, 0] Branch { Points [0, 50] DstBlock "Samp Counter" DstPort 2 } Branch { Points [0, -10] DstBlock "Logical1" DstPort 2 } } Line { SrcBlock "Convert2" SrcPort 1 DstBlock "Logical4" DstPort 1 } Line { SrcBlock "FFT Load" SrcPort 1 DstBlock "Logical" DstPort 1 } Line { SrcBlock "S-R Latch1" SrcPort 1 Points [20, 0; 0, -10] Branch { Points [0, -40] DstBlock "Logical4" DstPort 2 } Branch { Points [205, 0; 0, -40; 355, 0] DstBlock "Logical2" DstPort 1 } } Line { SrcBlock "Relational1" SrcPort 1 Points [20, 0; 0, 300; -1060, 0; 0, -135] DstBlock "Logical" DstPort 2 } Line { SrcBlock "Samp Counter" SrcPort 1 Points [20, 0] Branch { DstBlock "Relational3" DstPort 2 } Branch { Points [0, 45] Branch { DstBlock "Relational4" DstPort 2 } Branch { Points [0, 45] DstBlock "Relational2" DstPort 2 } } Branch { Points [0, -360] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "Relational3" SrcPort 1 Points [30, 0; 0, 135; -245, 0] Branch { Points [0, -140] DstBlock "Samp Counter" DstPort 1 } Branch { Points [0, 55] DstBlock "Posedge" DstPort 1 } Branch { Points [-430, 0; 0, -75] Branch { DstBlock "Inverter" DstPort 1 } Branch { Points [0, -35] DstBlock "S-R Latch1" DstPort 2 } } } Line { SrcBlock "Count-To Calc" SrcPort 2 Points [35, 0; 0, 170] Branch { DstBlock "Relational4" DstPort 1 } Branch { Points [0, 45] DstBlock "Relational2" DstPort 1 } } Line { SrcBlock "Relational4" SrcPort 1 DstBlock "Logical2" DstPort 2 } Line { SrcBlock "Logical2" SrcPort 1 Points [80, 0] Branch { DstBlock "FFT tvalid" DstPort 1 } Branch { Points [0, -370] DstBlock "Gateway Out5" DstPort 1 } } Line { Name "FFT tvalid" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 DstBlock "Ctrl" DstPort 6 } Line { Name "Rd Addr" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 DstBlock "Ctrl" DstPort 7 } Line { Name "LTS Sync" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 DstBlock "Ctrl" DstPort 1 } Line { Name "Rx Samp Ind" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 DstBlock "Ctrl" DstPort 2 } Line { Name "Init Samp Addr" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 DstBlock "Ctrl" DstPort 3 } Line { Name "Rd Counter" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 DstBlock "Ctrl" DstPort 4 } Line { Name "Samp Counter" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 DstBlock "Ctrl" DstPort 5 } Line { SrcBlock "Logical1" SrcPort 1 Points [15, 0] Branch { DstBlock "Rd Counter" DstPort 3 } Branch { Points [0, 270] DstBlock "Reading" DstPort 1 } } Line { SrcBlock "Delay" SrcPort 1 Points [95, 0] Branch { DstBlock "Rd Counter" DstPort 1 } Branch { Points [0, 30] DstBlock "Logical1" DstPort 1 } } Line { SrcBlock "Inverter" SrcPort 1 Points [10, 0; 0, -75] DstBlock "Logical4" DstPort 3 } Line { SrcBlock "LTS Sync" SrcPort 1 Points [30, 0] Branch { DstBlock "First Samp\nCalc" DstPort 2 } Branch { Points [0, 145] DstBlock "Delay" DstPort 1 } Branch { Points [0, -180] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "Relational2" SrcPort 1 DstBlock "FFT tlast" DstPort 1 } Line { SrcBlock "Logical" SrcPort 1 DstBlock "Logical3" DstPort 1 } Line { SrcBlock "Logical3" SrcPort 1 DstBlock "S-R Latch1" DstPort 1 } Line { SrcBlock "FFT LTS Load" SrcPort 1 Points [135, 0] DstBlock "Logical3" DstPort 2 } } } Block { BlockType SubSystem Name "FSM" SID "296" Ports [3, 3] Position [490, 632, 610, 668] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "FSM" Location [311, 989, 1176, 1189] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "FFT Load Done" SID "297" Position [155, 238, 185, 252] IconDisplay "Port number" } Block { BlockType Inport Name "LTS" SID "298" Position [155, 213, 185, 227] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "Pkt Done" SID "299" Position [155, 268, 185, 282] Port "3" IconDisplay "Port number" } Block { BlockType Reference Name "Convert" SID "300" Ports [1, 1] Position [275, 236, 300, 254] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cast');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "301" Ports [1, 1] Position [275, 211, 300, 229] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cast');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "302" Ports [1, 1] Position [275, 266, 300, 284] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cast');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert3" SID "303" Ports [1, 1] Position [675, 211, 700, 229] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cast');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert4" SID "304" Ports [1, 1] Position [675, 236, 700, 254] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cast');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Scope Name "FFT Load FSM" SID "305" Ports [9] Position [1000, 381, 1035, 529] ZOrder -3 Floating off Location [797, 508, 2334, 1506] Open off NumInputPorts "9" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" axes9 "%" } List { ListType ScopeGraphics FigureColor "[0.5 0.5 0.5]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "10000" YMin "-0.25~-0.25~0~0~0~-0.1~-0.1~-5~-5" YMax "0.2~0.2~300~300~4000~1.1~1.1~5~5" SaveName "ScopeData48" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType Reference Name "Gateway Out1" SID "306" Ports [1, 1] Position [875, 419, 910, 431] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Pkt Done" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "307" Ports [1, 1] Position [875, 449, 910, 461] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "FFT Data Load" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "308" Ports [1, 1] Position [875, 464, 910, 476] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "FFT LTS Load" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "309" Ports [1, 1] Position [875, 479, 910, 491] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "FFT skip sel" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "310" Ports [1, 1] Position [875, 404, 910, 416] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "FFT Load Done" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "311" Ports [1, 1] Position [875, 389, 910, 401] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "LTS Sync" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "MCode" SID "312" Ports [3, 3] Position [415, 205, 635, 285] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/MCode" SourceType "Xilinx MCode Block Block" infoedit "Pass input values to a MATLAB function for evaluation in Xilinx fixed-point type. The input ports of " "the block are input arguments of the function. The output ports of the block are output arguments of the function." mfname "rx_fft_ctrl_fsm" explicit_period on period "1" inputsTable "{'boundInpExpr'=>['','',''],'inputs'=>['lts_sync','fft_load_done','pkt_done']}" outputsTable "{'outputs'=>['fft_load','samp_skip_mode'],'suppressOut'=>['off','off']}" dbl_ovrd off enable_stdout off enable_debug off xl_use_area off xl_area "[0,0,0,0,0,0,0]" suppress_output "on" defparams "{}" hide_port_list "{}" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mcode" sg_icon_stat "220,80,3,3,white,blue,0,c9d27118,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 220 220 0 0 ],[0 0 80 80 0 ],[0.77 0.82 0" ".91 ]);\nplot([0 220 220 0 0 ],[0 0 80 80 0 ]);\npatch([85.525 101.42 112.42 123.42 134.42 112.42 96.525 85.525 ]," "[52.21 52.21 63.21 52.21 63.21 63.21 63.21 52.21 ],[1 1 1 ]);\npatch([96.525 112.42 101.42 85.525 96.525 ],[41.21 " "41.21 52.21 52.21 41.21 ],[0.931 0.946 0.973 ]);\npatch([85.525 101.42 112.42 96.525 85.525 ],[30.21 30.21 41.21 4" "1.21 30.21 ],[1 1 1 ]);\npatch([96.525 134.42 123.42 112.42 101.42 85.525 96.525 ],[19.21 19.21 30.21 19.21 30.21 " "30.21 19.21 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon t" "ext');\ncolor('black');port_label('input',1,'lts_sync');\ncolor('black');port_label('input',2,'fft_load_done');\nc" "olor('black');port_label('input',3,'pkt_done');\ncolor('black');port_label('output',1,'fft_load');\ncolor('black')" ";port_label('output',2,'fft_lts_load');\ncolor('black');port_label('output',3,'samp_skip_mode');\ncolor('black');d" "isp('\\bf{rx\\_fft\\_ctrl\\_fsm}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "FFT skip sel" SID "313" Position [775, 263, 805, 277] IconDisplay "Port number" } Block { BlockType Outport Name "FFT LTS load" SID "314" Position [900, 238, 930, 252] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "FFT Data load" SID "315" Position [765, 213, 795, 227] Port "3" IconDisplay "Port number" } Line { SrcBlock "Pkt Done" SrcPort 1 DstBlock "Convert2" DstPort 1 } Line { SrcBlock "Convert1" SrcPort 1 Points [85, 0] Branch { DstBlock "MCode" DstPort 1 } Branch { Points [0, 175] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "MCode" SrcPort 1 DstBlock "Convert3" DstPort 1 } Line { SrcBlock "MCode" SrcPort 2 DstBlock "Convert4" DstPort 1 } Line { SrcBlock "Convert" SrcPort 1 Points [80, 0] Branch { DstBlock "MCode" DstPort 2 } Branch { Points [0, 165] DstBlock "Gateway Out5" DstPort 1 } } Line { SrcBlock "LTS" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "FFT Load Done" SrcPort 1 DstBlock "Convert" DstPort 1 } Line { SrcBlock "Convert2" SrcPort 1 Points [0, -5; 75, 0] Branch { DstBlock "MCode" DstPort 3 } Branch { Points [0, 155] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "MCode" SrcPort 3 Points [85, 0] Branch { DstBlock "FFT skip sel" DstPort 1 } Branch { Points [0, 215] DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "Convert3" SrcPort 1 Points [30, 0] Branch { DstBlock "FFT Data load" DstPort 1 } Branch { Points [0, 235] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "Convert4" SrcPort 1 Points [25, 0] Branch { DstBlock "FFT LTS load" DstPort 1 } Branch { Points [0, 225] DstBlock "Gateway Out3" DstPort 1 } } Line { Name "FFT Load Done" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 DstBlock "FFT Load FSM" DstPort 2 } Line { Name "LTS Sync" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 DstBlock "FFT Load FSM" DstPort 1 } Line { Name "Pkt Done" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 DstBlock "FFT Load FSM" DstPort 3 } Line { Name "FFT Data Load" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 DstBlock "FFT Load FSM" DstPort 5 } Line { Name "FFT LTS Load" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 DstBlock "FFT Load FSM" DstPort 6 } Line { Points [955, 440] DstBlock "FFT Load FSM" DstPort 4 } Line { Name "FFT skip sel" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 DstBlock "FFT Load FSM" DstPort 7 } } } Block { BlockType Reference Name "Gateway Out1" SID "316" Ports [1, 1] Position [1040, 219, 1075, 231] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Rd Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "317" Ports [1, 1] Position [1040, 234, 1075, 246] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Wr Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "318" Ports [1, 1] Position [1040, 249, 1075, 261] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Pkt Det" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "319" Ports [1, 1] Position [1040, 264, 1075, 276] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Pkt Done" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "320" Ports [1, 1] Position [1040, 204, 1075, 216] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "FFT In I" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "321" Ports [1, 1] Position [1040, 189, 1075, 201] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "ADC I" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "322" Ports [1, 1] Position [1040, 279, 1075, 291] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "FFT Load Done" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "323" Ports [1, 1] Position [1040, 294, 1075, 306] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "FFT In tvalid" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out9" SID "11306" Ports [1, 1] Position [1040, 309, 1075, 321] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "DEBUG Payload" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Goto Name "Goto" SID "324" Position [1065, 786, 1290, 804] ZOrder -10 ShowName off GotoTag "OFDM_RX_RUNNING_DSSS_BLOCK" TagVisibility "global" } Block { BlockType Reference Name "Logical2" SID "325" Ports [2, 1] Position [285, 620, 320, 675] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,55,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 55 55 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 55 55 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[32.55" " 32.55 37.55 32.55 37.55 37.55 37.55 32.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[27.55 27.55 32" ".55 32.55 27.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[22.55 22.55 27.55 27.55 22.55 " "],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[17.55 17.55 22.55 17.55 22.55 22.55 17.55 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n" "color('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Posedge" SID "326" Ports [1, 1] Position [360, 638, 415, 662] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Posedge" Location [384, 656, 940, 879] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "327" Position [200, 253, 230, 267] IconDisplay "Port number" } Block { BlockType Reference Name "Delay" SID "328" Ports [1, 1] Position [425, 153, 460, 177] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. If r" "egister retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[15.33 15" ".33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.33 12.33 15.33" " 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 " "1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');" "disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "329" Ports [1, 1] Position [490, 156, 515, 174] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "330" Ports [2, 1] Position [540, 151, 585, 204] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,53,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 53 53 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 53 53 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[32.66 32.66 3" "8.66 32.66 38.66 38.66 38.66 32.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[26.66 26.66 32.66 32.66 26" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[20.66 20.66 26.66 26.66 20.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[14.66 14.66 20.66 14.66 20.66 20.66 14.66 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('" "and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "331" Position [610, 173, 640, 187] IconDisplay "Port number" } Line { SrcBlock "D" SrcPort 1 Points [150, 0; 0, -70] Branch { DstBlock "Logical1" DstPort 2 } Branch { Points [0, -25] DstBlock "Delay" DstPort 1 } } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Delay" SrcPort 1 DstBlock "Inverter" DstPort 1 } Annotation { Name "Rising Edge Detection" Position [500, 112] } } } Block { BlockType SubSystem Name "Posedge3" SID "332" Ports [1, 1] Position [725, 648, 780, 672] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Posedge3" Location [88, 301, 2330, 1301] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "333" Position [200, 253, 230, 267] IconDisplay "Port number" } Block { BlockType Reference Name "Delay" SID "334" Ports [1, 1] Position [425, 153, 460, 177] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. If r" "egister retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[15.33 15" ".33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.33 12.33 15.33" " 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 " "1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');" "disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "335" Ports [1, 1] Position [490, 156, 515, 174] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "336" Ports [2, 1] Position [540, 151, 585, 204] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,53,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 53 53 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 53 53 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[32.66 32.66 3" "8.66 32.66 38.66 38.66 38.66 32.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[26.66 26.66 32.66 32.66 26" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[20.66 20.66 26.66 26.66 20.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[14.66 14.66 20.66 14.66 20.66 20.66 14.66 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('" "and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "337" Position [610, 173, 640, 187] IconDisplay "Port number" } Line { SrcBlock "D" SrcPort 1 Points [150, 0; 0, -70] Branch { DstBlock "Logical1" DstPort 2 } Branch { Points [0, -25] DstBlock "Delay" DstPort 1 } } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Delay" SrcPort 1 DstBlock "Inverter" DstPort 1 } Annotation { Name "Rising Edge Detection" Position [500, 112] } } } Block { BlockType Reference Name "Register" SID "338" Ports [1, 1] Position [930, 657, 965, 683] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 26 26 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ]" ",[16.33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[13.3" "3 13.33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[10.33 10.33 13.3" "3 13.33 10.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[7.33 7.33 10.33 7.33 10.33 1" "0.33 7.33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon " "text');\ncolor('black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');" "disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "339" Ports [1, 1] Position [1000, 657, 1035, 683] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 26 26 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ]" ",[16.33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[13.3" "3 13.33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[10.33 10.33 13.3" "3 13.33 10.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[7.33 7.33 10.33 7.33 10.33 1" "0.33 7.33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon " "text');\ncolor('black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');" "disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "S-R Latch" SID "340" Ports [2, 1] Position [845, 653, 890, 682] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "S-R Latch" Location [-1278, 70, -2, 1004] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "341" Position [140, 103, 170, 117] IconDisplay "Port number" } Block { BlockType Inport Name "R" SID "342" Position [140, 88, 170, 102] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "343" Ports [0, 1] Position [195, 71, 210, 89] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "15,18,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11.22 13.22 " "11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 9.22 ],[0.931" " 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([4.55 11.44 9.44" " 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon" " graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "344" Ports [3, 1] Position [255, 71, 300, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 30.66 3" "6.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 30.66 24" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('" "input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'en');\ncolor('bl" "ack');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon te" "xt');" } Block { BlockType Outport Name "Q" SID "345" Position [325, 88, 355, 102] IconDisplay "Port number" } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "S" SrcPort 1 DstBlock "Register2" DstPort 3 } } } Block { BlockType Scope Name "Scope" SID "346" Ports [9] Position [1170, 181, 1205, 329] ZOrder -3 Floating off Location [5, 40, 1925, 1194] Open off NumInputPorts "9" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" axes9 "%" } List { ListType ScopeGraphics FigureColor "[0.501960784313725 0.501960784313725 0.501960784313725]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[2 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "10000" YMin "-0.4~-0.4~0~0~0~-0.1~-0.1~-5~-5" YMax "0.5~0.4~275~275~4000~1.1~1.1~5~5" SaveName "ScopeData25" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType SubSystem Name "Slice" SID "347" Ports [1, 2] Position [865, 395, 915, 430] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Slice" Location [1155, 565, 1558, 696] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "IQ" SID "348" Position [190, 123, 220, 137] IconDisplay "Port number" } Block { BlockType Reference Name "Reinterpret2" SID "349" Ports [1, 1] Position [350, 119, 390, 141] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can change the signal between s" "igned and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.
Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsig" "ned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111" "000 in binary)." force_arith_type on arith_type "Signed (2's comp)" force_bin_pt on bin_pt "15" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "reinterpret" sg_icon_stat "40,22,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 22 22 0 ]);\npatch([13.325 17.66 20.66 23.66 26.66 20.66 16.325 13.325 ],[14.33 14" ".33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([16.325 20.66 17.66 13.325 16.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([13.325 17.66 20.66 16.325 13.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 " "1 1 ]);\npatch([16.325 26.66 23.66 20.66 17.66 13.325 16.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');" "disp('reinterpret');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Reinterpret3" SID "350" Ports [1, 1] Position [350, 144, 390, 166] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can change the signal between s" "igned and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.
Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsig" "ned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111" "000 in binary)." force_arith_type on arith_type "Signed (2's comp)" force_bin_pt on bin_pt "15" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "reinterpret" sg_icon_stat "40,22,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 22 22 0 ]);\npatch([13.325 17.66 20.66 23.66 26.66 20.66 16.325 13.325 ],[14.33 14" ".33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([16.325 20.66 17.66 13.325 16.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([13.325 17.66 20.66 16.325 13.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 " "1 1 ]);\npatch([16.325 26.66 23.66 20.66 17.66 13.325 16.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');" "disp('reinterpret');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Slice" SID "351" Ports [1, 1] Position [265, 119, 300, 141] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type" " is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardw" "are notes: In hardware this block costs nothing." nbits "16" boolean_output off mode "Upper Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "35,22,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 22 22 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[14.33 14" ".33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 " "1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');po" "rt_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Slice1" SID "352" Ports [1, 1] Position [265, 144, 300, 166] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type" " is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardw" "are notes: In hardware this block costs nothing." nbits "16" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "35,22,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 22 22 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[14.33 14" ".33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 " "1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');po" "rt_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "I" SID "353" Position [450, 123, 480, 137] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Outport Name "Q" SID "354" Position [450, 148, 480, 162] Port "2" IconDisplay "Port number" } Line { SrcBlock "Slice" SrcPort 1 DstBlock "Reinterpret2" DstPort 1 } Line { SrcBlock "Slice1" SrcPort 1 DstBlock "Reinterpret3" DstPort 1 } Line { SrcBlock "IQ" SrcPort 1 Points [15, 0] Branch { Points [0, 25] DstBlock "Slice1" DstPort 1 } Branch { DstBlock "Slice" DstPort 1 } } Line { SrcBlock "Reinterpret2" SrcPort 1 DstBlock "I" DstPort 1 } Line { SrcBlock "Reinterpret3" SrcPort 1 DstBlock "Q" DstPort 1 } } } Block { BlockType Terminator Name "Terminator" SID "355" Position [865, 340, 885, 360] ZOrder -5 ShowName off } Block { BlockType ToWorkspace Name "To Workspace" SID "18120" Ports [1] Position [1170, 657, 1325, 683] ZOrder -7 ShowName off VariableName "rx_sim_phy_active_debug_out" MaxDataPoints "inf" SampleTime "-1" SaveFormat "Array" } Block { BlockType Reference Name "dbg_payload" SID "356" Ports [1, 1] Position [1080, 663, 1120, 677] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "40,14,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9" ".22 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22" " 9.22 7.22 ],[0.985 0.979 0.895 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.985 0.979 0.89" "5 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprin" "tf('','COMMENT: end icon text');" } Block { BlockType Outport Name "I" SID "357" Position [1040, 398, 1070, 412] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Outport Name "Q" SID "358" Position [1040, 413, 1070, 427] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "Buff Rd" SID "359" Position [835, 493, 865, 507] NamePlacement "alternate" Port "3" IconDisplay "Port number" } Block { BlockType Outport Name " IQ valid" SID "360" Position [835, 513, 865, 527] Port "4" IconDisplay "Port number" } Block { BlockType Outport Name "tlast" SID "361" Position [835, 553, 865, 567] Port "5" IconDisplay "Port number" } Line { SrcBlock "Concat" SrcPort 1 DstBlock "Circular Sample\nBuffer" DstPort 2 } Line { SrcBlock "Circular Sample\nBuffer" SrcPort 1 DstBlock "Terminator" DstPort 1 } Line { SrcBlock "FFT Load Ctrl" SrcPort 1 Points [15, 0; 0, -90] Branch { DstBlock "Circular Sample\nBuffer" DstPort 4 } Branch { Points [0, -165] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "Constant3" SrcPort 1 DstBlock "Circular Sample\nBuffer" DstPort 5 } Line { SrcBlock "Constant4" SrcPort 1 DstBlock "Circular Sample\nBuffer" DstPort 6 } Line { SrcBlock "Logical2" SrcPort 1 DstBlock "Posedge" DstPort 1 } Line { SrcBlock "Posedge" SrcPort 1 Points [30, 0] Branch { Points [0, -140] DstBlock "FFT Load Ctrl" DstPort 3 } Branch { Labels [0, 0] DstBlock "FSM" DstPort 2 } } Line { SrcBlock "FFT Load Ctrl" SrcPort 5 Points [20, 0; 0, 45] Branch { Points [-180, 0] DstBlock "FSM" DstPort 1 } Branch { Points [330, 0; 0, -320] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "FSM" SrcPort 3 Points [30, 0; 0, -75; -150, 0; 0, -30] DstBlock "FFT Load Ctrl" DstPort 6 } Line { Labels [0, 0] SrcBlock "Circular Sample\nBuffer" SrcPort 2 DstBlock "Slice" DstPort 1 } Line { SrcBlock "FSM" SrcPort 1 Points [15, 0; 0, -45; -155, 0; 0, -70] DstBlock "FFT Load Ctrl" DstPort 4 } Line { SrcBlock "FFT Load Ctrl" SrcPort 3 Points [55, 0] Branch { DstBlock "Delay" DstPort 1 } Branch { Points [0, 140] DstBlock "Posedge3" DstPort 1 } } Line { SrcBlock "FFT Load Ctrl" SrcPort 2 DstBlock "Delay2" DstPort 1 } Line { SrcBlock "Pkt Done" SrcPort 1 Points [20, 0] Branch { Points [0, 290; -75, 0; 0, 130; 305, 0] Branch { DstBlock "FSM" DstPort 3 } Branch { Points [345, 0; 0, -20] DstBlock "S-R Latch" DstPort 2 } } Branch { Points [0, -100; 685, 0; 0, 95] DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "rx I" SrcPort 1 Points [25, 0] Branch { DstBlock "Concat" DstPort 1 } Branch { Points [0, -145] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "rx Q" SrcPort 1 DstBlock "Concat" DstPort 2 } Line { SrcBlock "IQ valid" SrcPort 1 Points [240, 0] Branch { DstBlock "Circular Sample\nBuffer" DstPort 3 } Branch { Points [0, -75] DstBlock "Counter" DstPort 1 } } Line { SrcBlock "Slice" SrcPort 1 Points [55, 0] Branch { DstBlock "I" DstPort 1 } Branch { Points [0, -195] DstBlock "Gateway Out5" DstPort 1 } } Line { SrcBlock "Slice" SrcPort 2 DstBlock "Q" DstPort 1 } Line { SrcBlock "FIFO tready" SrcPort 1 DstBlock "FFT Load Ctrl" DstPort 2 } Line { SrcBlock "Delay2" SrcPort 1 DstBlock "Buff Rd" DstPort 1 } Line { SrcBlock "Delay" SrcPort 1 Points [50, 0] Branch { DstBlock " IQ valid" DstPort 1 } Branch { Points [0, -50; 210, 0; 0, -170] DstBlock "Gateway Out8" DstPort 1 } } Line { SrcBlock "FFT Load Ctrl" SrcPort 4 Points [140, 0; 0, 20] DstBlock "tlast" DstPort 1 } Line { SrcBlock "LTS Sync 2" SrcPort 1 DstBlock "Logical2" DstPort 1 } Line { SrcBlock "Pkt Det" SrcPort 1 Points [40, 0] Branch { Points [0, 415] DstBlock "Logical2" DstPort 2 } Branch { Points [0, -100; 855, 0; 0, 110] DstBlock "Gateway Out3" DstPort 1 } } Line { Name "FFT In I" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 DstBlock "Scope" DstPort 2 } Line { Name "Rd Addr" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 DstBlock "Scope" DstPort 3 } Line { Name "Wr Addr" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 DstBlock "Scope" DstPort 4 } Line { Name "Pkt Det" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 DstBlock "Scope" DstPort 5 } Line { SrcBlock "Posedge3" SrcPort 1 DstBlock "S-R Latch" DstPort 1 } Line { SrcBlock "S-R Latch" SrcPort 1 Points [5, 0] Branch { Points [5, 0] Branch { DstBlock "Register" DstPort 1 } Branch { Points [0, 125] DstBlock "Goto" DstPort 1 } } Branch { Points [0, -35; 115, 0; 0, -320] DstBlock "Gateway Out9" DstPort 1 } } Line { Name "Pkt Done" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 DstBlock "Scope" DstPort 6 } Line { Name "ADC I" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 DstBlock "Scope" DstPort 1 } Line { SrcBlock "Register" SrcPort 1 DstBlock "Register1" DstPort 1 } Line { SrcBlock "Register1" SrcPort 1 DstBlock "dbg_payload" DstPort 1 } Line { Name "FFT Load Done" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 DstBlock "Scope" DstPort 7 } Line { SrcBlock "Counter" SrcPort 1 Points [35, 0] Branch { Points [245, 0; 0, 35] DstBlock "Circular Sample\nBuffer" DstPort 1 } Branch { Points [0, 185] DstBlock "FFT Load Ctrl" DstPort 1 } Branch { Points [0, -55] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "FSM" SrcPort 2 Points [25, 0; 0, -60; -150, 0; 0, -50] DstBlock "FFT Load Ctrl" DstPort 5 } Line { Name "FFT In tvalid" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 DstBlock "Scope" DstPort 8 } Line { Name "DEBUG Payload" Labels [0, 0] SrcBlock "Gateway Out9" SrcPort 1 DstBlock "Scope" DstPort 9 } Line { SrcBlock "dbg_payload" SrcPort 1 DstBlock "To Workspace" DstPort 1 } Annotation { Name "Circular sample buffer records all incoming I/Q samples post pkt det\nSamples are unloaded from th" "e buffer after LTS sync and fed into\nthe FFT (via CFO correction and a FIFO)\n\nThis buffer is required becaus" "e 802.11 uses the same preamble samples\n(the LTS) for sample-level synchronization and CFO estimation. The \nr" "eceived LTS samples must be saved and CFO-corrected before the\nFFT to avoid degrading the channel estimates." Position [577, 88] HorizontalAlignment "left" } } } Block { BlockType Reference Name "Slice1" SID "362" Ports [1, 1] Position [620, 503, 655, 517] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardwar" "e notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "35,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 14 14 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[9.22 9.22 11." "22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0." "931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([14.55 21" ".44 19.44 17.44 15.44 12.55 14.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a:b]');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Slice2" SID "363" Ports [1, 1] Position [620, 453, 655, 467] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardwar" "e notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Upper Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "35,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 14 14 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[9.22 9.22 11." "22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0." "931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([14.55 21" ".44 19.44 17.44 15.44 12.55 14.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a:b]');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "FFT tdata_im" SID "364" Position [1390, 458, 1420, 472] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Outport Name "FFT tdata_re" SID "365" Position [1390, 408, 1420, 422] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "FFT tvalid" SID "366" Position [1390, 358, 1420, 372] NamePlacement "alternate" Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "FFT tlast" SID "367" Position [1390, 508, 1420, 522] NamePlacement "alternate" Port "4" IconDisplay "Port number" } Line { SrcBlock "Rx Q" SrcPort 1 Points [65, 0] Branch { Points [315, 0] Branch { Points [0, 120] DstBlock "CFO Estimation" DstPort 3 } Branch { DstBlock "Samp Buffer" DstPort 4 } } Branch { Points [0, -215] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "Rx I" SrcPort 1 Points [40, 0] Branch { Points [310, 0] Branch { Labels [0, 0] DstBlock "Samp Buffer" DstPort 3 } Branch { Points [0, 125] DstBlock "CFO Estimation" DstPort 2 } } Branch { Points [0, -210] DstBlock "Gateway Out17" DstPort 1 } } Line { SrcBlock "FFT tready" SrcPort 1 Points [15, 0] Branch { Points [10, 0] DstBlock "FIFO" DstPort 5 } Branch { Points [0, -270] DstBlock "Gateway Out9" DstPort 1 } } Line { SrcBlock "Samp Buffer" SrcPort 1 DstBlock "CFO\nCorrection" DstPort 1 } Line { SrcBlock "Samp Buffer" SrcPort 2 Points [90, 0] DstBlock "CFO\nCorrection" DstPort 2 } Line { SrcBlock "CFO\nCorrection" SrcPort 2 DstBlock "FIFO" DstPort 2 } Line { SrcBlock "CFO\nCorrection" SrcPort 3 Points [160, 0] DstBlock "FIFO" DstPort 3 } Line { SrcBlock "CFO\nCorrection" SrcPort 1 Points [125, 0] Branch { Points [35, 0] DstBlock "FIFO" DstPort 1 } Branch { Points [0, -135] DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "Samp Buffer" SrcPort 5 Points [90, 0] DstBlock "CFO\nCorrection" DstPort 5 } Line { SrcBlock "Samp Buffer" SrcPort 4 Points [90, 0] DstBlock "CFO\nCorrection" DstPort 4 } Line { SrcBlock "FIFO" SrcPort 5 Points [25, 0; 0, 45; -600, 0; 0, -130] DstBlock "Samp Buffer" DstPort 7 } Line { SrcBlock "FIFO" SrcPort 4 Points [40, 0] Branch { DstBlock "FFT tlast" DstPort 1 } Branch { Points [0, -250] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "FIFO" SrcPort 3 DstBlock "FFT tdata_im" DstPort 1 } Line { SrcBlock "FIFO" SrcPort 1 Points [35, 0] Branch { DstBlock "FFT tvalid" DstPort 1 } Branch { Points [0, -115] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "FIFO" SrcPort 2 DstBlock "FFT tdata_re" DstPort 1 } Line { Name "FIFO IN: tlast" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 DstBlock "FFT in FIFO Ctrl" DstPort 1 } Line { Name "FIFO IN: valid" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 DstBlock "FFT in FIFO Ctrl" DstPort 2 } Line { SrcBlock "IQ Valid" SrcPort 1 Points [95, 0] Branch { Points [320, 0] Branch { Points [0, 115] DstBlock "CFO Estimation" DstPort 4 } Branch { Labels [0, 0] DstBlock "Samp Buffer" DstPort 5 } } Branch { Points [0, -220] DstBlock "Gateway Out5" DstPort 1 } } Line { SrcBlock "Slice1" SrcPort 1 DstBlock "CFO Estimation" DstPort 1 } Line { SrcBlock "Slice2" SrcPort 1 DstBlock "Samp Buffer" DstPort 6 } Line { Name "ADC I" Labels [0, 0] SrcBlock "Gateway Out17" SrcPort 1 DstBlock "ADC/Corr" DstPort 1 } Line { Name "ADC Q" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 DstBlock "ADC/Corr" DstPort 2 } Line { Name "ADC Valid" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 DstBlock "ADC/Corr" DstPort 3 } Line { SrcBlock "Samp Buffer" SrcPort 3 Points [90, 0] DstBlock "CFO\nCorrection" DstPort 3 } Line { SrcBlock "CFO\nCorrection" SrcPort 4 Points [120, 0] Branch { Points [40, 0] DstBlock "FIFO" DstPort 4 } Branch { Labels [1, 0] Points [0, -285] DstBlock "Gateway Out3" DstPort 1 } } Line { Name "FIFO Out: valid" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 DstBlock "FFT in FIFO Ctrl" DstPort 3 } Line { Name "FIFO Out: tlast" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 DstBlock "FFT in FIFO Ctrl" DstPort 4 } Line { Name "FFT in: tready" Labels [0, 0] SrcBlock "Gateway Out9" SrcPort 1 DstBlock "FFT in FIFO Ctrl" DstPort 5 } Line { Name "Pkt Det" Labels [0, 0] SrcBlock "Gateway Out10" SrcPort 1 DstBlock "ADC/Corr" DstPort 4 } Line { SrcBlock "CFO Estimation" SrcPort 1 Points [60, 0; 0, -55] DstBlock "CFO\nCorrection" DstPort 6 } Line { SrcBlock "LTS Sync" SrcPort 1 Points [175, 0] Branch { Points [0, -50] DstBlock "Slice2" DstPort 1 } Branch { DstBlock "Slice1" DstPort 1 } } Line { SrcBlock "Pkt Det" SrcPort 1 Points [125, 0] Branch { DstBlock "Samp Buffer" DstPort 1 } Branch { Points [0, -125] DstBlock "Gateway Out10" DstPort 1 } } Line { SrcBlock "Reset" SrcPort 1 Points [135, 0; 0, 0] Branch { Points [0, 0] Branch { Points [0, -190] DstBlock "Samp Buffer" DstPort 2 } Branch { DstBlock "CFO Estimation" DstPort 5 } } Branch { Points [0, 80; 350, 0] Branch { Points [445, 0] DstBlock "Gateway Out6" DstPort 1 } Branch { Points [0, -140] DstBlock "CFO\nCorrection" DstPort 7 } } } Line { Name "Reset" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 DstBlock "FFT in FIFO Ctrl" DstPort 7 } Annotation { Name "FIXME:\n-DDS runs 1 extra cycle during LTS; it's right for post-LTS FFT inputs\n(still true?)" Position [592, 750] HorizontalAlignment "left" } } } Block { BlockType SubSystem Name "Chan Est & EQ" SID "368" Ports [5, 5] Position [760, 156, 845, 244] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Chan Est & EQ" Location [862, 511, 1417, 681] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "124" Block { BlockType Inport Name "Rx I" SID "369" Position [230, 253, 260, 267] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "Rx Q" SID "370" Position [230, 293, 260, 307] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "iq_valid " SID "372" Position [230, 373, 260, 387] NamePlacement "alternate" Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "sc_ind" SID "371" Position [230, 333, 260, 347] NamePlacement "alternate" Port "4" IconDisplay "Port number" } Block { BlockType Inport Name "sym_ind" SID "373" Position [230, 413, 260, 427] NamePlacement "alternate" Port "5" IconDisplay "Port number" } Block { BlockType SubSystem Name "Chan Est" SID "374" Ports [5, 7] Position [320, 239, 395, 441] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Chan Est" Location [2, 74, 2464, 1576] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "121" Block { BlockType Inport Name "x_re" SID "375" Position [300, 28, 330, 42] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "x_im" SID "376" Position [300, 63, 330, 77] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "x_ind" SID "377" Position [440, 368, 470, 382] NamePlacement "alternate" Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "x_valid" SID "378" Position [135, 203, 165, 217] NamePlacement "alternate" Port "4" IconDisplay "Port number" } Block { BlockType Inport Name "Sym Ind" SID "379" Position [135, 263, 165, 277] Port "5" IconDisplay "Port number" } Block { BlockType Abs Name "Abs" SID "380" Position [1140, 731, 1160, 749] ZOrder -1 ShowName off SaturateOnIntegerOverflow off } Block { BlockType Abs Name "Abs1" SID "381" Position [1140, 706, 1160, 724] ZOrder -1 ShowName off SaturateOnIntegerOverflow off } Block { BlockType SubSystem Name "Chan Est Offload" SID "382" Ports [5] Position [1070, 303, 1150, 367] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Chan Est Offload" Location [1302, 750, 1870, 979] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "125" Block { BlockType Inport Name "x_ind" SID "383" Position [320, 228, 350, 242] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "x_I" SID "384" Position [320, 258, 350, 272] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "x_Q" SID "385" Position [320, 273, 350, 287] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "x_valid" SID "386" Position [320, 333, 350, 347] Port "4" IconDisplay "Port number" } Block { BlockType Inport Name "sym_ind" SID "387" Position [320, 388, 350, 402] Port "5" IconDisplay "Port number" } Block { BlockType Reference Name "Concat" SID "388" Ports [2, 1] Position [685, 255, 730, 290] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point at z" "ero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "45,35,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 35 35 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 35 35 0 ]);\npatch([10.875 18.1 23.1 28.1 33.1 23.1 15.875 10.875 ],[22.55 22.55 2" "7.55 22.55 27.55 27.55 27.55 22.55 ],[1 1 1 ]);\npatch([15.875 23.1 18.1 10.875 15.875 ],[17.55 17.55 22.55 22.55 " "17.55 ],[0.931 0.946 0.973 ]);\npatch([10.875 18.1 23.1 15.875 10.875 ],[12.55 12.55 17.55 17.55 12.55 ],[1 1 1 ])" ";\npatch([15.875 33.1 28.1 23.1 18.1 10.875 15.875 ],[7.55 7.55 12.55 7.55 12.55 12.55 7.55 ],[0.931 0.946 0.973 ]" ");\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label(" "'input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fontsize{20}\\}','texmode'," "'on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant1" SID "389" Ports [0, 1] Position [475, 445, 495, 465] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "7" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "8" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "20,20,0,1,white,blue,0,2a6960a5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 20 20 0 0 ],[0 0 20 20 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[12.22 12.22 14." "22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[10.22 10.22 12.22 12.22 10.22 ]" ",[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatch([7.55 " "14.44 12.44 10.44 8.44 5.55 7.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'7');\nfpr" "intf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant3" SID "390" Ports [0, 1] Position [535, 365, 555, 385] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "2" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "8" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "20,20,0,1,white,blue,0,fca86624,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 20 20 0 0 ],[0 0 20 20 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[12.22 12.22 14." "22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[10.22 10.22 12.22 12.22 10.22 ]" ",[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatch([7.55 " "14.44 12.44 10.44 8.44 5.55 7.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'2');\nfpr" "intf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "391" Ports [1, 1] Position [510, 257, 540, 273] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "16" bin_pt "15" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "30,16,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 16 16 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 16 16 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[10.22 10.22" " 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[8.22 8.22 10.22 10.22 8" ".22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatch" "([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output'" ",1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "392" Ports [1, 1] Position [510, 272, 540, 288] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "16" bin_pt "15" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "30,16,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 16 16 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 16 16 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[10.22 10.22" " 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[8.22 8.22 10.22 10.22 8" ".22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatch" "([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output'" ",1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From1" SID "393" Position [320, 473, 485, 497] ZOrder -9 ShowName off GotoTag "RX_PHY_MODE_11N" TagVisibility "global" } Block { BlockType Goto Name "Goto" SID "394" Position [845, 365, 995, 385] ZOrder -10 ShowName off GotoTag "CHAN_EST_VALID" TagVisibility "global" } Block { BlockType Goto Name "Goto1" SID "395" Position [820, 265, 970, 285] ZOrder -10 ShowName off GotoTag "CHAN_EST_IQ_32b" TagVisibility "global" } Block { BlockType Goto Name "Goto2" SID "396" Position [820, 225, 970, 245] ZOrder -10 ShowName off GotoTag "CHAN_EST_IND" TagVisibility "global" } Block { BlockType Reference Name "Logical1" SID "397" Ports [2, 1] Position [675, 363, 705, 447] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "30,84,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 84 84 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 84 84 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[46.44 46.44 50.4" "4 46.44 50.44 50.44 50.44 46.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[42.44 42.44 46.44 46.44 42.44 ]," "[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[38.44 38.44 42.44 42.44 38.44 ],[1 1 1 ]);\npatch([10.1" " 23.88 19.88 15.88 11.88 6.1 10.1 ],[34.44 34.44 38.44 34.44 38.44 38.44 34.44 ],[0.931 0.946 0.973 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('or');\nfprin" "tf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical3" SID "398" Ports [2, 1] Position [745, 309, 775, 436] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "30,127,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 127 127 0 ],[0.77 0.82 0" ".91 ]);\nplot([0 30 30 0 0 ],[0 0 127 127 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[67.44 67.44 " "71.44 67.44 71.44 71.44 71.44 67.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[63.44 63.44 67.44 67.44 63.4" "4 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[59.44 59.44 63.44 63.44 59.44 ],[1 1 1 ]);\npatch([" "10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[55.44 55.44 59.44 55.44 59.44 59.44 55.44 ],[0.931 0.946 0.973 ]);\nfprin" "tf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('and');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical4" SID "399" Ports [2, 1] Position [605, 423, 635, 507] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "30,84,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 84 84 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 84 84 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[46.44 46.44 50.4" "4 46.44 50.44 50.44 50.44 46.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[42.44 42.44 46.44 46.44 42.44 ]," "[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[38.44 38.44 42.44 42.44 38.44 ],[1 1 1 ]);\npatch([10.1" " 23.88 19.88 15.88 11.88 6.1 10.1 ],[34.44 34.44 38.44 34.44 38.44 38.44 34.44 ],[0.931 0.946 0.973 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('and');\nfpri" "ntf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register" SID "9925" Ports [1, 1] Position [415, 222, 445, 248] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[16.33 16.3" "3 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 13.33 16.33 16" ".33 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 " "1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port" "_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "9926" Ports [1, 1] Position [415, 252, 445, 278] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[16.33 16.3" "3 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 13.33 16.33 16" ".33 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 " "1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port" "_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "9927" Ports [1, 1] Position [415, 267, 445, 293] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[16.33 16.3" "3 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 13.33 16.33 16" ".33 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 " "1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port" "_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register3" SID "9928" Ports [1, 1] Position [415, 327, 445, 353] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[16.33 16.3" "3 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 13.33 16.33 16" ".33 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 " "1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port" "_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register4" SID "9929" Ports [1, 1] Position [415, 382, 445, 408] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[16.33 16.3" "3 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 13.33 16.33 16" ".33 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 " "1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port" "_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Reinterpret" SID "400" Ports [1, 1] Position [600, 257, 635, 273] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can change the signal between s" "igned and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.
Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsig" "ned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111" "000 in binary)." force_arith_type on arith_type "Unsigned" force_bin_pt on bin_pt "0" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "reinterpret" sg_icon_stat "35,16,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 16 16 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 16 16 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[10.22 10.22" " 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[8.22 8.22 10.22 10.22 8" ".22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatch" "([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('reinterpret" "');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Reinterpret1" SID "401" Ports [1, 1] Position [600, 272, 635, 288] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can change the signal between s" "igned and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.
Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsig" "ned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111" "000 in binary)." force_arith_type on arith_type "Unsigned" force_bin_pt on bin_pt "0" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "reinterpret" sg_icon_stat "35,16,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 16 16 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 16 16 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[10.22 10.22" " 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[8.22 8.22 10.22 10.22 8" ".22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatch" "([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('reinterpret" "');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational1" SID "402" Ports [2, 1] Position [535, 424, 580, 466] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "45,42,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 42 42 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 42 42 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[27.66 27.66 3" "3.66 27.66 33.66 33.66 33.66 27.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[21.66 21.66 27.66 27.66 21" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[15.66 15.66 21.66 21.66 15.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[9.66 9.66 15.66 9.66 15.66 15.66 9.66 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('inpu" "t',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa = b','texmode'," "'on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational3" SID "403" Ports [2, 1] Position [600, 364, 645, 406] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "45,42,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 42 42 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 42 42 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[27.66 27.66 3" "3.66 27.66 33.66 33.66 33.66 27.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[21.66 21.66 27.66 27.66 21" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[15.66 15.66 21.66 21.66 15.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[9.66 9.66 15.66 9.66 15.66 15.66 9.66 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('inpu" "t',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa = b','texmode'," "'on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Line { SrcBlock "x_ind" SrcPort 1 DstBlock "Register" DstPort 1 } Line { SrcBlock "x_I" SrcPort 1 DstBlock "Register1" DstPort 1 } Line { SrcBlock "x_Q" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "x_valid" SrcPort 1 DstBlock "Register3" DstPort 1 } Line { SrcBlock "sym_ind" SrcPort 1 DstBlock "Register4" DstPort 1 } Line { SrcBlock "Convert2" SrcPort 1 DstBlock "Reinterpret1" DstPort 1 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Reinterpret" DstPort 1 } Line { SrcBlock "Logical3" SrcPort 1 DstBlock "Goto" DstPort 1 } Line { SrcBlock "Constant3" SrcPort 1 DstBlock "Relational3" DstPort 1 } Line { SrcBlock "Reinterpret1" SrcPort 1 DstBlock "Concat" DstPort 2 } Line { SrcBlock "Reinterpret" SrcPort 1 DstBlock "Concat" DstPort 1 } Line { SrcBlock "Concat" SrcPort 1 DstBlock "Goto1" DstPort 1 } Line { SrcBlock "Relational3" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Logical3" DstPort 2 } Line { SrcBlock "Logical4" SrcPort 1 Points [10, 0; 0, -40] DstBlock "Logical1" DstPort 2 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Relational1" DstPort 2 } Line { SrcBlock "Relational1" SrcPort 1 DstBlock "Logical4" DstPort 1 } Line { SrcBlock "From1" SrcPort 1 DstBlock "Logical4" DstPort 2 } Line { SrcBlock "Register" SrcPort 1 DstBlock "Goto2" DstPort 1 } Line { SrcBlock "Register1" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Convert2" DstPort 1 } Line { SrcBlock "Register3" SrcPort 1 DstBlock "Logical3" DstPort 1 } Line { SrcBlock "Register4" SrcPort 1 Points [45, 0] Branch { DstBlock "Relational3" DstPort 2 } Branch { Points [0, 40] DstBlock "Relational1" DstPort 1 } } Annotation { Name "These signals route to the packet buffer interface. The\nchan ests are written to dedicated bytes in eac" "h packet\nbuffer, ahead of the packet payload. This is way\nbetter than using a Sysgen shared memory block here\ns" "ince it allows CPU High to treat the H ests as meta data\nalongside the packet contents, with no further\ninvolvem" "ent from the PHY or CPU Low.\n\nEstimates are written to the pkt buf after all training is \ncomplete. Training fr" "om the L-LTF are written in OFDM\nsymbol 2 (SIGNAL). For 11n Rx the estimates are over-\nwritten during sybmol 7 (" "first DATA). This assumes 1\nspatial stream.\n\nThe timing of CHAN_EST_VALID is critical. This signal \nbecomes th" "e write enable on the pkt buf BRAM interface.\nThe CHAN_EST_VALID signal must *not* assert when actual\nbytes are " "being written to the pkt buf. Asserting on OFDM syms\n2 and 7 is safe- there cannot be any decoded bits at these s" "ymbol\nintervals. Any changes to pkt buf or decoder timing must be\nchecked for conflicts in BRAM write enable ass" "ertion between\nchan ests and decoded bytes!" Position [726, 600] HorizontalAlignment "left" } } } Block { BlockType Reference Name "Constant" SID "9605" Ports [0, 1] Position [1275, 327, 1330, 353] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0.4625" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "19" bin_pt "17" preci_type "Single" exp_width "8" frac_width "24" explicit_period on period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "55,26,0,1,white,blue,0,8a69a89d,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\npatch([20.325 24.66 27.66 30.66 33.66 27.66 23.325 20.325 ]" ",[16.33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([23.325 27.66 24.66 20.325 23.325 ],[13.3" "3 13.33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([20.325 24.66 27.66 23.325 20.325 ],[10.33 10.33 13.3" "3 13.33 10.33 ],[1 1 1 ]);\npatch([23.325 33.66 30.66 27.66 24.66 20.325 23.325 ],[7.33 7.33 10.33 7.33 10.33 1" "0.33 7.33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon " "text');\ncolor('black');port_label('output',1,'0.46250152587890625');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant1" SID "9606" Ports [0, 1] Position [1275, 432, 1330, 458] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "19" bin_pt "17" preci_type "Single" exp_width "8" frac_width "24" explicit_period on period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "55,26,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\npatch([20.325 24.66 27.66 30.66 33.66 27.66 23.325 20.325 ]" ",[16.33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([23.325 27.66 24.66 20.325 23.325 ],[13.3" "3 13.33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([20.325 24.66 27.66 23.325 20.325 ],[10.33 10.33 13.3" "3 13.33 10.33 ],[1 1 1 ]);\npatch([23.325 33.66 30.66 27.66 24.66 20.325 23.325 ],[7.33 7.33 10.33 7.33 10.33 1" "0.33 7.33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon " "text');\ncolor('black');port_label('output',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Control" SID "404" Ports [1, 4] Position [250, 215, 355, 320] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Control" Location [317, 558, 610, 737] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "125" Block { BlockType Inport Name "Sym Ind" SID "405" Position [210, 68, 240, 82] IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "406" Ports [0, 1] Position [295, 107, 330, 133] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "2" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "8" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "35,26,0,1,white,blue,0,fca86624,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 26 26 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[16.33 16" ".33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[13.33 13.33 16.33" " 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[10.33 10.33 13.33 13.33 10.33 ]," "[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('output',1,'2');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant2" SID "407" Ports [0, 1] Position [295, 42, 330, 68] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "8" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "35,26,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 26 26 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[16.33 16" ".33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[13.33 13.33 16.33" " 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[10.33 10.33 13.33 13.33 10.33 ]," "[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('output',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant3" SID "408" Ports [0, 1] Position [295, 412, 330, 438] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "5" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "8" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "35,26,0,1,white,blue,0,98872051,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 26 26 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[16.33 16" ".33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[13.33 13.33 16.33" " 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[10.33 10.33 13.33 13.33 10.33 ]," "[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('output',1,'5');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant4" SID "409" Ports [0, 1] Position [295, 257, 330, 283] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "6" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "8" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "35,26,0,1,white,blue,0,f0403ad7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 26 26 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[16.33 16" ".33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[13.33 13.33 16.33" " 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[10.33 10.33 13.33 13.33 10.33 ]," "[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('output',1,'6');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "410" Position [75, 298, 240, 322] ZOrder -9 ShowName off GotoTag "RX_PHY_MODE_11N_AC" TagVisibility "global" } Block { BlockType Reference Name "Logical1" SID "411" Ports [2, 1] Position [580, 329, 620, 371] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,42,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 42 42 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 42 42 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[26.55 26.55 31." "55 26.55 31.55 31.55 31.55 26.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[21.55 21.55 26.55 26.55 21." "55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[16.55 16.55 21.55 21.55 16.55 ],[1 1 1 ]);\npa" "tch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[11.55 11.55 16.55 11.55 16.55 16.55 11.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('a" "nd');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "412" Ports [2, 1] Position [690, 54, 730, 96] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,42,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 42 42 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 42 42 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[26.55 26.55 31." "55 26.55 31.55 31.55 31.55 26.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[21.55 21.55 26.55 26.55 21." "55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[16.55 16.55 21.55 21.55 16.55 ],[1 1 1 ]);\npa" "tch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[11.55 11.55 16.55 11.55 16.55 16.55 11.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('o" "r');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical3" SID "413" Ports [2, 1] Position [690, 99, 730, 141] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,42,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 42 42 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 42 42 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[26.55 26.55 31." "55 26.55 31.55 31.55 31.55 26.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[21.55 21.55 26.55 26.55 21." "55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[16.55 16.55 21.55 21.55 16.55 ],[1 1 1 ]);\npa" "tch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[11.55 11.55 16.55 11.55 16.55 16.55 11.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('o" "r');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical4" SID "414" Ports [2, 1] Position [580, 249, 620, 291] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,42,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 42 42 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 42 42 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[26.55 26.55 31." "55 26.55 31.55 31.55 31.55 26.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[21.55 21.55 26.55 26.55 21." "55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[16.55 16.55 21.55 21.55 16.55 ],[1 1 1 ]);\npa" "tch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[11.55 11.55 16.55 11.55 16.55 16.55 11.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('a" "nd');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical5" SID "415" Ports [2, 1] Position [495, 392, 525, 483] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "30,91,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 91 91 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 91 91 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[49.44 49.44 53.4" "4 49.44 53.44 53.44 53.44 49.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[45.44 45.44 49.44 49.44 45.44 ]," "[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[41.44 41.44 45.44 45.44 41.44 ],[1 1 1 ]);\npatch([10.1" " 23.88 19.88 15.88 11.88 6.1 10.1 ],[37.44 37.44 41.44 37.44 41.44 41.44 37.44 ],[0.931 0.946 0.973 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('or');\nfprin" "tf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical6" SID "416" Ports [2, 1] Position [580, 409, 620, 451] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,42,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 42 42 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 42 42 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[26.55 26.55 31." "55 26.55 31.55 31.55 31.55 26.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[21.55 21.55 26.55 26.55 21." "55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[16.55 16.55 21.55 21.55 16.55 ],[1 1 1 ]);\npa" "tch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[11.55 11.55 16.55 11.55 16.55 16.55 11.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('a" "nd');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical7" SID "417" Ports [2, 1] Position [675, 399, 715, 441] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,42,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 42 42 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 42 42 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[26.55 26.55 31." "55 26.55 31.55 31.55 31.55 26.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[21.55 21.55 26.55 26.55 21." "55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[16.55 16.55 21.55 21.55 16.55 ],[1 1 1 ]);\npa" "tch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[11.55 11.55 16.55 11.55 16.55 16.55 11.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('o" "r');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational1" SID "418" Ports [2, 1] Position [410, 89, 455, 131] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "45,42,2,1,white,blue,0,6218dc92,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 42 42 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 42 42 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[27.66 27.66 3" "3.66 27.66 33.66 33.66 33.66 27.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[21.66 21.66 27.66 27.66 21" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[15.66 15.66 21.66 21.66 15.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[9.66 9.66 15.66 9.66 15.66 15.66 9.66 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('inpu" "t',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa \\geq b','texmo" "de','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational4" SID "421" Ports [2, 1] Position [410, 239, 455, 281] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "45,42,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 42 42 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 42 42 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[27.66 27.66 3" "3.66 27.66 33.66 33.66 33.66 27.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[21.66 21.66 27.66 27.66 21" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[15.66 15.66 21.66 21.66 15.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[9.66 9.66 15.66 9.66 15.66 15.66 9.66 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('inpu" "t',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa = b','texmode'," "'on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational5" SID "422" Ports [2, 1] Position [410, 439, 455, 481] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "45,42,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 42 42 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 42 42 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[27.66 27.66 3" "3.66 27.66 33.66 33.66 33.66 27.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[21.66 21.66 27.66 27.66 21" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[15.66 15.66 21.66 21.66 15.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[9.66 9.66 15.66 9.66 15.66 15.66 9.66 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('inpu" "t',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa = b','texmode'," "'on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational6" SID "423" Ports [2, 1] Position [410, 394, 455, 436] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "45,42,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 42 42 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 42 42 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[27.66 27.66 3" "3.66 27.66 33.66 33.66 33.66 27.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[21.66 21.66 27.66 27.66 21" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[15.66 15.66 21.66 21.66 15.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[9.66 9.66 15.66 9.66 15.66 15.66 9.66 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('inpu" "t',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa = b','texmode'," "'on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Est WrEn" SID "425" Position [800, 113, 830, 127] IconDisplay "Port number" } Block { BlockType Outport Name "Est Overwrite" SID "424" Position [800, 68, 830, 82] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "Scale" SID "426" Position [800, 343, 830, 357] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "Sym Invalid" SID "427" Position [800, 413, 830, 427] Port "4" IconDisplay "Port number" } Line { SrcBlock "Constant2" SrcPort 1 DstBlock "Relational2" DstPort 1 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Relational1" DstPort 2 } Line { SrcBlock "Sym Ind" SrcPort 1 Points [130, 0] Branch { DstBlock "Relational2" DstPort 2 } Branch { Points [0, 25] Branch { DstBlock "Relational1" DstPort 1 } Branch { Points [0, 150] Branch { DstBlock "Relational4" DstPort 1 } Branch { Points [0, 80] Branch { DstBlock "Relational3" DstPort 1 } Branch { Points [0, 75] Branch { Points [0, 45] DstBlock "Relational5" DstPort 1 } Branch { DstBlock "Relational6" DstPort 1 } } } } } } Line { SrcBlock "Relational2" SrcPort 1 DstBlock "Logical2" DstPort 1 } Line { SrcBlock "Relational1" SrcPort 1 Points [190, 0] Branch { DstBlock "Logical3" DstPort 1 } Branch { Points [0, 300] DstBlock "Logical7" DstPort 1 } } Line { SrcBlock "Logical2" SrcPort 1 DstBlock "Est Overwrite" DstPort 1 } Line { SrcBlock "Logical4" SrcPort 1 Points [20, 0; 0, -140] Branch { DstBlock "Logical3" DstPort 2 } Branch { Points [0, -45] DstBlock "Logical2" DstPort 2 } } Line { SrcBlock "Logical3" SrcPort 1 DstBlock "Est WrEn" DstPort 1 } Line { SrcBlock "Relational4" SrcPort 1 DstBlock "Logical4" DstPort 1 } Line { SrcBlock "Constant4" SrcPort 1 Points [35, 0] Branch { DstBlock "Relational4" DstPort 2 } Branch { Points [0, 80] Branch { DstBlock "Relational3" DstPort 2 } Branch { Points [0, 120] DstBlock "Relational5" DstPort 2 } } } Line { SrcBlock "From" SrcPort 1 Points [310, 0] Branch { Points [0, -30] DstBlock "Logical4" DstPort 2 } Branch { Points [0, 50] Branch { DstBlock "Logical1" DstPort 2 } Branch { Points [0, 60] DstBlock "Logical6" DstPort 1 } } } Line { SrcBlock "Relational3" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Scale" DstPort 1 } Line { SrcBlock "Constant3" SrcPort 1 DstBlock "Relational6" DstPort 2 } Line { SrcBlock "Relational6" SrcPort 1 DstBlock "Logical5" DstPort 1 } Line { SrcBlock "Relational5" SrcPort 1 DstBlock "Logical5" DstPort 2 } Line { SrcBlock "Logical5" SrcPort 1 DstBlock "Logical6" DstPort 2 } Line { SrcBlock "Logical7" SrcPort 1 DstBlock "Sym Invalid" DstPort 1 } Line { SrcBlock "Logical6" SrcPort 1 DstBlock "Logical7" DstPort 2 } Annotation { Name "OFDM Symbols in 11a/g:\n0: LTF (BPSK)\n1: LTF (BPSK)\n2: SIG (BPSK)\n3-N: Data" Position [144, 588] HorizontalAlignment "left" } Annotation { Name "OFDM Symbols in 11n SISO:\n0: L-LTF (BPSK)\n1: L-LTF (BPSK)\n2: L-SIG (BPSK)\n3: HT-SIG1 (QBPSK)\n4: HT-" "SIG2 (QBPSK)\n5: HT-STF\n6: HT-LFT1\n7-N: Data" Position [294, 613] HorizontalAlignment "left" } Annotation { Name "OFDM Symbols in 11ac SISO:\n0: L-LTF (BPSK)\n1: L-LTF (BPSK)\n2: L-SIG (BPSK)\n3: VHT-SIGA1 (BPSK)\n4: V" "HT-SIGA2 (QBPSK)\n5: VHT-STF\n6: VHT-LFT1\n7: VHT-SIGB\n8-N: Data" Position [469, 628] HorizontalAlignment "left" } Annotation { Name "Downstream blocks should ignore Rx I/Q and H_est I/Q\nduring all training symbols in all PHY modes" Position [987, 424] } } } Block { BlockType Reference Name "Delay1" SID "9950" Ports [1, 1] Position [810, 436, 830, 454] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "6" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "20,18,1,1,white,blue,0,aa5bc30d,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 20 20 0 0 ],[0 0 18 18 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[9.22 9.22 11.22 11" ".22 9.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\np" "atch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfpr" "intf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-6" "}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay2" SID "9951" Ports [1, 1] Position [810, 486, 830, 504] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "6" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "20,18,1,1,white,blue,0,aa5bc30d,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 20 20 0 0 ],[0 0 18 18 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[9.22 9.22 11.22 11" ".22 9.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\np" "atch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfpr" "intf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-6" "}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay3" SID "9952" Ports [1, 1] Position [810, 26, 830, 44] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "6" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "20,18,1,1,white,blue,0,aa5bc30d,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 20 20 0 0 ],[0 0 18 18 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[9.22 9.22 11.22 11" ".22 9.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\np" "atch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfpr" "intf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-6" "}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay4" SID "9953" Ports [1, 1] Position [810, 61, 830, 79] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "6" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "20,18,1,1,white,blue,0,aa5bc30d,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 20 20 0 0 ],[0 0 18 18 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[9.22 9.22 11.22 11" ".22 9.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\np" "atch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfpr" "intf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-6" "}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay5" SID "9753" Ports [1, 1] Position [810, 366, 830, 384] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "6" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "20,18,1,1,white,blue,0,aa5bc30d,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 20 20 0 0 ],[0 0 18 18 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[9.22 9.22 11.22 11" ".22 9.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\np" "atch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfpr" "intf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-6" "}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Estimate Buffers" SID "441" Ports [7, 2] Position [740, 135, 850, 325] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Estimate Buffers" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "x_I" SID "442" Position [145, 218, 175, 232] IconDisplay "Port number" } Block { BlockType Inport Name "x_Q" SID "9824" Position [145, 588, 175, 602] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "Empty Sc" SID "9669" Position [145, 438, 175, 452] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "Est_WE" SID "444" Position [145, 278, 175, 292] Port "4" IconDisplay "Port number" } Block { BlockType Inport Name "First Sym" SID "445" Position [145, 358, 175, 372] Port "5" IconDisplay "Port number" } Block { BlockType Inport Name "Scale" SID "446" Position [810, 218, 840, 232] Port "6" IconDisplay "Port number" } Block { BlockType Inport Name "Est_Addr" SID "443" Position [145, 313, 175, 327] Port "7" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub1" SID "9830" Ports [2, 1] Position [390, 563, 435, 607] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Signed (2's comp)" n_bits "18" bin_pt "15" quantization "Truncate" overflow "Flag as error" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" use_rpm "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,2,1,white,blue,0,e139daf6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 28.66 3" "4.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 28.66 22" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('" "input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bf{a + b}','tex" "mode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub2" SID "447" Ports [2, 1] Position [405, 193, 450, 237] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Signed (2's comp)" n_bits "18" bin_pt "15" quantization "Truncate" overflow "Flag as error" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" use_rpm "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,2,1,white,blue,0,e139daf6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 28.66 3" "4.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 28.66 22" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('" "input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bf{a + b}','tex" "mode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant\nRead State" SID "448" Ports [0, 1] Position [415, 338, 435, 352] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "20,14,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 20 20 0 0 ],[0 0 14 14 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[9.22 9.22 11.22" " 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0.931 0" ".946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([7.55 14.44 12.44" " 10.44 8.44 5.55 7.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end ico" "n graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'0');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Reference Name "Constant\nRead State1" SID "9831" Ports [0, 1] Position [400, 708, 420, 722] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "20,14,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 20 20 0 0 ],[0 0 14 14 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[9.22 9.22 11.22" " 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0.931 0" ".946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([7.55 14.44 12.44" " 10.44 8.44 5.55 7.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end ico" "n graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'0');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Reference Name "Constant1" SID "9832" Ports [0, 1] Position [400, 688, 420, 702] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "18" bin_pt "15" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "20,14,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 20 20 0 0 ],[0 0 14 14 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[9.22 9.22 11.22" " 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0.931 0" ".946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([7.55 14.44 12.44" " 10.44 8.44 5.55 7.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end ico" "n graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'0');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Reference Name "Constant4" SID "449" Ports [0, 1] Position [415, 318, 435, 332] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "18" bin_pt "15" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "20,14,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 20 20 0 0 ],[0 0 14 14 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[9.22 9.22 11.22" " 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0.931 0" ".946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([7.55 14.44 12.44" " 10.44 8.44 5.55 7.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end ico" "n graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'0');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "450" Ports [1, 1] Position [510, 155, 555, 185] BlockMirror on ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "18" bin_pt "15" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Flag as error" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,30,1,1,white,blue,0,edca21da,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\npatch([13.1 18.88 22.88 26.88 30.88 22.88 17.1 13.1 ],[19.44 19.44 23" ".44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([17.1 22.88 18.88 13.1 17.1 ],[15.44 15.44 19.44 19.44 15.44" " ],[0.931 0.946 0.973 ]);\npatch([13.1 18.88 22.88 17.1 13.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch(" "[17.1 30.88 26.88 22.88 18.88 13.1 17.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf" "('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output'," "1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert3" SID "451" Ports [1, 1] Position [685, 255, 730, 285] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "17" bin_pt "15" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Flag as error" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "20,20,374,366" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,30,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\npatch([13.1 18.88 22.88 26.88 30.88 22.88 17.1 13.1 ],[19.44 19.44 23" ".44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([17.1 22.88 18.88 13.1 17.1 ],[15.44 15.44 19.44 19.44 15.44" " ],[0.931 0.946 0.973 ]);\npatch([13.1 18.88 22.88 17.1 13.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch(" "[17.1 30.88 26.88 22.88 18.88 13.1 17.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf" "('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output'," "1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert4" SID "9833" Ports [1, 1] Position [495, 525, 540, 555] BlockMirror on ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "18" bin_pt "15" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Flag as error" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,30,1,1,white,blue,0,edca21da,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\npatch([13.1 18.88 22.88 26.88 30.88 22.88 17.1 13.1 ],[19.44 19.44 23" ".44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([17.1 22.88 18.88 13.1 17.1 ],[15.44 15.44 19.44 19.44 15.44" " ],[0.931 0.946 0.973 ]);\npatch([13.1 18.88 22.88 17.1 13.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch(" "[17.1 30.88 26.88 22.88 18.88 13.1 17.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf" "('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output'," "1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert6" SID "9879" Ports [1, 1] Position [685, 625, 730, 655] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "17" bin_pt "15" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Flag as error" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "20,20,374,366" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,30,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\npatch([13.1 18.88 22.88 26.88 30.88 22.88 17.1 13.1 ],[19.44 19.44 23" ".44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([17.1 22.88 18.88 13.1 17.1 ],[15.44 15.44 19.44 19.44 15.44" " ],[0.931 0.946 0.973 ]);\npatch([13.1 18.88 22.88 17.1 13.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch(" "[17.1 30.88 26.88 22.88 18.88 13.1 17.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf" "('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output'," "1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay1" SID "9732" Ports [1, 1] Position [515, 436, 535, 454] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. If r" "egister retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "20,18,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 20 20 0 0 ],[0 0 18 18 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[11.22 11.22 13." "22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[9.22 9.22 11.22 11.22 9.22 ],[0" ".931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([7.55 14.44" " 12.44 10.44 8.44 5.55 7.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: e" "nd icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-1}','texmode','on');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay10" SID "11308" Ports [1, 1] Position [1225, 203, 1260, 237] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "3" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,34,1,1,white,blue,0,83e6bb61,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 34 34 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 34 34 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[21.44 21.44 25.4" "4 21.44 25.44 25.44 25.44 21.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[17.44 17.44 21.44 21.44 17.44 ]," "[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[13.44 13.44 17.44 17.44 13.44 ],[1 1 1 ]);\npatch([12.1" " 25.88 21.88 17.88 13.88 8.1 12.1 ],[9.44 9.44 13.44 9.44 13.44 13.44 9.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-3}','texmode'," "'on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay11" SID "11309" Ports [1, 1] Position [1230, 728, 1265, 762] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "3" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,34,1,1,white,blue,0,83e6bb61,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 34 34 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 34 34 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[21.44 21.44 25.4" "4 21.44 25.44 25.44 25.44 21.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[17.44 17.44 21.44 21.44 17.44 ]," "[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[13.44 13.44 17.44 17.44 13.44 ],[1 1 1 ]);\npatch([12.1" " 25.88 21.88 17.88 13.88 8.1 12.1 ],[9.44 9.44 13.44 9.44 13.44 13.44 9.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-3}','texmode'," "'on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay2" SID "9917" Ports [1, 1] Position [895, 401, 915, 419] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. If r" "egister retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "20,18,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 20 20 0 0 ],[0 0 18 18 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[11.22 11.22 13." "22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[9.22 9.22 11.22 11.22 9.22 ],[0" ".931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([7.55 14.44" " 12.44 10.44 8.44 5.55 7.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: e" "nd icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-1}','texmode','on');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay3" SID "452" Ports [1, 1] Position [340, 276, 360, 294] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. If r" "egister retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "20,18,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 20 20 0 0 ],[0 0 18 18 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[11.22 11.22 13." "22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[9.22 9.22 11.22 11.22 9.22 ],[0" ".931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([7.55 14.44" " 12.44 10.44 8.44 5.55 7.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: e" "nd icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-1}','texmode','on');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay4" SID "9837" Ports [1, 1] Position [325, 646, 345, 664] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. If r" "egister retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "20,18,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 20 20 0 0 ],[0 0 18 18 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[11.22 11.22 13." "22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[9.22 9.22 11.22 11.22 9.22 ],[0" ".931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([7.55 14.44" " 12.44 10.44 8.44 5.55 7.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: e" "nd icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-1}','texmode','on');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay5" SID "9838" Ports [1, 1] Position [325, 606, 345, 624] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. If r" "egister retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "20,18,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 20 20 0 0 ],[0 0 18 18 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[11.22 11.22 13." "22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[9.22 9.22 11.22 11.22 9.22 ],[0" ".931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([7.55 14.44" " 12.44 10.44 8.44 5.55 7.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: e" "nd icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-1}','texmode','on');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay6" SID "453" Ports [1, 1] Position [340, 236, 360, 254] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. If r" "egister retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "20,18,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 20 20 0 0 ],[0 0 18 18 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[11.22 11.22 13." "22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[9.22 9.22 11.22 11.22 9.22 ],[0" ".931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([7.55 14.44" " 12.44 10.44 8.44 5.55 7.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: e" "nd icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-1}','texmode','on');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay7" SID "454" Ports [1, 1] Position [340, 216, 360, 234] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. If r" "egister retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "20,18,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 20 20 0 0 ],[0 0 18 18 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[11.22 11.22 13." "22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[9.22 9.22 11.22 11.22 9.22 ],[0" ".931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([7.55 14.44" " 12.44 10.44 8.44 5.55 7.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: e" "nd icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-1}','texmode','on');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay8" SID "9839" Ports [1, 1] Position [325, 586, 345, 604] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. If r" "egister retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "20,18,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 20 20 0 0 ],[0 0 18 18 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[11.22 11.22 13." "22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[9.22 9.22 11.22 11.22 9.22 ],[0" ".931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([7.55 14.44" " 12.44 10.44 8.44 5.55 7.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: e" "nd icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-1}','texmode','on');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay9" SID "9919" Ports [1, 1] Position [895, 436, 915, 454] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. If r" "egister retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "20,18,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 20 20 0 0 ],[0 0 18 18 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[11.22 11.22 13." "22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[9.22 9.22 11.22 11.22 9.22 ],[0" ".931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([7.55 14.44" " 12.44 10.44 8.44 5.55 7.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: e" "nd icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-1}','texmode','on');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Dual Port RAM" SID "455" Ports [7, 2] Position [500, 233, 570, 377] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Dual Port RAM" SourceType "Xilinx Dual Port Random Access Memory Block" depth "MAX_NUM_SC" initVector "0" distributed_mem "Block RAM" init_a "0" init_b "0" rst_a off rst_b on en_a off en_b off latency "1" write_mode_A "Read After Write" write_mode_B "Read After Write" dbl_ovrd off optimize "Area" xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "dpram" block_version "VER_STRING_GOES_HERE" sg_icon_stat "70,144,7,2,white,blue,0,7d88b3c1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 70 70 0 0 ],[0 0 144 144 0 ],[0.77 0.82 0" ".91 ]);\nplot([0 70 70 0 0 ],[0 0 144 144 0 ]);\npatch([12.75 27.2 37.2 47.2 57.2 37.2 22.75 12.75 ],[83.1 83.1 93" ".1 83.1 93.1 93.1 93.1 83.1 ],[1 1 1 ]);\npatch([22.75 37.2 27.2 12.75 22.75 ],[73.1 73.1 83.1 83.1 73.1 ],[0.931 " "0.946 0.973 ]);\npatch([12.75 27.2 37.2 22.75 12.75 ],[63.1 63.1 73.1 73.1 63.1 ],[1 1 1 ]);\npatch([22.75 57.2 47" ".2 37.2 27.2 12.75 22.75 ],[53.1 53.1 63.1 53.1 63.1 63.1 53.1 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end " "icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'addra');\ncolor('b" "lack');port_label('input',2,'dina');\ncolor('black');port_label('input',3,'wea');\ncolor('black');port_label('inpu" "t',4,'addrb');\ncolor('black');port_label('input',5,'dinb');\ncolor('black');port_label('input',6,'web');\ncolor('" "black');port_label('input',7,'rstb');\ncolor('black');port_label('output',1,'A');\ncolor('black');port_label('outp" "ut',2,'B');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Dual Port RAM1" SID "9840" Ports [7, 2] Position [485, 603, 555, 747] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Dual Port RAM" SourceType "Xilinx Dual Port Random Access Memory Block" depth "MAX_NUM_SC" initVector "0" distributed_mem "Block RAM" init_a "0" init_b "0" rst_a off rst_b on en_a off en_b off latency "1" write_mode_A "Read After Write" write_mode_B "Read After Write" dbl_ovrd off optimize "Area" xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "dpram" block_version "VER_STRING_GOES_HERE" sg_icon_stat "70,144,7,2,white,blue,0,7d88b3c1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 70 70 0 0 ],[0 0 144 144 0 ],[0.77 0.82 0" ".91 ]);\nplot([0 70 70 0 0 ],[0 0 144 144 0 ]);\npatch([12.75 27.2 37.2 47.2 57.2 37.2 22.75 12.75 ],[83.1 83.1 93" ".1 83.1 93.1 93.1 93.1 83.1 ],[1 1 1 ]);\npatch([22.75 37.2 27.2 12.75 22.75 ],[73.1 73.1 83.1 83.1 73.1 ],[0.931 " "0.946 0.973 ]);\npatch([12.75 27.2 37.2 22.75 12.75 ],[63.1 63.1 73.1 73.1 63.1 ],[1 1 1 ]);\npatch([22.75 57.2 47" ".2 37.2 27.2 12.75 22.75 ],[53.1 53.1 63.1 53.1 63.1 63.1 53.1 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end " "icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'addra');\ncolor('b" "lack');port_label('input',2,'dina');\ncolor('black');port_label('input',3,'wea');\ncolor('black');port_label('inpu" "t',4,'addrb');\ncolor('black');port_label('input',5,'dinb');\ncolor('black');port_label('input',6,'web');\ncolor('" "black');port_label('input',7,'rstb');\ncolor('black');port_label('output',1,'A');\ncolor('black');port_label('outp" "ut',2,'B');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Gateway Out1" SID "9896" Ports [1, 1] Position [1360, 379, 1395, 391] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "A" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "9897" Ports [1, 1] Position [1360, 404, 1395, 416] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "B" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "9908" Ports [1, 1] Position [1140, 829, 1175, 841] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "Gateway Out4" SID "9910" Ports [1, 1] Position [1140, 874, 1175, 886] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "Gateway Out6" SID "9902" Ports [1, 1] Position [1360, 504, 1395, 516] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "H Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "9906" Ports [1, 1] Position [1360, 529, 1395, 541] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Next Empty Sc" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "9894" Ports [1, 1] Position [1360, 354, 1395, 366] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "H" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Mux1" SID "9841" Ports [3, 1] Position [980, 572, 1005, 708] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "25,136,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 19.4286 116.571 136 0 ],[0" ".77 0.82 0.91 ]);\nplot([0 25 25 0 0 ],[0 19.4286 116.571 136 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.3" "25 5.325 ],[71.33 71.33 74.33 71.33 74.33 74.33 74.33 71.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[6" "8.33 68.33 71.33 71.33 68.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[65.33 65.33 68.33 68" ".33 65.33 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[62.33 62.33 65.33 62.33 65.33 65.33 62." "33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nc" "olor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label(" "'input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux2" SID "465" Ports [3, 1] Position [980, 202, 1005, 338] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "25,136,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 19.4286 116.571 136 0 ],[0" ".77 0.82 0.91 ]);\nplot([0 25 25 0 0 ],[0 19.4286 116.571 136 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.3" "25 5.325 ],[71.33 71.33 74.33 71.33 74.33 74.33 74.33 71.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[6" "8.33 68.33 71.33 71.33 68.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[65.33 65.33 68.33 68" ".33 65.33 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[62.33 62.33 65.33 62.33 65.33 65.33 62." "33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nc" "olor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label(" "'input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register" SID "9916" Ports [2, 1] Position [1085, 260, 1125, 295] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "40,35,2,1,white,blue,0,140cc11c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 35 35 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 35 35 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[22.55 22.55 27." "55 22.55 27.55 27.55 27.55 22.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[17.55 17.55 22.55 22.55 17." "55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[12.55 12.55 17.55 17.55 12.55 ],[1 1 1 ]);\npa" "tch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[7.55 7.55 12.55 7.55 12.55 12.55 7.55 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input" "',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'q');\ncolor('black')" ";disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "9918" Ports [2, 1] Position [1090, 630, 1130, 665] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "40,35,2,1,white,blue,0,140cc11c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 35 35 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 35 35 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[22.55 22.55 27." "55 22.55 27.55 27.55 27.55 22.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[17.55 17.55 22.55 22.55 17." "55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[12.55 12.55 17.55 17.55 12.55 ],[1 1 1 ]);\npa" "tch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[7.55 7.55 12.55 7.55 12.55 12.55 7.55 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input" "',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'q');\ncolor('black')" ";disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Smoothing Coef" SID "9863" Ports [1, 2] Position [935, 426, 1005, 464] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Smoothing Coef" Location [61, 101, 2373, 1521] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "156" Block { BlockType Inport Name "Next Empty" SID "9864" Position [315, 188, 345, 202] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub1" SID "9815" Ports [2, 1] Position [480, 288, 525, 332] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "1" precision "User Defined" arith_type "Unsigned" n_bits "12" bin_pt "12" quantization "Truncate" overflow "Flag as error" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" use_rpm "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,2,1,white,blue,0,e85d8a90,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bf{a + b}','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\ne" "wline\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay3" SID "9726" Ports [1, 1] Position [420, 183, 450, 207] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "2" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "30,24,1,1,white,blue,0,85ce9542,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 24 24 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 24 24 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[15.3" "3 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[12.33 12.33 " "15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[9.33 9.33 12.33 12.33 9.33 " "],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('" "black');disp('z^{-2}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Display Name "Display" SID "9811" Ports [1] Position [680, 403, 775, 427] ZOrder -1 ShowName off Decimation "1" Lockdown off } Block { BlockType Display Name "Display1" SID "9813" Ports [1] Position [680, 433, 775, 457] ZOrder -1 ShowName off Decimation "1" Lockdown off } Block { BlockType Display Name "Display2" SID "9892" Ports [1] Position [680, 468, 775, 492] ZOrder -1 ShowName off Decimation "1" Lockdown off } Block { BlockType From Name "From" SID "9808" Position [145, 344, 325, 366] ZOrder -9 ShowName off GotoTag "regRx_Chan_Est_Smoothing_B" TagVisibility "global" } Block { BlockType From Name "From1" SID "9809" Position [145, 239, 325, 261] ZOrder -9 ShowName off GotoTag "regRx_Chan_Est_Smoothing_A" TagVisibility "global" } Block { BlockType Reference Name "Gateway Out1" SID "9814" Ports [1, 1] Position [600, 439, 635, 451] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out2" SID "9893" Ports [1, 1] Position [600, 474, 635, 486] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out8" SID "9812" Ports [1, 1] Position [600, 409, 635, 421] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Logical" SID "9727" Ports [2, 1] Position [495, 173, 525, 202] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "30,29,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 29 29 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 29 29 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 18.4" "4 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 18.44 " "14.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\np" "atch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('or" "');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux" SID "9730" Ports [3, 1] Position [590, 163, 615, 337] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "25,174,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 24.8571 149.143 174 0 " "],[0.77 0.82 0.91 ]);\nplot([0 25 25 0 0 ],[0 24.8571 149.143 174 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12." "66 8.325 5.325 ],[90.33 90.33 93.33 90.33 93.33 93.33 93.33 90.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8." "325 ],[87.33 87.33 90.33 90.33 87.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[84.33 84.3" "3 87.33 87.33 84.33 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[81.33 81.33 84.33 81.33 84." "33 84.33 81.33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin i" "con text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('bla" "ck');port_label('input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon" " text');" } Block { BlockType Outport Name "A" SID "9865" Position [725, 243, 755, 257] IconDisplay "Port number" } Block { BlockType Outport Name "B" SID "9866" Position [725, 348, 755, 362] Port "2" IconDisplay "Port number" } Line { SrcBlock "From" SrcPort 1 Points [20, 0] Branch { Points [210, 0] Branch { DstBlock "B" DstPort 1 } Branch { Points [0, 125] DstBlock "Gateway Out2" DstPort 1 } } Branch { Points [0, -35] DstBlock "AddSub1" DstPort 2 } } Line { SrcBlock "Next Empty" SrcPort 1 Points [50, 0] Branch { DstBlock "Delay3" DstPort 1 } Branch { Points [0, -15] DstBlock "Logical" DstPort 1 } } Line { SrcBlock "From1" SrcPort 1 Points [20, 0] Branch { Points [0, 50] DstBlock "AddSub1" DstPort 1 } Branch { Points [220, 0] Branch { DstBlock "Mux" DstPort 2 } Branch { Points [0, 165] DstBlock "Gateway Out8" DstPort 1 } } } Line { SrcBlock "Delay3" SrcPort 1 DstBlock "Logical" DstPort 2 } Line { SrcBlock "Logical" SrcPort 1 DstBlock "Mux" DstPort 1 } Line { SrcBlock "Gateway Out8" SrcPort 1 DstBlock "Display" DstPort 1 } Line { SrcBlock "Gateway Out1" SrcPort 1 DstBlock "Display1" DstPort 1 } Line { SrcBlock "Mux" SrcPort 1 DstBlock "A" DstPort 1 } Line { SrcBlock "Gateway Out2" SrcPort 1 DstBlock "Display2" DstPort 1 } Line { SrcBlock "AddSub1" SrcPort 1 Points [35, 0] Branch { DstBlock "Mux" DstPort 3 } Branch { Points [0, 135] DstBlock "Gateway Out1" DstPort 1 } } Annotation { Name "Increase A coefficient to (A+B) when next or previous subcarrier is empty" Position [588, 143] } } } Block { BlockType SubSystem Name "Smoothing I" SID "9716" Ports [3, 1] Position [1195, 271, 1295, 329] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Smoothing I" Location [2, 70, 2469, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "153" Block { BlockType Inport Name "H" SID "9717" Position [225, 288, 255, 302] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "A" SID "9718" Position [225, 313, 255, 327] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "B" SID "9867" Position [225, 373, 255, 387] Port "3" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub1" SID "9721" Ports [2, 1] Position [705, 298, 750, 342] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Signed (2's comp)" n_bits "18" bin_pt "16" quantization "Truncate" overflow "Flag as error" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" use_rpm "on" has_advanced_control "0" sggui_pos "20,27,348,319" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,2,1,white,blue,0,e139daf6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bf{a + b}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub3" SID "9722" Ports [2, 1] Position [600, 338, 645, 382] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "1" precision "User Defined" arith_type "Signed (2's comp)" n_bits "18" bin_pt "16" quantization "Truncate" overflow "Flag as error" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" use_rpm "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,2,1,white,blue,0,e85d8a90,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bf{a + b}','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\ne" "wline\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay1" SID "9724" Ports [1, 1] Position [495, 293, 530, 327] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,34,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 34 34 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 34 34 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[21.44 21.4" "4 25.44 21.44 25.44 25.44 25.44 21.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[17.44 17.44 21.44 21.44 " "17.44 ],[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[13.44 13.44 17.44 17.44 13.44 ],[1 1 1 ]);\np" "atch([12.1 25.88 21.88 17.88 13.88 8.1 12.1 ],[9.44 9.44 13.44 9.44 13.44 13.44 9.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-" "1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay2" SID "9725" Ports [1, 1] Position [495, 333, 530, 367] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "2" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,34,1,1,white,blue,0,85ce9542,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 34 34 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 34 34 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[21.44 21.4" "4 25.44 21.44 25.44 25.44 25.44 21.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[17.44 17.44 21.44 21.44 " "17.44 ],[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[13.44 13.44 17.44 17.44 13.44 ],[1 1 1 ]);\np" "atch([12.1 25.88 21.88 17.88 13.88 8.1 12.1 ],[9.44 9.44 13.44 9.44 13.44 13.44 9.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-" "2}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out1" SID "9915" Ports [1, 1] Position [665, 514, 700, 526] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "A" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "9914" Ports [1, 1] Position [665, 539, 700, 551] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "B" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "9898" Ports [1, 1] Position [665, 564, 700, 576] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Sum 1" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "9899" Ports [1, 1] Position [665, 589, 700, 601] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Sum 2" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "9901" Ports [1, 1] Position [665, 614, 700, 626] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Sum 3" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "9913" Ports [1, 1] Position [665, 639, 700, 651] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "H Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "9912" Ports [1, 1] Position [665, 489, 700, 501] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "H" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Mult" SID "9728" Ports [2, 1] Position [375, 283, 425, 332] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mult" SourceType "Xilinx Multiplier Block" infoedit "Hardware notes: To check for the optimum internal pipeline stages of the dedicated multiplier you" " must select 'Test for optimum pipelining'.

Optimization Goal: For implementation into device fabric (LUT" "s), the Speed or Area optimization will take effect only if it's supported by IP for the particular device famil" "y. Otherwise, the results will be identical regardless of the selection." precision "User Defined" arith_type "Signed (2's comp)" n_bits "18" bin_pt "16" quantization "Truncate" overflow "Wrap" en off latency "1" dbl_ovrd off use_behavioral_HDL off opt "Speed" use_embedded on optimum_pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" pipeline "on" use_rpm "on" placement_style "Triangular" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mult" sg_icon_stat "50,49,2,1,white,blue,0,82c891c1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 49 49 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 49 49 0 ]);\npatch([9.425 19.54 26.54 33.54 40.54 26.54 16.425 9.425 ],[31.7" "7 31.77 38.77 31.77 38.77 38.77 38.77 31.77 ],[1 1 1 ]);\npatch([16.425 26.54 19.54 9.425 16.425 ],[24.77 24.77 " "31.77 31.77 24.77 ],[0.931 0.946 0.973 ]);\npatch([9.425 19.54 26.54 16.425 9.425 ],[17.77 17.77 24.77 24.77 17." "77 ],[1 1 1 ]);\npatch([16.425 40.54 33.54 26.54 19.54 9.425 16.425 ],[10.77 10.77 17.77 10.77 17.77 17.77 10.77" " ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nc" "olor('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('" "output',1,'\\bfa \\times b','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('bl" "ack');disp(' \\n ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mult1" SID "9880" Ports [2, 1] Position [375, 343, 425, 392] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mult" SourceType "Xilinx Multiplier Block" infoedit "Hardware notes: To check for the optimum internal pipeline stages of the dedicated multiplier you" " must select 'Test for optimum pipelining'.

Optimization Goal: For implementation into device fabric (LUT" "s), the Speed or Area optimization will take effect only if it's supported by IP for the particular device famil" "y. Otherwise, the results will be identical regardless of the selection." precision "User Defined" arith_type "Signed (2's comp)" n_bits "18" bin_pt "16" quantization "Truncate" overflow "Wrap" en off latency "1" dbl_ovrd off use_behavioral_HDL off opt "Speed" use_embedded on optimum_pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" pipeline "on" use_rpm "on" placement_style "Triangular" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mult" sg_icon_stat "50,49,2,1,white,blue,0,82c891c1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 49 49 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 49 49 0 ]);\npatch([9.425 19.54 26.54 33.54 40.54 26.54 16.425 9.425 ],[31.7" "7 31.77 38.77 31.77 38.77 38.77 38.77 31.77 ],[1 1 1 ]);\npatch([16.425 26.54 19.54 9.425 16.425 ],[24.77 24.77 " "31.77 31.77 24.77 ],[0.931 0.946 0.973 ]);\npatch([9.425 19.54 26.54 16.425 9.425 ],[17.77 17.77 24.77 24.77 17." "77 ],[1 1 1 ]);\npatch([16.425 40.54 33.54 26.54 19.54 9.425 16.425 ],[10.77 10.77 17.77 10.77 17.77 17.77 10.77" " ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nc" "olor('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('" "output',1,'\\bfa \\times b','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('bl" "ack');disp(' \\n ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register" SID "9924" Ports [1, 1] Position [605, 297, 635, 323] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[16.3" "3 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 13.33 " "16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13.33 10." "33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor" "('black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','" "texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Scope Name "Smoothing I" SID "9911" Ports [9] Position [855, 490, 890, 700] ZOrder -3 Floating off Location [6, 202, 1686, 1206] Open off NumInputPorts "9" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" axes9 "%" } List { ListType ScopeGraphics FigureColor "[0.5 0.5 0.5]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "772.0815318097584" YMin "-0.5~-0.6~-0.5~-0.5~0~0~0~0~0" YMax "0.7~0.5~0.5~0.5~70~3~1~0.5~0.7" SaveName "ScopeData7" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType Outport Name "H-sm" SID "9731" Position [805, 313, 835, 327] IconDisplay "Port number" } Line { SrcBlock "H" SrcPort 1 Points [90, 0] Branch { DstBlock "Mult" DstPort 1 } Branch { Points [0, 60] Branch { DstBlock "Mult1" DstPort 1 } Branch { Points [0, 140] DstBlock "Gateway Out8" DstPort 1 } } } Line { SrcBlock "Mult1" SrcPort 1 Points [35, 0] Branch { Points [0, -20] DstBlock "Delay2" DstPort 1 } Branch { Points [95, 0] Branch { DstBlock "AddSub3" DstPort 2 } Branch { Points [0, 250] DstBlock "Gateway Out5" DstPort 1 } } } Line { SrcBlock "Delay2" SrcPort 1 Points [30, 0] Branch { DstBlock "AddSub3" DstPort 1 } Branch { Points [0, 245] DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "Mult" SrcPort 1 DstBlock "Delay1" DstPort 1 } Line { SrcBlock "AddSub3" SrcPort 1 Points [20, 0; 0, -30] DstBlock "AddSub1" DstPort 2 } Line { SrcBlock "AddSub1" SrcPort 1 Points [20, 0] Branch { DstBlock "H-sm" DstPort 1 } Branch { Points [0, 150; -155, 0; 0, 175] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "Delay1" SrcPort 1 Points [35, 0] Branch { Points [0, 260] DstBlock "Gateway Out3" DstPort 1 } Branch { DstBlock "Register" DstPort 1 } } Line { SrcBlock "A" SrcPort 1 Points [85, 0] Branch { DstBlock "Mult" DstPort 2 } Branch { Points [0, 200] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "B" SrcPort 1 Points [80, 0] Branch { DstBlock "Mult1" DstPort 2 } Branch { Points [0, 165] DstBlock "Gateway Out2" DstPort 1 } } Line { Name "H" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 DstBlock "Smoothing I" DstPort 1 } Line { Name "A" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 DstBlock "Smoothing I" DstPort 2 } Line { Name "B" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 DstBlock "Smoothing I" DstPort 3 } Line { Name "Sum 1" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 DstBlock "Smoothing I" DstPort 4 } Line { Name "Sum 2" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 DstBlock "Smoothing I" DstPort 5 } Line { Name "Sum 3" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 DstBlock "Smoothing I" DstPort 6 } Line { Name "H Out" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 DstBlock "Smoothing I" DstPort 7 } Line { SrcBlock "Register" SrcPort 1 DstBlock "AddSub1" DstPort 1 } Annotation { Name "S(n-1) = AH(n-1) + BH(n) + BH(n-2)" Position [452, 238] } } } Block { BlockType Scope Name "Smoothing I1" SID "9895" Ports [9] Position [1550, 355, 1585, 565] ZOrder -3 Floating off Location [1, 45, 2472, 1599] Open off NumInputPorts "9" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" axes9 "%" } List { ListType ScopeGraphics FigureColor "[0.5 0.5 0.5]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "772.0815318097584" YMin "-0.5~-0.6~-0.5~-0.5~0~0~0~0~0" YMax "0.7~0.5~0.5~0.5~70~3~1~0.5~0.7" SaveName "ScopeData7" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType SubSystem Name "Smoothing Q" SID "9930" Ports [3, 1] Position [1200, 641, 1300, 699] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Smoothing Q" Location [2, 70, 2469, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "153" Block { BlockType Inport Name "H" SID "9931" Position [225, 288, 255, 302] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "A" SID "9932" Position [225, 313, 255, 327] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "B" SID "9933" Position [225, 373, 255, 387] Port "3" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub1" SID "9934" Ports [2, 1] Position [705, 298, 750, 342] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Signed (2's comp)" n_bits "18" bin_pt "16" quantization "Truncate" overflow "Flag as error" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" use_rpm "on" has_advanced_control "0" sggui_pos "20,27,348,319" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,2,1,white,blue,0,e139daf6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bf{a + b}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub3" SID "9935" Ports [2, 1] Position [600, 338, 645, 382] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "1" precision "User Defined" arith_type "Signed (2's comp)" n_bits "18" bin_pt "16" quantization "Truncate" overflow "Flag as error" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" use_rpm "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,2,1,white,blue,0,e85d8a90,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bf{a + b}','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\ne" "wline\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay1" SID "9936" Ports [1, 1] Position [495, 293, 530, 327] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,34,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 34 34 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 34 34 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[21.44 21.4" "4 25.44 21.44 25.44 25.44 25.44 21.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[17.44 17.44 21.44 21.44 " "17.44 ],[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[13.44 13.44 17.44 17.44 13.44 ],[1 1 1 ]);\np" "atch([12.1 25.88 21.88 17.88 13.88 8.1 12.1 ],[9.44 9.44 13.44 9.44 13.44 13.44 9.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-" "1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay2" SID "9937" Ports [1, 1] Position [495, 333, 530, 367] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "2" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,34,1,1,white,blue,0,85ce9542,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 34 34 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 34 34 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[21.44 21.4" "4 25.44 21.44 25.44 25.44 25.44 21.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[17.44 17.44 21.44 21.44 " "17.44 ],[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[13.44 13.44 17.44 17.44 13.44 ],[1 1 1 ]);\np" "atch([12.1 25.88 21.88 17.88 13.88 8.1 12.1 ],[9.44 9.44 13.44 9.44 13.44 13.44 9.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-" "2}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out1" SID "9938" Ports [1, 1] Position [665, 514, 700, 526] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "A" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "9939" Ports [1, 1] Position [665, 539, 700, 551] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "B" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "9940" Ports [1, 1] Position [665, 564, 700, 576] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Sum 1" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "9941" Ports [1, 1] Position [665, 589, 700, 601] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Sum 2" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "9942" Ports [1, 1] Position [665, 614, 700, 626] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Sum 3" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "9943" Ports [1, 1] Position [665, 639, 700, 651] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "H Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "9944" Ports [1, 1] Position [665, 489, 700, 501] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "H" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Mult" SID "9945" Ports [2, 1] Position [375, 283, 425, 332] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mult" SourceType "Xilinx Multiplier Block" infoedit "Hardware notes: To check for the optimum internal pipeline stages of the dedicated multiplier you" " must select 'Test for optimum pipelining'.

Optimization Goal: For implementation into device fabric (LUT" "s), the Speed or Area optimization will take effect only if it's supported by IP for the particular device famil" "y. Otherwise, the results will be identical regardless of the selection." precision "User Defined" arith_type "Signed (2's comp)" n_bits "18" bin_pt "16" quantization "Truncate" overflow "Wrap" en off latency "1" dbl_ovrd off use_behavioral_HDL off opt "Speed" use_embedded on optimum_pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" pipeline "on" use_rpm "on" placement_style "Triangular" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mult" sg_icon_stat "50,49,2,1,white,blue,0,82c891c1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 49 49 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 49 49 0 ]);\npatch([9.425 19.54 26.54 33.54 40.54 26.54 16.425 9.425 ],[31.7" "7 31.77 38.77 31.77 38.77 38.77 38.77 31.77 ],[1 1 1 ]);\npatch([16.425 26.54 19.54 9.425 16.425 ],[24.77 24.77 " "31.77 31.77 24.77 ],[0.931 0.946 0.973 ]);\npatch([9.425 19.54 26.54 16.425 9.425 ],[17.77 17.77 24.77 24.77 17." "77 ],[1 1 1 ]);\npatch([16.425 40.54 33.54 26.54 19.54 9.425 16.425 ],[10.77 10.77 17.77 10.77 17.77 17.77 10.77" " ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nc" "olor('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('" "output',1,'\\bfa \\times b','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('bl" "ack');disp(' \\n ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mult1" SID "9946" Ports [2, 1] Position [375, 343, 425, 392] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mult" SourceType "Xilinx Multiplier Block" infoedit "Hardware notes: To check for the optimum internal pipeline stages of the dedicated multiplier you" " must select 'Test for optimum pipelining'.

Optimization Goal: For implementation into device fabric (LUT" "s), the Speed or Area optimization will take effect only if it's supported by IP for the particular device famil" "y. Otherwise, the results will be identical regardless of the selection." precision "User Defined" arith_type "Signed (2's comp)" n_bits "18" bin_pt "16" quantization "Truncate" overflow "Wrap" en off latency "1" dbl_ovrd off use_behavioral_HDL off opt "Speed" use_embedded on optimum_pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" pipeline "on" use_rpm "on" placement_style "Triangular" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mult" sg_icon_stat "50,49,2,1,white,blue,0,82c891c1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 49 49 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 49 49 0 ]);\npatch([9.425 19.54 26.54 33.54 40.54 26.54 16.425 9.425 ],[31.7" "7 31.77 38.77 31.77 38.77 38.77 38.77 31.77 ],[1 1 1 ]);\npatch([16.425 26.54 19.54 9.425 16.425 ],[24.77 24.77 " "31.77 31.77 24.77 ],[0.931 0.946 0.973 ]);\npatch([9.425 19.54 26.54 16.425 9.425 ],[17.77 17.77 24.77 24.77 17." "77 ],[1 1 1 ]);\npatch([16.425 40.54 33.54 26.54 19.54 9.425 16.425 ],[10.77 10.77 17.77 10.77 17.77 17.77 10.77" " ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nc" "olor('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('" "output',1,'\\bfa \\times b','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('bl" "ack');disp(' \\n ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register" SID "9947" Ports [1, 1] Position [605, 297, 635, 323] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[16.3" "3 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 13.33 " "16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13.33 10." "33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor" "('black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','" "texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Scope Name "Smoothing I" SID "9948" Ports [9] Position [855, 490, 890, 700] ZOrder -3 Floating off Location [6, 202, 1686, 1206] Open off NumInputPorts "9" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" axes9 "%" } List { ListType ScopeGraphics FigureColor "[0.5 0.5 0.5]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "772.0815318097584" YMin "-0.5~-0.6~-0.5~-0.5~0~0~0~0~0" YMax "0.7~0.5~0.5~0.5~70~3~1~0.5~0.7" SaveName "ScopeData7" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType Outport Name "H-sm" SID "9949" Position [805, 313, 835, 327] IconDisplay "Port number" } Line { SrcBlock "Register" SrcPort 1 DstBlock "AddSub1" DstPort 1 } Line { Name "H Out" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 DstBlock "Smoothing I" DstPort 7 } Line { Name "Sum 3" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 DstBlock "Smoothing I" DstPort 6 } Line { Name "Sum 2" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 DstBlock "Smoothing I" DstPort 5 } Line { Name "Sum 1" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 DstBlock "Smoothing I" DstPort 4 } Line { Name "B" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 DstBlock "Smoothing I" DstPort 3 } Line { Name "A" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 DstBlock "Smoothing I" DstPort 2 } Line { Name "H" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 DstBlock "Smoothing I" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [80, 0] Branch { Points [0, 165] DstBlock "Gateway Out2" DstPort 1 } Branch { DstBlock "Mult1" DstPort 2 } } Line { SrcBlock "A" SrcPort 1 Points [85, 0] Branch { Points [0, 200] DstBlock "Gateway Out1" DstPort 1 } Branch { DstBlock "Mult" DstPort 2 } } Line { SrcBlock "Delay1" SrcPort 1 Points [35, 0] Branch { DstBlock "Register" DstPort 1 } Branch { Points [0, 260] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "AddSub1" SrcPort 1 Points [20, 0] Branch { Points [0, 150; -155, 0; 0, 175] DstBlock "Gateway Out6" DstPort 1 } Branch { DstBlock "H-sm" DstPort 1 } } Line { SrcBlock "AddSub3" SrcPort 1 Points [20, 0; 0, -30] DstBlock "AddSub1" DstPort 2 } Line { SrcBlock "Mult" SrcPort 1 DstBlock "Delay1" DstPort 1 } Line { SrcBlock "Delay2" SrcPort 1 Points [30, 0] Branch { Points [0, 245] DstBlock "Gateway Out4" DstPort 1 } Branch { DstBlock "AddSub3" DstPort 1 } } Line { SrcBlock "Mult1" SrcPort 1 Points [35, 0] Branch { Points [95, 0] Branch { Points [0, 250] DstBlock "Gateway Out5" DstPort 1 } Branch { DstBlock "AddSub3" DstPort 2 } } Branch { Points [0, -20] DstBlock "Delay2" DstPort 1 } } Line { SrcBlock "H" SrcPort 1 Points [90, 0] Branch { Points [0, 60] Branch { Points [0, 140] DstBlock "Gateway Out8" DstPort 1 } Branch { DstBlock "Mult1" DstPort 1 } } Branch { DstBlock "Mult" DstPort 1 } } Annotation { Name "S(n-1) = AH(n-1) + BH(n) + BH(n-2)" Position [452, 238] } } } Block { BlockType ToWorkspace Name "To Workspace" SID "9907" Ports [1] Position [1240, 825, 1415, 845] ZOrder -7 VariableName "h_est_smoothing_next_empty" MaxDataPoints "inf" SampleTime "-1" SaveFormat "Structure With Time" } Block { BlockType ToWorkspace Name "To Workspace1" SID "9909" Ports [1] Position [1240, 870, 1415, 890] ZOrder -7 VariableName "h_est_smoothing_H_I" MaxDataPoints "inf" SampleTime "-1" SaveFormat "Structure With Time" } Block { BlockType Reference Name "div_2" SID "466" Ports [1, 1] Position [900, 259, 930, 281] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Scale" SourceType "Xilinx Input Scaler Block" infoedit "Scales input by a power of two by adjusting the binary point position.

Hardware notes: In hard" "ware this block costs nothing." scale_factor "-1" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "scale" sg_icon_stat "30,22,1,1,white,blue,0,315b7d78,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 22 22 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[14.33 14.3" "3 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[11.33 11.33 14.33 14" ".33 11.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 1 1 ]" ");\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 0.973 " "]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('" "\\bf{2^{-1}}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "div_2 " SID "9861" Ports [1, 1] Position [900, 629, 930, 651] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Scale" SourceType "Xilinx Input Scaler Block" infoedit "Scales input by a power of two by adjusting the binary point position.

Hardware notes: In hard" "ware this block costs nothing." scale_factor "-1" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "scale" sg_icon_stat "30,22,1,1,white,blue,0,315b7d78,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 22 22 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[14.33 14.3" "3 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[11.33 11.33 14.33 14" ".33 11.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 1 1 ]" ");\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 0.973 " "]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('" "\\bf{2^{-1}}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "h_I[n]" SID "467" Position [1365, 293, 1395, 307] IconDisplay "Port number" } Block { BlockType Outport Name "h_Q[n]" SID "9862" Position [1365, 663, 1395, 677] Port "2" IconDisplay "Port number" } Line { SrcBlock "Constant4" SrcPort 1 DstBlock "Dual Port RAM" DstPort 5 } Line { SrcBlock "Constant\nRead State" SrcPort 1 DstBlock "Dual Port RAM" DstPort 6 } Line { SrcBlock "AddSub2" SrcPort 1 Points [5, 0; 0, 50] DstBlock "Dual Port RAM" DstPort 2 } Line { SrcBlock "Convert1" SrcPort 1 Points [-115, 0] DstBlock "AddSub2" DstPort 1 } Line { SrcBlock "Delay6" SrcPort 1 DstBlock "Dual Port RAM" DstPort 1 } Line { SrcBlock "Delay3" SrcPort 1 DstBlock "Dual Port RAM" DstPort 3 } Line { SrcBlock "Delay7" SrcPort 1 DstBlock "AddSub2" DstPort 2 } Line { SrcBlock "Est_WE" SrcPort 1 Points [25, 0] Branch { DstBlock "Delay3" DstPort 1 } Branch { Points [0, 370] DstBlock "Delay4" DstPort 1 } } Line { SrcBlock "Est_Addr" SrcPort 1 Points [20, 0] Branch { Points [95, 0; 0, -15] Branch { Points [0, -60] DstBlock "Delay6" DstPort 1 } Branch { DstBlock "Dual Port RAM" DstPort 4 } } Branch { Points [0, 355; 95, 0] Branch { DstBlock "Dual Port RAM1" DstPort 4 } Branch { Points [0, -60] DstBlock "Delay5" DstPort 1 } } } Line { SrcBlock "First Sym" SrcPort 1 Points [15, 0] Branch { DstBlock "Dual Port RAM" DstPort 7 } Branch { Points [0, 370] DstBlock "Dual Port RAM1" DstPort 7 } } Line { SrcBlock "x_I" SrcPort 1 DstBlock "Delay7" DstPort 1 } Line { SrcBlock "Dual Port RAM" SrcPort 2 Points [40, 0; 0, -170] DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Convert3" SrcPort 1 Points [135, 0] Branch { DstBlock "div_2" DstPort 1 } Branch { Points [0, 45] DstBlock "Mux2" DstPort 3 } } Line { SrcBlock "Dual Port RAM" SrcPort 1 DstBlock "Convert3" DstPort 1 } Line { SrcBlock "Scale" SrcPort 1 Points [10, 0] Branch { DstBlock "Mux2" DstPort 1 } Branch { Points [0, 370] DstBlock "Mux1" DstPort 1 } } Line { SrcBlock "div_2" SrcPort 1 DstBlock "Mux2" DstPort 2 } Line { SrcBlock "Mux2" SrcPort 1 Points [30, 0] Branch { Points [0, 90] Branch { DstBlock "Gateway Out8" DstPort 1 } Branch { Points [0, 520] DstBlock "Gateway Out4" DstPort 1 } } Branch { DstBlock "Register" DstPort 1 } } Line { SrcBlock "Empty Sc" SrcPort 1 DstBlock "Delay1" DstPort 1 } Line { SrcBlock "Smoothing I" SrcPort 1 Points [25, 0] Branch { Points [0, 210] DstBlock "Gateway Out6" DstPort 1 } Branch { DstBlock "h_I[n]" DstPort 1 } } Line { SrcBlock "div_2 " SrcPort 1 DstBlock "Mux1" DstPort 2 } Line { SrcBlock "Dual Port RAM1" SrcPort 1 DstBlock "Convert6" DstPort 1 } Line { SrcBlock "Convert6" SrcPort 1 Points [125, 0] Branch { Points [0, 45] DstBlock "Mux1" DstPort 3 } Branch { DstBlock "div_2 " DstPort 1 } } Line { SrcBlock "Dual Port RAM1" SrcPort 2 Points [40, 0; 0, -170] DstBlock "Convert4" DstPort 1 } Line { SrcBlock "x_Q" SrcPort 1 DstBlock "Delay8" DstPort 1 } Line { SrcBlock "Delay8" SrcPort 1 DstBlock "AddSub1" DstPort 2 } Line { SrcBlock "Delay4" SrcPort 1 DstBlock "Dual Port RAM1" DstPort 3 } Line { SrcBlock "Delay5" SrcPort 1 DstBlock "Dual Port RAM1" DstPort 1 } Line { SrcBlock "Convert4" SrcPort 1 Points [-115, 0] DstBlock "AddSub1" DstPort 1 } Line { SrcBlock "AddSub1" SrcPort 1 Points [0, 50] DstBlock "Dual Port RAM1" DstPort 2 } Line { SrcBlock "Constant\nRead State1" SrcPort 1 DstBlock "Dual Port RAM1" DstPort 6 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Dual Port RAM1" DstPort 5 } Line { SrcBlock "Smoothing Q" SrcPort 1 DstBlock "h_Q[n]" DstPort 1 } Line { SrcBlock "Delay1" SrcPort 1 Points [330, 0] Branch { Points [0, 90] Branch { DstBlock "Gateway Out7" DstPort 1 } Branch { Points [0, 300] DstBlock "Gateway Out3" DstPort 1 } } Branch { Points [0, -35] DstBlock "Delay2" DstPort 1 } Branch { DstBlock "Delay9" DstPort 1 } } Line { SrcBlock "Smoothing Coef" SrcPort 1 Points [150, 0] Branch { Points [0, -50] Branch { Points [0, -85] DstBlock "Smoothing I" DstPort 2 } Branch { DstBlock "Gateway Out1" DstPort 1 } } Branch { Points [0, 235] DstBlock "Smoothing Q" DstPort 2 } } Line { SrcBlock "Smoothing Coef" SrcPort 2 Points [145, 0] Branch { Points [0, -45] Branch { Points [0, -90] DstBlock "Smoothing I" DstPort 3 } Branch { DstBlock "Gateway Out2" DstPort 1 } } Branch { Points [0, 235] DstBlock "Smoothing Q" DstPort 3 } } Line { Name "H" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 DstBlock "Smoothing I1" DstPort 1 } Line { Name "A" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 DstBlock "Smoothing I1" DstPort 2 } Line { Name "B" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 DstBlock "Smoothing I1" DstPort 3 } Line { Name "Sum 1" Labels [0, 0] Points [1400, 435] DstBlock "Smoothing I1" DstPort 4 } Line { Name "Sum 2" Labels [0, 0] Points [1400, 460] DstBlock "Smoothing I1" DstPort 5 } Line { Name "Sum 3" Labels [0, 0] Points [1400, 485] DstBlock "Smoothing I1" DstPort 6 } Line { Name "H Out" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 DstBlock "Smoothing I1" DstPort 7 } Line { Name "Next Empty Sc" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 DstBlock "Smoothing I1" DstPort 8 } Line { SrcBlock "Gateway Out3" SrcPort 1 DstBlock "To Workspace" DstPort 1 } Line { SrcBlock "Gateway Out4" SrcPort 1 DstBlock "To Workspace1" DstPort 1 } Line { SrcBlock "Register" SrcPort 1 Points [50, 0] Branch { Points [0, -60] DstBlock "Delay10" DstPort 1 } Branch { DstBlock "Smoothing I" DstPort 1 } } Line { SrcBlock "Delay2" SrcPort 1 Points [130, 0] Branch { Points [0, -125] DstBlock "Register" DstPort 2 } Branch { Points [0, 245] DstBlock "Register1" DstPort 2 } } Line { SrcBlock "Mux1" SrcPort 1 DstBlock "Register1" DstPort 1 } Line { SrcBlock "Register1" SrcPort 1 Points [45, 0] Branch { DstBlock "Smoothing Q" DstPort 1 } Branch { Points [0, 95] DstBlock "Delay11" DstPort 1 } } Line { SrcBlock "Delay9" SrcPort 1 DstBlock "Smoothing Coef" DstPort 1 } Annotation { Name "11a/g preamble has two L-LTF. Both generate estimates and are summed\nbefore the RAM. The sum must be di" "vided by 2 to properly scale\nthe H ests for the EQ.\n11n/ac have 1 HT-LTF for 1SS mode, so no scaling is required" "." Position [684, 144] HorizontalAlignment "left" } Annotation { Name "Delay by 1 less than buffer latency so smoothing\nlogic knows when \"next\" subcarrier is empty and \nca" "n adjust the smoothing coefficients accordingly." Position [530, 478] } } } Block { BlockType Reference Name "Gateway Out1" SID "433" Ports [1, 1] Position [1020, 559, 1055, 571] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "x_Q" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out12" SID "10102" Ports [1, 1] Position [1140, 854, 1175, 866] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out13" SID "10103" Ports [1, 1] Position [1140, 869, 1175, 881] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out2" SID "434" Ports [1, 1] Position [1020, 584, 1055, 596] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "H_I" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "435" Ports [1, 1] Position [1020, 609, 1055, 621] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "H_Q" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "436" Ports [1, 1] Position [1020, 634, 1055, 646] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "SC Ind" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "437" Ports [1, 1] Position [1020, 684, 1055, 696] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Valid Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "438" Ports [1, 1] Position [1020, 659, 1055, 671] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Sym Ind" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "10104" Ports [1, 1] Position [1140, 784, 1175, 796] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out8" SID "439" Ports [1, 1] Position [1020, 534, 1055, 546] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "x_I" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Scope Name "H Est Outputs" SID "440" Ports [9] Position [1210, 535, 1245, 745] ZOrder -3 Floating off Location [6, 40, 1841, 1194] Open off NumInputPorts "9" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" axes9 "%" } List { ListType ScopeGraphics FigureColor "[0.5 0.5 0.5]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "50000" YMin "-1~-1~-0.5~-0.5~0~0~0~0~0" YMax "1~1~1~0.5~80~60~1~1~0.8" SaveName "ScopeData16" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType Reference Name "Inverter" SID "468" Ports [1, 1] Position [420, 456, 455, 474] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "35,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 18 18 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[1" "1.22 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[9.22 9.22 " "11.22 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[7.22 7.22 9.22 9.22 7.22 ],[" "1 1 1 ]);\npatch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('bla" "ck');disp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter1" SID "14909" Ports [1, 1] Position [655, 426, 690, 444] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "35,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 18 18 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[1" "1.22 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[9.22 9.22 " "11.22 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[7.22 7.22 9.22 9.22 7.22 ],[" "1 1 1 ]);\npatch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('bla" "ck');disp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "469" Ports [2, 1] Position [490, 434, 530, 476] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,42,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 42 42 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 42 42 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[26.55" " 26.55 31.55 26.55 31.55 31.55 31.55 26.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[21.55 21.55 26" ".55 26.55 21.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[16.55 16.55 21.55 21.55 16.55 " "],[1 1 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[11.55 11.55 16.55 11.55 16.55 16.55 11.55 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n" "color('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "470" Ports [2, 1] Position [450, 205, 480, 240] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "30,35,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 35 35 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 35 35 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[21.44 " "21.44 25.44 21.44 25.44 25.44 25.44 21.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[17.44 17.44 21.44 2" "1.44 17.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[13.44 13.44 17.44 17.44 13.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[9.44 9.44 13.44 9.44 13.44 13.44 9.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');" "disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical3" SID "14908" Ports [2, 1] Position [715, 424, 755, 466] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,42,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 42 42 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 42 42 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[26.55" " 26.55 31.55 26.55 31.55 31.55 31.55 26.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[21.55 21.55 26" ".55 26.55 21.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[16.55 16.55 21.55 21.55 16.55 " "],[1 1 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[11.55 11.55 16.55 11.55 16.55 16.55 11.55 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n" "color('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Mult by LTF" SID "471" Ports [5, 3] Position [540, 140, 620, 220] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Mult by LTF" Location [-1678, 70, -2, 1030] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "x_re" SID "472" Position [525, 383, 555, 397] IconDisplay "Port number" } Block { BlockType Inport Name "x_im" SID "473" Position [525, 503, 555, 517] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "Sym Ind" SID "14917" Position [160, 208, 190, 222] NamePlacement "alternate" Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "x_valid" SID "9903" Position [525, 123, 555, 137] Port "4" IconDisplay "Port number" } Block { BlockType Inport Name "x_ind" SID "474" Position [525, 218, 555, 232] Port "5" IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "475" Ports [0, 1] Position [960, 472, 995, 498] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "2" bin_pt "2" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "8" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "35,26,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 26 26 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[16.33 16" ".33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[13.33 13.33 16.33" " 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[10.33 10.33 13.33 13.33 10.33 ]," "[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('output',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant2" SID "476" Ports [0, 1] Position [960, 352, 995, 378] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "2" bin_pt "2" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "8" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "35,26,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 26 26 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[16.33 16" ".33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[13.33 13.33 16.33" " 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[10.33 10.33 13.33 13.33 10.33 ]," "[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('output',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant3" SID "14914" Ports [0, 1] Position [160, 222, 195, 248] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "6" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "8" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "35,26,0,1,white,blue,0,f0403ad7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 26 26 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[16.33 16" ".33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[13.33 13.33 16.33" " 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[10.33 10.33 13.33 13.33 10.33 ]," "[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('output',1,'6');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "477" Position [125, 148, 345, 172] ZOrder -9 ShowName off GotoTag "RX_PHY_MODE_11N_AC" TagVisibility "global" } Block { BlockType Reference Name "HT-LTF" SID "478" Ports [1, 1] Position [605, 251, 680, 289] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/ROM" SourceType "Xilinx Single Port Read-Only Memory Block" depth "MAX_NUM_SC" initVector "ht_ltf_f" distributed_mem "Distributed memory" rst off init_reg "0" en off latency "0" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "2" bin_pt "1" preci_type "Single" exp_width "8" frac_width "24" dbl_ovrd off optimize "Area" use_rpm on xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "sprom" sg_icon_stat "75,38,1,1,white,blue,0,eff69a7e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 75 75 0 0 ],[0 0 38 38 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 75 75 0 0 ],[0 0 38 38 0 ]);\npatch([25.875 33.1 38.1 43.1 48.1 38.1 30.875 25.875 ],[24.55 24.55 2" "9.55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([30.875 38.1 33.1 25.875 30.875 ],[19.55 19.55 24.55 24.55 " "19.55 ],[0.931 0.946 0.973 ]);\npatch([25.875 33.1 38.1 30.875 25.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1 1 ])" ";\npatch([30.875 48.1 43.1 38.1 33.1 25.875 30.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0.973 ]" ");\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label(" "'input',1,'addr');\n\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "9904" Ports [1, 1] Position [1055, 202, 1090, 218] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "35,16,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 16 16 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 16 16 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[10.22 10.22" " 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[8.22 8.22 10.22 10.22 8" ".22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatch" "([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfpr" "intf('','COMMENT: end icon text');" } Block { BlockType Reference Name "L-LTF" SID "479" Ports [1, 1] Position [605, 206, 680, 244] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/ROM" SourceType "Xilinx Single Port Read-Only Memory Block" depth "MAX_NUM_SC" initVector "l_ltf_f" distributed_mem "Distributed memory" rst off init_reg "0" en off latency "0" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "2" bin_pt "1" preci_type "Single" exp_width "8" frac_width "24" dbl_ovrd off optimize "Area" use_rpm on xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "sprom" sg_icon_stat "75,38,1,1,white,blue,0,eff69a7e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 75 75 0 0 ],[0 0 38 38 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 75 75 0 0 ],[0 0 38 38 0 ]);\npatch([25.875 33.1 38.1 43.1 48.1 38.1 30.875 25.875 ],[24.55 24.55 2" "9.55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([30.875 38.1 33.1 25.875 30.875 ],[19.55 19.55 24.55 24.55 " "19.55 ],[0.931 0.946 0.973 ]);\npatch([25.875 33.1 38.1 30.875 25.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1 1 ])" ";\npatch([30.875 48.1 43.1 38.1 33.1 25.875 30.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0.973 ]" ");\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label(" "'input',1,'addr');\n\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical" SID "9905" Ports [2, 1] Position [1145, 190, 1185, 270] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,80,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 80 80 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 80 80 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[45.55 45.55 50." "55 45.55 50.55 50.55 50.55 45.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[40.55 40.55 45.55 45.55 40." "55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[35.55 35.55 40.55 40.55 35.55 ],[1 1 1 ]);\npa" "tch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[30.55 30.55 35.55 30.55 35.55 35.55 30.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('o" "r');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "14916" Ports [2, 1] Position [440, 140, 480, 220] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,80,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 80 80 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 80 80 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[45.55 45.55 50." "55 45.55 50.55 50.55 50.55 45.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[40.55 40.55 45.55 45.55 40." "55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[35.55 35.55 40.55 40.55 35.55 ],[1 1 1 ]);\npa" "tch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[30.55 30.55 35.55 30.55 35.55 35.55 30.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('a" "nd');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux" SID "480" Ports [4, 1] Position [1060, 326, 1085, 429] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "25,103,4,1,white,blue,3,58b3489d,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 14.7143 88.2857 103 0 ],[0" ".77 0.82 0.91 ]);\nplot([0 25 25 0 0 ],[0 14.7143 88.2857 103 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.3" "25 5.325 ],[54.33 54.33 57.33 54.33 57.33 57.33 57.33 54.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[5" "1.33 51.33 54.33 54.33 51.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[48.33 48.33 51.33 51" ".33 48.33 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[45.33 45.33 48.33 45.33 48.33 48.33 45." "33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nc" "olor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label(" "'input',3,'d1');\ncolor('black');port_label('input',4,'d2');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfpr" "intf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux1" SID "481" Ports [4, 1] Position [1060, 446, 1085, 549] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "25,103,4,1,white,blue,3,58b3489d,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 14.7143 88.2857 103 0 ],[0" ".77 0.82 0.91 ]);\nplot([0 25 25 0 0 ],[0 14.7143 88.2857 103 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.3" "25 5.325 ],[54.33 54.33 57.33 54.33 57.33 57.33 57.33 54.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[5" "1.33 51.33 54.33 54.33 51.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[48.33 48.33 51.33 51" ".33 48.33 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[45.33 45.33 48.33 45.33 48.33 48.33 45." "33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nc" "olor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label(" "'input',3,'d1');\ncolor('black');port_label('input',4,'d2');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfpr" "intf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux2" SID "482" Ports [3, 1] Position [760, 157, 785, 293] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "25,136,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 19.4286 116.571 136 0 ],[0" ".77 0.82 0.91 ]);\nplot([0 25 25 0 0 ],[0 19.4286 116.571 136 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.3" "25 5.325 ],[71.33 71.33 74.33 71.33 74.33 74.33 74.33 71.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[6" "8.33 68.33 71.33 71.33 68.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[65.33 65.33 68.33 68" ".33 65.33 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[62.33 62.33 65.33 62.33 65.33 65.33 62." "33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nc" "olor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label(" "'input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Negate" SID "483" Ports [1, 1] Position [960, 398, 990, 432] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Negate" SourceType "Xilinx Negate Block Block" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "negate" sg_icon_stat "30,34,1,1,white,blue,0,36bd7045,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 34 34 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 34 34 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[21.44 21.44 25.4" "4 21.44 25.44 25.44 25.44 21.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[17.44 17.44 21.44 21.44 17.44 ]," "[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[13.44 13.44 17.44 17.44 13.44 ],[1 1 1 ]);\npatch([10.1" " 23.88 19.88 15.88 11.88 6.1 10.1 ],[9.44 9.44 13.44 9.44 13.44 13.44 9.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('\\bf{x(-1)}','texm" "ode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Negate1" SID "484" Ports [1, 1] Position [960, 518, 990, 552] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Negate" SourceType "Xilinx Negate Block Block" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "negate" sg_icon_stat "30,34,1,1,white,blue,0,36bd7045,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 34 34 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 34 34 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[21.44 21.44 25.4" "4 21.44 25.44 25.44 25.44 21.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[17.44 17.44 21.44 21.44 17.44 ]," "[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[13.44 13.44 17.44 17.44 13.44 ],[1 1 1 ]);\npatch([10.1" " 23.88 19.88 15.88 11.88 6.1 10.1 ],[9.44 9.44 13.44 9.44 13.44 13.44 9.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('\\bf{x(-1)}','texm" "ode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Reinterpret" SID "485" Ports [1, 1] Position [900, 331, 935, 349] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can change the signal between s" "igned and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.
Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsig" "ned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111" "000 in binary)." force_arith_type on arith_type "Unsigned" force_bin_pt on bin_pt "0" has_advanced_control "0" sggui_pos "20,20,356,278" block_type "cast" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,18,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 18 18 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[11.22 11.22" " 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[9.22 9.22 11.22 11.22 9" ".22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch" "([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('reinterpret" "');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational" SID "9714" Ports [2, 1] Position [1050, 231, 1095, 269] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "45,38,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 38 38 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 38 38 0 ]);\npatch([10.875 18.1 23.1 28.1 33.1 23.1 15.875 10.875 ],[24.55 24.55 2" "9.55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([15.875 23.1 18.1 10.875 15.875 ],[19.55 19.55 24.55 24.55 " "19.55 ],[0.931 0.946 0.973 ]);\npatch([10.875 18.1 23.1 15.875 10.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1 1 ])" ";\npatch([15.875 33.1 28.1 23.1 18.1 10.875 15.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0.973 ]" ");\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label(" "'input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa = b','texm" "ode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational3" SID "14915" Ports [2, 1] Position [260, 204, 305, 246] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a>=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "45,42,2,1,white,blue,0,6218dc92,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 42 42 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 42 42 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[27.66 27.66 3" "3.66 27.66 33.66 33.66 33.66 27.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[21.66 21.66 27.66 27.66 21" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[15.66 15.66 21.66 21.66 15.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[9.66 9.66 15.66 9.66 15.66 15.66 9.66 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('inpu" "t',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa \\geq b','texmo" "de','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "H_re" SID "486" Position [1220, 373, 1250, 387] IconDisplay "Port number" } Block { BlockType Outport Name "H_im" SID "487" Position [1220, 493, 1250, 507] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "Empty Sc" SID "9715" Position [1275, 223, 1305, 237] Port "3" IconDisplay "Port number" } Line { SrcBlock "Negate" SrcPort 1 DstBlock "Mux" DstPort 4 } Line { SrcBlock "Constant2" SrcPort 1 Points [25, 0] Branch { DstBlock "Mux" DstPort 2 } Branch { Points [0, -125] DstBlock "Relational" DstPort 1 } } Line { SrcBlock "x_re" SrcPort 1 Points [375, 0] Branch { DstBlock "Mux" DstPort 3 } Branch { Points [0, 25] DstBlock "Negate" DstPort 1 } } Line { SrcBlock "x_ind" SrcPort 1 Points [15, 0] Branch { DstBlock "L-LTF" DstPort 1 } Branch { Points [0, 45] DstBlock "HT-LTF" DstPort 1 } } Line { SrcBlock "Mux" SrcPort 1 DstBlock "H_re" DstPort 1 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Mux1" DstPort 2 } Line { SrcBlock "x_im" SrcPort 1 Points [375, 0] Branch { Points [0, 25] DstBlock "Negate1" DstPort 1 } Branch { DstBlock "Mux1" DstPort 3 } } Line { SrcBlock "Mux1" SrcPort 1 DstBlock "H_im" DstPort 1 } Line { SrcBlock "Reinterpret" SrcPort 1 Points [95, 0] Branch { DstBlock "Mux" DstPort 1 } Branch { Points [0, 120] DstBlock "Mux1" DstPort 1 } Branch { DstBlock "Relational" DstPort 2 } } Line { SrcBlock "Negate1" SrcPort 1 DstBlock "Mux1" DstPort 4 } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Mux2" DstPort 1 } Line { SrcBlock "L-LTF" SrcPort 1 DstBlock "Mux2" DstPort 2 } Line { SrcBlock "HT-LTF" SrcPort 1 DstBlock "Mux2" DstPort 3 } Line { SrcBlock "Mux2" SrcPort 1 Points [55, 0; 0, 115] DstBlock "Reinterpret" DstPort 1 } Line { SrcBlock "Relational" SrcPort 1 DstBlock "Logical" DstPort 2 } Line { SrcBlock "Logical" SrcPort 1 DstBlock "Empty Sc" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical" DstPort 1 } Line { SrcBlock "x_valid" SrcPort 1 Points [415, 0; 0, 80] DstBlock "Inverter" DstPort 1 } Line { SrcBlock "From" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Sym Ind" SrcPort 1 DstBlock "Relational3" DstPort 1 } Line { SrcBlock "Constant3" SrcPort 1 DstBlock "Relational3" DstPort 2 } Line { SrcBlock "Relational3" SrcPort 1 Points [55, 0; 0, -25] DstBlock "Logical1" DstPort 2 } Annotation { Name "OFDM Symbols in 11a/g:\n0: LTF (BPSK)\n1: LTF (BPSK)\n2: SIG (BPSK)\n3-N: Data" Position [859, 918] HorizontalAlignment "left" } Annotation { Name "OFDM Symbols in 11n SISO:\n0: L-LTF (BPSK)\n1: L-LTF (BPSK)\n2: L-SIG (BPSK)\n3: HT-SIG1 (QBPSK)\n4: HT-" "SIG2 (QBPSK)\n5: HT-STF\n6: HT-LFT1\n7-N: Data" Position [1009, 943] HorizontalAlignment "left" } Annotation { Name "OFDM Symbols in 11ac SISO:\n0: L-LTF (BPSK)\n1: L-LTF (BPSK)\n2: L-SIG (BPSK)\n3: VHT-SIGA1 (BPSK)\n4: V" "HT-SIGA2 (QBPSK)\n5: VHT-STF\n6: VHT-LFT1\n7: VHT-SIGB\n8-N: Data" Position [1184, 958] HorizontalAlignment "left" } Annotation { Name "Ignore early phy_mode det - only use HT masks\nfor HT-LTF and later symbols" Position [245, 266] } } } Block { BlockType RealImagToComplex Name "Real-Imag to\nComplex" SID "514" Ports [2, 1] Position [1095, 732, 1120, 748] ZOrder -21 ShowName off Input "Real and imag" } Block { BlockType RealImagToComplex Name "Real-Imag to\nComplex1" SID "515" Ports [2, 1] Position [1095, 707, 1120, 723] ZOrder -21 ShowName off Input "Real and imag" } Block { BlockType RealImagToComplex Name "Real-Imag to\nComplex2" SID "10105" Ports [2, 1] Position [1215, 853, 1245, 882] ZOrder -21 Input "Real and imag" } Block { BlockType SubSystem Name "To Float" SID "516" Ports [7, 7] Position [1055, 22, 1160, 258] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "To Float" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "x_I " SID "517" Position [480, 423, 510, 437] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "x_Q " SID "518" Position [480, 463, 510, 477] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "H_I " SID "519" Position [480, 548, 510, 562] NamePlacement "alternate" Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "H_Q " SID "520" Position [480, 573, 510, 587] Port "4" IconDisplay "Port number" } Block { BlockType Inport Name "x_ind" SID "521" Position [355, 733, 385, 747] Port "5" IconDisplay "Port number" } Block { BlockType Inport Name "x_valid" SID "522" Position [355, 628, 385, 642] Port "6" IconDisplay "Port number" } Block { BlockType Inport Name "sym_ind" SID "523" Position [355, 808, 385, 822] Port "7" IconDisplay "Port number" } Block { BlockType Reference Name "Delay1" SID "524" Ports [1, 1] Position [695, 678, 730, 702] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "3" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,24,1,1,white,blue,0,83e6bb61,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[15.33 15" ".33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.33 12.33 15.33" " 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 " "1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');" "disp('z^{-3}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay2" SID "525" Ports [1, 1] Position [695, 728, 730, 752] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "3" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,24,1,1,white,blue,0,83e6bb61,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[15.33 15" ".33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.33 12.33 15.33" " 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 " "1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');" "disp('z^{-3}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay3" SID "526" Ports [1, 1] Position [695, 803, 730, 827] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "3" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,24,1,1,white,blue,0,83e6bb61,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[15.33 15" ".33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.33 12.33 15.33" " 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 " "1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');" "disp('z^{-3}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "527" Ports [1, 1] Position [435, 627, 470, 643] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "35,16,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 16 16 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 16 16 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[10.22 10.22" " 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[8.22 8.22 10.22 10.22 8" ".22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatch" "([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfpr" "intf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register" SID "528" Ports [2, 1] Position [640, 422, 685, 453] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "45,31,2,1,white,blue,0,140cc11c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 31 31 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 31 31 0 ]);\npatch([13.1 18.88 22.88 26.88 30.88 22.88 17.1 13.1 ],[19.44 19.44 23" ".44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([17.1 22.88 18.88 13.1 17.1 ],[15.44 15.44 19.44 19.44 15.44" " ],[0.931 0.946 0.973 ]);\npatch([13.1 18.88 22.88 17.1 13.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch(" "[17.1 30.88 26.88 22.88 18.88 13.1 17.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf" "('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp" "('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "529" Ports [2, 1] Position [640, 462, 685, 493] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "45,31,2,1,white,blue,0,140cc11c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 31 31 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 31 31 0 ]);\npatch([13.1 18.88 22.88 26.88 30.88 22.88 17.1 13.1 ],[19.44 19.44 23" ".44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([17.1 22.88 18.88 13.1 17.1 ],[15.44 15.44 19.44 19.44 15.44" " ],[0.931 0.946 0.973 ]);\npatch([13.1 18.88 22.88 17.1 13.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch(" "[17.1 30.88 26.88 22.88 18.88 13.1 17.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf" "('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp" "('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "530" Ports [2, 1] Position [640, 547, 685, 578] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "45,31,2,1,white,blue,0,140cc11c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 31 31 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 31 31 0 ]);\npatch([13.1 18.88 22.88 26.88 30.88 22.88 17.1 13.1 ],[19.44 19.44 23" ".44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([17.1 22.88 18.88 13.1 17.1 ],[15.44 15.44 19.44 19.44 15.44" " ],[0.931 0.946 0.973 ]);\npatch([13.1 18.88 22.88 17.1 13.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch(" "[17.1 30.88 26.88 22.88 18.88 13.1 17.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf" "('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp" "('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register3" SID "531" Ports [2, 1] Position [640, 572, 685, 603] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "45,31,2,1,white,blue,0,140cc11c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 31 31 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 31 31 0 ]);\npatch([13.1 18.88 22.88 26.88 30.88 22.88 17.1 13.1 ],[19.44 19.44 23" ".44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([17.1 22.88 18.88 13.1 17.1 ],[15.44 15.44 19.44 19.44 15.44" " ],[0.931 0.946 0.973 ]);\npatch([13.1 18.88 22.88 17.1 13.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch(" "[17.1 30.88 26.88 22.88 18.88 13.1 17.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf" "('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp" "('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "To FP1" SID "532" Ports [1, 1] Position [745, 465, 790, 495] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Floating-point" arith_type "Floating-point" n_bits "16" bin_pt "14" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "2" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "45,30,1,1,white,blue,0,b61d041b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\npatch([13.1 18.88 22.88 26.88 30.88 22.88 17.1 13.1 ],[19.44 19.44 23" ".44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([17.1 22.88 18.88 13.1 17.1 ],[15.44 15.44 19.44 19.44 15.44" " ],[0.931 0.946 0.973 ]);\npatch([13.1 18.88 22.88 17.1 13.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch(" "[17.1 30.88 26.88 22.88 18.88 13.1 17.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf" "('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output'," "1,'cast');\ncolor('black');disp('z^{-2}\\newline ','texmode','on');\ncolor('black');disp(' \\n ');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Reference Name "To FP2" SID "533" Ports [1, 1] Position [745, 550, 790, 580] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Floating-point" arith_type "Floating-point" n_bits "16" bin_pt "14" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "2" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "45,30,1,1,white,blue,0,b61d041b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\npatch([13.1 18.88 22.88 26.88 30.88 22.88 17.1 13.1 ],[19.44 19.44 23" ".44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([17.1 22.88 18.88 13.1 17.1 ],[15.44 15.44 19.44 19.44 15.44" " ],[0.931 0.946 0.973 ]);\npatch([13.1 18.88 22.88 17.1 13.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch(" "[17.1 30.88 26.88 22.88 18.88 13.1 17.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf" "('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output'," "1,'cast');\ncolor('black');disp('z^{-2}\\newline ','texmode','on');\ncolor('black');disp(' \\n ');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Reference Name "To FP3" SID "534" Ports [1, 1] Position [745, 575, 790, 605] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Floating-point" arith_type "Floating-point" n_bits "16" bin_pt "14" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "2" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "45,30,1,1,white,blue,0,b61d041b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\npatch([13.1 18.88 22.88 26.88 30.88 22.88 17.1 13.1 ],[19.44 19.44 23" ".44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([17.1 22.88 18.88 13.1 17.1 ],[15.44 15.44 19.44 19.44 15.44" " ],[0.931 0.946 0.973 ]);\npatch([13.1 18.88 22.88 17.1 13.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch(" "[17.1 30.88 26.88 22.88 18.88 13.1 17.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf" "('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output'," "1,'cast');\ncolor('black');disp('z^{-2}\\newline ','texmode','on');\ncolor('black');disp(' \\n ');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Reference Name "To FP4" SID "535" Ports [1, 1] Position [745, 425, 790, 455] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Floating-point" arith_type "Floating-point" n_bits "16" bin_pt "14" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "2" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "45,30,1,1,white,blue,0,b61d041b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\npatch([13.1 18.88 22.88 26.88 30.88 22.88 17.1 13.1 ],[19.44 19.44 23" ".44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([17.1 22.88 18.88 13.1 17.1 ],[15.44 15.44 19.44 19.44 15.44" " ],[0.931 0.946 0.973 ]);\npatch([13.1 18.88 22.88 17.1 13.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch(" "[17.1 30.88 26.88 22.88 18.88 13.1 17.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf" "('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output'," "1,'cast');\ncolor('black');disp('z^{-2}\\newline ','texmode','on');\ncolor('black');disp(' \\n ');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Outport Name " x_I" SID "536" Position [895, 433, 925, 447] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Outport Name " x_Q" SID "537" Position [895, 473, 925, 487] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "H_I" SID "538" Position [895, 558, 925, 572] NamePlacement "alternate" Port "3" IconDisplay "Port number" } Block { BlockType Outport Name " H_Q" SID "539" Position [895, 583, 925, 597] Port "4" IconDisplay "Port number" } Block { BlockType Outport Name " x_ind" SID "540" Position [895, 733, 925, 747] Port "5" IconDisplay "Port number" } Block { BlockType Outport Name " x_valid" SID "541" Position [895, 683, 925, 697] Port "6" IconDisplay "Port number" } Block { BlockType Outport Name " sym_ind" SID "542" Position [895, 808, 925, 822] Port "7" IconDisplay "Port number" } Line { SrcBlock "To FP3" SrcPort 1 DstBlock " H_Q" DstPort 1 } Line { SrcBlock "To FP2" SrcPort 1 DstBlock "H_I" DstPort 1 } Line { SrcBlock "To FP1" SrcPort 1 DstBlock " x_Q" DstPort 1 } Line { SrcBlock "To FP4" SrcPort 1 DstBlock " x_I" DstPort 1 } Line { SrcBlock "Register3" SrcPort 1 DstBlock "To FP3" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "To FP2" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 Points [85, 0; 0, -40] Branch { DstBlock "Register3" DstPort 2 } Branch { Points [0, -25] Branch { DstBlock "Register2" DstPort 2 } Branch { Points [0, -85] Branch { DstBlock "Register1" DstPort 2 } Branch { Points [0, -40] DstBlock "Register" DstPort 2 } } } } Line { SrcBlock "Register1" SrcPort 1 DstBlock "To FP1" DstPort 1 } Line { SrcBlock "Register" SrcPort 1 DstBlock "To FP4" DstPort 1 } Line { SrcBlock "x_I " SrcPort 1 DstBlock "Register" DstPort 1 } Line { SrcBlock "x_Q " SrcPort 1 DstBlock "Register1" DstPort 1 } Line { SrcBlock "H_I " SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "H_Q " SrcPort 1 DstBlock "Register3" DstPort 1 } Line { SrcBlock "x_valid" SrcPort 1 Points [15, 0] Branch { DstBlock "Inverter" DstPort 1 } Branch { Points [0, 55] DstBlock "Delay1" DstPort 1 } } Line { SrcBlock "Delay1" SrcPort 1 DstBlock " x_valid" DstPort 1 } Line { SrcBlock "x_ind" SrcPort 1 DstBlock "Delay2" DstPort 1 } Line { SrcBlock "Delay2" SrcPort 1 DstBlock " x_ind" DstPort 1 } Line { SrcBlock "sym_ind" SrcPort 1 DstBlock "Delay3" DstPort 1 } Line { SrcBlock "Delay3" SrcPort 1 DstBlock " sym_ind" DstPort 1 } } } Block { BlockType ToWorkspace Name "To Workspace" SID "10106" Ports [1] Position [1280, 855, 1340, 885] ZOrder -7 VariableName "pre_eq" MaxDataPoints "inf" SampleTime "-1" SaveFormat "Array" } Block { BlockType ToWorkspace Name "To Workspace1" SID "10107" Ports [1] Position [1280, 775, 1340, 805] ZOrder -7 VariableName "pre_eq_valid" MaxDataPoints "inf" SampleTime "-1" SaveFormat "Array" } Block { BlockType Outport Name " x_I" SID "543" Position [1230, 28, 1260, 42] IconDisplay "Port number" } Block { BlockType Outport Name " x_Q" SID "544" Position [1230, 63, 1260, 77] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "H_I" SID "545" Position [1230, 98, 1260, 112] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "H_Q" SID "546" Position [1230, 133, 1260, 147] Port "4" IconDisplay "Port number" } Block { BlockType Outport Name " valid" SID "547" Position [1230, 203, 1260, 217] Port "5" IconDisplay "Port number" } Block { BlockType Outport Name " x_ind" SID "548" Position [1230, 168, 1260, 182] Port "6" IconDisplay "Port number" } Block { BlockType Outport Name " sym_ind" SID "549" Position [1230, 238, 1260, 252] Port "7" IconDisplay "Port number" } Line { SrcBlock "Logical2" SrcPort 1 Points [0, 5] DstBlock "Estimate Buffers" DstPort 4 } Line { SrcBlock "x_valid" SrcPort 1 Points [235, 0] Branch { Points [0, -15] DstBlock "Mult by LTF" DstPort 4 } Branch { Points [0, 5] Branch { Points [0, 230] DstBlock "Logical1" DstPort 1 } Branch { DstBlock "Logical2" DstPort 1 } } } Line { SrcBlock "Sym Ind" SrcPort 1 Points [35, 0] Branch { Labels [0, 0] DstBlock "Control" DstPort 1 } Branch { Points [0, 225] DstBlock "Delay2" DstPort 1 } Branch { Points [0, -90] DstBlock "Mult by LTF" DstPort 3 } } Line { Labels [0, 0] SrcBlock "Control" SrcPort 2 DstBlock "Estimate Buffers" DstPort 5 } Line { SrcBlock "Control" SrcPort 1 DstBlock "Logical2" DstPort 2 } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Logical3" DstPort 2 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical1" DstPort 2 } Line { SrcBlock "Estimate Buffers" SrcPort 2 Points [85, 0] Branch { Points [0, 335] DstBlock "Gateway Out3" DstPort 1 } Branch { Points [30, 0] Branch { Points [0, -140] DstBlock "To Float" DstPort 4 } Branch { Points [0, 55] DstBlock "Chan Est Offload" DstPort 3 } } } Line { Name "x_I" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 Points [10, 0] Branch { Points [0, 195] DstBlock "Real-Imag to\nComplex" DstPort 1 } Branch { DstBlock "H Est Outputs" DstPort 1 } } Line { Name "x_Q" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 Points [5, 0] Branch { Points [0, 180] DstBlock "Real-Imag to\nComplex" DstPort 2 } Branch { DstBlock "H Est Outputs" DstPort 2 } } Line { Name "H_I" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 Points [20, 0] Branch { DstBlock "Real-Imag to\nComplex1" DstPort 1 } Branch { DstBlock "H Est Outputs" DstPort 3 } } Line { Name "H_Q" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 Points [15, 0] Branch { Points [0, 105] DstBlock "Real-Imag to\nComplex1" DstPort 2 } Branch { DstBlock "H Est Outputs" DstPort 4 } } Line { Name "SC Ind" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 DstBlock "H Est Outputs" DstPort 5 } Line { Name "Valid Out" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 DstBlock "H Est Outputs" DstPort 7 } Line { SrcBlock "x_ind" SrcPort 1 Points [30, 0] Branch { Points [185, 0] Branch { Points [0, -70] DstBlock "Estimate Buffers" DstPort 7 } Branch { DstBlock "Delay5" DstPort 1 } } Branch { Points [0, -165] DstBlock "Mult by LTF" DstPort 5 } } Line { SrcBlock "x_re" SrcPort 1 Points [175, 0] Branch { Points [0, 115] DstBlock "Mult by LTF" DstPort 1 } Branch { DstBlock "Delay3" DstPort 1 } } Line { SrcBlock "x_im" SrcPort 1 Points [170, 0] Branch { Points [0, 95] DstBlock "Mult by LTF" DstPort 2 } Branch { DstBlock "Delay4" DstPort 1 } } Line { SrcBlock "Mult by LTF" SrcPort 2 Points [15, 0] Branch { DstBlock "Estimate Buffers" DstPort 2 } Branch { Points [0, 385] Branch { DstBlock "Gateway Out1" DstPort 1 } Branch { Points [0, 310] DstBlock "Gateway Out13" DstPort 1 } } } Line { SrcBlock "Mult by LTF" SrcPort 1 Points [30, 0] Branch { DstBlock "Estimate Buffers" DstPort 1 } Branch { Points [0, 385] Branch { DstBlock "Gateway Out8" DstPort 1 } Branch { Points [0, 320] DstBlock "Gateway Out12" DstPort 1 } } } Line { SrcBlock "To Float" SrcPort 1 DstBlock " x_I" DstPort 1 } Line { SrcBlock "To Float" SrcPort 2 DstBlock " x_Q" DstPort 1 } Line { SrcBlock "To Float" SrcPort 3 DstBlock "H_I" DstPort 1 } Line { SrcBlock "To Float" SrcPort 4 DstBlock "H_Q" DstPort 1 } Line { SrcBlock "To Float" SrcPort 5 DstBlock " x_ind" DstPort 1 } Line { SrcBlock "To Float" SrcPort 6 DstBlock " valid" DstPort 1 } Line { SrcBlock "To Float" SrcPort 7 DstBlock " sym_ind" DstPort 1 } Line { SrcBlock "Abs" SrcPort 1 DstBlock "H Est Outputs" DstPort 9 } Line { SrcBlock "Real-Imag to\nComplex" SrcPort 1 DstBlock "Abs" DstPort 1 } Line { SrcBlock "Real-Imag to\nComplex1" SrcPort 1 DstBlock "Abs1" DstPort 1 } Line { SrcBlock "Abs1" SrcPort 1 DstBlock "H Est Outputs" DstPort 8 } Line { Name "Sym Ind" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 DstBlock "H Est Outputs" DstPort 6 } Line { SrcBlock "Control" SrcPort 3 DstBlock "Estimate Buffers" DstPort 6 } Line { SrcBlock "Control" SrcPort 4 Points [20, 0; 0, 160] DstBlock "Inverter" DstPort 1 } Line { Labels [1, 0] SrcBlock "Estimate Buffers" SrcPort 1 Points [90, 0] Branch { Points [0, 405] DstBlock "Gateway Out2" DstPort 1 } Branch { Points [20, 0] Branch { Points [0, -80] DstBlock "To Float" DstPort 3 } Branch { Points [0, 140] DstBlock "Chan Est Offload" DstPort 2 } } } Line { SrcBlock "Mult by LTF" SrcPort 3 Points [10, 0] Branch { DstBlock "Estimate Buffers" DstPort 3 } Branch { Points [0, 230] DstBlock "Inverter1" DstPort 1 } } Line { SrcBlock "Delay5" SrcPort 1 Points [50, 0] Branch { Points [0, 265] DstBlock "Gateway Out4" DstPort 1 } Branch { Points [100, 0; 0, -60] Branch { Points [0, -140] DstBlock "To Float" DstPort 5 } Branch { DstBlock "Chan Est Offload" DstPort 1 } } } Line { SrcBlock "Delay1" SrcPort 1 Points [25, 0] Branch { Points [145, 0; 0, -100] Branch { DstBlock "Chan Est Offload" DstPort 4 } Branch { Points [0, -135] DstBlock "To Float" DstPort 6 } } Branch { Points [0, 245] Branch { DstBlock "Gateway Out5" DstPort 1 } Branch { Points [0, 100] DstBlock "Gateway Out7" DstPort 1 } } } Line { SrcBlock "Delay2" SrcPort 1 Points [35, 0] Branch { Points [150, 0; 0, -140] Branch { Points [0, -110] DstBlock "To Float" DstPort 7 } Branch { Labels [0, 0] DstBlock "Chan Est Offload" DstPort 5 } } Branch { Points [0, 170] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "Delay4" SrcPort 1 DstBlock "To Float" DstPort 2 } Line { SrcBlock "Delay3" SrcPort 1 DstBlock "To Float" DstPort 1 } Line { SrcBlock "Gateway Out12" SrcPort 1 DstBlock "Real-Imag to\nComplex2" DstPort 1 } Line { SrcBlock "Gateway Out13" SrcPort 1 DstBlock "Real-Imag to\nComplex2" DstPort 2 } Line { SrcBlock "Real-Imag to\nComplex2" SrcPort 1 DstBlock "To Workspace" DstPort 1 } Line { SrcBlock "Gateway Out7" SrcPort 1 DstBlock "To Workspace1" DstPort 1 } Line { SrcBlock "Logical3" SrcPort 1 DstBlock "Delay1" DstPort 1 } Line { SrcBlock "Inverter1" SrcPort 1 DstBlock "Logical3" DstPort 1 } } } Block { BlockType SubSystem Name "Debug Outputs" SID "550" Ports [4] Position [800, 482, 870, 543] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Debug Outputs" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "80" Block { BlockType Inport Name "I" SID "551" Position [390, 423, 420, 437] IconDisplay "Port number" } Block { BlockType Inport Name "Q" SID "552" Position [390, 458, 420, 472] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "valid" SID "553" Position [380, 533, 410, 547] NamePlacement "alternate" Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "x_ind" SID "554" Position [380, 573, 410, 587] Port "4" IconDisplay "Port number" } Block { BlockType SubSystem Name "4x Buffer" SID "555" Ports [3, 3] Position [1235, 411, 1295, 519] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "4x Buffer" Location [1002, 291, 1570, 505] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "136" Block { BlockType Inport Name "I" SID "556" Position [245, 258, 275, 272] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "Q" SID "557" Position [245, 283, 275, 297] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "Vin" SID "558" Position [400, 308, 430, 322] Port "3" IconDisplay "Port number" } Block { BlockType Reference Name "14LSB" SID "559" Ports [1, 1] Position [660, 266, 690, 284] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type" " is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardw" "are notes: In hardware this block costs nothing." nbits "14" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "30,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 18 18 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[11.22 11.22" " 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[9.22 9.22 11.22 11.22 9" ".22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch" "([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output'" ",1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "14MSB" SID "560" Ports [1, 1] Position [660, 241, 690, 259] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type" " is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardw" "are notes: In hardware this block costs nothing." nbits "14" boolean_output off mode "Upper Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "30,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 18 18 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[11.22 11.22" " 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[9.22 9.22 11.22 11.22 9" ".22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch" "([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output'" ",1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Concat" SID "561" Ports [2, 1] Position [400, 253, 430, 302] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point at z" "ero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "30,49,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 49 49 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 49 49 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[28.44 28.44 32.4" "4 28.44 32.44 32.44 32.44 28.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[24.44 24.44 28.44 28.44 24.44 ]," "[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[20.44 20.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([10.1" " 23.88 19.88 15.88 11.88 6.1 10.1 ],[16.44 16.44 20.44 16.44 20.44 20.44 16.44 ],[0.931 0.946 0.973 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'hi" "');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fontsize{20}\\}','texmode','on');\nfprin" "tf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant3" SID "562" Ports [0, 1] Position [445, 345, 465, 365] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Boolean" arith_type "Boolean" n_bits "5" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period on period "4" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "20,20,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 20 20 0 0 ],[0 0 20 20 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[12.22 12.22 14." "22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[10.22 10.22 12.22 12.22 10.22 ]" ",[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatch([7.55 " "14.44 12.44 10.44 8.44 5.55 7.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nfpr" "intf('','COMMENT: end icon text');" } Block { BlockType Reference Name "FIFO" SID "563" Ports [3, 3] Position [505, 258, 585, 372] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/FIFO" SourceType "Xilinx FIFO Block Block" mem_type "Block RAM" performance_options "Standard_FIFO" infoedit1 "Available only for V4, V5, V6, V7, K7, A7 and Zynq devices." embedded_registers off depth "64" percent_nbits "1" rst off en off use_dcount off use_percent_full_port off use_almost_empty off almost_empty_thresh "2" use_almost_full off almost_full_thresh "14" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" explicit_period "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "fifo" sg_icon_stat "80,114,3,3,white,blue,0,375ec951,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 80 80 0 0 ],[0 0 114 114 0 ],[0.77 0.82 0" ".91 ]);\nplot([0 80 80 0 0 ],[0 0 114 114 0 ]);\npatch([15.525 31.42 42.42 53.42 64.42 42.42 26.525 15.525 ],[69.2" "1 69.21 80.21 69.21 80.21 80.21 80.21 69.21 ],[1 1 1 ]);\npatch([26.525 42.42 31.42 15.525 26.525 ],[58.21 58.21 6" "9.21 69.21 58.21 ],[0.931 0.946 0.973 ]);\npatch([15.525 31.42 42.42 26.525 15.525 ],[47.21 47.21 58.21 58.21 47.2" "1 ],[1 1 1 ]);\npatch([26.525 64.42 53.42 42.42 31.42 15.525 26.525 ],[36.21 36.21 47.21 36.21 47.21 47.21 36.21 ]" ",[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor" "('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'we');\ncolor('black');port_label('inp" "ut',3,'re');\ncolor('black');port_label('output',1,'dout');\ncolor('black');port_label('output',2,'empty');\ncolor" "('black');port_label('output',3,'full');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Reinterpret" SID "564" Ports [1, 1] Position [310, 255, 340, 275] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can change the signal between s" "igned and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.
Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsig" "ned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111" "000 in binary)." force_arith_type on arith_type "Unsigned" force_bin_pt on bin_pt "0" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "reinterpret" sg_icon_stat "30,20,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 20 20 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[12.22 12.22" " 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[10.22 10.22 12.22 12.22" " 10.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\n" "patch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('reinte" "rpret');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Reinterpret1" SID "565" Ports [1, 1] Position [310, 280, 340, 300] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can change the signal between s" "igned and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.
Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsig" "ned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111" "000 in binary)." force_arith_type on arith_type "Unsigned" force_bin_pt on bin_pt "0" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "reinterpret" sg_icon_stat "30,20,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 20 20 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[12.22 12.22" " 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[10.22 10.22 12.22 12.22" " 10.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\n" "patch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('reinte" "rpret');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Reinterpret2" SID "566" Ports [1, 1] Position [730, 240, 760, 260] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can change the signal between s" "igned and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.
Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsig" "ned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111" "000 in binary)." force_arith_type on arith_type "Signed (2's comp)" force_bin_pt on bin_pt "13" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "reinterpret" sg_icon_stat "30,20,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 20 20 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[12.22 12.22" " 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[10.22 10.22 12.22 12.22" " 10.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\n" "patch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('reinte" "rpret');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Reinterpret3" SID "567" Ports [1, 1] Position [730, 265, 760, 285] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can change the signal between s" "igned and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.
Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsig" "ned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111" "000 in binary)." force_arith_type on arith_type "Signed (2's comp)" force_bin_pt on bin_pt "13" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "reinterpret" sg_icon_stat "30,20,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 20 20 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[12.22 12.22" " 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[10.22 10.22 12.22 12.22" " 10.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\n" "patch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('reinte" "rpret');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Up Sample" SID "568" Ports [1, 1] Position [815, 237, 840, 263] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Up Sample" SourceType "Xilinx Up Sampler Block" infoedit "Up samples input data. Inserted values can be zeros or copies of the most recent input sample.
<" "br>Hardware notes: No hardware is needed if inserted values are copies of the input sample; otherwise, a mux and s" "ingle bit flip-flop are used." sample_ratio "4" copy_samples on en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "usamp" sg_icon_stat "25,26,1,1,white,blue,0,a300b05e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 " "19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 1" "3.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\n" "patch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('{\\fo" "ntsize{14pt}\\bf\\uparrow}4','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Up Sample1" SID "569" Ports [1, 1] Position [815, 262, 840, 288] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Up Sample" SourceType "Xilinx Up Sampler Block" infoedit "Up samples input data. Inserted values can be zeros or copies of the most recent input sample.
<" "br>Hardware notes: No hardware is needed if inserted values are copies of the input sample; otherwise, a mux and s" "ingle bit flip-flop are used." sample_ratio "4" copy_samples on en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "usamp" sg_icon_stat "25,26,1,1,white,blue,0,a300b05e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 " "19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 1" "3.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\n" "patch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('{\\fo" "ntsize{14pt}\\bf\\uparrow}4','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name " I" SID "570" Position [875, 243, 905, 257] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Outport Name " Q" SID "571" Position [875, 268, 905, 282] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "#Vout" SID "572" Position [875, 308, 905, 322] Port "3" IconDisplay "Port number" } Line { SrcBlock "Constant3" SrcPort 1 DstBlock "FIFO" DstPort 3 } Line { SrcBlock "Concat" SrcPort 1 DstBlock "FIFO" DstPort 1 } Line { SrcBlock "I" SrcPort 1 DstBlock "Reinterpret" DstPort 1 } Line { SrcBlock "14MSB" SrcPort 1 DstBlock "Reinterpret2" DstPort 1 } Line { SrcBlock "Q" SrcPort 1 DstBlock "Reinterpret1" DstPort 1 } Line { SrcBlock "14LSB" SrcPort 1 DstBlock "Reinterpret3" DstPort 1 } Line { SrcBlock "Vin" SrcPort 1 DstBlock "FIFO" DstPort 2 } Line { SrcBlock "FIFO" SrcPort 2 DstBlock "#Vout" DstPort 1 } Line { SrcBlock "Reinterpret" SrcPort 1 DstBlock "Concat" DstPort 1 } Line { SrcBlock "Reinterpret1" SrcPort 1 DstBlock "Concat" DstPort 2 } Line { SrcBlock "Reinterpret2" SrcPort 1 DstBlock "Up Sample" DstPort 1 } Line { SrcBlock "Reinterpret3" SrcPort 1 DstBlock "Up Sample1" DstPort 1 } Line { SrcBlock "Up Sample" SrcPort 1 DstBlock " I" DstPort 1 } Line { SrcBlock "Up Sample1" SrcPort 1 DstBlock " Q" DstPort 1 } Line { SrcBlock "FIFO" SrcPort 1 Points [35, 0] Branch { DstBlock "14LSB" DstPort 1 } Branch { Points [0, -25] DstBlock "14MSB" DstPort 1 } } } } Block { BlockType Reference Name "Constant" SID "573" Ports [0, 1] Position [465, 597, 495, 623] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,26,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[" "16.33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 1" "3.33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13." "33 10.33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\ncolor('black');port_label('output',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant1" SID "574" Ports [0, 1] Position [465, 677, 495, 703] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "27" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "5" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,26,0,1,white,blue,0,63edda7d,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[" "16.33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 1" "3.33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13." "33 10.33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\ncolor('black');port_label('output',1,'27');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant2" SID "575" Ports [0, 1] Position [465, 742, 495, 768] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "37" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "6" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,26,0,1,white,blue,0,cd6148db,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[" "16.33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 1" "3.33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13." "33 10.33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\ncolor('black');port_label('output',1,'37');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant3" SID "8474" Ports [0, 1] Position [465, 817, 495, 843] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "29" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "5" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,26,0,1,white,blue,0,c108aa3c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[" "16.33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 1" "3.33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13." "33 10.33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\ncolor('black');port_label('output',1,'29');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant4" SID "8475" Ports [0, 1] Position [465, 882, 495, 908] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "35" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "6" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,26,0,1,white,blue,0,c201f606,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[" "16.33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 1" "3.33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13." "33 10.33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\ncolor('black');port_label('output',1,'35');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Scope Name "Debug EQ IQ" SID "576" Ports [7] Position [1750, 613, 1790, 787] ZOrder -3 Floating off Location [5, 430, 2480, 1588] Open off NumInputPorts "7" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" } List { ListType ScopeGraphics FigureColor "[0.5 0.5 0.5]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } YMin "-1.1~-1~-1.1~-1~-5~-5~-5" YMax "1.1~1~1.2~1~5~5~5" SaveName "ScopeData13" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType Reference Name "Delay" SID "577" Ports [1, 1] Position [1150, 668, 1180, 692] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "30,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 24 24 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 24 24 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[" "15.33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[12.33 1" "2.33 15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[9.33 9.33 12.33 12.33" " 9.33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ]," "[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n" "color('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay1" SID "578" Ports [1, 1] Position [465, 528, 495, 552] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "30,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 24 24 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 24 24 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[" "15.33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[12.33 1" "2.33 15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[9.33 9.33 12.33 12.33" " 9.33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ]," "[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n" "color('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "8479" Position [615, 613, 780, 637] ZOrder -9 ShowName off GotoTag "RX_PHY_MODE_11N_AC" TagVisibility "global" } Block { BlockType Reference Name "Gateway Out12" SID "579" Ports [1, 1] Position [1645, 1004, 1680, 1016] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out13" SID "580" Ports [1, 1] Position [1645, 1019, 1680, 1031] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out8" SID "581" Ports [1, 1] Position [1645, 934, 1680, 946] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Goto Name "Goto" SID "582" Position [1475, 571, 1545, 589] ZOrder -10 ShowName off GotoTag "CS_EQ_I" TagVisibility "global" } Block { BlockType Goto Name "Goto1" SID "583" Position [1475, 621, 1545, 639] ZOrder -10 ShowName off GotoTag "CS_EQ_Q" TagVisibility "global" } Block { BlockType Goto Name "Goto2" SID "584" Position [1475, 671, 1545, 689] ZOrder -10 ShowName off GotoTag "CS_EQ_Valid" TagVisibility "global" } Block { BlockType Reference Name "Inverter1" SID "585" Ports [1, 1] Position [1065, 576, 1100, 594] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "35,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 18 18 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[1" "1.22 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[9.22 9.22 " "11.22 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[7.22 7.22 9.22 9.22 7.22 ],[" "1 1 1 ]);\npatch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('bla" "ck');disp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical" SID "586" Ports [3, 1] Position [875, 555, 930, 615] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "55,60,3,1,white,blue,0,98d76266,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 60 60 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ]" ",[37.77 37.77 44.77 37.77 44.77 44.77 44.77 37.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[30.7" "7 30.77 37.77 37.77 30.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[23.77 23.77 30.7" "7 30.77 23.77 ],[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[16.77 16.77 23.77 16.77 23.7" "7 23.77 16.77 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin i" "con text');\n\n\n\n\ncolor('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "587" Ports [2, 1] Position [630, 647, 660, 778] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "30,131,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 131 131 0 ],[0.77" " 0.82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 131 131 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[69" ".44 69.44 73.44 69.44 73.44 73.44 73.44 69.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[65.44 65.44 69." "44 69.44 65.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[61.44 61.44 65.44 65.44 61.44 ],[1 " "1 1 ]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[57.44 57.44 61.44 57.44 61.44 61.44 57.44 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('" "black');disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "8476" Ports [2, 1] Position [630, 787, 660, 918] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "30,131,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 131 131 0 ],[0.77" " 0.82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 131 131 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[69" ".44 69.44 73.44 69.44 73.44 73.44 73.44 69.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[65.44 65.44 69." "44 69.44 65.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[61.44 61.44 65.44 65.44 61.44 ],[1 " "1 1 ]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[57.44 57.44 61.44 57.44 61.44 61.44 57.44 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('" "black');disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux" SID "8480" Ports [3, 1] Position [815, 678, 845, 812] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "30,134,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 19.1429 114.857 134" " 0 ],[0.77 0.82 0.91 ]);\nplot([0 30 30 0 0 ],[0 19.1429 114.857 134 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 " "15.88 10.1 6.1 ],[71.44 71.44 75.44 71.44 75.44 75.44 75.44 71.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10." "1 ],[67.44 67.44 71.44 71.44 67.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[63.44 63.44 67." "44 67.44 63.44 ],[1 1 1 ]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[59.44 59.44 63.44 59.44 63.44 63.4" "4 59.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon te" "xt');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');" "port_label('input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" } Block { BlockType RealImagToComplex Name "Real-Imag to\nComplex" SID "588" Ports [2, 1] Position [1720, 1003, 1750, 1032] ZOrder -21 Input "Real and imag" } Block { BlockType Reference Name "Register" SID "589" Ports [1, 1] Position [465, 565, 495, 595] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 30 30 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 30 30 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 " "19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 1" "9.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "590" Ports [1, 1] Position [465, 415, 495, 445] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 30 30 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 30 30 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 " "19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 1" "9.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "591" Ports [1, 1] Position [465, 450, 495, 480] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 30 30 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 30 30 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 " "19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 1" "9.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register3" SID "592" Ports [2, 1] Position [1145, 562, 1190, 593] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "45,31,2,1,white,blue,0,140cc11c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 31 31 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 31 31 0 ]);\npatch([13.1 18.88 22.88 26.88 30.88 22.88 17.1 13.1 ],[19.4" "4 19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([17.1 22.88 18.88 13.1 17.1 ],[15.44 15.44 19.4" "4 19.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([13.1 18.88 22.88 17.1 13.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1" " 1 1 ]);\npatch([17.1 30.88 26.88 22.88 18.88 13.1 17.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946" " 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'" "q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register4" SID "593" Ports [2, 1] Position [1385, 422, 1430, 453] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "45,31,2,1,white,blue,0,140cc11c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 31 31 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 31 31 0 ]);\npatch([13.1 18.88 22.88 26.88 30.88 22.88 17.1 13.1 ],[19.4" "4 19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([17.1 22.88 18.88 13.1 17.1 ],[15.44 15.44 19.4" "4 19.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([13.1 18.88 22.88 17.1 13.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1" " 1 1 ]);\npatch([17.1 30.88 26.88 22.88 18.88 13.1 17.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946" " 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'" "q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register5" SID "594" Ports [2, 1] Position [1385, 457, 1430, 488] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "45,31,2,1,white,blue,0,140cc11c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 31 31 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 31 31 0 ]);\npatch([13.1 18.88 22.88 26.88 30.88 22.88 17.1 13.1 ],[19.4" "4 19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([17.1 22.88 18.88 13.1 17.1 ],[15.44 15.44 19.4" "4 19.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([13.1 18.88 22.88 17.1 13.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1" " 1 1 ]);\npatch([17.1 30.88 26.88 22.88 18.88 13.1 17.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946" " 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'" "q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register6" SID "595" Ports [2, 1] Position [1145, 612, 1190, 643] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "45,31,2,1,white,blue,0,140cc11c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 31 31 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 31 31 0 ]);\npatch([13.1 18.88 22.88 26.88 30.88 22.88 17.1 13.1 ],[19.4" "4 19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([17.1 22.88 18.88 13.1 17.1 ],[15.44 15.44 19.4" "4 19.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([13.1 18.88 22.88 17.1 13.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1" " 1 1 ]);\npatch([17.1 30.88 26.88 22.88 18.88 13.1 17.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946" " 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'" "q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register7" SID "596" Ports [1, 1] Position [1495, 425, 1525, 455] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 30 30 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 30 30 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 " "19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 1" "9.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register8" SID "597" Ports [1, 1] Position [1495, 460, 1525, 490] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 30 30 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 30 30 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 " "19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 1" "9.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational" SID "598" Ports [2, 1] Position [565, 567, 600, 623] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a!=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,56,2,1,white,blue,0,850de6e7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 56 56 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 56 56 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[33.55" " 33.55 38.55 33.55 38.55 38.55 38.55 33.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[28.55 28.55 33" ".55 33.55 28.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[23.55 23.55 28.55 28.55 23.55 " "],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[18.55 18.55 23.55 18.55 23.55 23.55 18.55 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor(" "'black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('outp" "ut',1,'\\bfa \\neq b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational1" SID "599" Ports [2, 1] Position [565, 650, 600, 705] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "ab" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,55,2,1,white,blue,0,b5131c97,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 55 55 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 55 55 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[32.55" " 32.55 37.55 32.55 37.55 37.55 37.55 32.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[27.55 27.55 32" ".55 32.55 27.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[22.55 22.55 27.55 27.55 22.55 " "],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[17.55 17.55 22.55 17.55 22.55 22.55 17.55 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor(" "'black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('outp" "ut',1,'\\bfa > b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational3" SID "8477" Ports [2, 1] Position [565, 790, 600, 845] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "ab" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,55,2,1,white,blue,0,b5131c97,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 55 55 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 55 55 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[32.55" " 32.55 37.55 32.55 37.55 37.55 37.55 32.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[27.55 27.55 32" ".55 32.55 27.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[22.55 22.55 27.55 27.55 22.55 " "],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[17.55 17.55 22.55 17.55 22.55 22.55 17.55 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor(" "'black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('outp" "ut',1,'\\bfa > b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "To FP1" SID "601" Ports [1, 1] Position [1030, 458, 1060, 472] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do" " not." gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "14" bin_pt "13" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Saturate" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "30,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 14 14 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 14 14 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[9" ".22 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[7.22 7.22 9.22" " 9.22 7.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 " "]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');por" "t_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "To FP4" SID "602" Ports [1, 1] Position [1030, 423, 1060, 437] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do" " not." gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "14" bin_pt "13" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Saturate" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "30,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 14 14 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 14 14 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[9" ".22 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[7.22 7.22 9.22" " 9.22 7.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 " "]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');por" "t_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType ToWorkspace Name "To Workspace" SID "603" Ports [1] Position [1785, 1005, 1845, 1035] ZOrder -7 VariableName "eq_out" MaxDataPoints "inf" SampleTime "-1" SaveFormat "Array" } Block { BlockType ToWorkspace Name "To Workspace1" SID "604" Ports [1] Position [1785, 925, 1845, 955] ZOrder -7 VariableName "eq_out_valid" MaxDataPoints "inf" SampleTime "-1" SaveFormat "Array" } Block { BlockType Reference Name "dbg_EQ_I" SID "606" Ports [1, 1] Position [1570, 430, 1630, 450] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[1" "2.22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.2" "2 12.22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.2" "2 ],[1 1 1 ]);\npatch([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985" " 0.979 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','o" "n');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "dbg_EQ_Q" SID "607" Ports [1, 1] Position [1570, 465, 1630, 485] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[1" "2.22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.2" "2 12.22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.2" "2 ],[1 1 1 ]);\npatch([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985" " 0.979 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','o" "n');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "dbg_EQ_Q1" SID "608" Ports [1, 1] Position [1670, 743, 1700, 757] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,14,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 14 14 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 30 30 0 0 ],[0 0 14 14 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[9" ".22 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[7.22 7.22 9.22" " 9.22 7.22 ],[0.964 0.964 0.964 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 " "]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.964 0.964 0.96" "4 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('" "','COMMENT: end icon text');" } Block { BlockType Reference Name "dbg_EQ_Q2" SID "609" Ports [1, 1] Position [1670, 768, 1700, 782] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,14,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 14 14 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 30 30 0 0 ],[0 0 14 14 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[9" ".22 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[7.22 7.22 9.22" " 9.22 7.22 ],[0.964 0.964 0.964 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 " "]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.964 0.964 0.96" "4 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('" "','COMMENT: end icon text');" } Block { BlockType Reference Name "dbg_EQ_Q3" SID "610" Ports [1, 1] Position [1670, 718, 1700, 732] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,14,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 14 14 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 30 30 0 0 ],[0 0 14 14 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[9" ".22 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[7.22 7.22 9.22" " 9.22 7.22 ],[0.964 0.964 0.964 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 " "]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.964 0.964 0.96" "4 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('" "','COMMENT: end icon text');" } Block { BlockType Reference Name "dbg_EQ_Q4" SID "611" Ports [1, 1] Position [1625, 643, 1655, 657] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,14,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 14 14 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 30 30 0 0 ],[0 0 14 14 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[9" ".22 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[7.22 7.22 9.22" " 9.22 7.22 ],[0.964 0.964 0.964 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 " "]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.964 0.964 0.96" "4 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('" "','COMMENT: end icon text');" } Line { SrcBlock "Inverter1" SrcPort 1 Points [15, 0] Branch { DstBlock "Register3" DstPort 2 } Branch { Points [0, 50] DstBlock "Register6" DstPort 2 } } Line { SrcBlock "Logical" SrcPort 1 Points [35, 0] Branch { DstBlock "Inverter1" DstPort 1 } Branch { Points [0, 95] Branch { DstBlock "Delay" DstPort 1 } Branch { Points [0, 260] DstBlock "Gateway Out8" DstPort 1 } } Branch { Points [0, -85] DstBlock "4x Buffer" DstPort 3 } } Line { SrcBlock "Register2" SrcPort 1 Points [500, 0] Branch { DstBlock "To FP1" DstPort 1 } Branch { Points [0, 155] Branch { DstBlock "Register6" DstPort 1 } Branch { Points [0, 405] DstBlock "Gateway Out13" DstPort 1 } } } Line { SrcBlock "Register1" SrcPort 1 Points [505, 0] Branch { DstBlock "To FP4" DstPort 1 } Branch { Points [0, 140] Branch { DstBlock "Register3" DstPort 1 } Branch { Points [0, 440] DstBlock "Gateway Out12" DstPort 1 } } } Line { SrcBlock "x_ind" SrcPort 1 DstBlock "Register" DstPort 1 } Line { SrcBlock "Constant" SrcPort 1 DstBlock "Relational" DstPort 2 } Line { SrcBlock "Relational" SrcPort 1 Points [0, -10] DstBlock "Logical" DstPort 2 } Line { SrcBlock "I" SrcPort 1 DstBlock "Register1" DstPort 1 } Line { SrcBlock "Q" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Relational1" DstPort 2 } Line { SrcBlock "Constant2" SrcPort 1 DstBlock "Relational2" DstPort 2 } Line { SrcBlock "Relational1" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Relational2" SrcPort 1 DstBlock "Logical1" DstPort 2 } Line { SrcBlock "Register3" SrcPort 1 Points [40, 0] Branch { DstBlock "Goto" DstPort 1 } Branch { Points [0, 145] DstBlock "dbg_EQ_Q3" DstPort 1 } } Line { SrcBlock "Register6" SrcPort 1 Points [30, 0] Branch { DstBlock "Goto1" DstPort 1 } Branch { Points [0, 120] DstBlock "dbg_EQ_Q1" DstPort 1 } } Line { SrcBlock "Delay" SrcPort 1 Points [30, 0] Branch { DstBlock "Goto2" DstPort 1 } Branch { Points [0, 95] DstBlock "dbg_EQ_Q2" DstPort 1 } } Line { SrcBlock "valid" SrcPort 1 DstBlock "Delay1" DstPort 1 } Line { SrcBlock "Delay1" SrcPort 1 Points [255, 0; 0, 25] DstBlock "Logical" DstPort 1 } Line { SrcBlock "Register7" SrcPort 1 DstBlock "dbg_EQ_I" DstPort 1 } Line { SrcBlock "Register8" SrcPort 1 DstBlock "dbg_EQ_Q" DstPort 1 } Line { SrcBlock "dbg_EQ_I" SrcPort 1 Points [50, 0; 0, 240; 40, 0] Branch { Points [0, 175; 25, 0] } Branch { DstBlock "Debug EQ IQ" DstPort 3 } } Line { SrcBlock "dbg_EQ_Q" SrcPort 1 Points [25, 0; 0, 230; 55, 0] Branch { Points [0, 165; 35, 0] } Branch { DstBlock "Debug EQ IQ" DstPort 4 } } Line { SrcBlock "dbg_EQ_Q3" SrcPort 1 DstBlock "Debug EQ IQ" DstPort 5 } Line { SrcBlock "dbg_EQ_Q1" SrcPort 1 DstBlock "Debug EQ IQ" DstPort 6 } Line { SrcBlock "dbg_EQ_Q2" SrcPort 1 DstBlock "Debug EQ IQ" DstPort 7 } Line { SrcBlock "Gateway Out12" SrcPort 1 DstBlock "Real-Imag to\nComplex" DstPort 1 } Line { SrcBlock "Gateway Out13" SrcPort 1 DstBlock "Real-Imag to\nComplex" DstPort 2 } Line { SrcBlock "Real-Imag to\nComplex" SrcPort 1 DstBlock "To Workspace" DstPort 1 } Line { SrcBlock "Gateway Out8" SrcPort 1 DstBlock "To Workspace1" DstPort 1 } Line { SrcBlock "To FP4" SrcPort 1 DstBlock "4x Buffer" DstPort 1 } Line { SrcBlock "To FP1" SrcPort 1 DstBlock "4x Buffer" DstPort 2 } Line { SrcBlock "Register4" SrcPort 1 DstBlock "Register7" DstPort 1 } Line { SrcBlock "4x Buffer" SrcPort 1 DstBlock "Register4" DstPort 1 } Line { SrcBlock "4x Buffer" SrcPort 3 Points [55, 0] Branch { Points [0, -20] Branch { Points [0, -35] DstBlock "Register4" DstPort 2 } Branch { DstBlock "Register5" DstPort 2 } } Branch { Points [220, 0; 0, 150] DstBlock "dbg_EQ_Q4" DstPort 1 } } Line { SrcBlock "4x Buffer" SrcPort 2 DstBlock "Register5" DstPort 1 } Line { SrcBlock "Register5" SrcPort 1 DstBlock "Register8" DstPort 1 } Line { SrcBlock "dbg_EQ_Q4" SrcPort 1 DstBlock "Debug EQ IQ" DstPort 2 } Line { SrcBlock "Constant3" SrcPort 1 DstBlock "Relational3" DstPort 2 } Line { SrcBlock "Constant4" SrcPort 1 DstBlock "Relational4" DstPort 2 } Line { SrcBlock "Relational3" SrcPort 1 DstBlock "Logical2" DstPort 1 } Line { SrcBlock "Relational4" SrcPort 1 DstBlock "Logical2" DstPort 2 } Line { SrcBlock "Register" SrcPort 1 Points [35, 0] Branch { DstBlock "Relational" DstPort 1 } Branch { Points [0, 85] Branch { DstBlock "Relational1" DstPort 1 } Branch { Points [0, 65] Branch { DstBlock "Relational2" DstPort 1 } Branch { Points [0, 75] Branch { DstBlock "Relational3" DstPort 1 } Branch { Points [0, 65] DstBlock "Relational4" DstPort 1 } } } } } Line { SrcBlock "Mux" SrcPort 1 Points [5, 0; 0, -140] DstBlock "Logical" DstPort 3 } Line { SrcBlock "From" SrcPort 1 Points [5, 0; 0, 75] DstBlock "Mux" DstPort 1 } Line { SrcBlock "Logical2" SrcPort 1 Points [65, 0; 0, -65] DstBlock "Mux" DstPort 3 } Line { SrcBlock "Logical1" SrcPort 1 Points [65, 0; 0, 30] DstBlock "Mux" DstPort 2 } Annotation { Name "Only capture data and pilot subcarriers\nfor debug outputs and chipscope" Position [1035, 370] } } } Block { BlockType SubSystem Name "Equalizer,\nPilot Processing\n& PHY Mode Det" SID "612" Ports [7, 7] Position [465, 239, 560, 441] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Equalizer,\nPilot Processing\n& PHY Mode Det" Location [61, 101, 2263, 1443] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "88" Block { BlockType Inport Name "x_I" SID "613" Position [230, 338, 260, 352] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "x_Q" SID "614" Position [230, 368, 260, 382] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "H_I" SID "615" Position [370, 398, 400, 412] NamePlacement "alternate" Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "H_Q" SID "616" Position [370, 428, 400, 442] Port "4" IconDisplay "Port number" } Block { BlockType Inport Name "x_valid" SID "617" Position [230, 493, 260, 507] NamePlacement "alternate" Port "5" IconDisplay "Port number" } Block { BlockType Inport Name "x_ind" SID "618" Position [230, 513, 260, 527] Port "6" IconDisplay "Port number" } Block { BlockType Inport Name "Sym ind" SID "619" Position [275, 533, 305, 547] Port "7" IconDisplay "Port number" } Block { BlockType Reference Name "Constant" SID "9510" Ports [0, 1] Position [590, 832, 645, 858] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0.034" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "16" bin_pt "13" preci_type "Single" exp_width "8" frac_width "24" explicit_period on period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "55,26,0,1,white,blue,0,3f77ca8a,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\npatch([20.325 24.66 27.66 30.66 33.66 27.66 23.325 20.325 ]" ",[16.33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([23.325 27.66 24.66 20.325 23.325 ],[13.3" "3 13.33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([20.325 24.66 27.66 23.325 20.325 ],[10.33 10.33 13.3" "3 13.33 10.33 ],[1 1 1 ]);\npatch([23.325 33.66 30.66 27.66 24.66 20.325 23.325 ],[7.33 7.33 10.33 7.33 10.33 1" "0.33 7.33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon " "text');\ncolor('black');port_label('output',1,'0.0340576171875');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant1" SID "9603" Ports [0, 1] Position [590, 877, 645, 903] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "16" bin_pt "13" preci_type "Single" exp_width "8" frac_width "24" explicit_period on period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "55,26,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\npatch([20.325 24.66 27.66 30.66 33.66 27.66 23.325 20.325 ]" ",[16.33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([23.325 27.66 24.66 20.325 23.325 ],[13.3" "3 13.33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([20.325 24.66 27.66 23.325 20.325 ],[10.33 10.33 13.3" "3 13.33 10.33 ],[1 1 1 ]);\npatch([23.325 33.66 30.66 27.66 24.66 20.325 23.325 ],[7.33 7.33 10.33 7.33 10.33 1" "0.33 7.33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon " "text');\ncolor('black');port_label('output',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert" SID "620" Ports [1, 1] Position [880, 358, 915, 382] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do" " not." gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "16" bin_pt "14" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" en off latency "1" dbl_ovrd off pipeline on xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "35,24,1,1,white,blue,0,0c6bad53,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ]" ",[15.33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.3" "3 12.33 15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 " "12.33 9.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\n\ncolor('black');port_label('output',1,'cast');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\nco" "lor('black');disp(' \\n ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "621" Ports [1, 1] Position [880, 423, 915, 447] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do" " not." gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "16" bin_pt "14" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" en off latency "1" dbl_ovrd off pipeline on xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "35,24,1,1,white,blue,0,0c6bad53,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ]" ",[15.33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.3" "3 12.33 15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 " "12.33 9.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\n\ncolor('black');port_label('output',1,'cast');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\nco" "lor('black');disp(' \\n ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "10108" Ports [1, 1] Position [880, 308, 915, 332] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do" " not." gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "20" bin_pt "14" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" en off latency "1" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "35,24,1,1,white,blue,0,0c6bad53,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ]" ",[15.33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.3" "3 12.33 15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 " "12.33 9.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\n\ncolor('black');port_label('output',1,'cast');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\nco" "lor('black');disp(' \\n ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert4" SID "10110" Ports [1, 1] Position [880, 273, 915, 297] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do" " not." gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "20" bin_pt "14" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" en off latency "1" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "35,24,1,1,white,blue,0,0c6bad53,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ]" ",[15.33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.3" "3 12.33 15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 " "12.33 9.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\n\ncolor('black');port_label('output',1,'cast');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\nco" "lor('black');disp(' \\n ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay1" SID "622" Ports [1, 1] Position [1030, 668, 1065, 692] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "62" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,24,1,1,white,blue,0,41dc5a24,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ]" ",[15.33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.3" "3 12.33 15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 " "12.33 9.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\n\n\ncolor('black');disp('z^{-62}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay10" SID "623" Ports [1, 1] Position [1030, 423, 1065, 447] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "62" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,24,1,1,white,blue,0,41dc5a24,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ]" ",[15.33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.3" "3 12.33 15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 " "12.33 9.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\n\n\ncolor('black');disp('z^{-62}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay12" SID "624" Ports [1, 1] Position [690, 613, 725, 637] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "23" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,24,1,1,white,blue,0,b88b7ef0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ]" ",[15.33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.3" "3 12.33 15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 " "12.33 9.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\n\n\ncolor('black');disp('z^{-23}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay14" SID "625" Ports [1, 1] Position [690, 668, 725, 692] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "23" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,24,1,1,white,blue,0,b88b7ef0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ]" ",[15.33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.3" "3 12.33 15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 " "12.33 9.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\n\n\ncolor('black');disp('z^{-23}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay17" SID "626" Ports [1, 1] Position [690, 723, 725, 747] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "23" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,24,1,1,white,blue,0,b88b7ef0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ]" ",[15.33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.3" "3 12.33 15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 " "12.33 9.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\n\n\ncolor('black');disp('z^{-23}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay2" SID "627" Ports [1, 1] Position [490, 511, 510, 529] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "8" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "20,18,1,1,white,blue,0,e47f993a,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 20 20 0 0 ],[0 0 18 18 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[9.22 9.22 11.22 11" ".22 9.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\np" "atch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfpr" "intf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-8" "}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay3" SID "628" Ports [1, 1] Position [1030, 723, 1065, 747] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "62" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,24,1,1,white,blue,0,41dc5a24,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ]" ",[15.33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.3" "3 12.33 15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 " "12.33 9.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\n\n\ncolor('black');disp('z^{-62}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay4" SID "629" Ports [1, 1] Position [1030, 613, 1065, 637] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "62" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,24,1,1,white,blue,0,41dc5a24,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ]" ",[15.33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.3" "3 12.33 15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 " "12.33 9.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\n\n\ncolor('black');disp('z^{-62}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay6" SID "630" Ports [1, 1] Position [490, 491, 510, 509] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "8" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "20,18,1,1,white,blue,0,e47f993a,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 20 20 0 0 ],[0 0 18 18 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[9.22 9.22 11.22 11" ".22 9.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\np" "atch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfpr" "intf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-8" "}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay7" SID "631" Ports [1, 1] Position [490, 531, 510, 549] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "8" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "20,18,1,1,white,blue,0,e47f993a,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 20 20 0 0 ],[0 0 18 18 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[9.22 9.22 11.22 11" ".22 9.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\np" "atch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfpr" "intf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-8" "}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay8" SID "632" Ports [1, 1] Position [1030, 358, 1065, 382] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "62" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,24,1,1,white,blue,0,41dc5a24,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ]" ",[15.33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.3" "3 12.33 15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 " "12.33 9.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\n\n\ncolor('black');disp('z^{-62}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Divide" SID "633" Ports [2, 1] Position [735, 354, 790, 381] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Divide" SourceType "Xilinx Divider Block" infoedit "Blocking: Wait for data on all inputs, allow back-pressure.
NonBlocking: operate every cycl" "e in which all inputs are valid, no back-pressure." flow_control "NonBlocking" axi_optimize_goal "Resources" algorithm_type "High_Radix" infoedit1 "Specify output fraction-width for Fixed-point division." fractional_width "16" latency "21" rate "1" has_a_tlast off has_a_tuser off has_b_tlast off has_b_tuser off en off has_result_tready off result_tlast_behv "Pass_A_TLAST" has_underflow off has_overflow off has_invalid_op off has_divide_by_zero off xl_use_area off xl_area "[0,0,0,0,0,0,0]" fpo_op_type "mergeddivide" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "divide" sg_icon_stat "55,27,2,1,white,blue,0,2ccf8398,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 27 27 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 27 27 0 ]);\npatch([20.325 24.66 27.66 30.66 33.66 27.66 23.325 20.325 ]" ",[16.33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([23.325 27.66 24.66 20.325 23.325 ],[13.3" "3 13.33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([20.325 24.66 27.66 23.325 20.325 ],[10.33 10.33 13.3" "3 13.33 10.33 ],[1 1 1 ]);\npatch([23.325 33.66 30.66 27.66 24.66 20.325 23.325 ],[7.33 7.33 10.33 7.33 10.33 1" "0.33 7.33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon " "text');\ncolor('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');p" "ort_label('output',1,'op');\ncolor('black');disp('z^{-21}\\newline ','texmode','on');\ncolor('black');disp(' \\" "newline\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Divide1" SID "634" Ports [2, 1] Position [735, 419, 790, 446] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Divide" SourceType "Xilinx Divider Block" infoedit "Blocking: Wait for data on all inputs, allow back-pressure.
NonBlocking: operate every cycl" "e in which all inputs are valid, no back-pressure." flow_control "NonBlocking" axi_optimize_goal "Resources" algorithm_type "High_Radix" infoedit1 "Specify output fraction-width for Fixed-point division." fractional_width "16" latency "21" rate "1" has_a_tlast off has_a_tuser off has_b_tlast off has_b_tuser off en off has_result_tready off result_tlast_behv "Pass_A_TLAST" has_underflow off has_overflow off has_invalid_op off has_divide_by_zero off xl_use_area off xl_area "[0,0,0,0,0,0,0]" fpo_op_type "mergeddivide" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "divide" sg_icon_stat "55,27,2,1,white,blue,0,2ccf8398,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 27 27 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 27 27 0 ]);\npatch([20.325 24.66 27.66 30.66 33.66 27.66 23.325 20.325 ]" ",[16.33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([23.325 27.66 24.66 20.325 23.325 ],[13.3" "3 13.33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([20.325 24.66 27.66 23.325 20.325 ],[10.33 10.33 13.3" "3 13.33 10.33 ],[1 1 1 ]);\npatch([23.325 33.66 30.66 27.66 24.66 20.325 23.325 ],[7.33 7.33 10.33 7.33 10.33 1" "0.33 7.33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon " "text');\ncolor('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');p" "ort_label('output',1,'op');\ncolor('black');disp('z^{-21}\\newline ','texmode','on');\ncolor('black');disp(' \\" "newline\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Scope Name "EQ" SID "635" Ports [8] Position [1680, 13, 1715, 222] ZOrder -3 Floating off Location [6, 94, 2477, 1460] Open off NumInputPorts "8" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" } List { ListType ScopeGraphics FigureColor "[0.501960784313725 0.501960784313725 0.501960784313725]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "20000" YMin "-0.5~-0.5~0~0~0~-2~-2~0" YMax "0.5~0.5~1~80~40~2~0.5~1" SaveName "ScopeData9" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType Reference Name "Gateway Out" SID "636" Ports [1, 1] Position [1525, 24, 1560, 36] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "X_I" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out1" SID "637" Ports [1, 1] Position [1525, 49, 1560, 61] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "X_Q" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "638" Ports [1, 1] Position [1525, 174, 1560, 186] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "EQ Q" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "639" Ports [1, 1] Position [1525, 199, 1560, 211] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "EQ Valid" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "640" Ports [1, 1] Position [1525, 74, 1560, 86] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "X Valid" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "641" Ports [1, 1] Position [1525, 99, 1560, 111] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "EQ X Ind" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "642" Ports [1, 1] Position [1525, 124, 1560, 136] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Sym Ind" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "643" Ports [1, 1] Position [1525, 149, 1560, 161] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "EQ I" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Goto Name "Goto" SID "644" Position [1475, 903, 1620, 927] ZOrder -10 ShowName off GotoTag "RX_PHY_MODE_11N" TagVisibility "global" } Block { BlockType Goto Name "Goto1" SID "645" Position [1475, 873, 1620, 897] ZOrder -10 ShowName off GotoTag "RX_PHY_MODE_11AC" TagVisibility "global" } Block { BlockType Goto Name "Goto2" SID "646" Position [1475, 933, 1620, 957] ZOrder -10 ShowName off GotoTag "RX_PHY_MODE_11AG" TagVisibility "global" } Block { BlockType Goto Name "Goto3" SID "647" Position [1475, 833, 1620, 857] ZOrder -10 ShowName off GotoTag "RX_PHY_MODE_11N_AC" TagVisibility "global" } Block { BlockType Goto Name "Goto4" SID "942" Position [1390, 486, 1510, 514] ZOrder -10 ShowName off GotoTag "CS_Phase_Err" TagVisibility "global" } Block { BlockType Reference Name "Logical4" SID "648" Ports [2, 1] Position [1410, 824, 1445, 866] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,42,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 42 42 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 42 42 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[26.55" " 26.55 31.55 26.55 31.55 31.55 31.55 26.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[21.55 21.55 26" ".55 26.55 21.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[16.55 16.55 21.55 21.55 16.55 " "],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[11.55 11.55 16.55 11.55 16.55 16.55 11.55 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n" "color('black');disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Mag" SID "649" Ports [2, 1] Position [475, 255, 515, 315] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Mag" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "156" Block { BlockType Inport Name "I" SID "650" Position [225, 33, 255, 47] IconDisplay "Port number" } Block { BlockType Inport Name "Q" SID "651" Position [225, 93, 255, 107] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub" SID "652" Ports [2, 1] Position [525, 36, 585, 94] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "4" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL off hw_selection "DSP48" pipelined off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" sg_icon_stat "60,58,2,1,white,blue,0,eeab5c4c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 58 58 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 60 60 0 0 ],[0 0 58 58 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[37.88 37.88 45" ".88 37.88 45.88 45.88 45.88 37.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[29.88 29.88 37.88 37.88 29.88" " ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[21.88 21.88 29.88 29.88 21.88 ],[1 1 1 ]);\npatch(" "[20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[13.88 13.88 21.88 13.88 21.88 21.88 13.88 ],[0.931 0.946 0.973 ]);\nfpr" "intf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'" ",1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bf{a + b}','texmode'," "'on');\ncolor('black');disp('z^{-4}\\newline ','texmode','on');\ncolor('black');disp(' \\newline\\bf{}','texmode'," "'on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mult" SID "653" Ports [2, 1] Position [300, 28, 355, 72] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mult" SourceType "Xilinx Multiplier Block" infoedit "Hardware notes: To check for the optimum internal pipeline stages of the dedicated multiplier you mus" "t select 'Test for optimum pipelining'.

Optimization Goal: For implementation into device fabric (LUTs), th" "e Speed or Area optimization will take effect only if it's supported by IP for the particular device family. Other" "wise, the results will be identical regardless of the selection." precision "Full" arith_type "Signed (2's comp)" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" en off latency "2" dbl_ovrd off use_behavioral_HDL off opt "Speed" use_embedded on optimum_pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" pipeline "on" use_rpm "on" placement_style "Triangular" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mult" sg_icon_stat "55,44,2,1,white,blue,0,2fbe4d8a,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 44 44 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 55 55 0 0 ],[0 0 44 44 0 ]);\npatch([13.65 22.32 28.32 34.32 40.32 28.32 19.65 13.65 ],[28.66 28.66" " 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([19.65 28.32 22.32 13.65 19.65 ],[22.66 22.66 28.66 28.66" " 22.66 ],[0.931 0.946 0.973 ]);\npatch([13.65 22.32 28.32 19.65 13.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1 1 ])" ";\npatch([19.65 40.32 34.32 28.32 22.32 13.65 19.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0.946 0." "973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa \\tim" "es b','texmode','on');\ncolor('black');disp('z^{-2}\\newline ','texmode','on');\ncolor('black');disp(' \\n ');\nfp" "rintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mult1" SID "654" Ports [2, 1] Position [300, 88, 355, 132] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mult" SourceType "Xilinx Multiplier Block" infoedit "Hardware notes: To check for the optimum internal pipeline stages of the dedicated multiplier you mus" "t select 'Test for optimum pipelining'.

Optimization Goal: For implementation into device fabric (LUTs), th" "e Speed or Area optimization will take effect only if it's supported by IP for the particular device family. Other" "wise, the results will be identical regardless of the selection." precision "Full" arith_type "Signed (2's comp)" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" en off latency "2" dbl_ovrd off use_behavioral_HDL off opt "Speed" use_embedded on optimum_pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" pipeline "on" use_rpm "on" placement_style "Triangular" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mult" sg_icon_stat "55,44,2,1,white,blue,0,2fbe4d8a,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 44 44 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 55 55 0 0 ],[0 0 44 44 0 ]);\npatch([13.65 22.32 28.32 34.32 40.32 28.32 19.65 13.65 ],[28.66 28.66" " 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([19.65 28.32 22.32 13.65 19.65 ],[22.66 22.66 28.66 28.66" " 22.66 ],[0.931 0.946 0.973 ]);\npatch([13.65 22.32 28.32 19.65 13.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1 1 ])" ";\npatch([19.65 40.32 34.32 28.32 22.32 13.65 19.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0.946 0." "973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa \\tim" "es b','texmode','on');\ncolor('black');disp('z^{-2}\\newline ','texmode','on');\ncolor('black');disp(' \\n ');\nfp" "rintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "655" Ports [1, 1] Position [415, 65, 470, 95] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "55,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 55 55 0 0 ],[0 0 30 30 0 ]);\npatch([18.1 23.88 27.88 31.88 35.88 27.88 22.1 18.1 ],[19.44 19.44 23" ".44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([22.1 27.88 23.88 18.1 22.1 ],[15.44 15.44 19.44 19.44 15.44" " ],[0.931 0.946 0.973 ]);\npatch([18.1 23.88 27.88 22.1 18.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch(" "[22.1 35.88 31.88 27.88 23.88 18.1 22.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf" "('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMME" "NT: end icon text');" } Block { BlockType Reference Name "Register2" SID "656" Ports [1, 1] Position [415, 35, 470, 65] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "55,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 55 55 0 0 ],[0 0 30 30 0 ]);\npatch([18.1 23.88 27.88 31.88 35.88 27.88 22.1 18.1 ],[19.44 19.44 23" ".44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([22.1 27.88 23.88 18.1 22.1 ],[15.44 15.44 19.44 19.44 15.44" " ],[0.931 0.946 0.973 ]);\npatch([18.1 23.88 27.88 22.1 18.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch(" "[22.1 35.88 31.88 27.88 23.88 18.1 22.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf" "('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMME" "NT: end icon text');" } Block { BlockType Reference Name "Register3" SID "657" Ports [1, 1] Position [655, 50, 710, 80] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "55,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 55 55 0 0 ],[0 0 30 30 0 ]);\npatch([18.1 23.88 27.88 31.88 35.88 27.88 22.1 18.1 ],[19.44 19.44 23" ".44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([22.1 27.88 23.88 18.1 22.1 ],[15.44 15.44 19.44 19.44 15.44" " ],[0.931 0.946 0.973 ]);\npatch([18.1 23.88 27.88 22.1 18.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch(" "[22.1 35.88 31.88 27.88 23.88 18.1 22.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf" "('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMME" "NT: end icon text');" } Block { BlockType Outport Name "M" SID "658" Position [745, 58, 775, 72] IconDisplay "Port number" } Line { SrcBlock "I" SrcPort 1 Points [10, 0] Branch { DstBlock "Mult" DstPort 1 } Branch { Points [0, 20] DstBlock "Mult" DstPort 2 } } Line { SrcBlock "Q" SrcPort 1 Points [15, 0] Branch { DstBlock "Mult1" DstPort 1 } Branch { Points [0, 20] DstBlock "Mult1" DstPort 2 } } Line { SrcBlock "Mult" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "Mult1" SrcPort 1 Points [30, 0; 0, -30] DstBlock "Register1" DstPort 1 } Line { SrcBlock "AddSub" SrcPort 1 DstBlock "Register3" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "AddSub" DstPort 1 } Line { SrcBlock "Register1" SrcPort 1 DstBlock "AddSub" DstPort 2 } Line { SrcBlock "Register3" SrcPort 1 DstBlock "M" DstPort 1 } } } Block { BlockType SubSystem Name "PHY Mode Det" SID "659" Ports [4, 3] Position [1255, 872, 1325, 958] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "PHY Mode Det" Location [98, 303, 2319, 1506] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "80" Block { BlockType Inport Name "x_I" SID "660" Position [205, 323, 235, 337] IconDisplay "Port number" } Block { BlockType Inport Name "x_Q" SID "661" Position [205, 388, 235, 402] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "x_valid" SID "662" Position [205, 428, 235, 442] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "Sym ind" SID "663" Position [15, 643, 45, 657] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name " 11ac" SID "664" Ports [3, 1] Position [1610, 589, 1670, 641] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "60,52,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 52 52 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 60 60 0 0 ],[0 0 52 52 0 ]);\npatch([14.425 24.54 31.54 38.54 45.54 31.54 21.425 14.425 ],[33.77 33" ".77 40.77 33.77 40.77 40.77 40.77 33.77 ],[1 1 1 ]);\npatch([21.425 31.54 24.54 14.425 21.425 ],[26.77 26.77 33.77" " 33.77 26.77 ],[0.931 0.946 0.973 ]);\npatch([14.425 24.54 31.54 21.425 14.425 ],[19.77 19.77 26.77 26.77 19.77 ]," "[1 1 1 ]);\npatch([21.425 45.54 38.54 31.54 24.54 14.425 21.425 ],[12.77 12.77 19.77 12.77 19.77 19.77 12.77 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3" ",'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Reference Name " 11ag" SID "665" Ports [3, 1] Position [1610, 729, 1670, 781] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "1" rst on en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "60,52,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 52 52 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 60 60 0 0 ],[0 0 52 52 0 ]);\npatch([14.425 24.54 31.54 38.54 45.54 31.54 21.425 14.425 ],[33.77 33" ".77 40.77 33.77 40.77 40.77 40.77 33.77 ],[1 1 1 ]);\npatch([21.425 31.54 24.54 14.425 21.425 ],[26.77 26.77 33.77" " 33.77 26.77 ],[0.931 0.946 0.973 ]);\npatch([14.425 24.54 31.54 21.425 14.425 ],[19.77 19.77 26.77 26.77 19.77 ]," "[1 1 1 ]);\npatch([21.425 45.54 38.54 31.54 24.54 14.425 21.425 ],[12.77 12.77 19.77 12.77 19.77 19.77 12.77 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3" ",'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Reference Name " 11n" SID "666" Ports [3, 1] Position [1610, 659, 1670, 711] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "60,52,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 52 52 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 60 60 0 0 ],[0 0 52 52 0 ]);\npatch([14.425 24.54 31.54 38.54 45.54 31.54 21.425 14.425 ],[33.77 33" ".77 40.77 33.77 40.77 40.77 40.77 33.77 ],[1 1 1 ]);\npatch([21.425 31.54 24.54 14.425 21.425 ],[26.77 26.77 33.77" " 33.77 26.77 ],[0.931 0.946 0.973 ]);\npatch([14.425 24.54 31.54 21.425 14.425 ],[19.77 19.77 26.77 26.77 19.77 ]," "[1 1 1 ]);\npatch([21.425 45.54 38.54 31.54 24.54 14.425 21.425 ],[12.77 12.77 19.77 12.77 19.77 19.77 12.77 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3" ",'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Reference Name "Absolute" SID "667" Ports [1, 1] Position [365, 315, 405, 345] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Absolute" SourceType "Xilinx Absolute Block Block" precision "User Defined" arith_type "Signed (2's comp)" n_bits "8" bin_pt "7" quantization "Truncate" overflow "Saturate" en off latency "1" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "abs" sg_icon_stat "40,30,1,1,white,blue,0,6c6606ff,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 30 30 0 ]);\npatch([11.1 16.88 20.88 24.88 28.88 20.88 15.1 11.1 ],[19.44 19.44 23" ".44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([15.1 20.88 16.88 11.1 15.1 ],[15.44 15.44 19.44 19.44 15.44" " ],[0.931 0.946 0.973 ]);\npatch([11.1 16.88 20.88 15.1 11.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch(" "[15.1 28.88 24.88 20.88 16.88 11.1 15.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf" "('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "a');\ncolor('black');port_label('output',1,'|a|');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor" "('black');disp(' \\newline\\bf{|x|}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Absolute1" SID "668" Ports [1, 1] Position [365, 380, 405, 410] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Absolute" SourceType "Xilinx Absolute Block Block" precision "User Defined" arith_type "Signed (2's comp)" n_bits "8" bin_pt "7" quantization "Truncate" overflow "Saturate" en off latency "1" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "abs" sg_icon_stat "40,30,1,1,white,blue,0,6c6606ff,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 30 30 0 ]);\npatch([11.1 16.88 20.88 24.88 28.88 20.88 15.1 11.1 ],[19.44 19.44 23" ".44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([15.1 20.88 16.88 11.1 15.1 ],[15.44 15.44 19.44 19.44 15.44" " ],[0.931 0.946 0.973 ]);\npatch([11.1 16.88 20.88 15.1 11.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch(" "[15.1 28.88 24.88 20.88 16.88 11.1 15.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf" "('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "a');\ncolor('black');port_label('output',1,'|a|');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor" "('black');disp(' \\newline\\bf{|x|}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Assert" SID "669" Ports [1, 1] Position [1755, 606, 1795, 624] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Assert" SourceType "Xilinx Assert Block" infoedit "Asserts a user-defined sample rate and/or type on a signal.

Hardware notes: In hardware this b" "lock costs nothing." assert_type off type_source "Explicitly" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "16" bin_pt "14" preci_type "Single" exp_width "8" frac_width "24" assert_rate on rate_source "Explicitly" period "1" output_port on has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "assert" sg_icon_stat "40,18,1,1,white,blue,0,9657e937,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22 11.22" " 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22 11.22 9" ".22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch" "([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('Assert');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Assert1" SID "670" Ports [1, 1] Position [1755, 676, 1795, 694] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Assert" SourceType "Xilinx Assert Block" infoedit "Asserts a user-defined sample rate and/or type on a signal.

Hardware notes: In hardware this b" "lock costs nothing." assert_type off type_source "Explicitly" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "16" bin_pt "14" preci_type "Single" exp_width "8" frac_width "24" assert_rate on rate_source "Explicitly" period "1" output_port on has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "assert" sg_icon_stat "40,18,1,1,white,blue,0,9657e937,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22 11.22" " 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22 11.22 9" ".22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch" "([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('Assert');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Assert2" SID "671" Ports [1, 1] Position [1755, 746, 1795, 764] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Assert" SourceType "Xilinx Assert Block" infoedit "Asserts a user-defined sample rate and/or type on a signal.

Hardware notes: In hardware this b" "lock costs nothing." assert_type off type_source "Explicitly" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "16" bin_pt "14" preci_type "Single" exp_width "8" frac_width "24" assert_rate on rate_source "Explicitly" period "1" output_port on has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "assert" sg_icon_stat "40,18,1,1,white,blue,0,9657e937,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22 11.22" " 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22 11.22 9" ".22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch" "([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('Assert');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Concat" SID "672" Ports [2, 1] Position [805, 355, 850, 395] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point at z" "ero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "45,40,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 40 40 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 40 40 0 ]);\npatch([10.875 18.1 23.1 28.1 33.1 23.1 15.875 10.875 ],[25.55 25.55 3" "0.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([15.875 23.1 18.1 10.875 15.875 ],[20.55 20.55 25.55 25.55 " "20.55 ],[0.931 0.946 0.973 ]);\npatch([10.875 18.1 23.1 15.875 10.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1 1 ])" ";\npatch([15.875 33.1 28.1 23.1 18.1 10.875 15.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.946 0.9" "73 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_la" "bel('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fontsize{20}\\}','texmo" "de','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Concat1" SID "673" Ports [3, 1] Position [1590, 440, 1640, 530] BlockMirror on NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point at z" "ero." num_inputs "3" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "50,90,3,1,white,blue,0,61ef8218,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 90 90 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 50 50 0 0 ],[0 0 90 90 0 ]);\npatch([9.425 19.54 26.54 33.54 40.54 26.54 16.425 9.425 ],[52.77 52.7" "7 59.77 52.77 59.77 59.77 59.77 52.77 ],[1 1 1 ]);\npatch([16.425 26.54 19.54 9.425 16.425 ],[45.77 45.77 52.77 52" ".77 45.77 ],[0.931 0.946 0.973 ]);\npatch([9.425 19.54 26.54 16.425 9.425 ],[38.77 38.77 45.77 45.77 38.77 ],[1 1 " "1 ]);\npatch([16.425 40.54 33.54 26.54 19.54 9.425 16.425 ],[31.77 31.77 38.77 31.77 38.77 38.77 31.77 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('input',1,'hi');\n\ncolor('black');port_label('input',3,'lo');\n\ncolor('black');disp('\\fontsize{20}\\" "}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Concat2" SID "674" Ports [3, 1] Position [805, 215, 850, 255] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point at z" "ero." num_inputs "3" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "45,40,3,1,white,blue,0,61ef8218,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 40 40 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 40 40 0 ]);\npatch([10.875 18.1 23.1 28.1 33.1 23.1 15.875 10.875 ],[25.55 25.55 3" "0.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([15.875 23.1 18.1 10.875 15.875 ],[20.55 20.55 25.55 25.55 " "20.55 ],[0.931 0.946 0.973 ]);\npatch([10.875 18.1 23.1 15.875 10.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1 1 ])" ";\npatch([15.875 33.1 28.1 23.1 18.1 10.875 15.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.946 0.9" "73 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_la" "bel('input',1,'hi');\n\ncolor('black');port_label('input',3,'lo');\n\ncolor('black');disp('\\fontsize{20}\\}','tex" "mode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant1" SID "675" Ports [0, 1] Position [95, 657, 125, 673] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,16,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 16 16 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 16 16 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[10.22 10.22" " 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[8.22 8.22 10.22 10.22 8" ".22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatch" "([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1" ",'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant3" SID "676" Ports [0, 1] Position [95, 707, 125, 723] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "3" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,16,0,1,white,blue,0,279a71c8,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 16 16 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 16 16 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[10.22 10.22" " 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[8.22 8.22 10.22 10.22 8" ".22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatch" "([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1" ",'3');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant4" SID "677" Ports [0, 1] Position [95, 782, 125, 798] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "4" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,16,0,1,white,blue,0,85f36853,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 16 16 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 16 16 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[10.22 10.22" " 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[8.22 8.22 10.22 10.22 8" ".22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatch" "([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1" ",'4');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant5" SID "678" Ports [0, 1] Position [1065, 597, 1095, 613] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,16,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 16 16 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 16 16 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[10.22 10.22" " 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[8.22 8.22 10.22 10.22 8" ".22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatch" "([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1" ",'1');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant7" SID "679" Ports [0, 1] Position [1065, 667, 1095, 683] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "2" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,16,0,1,white,blue,0,fca86624,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 16 16 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 16 16 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[10.22 10.22" " 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[8.22 8.22 10.22 10.22 8" ".22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatch" "([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1" ",'2');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant8" SID "680" Ports [0, 1] Position [1065, 772, 1095, 788] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "2" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,16,0,1,white,blue,0,fca86624,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 16 16 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 16 16 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[10.22 10.22" " 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[8.22 8.22 10.22 10.22 8" ".22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatch" "([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1" ",'2');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert" SID "681" Ports [1, 1] Position [290, 319, 325, 341] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "9" bin_pt "7" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "35,22,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 22 22 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[14.33 14" ".33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 " "1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');po" "rt_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "682" Ports [1, 1] Position [290, 384, 325, 406] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "9" bin_pt "7" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "35,22,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 22 22 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[14.33 14" ".33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 " "1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');po" "rt_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "683" Ports [1, 1] Position [370, 524, 405, 546] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "9" bin_pt "7" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "35,22,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 22 22 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[14.33 14" ".33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 " "1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');po" "rt_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay1" SID "684" Ports [1, 1] Position [980, 856, 1000, 874] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "20,18,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 20 20 0 0 ],[0 0 18 18 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[11.22 11.22 13." "22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[9.22 9.22 11.22 11.22 9.22 ],[0" ".931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([7.55 14.44" " 12.44 10.44 8.44 5.55 7.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: e" "nd icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-1}','texmode','on');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay2" SID "685" Ports [1, 1] Position [980, 836, 1000, 854] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "20,18,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 20 20 0 0 ],[0 0 18 18 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[11.22 11.22 13." "22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[9.22 9.22 11.22 11.22 9.22 ],[0" ".931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([7.55 14.44" " 12.44 10.44 8.44 5.55 7.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: e" "nd icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-1}','texmode','on');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay3" SID "686" Ports [1, 1] Position [705, 671, 725, 689] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "20,18,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 20 20 0 0 ],[0 0 18 18 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[11.22 11.22 13." "22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[9.22 9.22 11.22 11.22 9.22 ],[0" ".931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([7.55 14.44" " 12.44 10.44 8.44 5.55 7.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: e" "nd icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-1}','texmode','on');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay5" SID "687" Ports [1, 1] Position [705, 776, 725, 794] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "20,18,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 20 20 0 0 ],[0 0 18 18 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[11.22 11.22 13." "22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[9.22 9.22 11.22 11.22 9.22 ],[0" ".931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([7.55 14.44" " 12.44 10.44 8.44 5.55 7.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: e" "nd icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-1}','texmode','on');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay7" SID "688" Ports [1, 1] Position [375, 426, 395, 444] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "20,18,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 20 20 0 0 ],[0 0 18 18 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[11.22 11.22 13." "22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[9.22 9.22 11.22 11.22 9.22 ],[0" ".931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([7.55 14.44" " 12.44 10.44 8.44 5.55 7.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: e" "nd icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-1}','texmode','on');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "689" Position [1505, 335, 1700, 355] ZOrder -9 ShowName off GotoTag "regRx_PHY_MODE_11N_ENABLE" TagVisibility "global" } Block { BlockType From Name "From1" SID "14911" Position [940, 523, 1190, 547] ZOrder -9 ShowName off GotoTag "regRx_PHY_MODE_11AC_DET_ENABLE" TagVisibility "global" } Block { BlockType Reference Name "Gateway Out1" SID "690" Ports [1, 1] Position [1025, 79, 1060, 91] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "X_I" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "691" Ports [1, 1] Position [1025, 154, 1060, 166] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Sym_Ind" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "692" Ports [1, 1] Position [1025, 129, 1060, 141] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "x_valid" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "693" Ports [1, 1] Position [1025, 104, 1060, 116] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "X_Q" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "694" Ports [1, 1] Position [1025, 229, 1060, 241] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "mod_det" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "695" Ports [1, 1] Position [1025, 254, 1060, 266] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "PHY_mode" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "696" Ports [1, 1] Position [1025, 179, 1060, 191] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "I_Accum" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "697" Ports [1, 1] Position [1025, 204, 1060, 216] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Q_Accum" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "I_Accum" SID "698" Ports [3, 1] Position [515, 321, 575, 379] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Accumulator" SourceType "Xilinx Accumulator Block" infoedit "Adder or subtracter-based accumulator. Output type and binary point position match the input.
Hardware notes: When \"Reinitialize with input 'b' on reset\" is selected, the accumulator is forced to run at t" "he system rate even if the input 'b' is running at a slower rate." operation "Add" n_bits "16" overflow "Wrap" scale "1" rst on infoeditControl "reset for floating point data type must be asserted for a minimum of 2 cycles" hasbypass off en on latency "0" dbl_ovrd off msb_inp "100" msb "100" lsb "-100" use_behavioral_HDL on implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "accum" sg_icon_stat "60,58,3,1,white,blue,0,ee9eb47a,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 58 58 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 60 60 0 0 ],[0 0 58 58 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[37.88 37.88 45" ".88 37.88 45.88 45.88 45.88 37.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[29.88 29.88 37.88 37.88 29.88" " ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[21.88 21.88 29.88 29.88 21.88 ],[1 1 1 ]);\npatch(" "[20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[13.88 13.88 21.88 13.88 21.88 21.88 13.88 ],[0.931 0.946 0.973 ]);\nfpr" "intf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'" ",1,'b');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'en');\ncolor('black');" "port_label('output',1,'\\bf+=b','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "699" Ports [1, 1] Position [1850, 766, 1875, 784] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "LSB" SID "700" Ports [1, 1] Position [215, 523, 245, 547] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type" " is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardw" "are notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "30,24,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 24 24 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 24 24 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[15.33 15.3" "3 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[12.33 12.33 15.33 15" ".33 12.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 1 1 ]" ");\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 0.973 " "]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_lab" "el('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "701" Ports [2, 1] Position [1905, 654, 1940, 696] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,42,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 42 42 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 42 42 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[26.55 26.55 31." "55 26.55 31.55 31.55 31.55 26.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[21.55 21.55 26.55 26.55 21." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[16.55 16.55 21.55 21.55 16.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[11.55 11.55 16.55 11.55 16.55 16.55 11.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('a" "nd');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "702" Ports [3, 1] Position [1320, 559, 1355, 641] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,82,3,1,white,blue,0,98d76266,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 82 82 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 82 82 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[46.55 46.55 51." "55 46.55 51.55 51.55 51.55 46.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[41.55 41.55 46.55 46.55 41." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[36.55 36.55 41.55 41.55 36.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[31.55 31.55 36.55 31.55 36.55 36.55 31.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\ncolor('black');disp(" "'and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical3" SID "703" Ports [2, 1] Position [1045, 834, 1080, 876] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,42,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 42 42 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 42 42 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[26.55 26.55 31." "55 26.55 31.55 31.55 31.55 26.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[21.55 21.55 26.55 26.55 21." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[16.55 16.55 21.55 21.55 16.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[11.55 11.55 16.55 11.55 16.55 16.55 11.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('o" "r');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical4" SID "704" Ports [2, 1] Position [1405, 719, 1440, 761] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "NOR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,42,2,1,white,blue,0,affe8783,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 42 42 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 42 42 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[26.55 26.55 31." "55 26.55 31.55 31.55 31.55 26.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[21.55 21.55 26.55 26.55 21." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[16.55 16.55 21.55 21.55 16.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[11.55 11.55 16.55 11.55 16.55 16.55 11.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('n" "or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical5" SID "705" Ports [2, 1] Position [1905, 744, 1940, 786] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,42,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 42 42 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 42 42 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[26.55 26.55 31." "55 26.55 31.55 31.55 31.55 26.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[21.55 21.55 26.55 26.55 21." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[16.55 16.55 21.55 21.55 16.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[11.55 11.55 16.55 11.55 16.55 16.55 11.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('o" "r');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Mod Det" SID "706" Ports [2, 3] Position [680, 336, 750, 394] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Mod Det" Location [769, 470, 1379, 856] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "I" SID "707" Position [340, 508, 370, 522] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "Q" SID "708" Position [340, 538, 370, 552] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name " BPSK" SID "709" Ports [2, 1] Position [855, 472, 895, 508] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,36,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 36 36 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 36 36 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[23.55 23." "55 28.55 23.55 28.55 28.55 28.55 23.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[18.55 18.55 23.55 2" "3.55 18.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[13.55 13.55 18.55 18.55 13.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[8.55 8.55 13.55 8.55 13.55 13.55 8.55 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black" "');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name " QAM" SID "710" Ports [1, 1] Position [855, 761, 890, 789] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "35,28,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 28 28 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[18.44 18.4" "4 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[14.44 14.44 18.44 18.44 " "14.44 ],[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\np" "atch([12.1 25.88 21.88 17.88 13.88 8.1 12.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name " QBPSK" SID "711" Ports [2, 1] Position [855, 672, 895, 708] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,36,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 36 36 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 36 36 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[23.55 23." "55 28.55 23.55 28.55 28.55 28.55 23.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[18.55 18.55 23.55 2" "3.55 18.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[13.55 13.55 18.55 18.55 13.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[8.55 8.55 13.55 8.55 13.55 13.55 8.55 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black" "');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Absolute2" SID "712" Ports [1, 1] Position [580, 455, 620, 485] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Absolute" SourceType "Xilinx Absolute Block Block" precision "Full" arith_type "Signed (2's comp)" n_bits "8" bin_pt "7" quantization "Truncate" overflow "Saturate" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "abs" sg_icon_stat "40,30,1,1,white,blue,0,c9bc0535,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 30 30 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 30 30 0 ]);\npatch([11.1 16.88 20.88 24.88 28.88 20.88 15.1 11.1 ],[19.44 19" ".44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([15.1 20.88 16.88 11.1 15.1 ],[15.44 15.44 19.44 19." "44 15.44 ],[0.931 0.946 0.973 ]);\npatch([11.1 16.88 20.88 15.1 11.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]" ");\npatch([15.1 28.88 24.88 20.88 16.88 11.1 15.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 " "]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_lab" "el('input',1,'a');\ncolor('black');port_label('output',1,'|a|');\ncolor('black');disp('\\bf{|x|}','texmode','on'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub" SID "713" Ports [2, 1] Position [425, 501, 485, 559] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Subtraction" use_carryin off use_carryout off en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL off hw_selection "Fabric" pipelined off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" sg_icon_stat "60,58,2,1,white,blue,0,32e1f85f,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 58 58 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 58 58 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[37.88 37" ".88 45.88 37.88 45.88 45.88 45.88 37.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[29.88 29.88 37.88 37." "88 29.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[21.88 21.88 29.88 29.88 21.88 ],[1 1 1 ]" ");\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[13.88 13.88 21.88 13.88 21.88 21.88 13.88 ],[0.931 0.946 0." "973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port" "_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bf{a " "- b}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant5" SID "714" Ports [0, 1] Position [585, 592, 615, 608] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,16,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 16 16 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_la" "bel('output',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant6" SID "715" Ports [0, 1] Position [435, 382, 465, 398] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "20" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "5" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,16,0,1,white,blue,0,a4afb800,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 16 16 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_la" "bel('output',1,'20');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From1" SID "14847" Position [420, 423, 585, 447] ZOrder -9 ShowName off GotoTag "regRx_PHY_Det_IQ_Thresh" TagVisibility "global" } Block { BlockType Reference Name "Inverter" SID "716" Ports [1, 1] Position [780, 686, 815, 714] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "35,28,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 28 28 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[18.44 18.4" "4 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[14.44 14.44 18.44 18.44 " "14.44 ],[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\np" "atch([12.1 25.88 21.88 17.88 13.88 8.1 12.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational4" SID "717" Ports [2, 1] Position [675, 568, 720, 612] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a>b" en off latency "1" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "45,44,2,1,white,blue,0,3049caaa,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bfa > b','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\n ')" ";\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational5" SID "718" Ports [2, 1] Position [675, 458, 720, 502] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a>b" en off latency "1" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "45,44,2,1,white,blue,0,3049caaa,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bfa > b','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\n ')" ";\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "QAM" SID "719" Position [955, 768, 985, 782] IconDisplay "Port number" } Block { BlockType Outport Name "QBPSK" SID "720" Position [955, 683, 985, 697] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "BPSK" SID "721" Position [965, 483, 995, 497] Port "3" IconDisplay "Port number" } Line { SrcBlock "Constant5" SrcPort 1 DstBlock "Relational4" DstPort 2 } Line { SrcBlock "AddSub" SrcPort 1 Points [55, 0] Branch { Points [0, 50] DstBlock "Relational4" DstPort 1 } Branch { Points [0, -60] DstBlock "Absolute2" DstPort 1 } } Line { SrcBlock "Absolute2" SrcPort 1 DstBlock "Relational5" DstPort 1 } Line { SrcBlock "From1" SrcPort 1 Points [50, 0; 0, 55] DstBlock "Relational5" DstPort 2 } Line { SrcBlock "Relational5" SrcPort 1 Points [15, 0] Branch { Points [90, 0] Branch { DstBlock " BPSK" DstPort 1 } Branch { Points [0, 200] DstBlock " QBPSK" DstPort 1 } } Branch { Points [0, 295] DstBlock " QAM" DstPort 1 } } Line { SrcBlock "Relational4" SrcPort 1 Points [25, 0] Branch { Points [0, -90] DstBlock " BPSK" DstPort 2 } Branch { Points [0, 110] DstBlock "Inverter" DstPort 1 } } Line { SrcBlock "Inverter" SrcPort 1 DstBlock " QBPSK" DstPort 2 } Line { SrcBlock " BPSK" SrcPort 1 DstBlock "BPSK" DstPort 1 } Line { SrcBlock "I" SrcPort 1 DstBlock "AddSub" DstPort 1 } Line { SrcBlock "Q" SrcPort 1 DstBlock "AddSub" DstPort 2 } Line { SrcBlock " QBPSK" SrcPort 1 DstBlock "QBPSK" DstPort 1 } Line { SrcBlock " QAM" SrcPort 1 DstBlock "QAM" DstPort 1 } Annotation { Name "PHY Mode Det calc = sum(abs(I) - abs(Q)):\n Large Positive => BPSK\n Large Negative => QBPSK\n Nea" "r Zero => QAM" Position [469, 756] HorizontalAlignment "left" } } } Block { BlockType Reference Name "Mod_Sym_3" SID "722" Ports [3, 1] Position [960, 626, 1020, 694] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "60,68,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 68 68 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 60 60 0 0 ],[0 0 68 68 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[42.88 42.88 50" ".88 42.88 50.88 50.88 50.88 42.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[34.88 34.88 42.88 42.88 34.88" " ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[26.88 26.88 34.88 34.88 26.88 ],[1 1 1 ]);\npatch(" "[20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[18.88 18.88 26.88 18.88 26.88 26.88 18.88 ],[0.931 0.946 0.973 ]);\nfpr" "intf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'" ",1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'en');\ncolor('black');" "port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mod_Sym_4" SID "723" Ports [3, 1] Position [960, 731, 1020, 799] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "60,68,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 68 68 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 60 60 0 0 ],[0 0 68 68 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[42.88 42.88 50" ".88 42.88 50.88 50.88 50.88 42.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[34.88 34.88 42.88 42.88 34.88" " ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[26.88 26.88 34.88 34.88 26.88 ],[1 1 1 ]);\npatch(" "[20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[18.88 18.88 26.88 18.88 26.88 26.88 18.88 ],[0.931 0.946 0.973 ]);\nfpr" "intf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'" ",1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'en');\ncolor('black');" "port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Scope Name "PHY Mode Det" SID "724" Ports [8] Position [1185, 68, 1220, 277] ZOrder -3 Floating off Location [1, 45, 2476, 1599] Open off NumInputPorts "8" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" } List { ListType ScopeGraphics FigureColor "[0.5 0.5 0.5]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "10000" YMin "-2~-2~0~0~0~0~3.8~0.95" YMax "1.5~1.5~1~6~50~50~4.2~1.05" SaveName "ScopeData11" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType Reference Name "Q_Accum" SID "725" Ports [3, 1] Position [515, 386, 575, 444] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Accumulator" SourceType "Xilinx Accumulator Block" infoedit "Adder or subtracter-based accumulator. Output type and binary point position match the input.
Hardware notes: When \"Reinitialize with input 'b' on reset\" is selected, the accumulator is forced to run at t" "he system rate even if the input 'b' is running at a slower rate." operation "Add" n_bits "16" overflow "Wrap" scale "1" rst on infoeditControl "reset for floating point data type must be asserted for a minimum of 2 cycles" hasbypass off en on latency "0" dbl_ovrd off msb_inp "100" msb "100" lsb "-100" use_behavioral_HDL on implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "accum" sg_icon_stat "60,58,3,1,white,blue,0,ee9eb47a,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 58 58 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 60 60 0 0 ],[0 0 58 58 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[37.88 37.88 45" ".88 37.88 45.88 45.88 45.88 37.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[29.88 29.88 37.88 37.88 29.88" " ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[21.88 21.88 29.88 29.88 21.88 ],[1 1 1 ]);\npatch(" "[20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[13.88 13.88 21.88 13.88 21.88 21.88 13.88 ],[0.931 0.946 0.973 ]);\nfpr" "intf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'" ",1,'b');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'en');\ncolor('black');" "port_label('output',1,'\\bf+=b','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational1" SID "726" Ports [2, 1] Position [170, 640, 205, 675] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,35,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 35 35 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 35 35 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[22.55 22.55 27." "55 22.55 27.55 27.55 27.55 22.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[17.55 17.55 22.55 22.55 17." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[12.55 12.55 17.55 17.55 12.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[7.55 7.55 12.55 7.55 12.55 12.55 7.55 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input" "',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa = b','texmode','" "on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational2" SID "727" Ports [2, 1] Position [170, 690, 205, 725] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,35,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 35 35 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 35 35 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[22.55 22.55 27." "55 22.55 27.55 27.55 27.55 22.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[17.55 17.55 22.55 22.55 17." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[12.55 12.55 17.55 17.55 12.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[7.55 7.55 12.55 7.55 12.55 12.55 7.55 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input" "',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa = b','texmode','" "on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational3" SID "728" Ports [2, 1] Position [170, 765, 205, 800] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,35,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 35 35 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 35 35 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[22.55 22.55 27." "55 22.55 27.55 27.55 27.55 22.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[17.55 17.55 22.55 22.55 17." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[12.55 12.55 17.55 17.55 12.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[7.55 7.55 12.55 7.55 12.55 12.55 7.55 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input" "',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa = b','texmode','" "on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational4" SID "729" Ports [2, 1] Position [1140, 580, 1175, 615] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,35,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 35 35 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 35 35 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[22.55 22.55 27." "55 22.55 27.55 27.55 27.55 22.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[17.55 17.55 22.55 22.55 17." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[12.55 12.55 17.55 17.55 12.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[7.55 7.55 12.55 7.55 12.55 12.55 7.55 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input" "',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa = b','texmode','" "on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational6" SID "730" Ports [2, 1] Position [1140, 650, 1175, 685] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,35,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 35 35 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 35 35 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[22.55 22.55 27." "55 22.55 27.55 27.55 27.55 22.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[17.55 17.55 22.55 22.55 17." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[12.55 12.55 17.55 17.55 12.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[7.55 7.55 12.55 7.55 12.55 12.55 7.55 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input" "',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa = b','texmode','" "on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational7" SID "731" Ports [2, 1] Position [1140, 755, 1175, 790] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,35,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 35 35 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 35 35 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[22.55 22.55 27." "55 22.55 27.55 27.55 27.55 22.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[17.55 17.55 22.55 22.55 17." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[12.55 12.55 17.55 17.55 12.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[7.55 7.55 12.55 7.55 12.55 12.55 7.55 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input" "',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa = b','texmode','" "on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "edge" SID "732" Ports [1, 1] Position [280, 525, 320, 545] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "edge" Location [34, 75, 2338, 1290] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "733" Position [90, 33, 120, 47] IconDisplay "Port number" } Block { BlockType Reference Name "Delay6" SID "734" Ports [1, 1] Position [175, 48, 210, 72] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[15" ".33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.33 12." "33 15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 12.33 " "9.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\nc" "olor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical" SID "735" Ports [2, 1] Position [275, 32, 315, 68] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "XOR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,36,2,1,white,blue,0,dc21e094,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 36 36 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 36 36 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[23.55 23." "55 28.55 23.55 28.55 28.55 28.55 23.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[18.55 18.55 23.55 2" "3.55 18.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[13.55 13.55 18.55 18.55 13.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[8.55 8.55 13.55 8.55 13.55 13.55 8.55 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black" "');disp('xor');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "736" Position [340, 43, 370, 57] IconDisplay "Port number" } Line { SrcBlock "Delay6" SrcPort 1 DstBlock "Logical" DstPort 2 } Line { SrcBlock "D" SrcPort 1 Points [35, 0] Branch { DstBlock "Logical" DstPort 1 } Branch { DstBlock "Delay6" DstPort 1 } } Line { SrcBlock "Logical" SrcPort 1 DstBlock "Q" DstPort 1 } } } Block { BlockType SubSystem Name "negedge" SID "737" Ports [1, 1] Position [265, 700, 305, 720] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "negedge" Location [34, 75, 2338, 1290] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "738" Position [25, 33, 55, 47] IconDisplay "Port number" } Block { BlockType Reference Name "Delay6" SID "739" Ports [1, 1] Position [175, 48, 210, 72] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[15" ".33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.33 12." "33 15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 12.33 " "9.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\nc" "olor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "740" Ports [1, 1] Position [255, 26, 290, 54] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "35,28,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 28 28 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[18.44 18.4" "4 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[14.44 14.44 18.44 18.44 " "14.44 ],[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\np" "atch([12.1 25.88 21.88 17.88 13.88 8.1 12.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical" SID "741" Ports [2, 1] Position [330, 32, 370, 68] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,36,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 36 36 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 36 36 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[23.55 23." "55 28.55 23.55 28.55 28.55 28.55 23.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[18.55 18.55 23.55 2" "3.55 18.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[13.55 13.55 18.55 18.55 13.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[8.55 8.55 13.55 8.55 13.55 13.55 8.55 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black" "');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "742" Position [395, 43, 425, 57] IconDisplay "Port number" } Line { SrcBlock "Delay6" SrcPort 1 DstBlock "Logical" DstPort 2 } Line { SrcBlock "D" SrcPort 1 Points [100, 0] Branch { DstBlock "Delay6" DstPort 1 } Branch { DstBlock "Inverter" DstPort 1 } } Line { SrcBlock "Logical" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical" DstPort 1 } } } Block { BlockType SubSystem Name "negedge1" SID "743" Ports [1, 1] Position [265, 775, 305, 795] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "negedge1" Location [34, 75, 2338, 1290] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "744" Position [25, 33, 55, 47] IconDisplay "Port number" } Block { BlockType Reference Name "Delay6" SID "745" Ports [1, 1] Position [175, 48, 210, 72] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[15" ".33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.33 12." "33 15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 12.33 " "9.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\nc" "olor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "746" Ports [1, 1] Position [255, 26, 290, 54] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "35,28,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 28 28 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[18.44 18.4" "4 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[14.44 14.44 18.44 18.44 " "14.44 ],[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\np" "atch([12.1 25.88 21.88 17.88 13.88 8.1 12.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical" SID "747" Ports [2, 1] Position [330, 32, 370, 68] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,36,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 36 36 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 36 36 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[23.55 23." "55 28.55 23.55 28.55 28.55 28.55 23.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[18.55 18.55 23.55 2" "3.55 18.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[13.55 13.55 18.55 18.55 13.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[8.55 8.55 13.55 8.55 13.55 13.55 8.55 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black" "');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "748" Position [395, 43, 425, 57] IconDisplay "Port number" } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical" DstPort 1 } Line { SrcBlock "Logical" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "D" SrcPort 1 Points [100, 0] Branch { DstBlock "Inverter" DstPort 1 } Branch { DstBlock "Delay6" DstPort 1 } } Line { SrcBlock "Delay6" SrcPort 1 DstBlock "Logical" DstPort 2 } } } Block { BlockType Outport Name "11ac" SID "749" Position [1985, 608, 2015, 622] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Outport Name "11n" SID "750" Position [1985, 668, 2015, 682] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "11a/g" SID "751" Position [1985, 758, 2015, 772] NamePlacement "alternate" Port "3" IconDisplay "Port number" } Line { SrcBlock "Sym ind" SrcPort 1 Points [25, 0] Branch { DstBlock "Relational1" DstPort 1 } Branch { Points [0, 50] Branch { DstBlock "Relational2" DstPort 1 } Branch { Points [0, 75] DstBlock "Relational3" DstPort 1 } } Branch { Points [0, -115] Branch { DstBlock "LSB" DstPort 1 } Branch { Points [0, -375] DstBlock "Gateway Out2" DstPort 1 } } } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Relational1" DstPort 2 } Line { SrcBlock "Relational1" SrcPort 1 Points [210, 0] Branch { DstBlock "Mod_Sym_3" DstPort 2 } Branch { Points [0, 105] Branch { DstBlock "Mod_Sym_4" DstPort 2 } Branch { Points [0, 120; 1135, 0; 0, -130] Branch { DstBlock " 11ag" DstPort 2 } Branch { Points [0, -70] Branch { DstBlock " 11n" DstPort 2 } Branch { Points [0, -70] DstBlock " 11ac" DstPort 2 } } } } } Line { SrcBlock "Constant3" SrcPort 1 DstBlock "Relational2" DstPort 2 } Line { SrcBlock "Constant4" SrcPort 1 DstBlock "Relational3" DstPort 2 } Line { SrcBlock "negedge" SrcPort 1 Points [70, 0; 0, -30] DstBlock "Delay3" DstPort 1 } Line { SrcBlock "Relational2" SrcPort 1 DstBlock "negedge" DstPort 1 } Line { SrcBlock "Convert" SrcPort 1 DstBlock "Absolute" DstPort 1 } Line { SrcBlock "Relational3" SrcPort 1 DstBlock "negedge1" DstPort 1 } Line { SrcBlock "negedge1" SrcPort 1 DstBlock "Delay5" DstPort 1 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Absolute1" DstPort 1 } Line { SrcBlock "Absolute" SrcPort 1 DstBlock "I_Accum" DstPort 1 } Line { SrcBlock "Absolute1" SrcPort 1 DstBlock "Q_Accum" DstPort 1 } Line { SrcBlock "x_valid" SrcPort 1 Points [25, 0] Branch { DstBlock "Delay7" DstPort 1 } Branch { Points [0, -300] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "x_I" SrcPort 1 Points [15, 0] Branch { DstBlock "Convert" DstPort 1 } Branch { Points [0, -245] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "x_Q" SrcPort 1 Points [20, 0] Branch { DstBlock "Convert1" DstPort 1 } Branch { Points [0, -285] DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "Delay7" SrcPort 1 Points [55, 0] Branch { DstBlock "Q_Accum" DstPort 3 } Branch { Points [0, -65] DstBlock "I_Accum" DstPort 3 } } Line { SrcBlock "LSB" SrcPort 1 DstBlock "edge" DstPort 1 } Line { SrcBlock "edge" SrcPort 1 DstBlock "Convert2" DstPort 1 } Line { SrcBlock "I_Accum" SrcPort 1 Points [40, 0] Branch { DstBlock "Mod Det" DstPort 1 } Branch { Points [0, -165] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "Q_Accum" SrcPort 1 Points [45, 0; 0, -35] Branch { DstBlock "Mod Det" DstPort 2 } Branch { Points [0, -170] DstBlock "Gateway Out8" DstPort 1 } } Line { SrcBlock "Concat" SrcPort 1 Points [65, 0; 0, 265] Branch { DstBlock "Mod_Sym_3" DstPort 1 } Branch { Points [0, 105] DstBlock "Mod_Sym_4" DstPort 1 } } Line { SrcBlock "Constant5" SrcPort 1 DstBlock "Relational4" DstPort 2 } Line { SrcBlock "Mod_Sym_3" SrcPort 1 Points [30, 0] Branch { Points [0, -70] DstBlock "Relational4" DstPort 1 } Branch { DstBlock "Relational6" DstPort 1 } } Line { SrcBlock "Constant7" SrcPort 1 DstBlock "Relational6" DstPort 2 } Line { SrcBlock "Mod Det" SrcPort 2 Points [25, 0] Branch { DstBlock "Concat" DstPort 1 } Branch { Points [0, -130] DstBlock "Concat2" DstPort 2 } } Line { SrcBlock "Mod Det" SrcPort 3 Points [30, 0] Branch { DstBlock "Concat" DstPort 2 } Branch { Points [0, -135] DstBlock "Concat2" DstPort 3 } } Line { SrcBlock "Mod_Sym_4" SrcPort 1 DstBlock "Relational7" DstPort 1 } Line { SrcBlock "Constant8" SrcPort 1 DstBlock "Relational7" DstPort 2 } Line { SrcBlock "Relational6" SrcPort 1 Points [180, 0] Branch { Points [0, 80] DstBlock "Logical4" DstPort 2 } Branch { DstBlock " 11n" DstPort 1 } } Line { SrcBlock "Relational7" SrcPort 1 Points [40, 0; 0, -150] DstBlock "Logical2" DstPort 3 } Line { SrcBlock "Relational4" SrcPort 1 DstBlock "Logical2" DstPort 2 } Line { SrcBlock "Logical2" SrcPort 1 Points [10, 0] Branch { Points [0, 130] DstBlock "Logical4" DstPort 1 } Branch { DstBlock " 11ac" DstPort 1 } } Line { SrcBlock "Logical4" SrcPort 1 DstBlock " 11ag" DstPort 1 } Line { SrcBlock "Delay3" SrcPort 1 Points [185, 0] Branch { DstBlock "Mod_Sym_3" DstPort 3 } Branch { Points [0, 185] DstBlock "Delay1" DstPort 1 } } Line { SrcBlock "Delay5" SrcPort 1 Points [195, 0] Branch { DstBlock "Mod_Sym_4" DstPort 3 } Branch { Points [0, 60] DstBlock "Delay2" DstPort 1 } } Line { SrcBlock "Logical3" SrcPort 1 Points [475, 0; 0, -85] Branch { DstBlock " 11ag" DstPort 3 } Branch { Points [0, -70] Branch { DstBlock " 11n" DstPort 3 } Branch { Points [0, -70] DstBlock " 11ac" DstPort 3 } } } Line { SrcBlock " 11ag" SrcPort 1 Points [50, 0] Branch { Points [0, -240] DstBlock "Concat1" DstPort 3 } Branch { DstBlock "Assert2" DstPort 1 } } Line { Name "X_I" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 DstBlock "PHY Mode Det" DstPort 1 } Line { Name "X_Q" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 DstBlock "PHY Mode Det" DstPort 2 } Line { Name "Sym_Ind" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 DstBlock "PHY Mode Det" DstPort 4 } Line { Name "x_valid" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 DstBlock "PHY Mode Det" DstPort 3 } Line { SrcBlock "Concat2" SrcPort 1 DstBlock "Gateway Out5" DstPort 1 } Line { Name "mod_det" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 DstBlock "PHY Mode Det" DstPort 7 } Line { Name "PHY_mode" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 DstBlock "PHY Mode Det" DstPort 8 } Line { Name "I_Accum" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 DstBlock "PHY Mode Det" DstPort 5 } Line { Name "Q_Accum" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 DstBlock "PHY Mode Det" DstPort 6 } Line { SrcBlock "Convert2" SrcPort 1 Points [65, 0; 0, -120] Branch { DstBlock "Q_Accum" DstPort 2 } Branch { Points [0, -65] DstBlock "I_Accum" DstPort 2 } } Line { SrcBlock "Mod Det" SrcPort 1 Points [15, 0; 0, -125] DstBlock "Concat2" DstPort 1 } Line { SrcBlock " 11n" SrcPort 1 Points [40, 0] Branch { Points [0, -200] DstBlock "Concat1" DstPort 2 } Branch { DstBlock "Assert1" DstPort 1 } } Line { SrcBlock " 11ac" SrcPort 1 Points [25, 0] Branch { Points [0, -160] DstBlock "Concat1" DstPort 1 } Branch { DstBlock "Assert" DstPort 1 } } Line { SrcBlock "Concat1" SrcPort 1 Points [-605, 0; 0, -225] DstBlock "Gateway Out6" DstPort 1 } Line { SrcBlock "Assert" SrcPort 1 DstBlock "11ac" DstPort 1 } Line { SrcBlock "Assert1" SrcPort 1 DstBlock "Logical1" DstPort 2 } Line { SrcBlock "Assert2" SrcPort 1 DstBlock "Logical5" DstPort 1 } Line { SrcBlock "Delay2" SrcPort 1 DstBlock "Logical3" DstPort 1 } Line { SrcBlock "Delay1" SrcPort 1 DstBlock "Logical3" DstPort 2 } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "11n" DstPort 1 } Line { SrcBlock "From" SrcPort 1 Points [105, 0; 0, 320] Branch { DstBlock "Logical1" DstPort 1 } Branch { Points [0, 110] DstBlock "Inverter" DstPort 1 } } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical5" DstPort 2 } Line { SrcBlock "Logical5" SrcPort 1 DstBlock "11a/g" DstPort 1 } Line { SrcBlock "From1" SrcPort 1 Points [55, 0; 0, 40] DstBlock "Logical2" DstPort 1 } Annotation { Name "OFDM Symbols in 11a/g:\n0: LTF (BPSK)\n1: LTF (BPSK)\n2: SIG (BPSK)\n3-N: Data" Position [954, 943] HorizontalAlignment "left" } Annotation { Name "PHY Mode\n001: 11a/g\n010: 11n\n100: 11ac" Position [1597, 409] HorizontalAlignment "left" } Annotation { Name "OFDM Symbols in 11n SISO:\n0: L-LTF (BPSK)\n1: L-LTF (BPSK)\n2: L-SIG (BPSK)\n3: HT-SIG1 (QBPSK)\n4: HT-" "SIG2 (QBPSK)\n5: HT-STF\n6: HT-LFT1\n7-N: Data" Position [1104, 968] HorizontalAlignment "left" } Annotation { Name "OFDM Symbols in 11ac SISO:\n0: L-LTF (BPSK)\n1: L-LTF (BPSK)\n2: L-SIG (BPSK)\n3: VHT-SIGA1 (BPSK)\n4: V" "HT-SIGA2 (QBPSK)\n5: VHT-STF\n6: VHT-LFT1\n7: VHT-SIGB\n8-N: Data" Position [1279, 983] HorizontalAlignment "left" } Annotation { Name "Assert rates here to avoid\nrate ambiguity when these\nsignals are fed back to earlier\nblocks in the pi" "peline" Position [1761, 825] } Annotation { Name "Mark all Rx as 11a/g when 11n mode\nis disabled." Position [2034, 717] } } } Block { BlockType SubSystem Name "Phase Err Calc" SID "752" Ports [5, 2] Position [990, 451, 1105, 549] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Phase Err Calc" Location [2, 74, 2464, 1576] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "156" Block { BlockType Inport Name "CP_I" SID "753" Position [130, 213, 160, 227] IconDisplay "Port number" } Block { BlockType Inport Name "CP_Q" SID "754" Position [130, 248, 160, 262] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "x_valid" SID "755" Position [130, 123, 160, 137] NamePlacement "alternate" Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "x_ind" SID "756" Position [130, 153, 160, 167] Port "4" IconDisplay "Port number" } Block { BlockType Inport Name "sym_ind" SID "757" Position [130, 283, 160, 297] Port "5" IconDisplay "Port number" } Block { BlockType Reference Name "Constant3" SID "774" Ports [0, 1] Position [225, 345, 245, 365] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "6" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "8" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "20,20,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 20 20 0 0 ],[0 0 20 20 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[12.22 12.22 14." "22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[10.22 10.22 12.22 12.22 10.22 ]" ",[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatch([7.55 " "14.44 12.44 10.44 8.44 5.55 7.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'0');\nfpr" "intf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Count" SID "775" Ports [2, 1] Position [670, 321, 715, 359] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Count" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "En" SID "776" Position [490, 493, 520, 507] IconDisplay "Port number" } Block { BlockType Inport Name "Rst" SID "777" Position [405, 468, 435, 482] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Constant3" SID "778" Ports [0, 1] Position [710, 415, 730, 435] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "4" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "6" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "8" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "20,20,0,1,white,blue,0,85f36853,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 20 20 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 20 20 0 0 ],[0 0 20 20 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[12.22 12." "22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[10.22 10.22 12.22 12.22" " 10.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npa" "tch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfprin" "tf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output" "',1,'4');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Counter" SID "779" Ports [2, 1] Position [610, 464, 660, 511] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited count" "er is implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "Inf" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "3" bin_pt "0" load_pin off rst on en on explicit_period "off" period "1" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "counter" sg_icon_stat "50,47,2,1,white,blue,0,ae3608d6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 47 47 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 47 47 0 ]);\npatch([11.65 20.32 26.32 32.32 38.32 26.32 17.65 11.65 ],[29.66" " 29.66 35.66 29.66 35.66 35.66 35.66 29.66 ],[1 1 1 ]);\npatch([17.65 26.32 20.32 11.65 17.65 ],[23.66 23.66 29." "66 29.66 23.66 ],[0.931 0.946 0.973 ]);\npatch([11.65 20.32 26.32 17.65 11.65 ],[17.66 17.66 23.66 23.66 17.66 ]" ",[1 1 1 ]);\npatch([17.65 38.32 32.32 26.32 20.32 11.65 17.65 ],[11.66 11.66 17.66 11.66 17.66 17.66 11.66 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'rst');\ncolor('black');port_label('input',2,'en');\n\ncolor('black');disp('{\\font" "size{14}\\bf++}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay" SID "780" Ports [1, 1] Position [615, 527, 655, 563] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "40,36,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 36 36 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 36 36 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[23.55 23." "55 28.55 23.55 28.55 28.55 28.55 23.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[18.55 18.55 23.55 2" "3.55 18.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[13.55 13.55 18.55 18.55 13.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[8.55 8.55 13.55 8.55 13.55 13.55 8.55 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black')" ";disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay1" SID "781" Ports [1, 1] Position [985, 427, 1025, 463] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "4" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "40,36,1,1,white,blue,0,d390c2d8,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 36 36 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 36 36 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[23.55 23." "55 28.55 23.55 28.55 28.55 28.55 23.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[18.55 18.55 23.55 2" "3.55 18.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[13.55 13.55 18.55 18.55 13.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[8.55 8.55 13.55 8.55 13.55 13.55 8.55 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black')" ";disp('z^{-4}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical" SID "782" Ports [2, 1] Position [885, 426, 920, 464] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,38,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 38 38 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 38 38 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[24.55 24." "55 29.55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[19.55 19.55 24.55 2" "4.55 19.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black" "');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational7" SID "783" Ports [2, 1] Position [780, 414, 820, 461] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[2 0 0 3 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,47,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 47 47 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 47 47 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[28.55 28." "55 33.55 28.55 33.55 33.55 33.55 28.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[23.55 23.55 28.55 2" "8.55 23.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[18.55 18.55 23.55 23.55 18.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[13.55 13.55 18.55 13.55 18.55 18.55 13.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bfa = b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Last" SID "784" Position [1095, 438, 1125, 452] IconDisplay "Port number" } Line { SrcBlock "Counter" SrcPort 1 Points [70, 0; 0, -35] DstBlock "Relational7" DstPort 2 } Line { SrcBlock "Constant3" SrcPort 1 DstBlock "Relational7" DstPort 1 } Line { SrcBlock "Relational7" SrcPort 1 Points [0, -5] DstBlock "Logical" DstPort 1 } Line { SrcBlock "En" SrcPort 1 Points [45, 0] Branch { DstBlock "Counter" DstPort 2 } Branch { Points [0, 45] DstBlock "Delay" DstPort 1 } } Line { SrcBlock "Rst" SrcPort 1 DstBlock "Counter" DstPort 1 } Line { SrcBlock "Logical" SrcPort 1 DstBlock "Delay1" DstPort 1 } Line { SrcBlock "Delay" SrcPort 1 Points [175, 0; 0, -90] DstBlock "Logical" DstPort 2 } Line { SrcBlock "Delay1" SrcPort 1 DstBlock "Last" DstPort 1 } Annotation { Name "Latency to match phase accum latency" Position [1036, 493] } } } Block { BlockType Reference Name "Delay8" SID "785" Ports [1, 1] Position [445, 126, 465, 144] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "20,18,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 20 20 0 0 ],[0 0 18 18 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[11.22 11.22 13." "22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[9.22 9.22 11.22 11.22 9.22 ],[0" ".931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([7.55 14.44" " 12.44 10.44 8.44 5.55 7.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: e" "nd icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-1}','texmode','on');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Descramble" SID "786" Ports [4, 2] Position [420, 168, 485, 307] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Descramble" Location [-1678, 70, -18, 1030] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Negate" SID "787" Position [810, 468, 840, 482] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "x_I" SID "788" Position [855, 653, 885, 667] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "x_Q" SID "789" Position [855, 753, 885, 767] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "Sym Ind" SID "790" Position [295, 548, 325, 562] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "791" Ports [0, 1] Position [355, 407, 385, 423] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "5" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,16,0,1,white,blue,0,98872051,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 16 16 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_la" "bel('output',1,'5');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant2" SID "792" Ports [0, 1] Position [290, 597, 325, 623] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "3" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "8" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "35,26,0,1,white,blue,0,279a71c8,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 26 26 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 26 26 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[13.33 13." "33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[10.33 10.33 13.33 13.3" "3 10.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7." "33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n" "color('black');port_label('output',1,'3');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant3" SID "793" Ports [0, 1] Position [355, 452, 385, 468] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "6" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,16,0,1,white,blue,0,f0403ad7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 16 16 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_la" "bel('output',1,'6');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay" SID "794" Ports [1, 1] Position [970, 647, 995, 673] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "25,26,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 " "16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33" " 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('blac" "k');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay1" SID "795" Ports [1, 1] Position [970, 747, 995, 773] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "25,26,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 " "16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33" " 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('blac" "k');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay2" SID "796" Ports [1, 1] Position [970, 542, 995, 568] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "25,26,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 " "16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33" " 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('blac" "k');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay3" SID "797" Ports [1, 1] Position [647, 490, 673, 515] BlockRotation 270 BlockMirror on ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "26,25,1,1,white,blue,0,07b98262,down,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 26 26 0 0 ],[0 0 25 25 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 26 26 0 0 ],[0 0 25 25 0 ]);\npatch([6.325 10.66 13.66 16.66 19.66 13.66 9.325 6.325 ],[15.33" " 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([9.325 13.66 10.66 6.325 9.325 ],[12.33 12.33 15." "33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([6.325 10.66 13.66 9.325 6.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1" " 1 1 ]);\npatch([9.325 19.66 16.66 13.66 10.66 6.325 9.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black'" ");disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "798" Position [315, 358, 480, 382] ZOrder -9 ShowName off GotoTag "RX_PHY_MODE_11N_AC" TagVisibility "global" } Block { BlockType Reference Name "Logical" SID "799" Ports [2, 1] Position [885, 536, 920, 569] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "XOR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,33,2,1,white,blue,0,dc21e094,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 33 33 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 33 33 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[20.44 20.4" "4 24.44 20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[16.44 16.44 20.44 20.44 " "16.44 ],[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1 1 1 ]);\np" "atch([12.1 25.88 21.88 17.88 13.88 8.1 12.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('xo" "r');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "800" Ports [2, 1] Position [515, 447, 555, 478] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,31,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 31 31 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 31 31 0 ]);\npatch([11.1 16.88 20.88 24.88 28.88 20.88 15.1 11.1 ],[19.44 19" ".44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([15.1 20.88 16.88 11.1 15.1 ],[15.44 15.44 19.44 19." "44 15.44 ],[0.931 0.946 0.973 ]);\npatch([11.1 16.88 20.88 15.1 11.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]" ");\npatch([15.1 28.88 24.88 20.88 16.88 11.1 15.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 " "]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');di" "sp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "801" Ports [2, 1] Position [690, 532, 730, 563] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,31,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 31 31 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 31 31 0 ]);\npatch([11.1 16.88 20.88 24.88 28.88 20.88 15.1 11.1 ],[19.44 19" ".44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([15.1 20.88 16.88 11.1 15.1 ],[15.44 15.44 19.44 19." "44 15.44 ],[0.931 0.946 0.973 ]);\npatch([11.1 16.88 20.88 15.1 11.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]" ");\npatch([15.1 28.88 24.88 20.88 16.88 11.1 15.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 " "]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');di" "sp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical4" SID "802" Ports [2, 1] Position [600, 426, 640, 479] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "NAND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,53,2,1,white,blue,0,68c5cabf,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 53 53 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 53 53 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[31.55 31." "55 36.55 31.55 36.55 36.55 36.55 31.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[26.55 26.55 31.55 3" "1.55 26.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[21.55 21.55 26.55 26.55 21.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[16.55 16.55 21.55 16.55 21.55 21.55 16.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('b" "lack');disp('nand');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux1" SID "803" Ports [3, 1] Position [1070, 615, 1090, 705] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Signed (2's comp)" n_bits "8" bin_pt "2" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[16 0 0 32 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" block_version "VER_STRING_GOES_HERE" sg_icon_stat "20,90,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 12.8571 77.1429 90 0 ]" ",[0.77 0.82 0.91 ]);\nplot([0 20 20 0 0 ],[0 12.8571 77.1429 90 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 " "7.55 5.55 ],[47.22 47.22 49.22 47.22 49.22 49.22 49.22 47.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[4" "5.22 45.22 47.22 47.22 45.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[43.22 43.22 45.22 45." "22 43.22 ],[1 1 1 ]);\npatch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[41.22 41.22 43.22 41.22 43.22 43.22 41.22" " ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nc" "olor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_labe" "l('input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux2" SID "804" Ports [3, 1] Position [1070, 715, 1090, 805] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Signed (2's comp)" n_bits "8" bin_pt "2" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[16 0 0 32 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" block_version "VER_STRING_GOES_HERE" sg_icon_stat "20,90,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 12.8571 77.1429 90 0 ]" ",[0.77 0.82 0.91 ]);\nplot([0 20 20 0 0 ],[0 12.8571 77.1429 90 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 " "7.55 5.55 ],[47.22 47.22 49.22 47.22 49.22 49.22 49.22 47.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[4" "5.22 45.22 47.22 47.22 45.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[43.22 43.22 45.22 45." "22 43.22 ],[1 1 1 ]);\npatch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[41.22 41.22 43.22 41.22 43.22 43.22 41.22" " ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nc" "olor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_labe" "l('input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Negate1" SID "805" Ports [1, 1] Position [965, 675, 995, 705] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Negate" SourceType "Xilinx Negate Block Block" precision "Full" arith_type "Signed (2's comp)" n_bits "17" bin_pt "15" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" en off latency "1" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "negate" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,30,1,1,white,blue,0,fc5ddbd7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 30 30 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 30 30 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 19.4" "4 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 19.44 " "15.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\np" "atch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-" "1}\\newline ','texmode','on');\ncolor('black');disp(' \\newline\\bf{x(-1)}','texmode','on');\nfprintf('','COMMEN" "T: end icon text');" } Block { BlockType Reference Name "Negate2" SID "806" Ports [1, 1] Position [965, 775, 995, 805] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Negate" SourceType "Xilinx Negate Block Block" precision "Full" arith_type "Signed (2's comp)" n_bits "17" bin_pt "15" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" en off latency "1" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "negate" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,30,1,1,white,blue,0,fc5ddbd7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 30 30 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 30 30 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 19.4" "4 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 19.44 " "15.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\np" "atch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-" "1}\\newline ','texmode','on');\ncolor('black');disp(' \\newline\\bf{x(-1)}','texmode','on');\nfprintf('','COMMEN" "T: end icon text');" } Block { BlockType Reference Name "Relational1" SID "807" Ports [2, 1] Position [430, 405, 465, 440] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,35,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 35 35 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 35 35 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[22.55 22." "55 27.55 22.55 27.55 27.55 27.55 22.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[17.55 17.55 22.55 2" "2.55 17.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[12.55 12.55 17.55 17.55 12.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[7.55 7.55 12.55 7.55 12.55 12.55 7.55 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');por" "t_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa " "= b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational2" SID "808" Ports [2, 1] Position [375, 579, 420, 621] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a
Hardware notes: In hardware th" "is block costs nothing." assert_type on type_source "Explicitly" gui_display_data_type "Boolean" arith_type "Boolean" n_bits "16" bin_pt "14" preci_type "Single" exp_width "8" frac_width "24" assert_rate on rate_source "Explicitly" period "1" output_port on has_advanced_control "0" sggui_pos "20,20,356,436" block_type "assert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,16,1,1,white,blue,0,9657e937,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 16 16 0 ]);\npatch([17.55 20.44 22.44 24.44 26.44 22.44 19.55 17.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([19.55 22.44 20.44 17.55 19.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([17.55 20.44 22.44 19.55 17.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([19.55 26.44 24.44 22.44 20.44 17.55 19.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');dis" "p('Assert');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Assert1" SID "814" Ports [1, 1] Position [665, 257, 710, 273] BlockMirror on NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Assert" SourceType "Xilinx Assert Block" infoedit "Asserts a user-defined sample rate and/or type on a signal.

Hardware notes: In hardware this" " block costs nothing." assert_type on type_source "Explicitly" gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "16" bin_pt "14" preci_type "Single" exp_width "8" frac_width "24" assert_rate on rate_source "Explicitly" period "1" output_port on has_advanced_control "0" sggui_pos "20,20,356,436" block_type "assert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,16,1,1,white,blue,0,9657e937,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 16 16 0 ]);\npatch([17.55 20.44 22.44 24.44 26.44 22.44 19.55 17.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([19.55 22.44 20.44 17.55 19.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([17.55 20.44 22.44 19.55 17.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([19.55 26.44 24.44 22.44 20.44 17.55 19.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');dis" "p('Assert');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert" SID "815" Ports [1, 1] Position [305, 475, 330, 495] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "16" bin_pt "14" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,20,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 20 20 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 20 20 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[12.22 12" ".22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[10.22 10.22 12.22 12." "22 10.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\n" "patch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('o" "utput',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "816" Ports [1, 1] Position [305, 500, 330, 520] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "16" bin_pt "14" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,20,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 20 20 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 20 20 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[12.22 12" ".22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[10.22 10.22 12.22 12." "22 10.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\n" "patch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('o" "utput',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical" SID "817" Ports [2, 1] Position [575, 233, 620, 277] BlockMirror on NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "XOR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,2,1,white,blue,0,dc21e094,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('" "black');disp('xor');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register" SID "818" Ports [3, 1] Position [400, 306, 445, 354] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "1" rst on en on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "819" Ports [3, 1] Position [485, 306, 530, 354] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "1" rst on en on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "820" Ports [3, 1] Position [575, 306, 620, 354] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "1" rst on en on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Reference Name "Register3" SID "821" Ports [3, 1] Position [665, 306, 710, 354] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "1" rst on en on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Reference Name "Register4" SID "822" Ports [3, 1] Position [825, 306, 870, 354] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "1" rst on en on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Reference Name "Register5" SID "823" Ports [3, 1] Position [915, 306, 960, 354] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "1" rst on en on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Reference Name "Register6" SID "824" Ports [3, 1] Position [1000, 306, 1045, 354] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "1" rst on en on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "825" Position [585, 188, 615, 202] NamePlacement "alternate" IconDisplay "Port number" } Line { SrcBlock "rst" SrcPort 1 DstBlock "Convert" DstPort 1 } Line { SrcBlock "Register6" SrcPort 1 Points [20, 0; 0, -85] DstBlock "Assert" DstPort 1 } Line { SrcBlock "Logical" SrcPort 1 Points [-225, 0] Branch { Points [0, 60] DstBlock "Register" DstPort 1 } Branch { Points [0, -60] DstBlock "Q" DstPort 1 } } Line { SrcBlock "Register5" SrcPort 1 Points [0, -15] DstBlock "Register6" DstPort 1 } Line { SrcBlock "Register4" SrcPort 1 Points [10, 0; 0, -15] DstBlock "Register5" DstPort 1 } Line { SrcBlock "Register3" SrcPort 1 Points [45, 0; 0, -15] Branch { DstBlock "Register4" DstPort 1 } Branch { Points [0, -50] DstBlock "Assert1" DstPort 1 } } Line { SrcBlock "Register2" SrcPort 1 Points [10, 0; 0, -15] DstBlock "Register3" DstPort 1 } Line { SrcBlock "Register1" SrcPort 1 Points [0, -15] DstBlock "Register2" DstPort 1 } Line { SrcBlock "Register" SrcPort 1 Points [5, 0; 0, -15] DstBlock "Register1" DstPort 1 } Line { SrcBlock "Assert" SrcPort 1 DstBlock "Logical" DstPort 1 } Line { SrcBlock "Assert1" SrcPort 1 DstBlock "Logical" DstPort 2 } Line { SrcBlock "en" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Convert" SrcPort 1 Points [30, 0] Branch { Points [0, -155] DstBlock "Register" DstPort 2 } Branch { Points [95, 0] Branch { Points [0, -155] DstBlock "Register1" DstPort 2 } Branch { Points [80, 0] Branch { Points [0, -155] DstBlock "Register2" DstPort 2 } Branch { Points [100, 0] Branch { Points [0, -155] DstBlock "Register3" DstPort 2 } Branch { Points [150, 0] Branch { Points [0, -155] DstBlock "Register4" DstPort 2 } Branch { Points [100, 0] Branch { Points [0, -155] DstBlock "Register5" DstPort 2 } Branch { Points [80, 0; 0, -155] DstBlock "Register6" DstPort 2 } } } } } } } Line { SrcBlock "Convert1" SrcPort 1 Points [40, 0] Branch { Points [0, -165] DstBlock "Register" DstPort 3 } Branch { Points [95, 0] Branch { DstBlock "Register1" DstPort 3 } Branch { Points [80, 0] Branch { Points [0, -165] DstBlock "Register2" DstPort 3 } Branch { Points [100, 0] Branch { DstBlock "Register3" DstPort 3 } Branch { Points [150, 0] Branch { Points [0, -165] DstBlock "Register4" DstPort 3 } Branch { Points [100, 0] Branch { DstBlock "Register5" DstPort 3 } Branch { Points [75, 0; 0, -165] DstBlock "Register6" DstPort 3 } } } } } } } Annotation { Name "Was 0!" Position [510, 370] } } } Block { BlockType SubSystem Name "edge" SID "826" Ports [1, 1] Position [375, 541, 415, 569] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "edge" Location [1175, 774, 1570, 870] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "827" Position [25, 33, 55, 47] IconDisplay "Port number" } Block { BlockType Reference Name "Delay6" SID "828" Ports [1, 1] Position [175, 48, 210, 72] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[15" ".33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.33 12." "33 15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 12.33 " "9.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\nc" "olor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "LSB" SID "829" Ports [1, 1] Position [90, 28, 120, 52] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "30,24,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 24 24 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 24 24 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[15.3" "3 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[12.33 12.33 " "15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[9.33 9.33 12.33 12.33 9.33 " "],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('bl" "ack');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical" SID "830" Ports [2, 1] Position [275, 32, 315, 68] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "XOR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,36,2,1,white,blue,0,dc21e094,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 36 36 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 36 36 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[23.55 23." "55 28.55 23.55 28.55 28.55 28.55 23.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[18.55 18.55 23.55 2" "3.55 18.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[13.55 13.55 18.55 18.55 13.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[8.55 8.55 13.55 8.55 13.55 13.55 8.55 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black" "');disp('xor');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "831" Position [340, 43, 370, 57] IconDisplay "Port number" } Line { SrcBlock "LSB" SrcPort 1 Points [35, 0] Branch { DstBlock "Logical" DstPort 1 } Branch { DstBlock "Delay6" DstPort 1 } } Line { SrcBlock "Delay6" SrcPort 1 DstBlock "Logical" DstPort 2 } Line { SrcBlock "D" SrcPort 1 DstBlock "LSB" DstPort 1 } Line { SrcBlock "Logical" SrcPort 1 DstBlock "Q" DstPort 1 } } } Block { BlockType Outport Name " x_I" SID "832" Position [1155, 653, 1185, 667] IconDisplay "Port number" } Block { BlockType Outport Name " x_Q" SID "833" Position [1155, 753, 1185, 767] Port "2" IconDisplay "Port number" } Line { SrcBlock "Constant2" SrcPort 1 DstBlock "Relational2" DstPort 2 } Line { SrcBlock "Relational2" SrcPort 1 Points [320, 0; 0, -30] DstBlock "Scrambling LFSR" DstPort 2 } Line { SrcBlock "Scrambling LFSR" SrcPort 1 DstBlock "Logical" DstPort 2 } Line { SrcBlock "Logical" SrcPort 1 DstBlock "Delay2" DstPort 1 } Line { SrcBlock "Negate1" SrcPort 1 DstBlock "Mux1" DstPort 3 } Line { SrcBlock "x_I" SrcPort 1 Points [55, 0] Branch { Points [0, 30] DstBlock "Negate1" DstPort 1 } Branch { DstBlock "Delay" DstPort 1 } } Line { SrcBlock "Sym Ind" SrcPort 1 Points [15, 0] Branch { DstBlock "edge" DstPort 1 } Branch { Points [0, 35] DstBlock "Relational2" DstPort 1 } Branch { Points [0, -80] Branch { DstBlock "Relational4" DstPort 2 } Branch { Points [0, -45] DstBlock "Relational1" DstPort 2 } } } Line { SrcBlock "Negate" SrcPort 1 Points [20, 0; 0, 70] DstBlock "Logical" DstPort 1 } Line { SrcBlock "Mux1" SrcPort 1 DstBlock " x_I" DstPort 1 } Line { SrcBlock "Negate2" SrcPort 1 DstBlock "Mux2" DstPort 3 } Line { SrcBlock "x_Q" SrcPort 1 Points [55, 0] Branch { Points [0, 30] DstBlock "Negate2" DstPort 1 } Branch { DstBlock "Delay1" DstPort 1 } } Line { SrcBlock "Mux2" SrcPort 1 DstBlock " x_Q" DstPort 1 } Line { SrcBlock "Delay" SrcPort 1 DstBlock "Mux1" DstPort 2 } Line { SrcBlock "Delay1" SrcPort 1 DstBlock "Mux2" DstPort 2 } Line { SrcBlock "Delay2" SrcPort 1 Points [40, 0; 0, 75] Branch { DstBlock "Mux1" DstPort 1 } Branch { Points [0, 100] DstBlock "Mux2" DstPort 1 } } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Relational1" DstPort 1 } Line { SrcBlock "Constant3" SrcPort 1 DstBlock "Relational4" DstPort 1 } Line { SrcBlock "Relational1" SrcPort 1 Points [20, 0; 0, 30] DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Relational4" SrcPort 1 DstBlock "Logical1" DstPort 2 } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Logical4" DstPort 2 } Line { SrcBlock "From" SrcPort 1 Points [55, 0; 0, 70] DstBlock "Logical4" DstPort 1 } Line { SrcBlock "Logical2" SrcPort 1 DstBlock "Scrambling LFSR" DstPort 1 } Line { SrcBlock "edge" SrcPort 1 DstBlock "Logical2" DstPort 2 } Line { SrcBlock "Logical4" SrcPort 1 Points [15, 0] DstBlock "Delay3" DstPort 1 } Line { SrcBlock "Delay3" SrcPort 1 Points [0, 20] DstBlock "Logical2" DstPort 1 } Annotation { Name "Match latency of edge det\non sym index" Position [742, 504] } Annotation { Name "Advance state of pilot scrambling LFSR on all\nOFDM symbols *except* HT-SFT/HT-LTF in\nsymbols 5,6" Position [394, 324] } } } Block { BlockType Reference Name "Gateway Out1" SID "9514" Ports [1, 1] Position [985, 564, 1020, 576] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Sym Ind" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out10" SID "834" Ports [1, 1] Position [985, 764, 1020, 776] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Conj Prod Q" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "9540" Ports [1, 1] Position [985, 589, 1020, 601] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Accum Resets" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "835" Ports [1, 1] Position [985, 614, 1020, 626] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Accum I" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "836" Ports [1, 1] Position [985, 639, 1020, 651] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Accum Q" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "837" Ports [1, 1] Position [985, 664, 1020, 676] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Phase Err" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "838" Ports [1, 1] Position [985, 689, 1020, 701] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Descram I" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "839" Ports [1, 1] Position [985, 714, 1020, 726] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Descram Q" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "840" Ports [1, 1] Position [985, 539, 1020, 551] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Sc Ind" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out9" SID "841" Ports [1, 1] Position [985, 739, 1020, 751] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Conj Prod I" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType SubSystem Name "IQ Accum" SID "9561" Ports [4, 2] Position [650, 199, 735, 256] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "IQ Accum" Location [2, 70, 2469, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "156" Block { BlockType Inport Name "I" SID "9578" Position [400, 213, 430, 227] IconDisplay "Port number" } Block { BlockType Inport Name "Q" SID "9563" Position [400, 358, 430, 372] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "En" SID "9562" Position [400, 458, 430, 472] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "Rst" SID "9564" Position [400, 418, 430, 432] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub1" SID "9572" Ports [2, 1] Position [550, 333, 590, 377] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "4" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL off hw_selection "DSP48" pipelined off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" sg_icon_stat "40,44,2,1,white,blue,0,eeab5c4c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 44 44 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[27.55 27." "55 32.55 27.55 32.55 32.55 32.55 27.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[22.55 22.55 27.55 2" "7.55 22.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[17.55 17.55 22.55 22.55 17.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[12.55 12.55 17.55 12.55 17.55 17.55 12.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bf{a + b}','texmode','on');\ncolor('black');disp('z^{-4}\\newline ','texmode','on');\ncolor('black');disp(' \\ne" "wline\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub2" SID "9575" Ports [2, 1] Position [540, 188, 580, 232] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "4" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL off hw_selection "DSP48" pipelined off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" sg_icon_stat "40,44,2,1,white,blue,0,eeab5c4c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 44 44 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[27.55 27." "55 32.55 27.55 32.55 32.55 32.55 27.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[22.55 22.55 27.55 2" "7.55 22.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[17.55 17.55 22.55 22.55 17.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[12.55 12.55 17.55 12.55 17.55 17.55 12.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bf{a + b}','texmode','on');\ncolor('black');disp('z^{-4}\\newline ','texmode','on');\ncolor('black');disp(' \\ne" "wline\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Assert" SID "9574" Ports [1, 1] Position [690, 308, 720, 322] BlockMirror on NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Assert" SourceType "Xilinx Assert Block" infoedit "Asserts a user-defined sample rate and/or type on a signal.

Hardware notes: In hardware th" "is block costs nothing." assert_type off type_source "Explicitly" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "16" bin_pt "14" preci_type "Single" exp_width "8" frac_width "24" assert_rate on rate_source "Explicitly" period "1" output_port on has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "assert" sg_icon_stat "30,14,1,1,white,blue,0,9657e937,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 14 14 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[9.22 " "9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[7.22 7.22 9.22 9.22" " 7.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\np" "atch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('Ass" "ert');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Assert1" SID "9577" Ports [1, 1] Position [690, 153, 720, 167] BlockMirror on NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Assert" SourceType "Xilinx Assert Block" infoedit "Asserts a user-defined sample rate and/or type on a signal.

Hardware notes: In hardware th" "is block costs nothing." assert_type off type_source "Explicitly" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "16" bin_pt "14" preci_type "Single" exp_width "8" frac_width "24" assert_rate on rate_source "Explicitly" period "1" output_port on has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "assert" sg_icon_stat "30,14,1,1,white,blue,0,9657e937,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 14 14 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[9.22 " "9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[7.22 7.22 9.22 9.22" " 7.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\np" "atch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('Ass" "ert');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay2" SID "9573" Ports [1, 1] Position [560, 456, 580, 474] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "4" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "20,18,1,1,white,blue,0,d390c2d8,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 20 20 0 0 ],[0 0 18 18 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[11.22 11." "22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[9.22 9.22 11.22 11.22 9" ".22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([" "7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf(''" ",'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-4}','texm" "ode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out1" SID "9591" Ports [1, 1] Position [855, 544, 890, 556] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Q" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "9592" Ports [1, 1] Position [855, 569, 890, 581] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "En" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "9593" Ports [1, 1] Position [855, 594, 890, 606] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Reset" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "9594" Ports [1, 1] Position [855, 619, 890, 631] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "I DFF" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "9595" Ports [1, 1] Position [855, 644, 890, 656] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Q DFF" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "9596" Ports [1, 1] Position [855, 669, 890, 681] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "I Adder" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "9597" Ports [1, 1] Position [855, 694, 890, 706] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Q Adder" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "9589" Ports [1, 1] Position [855, 519, 890, 531] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "I" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Scope Name "Pilot Proc Accum" SID "9590" Ports [10] Position [1035, 508, 1075, 767] ZOrder -3 Floating off Location [-1679, 202, 1, 1206] Open off NumInputPorts "10" ZoomMode "yonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" axes9 "%" axes10 "%" } List { ListType ScopeGraphics FigureColor "[0.5 0.5 0.5]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "14000" YMin "0~-0.1~-0.1~-0.4~0~0~0~-0.2~-5~-5" YMax "80~0.1~1.1~0.4~80~1~1~0.2~5~5" SaveName "ScopeData50" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType Reference Name "Register" SID "9569" Ports [3, 1] Position [690, 347, 725, 383] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,36,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 36 36 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 36 36 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[23.55 23." "55 28.55 23.55 28.55 28.55 28.55 23.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[18.55 18.55 23.55 2" "3.55 18.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[13.55 13.55 18.55 18.55 13.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[8.55 8.55 13.55 8.55 13.55 13.55 8.55 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');por" "t_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'en');" "\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT" ": end icon text');" } Block { BlockType Reference Name "Register1" SID "9576" Ports [3, 1] Position [690, 202, 725, 238] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,36,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 36 36 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 36 36 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[23.55 23." "55 28.55 23.55 28.55 28.55 28.55 23.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[18.55 18.55 23.55 2" "3.55 18.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[13.55 13.55 18.55 18.55 13.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[8.55 8.55 13.55 8.55 13.55 13.55 8.55 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');por" "t_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'en');" "\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT" ": end icon text');" } Block { BlockType Outport Name "I Sum" SID "9570" Position [790, 213, 820, 227] IconDisplay "Port number" } Block { BlockType Outport Name "Q Sum" SID "9571" Position [790, 358, 820, 372] Port "2" IconDisplay "Port number" } Line { SrcBlock "Register" SrcPort 1 Points [25, 0] Branch { DstBlock "Q Sum" DstPort 1 } Branch { Points [0, -50] DstBlock "Assert" DstPort 1 } Branch { Points [0, 285] DstBlock "Gateway Out5" DstPort 1 } } Line { SrcBlock "AddSub1" SrcPort 1 Points [30, 0] Branch { DstBlock "Register" DstPort 1 } Branch { Points [0, 345] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "Q" SrcPort 1 Points [35, 0] Branch { DstBlock "AddSub1" DstPort 2 } Branch { Points [0, 185] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "Rst" SrcPort 1 Points [80, 0] Branch { Points [130, 0; 0, -60] Branch { DstBlock "Register" DstPort 2 } Branch { Points [0, -145] DstBlock "Register1" DstPort 2 } } Branch { Points [0, 175] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "En" SrcPort 1 Points [85, 0] Branch { DstBlock "Delay2" DstPort 1 } Branch { Points [0, 110] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "Delay2" SrcPort 1 Points [65, 0; 0, -90] Branch { DstBlock "Register" DstPort 3 } Branch { Points [0, -145] DstBlock "Register1" DstPort 3 } } Line { SrcBlock "Assert" SrcPort 1 Points [-160, 0; 0, 30] DstBlock "AddSub1" DstPort 1 } Line { SrcBlock "Register1" SrcPort 1 Points [35, 0] Branch { DstBlock "I Sum" DstPort 1 } Branch { Points [0, -60] DstBlock "Assert1" DstPort 1 } Branch { Points [0, 405] DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "AddSub2" SrcPort 1 Points [45, 0] Branch { DstBlock "Register1" DstPort 1 } Branch { Points [0, 465] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "Assert1" SrcPort 1 Points [-165, 0; 0, 40] DstBlock "AddSub2" DstPort 1 } Line { SrcBlock "I" SrcPort 1 Points [40, 0] Branch { DstBlock "AddSub2" DstPort 2 } Branch { Points [0, 305] DstBlock "Gateway Out8" DstPort 1 } } Line { Name "I" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 DstBlock "Pilot Proc Accum" DstPort 1 } Line { Name "Q" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 DstBlock "Pilot Proc Accum" DstPort 2 } Line { Name "En" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 DstBlock "Pilot Proc Accum" DstPort 3 } Line { Name "Reset" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 DstBlock "Pilot Proc Accum" DstPort 4 } Line { Name "I DFF" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 DstBlock "Pilot Proc Accum" DstPort 5 } Line { Name "Q DFF" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 DstBlock "Pilot Proc Accum" DstPort 6 } Line { Name "I Adder" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 DstBlock "Pilot Proc Accum" DstPort 7 } Line { Name "Q Adder" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 DstBlock "Pilot Proc Accum" DstPort 8 } Annotation { Name "Pilot tones must be spaced by more subcarriers\nthan latency of this adder. With natural order FFT\no" "utputs worst case is 7->21 = 14 cycles" Position [571, 121] } } } Block { BlockType SubSystem Name "Phase Calc" SID "842" Ports [4, 2] Position [830, 198, 910, 322] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Phase Calc" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "I" SID "843" Position [235, 463, 265, 477] IconDisplay "Port number" } Block { BlockType Inport Name "Q" SID "844" Position [235, 413, 265, 427] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "IQ Valid" SID "845" Position [240, 348, 270, 362] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "Reset" SID "846" Position [795, 443, 825, 457] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "CORDIC 5.0 " SID "847" Ports [3, 3] Position [480, 346, 690, 494] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/CORDIC 5.0 " SourceType "Xilinx CORDIC 5.0 Block" infoedit "CORDIC 5.0" functional_selection "Arc_Tan" architectural_configuration "Parallel" pipelining_mode "Optimal" data_format "SignedFraction" phase_format "Scaled_Radians" input_width "16" output_width "16" round_mode "Truncate" iterations "0" precision "0" compensation_scaling "No_Scale_Compensation" coarse_rotation on aclken off aresetn off out_tready off cartesian_has_tuser off cartesian_has_tlast off cartesian_tuser_width "1" phase_has_tuser off phase_has_tlast off phase_tuser_width "1" out_tlast_behv "Null" flow_control "Blocking" optimize_goal "Resources" trim_axipin_name on xl_use_area off xl_area "[0,0,0,0,0,0,0]" ip_name "CORDIC" ip_version "5.0" dsptool_ready "true" ipcore_usecache "true" ipcore_useipmodelcache "true" wrapper_available "true" port_translation_map "{ 'aclken' => 'en', 'aresetn' => 'rst' }" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "cordic_v5_0" sg_icon_stat "210,148,3,3,white,blue,0,ae31d567,right,,[2 2 2 ],[2 3 3 ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 0 4 4 ],[141 7 7 141 ],[5.466667e-001" " 5.800000e-001 6.400000e-001 ]);\npatch([206 206 210 210 ],[141 107 107 141 ],[5.466667e-001 5.800000e-001 6.400" "000e-001 ]);\npatch([206 206 210 210 ],[91 7 7 91 ],[3.233333e-001 3.400000e-001 3.700000e-001 ]);\npatch([4 205" " 205 4 4 ],[0 0 148 148 0 ],[7.700000e-001 8.200000e-001 9.100000e-001 ]);\nplot([4 205 205 4 4 ],[0 0 148 148 0" " ]);\n\n\npatch([58.275 88.62 109.62 130.62 151.62 109.62 79.275 58.275 ],[97.31 97.31 118.31 97.31 118.31 118.3" "1 118.31 97.31 ],[1 1 1 ]);\npatch([79.275 109.62 88.62 58.275 79.275 ],[76.31 76.31 97.31 97.31 76.31 ],[0.931 " "0.946 0.973 ]);\npatch([58.275 88.62 109.62 79.275 58.275 ],[55.31 55.31 76.31 76.31 55.31 ],[1 1 1 ]);\npatch([" "79.275 151.62 130.62 109.62 88.62 58.275 79.275 ],[34.31 34.31 55.31 34.31 55.31 55.31 34.31 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,' cartesian_tvalid ');\ncolor('black');port_label('input',2,' cartesian_tdata_imag ');\ncolor" "('black');port_label('input',3,' cartesian_tdata_real ');\ncolor('black');port_label('output',1,' cartesian_t" "ready ');\ncolor('black');port_label('output',2,' dout_tvalid ');\ncolor('black');port_label('output',3,' do" "ut_tdata_phase ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "848" Ports [1, 1] Position [335, 461, 365, 479] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "17" bin_pt "15" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" en off latency "1" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "30,18,1,1,white,blue,0,0c6bad53,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 18 18 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'cast');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\n ')" ";\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert3" SID "849" Ports [1, 1] Position [335, 411, 365, 429] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "17" bin_pt "15" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" en off latency "1" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "30,18,1,1,white,blue,0,0c6bad53,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 18 18 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'cast');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\n ')" ";\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay" SID "9998" Ports [1, 1] Position [940, 498, 970, 532] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "30,34,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 34 34 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 34 34 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[21.44 21.4" "4 25.44 21.44 25.44 25.44 25.44 21.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[17.44 17.44 21.44 21.44 " "17.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[13.44 13.44 17.44 17.44 13.44 ],[1 1 1 ]);\np" "atch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[9.44 9.44 13.44 9.44 13.44 13.44 9.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-" "1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay4" SID "850" Ports [1, 1] Position [385, 346, 405, 364] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "20,18,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 20 20 0 0 ],[0 0 18 18 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[11.22 11." "22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[9.22 9.22 11.22 11.22 9" ".22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([" "7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf(''" ",'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-1}','texm" "ode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out1" SID "851" Ports [1, 1] Position [825, 714, 860, 726] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Q Fix" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "852" Ports [1, 1] Position [825, 689, 860, 701] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "I Fix" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "853" Ports [1, 1] Position [825, 739, 860, 751] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Phase Valid" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "854" Ports [1, 1] Position [825, 764, 860, 776] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Phase" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "855" Ports [1, 1] Position [825, 789, 860, 801] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Reset" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "9559" Ports [1, 1] Position [825, 639, 860, 651] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "I Float" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "9560" Ports [1, 1] Position [825, 664, 860, 676] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Q Float" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "856" Ports [1, 1] Position [825, 614, 860, 626] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "IQ Valid" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Scope Name "Pilot Phase Calc" SID "857" Ports [10] Position [1005, 603, 1045, 862] ZOrder -3 Floating off Location [6, 202, 1686, 1206] Open off NumInputPorts "10" ZoomMode "yonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" axes9 "%" axes10 "%" } List { ListType ScopeGraphics FigureColor "[0.5 0.5 0.5]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "70000" YMin "0~0~-1~0~-1~0~-0.6000000000000001~0~-1~-1" YMax "1~1~0.5~1~0.5~1~0.3999999999999999~1~1~1" SaveName "ScopeData21" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType Reference Name "Register" SID "858" Ports [3, 1] Position [935, 423, 970, 477] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,54,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 54 54 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 54 54 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[32.55 32." "55 37.55 32.55 37.55 37.55 37.55 32.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[27.55 27.55 32.55 3" "2.55 27.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[22.55 22.55 27.55 27.55 22.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[17.55 17.55 22.55 17.55 22.55 22.55 17.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'e" "n');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Outport Name "phase err" SID "859" Position [1040, 443, 1070, 457] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Outport Name "valid" SID "9997" Position [1045, 508, 1075, 522] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Line { SrcBlock "Convert3" SrcPort 1 Points [55, 0] Branch { DstBlock "CORDIC 5.0 " DstPort 2 } Branch { Points [0, 300] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "Convert1" SrcPort 1 Points [45, 0] Branch { DstBlock "CORDIC 5.0 " DstPort 3 } Branch { Points [0, 225] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "CORDIC 5.0 " SrcPort 3 Points [25, 0] Branch { Points [30, 0; 0, -40] DstBlock "Register" DstPort 1 } Branch { Points [0, 300] DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "CORDIC 5.0 " SrcPort 2 Points [30, 0] Branch { Points [0, 325] DstBlock "Gateway Out3" DstPort 1 } Branch { Points [40, 0; 0, 50; 130, 0] Branch { DstBlock "Register" DstPort 3 } Branch { Points [0, 45] DstBlock "Delay" DstPort 1 } } } Line { SrcBlock "Register" SrcPort 1 DstBlock "phase err" DstPort 1 } Line { SrcBlock "Delay4" SrcPort 1 Points [25, 0] Branch { Points [30, 0] DstBlock "CORDIC 5.0 " DstPort 1 } Branch { Points [0, 265] DstBlock "Gateway Out8" DstPort 1 } } Line { SrcBlock "Q" SrcPort 1 Points [25, 0] Branch { DstBlock "Convert3" DstPort 1 } Branch { Points [0, 250] Branch { DstBlock "Gateway Out7" DstPort 1 } Branch { Labels [0, 0] Points [0, 160; 35, 0] } } } Line { SrcBlock "I" SrcPort 1 Points [40, 0] Branch { DstBlock "Convert1" DstPort 1 } Branch { Points [0, 175] Branch { DstBlock "Gateway Out6" DstPort 1 } Branch { Labels [0, 0] Points [0, 165; 20, 0] } } } Line { SrcBlock "IQ Valid" SrcPort 1 DstBlock "Delay4" DstPort 1 } Line { SrcBlock "Reset" SrcPort 1 Points [25, 0] Branch { Points [0, 60; -80, 0; 0, 285] DstBlock "Gateway Out5" DstPort 1 } Branch { DstBlock "Register" DstPort 2 } } Line { Name "IQ Valid" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 DstBlock "Pilot Phase Calc" DstPort 1 } Line { Name "Q Fix" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 DstBlock "Pilot Phase Calc" DstPort 5 } Line { Name "I Fix" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 DstBlock "Pilot Phase Calc" DstPort 4 } Line { Name "Phase Valid" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 DstBlock "Pilot Phase Calc" DstPort 6 } Line { Name "Phase" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 DstBlock "Pilot Phase Calc" DstPort 7 } Line { Name "Reset" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 DstBlock "Pilot Phase Calc" DstPort 8 } Line { Name "I Float" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 DstBlock "Pilot Phase Calc" DstPort 2 } Line { Name "Q Float" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 DstBlock "Pilot Phase Calc" DstPort 3 } Line { SrcBlock "Delay" SrcPort 1 DstBlock "valid" DstPort 1 } Annotation { Name "ARCTAN outputs scaled radians:\nOutput [-1, +1] maps to actual\nphase of [-pi, +pi]" Position [583, 304] } } } Block { BlockType Scope Name "Pilot Proc" SID "860" Ports [10] Position [1155, 528, 1195, 787] ZOrder -3 Floating off Location [6, 40, 2477, 1594] Open off NumInputPorts "10" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" axes9 "%" axes10 "%" } List { ListType ScopeGraphics FigureColor "[0.5 0.5 0.5]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "20000" YMin "0~0~0~-0.5~-1~-0.8~-0.1~-0.25~-0.4~-0.4" YMax "80~40~1~1~0~0~0.3~0~0.4~0.4" SaveName "ScopeData10" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType SubSystem Name "Pilot Selection" SID "861" Ports [3, 2] Position [300, 111, 375, 209] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Pilot Selection" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "151" Block { BlockType Inport Name "x_valid" SID "862" Position [815, 313, 840, 327] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "x_ind" SID "863" Position [365, 213, 390, 227] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "sym_ind" SID "864" Position [320, 883, 345, 897] NamePlacement "alternate" Port "3" IconDisplay "Port number" } Block { BlockType Reference Name "2LSB" SID "865" Ports [1, 1] Position [435, 878, 465, 902] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "2" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "30,24,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 24 24 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 24 24 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[15.3" "3 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[12.33 12.33 " "15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[9.33 9.33 12.33 12.33 9.33 " "],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('bl" "ack');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant1" SID "866" Ports [0, 1] Position [400, 297, 435, 323] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "21" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "6" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "8" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "35,26,0,1,white,blue,0,b02509bd,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 26 26 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 26 26 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[13.33 13." "33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[10.33 10.33 13.33 13.3" "3 10.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7." "33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n" "color('black');port_label('output',1,'21');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant2" SID "867" Ports [0, 1] Position [400, 262, 435, 288] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "7" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "6" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "8" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "35,26,0,1,white,blue,0,2a6960a5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 26 26 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 26 26 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[13.33 13." "33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[10.33 10.33 13.33 13.3" "3 10.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7." "33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n" "color('black');port_label('output',1,'7');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant3" SID "868" Ports [0, 1] Position [400, 367, 435, 393] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "64-7" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "6" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "8" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "35,26,0,1,white,blue,0,624292f4,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 26 26 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 26 26 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[13.33 13." "33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[10.33 10.33 13.33 13.3" "3 10.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7." "33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n" "color('black');port_label('output',1,'57');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant4" SID "869" Ports [0, 1] Position [400, 332, 435, 358] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "64-21" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "6" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "8" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "35,26,0,1,white,blue,0,86470e0e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 26 26 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 26 26 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[13.33 13." "33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[10.33 10.33 13.33 13.3" "3 10.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7." "33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n" "color('black');port_label('output',1,'43');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant5" SID "870" Ports [0, 1] Position [320, 797, 355, 823] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "6" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "8" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "35,26,0,1,white,blue,0,f0403ad7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 26 26 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 26 26 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[13.33 13." "33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[10.33 10.33 13.33 13.3" "3 10.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7." "33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n" "color('black');port_label('output',1,'6');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant7" SID "871" Ports [0, 1] Position [640, 532, 670, 548] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "5" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,16,0,1,white,blue,0,98872051,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 16 16 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_la" "bel('output',1,'5');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant9" SID "872" Ports [0, 1] Position [640, 577, 670, 593] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "6" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,16,0,1,white,blue,0,f0403ad7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 16 16 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_la" "bel('output',1,'6');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "873" Position [385, 763, 550, 787] ZOrder -9 ShowName off GotoTag "RX_PHY_MODE_11N_AC" TagVisibility "global" } Block { BlockType Reference Name "Logical" SID "874" Ports [3, 1] Position [1010, 313, 1050, 367] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,54,3,1,white,blue,0,98d76266,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 54 54 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 54 54 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[32.55 32." "55 37.55 32.55 37.55 37.55 37.55 32.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[27.55 27.55 32.55 3" "2.55 27.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[22.55 22.55 27.55 27.55 22.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[17.55 17.55 22.55 17.55 22.55 22.55 17.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\ncolor(" "'black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "875" Ports [4, 1] Position [725, 270, 760, 405] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "4" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[2 0 0 2 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,135,4,1,white,blue,0,4f3eee2e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 135 135 0 ],[0.77 0." "82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 135 135 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[72.55" " 72.55 77.55 72.55 77.55 77.55 77.55 72.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[67.55 67.55 72." "55 72.55 67.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[62.55 62.55 67.55 67.55 62.55 ]," "[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[57.55 57.55 62.55 57.55 62.55 62.55 57.55 ],[0.931" " 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\n\n" "color('black');disp('or');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Logical2" SID "876" Ports [2, 1] Position [755, 761, 790, 819] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,58,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 58 58 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 58 58 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[34.55 34." "55 39.55 34.55 39.55 39.55 39.55 34.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[29.55 29.55 34.55 3" "4.55 29.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[24.55 24.55 29.55 29.55 24.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[19.55 19.55 24.55 19.55 24.55 24.55 19.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('b" "lack');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical3" SID "877" Ports [2, 1] Position [800, 572, 840, 603] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,31,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 31 31 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 31 31 0 ]);\npatch([11.1 16.88 20.88 24.88 28.88 20.88 15.1 11.1 ],[19.44 19" ".44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([15.1 20.88 16.88 11.1 15.1 ],[15.44 15.44 19.44 19." "44 15.44 ],[0.931 0.946 0.973 ]);\npatch([11.1 16.88 20.88 15.1 11.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]" ");\npatch([15.1 28.88 24.88 20.88 16.88 11.1 15.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 " "]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');di" "sp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical4" SID "878" Ports [2, 1] Position [895, 566, 935, 659] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "NAND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,93,2,1,white,blue,0,68c5cabf,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 93 93 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 93 93 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[51.55 51." "55 56.55 51.55 56.55 56.55 56.55 51.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[46.55 46.55 51.55 5" "1.55 46.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[41.55 41.55 46.55 46.55 41.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[36.55 36.55 41.55 36.55 41.55 41.55 36.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('b" "lack');disp('nand');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux" SID "879" Ports [5, 1] Position [725, 878, 770, 982] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "4" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "45,104,5,1,white,blue,3,d6c79293,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 14.8571 89.1429 104 0 " "],[0.77 0.82 0.91 ]);\nplot([0 45 45 0 0 ],[0 14.8571 89.1429 104 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23." "32 14.65 8.65 ],[58.66 58.66 64.66 58.66 64.66 64.66 64.66 58.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14." "65 ],[52.66 52.66 58.66 58.66 52.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[46.66 46.66 " "52.66 52.66 46.66 ],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[40.66 40.66 46.66 40.66 46.66" " 46.66 40.66 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin ico" "n text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black" "');port_label('input',3,'d1');\ncolor('black');port_label('input',4,'d2');\ncolor('black');port_label('input',5," "'d3');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux1" SID "880" Ports [3, 1] Position [880, 756, 910, 964] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "30,208,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 29.7143 178.286 208 0 " "],[0.77 0.82 0.91 ]);\nplot([0 30 30 0 0 ],[0 29.7143 178.286 208 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.8" "8 10.1 6.1 ],[108.44 108.44 112.44 108.44 112.44 112.44 112.44 108.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 " "10.1 ],[104.44 104.44 108.44 108.44 104.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[100.44 1" "00.44 104.44 104.44 100.44 ],[1 1 1 ]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[96.44 96.44 100.44 96.4" "4 100.44 100.44 96.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: " "begin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncol" "or('black');port_label('input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: e" "nd icon text');" } Block { BlockType Reference Name "Relational1" SID "881" Ports [2, 1] Position [430, 789, 470, 816] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a>b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[2 0 0 3 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,27,2,1,white,blue,0,b5131c97,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 27 27 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 27 27 0 ]);\npatch([13.325 17.66 20.66 23.66 26.66 20.66 16.325 13.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([16.325 20.66 17.66 13.325 16.325 ],[13.33 13." "33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([13.325 17.66 20.66 16.325 13.325 ],[10.33 10.33 13.33 13.3" "3 10.33 ],[1 1 1 ]);\npatch([16.325 26.66 23.66 20.66 17.66 13.325 16.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7." "33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n" "color('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label(" "'output',1,'\\bfa > b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational3" SID "882" Ports [2, 1] Position [715, 530, 750, 565] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,35,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 35 35 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 35 35 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[22.55 22." "55 27.55 22.55 27.55 27.55 27.55 22.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[17.55 17.55 22.55 2" "2.55 17.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[12.55 12.55 17.55 17.55 12.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[7.55 7.55 12.55 7.55 12.55 12.55 7.55 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');por" "t_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa " "= b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational4" SID "883" Ports [2, 1] Position [510, 269, 550, 296] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[2 0 0 3 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,27,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 27 27 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 27 27 0 ]);\npatch([13.325 17.66 20.66 23.66 26.66 20.66 16.325 13.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([16.325 20.66 17.66 13.325 16.325 ],[13.33 13." "33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([13.325 17.66 20.66 16.325 13.325 ],[10.33 10.33 13.33 13.3" "3 10.33 ],[1 1 1 ]);\npatch([16.325 26.66 23.66 20.66 17.66 13.325 16.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7." "33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n" "color('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label(" "'output',1,'\\bfa = b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational5" SID "884" Ports [2, 1] Position [510, 304, 550, 331] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[2 0 0 3 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,27,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 27 27 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 27 27 0 ]);\npatch([13.325 17.66 20.66 23.66 26.66 20.66 16.325 13.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([16.325 20.66 17.66 13.325 16.325 ],[13.33 13." "33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([13.325 17.66 20.66 16.325 13.325 ],[10.33 10.33 13.33 13.3" "3 10.33 ],[1 1 1 ]);\npatch([16.325 26.66 23.66 20.66 17.66 13.325 16.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7." "33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n" "color('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label(" "'output',1,'\\bfa = b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational6" SID "885" Ports [2, 1] Position [510, 339, 550, 366] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[2 0 0 3 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,27,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 27 27 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 27 27 0 ]);\npatch([13.325 17.66 20.66 23.66 26.66 20.66 16.325 13.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([16.325 20.66 17.66 13.325 16.325 ],[13.33 13." "33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([13.325 17.66 20.66 16.325 13.325 ],[10.33 10.33 13.33 13.3" "3 10.33 ],[1 1 1 ]);\npatch([16.325 26.66 23.66 20.66 17.66 13.325 16.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7." "33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n" "color('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label(" "'output',1,'\\bfa = b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational7" SID "886" Ports [2, 1] Position [510, 374, 550, 401] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[2 0 0 3 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,27,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 27 27 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 27 27 0 ]);\npatch([13.325 17.66 20.66 23.66 26.66 20.66 16.325 13.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([16.325 20.66 17.66 13.325 16.325 ],[13.33 13." "33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([13.325 17.66 20.66 16.325 13.325 ],[10.33 10.33 13.33 13.3" "3 10.33 ],[1 1 1 ]);\npatch([16.325 26.66 23.66 20.66 17.66 13.325 16.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7." "33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n" "color('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label(" "'output',1,'\\bfa = b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational8" SID "887" Ports [2, 1] Position [715, 575, 750, 610] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,35,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 35 35 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 35 35 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[22.55 22." "55 27.55 22.55 27.55 27.55 27.55 22.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[17.55 17.55 22.55 2" "2.55 17.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[12.55 12.55 17.55 17.55 12.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[7.55 7.55 12.55 7.55 12.55 12.55 7.55 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');por" "t_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa " "= b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Pilot" SID "888" Position [1100, 333, 1130, 347] IconDisplay "Port number" } Block { BlockType Outport Name "Negate" SID "889" Position [975, 853, 1005, 867] Port "2" IconDisplay "Port number" } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Relational5" DstPort 1 } Line { SrcBlock "Constant2" SrcPort 1 DstBlock "Relational4" DstPort 1 } Line { SrcBlock "Relational4" SrcPort 1 Points [40, 0] Branch { DstBlock "Logical1" DstPort 1 } Branch { Points [0, 625] DstBlock "Mux" DstPort 2 } } Line { SrcBlock "Relational5" SrcPort 1 Points [10, 0] Branch { DstBlock "Logical1" DstPort 2 } Branch { Points [0, 540; 15, 0] Branch { DstBlock "Mux1" DstPort 2 } Branch { Points [0, 110] DstBlock "Mux" DstPort 5 } } } Line { SrcBlock "Relational6" SrcPort 1 Points [30, 0] Branch { DstBlock "Logical1" DstPort 3 } Branch { Points [0, 595] DstBlock "Mux" DstPort 4 } } Line { SrcBlock "Relational7" SrcPort 1 Points [35, 0] Branch { DstBlock "Logical1" DstPort 4 } Branch { Points [0, 540] DstBlock "Mux" DstPort 3 } } Line { SrcBlock "x_ind" SrcPort 1 Points [90, 0; 0, 70] Branch { DstBlock "Relational4" DstPort 2 } Branch { Points [0, 35] Branch { DstBlock "Relational5" DstPort 2 } Branch { Points [0, 35] Branch { DstBlock "Relational6" DstPort 2 } Branch { Points [0, 35] DstBlock "Relational7" DstPort 2 } } } } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Logical" DstPort 2 } Line { SrcBlock "Constant4" SrcPort 1 DstBlock "Relational6" DstPort 1 } Line { SrcBlock "Constant3" SrcPort 1 DstBlock "Relational7" DstPort 1 } Line { SrcBlock "Logical" SrcPort 1 DstBlock "Pilot" DstPort 1 } Line { SrcBlock "x_valid" SrcPort 1 DstBlock "Logical" DstPort 1 } Line { SrcBlock "2LSB" SrcPort 1 DstBlock "Mux" DstPort 1 } Line { SrcBlock "sym_ind" SrcPort 1 Points [30, 0] Branch { DstBlock "2LSB" DstPort 1 } Branch { Points [0, -95] Branch { DstBlock "Relational1" DstPort 1 } Branch { Points [0, -195; 245, 0] Branch { DstBlock "Relational8" DstPort 2 } Branch { Points [0, -45] DstBlock "Relational3" DstPort 2 } } } } Line { SrcBlock "Constant5" SrcPort 1 DstBlock "Relational1" DstPort 2 } Line { SrcBlock "Mux1" SrcPort 1 DstBlock "Negate" DstPort 1 } Line { SrcBlock "From" SrcPort 1 Points [165, 0] Branch { DstBlock "Logical2" DstPort 1 } Branch { Points [0, -140] DstBlock "Logical4" DstPort 2 } } Line { SrcBlock "Relational1" SrcPort 1 DstBlock "Logical2" DstPort 2 } Line { SrcBlock "Logical2" SrcPort 1 DstBlock "Mux1" DstPort 1 } Line { SrcBlock "Constant7" SrcPort 1 DstBlock "Relational3" DstPort 1 } Line { SrcBlock "Constant9" SrcPort 1 DstBlock "Relational8" DstPort 1 } Line { SrcBlock "Relational3" SrcPort 1 Points [30, 0] DstBlock "Logical3" DstPort 1 } Line { SrcBlock "Relational8" SrcPort 1 DstBlock "Logical3" DstPort 2 } Line { SrcBlock "Logical3" SrcPort 1 DstBlock "Logical4" DstPort 1 } Line { SrcBlock "Mux" SrcPort 1 DstBlock "Mux1" DstPort 3 } Line { SrcBlock "Logical4" SrcPort 1 Points [40, 0; 0, -255] DstBlock "Logical" DstPort 3 } Annotation { Name "All PHY modes:\n-Pilot tones in subcarriers [-21,-7,7,21]\n-Subcarriers [-7,-21] are x_ind [57,43]\n-" "One pilot per OFDM sybmol is opposite sign of other 3\n\n11a/g:\n-Opposite sign always in subcarrier 21\n\n11n/a" "c:\n-Syms 0:4: Same as a/g\n-Syms 5:6: No pilot tones in HT-STF, HT-LTF\n-Syms 7:N: Opposite sign pilot rotates " "across 4 subcarriers sequentially:\n 7: 21\n 8: 7\n 9: -21\n 10: -7\n ...\nLogic uses 2LSB of sym ind" "ex to select current negative pilot subcarrier" Position [1273, 373] HorizontalAlignment "left" } } } Block { BlockType Reference Name "Register1" SID "890" Ports [2, 1] Position [755, 679, 790, 706] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,27,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 27 27 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 27 27 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[16.33 16" ".33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[13.33 13.33 16.33" " 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[10.33 10.33 13.33 13.33 10.33 ]," "[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q'" ");\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "891" Ports [2, 1] Position [755, 704, 790, 731] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,27,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 27 27 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 27 27 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[16.33 16" ".33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[13.33 13.33 16.33" " 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[10.33 10.33 13.33 13.33 10.33 ]," "[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q'" ");\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational1" SID "892" Ports [2, 1] Position [300, 374, 340, 401] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[2 0 0 3 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,27,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 27 27 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 27 27 0 ]);\npatch([13.325 17.66 20.66 23.66 26.66 20.66 16.325 13.325 ],[16.33 16" ".33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([16.325 20.66 17.66 13.325 16.325 ],[13.33 13.33 16.33" " 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([13.325 17.66 20.66 16.325 13.325 ],[10.33 10.33 13.33 13.33 10.33 ]," "[1 1 1 ]);\npatch([16.325 26.66 23.66 20.66 17.66 13.325 16.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\b" "fa = b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational7" SID "893" Ports [2, 1] Position [300, 334, 340, 361] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[2 0 0 3 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,27,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 27 27 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 27 27 0 ]);\npatch([13.325 17.66 20.66 23.66 26.66 20.66 16.325 13.325 ],[16.33 16" ".33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([16.325 20.66 17.66 13.325 16.325 ],[13.33 13.33 16.33" " 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([13.325 17.66 20.66 16.325 13.325 ],[10.33 10.33 13.33 13.33 10.33 ]," "[1 1 1 ]);\npatch([16.325 26.66 23.66 20.66 17.66 13.325 16.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\b" "fa = b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Sym Phase Err" SID "894" Position [1025, 223, 1055, 237] IconDisplay "Port number" } Block { BlockType Outport Name "phase err valid" SID "9999" Position [1025, 283, 1055, 297] Port "2" IconDisplay "Port number" } Line { SrcBlock "Relational7" SrcPort 1 Points [250, 0] Branch { DstBlock "Count" DstPort 2 } Branch { Points [0, 245] DstBlock "Gateway Out2" DstPort 1 } Branch { Points [0, -100] DstBlock "IQ Accum" DstPort 4 } } Line { SrcBlock "Descramble" SrcPort 1 Points [70, 0] Branch { Points [0, 480] DstBlock "Register1" DstPort 1 } Branch { DstBlock "IQ Accum" DstPort 1 } } Line { SrcBlock "Descramble" SrcPort 2 Points [65, 0] Branch { Points [0, 435] DstBlock "Register2" DstPort 1 } Branch { Points [0, -55] DstBlock "IQ Accum" DstPort 2 } } Line { SrcBlock "Delay8" SrcPort 1 Points [135, 0; 0, 100] Branch { DstBlock "IQ Accum" DstPort 3 } Branch { Points [0, 95] Branch { DstBlock "Count" DstPort 1 } Branch { Points [0, 370] Branch { DstBlock "Register1" DstPort 2 } Branch { Points [0, 25] DstBlock "Register2" DstPort 2 } } } } Line { SrcBlock "Count" SrcPort 1 Points [30, 0; 0, -65] DstBlock "Phase Calc" DstPort 3 } Line { SrcBlock "Pilot Selection" SrcPort 1 DstBlock "Delay8" DstPort 1 } Line { SrcBlock "Pilot Selection" SrcPort 2 DstBlock "Descramble" DstPort 1 } Line { SrcBlock "CP_I" SrcPort 1 Points [10, 0] Branch { Points [0, 525] DstBlock "Gateway Out9" DstPort 1 } Branch { DstBlock "Descramble" DstPort 2 } } Line { SrcBlock "CP_Q" SrcPort 1 Points [5, 0] Branch { Points [0, 515] DstBlock "Gateway Out10" DstPort 1 } Branch { DstBlock "Descramble" DstPort 3 } } Line { SrcBlock "Phase Calc" SrcPort 1 Points [20, 0] Branch { DstBlock "Sym Phase Err" DstPort 1 } Branch { Points [0, 440] DstBlock "Gateway Out5" DstPort 1 } } Line { SrcBlock "sym_ind" SrcPort 1 Points [15, 0] Branch { Points [90, 0] Branch { Points [0, 90] DstBlock "Relational1" DstPort 1 } Branch { Points [0, -100] DstBlock "Pilot Selection" DstPort 3 } Branch { DstBlock "Descramble" DstPort 4 } } Branch { Points [0, 280] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "Relational1" SrcPort 1 Points [410, 0; 0, -85] DstBlock "Phase Calc" DstPort 4 } Line { SrcBlock "x_valid" SrcPort 1 DstBlock "Pilot Selection" DstPort 1 } Line { SrcBlock "x_ind" SrcPort 1 Points [25, 0] Branch { DstBlock "Pilot Selection" DstPort 2 } Branch { Points [0, 180] Branch { DstBlock "Relational7" DstPort 1 } Branch { Points [0, 205] DstBlock "Gateway Out8" DstPort 1 } } } Line { SrcBlock "Constant3" SrcPort 1 Points [10, 0] Branch { DstBlock "Relational7" DstPort 2 } Branch { Points [0, 40] DstBlock "Relational1" DstPort 2 } } Line { Name "Sc Ind" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 DstBlock "Pilot Proc" DstPort 1 } Line { Name "Accum I" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 DstBlock "Pilot Proc" DstPort 4 } Line { Name "Accum Q" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 DstBlock "Pilot Proc" DstPort 5 } Line { Name "Phase Err" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 DstBlock "Pilot Proc" DstPort 6 } Line { Name "Descram I" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 DstBlock "Pilot Proc" DstPort 7 } Line { Name "Descram Q" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 DstBlock "Pilot Proc" DstPort 8 } Line { Name "Conj Prod I" Labels [0, 0] SrcBlock "Gateway Out9" SrcPort 1 DstBlock "Pilot Proc" DstPort 9 } Line { Name "Conj Prod Q" Labels [0, 0] SrcBlock "Gateway Out10" SrcPort 1 DstBlock "Pilot Proc" DstPort 10 } Line { SrcBlock "Register1" SrcPort 1 DstBlock "Gateway Out6" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Gateway Out7" DstPort 1 } Line { Name "Sym Ind" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 DstBlock "Pilot Proc" DstPort 2 } Line { Name "Accum Resets" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 DstBlock "Pilot Proc" DstPort 3 } Line { SrcBlock "IQ Accum" SrcPort 1 Points [55, 0] Branch { DstBlock "Phase Calc" DstPort 1 } Branch { Points [0, 405] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "IQ Accum" SrcPort 2 Points [50, 0] Branch { DstBlock "Phase Calc" DstPort 2 } Branch { Points [0, 400] DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "Phase Calc" SrcPort 2 DstBlock "phase err valid" DstPort 1 } } } Block { BlockType Reference Name "Register3" SID "895" Ports [1, 1] Position [600, 410, 655, 440] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "55,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 30 30 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 30 30 0 ]);\npatch([18.1 23.88 27.88 31.88 35.88 27.88 22.1 18.1 ],[19.4" "4 19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([22.1 27.88 23.88 18.1 22.1 ],[15.44 15.44 19.4" "4 19.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([18.1 23.88 27.88 22.1 18.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1" " 1 1 ]);\npatch([22.1 35.88 31.88 27.88 23.88 18.1 22.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946" " 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode'," "'on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register4" SID "896" Ports [1, 1] Position [600, 345, 655, 375] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "55,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 30 30 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 30 30 0 ]);\npatch([18.1 23.88 27.88 31.88 35.88 27.88 22.1 18.1 ],[19.4" "4 19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([22.1 27.88 23.88 18.1 22.1 ],[15.44 15.44 19.4" "4 19.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([18.1 23.88 27.88 22.1 18.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1" " 1 1 ]);\npatch([22.1 35.88 31.88 27.88 23.88 18.1 22.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946" " 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode'," "'on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register5" SID "897" Ports [1, 1] Position [600, 270, 655, 300] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "55,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 30 30 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 30 30 0 ]);\npatch([18.1 23.88 27.88 31.88 35.88 27.88 22.1 18.1 ],[19.4" "4 19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([22.1 27.88 23.88 18.1 22.1 ],[15.44 15.44 19.4" "4 19.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([18.1 23.88 27.88 22.1 18.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1" " 1 1 ]);\npatch([22.1 35.88 31.88 27.88 23.88 18.1 22.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946" " 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode'," "'on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "a*conj(b)" SID "898" Ports [4, 2] Position [470, 326, 525, 454] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "a*conj(b)" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "139" Block { BlockType Inport Name "A_I" SID "899" Position [245, 308, 275, 322] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "A_Q" SID "900" Position [245, 373, 275, 387] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "B_I" SID "901" Position [245, 328, 275, 342] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "B_Q" SID "902" Position [245, 393, 275, 407] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub" SID "903" Ports [2, 1] Position [600, 294, 655, 421] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "4" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL off hw_selection "DSP48" pipelined off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" sg_icon_stat "55,127,2,1,white,blue,0,eeab5c4c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 127 127 0 ],[0.77 0.82 0" ".91 ]);\nplot([0 55 55 0 0 ],[0 0 127 127 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ],[70.7" "7 70.77 77.77 70.77 77.77 77.77 77.77 70.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[63.77 63.77 7" "0.77 70.77 63.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[56.77 56.77 63.77 63.77 56.7" "7 ],[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[49.77 49.77 56.77 49.77 56.77 56.77 49.77 ]" ",[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor" "('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output" "',1,'\\bf{a + b}','texmode','on');\ncolor('black');disp('z^{-4}\\newline ','texmode','on');\ncolor('black');disp('" " \\newline\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub1" SID "904" Ports [2, 1] Position [600, 454, 655, 581] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Subtraction" use_carryin off use_carryout off en off latency "4" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL off hw_selection "DSP48" pipelined off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" sg_icon_stat "55,127,2,1,white,blue,0,47390571,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 127 127 0 ],[0.77 0.82 0" ".91 ]);\nplot([0 55 55 0 0 ],[0 0 127 127 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ],[70.7" "7 70.77 77.77 70.77 77.77 77.77 77.77 70.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[63.77 63.77 7" "0.77 70.77 63.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[56.77 56.77 63.77 63.77 56.7" "7 ],[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[49.77 49.77 56.77 49.77 56.77 56.77 49.77 ]" ",[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor" "('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output" "',1,'\\bf{a - b}','texmode','on');\ncolor('black');disp('z^{-4}\\newline ','texmode','on');\ncolor('black');disp('" " \\newline\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mult1" SID "905" Ports [2, 1] Position [375, 303, 430, 347] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mult" SourceType "Xilinx Multiplier Block" infoedit "Hardware notes: To check for the optimum internal pipeline stages of the dedicated multiplier you mus" "t select 'Test for optimum pipelining'.

Optimization Goal: For implementation into device fabric (LUTs), th" "e Speed or Area optimization will take effect only if it's supported by IP for the particular device family. Other" "wise, the results will be identical regardless of the selection." precision "Full" arith_type "Signed (2's comp)" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" en off latency "2" dbl_ovrd off use_behavioral_HDL off opt "Speed" use_embedded on optimum_pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" pipeline "on" use_rpm "on" placement_style "Triangular" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mult" sg_icon_stat "55,44,2,1,white,blue,0,2fbe4d8a,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 44 44 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 55 55 0 0 ],[0 0 44 44 0 ]);\npatch([13.65 22.32 28.32 34.32 40.32 28.32 19.65 13.65 ],[28.66 28.66" " 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([19.65 28.32 22.32 13.65 19.65 ],[22.66 22.66 28.66 28.66" " 22.66 ],[0.931 0.946 0.973 ]);\npatch([13.65 22.32 28.32 19.65 13.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1 1 ])" ";\npatch([19.65 40.32 34.32 28.32 22.32 13.65 19.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0.946 0." "973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa \\tim" "es b','texmode','on');\ncolor('black');disp('z^{-2}\\newline ','texmode','on');\ncolor('black');disp(' \\n ');\nfp" "rintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mult2" SID "906" Ports [2, 1] Position [375, 368, 430, 412] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mult" SourceType "Xilinx Multiplier Block" infoedit "Hardware notes: To check for the optimum internal pipeline stages of the dedicated multiplier you mus" "t select 'Test for optimum pipelining'.

Optimization Goal: For implementation into device fabric (LUTs), th" "e Speed or Area optimization will take effect only if it's supported by IP for the particular device family. Other" "wise, the results will be identical regardless of the selection." precision "Full" arith_type "Signed (2's comp)" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" en off latency "2" dbl_ovrd off use_behavioral_HDL off opt "Speed" use_embedded on optimum_pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" pipeline "on" use_rpm "on" placement_style "Triangular" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mult" sg_icon_stat "55,44,2,1,white,blue,0,2fbe4d8a,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 44 44 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 55 55 0 0 ],[0 0 44 44 0 ]);\npatch([13.65 22.32 28.32 34.32 40.32 28.32 19.65 13.65 ],[28.66 28.66" " 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([19.65 28.32 22.32 13.65 19.65 ],[22.66 22.66 28.66 28.66" " 22.66 ],[0.931 0.946 0.973 ]);\npatch([13.65 22.32 28.32 19.65 13.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1 1 ])" ";\npatch([19.65 40.32 34.32 28.32 22.32 13.65 19.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0.946 0." "973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa \\tim" "es b','texmode','on');\ncolor('black');disp('z^{-2}\\newline ','texmode','on');\ncolor('black');disp(' \\n ');\nfp" "rintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mult3" SID "907" Ports [2, 1] Position [375, 463, 430, 507] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mult" SourceType "Xilinx Multiplier Block" infoedit "Hardware notes: To check for the optimum internal pipeline stages of the dedicated multiplier you mus" "t select 'Test for optimum pipelining'.

Optimization Goal: For implementation into device fabric (LUTs), th" "e Speed or Area optimization will take effect only if it's supported by IP for the particular device family. Other" "wise, the results will be identical regardless of the selection." precision "Full" arith_type "Signed (2's comp)" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" en off latency "2" dbl_ovrd off use_behavioral_HDL off opt "Speed" use_embedded on optimum_pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" pipeline "on" use_rpm "on" placement_style "Triangular" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mult" sg_icon_stat "55,44,2,1,white,blue,0,2fbe4d8a,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 44 44 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 55 55 0 0 ],[0 0 44 44 0 ]);\npatch([13.65 22.32 28.32 34.32 40.32 28.32 19.65 13.65 ],[28.66 28.66" " 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([19.65 28.32 22.32 13.65 19.65 ],[22.66 22.66 28.66 28.66" " 22.66 ],[0.931 0.946 0.973 ]);\npatch([13.65 22.32 28.32 19.65 13.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1 1 ])" ";\npatch([19.65 40.32 34.32 28.32 22.32 13.65 19.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0.946 0." "973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa \\tim" "es b','texmode','on');\ncolor('black');disp('z^{-2}\\newline ','texmode','on');\ncolor('black');disp(' \\n ');\nfp" "rintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mult4" SID "908" Ports [2, 1] Position [375, 528, 430, 572] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mult" SourceType "Xilinx Multiplier Block" infoedit "Hardware notes: To check for the optimum internal pipeline stages of the dedicated multiplier you mus" "t select 'Test for optimum pipelining'.

Optimization Goal: For implementation into device fabric (LUTs), th" "e Speed or Area optimization will take effect only if it's supported by IP for the particular device family. Other" "wise, the results will be identical regardless of the selection." precision "Full" arith_type "Signed (2's comp)" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" en off latency "2" dbl_ovrd off use_behavioral_HDL off opt "Speed" use_embedded on optimum_pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" pipeline "on" use_rpm "on" placement_style "Triangular" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mult" sg_icon_stat "55,44,2,1,white,blue,0,2fbe4d8a,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 44 44 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 55 55 0 0 ],[0 0 44 44 0 ]);\npatch([13.65 22.32 28.32 34.32 40.32 28.32 19.65 13.65 ],[28.66 28.66" " 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([19.65 28.32 22.32 13.65 19.65 ],[22.66 22.66 28.66 28.66" " 22.66 ],[0.931 0.946 0.973 ]);\npatch([13.65 22.32 28.32 19.65 13.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1 1 ])" ";\npatch([19.65 40.32 34.32 28.32 22.32 13.65 19.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0.946 0." "973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa \\tim" "es b','texmode','on');\ncolor('black');disp('z^{-2}\\newline ','texmode','on');\ncolor('black');disp(' \\n ');\nfp" "rintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "909" Ports [1, 1] Position [490, 375, 545, 405] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "55,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 55 55 0 0 ],[0 0 30 30 0 ]);\npatch([18.1 23.88 27.88 31.88 35.88 27.88 22.1 18.1 ],[19.44 19.44 23" ".44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([22.1 27.88 23.88 18.1 22.1 ],[15.44 15.44 19.44 19.44 15.44" " ],[0.931 0.946 0.973 ]);\npatch([18.1 23.88 27.88 22.1 18.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch(" "[22.1 35.88 31.88 27.88 23.88 18.1 22.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf" "('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMME" "NT: end icon text');" } Block { BlockType Reference Name "Register2" SID "910" Ports [1, 1] Position [490, 310, 545, 340] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "55,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 55 55 0 0 ],[0 0 30 30 0 ]);\npatch([18.1 23.88 27.88 31.88 35.88 27.88 22.1 18.1 ],[19.44 19.44 23" ".44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([22.1 27.88 23.88 18.1 22.1 ],[15.44 15.44 19.44 19.44 15.44" " ],[0.931 0.946 0.973 ]);\npatch([18.1 23.88 27.88 22.1 18.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch(" "[22.1 35.88 31.88 27.88 23.88 18.1 22.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf" "('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMME" "NT: end icon text');" } Block { BlockType Reference Name "Register3" SID "911" Ports [1, 1] Position [490, 470, 545, 500] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "55,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 55 55 0 0 ],[0 0 30 30 0 ]);\npatch([18.1 23.88 27.88 31.88 35.88 27.88 22.1 18.1 ],[19.44 19.44 23" ".44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([22.1 27.88 23.88 18.1 22.1 ],[15.44 15.44 19.44 19.44 15.44" " ],[0.931 0.946 0.973 ]);\npatch([18.1 23.88 27.88 22.1 18.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch(" "[22.1 35.88 31.88 27.88 23.88 18.1 22.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf" "('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMME" "NT: end icon text');" } Block { BlockType Reference Name "Register4" SID "912" Ports [1, 1] Position [490, 535, 545, 565] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "55,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 55 55 0 0 ],[0 0 30 30 0 ]);\npatch([18.1 23.88 27.88 31.88 35.88 27.88 22.1 18.1 ],[19.44 19.44 23" ".44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([22.1 27.88 23.88 18.1 22.1 ],[15.44 15.44 19.44 19.44 15.44" " ],[0.931 0.946 0.973 ]);\npatch([18.1 23.88 27.88 22.1 18.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch(" "[22.1 35.88 31.88 27.88 23.88 18.1 22.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf" "('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMME" "NT: end icon text');" } Block { BlockType Reference Name "Register5" SID "913" Ports [1, 1] Position [730, 345, 785, 375] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "55,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 55 55 0 0 ],[0 0 30 30 0 ]);\npatch([18.1 23.88 27.88 31.88 35.88 27.88 22.1 18.1 ],[19.44 19.44 23" ".44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([22.1 27.88 23.88 18.1 22.1 ],[15.44 15.44 19.44 19.44 15.44" " ],[0.931 0.946 0.973 ]);\npatch([18.1 23.88 27.88 22.1 18.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch(" "[22.1 35.88 31.88 27.88 23.88 18.1 22.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf" "('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMME" "NT: end icon text');" } Block { BlockType Reference Name "Register6" SID "914" Ports [1, 1] Position [730, 505, 785, 535] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "55,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 55 55 0 0 ],[0 0 30 30 0 ]);\npatch([18.1 23.88 27.88 31.88 35.88 27.88 22.1 18.1 ],[19.44 19.44 23" ".44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([22.1 27.88 23.88 18.1 22.1 ],[15.44 15.44 19.44 19.44 15.44" " ],[0.931 0.946 0.973 ]);\npatch([18.1 23.88 27.88 22.1 18.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch(" "[22.1 35.88 31.88 27.88 23.88 18.1 22.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf" "('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMME" "NT: end icon text');" } Block { BlockType Outport Name "P_I" SID "915" Position [820, 353, 850, 367] IconDisplay "Port number" } Block { BlockType Outport Name "P_Q" SID "916" Position [820, 513, 850, 527] Port "2" IconDisplay "Port number" } Line { SrcBlock "A_I" SrcPort 1 Points [5, 0] Branch { DstBlock "Mult1" DstPort 1 } Branch { Points [0, 245] DstBlock "Mult4" DstPort 2 } } Line { SrcBlock "B_I" SrcPort 1 Points [20, 0] Branch { DstBlock "Mult1" DstPort 2 } Branch { Points [0, 160] DstBlock "Mult3" DstPort 2 } } Line { SrcBlock "A_Q" SrcPort 1 Points [25, 0] Branch { DstBlock "Mult2" DstPort 1 } Branch { Points [0, 95] DstBlock "Mult3" DstPort 1 } } Line { SrcBlock "B_Q" SrcPort 1 Points [10, 0] Branch { DstBlock "Mult2" DstPort 2 } Branch { Points [0, 140] DstBlock "Mult4" DstPort 1 } } Line { SrcBlock "Mult1" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "Mult2" SrcPort 1 DstBlock "Register1" DstPort 1 } Line { SrcBlock "Mult3" SrcPort 1 DstBlock "Register3" DstPort 1 } Line { SrcBlock "Mult4" SrcPort 1 DstBlock "Register4" DstPort 1 } Line { SrcBlock "AddSub" SrcPort 1 DstBlock "Register5" DstPort 1 } Line { SrcBlock "AddSub1" SrcPort 1 DstBlock "Register6" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "AddSub" DstPort 1 } Line { SrcBlock "Register1" SrcPort 1 DstBlock "AddSub" DstPort 2 } Line { SrcBlock "Register3" SrcPort 1 DstBlock "AddSub1" DstPort 1 } Line { SrcBlock "Register4" SrcPort 1 DstBlock "AddSub1" DstPort 2 } Line { SrcBlock "Register5" SrcPort 1 DstBlock "P_I" DstPort 1 } Line { SrcBlock "Register6" SrcPort 1 DstBlock "P_Q" DstPort 1 } Annotation { Name "Implements A*conj(B)" Position [498, 252] } } } Block { BlockType Outport Name " x_I" SID "917" Position [1340, 363, 1370, 377] IconDisplay "Port number" } Block { BlockType Outport Name " x_Q" SID "918" Position [1340, 428, 1370, 442] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name " x_valid" SID "919" Position [1340, 618, 1370, 632] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "phase err" SID "920" Position [1340, 468, 1370, 482] Port "4" IconDisplay "Port number" } Block { BlockType Outport Name "phase err vld" SID "9996" Position [1340, 518, 1370, 532] Port "5" IconDisplay "Port number" } Block { BlockType Outport Name " x_ind" SID "921" Position [1340, 673, 1370, 687] Port "6" IconDisplay "Port number" } Block { BlockType Outport Name " sym ind" SID "922" Position [1340, 728, 1370, 742] Port "7" IconDisplay "Port number" } Line { SrcBlock "x_ind" SrcPort 1 DstBlock "Delay2" DstPort 1 } Line { SrcBlock "Sym ind" SrcPort 1 Points [30, 0] Branch { Points [0, -410] DstBlock "Gateway Out6" DstPort 1 } Branch { DstBlock "Delay7" DstPort 1 } } Line { SrcBlock "x_I" SrcPort 1 Points [45, 0] Branch { DstBlock "a*conj(b)" DstPort 1 } Branch { Points [0, -315] DstBlock "Gateway Out" DstPort 1 } } Line { SrcBlock "x_Q" SrcPort 1 Points [50, 0] Branch { DstBlock "a*conj(b)" DstPort 2 } Branch { Points [0, -320] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "H_I" SrcPort 1 Points [25, 0] Branch { DstBlock "a*conj(b)" DstPort 3 } Branch { Points [0, -135] DstBlock "Mag" DstPort 1 } } Line { SrcBlock "H_Q" SrcPort 1 Points [30, 0] Branch { DstBlock "a*conj(b)" DstPort 4 } Branch { Points [0, -135] DstBlock "Mag" DstPort 2 } } Line { SrcBlock "x_valid" SrcPort 1 Points [65, 0] Branch { Points [0, -420] DstBlock "Gateway Out4" DstPort 1 } Branch { DstBlock "Delay6" DstPort 1 } } Line { SrcBlock "Phase Err Calc" SrcPort 1 Points [175, 0] Branch { DstBlock "phase err" DstPort 1 } Branch { Points [0, 25] DstBlock "Goto4" DstPort 1 } } Line { SrcBlock "Delay7" SrcPort 1 Points [90, 0] Branch { DstBlock "Phase Err Calc" DstPort 5 } Branch { Points [0, 195] DstBlock "Delay17" DstPort 1 } } Line { SrcBlock "a*conj(b)" SrcPort 1 Points [45, 0] Branch { Points [0, 100] DstBlock "Phase Err Calc" DstPort 1 } Branch { DstBlock "Register4" DstPort 1 } } Line { SrcBlock "a*conj(b)" SrcPort 2 Points [30, 0] Branch { Points [0, 55] DstBlock "Phase Err Calc" DstPort 2 } Branch { DstBlock "Register3" DstPort 1 } } Line { SrcBlock "Delay2" SrcPort 1 Points [95, 0] Branch { DstBlock "Phase Err Calc" DstPort 4 } Branch { Points [0, 160] DstBlock "Delay14" DstPort 1 } } Line { SrcBlock "Mag" SrcPort 1 DstBlock "Register5" DstPort 1 } Line { SrcBlock "Divide" SrcPort 1 Points [40, 0] Branch { DstBlock "Convert" DstPort 1 } Branch { Points [0, -50] DstBlock "Convert2" DstPort 1 } } Line { SrcBlock "Divide1" SrcPort 1 Points [35, 0] Branch { DstBlock "Convert1" DstPort 1 } Branch { Points [0, -150] DstBlock "Convert4" DstPort 1 } } Line { SrcBlock "Convert" SrcPort 1 Points [35, 0] Branch { DstBlock "Delay8" DstPort 1 } Branch { Points [0, 515] DstBlock "PHY Mode Det" DstPort 1 } } Line { SrcBlock "Convert1" SrcPort 1 Points [25, 0] Branch { DstBlock "Delay10" DstPort 1 } Branch { Points [0, 470] DstBlock "PHY Mode Det" DstPort 2 } } Line { SrcBlock "Register3" SrcPort 1 DstBlock "Divide1" DstPort 1 } Line { SrcBlock "Register4" SrcPort 1 DstBlock "Divide" DstPort 1 } Line { SrcBlock "Delay12" SrcPort 1 Points [195, 0] Branch { DstBlock "Delay4" DstPort 1 } Branch { Points [0, 300] DstBlock "PHY Mode Det" DstPort 3 } } Line { SrcBlock "Delay14" SrcPort 1 DstBlock "Delay1" DstPort 1 } Line { SrcBlock "Delay17" SrcPort 1 Points [170, 0] Branch { DstBlock "Delay3" DstPort 1 } Branch { Points [0, 210] DstBlock "PHY Mode Det" DstPort 4 } } Line { SrcBlock "Delay6" SrcPort 1 Points [100, 0] Branch { DstBlock "Phase Err Calc" DstPort 3 } Branch { Points [0, 125] DstBlock "Delay12" DstPort 1 } } Line { Name "Sym Ind" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 DstBlock "EQ" DstPort 5 } Line { Name "EQ X Ind" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 DstBlock "EQ" DstPort 4 } Line { Name "X Valid" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 DstBlock "EQ" DstPort 3 } Line { Name "EQ Q" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 DstBlock "EQ" DstPort 7 } Line { Name "X_Q" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 DstBlock "EQ" DstPort 2 } Line { Name "X_I" Labels [0, 0] SrcBlock "Gateway Out" SrcPort 1 DstBlock "EQ" DstPort 1 } Line { Name "EQ I" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 DstBlock "EQ" DstPort 6 } Line { Name "EQ Valid" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 DstBlock "EQ" DstPort 8 } Line { SrcBlock "Register5" SrcPort 1 Points [30, 0; 0, 90] Branch { DstBlock "Divide" DstPort 2 } Branch { Points [0, 65] DstBlock "Divide1" DstPort 2 } } Line { SrcBlock "PHY Mode Det" SrcPort 3 DstBlock "Goto2" DstPort 1 } Line { SrcBlock "PHY Mode Det" SrcPort 2 Points [60, 0] Branch { DstBlock "Goto" DstPort 1 } Branch { Points [0, -60] DstBlock "Logical4" DstPort 2 } } Line { SrcBlock "PHY Mode Det" SrcPort 1 Points [55, 0] Branch { DstBlock "Goto1" DstPort 1 } Branch { Points [0, -50] DstBlock "Logical4" DstPort 1 } } Line { SrcBlock "Logical4" SrcPort 1 DstBlock "Goto3" DstPort 1 } Line { SrcBlock "Delay8" SrcPort 1 Points [225, 0] Branch { DstBlock " x_I" DstPort 1 } Branch { Points [0, -215] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "Delay10" SrcPort 1 Points [230, 0] Branch { DstBlock " x_Q" DstPort 1 } Branch { Points [0, -255] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "Delay4" SrcPort 1 Points [245, 0] Branch { DstBlock " x_valid" DstPort 1 } Branch { Points [0, -420] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "Delay1" SrcPort 1 Points [185, 0] Branch { DstBlock " x_ind" DstPort 1 } Branch { Points [0, -575] DstBlock "Gateway Out5" DstPort 1 } } Line { SrcBlock "Delay3" SrcPort 1 DstBlock " sym ind" DstPort 1 } Line { SrcBlock "Phase Err Calc" SrcPort 2 DstBlock "phase err vld" DstPort 1 } Line { SrcBlock "Convert2" SrcPort 1 Points [65, 0] } Line { SrcBlock "Convert4" SrcPort 1 Points [65, 0] } Annotation { Name "PHY Mode affects many subsystems - use Goto/From\ntags to avoid messy routing of these control sig" "nals" Position [1534, 985] } } } Block { BlockType SubSystem Name "Phase Tracking\n& Correction" SID "923" Ports [7, 5] Position [615, 237, 715, 443] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Phase Tracking\n& Correction" Location [61, 101, 2263, 1443] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "110" Block { BlockType Inport Name "x_I" SID "924" Position [505, 373, 535, 387] IconDisplay "Port number" } Block { BlockType Inport Name "x_Q" SID "925" Position [505, 408, 535, 422] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "x_valid" SID "926" Position [505, 443, 535, 457] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "Phase Err" SID "927" Position [505, 478, 535, 492] Port "4" IconDisplay "Port number" } Block { BlockType Inport Name "Phase Err Valid" SID "10000" Position [505, 523, 535, 537] Port "5" IconDisplay "Port number" } Block { BlockType Inport Name "x_ind " SID "928" Position [505, 573, 535, 587] Port "6" IconDisplay "Port number" } Block { BlockType Inport Name "sym_ind " SID "929" Position [505, 608, 535, 622] Port "7" IconDisplay "Port number" } Block { BlockType SubSystem Name "Bool Safe" SID "10151" Ports [1, 1] Position [920, 375, 965, 405] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Bool Safe" Location [2, 70, 2469, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" SID "10152" Position [160, 218, 190, 232] IconDisplay "Port number" } Block { BlockType Reference Name "Convert1" SID "10153" Ports [1, 1] Position [605, 231, 625, 249] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "18" bin_pt "14" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "20,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 20 20 0 0 ],[0 0 18 18 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[11.22 11.22 13." "22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[9.22 9.22 11.22 11.22 9.22 ],[0" ".931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([7.55 14.44" " 12.44 10.44 8.44 5.55 7.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: e" "nd icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cast');\nfpr" "intf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Indet Check" SID "10154" Ports [1, 1] Position [325, 210, 380, 240] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Indet Check" Location [149, 142, 2075, 1366] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "In1" SID "10155" Position [25, 53, 55, 67] IconDisplay "Port number" } Block { BlockType Reference Name "Constant" SID "10156" Ports [0, 1] Position [185, 79, 210, 101] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "18" bin_pt "14" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,400,346" block_type "constant" block_version "10.1.3" sg_icon_stat "25,22,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 22 22 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[14.33 " "14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 1 " "1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('output',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Disregard Subsystem" SID "10157" Tag "discardX" Ports [] Position [348, 257, 406, 315] ShowName off AttributesFormatString "Disregard Subsystem\\nFor Generation" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Disregard Subsystem" SourceType "Xilinx Disregard Subsystem For Generation Block" infoedit "Place this block into a subsystem to have System Generator ignore the subsystem during code gener" "ation. This block can be used in combination with the Simulation Multiplexer block to provide an alternative sim" "ulation model for another subsystem (e.g., to provide a simulation model for a black box)." has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "disregard" sg_icon_stat "58,58,-1,-1,darkgray,black,0,07734,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 58 58 0 0 ],[0 0 58 58 0 ],[0.1 0.1 0" ".1 ]);\nplot([0 58 58 0 0 ],[0 0 58 58 0 ]);\npatch([11.2 22.76 30.76 38.76 46.76 30.76 19.2 11.2 ],[37.88 37.88" " 45.88 37.88 45.88 45.88 45.88 37.88 ],[0.33 0.33 0.33 ]);\npatch([19.2 30.76 22.76 11.2 19.2 ],[29.88 29.88 37." "88 37.88 29.88 ],[0.261 0.261 0.261 ]);\npatch([11.2 22.76 30.76 19.2 11.2 ],[21.88 21.88 29.88 29.88 21.88 ],[0" ".33 0.33 0.33 ]);\npatch([19.2 46.76 38.76 30.76 22.76 11.2 19.2 ],[13.88 13.88 21.88 13.88 21.88 21.88 13.88 ]," "[0.261 0.261 0.261 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nfpri" "ntf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway In" SID "10158" Ports [1, 1] Position [165, 30, 230, 50] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to X" "ilinx fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top level" " input ports." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "16" bin_pt "14" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0.93" " 0.65 ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12.22" " 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 12." "22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1" " 1 1 ]);\npatch([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 " "0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');po" "rt_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfpri" "ntf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Indeterminate Probe" SID "10159" Ports [1, 1] Position [120, 27, 145, 53] LibraryVersion "1.2" LinkData { BlockName "Gateway Out" DialogParameters { sg_icon_stat "40,20,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 20 20 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 40 40 0 0 ],[0 0 20 20 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[12.22" " 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[10.22 10.22 12." "22 12.22 10.22 ],[0.964 0.964 0.964 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1" " 1 1 ]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.964 0.964 " "0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');po" "rt_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf" "('','COMMENT: end icon text');" } } SourceBlock "xbsIndex_r4/Indeterminate Probe" SourceType "Xilinx Indeterminate Probe Block" infoedit "Produces an output 1 of type double when input data is indeterminate. Output is 0 otherwise.
<" "br>Hardware notes: This block and any downstream blocks will be trimmed when hardware is generated." has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "indetprobe" sg_icon_stat "25,26,1,1,white,yellow,4,1c4257669fa6f259d9bb3743f2c8140f,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([25 24.7598 24.0485 22.8934 21.3388 19.4" "446 17.2835 14.9386 12.5 10.0614 7.71646 5.55537 3.66117 2.10663 0.951506 0.240184 0 0.240184 0.951506 2.10663 3" ".66117 5.55537 7.71646 10.0614 12.5 14.9386 17.2835 19.4446 21.3388 22.8934 24.0485 24.7598 25 25 ],[13 15.5362 " "17.9749 20.2224 22.1924 23.8091 25.0104 25.7502 26 25.7502 25.0104 23.8091 22.1924 20.2224 17.9749 15.5362 13 10" ".4638 8.02512 5.77759 3.80761 2.1909 0.989566 0.249791 0 0.249791 0.989566 2.1909 3.80761 5.77759 8.02512 10.463" "8 13 13 ],[0.95 0.93 0.65 ]);\nplot([25 24.7598 24.0485 22.8934 21.3388 19.4446 17.2835 14.9386 12.5 10.0614 7.7" "1646 5.55537 3.66117 2.10663 0.951506 0.240184 0 0.240184 0.951506 2.10663 3.66117 5.55537 7.71646 10.0614 12.5 " "14.9386 17.2835 19.4446 21.3388 22.8934 24.0485 24.7598 25 25 ],[13 15.5362 17.9749 20.2224 22.1924 23.8091 25.0" "104 25.7502 26 25.7502 25.0104 23.8091 22.1924 20.2224 17.9749 15.5362 13 10.4638 8.02512 5.77759 3.80761 2.1909" " 0.989566 0.249791 0 0.249791 0.989566 2.1909 3.80761 5.77759 8.02512 10.4638 13 13 ]);\npatch([5.325 9.66 12.66" " 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12." "66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.33 ],[0.985 0.979 0.895 ]);\npatch([5.325 9.66 12.66 8.325 5.3" "25 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 1" "0.33 7.33 10.33 10.33 7.33 ],[0.985 0.979 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMM" "ENT: begin icon text');\nfprintf('','COMMENT: end icon text');disp('!def');\n" } Block { BlockType Reference Name "Mux1" SID "10160" Ports [3, 1] Position [260, 27, 290, 103] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" block_version "10.1.3" sg_icon_stat "30,76,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 10.8571 65.1429 76 0 ]" ",[0.77 0.82 0.91 ]);\nplot([0 30 30 0 0 ],[0 10.8571 65.1429 76 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 " "10.1 6.1 ],[42.44 42.44 46.44 42.44 46.44 46.44 46.44 42.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[38" ".44 38.44 42.44 42.44 38.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[34.44 34.44 38.44 38.44" " 34.44 ],[1 1 1 ]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[30.44 30.44 34.44 30.44 34.44 34.44 30.44 ]" ",[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncol" "or('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label(" "'input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Out1" SID "10161" Position [370, 58, 400, 72] IconDisplay "Port number" } Line { SrcBlock "Gateway In" SrcPort 1 DstBlock "Mux1" DstPort 1 } Line { SrcBlock "Constant" SrcPort 1 DstBlock "Mux1" DstPort 3 } Line { SrcBlock "Indeterminate Probe" SrcPort 1 DstBlock "Gateway In" DstPort 1 } Line { SrcBlock "Mux1" SrcPort 1 DstBlock "Out1" DstPort 1 } Line { SrcBlock "In1" SrcPort 1 Points [15, 0] Branch { Points [90, 0; 0, 5] DstBlock "Mux1" DstPort 2 } Branch { Points [0, -20] DstBlock "Indeterminate Probe" DstPort 1 } } } } Block { BlockType Reference Name "Simulation Multiplexer" SID "10162" Ports [2, 1] Position [505, 212, 555, 263] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Simulation Multiplexer" SourceType "Xilinx Simulation Multiplexer Block" infoedit "Distinguish input subsystems as \"simulation only\" and \"generation only\". The input specified For" " Simulation will be used during Simulink simulation. The input specified For Generation will be used during code " "generation. This block will typically be used on the output of a HW Co-Simulation, Black Box, or ModelSim subsyst" "em.

Hardware Notes: This block costs nothing." sim_sel "1" hw_sel "2" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "simmux" sg_icon_stat "50,51,2,1,white,blue,0,4170dd71,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 51 51 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 50 50 0 0 ],[0 0 51 51 0 ]);\npatch([9.425 19.54 26.54 33.54 40.54 26.54 16.425 9.425 ],[32.77 32.7" "7 39.77 32.77 39.77 39.77 39.77 32.77 ],[1 1 1 ]);\npatch([16.425 26.54 19.54 9.425 16.425 ],[25.77 25.77 32.77 32" ".77 25.77 ],[0.931 0.946 0.973 ]);\npatch([9.425 19.54 26.54 16.425 9.425 ],[18.77 18.77 25.77 25.77 18.77 ],[1 1 " "1 ]);\npatch([16.425 40.54 33.54 26.54 19.54 9.425 16.425 ],[11.77 11.77 18.77 11.77 18.77 18.77 11.77 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\nfprintf('" "','COMMENT: end icon text');color('red');\nplot(swLineX,simSwLineY);\ncolor('black');\nplot(swLineX,hwSwLineY);\n" } Block { BlockType Outport Name "B" SID "10163" Position [675, 233, 705, 247] IconDisplay "Port number" } Line { SrcBlock "A" SrcPort 1 Points [15, 0] Branch { Labels [0, 0] DstBlock "Indet Check" DstPort 1 } Branch { Points [0, 25] DstBlock "Simulation Multiplexer" DstPort 2 } } Line { SrcBlock "Indet Check" SrcPort 1 DstBlock "Simulation Multiplexer" DstPort 1 } Line { SrcBlock "Simulation Multiplexer" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "B" DstPort 1 } Annotation { Name "Simulation-only block: Sets output to 0\nif input is indeterminate, which occurs at\nthe blackbox output" "s before the first reset" Position [311, 304] } } } Block { BlockType SubSystem Name "Bool Safe1" SID "10164" Ports [1, 1] Position [920, 415, 965, 445] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Bool Safe1" Location [2, 70, 2469, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" SID "10165" Position [160, 218, 190, 232] IconDisplay "Port number" } Block { BlockType Reference Name "Convert1" SID "10166" Ports [1, 1] Position [605, 231, 625, 249] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "18" bin_pt "14" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "20,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 20 20 0 0 ],[0 0 18 18 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[11.22 11.22 13." "22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[9.22 9.22 11.22 11.22 9.22 ],[0" ".931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([7.55 14.44" " 12.44 10.44 8.44 5.55 7.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: e" "nd icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cast');\nfpr" "intf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Indet Check" SID "10167" Ports [1, 1] Position [325, 210, 380, 240] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Indet Check" Location [2, 70, 2469, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "In1" SID "10168" Position [25, 53, 55, 67] IconDisplay "Port number" } Block { BlockType Reference Name "Constant" SID "10169" Ports [0, 1] Position [185, 79, 210, 101] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "18" bin_pt "14" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,400,346" block_type "constant" block_version "10.1.3" sg_icon_stat "25,22,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 22 22 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[14.33 " "14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 1 " "1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('output',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Disregard Subsystem" SID "10170" Tag "discardX" Ports [] Position [348, 257, 406, 315] ShowName off AttributesFormatString "Disregard Subsystem\\nFor Generation" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Disregard Subsystem" SourceType "Xilinx Disregard Subsystem For Generation Block" infoedit "Place this block into a subsystem to have System Generator ignore the subsystem during code gener" "ation. This block can be used in combination with the Simulation Multiplexer block to provide an alternative sim" "ulation model for another subsystem (e.g., to provide a simulation model for a black box)." has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "disregard" sg_icon_stat "58,58,-1,-1,darkgray,black,0,07734,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 58 58 0 0 ],[0 0 58 58 0 ],[0.1 0.1 0" ".1 ]);\nplot([0 58 58 0 0 ],[0 0 58 58 0 ]);\npatch([11.2 22.76 30.76 38.76 46.76 30.76 19.2 11.2 ],[37.88 37.88" " 45.88 37.88 45.88 45.88 45.88 37.88 ],[0.33 0.33 0.33 ]);\npatch([19.2 30.76 22.76 11.2 19.2 ],[29.88 29.88 37." "88 37.88 29.88 ],[0.261 0.261 0.261 ]);\npatch([11.2 22.76 30.76 19.2 11.2 ],[21.88 21.88 29.88 29.88 21.88 ],[0" ".33 0.33 0.33 ]);\npatch([19.2 46.76 38.76 30.76 22.76 11.2 19.2 ],[13.88 13.88 21.88 13.88 21.88 21.88 13.88 ]," "[0.261 0.261 0.261 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nfpri" "ntf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway In" SID "10171" Ports [1, 1] Position [165, 30, 230, 50] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to X" "ilinx fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top level" " input ports." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "16" bin_pt "14" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0.93" " 0.65 ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12.22" " 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 12." "22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1" " 1 1 ]);\npatch([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 " "0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');po" "rt_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfpri" "ntf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Indeterminate Probe" SID "10172" Ports [1, 1] Position [120, 27, 145, 53] LibraryVersion "1.2" LinkData { BlockName "Gateway Out" DialogParameters { sg_icon_stat "40,20,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0.93" " 0.65 ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12.22" " 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 12." "22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1" " 1 1 ]);\npatch([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 " "0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');po" "rt_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfpr" "intf('','COMMENT: end icon text');" } } SourceBlock "xbsIndex_r4/Indeterminate Probe" SourceType "Xilinx Indeterminate Probe Block" infoedit "Produces an output 1 of type double when input data is indeterminate. Output is 0 otherwise.
<" "br>Hardware notes: This block and any downstream blocks will be trimmed when hardware is generated." has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "indetprobe" sg_icon_stat "25,26,1,1,white,yellow,4,1c4257669fa6f259d9bb3743f2c8140f,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([25 24.7598 24.0485 22.8934 21.3388 19.4" "446 17.2835 14.9386 12.5 10.0614 7.71646 5.55537 3.66117 2.10663 0.951506 0.240184 0 0.240184 0.951506 2.10663 3" ".66117 5.55537 7.71646 10.0614 12.5 14.9386 17.2835 19.4446 21.3388 22.8934 24.0485 24.7598 25 25 ],[13 15.5362 " "17.9749 20.2224 22.1924 23.8091 25.0104 25.7502 26 25.7502 25.0104 23.8091 22.1924 20.2224 17.9749 15.5362 13 10" ".4638 8.02512 5.77759 3.80761 2.1909 0.989566 0.249791 0 0.249791 0.989566 2.1909 3.80761 5.77759 8.02512 10.463" "8 13 13 ],[0.95 0.93 0.65 ]);\nplot([25 24.7598 24.0485 22.8934 21.3388 19.4446 17.2835 14.9386 12.5 10.0614 7.7" "1646 5.55537 3.66117 2.10663 0.951506 0.240184 0 0.240184 0.951506 2.10663 3.66117 5.55537 7.71646 10.0614 12.5 " "14.9386 17.2835 19.4446 21.3388 22.8934 24.0485 24.7598 25 25 ],[13 15.5362 17.9749 20.2224 22.1924 23.8091 25.0" "104 25.7502 26 25.7502 25.0104 23.8091 22.1924 20.2224 17.9749 15.5362 13 10.4638 8.02512 5.77759 3.80761 2.1909" " 0.989566 0.249791 0 0.249791 0.989566 2.1909 3.80761 5.77759 8.02512 10.4638 13 13 ]);\npatch([5.325 9.66 12.66" " 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12." "66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.33 ],[0.985 0.979 0.895 ]);\npatch([5.325 9.66 12.66 8.325 5.3" "25 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 1" "0.33 7.33 10.33 10.33 7.33 ],[0.985 0.979 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMM" "ENT: begin icon text');\nfprintf('','COMMENT: end icon text');disp('!def');\n" } Block { BlockType Reference Name "Mux1" SID "10173" Ports [3, 1] Position [260, 27, 290, 103] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" block_version "10.1.3" sg_icon_stat "30,76,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 10.8571 65.1429 76 0 ]" ",[0.77 0.82 0.91 ]);\nplot([0 30 30 0 0 ],[0 10.8571 65.1429 76 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 " "10.1 6.1 ],[42.44 42.44 46.44 42.44 46.44 46.44 46.44 42.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[38" ".44 38.44 42.44 42.44 38.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[34.44 34.44 38.44 38.44" " 34.44 ],[1 1 1 ]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[30.44 30.44 34.44 30.44 34.44 34.44 30.44 ]" ",[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncol" "or('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label(" "'input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Out1" SID "10174" Position [370, 58, 400, 72] IconDisplay "Port number" } Line { SrcBlock "In1" SrcPort 1 Points [15, 0] Branch { Points [0, -20] DstBlock "Indeterminate Probe" DstPort 1 } Branch { Points [90, 0; 0, 5] DstBlock "Mux1" DstPort 2 } } Line { SrcBlock "Mux1" SrcPort 1 DstBlock "Out1" DstPort 1 } Line { SrcBlock "Indeterminate Probe" SrcPort 1 DstBlock "Gateway In" DstPort 1 } Line { SrcBlock "Constant" SrcPort 1 DstBlock "Mux1" DstPort 3 } Line { SrcBlock "Gateway In" SrcPort 1 DstBlock "Mux1" DstPort 1 } } } Block { BlockType Reference Name "Simulation Multiplexer" SID "10175" Ports [2, 1] Position [505, 212, 555, 263] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Simulation Multiplexer" SourceType "Xilinx Simulation Multiplexer Block" infoedit "Distinguish input subsystems as \"simulation only\" and \"generation only\". The input specified For" " Simulation will be used during Simulink simulation. The input specified For Generation will be used during code " "generation. This block will typically be used on the output of a HW Co-Simulation, Black Box, or ModelSim subsyst" "em.

Hardware Notes: This block costs nothing." sim_sel "1" hw_sel "2" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "simmux" sg_icon_stat "50,51,2,1,white,blue,0,4170dd71,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 51 51 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 50 50 0 0 ],[0 0 51 51 0 ]);\npatch([9.425 19.54 26.54 33.54 40.54 26.54 16.425 9.425 ],[32.77 32.7" "7 39.77 32.77 39.77 39.77 39.77 32.77 ],[1 1 1 ]);\npatch([16.425 26.54 19.54 9.425 16.425 ],[25.77 25.77 32.77 32" ".77 25.77 ],[0.931 0.946 0.973 ]);\npatch([9.425 19.54 26.54 16.425 9.425 ],[18.77 18.77 25.77 25.77 18.77 ],[1 1 " "1 ]);\npatch([16.425 40.54 33.54 26.54 19.54 9.425 16.425 ],[11.77 11.77 18.77 11.77 18.77 18.77 11.77 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\nfprintf('" "','COMMENT: end icon text');color('red');\nplot(swLineX,simSwLineY);\ncolor('black');\nplot(swLineX,hwSwLineY);\n" } Block { BlockType Outport Name "B" SID "10176" Position [675, 233, 705, 247] IconDisplay "Port number" } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "B" DstPort 1 } Line { SrcBlock "Simulation Multiplexer" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Indet Check" SrcPort 1 DstBlock "Simulation Multiplexer" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [15, 0] Branch { Points [0, 25] DstBlock "Simulation Multiplexer" DstPort 2 } Branch { Labels [0, 0] DstBlock "Indet Check" DstPort 1 } } Annotation { Name "Simulation-only block: Sets output to 0\nif input is indeterminate, which occurs at\nthe blackbox output" "s before the first reset" Position [311, 304] } } } Block { BlockType SubSystem Name "Phase Rotation" SID "10115" Ports [7, 5] Position [725, 367, 835, 573] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Phase Rotation" Location [2, 70, 2469, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "x_I" SID "10116" Position [370, 303, 400, 317] IconDisplay "Port number" } Block { BlockType Inport Name "x_Q" SID "10117" Position [370, 268, 400, 282] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "x_valid" SID "10118" Position [370, 233, 400, 247] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "Phase" SID "10119" Position [305, 458, 335, 472] Port "4" IconDisplay "Port number" } Block { BlockType Inport Name "Phase Valid" SID "10120" Position [305, 413, 335, 427] Port "5" IconDisplay "Port number" } Block { BlockType Inport Name "x_ind " SID "10121" Position [305, 733, 335, 747] Port "6" IconDisplay "Port number" } Block { BlockType Inport Name "sym_ind " SID "10122" Position [305, 678, 335, 692] Port "7" IconDisplay "Port number" } Block { BlockType BusCreator Name "Bus\nCreator" SID "10179" Ports [2, 1] Position [1520, 264, 1530, 291] ZOrder -2 ShowName off Inputs "2" DisplayOption "bar" Port { PortNumber 1 Name "Sin-Cos" PropagatedSignals ", " RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Complex Multiplier 5.0 " SID "10145" Ports [6, 3] Position [960, 318, 1165, 537] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Complex Multiplier 5.0 " SourceType "Xilinx Complex Multiplier 5.0 Block" hasatlast off hasatuser off atuserwidth "1" hasbtlast off hasbtuser off btuserwidth "1" multtype "Use_Mults" optimizegoal "Resources" flowcontrol "NonBlocking" outputwidth "18" roundmode "Truncate" hasctrltlast off hasctrltuser off ctrltuserwidth "1" outtlastbehv "Null" latencyconfig "Automatic" minimumlatency "37" aclken off aresetn off trim_axipin_name on aportwidth "63" bportwidth "63" ip_name "Complex Multiplier" ip_version "5.0" dsptool_ready "true" ipcore_usecache "true" ipcore_useipmodelcache "true" ipcore_verbose "false" ipcore_latency_parameter "'minimumlatency'" wrapper_available "true" port_translation_map "{ 'aclken' => 'en', 'aresetn' => 'rst'}" structural_sim "false" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "cmpy_v5_0" sg_icon_stat "205,219,6,3,white,blue,0,7e63527f,right,,[2 2 2 3 3 3 ],[4 4 4 ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 0 4 4 ],[209 115 115 209 ],[6.025000e-001" " 6.400000e-001 7.075000e-001 ]);\npatch([0 0 4 4 ],[104 10 10 104 ],[4.350000e-001 4.600000e-001 5.050000e-001 ]);" "\npatch([201 201 205 205 ],[208 6 6 208 ],[2.675000e-001 2.800000e-001 3.025000e-001 ]);\npatch([4 200 200 4 4 ],[" "0 0 219 219 0 ],[7.700000e-001 8.200000e-001 9.100000e-001 ]);\nplot([4 200 200 4 4 ],[0 0 219 219 0 ]);\n\n\npatc" "h([37.475 79.38 108.38 137.38 166.38 108.38 66.475 37.475 ],[141.19 141.19 170.19 141.19 170.19 170.19 170.19 141." "19 ],[1 1 1 ]);\npatch([66.475 108.38 79.38 37.475 66.475 ],[112.19 112.19 141.19 141.19 112.19 ],[0.931 0.946 0.9" "73 ]);\npatch([37.475 79.38 108.38 66.475 37.475 ],[83.19 83.19 112.19 112.19 83.19 ],[1 1 1 ]);\npatch([66.475 16" "6.38 137.38 108.38 79.38 37.475 66.475 ],[54.19 54.19 83.19 54.19 83.19 83.19 54.19 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' a_tvalid ');\ncolor('black');port_label('input',2,' a_tdata_imag ');\ncolor('black');port_label('input',3," "' a_tdata_real ');\ncolor('black');port_label('input',4,' b_tvalid ');\ncolor('black');port_label('input',5,' " " b_tdata_imag ');\ncolor('black');port_label('input',6,' b_tdata_real ');\ncolor('black');port_label('output',1" ",' dout_tvalid ');\ncolor('black');port_label('output',2,' dout_tdata_imag ');\ncolor('black');port_label('out" "put',3,' dout_tdata_real ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant1" SID "10125" Ports [0, 1] Position [490, 502, 510, 518] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Boolean" arith_type "Boolean" n_bits "16" bin_pt "13" preci_type "Single" exp_width "8" frac_width "24" explicit_period on period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "20,16,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 16 16 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 20 20 0 0 ],[0 0 16 16 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[10.22 10.22 12." "22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[8.22 8.22 10.22 10.22 8.22 ],[0" ".931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatch([7.55 14.44" " 12.44 10.44 8.44 5.55 7.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: e" "nd icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nfprintf(" "'','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant2" SID "10149" Ports [0, 1] Position [445, 412, 465, 428] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Boolean" arith_type "Boolean" n_bits "16" bin_pt "13" preci_type "Single" exp_width "8" frac_width "24" explicit_period on period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "20,16,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 16 16 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 20 20 0 0 ],[0 0 16 16 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[10.22 10.22 12." "22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[8.22 8.22 10.22 10.22 8.22 ],[0" ".931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatch([7.55 14.44" " 12.44 10.44 8.44 5.55 7.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: e" "nd icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nfprintf(" "'','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant3" SID "11310" Ports [0, 1] Position [655, 597, 750, 613] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "16" bin_pt "15" preci_type "Single" exp_width "8" frac_width "24" explicit_period on period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "95,16,0,1,white,blue,0,170720a6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 95 95 0 0 ],[0 0 16 16 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 95 95 0 0 ],[0 0 16 16 0 ]);\npatch([42.55 45.44 47.44 49.44 51.44 47.44 44.55 42.55 ],[10.22 10.22" " 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([44.55 47.44 45.44 42.55 44.55 ],[8.22 8.22 10.22 10.22 8" ".22 ],[0.931 0.946 0.973 ]);\npatch([42.55 45.44 47.44 44.55 42.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatch" "([44.55 51.44 49.44 47.44 45.44 42.55 44.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1" ",'0.999969482421875');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant4" SID "11311" Ports [0, 1] Position [655, 582, 750, 598] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "16" bin_pt "15" preci_type "Single" exp_width "8" frac_width "24" explicit_period on period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "95,16,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 95 95 0 0 ],[0 0 16 16 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 95 95 0 0 ],[0 0 16 16 0 ]);\npatch([42.55 45.44 47.44 49.44 51.44 47.44 44.55 42.55 ],[10.22 10.22" " 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([44.55 47.44 45.44 42.55 44.55 ],[8.22 8.22 10.22 10.22 8" ".22 ],[0.931 0.946 0.973 ]);\npatch([42.55 45.44 47.44 44.55 42.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatch" "([44.55 51.44 49.44 47.44 45.44 42.55 44.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1" ",'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert" SID "10150" Ports [1, 1] Position [395, 455, 425, 475] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "16" bin_pt "15" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "30,20,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 20 20 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[12.22 12.22" " 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[10.22 10.22 12.22 12.22" " 10.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\n" "patch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('ou" "tput',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "DDS Compiler 5.0 " SID "10127" Ports [3, 4] Position [570, 392, 800, 533] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/DDS Compiler 5.0 " SourceType "Xilinx DDS Compiler 5.0 Block" partspresent "SIN_COS_LUT_only" dds_clock_rate "100" channels "1" parameter_entry "Hardware_Parameters" spurious_free_dynamic_range "36" frequency_resolution "0.4" noise_shaping "None" phase_width "16" output_width "16" output_selection "Sine_and_Cosine" negative_sine on negative_cosine off amplitude_mode "Full_Range" memory_type "Auto" optimization_goal "Auto" dsp48_use "Minimal" latency_configuration "Auto" latency "8" has_phase_out off has_aclken off has_aresetn off explicit_period off period "1" data_has_tlast "Not_Required" has_tready on s_phase_has_tuser "Not_Required" m_data_has_tuser "Not_Required" m_phase_has_tuser "Not_Required" s_phase_tuser_width "1" s_config_sync_mode "On_Vector" phase_increment "Fixed" output_frequency1 "0" output_frequency2 "0" output_frequency3 "0" output_frequency4 "0" output_frequency5 "0" output_frequency6 "0" output_frequency7 "0" output_frequency8 "0" output_frequency9 "0" output_frequency10 "0" output_frequency11 "0" output_frequency12 "0" output_frequency13 "0" output_frequency14 "0" output_frequency15 "0" output_frequency16 "0" pinc1 "'0'" pinc2 "'0'" pinc3 "'0'" pinc4 "'0'" pinc5 "'0'" pinc6 "'0'" pinc7 "'0'" pinc8 "'0'" pinc9 "'0'" pinc10 "'0'" pinc11 "'0'" pinc12 "'0'" pinc13 "'0'" pinc14 "'0'" pinc15 "'0'" pinc16 "'0'" phase_offset "None" phase_offset_angles1 "0" phase_offset_angles2 "0" phase_offset_angles3 "0" phase_offset_angles4 "0" phase_offset_angles5 "0" phase_offset_angles6 "0" phase_offset_angles7 "0" phase_offset_angles8 "0" phase_offset_angles9 "0" phase_offset_angles10 "0" phase_offset_angles11 "0" phase_offset_angles12 "0" phase_offset_angles13 "0" phase_offset_angles14 "0" phase_offset_angles15 "0" phase_offset_angles16 "0" poff1 "'0'" poff2 "'0'" poff3 "'0'" poff4 "'0'" poff5 "'0'" poff6 "'0'" poff7 "'0'" poff8 "'0'" poff9 "'0'" poff10 "'0'" poff11 "'0'" poff12 "'0'" poff13 "'0'" poff14 "'0'" poff15 "'0'" poff16 "'0'" trim_axipin_name on por_mode "false" gui_behaviour "Sysgen" ip_name "DDS Compiler" ip_version "5.0" dsptool_ready "true" wrapper_available "true" port_translation_map "{ 'aclken' => 'en', 'aresetn' => 'rst' }" ipcore_xco_need_fpga_part "true" ipcore_fpga_part "xlipgetpartsetting(gcb, {'virtex6', 'xc6vlx75t', '-3', 'ff784'})" ipcore_usecache "true" ipcore_useipmodelcache "true" ipcore_verbose "false" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "dds_compiler_v5_0" sg_icon_stat "230,141,3,4,white,blue,0,b4465e70,right,,[2 2 3 ],[2 3 3 3 ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 0 4 4 ],[129 52 52 129 ],[5.466667e-001 5" ".800000e-001 6.400000e-001 ]);\npatch([0 0 4 4 ],[39 7 7 39 ],[3.233333e-001 3.400000e-001 3.700000e-001 ]);\npatc" "h([226 226 230 230 ],[135 111 111 135 ],[5.466667e-001 5.800000e-001 6.400000e-001 ]);\npatch([226 226 230 230 ],[" "100 6 6 100 ],[3.233333e-001 3.400000e-001 3.700000e-001 ]);\npatch([4 225 225 4 4 ],[0 0 141 141 0 ],[7.700000e-0" "01 8.200000e-001 9.100000e-001 ]);\nplot([4 225 225 4 4 ],[0 0 141 141 0 ]);\n\n\npatch([70.5 99.4 119.4 139.4 159" ".4 119.4 90.5 70.5 ],[92.2 92.2 112.2 92.2 112.2 112.2 112.2 92.2 ],[1 1 1 ]);\npatch([90.5 119.4 99.4 70.5 90.5 ]" ",[72.2 72.2 92.2 92.2 72.2 ],[0.931 0.946 0.973 ]);\npatch([70.5 99.4 119.4 90.5 70.5 ],[52.2 52.2 72.2 72.2 52.2 " "],[1 1 1 ]);\npatch([90.5 159.4 139.4 119.4 99.4 70.5 90.5 ],[32.2 32.2 52.2 32.2 52.2 52.2 32.2 ],[0.931 0.946 0." "973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,' phase_tvalid ');\ncolor('black');port_label('input',2,' phase_tdata_phase_in ');\ncolor('blac" "k');port_label('input',3,' data_tready ');\ncolor('black');port_label('output',1,' phase_tready ');\ncolor('bl" "ack');port_label('output',2,' data_tvalid ');\ncolor('black');port_label('output',3,' data_tdata_sine ');\ncol" "or('black');port_label('output',4,' data_tdata_cosine ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay1" SID "10128" Ports [1, 1] Position [1045, 728, 1080, 752] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "6" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,24,1,1,white,blue,0,aa5bc30d,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[15.33 15" ".33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.33 12.33 15.33" " 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 " "1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');" "disp('z^{-6}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay18" SID "10129" Ports [1, 1] Position [1045, 673, 1080, 697] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "6" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,24,1,1,white,blue,0,aa5bc30d,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[15.33 15" ".33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.33 12.33 15.33" " 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 " "1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');" "disp('z^{-6}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay2" SID "10182" Ports [1, 1] Position [670, 673, 705, 697] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "12" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,24,1,1,white,blue,0,aa753640,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[15.33 15" ".33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.33 12.33 15.33" " 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 " "1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');" "disp('z^{-12}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay3" SID "10183" Ports [1, 1] Position [670, 728, 705, 752] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "12" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,24,1,1,white,blue,0,aa753640,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[15.33 15" ".33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.33 12.33 15.33" " 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 " "1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');" "disp('z^{-12}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay4" SID "10184" Ports [1, 1] Position [660, 298, 695, 322] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "12" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,24,1,1,white,blue,0,aa753640,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[15.33 15" ".33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.33 12.33 15.33" " 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 " "1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');" "disp('z^{-12}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay5" SID "10185" Ports [1, 1] Position [660, 263, 695, 287] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "12" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,24,1,1,white,blue,0,aa753640,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[15.33 15" ".33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.33 12.33 15.33" " 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 " "1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');" "disp('z^{-12}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay6" SID "10186" Ports [1, 1] Position [660, 223, 695, 247] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "12" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,24,1,1,white,blue,0,aa753640,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[15.33 15" ".33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.33 12.33 15.33" " 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 " "1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');" "disp('z^{-12}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out1" SID "10146" Ports [1, 1] Position [1465, 144, 1500, 156] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Phase valid" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out10" SID "10130" Ports [1, 1] Position [1465, 244, 1500, 256] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Q Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out11" SID "10131" Ports [1, 1] Position [1465, 119, 1500, 131] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "X_Q" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out12" SID "10132" Ports [1, 1] Position [1465, 169, 1500, 181] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Phase" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out13" SID "10133" Ports [1, 1] Position [1465, 194, 1500, 206] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Valid Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "10148" Ports [1, 1] Position [1465, 294, 1500, 306] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Sin-Cos Valid" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "10180" Ports [1, 1] Position [1465, 264, 1500, 276] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "Gateway Out5" SID "10134" Ports [1, 1] Position [1465, 69, 1500, 81] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "X_IQ Valid" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "10181" Ports [1, 1] Position [1465, 279, 1500, 291] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "Gateway Out8" SID "10135" Ports [1, 1] Position [1465, 94, 1500, 106] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "X_I" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out9" SID "10136" Ports [1, 1] Position [1465, 219, 1500, 231] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "I Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Scope Name "Phase Correct" SID "10138" Ports [10] Position [1680, 53, 1720, 322] ZOrder -3 Floating off Location [1, 45, 1836, 1199] Open off NumInputPorts "10" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" axes9 "%" axes10 "%" } List { ListType ScopeGraphics FigureColor "[0.5 0.5 0.5]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "50000" YMin "0~-2~-2~0~-0.8~0~-2~-3~-1~0" YMax "1~2~2~2~0~1~3~2~1~1" SaveName "ScopeData14" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType Outport Name " x_I" SID "10139" Position [1240, 493, 1270, 507] IconDisplay "Port number" } Block { BlockType Outport Name " x_Q" SID "10140" Position [1240, 423, 1270, 437] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name " x_valid" SID "10141" Position [1240, 348, 1270, 362] NamePlacement "alternate" Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "x_ind" SID "10142" Position [1195, 733, 1225, 747] Port "4" IconDisplay "Port number" } Block { BlockType Outport Name " sym ind" SID "10143" Position [1195, 678, 1225, 692] Port "5" IconDisplay "Port number" } Line { Name "Phase" Labels [0, 0] SrcBlock "Gateway Out12" SrcPort 1 DstBlock "Phase Correct" DstPort 5 } Line { Name "X_Q" Labels [0, 0] SrcBlock "Gateway Out11" SrcPort 1 DstBlock "Phase Correct" DstPort 3 } Line { Name "I Out" Labels [0, 0] SrcBlock "Gateway Out9" SrcPort 1 DstBlock "Phase Correct" DstPort 7 } Line { Name "X_I" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 DstBlock "Phase Correct" DstPort 2 } Line { Name "X_IQ Valid" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 DstBlock "Phase Correct" DstPort 1 } Line { Name "Valid Out" Labels [0, 0] SrcBlock "Gateway Out13" SrcPort 1 DstBlock "Phase Correct" DstPort 6 } Line { Name "Q Out" Labels [0, 0] SrcBlock "Gateway Out10" SrcPort 1 DstBlock "Phase Correct" DstPort 8 } Line { SrcBlock "Delay1" SrcPort 1 DstBlock "x_ind" DstPort 1 } Line { SrcBlock "Delay18" SrcPort 1 DstBlock " sym ind" DstPort 1 } Line { SrcBlock "Phase" SrcPort 1 DstBlock "Convert" DstPort 1 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "DDS Compiler 5.0 " DstPort 3 } Line { SrcBlock "Constant2" SrcPort 1 Points [45, 0] Branch { DstBlock "DDS Compiler 5.0 " DstPort 1 } Branch { Points [0, -270] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "x_valid" SrcPort 1 Points [0, -5] DstBlock "Delay6" DstPort 1 } Line { SrcBlock "x_Q" SrcPort 1 DstBlock "Delay5" DstPort 1 } Line { SrcBlock "x_I" SrcPort 1 DstBlock "Delay4" DstPort 1 } Line { SrcBlock "DDS Compiler 5.0 " SrcPort 2 Points [55, 0] Branch { DstBlock "Complex Multiplier 5.0 " DstPort 4 } Branch { Points [0, 140; 580, 0; 0, -285] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "DDS Compiler 5.0 " SrcPort 3 Points [60, 0] Branch { Points [0, 100; 510, 0; 0, -295] DstBlock "Gateway Out6" DstPort 1 } Branch { DstBlock "Complex Multiplier 5.0 " DstPort 5 } } Line { SrcBlock "DDS Compiler 5.0 " SrcPort 4 Points [65, 0] Branch { Points [0, 60; 500, 0; 0, -305] DstBlock "Gateway Out4" DstPort 1 } Branch { DstBlock "Complex Multiplier 5.0 " DstPort 6 } } Line { SrcBlock "Complex Multiplier 5.0 " SrcPort 1 Points [40, 0] Branch { DstBlock " x_valid" DstPort 1 } Branch { Points [0, -160] DstBlock "Gateway Out13" DstPort 1 } } Line { SrcBlock "Complex Multiplier 5.0 " SrcPort 2 Points [45, 0] Branch { DstBlock " x_Q" DstPort 1 } Branch { Points [0, -180] DstBlock "Gateway Out10" DstPort 1 } } Line { SrcBlock "Complex Multiplier 5.0 " SrcPort 3 Points [50, 0] Branch { DstBlock " x_I" DstPort 1 } Branch { Points [0, -275] DstBlock "Gateway Out9" DstPort 1 } } Line { SrcBlock "sym_ind " SrcPort 1 DstBlock "Delay2" DstPort 1 } Line { SrcBlock "x_ind " SrcPort 1 DstBlock "Delay3" DstPort 1 } Line { Name "Phase valid" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 DstBlock "Phase Correct" DstPort 4 } Line { Name "Sin-Cos" Labels [0, 0] SrcBlock "Bus\nCreator" SrcPort 1 DstBlock "Phase Correct" DstPort 9 } Line { Name "Sin-Cos Valid" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 DstBlock "Phase Correct" DstPort 10 } Line { SrcBlock "Convert" SrcPort 1 Points [95, 0] Branch { DstBlock "DDS Compiler 5.0 " DstPort 2 } Branch { Points [0, -290] DstBlock "Gateway Out12" DstPort 1 } } Line { SrcBlock "Gateway Out4" SrcPort 1 DstBlock "Bus\nCreator" DstPort 1 } Line { SrcBlock "Gateway Out6" SrcPort 1 DstBlock "Bus\nCreator" DstPort 2 } Line { SrcBlock "Delay2" SrcPort 1 DstBlock "Delay18" DstPort 1 } Line { SrcBlock "Delay3" SrcPort 1 DstBlock "Delay1" DstPort 1 } Line { SrcBlock "Delay4" SrcPort 1 Points [135, 0] Branch { Points [0, 100] DstBlock "Complex Multiplier 5.0 " DstPort 3 } Branch { Points [0, -210] DstBlock "Gateway Out8" DstPort 1 } } Line { SrcBlock "Delay5" SrcPort 1 Points [165, 0] Branch { Points [0, 100] DstBlock "Complex Multiplier 5.0 " DstPort 2 } Branch { Points [0, -150] DstBlock "Gateway Out11" DstPort 1 } } Line { SrcBlock "Delay6" SrcPort 1 Points [195, 0] Branch { Points [0, 105] DstBlock "Complex Multiplier 5.0 " DstPort 1 } Branch { Points [0, -160] DstBlock "Gateway Out5" DstPort 1 } } Annotation { Name "Upstream logic pulses Phase Valid for 1 cycle each\ntime the Phase value is updated. However the DDS\non" "ly outputs valid sin/cos values when the phase_tvalid\nsignal is asserted. Since the complex mult will use the\nI/" "Q tvalid signal to qualify the output tvalid, we can\nsafely leave the DDS phase_tvalid input asserted all the tim" "e." Position [296, 590] HorizontalAlignment "left" } } } Block { BlockType Outport Name " x_I" SID "945" Position [1035, 383, 1065, 397] IconDisplay "Port number" } Block { BlockType Outport Name " x_Q" SID "946" Position [1035, 423, 1065, 437] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name " x_valid" SID "947" Position [1035, 463, 1065, 477] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "x_ind" SID "948" Position [1035, 503, 1065, 517] Port "4" IconDisplay "Port number" } Block { BlockType Outport Name " sym ind" SID "949" Position [1035, 543, 1065, 557] Port "5" IconDisplay "Port number" } Line { SrcBlock "x_I" SrcPort 1 DstBlock "Phase Rotation" DstPort 1 } Line { SrcBlock "x_Q" SrcPort 1 Points [25, 0; 0, -5] DstBlock "Phase Rotation" DstPort 2 } Line { SrcBlock "x_valid" SrcPort 1 Points [30, 0; 0, -10] DstBlock "Phase Rotation" DstPort 3 } Line { SrcBlock "Phase Err" SrcPort 1 Points [35, 0; 0, -15] DstBlock "Phase Rotation" DstPort 4 } Line { SrcBlock "Phase Err Valid" SrcPort 1 Points [40, 0; 0, -30] DstBlock "Phase Rotation" DstPort 5 } Line { SrcBlock "x_ind " SrcPort 1 Points [45, 0; 0, -50] DstBlock "Phase Rotation" DstPort 6 } Line { SrcBlock "sym_ind " SrcPort 1 Points [50, 0; 0, -55] DstBlock "Phase Rotation" DstPort 7 } Line { SrcBlock "Phase Rotation" SrcPort 1 DstBlock "Bool Safe" DstPort 1 } Line { SrcBlock "Phase Rotation" SrcPort 2 DstBlock "Bool Safe1" DstPort 1 } Line { SrcBlock "Phase Rotation" SrcPort 3 DstBlock " x_valid" DstPort 1 } Line { SrcBlock "Phase Rotation" SrcPort 4 DstBlock "x_ind" DstPort 1 } Line { SrcBlock "Phase Rotation" SrcPort 5 DstBlock " sym ind" DstPort 1 } Line { SrcBlock "Bool Safe" SrcPort 1 DstBlock " x_I" DstPort 1 } Line { SrcBlock "Bool Safe1" SrcPort 1 DstBlock " x_Q" DstPort 1 } } } Block { BlockType Outport Name "Eq I" SID "950" Position [900, 253, 930, 267] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Outport Name "Eq Q" SID "951" Position [900, 293, 930, 307] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "iq_valid" SID "952" Position [900, 333, 930, 347] NamePlacement "alternate" Port "3" IconDisplay "Port number" } Block { BlockType Outport Name " sc_ind" SID "953" Position [900, 373, 930, 387] NamePlacement "alternate" Port "4" IconDisplay "Port number" } Block { BlockType Outport Name " sym_ind" SID "954" Position [900, 413, 930, 427] NamePlacement "alternate" Port "5" IconDisplay "Port number" } Line { SrcBlock "Chan Est" SrcPort 3 DstBlock "Equalizer,\nPilot Processing\n& PHY Mode Det" DstPort 3 } Line { SrcBlock "Chan Est" SrcPort 4 DstBlock "Equalizer,\nPilot Processing\n& PHY Mode Det" DstPort 4 } Line { SrcBlock "Chan Est" SrcPort 5 DstBlock "Equalizer,\nPilot Processing\n& PHY Mode Det" DstPort 5 } Line { SrcBlock "Chan Est" SrcPort 6 DstBlock "Equalizer,\nPilot Processing\n& PHY Mode Det" DstPort 6 } Line { SrcBlock "Chan Est" SrcPort 7 DstBlock "Equalizer,\nPilot Processing\n& PHY Mode Det" DstPort 7 } Line { SrcBlock "Chan Est" SrcPort 1 DstBlock "Equalizer,\nPilot Processing\n& PHY Mode Det" DstPort 1 } Line { SrcBlock "Chan Est" SrcPort 2 DstBlock "Equalizer,\nPilot Processing\n& PHY Mode Det" DstPort 2 } Line { SrcBlock "Rx I" SrcPort 1 DstBlock "Chan Est" DstPort 1 } Line { SrcBlock "Rx Q" SrcPort 1 DstBlock "Chan Est" DstPort 2 } Line { SrcBlock "sc_ind" SrcPort 1 DstBlock "Chan Est" DstPort 3 } Line { SrcBlock "iq_valid " SrcPort 1 DstBlock "Chan Est" DstPort 4 } Line { SrcBlock "sym_ind" SrcPort 1 DstBlock "Chan Est" DstPort 5 } Line { SrcBlock "Equalizer,\nPilot Processing\n& PHY Mode Det" SrcPort 1 DstBlock "Phase Tracking\n& Correction" DstPort 1 } Line { SrcBlock "Equalizer,\nPilot Processing\n& PHY Mode Det" SrcPort 2 DstBlock "Phase Tracking\n& Correction" DstPort 2 } Line { SrcBlock "Equalizer,\nPilot Processing\n& PHY Mode Det" SrcPort 3 DstBlock "Phase Tracking\n& Correction" DstPort 3 } Line { SrcBlock "Equalizer,\nPilot Processing\n& PHY Mode Det" SrcPort 4 DstBlock "Phase Tracking\n& Correction" DstPort 4 } Line { SrcBlock "Phase Tracking\n& Correction" SrcPort 1 Points [40, 0] Branch { Points [0, 230] DstBlock "Debug Outputs" DstPort 1 } Branch { DstBlock "Eq I" DstPort 1 } } Line { SrcBlock "Phase Tracking\n& Correction" SrcPort 2 Points [35, 0] Branch { Points [0, 205] DstBlock "Debug Outputs" DstPort 2 } Branch { DstBlock "Eq Q" DstPort 1 } } Line { SrcBlock "Phase Tracking\n& Correction" SrcPort 3 Points [30, 0] Branch { Points [0, 180] DstBlock "Debug Outputs" DstPort 3 } Branch { DstBlock "iq_valid" DstPort 1 } } Line { SrcBlock "Equalizer,\nPilot Processing\n& PHY Mode Det" SrcPort 6 DstBlock "Phase Tracking\n& Correction" DstPort 6 } Line { SrcBlock "Equalizer,\nPilot Processing\n& PHY Mode Det" SrcPort 7 DstBlock "Phase Tracking\n& Correction" DstPort 7 } Line { SrcBlock "Phase Tracking\n& Correction" SrcPort 4 Points [25, 0] Branch { Points [0, 155] DstBlock "Debug Outputs" DstPort 4 } Branch { DstBlock " sc_ind" DstPort 1 } } Line { SrcBlock "Phase Tracking\n& Correction" SrcPort 5 DstBlock " sym_ind" DstPort 1 } Line { SrcBlock "Equalizer,\nPilot Processing\n& PHY Mode Det" SrcPort 5 DstBlock "Phase Tracking\n& Correction" DstPort 5 } } } Block { BlockType SubSystem Name "Changelog" SID "955" Ports [] Position [843, 286, 887, 333] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Changelog" Location [161, 165, 1904, 1332] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "75" Annotation { Name "2.00.b:\nSame as 2.00.a but with ILA removed (for MAC debug)\n\n2.00.c:\nSame as 2.00.b but with ILA re-e" "nabled\n\n2.00.d:\n-Reworked auto-corr pkt det data types to avoid overflow and allow thresholds\n to cover full r" "ange of mag/corr values observed in hw\n\n2.00.e:\nSame as 2.00.d but with ILA removed\n\n2.00.f:\n-Re-designed CFO" " est to take phase of average of conj mults (should be better \n performance at low SNR)\n\n2.00.g:\n-Added CFG bi" "t to bypass CFO est\n-Re-enabled ILA\n\n2.00.h:\n-Fixed zero_tail and num_bytes bug that flagged 2/3 of pkt lens ba" "d\n\n2.00.i:\n-Fixed rx_end timing bug that asserted end before FCS for some lengths\n-Redesigned DSSS and OFDM pkt" " buf and pkt done logic\n-Added DSSS bytes to FCS check\n-Removed pkt done state - now handled by MAC\n-Added DSSS " "length to SIGNAL register\n\n2.00.j:\n-Removed SIGNAL register (now handed by MAC)\n-Fixed DSSS/FCS bug (VIN was hi" "gh 8 cycles per byte)\n\n2.00.k:\n-Fixed rx_start rate/length output timing for OFDM rx\n-Bypassed OFDM descrabler " "for SIGNAL field bytes (raw SIGNAL now \n written to pkt buf)\n\n2.00.l:\n-Added 64-bit pkt buf interface option " "(32b is disregarded subsystem in this export)\n-Added pkt buf addr offset, common to all pkt bufs, so MAC can store" " per-pkt metadata\n\n2.00.m:\n-Re-designed all post-EQ logic (demod, de-interleave, decode) to support other mod sc" "hemes\n-Re-defined FEC_Config register; now only stores scaling values\n\n2.00.n:\n-Added pipeline regs at decoder " "input to resolve timing errors\n\n2.00.o:\n-Re-enabled CRC checking in DSSS headers, extended max length of DSSS pk" "ts (now 1500 bytes, not bits)\n\n2.00.p:\n-Removed protection DFF's between pkt buf sel regs and bram addr gen; it'" "s now software's job to be safe\n-Bit-order-swapped the RATE output to MAC\n\n2.00.q:\n-Fixed interpretation of RAT" "E values in m-code block to match new bit-un-reversed values\n\n2.00.r:\n-Fixed SIGNAL init values (wasn't a proble" "m, just inconsistent)\n-Robustified byte counter and byte_valid at decoder to stop after num bytes, even if decoder" " outputs extra bytes\n-Added OFDM_Running -> DSSS_Reset control\n\n2.00.s:\n-chunter export\n\n2.00.t:\n-Nuked Sysg" "en caches, re-exported\n\n2.00.u:\n-Bypassed de-scrambler for SIGNAL bytes (now SIGNAL is written to pkt buf for us" "e in software)\n\n2.00.v:\n-Tweaked reset logic for de-interleave addr gen (still chasing problem of corruption in " "Rx bytes at end\n of pkts > 105 bytes at Q34 in hardware, but not in sim...)\n\n2.00.w:\n-Moved CS.RSSI to post R" "SSI sum\n-Registered LEN/RATE on valid SIGNAL, reset to sane defaults every pkt\n-Robustified fake Rx busy logic (c" "an't start outside pkt det, stops running when done)\n\n2.00.x:\n-Fixed bug in SIGNAL invalid checking\n-Added SIGN" "AL value to register\n\n2.00.y:\n-Added more FFT/decoder ctrl signals to ChipScope\n\n2.00.z:\n-Added even more dem" "od/deint signals to CS ILA" Position [53, 687] HorizontalAlignment "left" BackgroundColor "[0.898039, 0.898039, 0.898039]" } Annotation { Position [565, 615] } Annotation { Name "2.02.a:\n-Disabled aresetn port on de-int sym FIFO\n\n2.02.b:\n-More CS signals\n\n2.02.c:\n-Yet more CS " "signals\n\n2.02.d:\n-Reworked RSSI det reset logic (posedge -> SR latch, simpler reset)\n-Reworked DSSS reset logic" " (now has 128 cycle reset pulse every time)\n-Reworked DSSS RX_END indication; every DSSS RX_START will lead to \n " " RX_END, even intra-Rx reset events (FCS will be bad, but RX_ED will occur)\n\n2.02.e:\n-Teweaked rx_ended_unexpect" "edly logic to require pkt_det = 1, to avoid sending\n rx_end.error if MAC blocks Rx post-good-fcs, pre-last-extend" "ed-samp\n-Added MAC rx_start/fcs/end to CS ILA\n\n2.02.f:\nRe-export, no modifications; trying to debug per-build b" "ad states\n\n2.02.g:\n-Re-added RSSI to CS ILA to debug pkt det issues\n\n2.02.h:\n-Changed pkt det reset extension" " to be negedge(pkt det reset), so every reset event\n (whether 1 or thousands of cycles) gets extended from its en" "d, not its beginning\n-Routed debug[0] to CS ILA trigger port, so sw can trigger CS\n\n2.02.i:\n-Added Rx_Sigs_Inva" "lid input from Tx PHY to block ADC/RSSI inputs during TxEn\n (only honored when USE_ bit is set in config register" ")\n-Added LTS and Rx_Sigs_Invalid sigs to CS ILA\n\n2.02.j:\n-Reworked pre-FFT samp buf control to handle cases of " "late pkt det (this was the\n cause of Rx deadlock, when post-Tx Rx events happened too soon)\n\n2.02.k:\n-Added Rx" " ctrl sigs back to ILA, to debug occasional long pkt det events in hardware\n (they look like perma-dets, but the " "Rx PHY somehow recovers)\n\n2.02.l:\n-Made decoder nrst synchronous throughout (chasing possible bug in SIGNAL pari" "ty\n error before last SIGNAL byte is written...it's a long shot)\n\n2.02.m:\n-Added 16-QAM support\n\n2.02.n:\n-A" "dded more robust FFT reset logic to handle case of mid-FFT RX_END event\n\n2.02.o:\n-Redesigned pilot phase error e" "st and correction (pilots now correct same symbol)\n-Fixed bugs in LTS correlator (lower thresholds!)\n-Added high/" "SNR thresholds for LTS corr (new register!)\n-Merged pilot phase error calc and EQ to avoid having two conj mults\n" "-Added dbg_SIGNAL_ERR_DISP gw out\n\n2.02.p:\n-Disabled aresetn on pre-FFT sample FIFO (trying to resolve sim/hw mi" "smatch for\n 16Q Rx errors with certain payload lengths)\n\n2.02.q:\n-Added DFF in phase error calc to resolve tim" "ing issues\n\n2.02.r:\n-Added more latency in phase error accumulators for timing (2.00.p and q missed timing\n by" " 6+ nsec)\n-Switched FP add/subs to use DSP48\n\n2.02.s, t:\n-Yet more latency in FP cores\n\n2.02.u:\n-Redesigned " "deinterleaver for lower latency\n-Added 64QAM support\n\n2.02.v,w,x:\n-Updated CS sigs to debug always-bad-SIGNAL i" "n hw\n\n2.02.y:\n-Registered output of SIGNAL rate decode, trying to fix unsimulatable behavior in sym FIFO\n\n2.02" ".z:\n-Tweaked BPSK demap to resolve (I hope) hw/sim mismatch\n\n2.03.a:\n-Increased sym fifo depth to 128 (grasping" " here...)\n\n2.03.b,c:\n-Added more de-int sigs to ILA\n\n2.03.d:\n-Added explicit reset to demappers - should help" " resolve all-bad-after-one-bad behavior in hw" Position [63, 1887] HorizontalAlignment "left" BackgroundColor "[0.898039, 0.898039, 0.898039]" } Annotation { Name "2.03.e:\n-Re-designed de-interleaver control to fix rate=2/3 bug\n\n2.03.f:\n-Modified decoder blackbox\n" " -Changed default traceback to 48 (K*7 - 1)\n -Added early_trace ctrl signal to start early 24 bit traceback for " "SIGNAL\n-Redesigned decoder control to stop vin after last symbol and trigger pkt_end\n (reduces latency to last i" "nput -> last output, required to meet SIFS at 64Q)\n\n2.03.g:\n-Added logic to store chan estimates per Rx event\n-" "Removed unused 32-bit pktBuf interface\n\n2.03.h:\n-Updated H est offset to be byte value (matching rx_header offse" "t)\n-Added bit to en/disable u32 order swap for H Est writing\n-Added selection diversity\n -Auto-select Rx ant ba" "sed on AGC gains\n -Dual pkt det subsystems\n-Split registers for post-AGC gains and RSSI, to capture RF A and B\n" "-Added FIFO to buffer/downsample EQ I/Q debug outputs for 40MS DAC outputs\n\n2.03.i:\n-Added RF B RSSI to CCA\n\n2" ".03.j:\n-Fixed bit sel bug in Rx CFG reg for RF B pkt det En\n\n2.03.k:\n-Fixed AGC gain capture bug (was always ca" "pturing 0, one cycle early)\n\n2.03.l:\n-Fixed FFT reset error for certain rate/length combos\n\n2.03.m:\n-Added ex" "t pkt det signal\n-Cleaned up CFO est block\n-Removed unused reset port\n\n2.03.n:\n-Updated auto-corr pkt det ener" "gy thresh datatype to UFix14_8 (from UFix12_0)\n-Reduced aut-corr pkt min dur type to UFix4_0 (from UFix6_0; value " "is 4 in ref des)\n-Updated LTS correlator to support arbitrary sample rates (still requires samp_rate<=(sys_clk/8))" "\n\n2.03.o:\n-Fixed descrambler reset bug, that caused wrong bad FCS events (at worst) every 1/126 pkts\n\n2.03.p:\n" "-Added RFC/RFD inputs\n-Added ext ADC_RX_CLK port to control sampling rate\n-Moved ext pkt det enable bit to config" "[13]\n-Added PHY CCA mode select (0=any enabled antenna, 1=all enabled antennas)\n-Added pkt det status reg bits, t" "o read per-Rx which antenna was selected\n-Moved non-switching-ant-sel to config[16:15]\n-Added PHY CCA busy calc m" "ode (any vs all enabled antennas > threshold)\n-Added DSSS active debug output\n-Added post-AGC-RSSI_CD register (_" "AB was already there)\n-Swapped some chipscope signals (added MAC rate, removed symfifo status)\n\n2.03.q:\n-Moved " "CS_ADC_x to pre-IQ-valid-qualified signals\n-Fixed bit numbering bug for pktDet_En on RFC/D\n\n2.03.r:\n-More pipel" "ineing in DSSS Rx for easier timing\n\n2.03.s:\n-Yet more pipeline registers, mostly at software accessible registe" "rs I/O\n\n2.03.t:\n-Explicit fanout regs for some sw regs for better timing\n\n2.03.u\n-More pipeline regs on top l" "evel outputs (mostly debug signals that could even be TIG)\n-Debug copy of FCS_Good signal for header output w/ ext" "ra regs\n\n2.03.v\n-Major rework of pkt det - seperate autocorr logic/thresholds for OFDM vs DSSS\n-DSSS Rx now req" "uires DSSS pkt det before starting\n-Updated registers for pkt det and DSSS Rx\n-Separate debug outputs for OFDM an" "d DSSS pkt det\n-Made max SIGNAL length value programmable (in units of kB)\n-Removed SIGNAL field register (wasn't" " used anymore - all Rx bytes are in pkt buf)\n\n2.03.w:\n-Updated DSSS autocorr threshold data types to handle high" "-SNR Rx\n-Added DSSS reset for autocorr_det but no sym sync - resets after 4 bit intervals\n-Tweaked chipscope sign" "als for better visibility of OFDM vs DSSS Rx activity\n\n2.03.x:\n-Fixed DSSS reset blocking OFDM pkt det (separate" "d min duration coutners for DSSS/OFDM)\n-Fixed DSSS pkt det signalt to CS ILA" Position [633, 692] HorizontalAlignment "left" BackgroundColor "[0.898039, 0.898039, 0.898039]" } Annotation { Name "4.00.a:\n-Redesigned LTS correlator for 4x over sampling\n\n4.00.b:\n-Disregarded ILA\n\n4.00.c:\n-Reincl" "uded ILA\n-Added \"demod reset\" input to demod sym fifo, registered to avoid async issues\n (without this some pk" "t mcs/len leave data in sym fifo at RX_END, breaking the next\n Rx. unclear if this is only possible with 40MSps " "mode?)\n\n4.00.d:\n-Disregarded ILA\n-Fixed control of OFDM sym counter in FFT subsystem. For some lengths it ran a" "way when\n FFT.data_out_tlast stuck high at end of Rx. Now conditioned on data_out_tlast & data_out_tvalid\n\n4.00" ".e:\n-Added CFO est read-ony register\n-Reincluded ILA\n\n4.00.f:\n-Removed deay on RXERROR output, so it is valid " "on RX_PARAMS, allowing the MAC core/code\n to properfly infer HT-SIG errors. before this chagne an HT-SIG field wi" "th errors could lead to deadlock\n in hardware, with MAC code waiting for the PHY to write bytes.\n-Added control " "bit to en/disbale 11n mode; when disabled PHY treats all Rx waveforms as 11a\n\n4.00.g:\n-Bypassed check on min(LEN" "GTH) in SIGNAL decode; 11n L-SIG.LENGTH can be small for very\n short payloads\n-Added PHY Mode == 11n check to HTS" "IG.valid assertion\n-Cleaned up init script, used 'rx_sim' struct to centralize sim-only params\n\n4.00.h:\n-Added " "ping/pong de-interleaving RAMs to support highest MCS at 40MSps\n\n4.00.i:\n-Redesigned de-interleaver, again; now " "uses parallel demod (all bits per subcarrier in 1 cycle) writing to\n blackbox BRAM, reading 2 LLRs per cycle into" " decoder. This architecture reduces latency enough to \n meet DATA_DONE before RX_END for all lengths at HTMF MCS7" ".\n-Added integer bit (now Fix9_7) in demod I/Q to de-skew quantized demod for outermost points in 64QAM\n\n4.00.j:" "\n-Added demod scaling for BPSK (previously re-used QPSK value)\n\n4.00.k:\n-Increased metric precision (param M) i" "n decoder to 8; fixes rare overflow in decoder for larger-than-expected\n soft bit values\n-Added global reset to " "SR latches in rate/length-busy, MAC outputs\n\n4.00.l:\n-Explicit fanout of FEC scaling values (previous 4:1 mux dr" "iving 6 mults was critical path)\n\n4.00.m:\n-Fixed reset of I/Q accumulators in pilot phase error estimate block\n" "\n4.00.n:\n-Added channel estimate smoothing\n\n4.00.o:\n-Replaced phase correction block with LUT (via DDS) and co" "mplex mult; fixes errors in low SNR where\n sym I/Q can exceed ~1.7\n\n4.00.p:\n-Simplified Rate-Length Busy block" " to always use SIGNAL.LENGTH and SIGNAL.RATE. Now works for any\nvalid SIGNAL/L-SIG field, indepdent of supported M" "CS. Much cleaner than previous version that did 11a vs 11n.\n-Updated RX_END and RX_END.ERROR outputs to cover all " "Rx PHY termination causes\n-Renamed \"RX_PARAMS\" MAC outputs to \"RX_PHY_HDR\"\n-Redefined PKTDET_BLOCK to block p" "kt det assertions but *not* cancel an ongoing Rx. Added RX_RESET\n input in place of old PKTDET_BLOCK gateway, allo" "wing MAC to reset Rx PHY if needed (i.e. during Tx)\n\n4.00.q:\n-Fixed dumb error in rate-length busy control (star" "t needed 1 cycle delay)\n\n4.00.r:\n-Added posedge to RX_ERROR OR output\n\n4.00.s - **Reference Design v1.5 Releas" "e**:\n-Added rate-length busy reset to that block's \"done\" output, so that logic depending on rate-length done wi" "ll\n see a done event even for invalid HT-SIG events\n\n4.00.t:\n-Better pipeline through Soft Demod logic, breaks" " up a few long combinational paths\n\n4.00.u:\n-Updated DATA_DONE MAC output to be OR of DSSS/OFDM outputs, permitt" "ing DATA_DONE to occur\n after RX_END\n\n4.00.v:\n-Swapped DSSS/OFDM inputs to muxes in MAC Outputs, so OFDM pipel" "ine drives outputs at all times except\n when DSSS is running. This fixes a problem when a corrupt SIGNAL de-asser" "ts RX_END long before the\n PHY_HEADER_READY signal asserts.\n-Fixed bit assignment for HT-SIG.RESERVED - previous" " assignment was wrong but didn't hurt anything\n-Updated HT-SIG decoding to require L-SIG.RATE==6Mb for valid HT-S" "IG, otherwise end with HT-SIG error\n-Delayed HT_SIG_ERROR and RX_END_ERROR so RX_END_ERROR_REASON has valid value " "when\n RX_END asserts in case of invalid HT-SIG" Position [1138, 712] HorizontalAlignment "left" BackgroundColor "[0.898039, 0.898039, 0.898039]" } Annotation { Name "4.00.w:\n-Fixed bit order for per-antenna pkt det status bits for DSSS det; now DSSS and OFDM bit orders " "match\n-Added more pipeline regs to software registers for easier timing closure\n-Removed unused debug_gpio regist" "er/port (w3_userio handles this now)\n-Moved ILA software trig bit to config register\n-Made PHY_MODE det threshold" " software param (was hard-coded to 20 before)\n-Removed RF C I/Q from ILA, added LTS Det to ILA\n-Increased latency" " in CFO and demod mults (1 to 3, now \"optimal\" for DSP48 pipeline)\n-Added better LTS correlation peak selection " "logic, now requires peaks separated by [63,64,65] samples\n\n4.00.x:\n-Change reinterpret binary point in soft demo" "d inputs to fix poor scaling that reduced soft-decision benefit\n This reverts soft demod behavior to v1.5.0 hardw" "are but with 18-bit inputs (vs 9-bit in v1.5.0). The bad\n binary point setting was adopted sometime between v1.5" ".0 and v1.5.2\n\n4.00.y:\n-Updated valid_out signal from chan est block to de-assert on zero subcarriers, improves " "robustness of\n phy_mode detection (now ignores bogus -2 values in empty subcarriers for mod_det calc)\n-Added mis" "sing pipeline delays on mod_sel output from soft_demod block (was wrong, but didn't break anything)\n-Added softwar" "e bit to block VHT waveform detection\n\n4.01.a:\n-Explicitly reset CFO estimate register and DDS between Rx events" " so that the DDS always starts at phase=0\n for new Rx events. This will help with hw/sim matching for sim of capt" "ured Rx waveforms\n\n4.01.b:\n-Fixed min_duration counter units in auto corr pkt det blocks; counter now increments" " per iq_valid, not per clock\n cycle. This provides a usable range of min_duration configuration values.\n-Added c" "ast and scale-by-2^-2 to CFO estimate vlaue latched for software (to match type of DDS input)\n\n4.01.c:\n-Redesign" "ed DSSS Rx, now with much more robust detection of PHY preamble\n-Added (disable-able) support for DSSS Rx without " "pkt det\n-Updated pkt det logic with separate \"Require Both\" config bits for DSSS and OFDM pipelines\n\n4.01.d - " "e:\n-Added registers along a few combinational feedback paths in the DSSS rx, trying to fix biazarre behavior\n in" " hardware\n\n4.01.f:\n-Fxied DSSS reset on RX_START with extra (AND NOT DSSS_RX_RUNNING) condition in DSSS reset\n\n" "4.01.g:\n-Made SYNC search time programmable\n-Added SYNC search target regs to EDK Processor\n-Re-designed SYNC/SF" "D timeouts to support pkt-det-less mode\n\n4.01.h:\n-Updated autoCorr pkt det calc to skip squaring, use real part " "of conj product as correlation coeff\n-Changed autoCorr corr thresh type to UFix8_7\n-Changed autoCorr energy thres" "h type to UFix14_10\n\n4.01.i:\n-Updated DSSS autoCorr pkt det to use abs(real(corr)) as correlation metric\n-Chang" "ed DSSS autoCorr energy_thresh to UFix16_12 (from UFix10_0)\n-Changed DSSS autoCorr corr_thresh to UFix8_7 (from UF" "ix8_6)\n\n4.01.j:\n-Added DISABLE_OFDM control bit to hold OFDM pipeline in reset\n\n4.01.k:\n-Added 2Mbps (DQPSK) " "rate to DSSS Rx, indicated to MAC as PHY_MODE=0, MCS=1\n\n4.01.l:\n-Added pkt det counters, connected to read-only " "registers\n\n4.01.m:\n-Fixed min LENGTH check for 2Mbps DSSS Rx\n-Updated auto corr pkt det logic again\n -Added se" "parate magnitude calc for OFDM/DSSS, now length-32 (OFDM) and length-40 (DSSS)\n -Changed corr_thresh types to UFix" "8_8 (0.5=128=perfect correlation, now that mag calc is 2x as long)\n\n4.01.n:\n-Fixed bug in DSSS Rx despreading ph" "ase selection\n\n4.01.o:\n-Added ASR to programatically shift despread phase selected by logic\n\n4.01.p:\n-Removed" " ASR from 4.01.o, added correct fixed dleays for IQ Mag and Desprad Phase \n before matching logic. Should *finall" "y* make selection of despread phase correct for all SNRs\n\n4.01.q:\n-Added option to block pkt det assertions when" " DSSS Rx PHY has found SYNC without pkt det\n avoids issues with mid-waveform AGC during low-SNR DSSS Rx\n\n4.01.r" ":\n-Changed both pkt det energy_thresh parsm to UFix14_3, based on experiments that shows the overall\n range was " "too small (max value set sensitivity around -75dBm) and had way too much resolution\n\n4.01.s:\n-Added delays betwe" "en RX_GLOBAL_RESET and SR latch resets in MAC IO, so DSSS RX_END+RX_END_ERROR\n can propagate to MAC before global" " reset reverts the latches \n-Added (& !DSSS_RX_RUNNING) condition to honoring the DSSS Req_PktDet config bit, to f" "ix issue where changing\n Req_PktDet mid-Rx could leave the MAC in a bad state (RX_END but no DATA_DONE)\n\n4.01.t" ":\n-Added optional mode for allow OFDM Rx to start with only LTF correlation, not requiring pkt det first. This mod" "e\n improves performance at low SNR where pkt-det is hard, and not really required since the AGC doesn't need to\n" " change gains much anyway.\n\n4.01.u:\n-Fixed missing RX_END for LTF-only Rx (overlooked pkt-det vs LTS corr input" " timing in rate-length-busy block)\n\n4.01.v:\n-Updated RSSI/gains capture logic for LTF-only and SYNC-only Rx\n -" "RSSI/gain capture was stale for non-pkt-det DSSS Rx before this\n -Both now captured on LTS correlation event or D" "SSS SIGNAL_VALID (both were AGC_DONE)\n -Added AGC_DONE to PKT_GAINS register to encode whether current\n Rx us" "ed AGC or not" Position [1133, 2027] HorizontalAlignment "left" BackgroundColor "[0.898039, 0.898039, 0.898039]" } Annotation { Position [1710, 1863] } Annotation { Position [832, 1865] } Annotation { Name "\n2.03.y:\n-Extended DSSS byte_valid to 8 cycles (trying to debug apparent failure of some DSSS payloads\n" " to be writte to BRAM...)\n\n2.03.z:\n-Fixed dumb error in 2.03.y export (DSSS det was tied high for sim, broken i" "n hw)\n\n2.04.a:\n-More itereating on DSSS data output logic\n-Added min SIGNAL.LENGTH (14 bytes) to DSSS decoder\n" "\n2.04.b:\n-Added DFF to ext pkt det reset debounce logic (fixed timing failure)\n\n2.04.c:\n-Added DFFs for ext pk" "t det input (failed timing)\n\n2.04.d:\n-Cleaned up init script and variable names\n\n2.04.e:\n-Changed auto corr m" "ag thres to UFix14_4 (from UFix14_8)\n-Added config bit to select pkt det mode that requires auto corr AND RSSI; go" "od for requiring\n min energy higher than auto corr mag can calculate on its own\n\n2.04.f:\n-More pipeline regs i" "n auto_corr pkt det\n\n2.04.g:\n-Separated state bits for RSSI pkt det for OFDM and DSSS detections. RSSI pkt det w" "as broken\n before this, ever since separating auto_corr detection blocks for DSSS/OFDM. RSSI pkt det is\n disabled" " in the reference design, so we never noticed\n\n2.04.h:\n-Increased number of bits in Decode/Ctrl/Coded Bit counte" "r by 1, fixing bug where max num bytes\n was effective halved.\n-Extended FCS_Good debug output pulse 16x for easi" "er scoping\n\n2.04.i:\n-Added logic to block PHY writes to pkt buf for byte addresses larger than a software-config" "ured\n value. This will ease tests with jumbo Rx frames.\n\n2.04.j:\n-Fixed a few hard-coded bit sizes to use MAX_N" "UM_BYTES\n-Changed MAC output BYTEIND to UFix22_0 (big enough for future updates)\n\n3.00.a:\n-Added 11n SISO suppo" "rt\n-Redesigned MAC-PHY interface\n -Added/removed ports for 11a/g/n support\n -New 'params valid' signal qualifi" "es rate/length/etc (*not* qualified RX_START anymore)\n-Updated rate-length calc for all equal modulation rates in " "11n\n -Rate-legnth block asserting busy now holds pkt det high, blocking other pkt det events\n -PHY pipeline sto" "ps on unsupported waveforms (no FFT's etc)\n -RX_END now occurs 1:1 with RX_START; RX_END always on last samp of i" "ncoming waveform,\n indepdendent of rate/bandwidth/etc\n-Updated BRAM interface addr offsets; MAC payload (post-S" "ERVICE) start at 0x10 (previously 0x8)\n\n3.00.b:\n-Added pipeline regs at SIG/HT-SIG decode outputs\n\n3.00.c:\n-F" "ixed offset for MPDU Rx bytenum output to MAC (was -12 instead of -16)\n-Fixed rate*length logic to handle short (A" "CK @ 24Mbps) 11a/g Rx events. Previous logic held\n bad state from short 11a/g packet finishing right before \"par" "ams_valid\" asserted.\n\n3.00.d:\n-Fixed Rx byte numbering for DSSS Rx (payload was at 12 insteda of 16, like OFDM)" "\n\n3.00.e:\n-Added DSSS active to Rx PHY CCA Busy (maskable by reg bit)\n-Re-added RX_ENDED_UNEXPECTEDLY to RX_ERR" "OR output (fixes bad state when Tx interrupts\n ongoing DSSS Rx; shouldn't happen (hence first fix above), but sti" "ll shouldn't cause bad state)\n\n3.00.f:\n-Extended duration of post-decode reset, to ensure upstream pipeline rese" "ts fully. Shorter duration in\nprevious version had Rx-to-Rx bad state for particular rate/length combos (including" " 24Mbps RTS)" Position [613, 1792] HorizontalAlignment "left" BackgroundColor "[0.898039, 0.898039, 0.898039]" } Annotation { Name "4.01.w:\n-Added DSSS_RX_RUNNING to PHY CCA_BUSY logic, so DSSS Rx will always assert\n CCA_BUSY, not jus" "t DSSS with pkt det active\n-Added logic to block AGC trigger for spurious mid-Rx pkt det with LTF-only Rx\n-Added " "logic to assert DATA_DONE if a reset occurs mid-reception\n-Added logic to defer pipeline reset if software disable" "s the pipeline mid-reception\n\n4.01.x:\n-Fixed bug introduced in 4.01.w where LTF det would reset AGC mid Rx\n\n4" ".01.y:\n-Removed ILA\n\n4.01.z:\n-Added pipeline reg to critical path in decoder HDL\n\n4.02.a:\n-Added RX_IQ_MAG_S" "UM_RFA register that captures real-time value from RF A\n auto-corr pkt det IQ mag calculation, for easy runtime o" "bservation of IQ level when\n calibrating front-end gains" Position [1658, 217] HorizontalAlignment "left" BackgroundColor "[0.898039, 0.898039, 0.898039]" } } } Block { BlockType SubSystem Name "ChipScope" SID "956" Ports [] Position [617, 287, 663, 333] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "ChipScope" Location [161, 165, 1853, 1141] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Reference Name "Concat1" SID "958" Ports [2, 1] Position [465, 163, 495, 207] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point at ze" "ro." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" block_version "8.2.02" sg_icon_stat "30,44,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 44 44 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 44 44 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[26.44 26.44 30.44 " "26.44 30.44 30.44 30.44 26.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[22.44 22.44 26.44 26.44 22.44 ],[0." "931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[18.44 18.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 23." "88 19.88 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 14.44 18.44 18.44 14.44 ],[0.931 0.946 0.973 ]);\nfprintf('','CO" "MMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'hi');\nc" "olor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fontsize{20}\\}','texmode','on');\nfprintf('','" "COMMENT: end icon text');\n" } Block { BlockType Reference Name "Concat2" SID "959" Ports [2, 1] Position [465, 213, 495, 257] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point at ze" "ro." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" block_version "8.2.02" sg_icon_stat "30,44,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 44 44 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 44 44 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[26.44 26.44 30.44 " "26.44 30.44 30.44 30.44 26.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[22.44 22.44 26.44 26.44 22.44 ],[0." "931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[18.44 18.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 23." "88 19.88 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 14.44 18.44 18.44 14.44 ],[0.931 0.946 0.973 ]);\nfprintf('','CO" "MMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'hi');\nc" "olor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fontsize{20}\\}','texmode','on');\nfprintf('','" "COMMENT: end icon text');\n" } Block { BlockType Reference Name "Convert1" SID "960" Ports [1, 1] Position [750, 525, 785, 545] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "16" bin_pt "14" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "35,20,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 20 20 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output'," "1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "961" Ports [1, 1] Position [750, 550, 785, 570] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "16" bin_pt "14" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "35,20,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 20 20 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output'," "1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert3" SID "962" Ports [1, 1] Position [1770, 1270, 1805, 1290] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "15" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "35,20,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 20 20 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output'," "1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert4" SID "963" Ports [1, 1] Position [750, 475, 785, 495] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "12" bin_pt "11" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "35,20,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 20 20 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output'," "1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert5" SID "964" Ports [1, 1] Position [750, 500, 785, 520] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "12" bin_pt "11" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "35,20,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 20 20 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output'," "1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "965" Position [510, 475, 665, 495] ZOrder -9 ShowName off GotoTag "CS_ADC_I" TagVisibility "global" } Block { BlockType From Name "From1" SID "966" Position [510, 500, 665, 520] ZOrder -9 ShowName off GotoTag "CS_ADC_Q" TagVisibility "global" } Block { BlockType From Name "From10" SID "967" Position [1520, 536, 1705, 554] ZOrder -9 ShowName off GotoTag "CS_DeInt_WrEn" } Block { BlockType From Name "From11" SID "968" Position [1520, 556, 1705, 574] ZOrder -9 ShowName off GotoTag "CS_DeInt_Stuff0" } Block { BlockType From Name "From12" SID "969" Position [1520, 576, 1705, 594] ZOrder -9 ShowName off GotoTag "CS_DeInt_Vout" } Block { BlockType From Name "From13" SID "970" Position [270, 185, 420, 205] ZOrder -9 ShowName off GotoTag "OFDM_FCS_GOOD" TagVisibility "global" } Block { BlockType From Name "From14" SID "971" Position [1520, 596, 1705, 614] ZOrder -9 ShowName off GotoTag "CS_DeInt_Reset" } Block { BlockType From Name "From15" SID "972" Position [1520, 1011, 1705, 1029] ZOrder -9 ShowName off GotoTag "CS_DeInt_WrAddr" } Block { BlockType From Name "From16" SID "973" Position [1520, 1036, 1705, 1054] ZOrder -9 ShowName off GotoTag "CS_DeInt_RdAddr" } Block { BlockType From Name "From17" SID "974" Position [250, 770, 400, 790] ZOrder -9 ShowName off GotoTag "CS_OFDM_SYM_IND" TagVisibility "global" } Block { BlockType From Name "From18" SID "975" Position [1045, 1160, 1195, 1180] ZOrder -9 ShowName off GotoTag "CS_DEC_LLR_b1" TagVisibility "global" } Block { BlockType From Name "From19" SID "976" Position [270, 165, 420, 185] ZOrder -9 ShowName off GotoTag "DSSS_FCS_GOOD" TagVisibility "global" } Block { BlockType From Name "From2" SID "977" Position [510, 525, 665, 545] ZOrder -9 ShowName off GotoTag "CS_EQ_I" TagVisibility "global" } Block { BlockType From Name "From20" SID "978" Position [270, 235, 420, 255] ZOrder -9 ShowName off GotoTag "OFDM_RX_DATA_DONE" TagVisibility "global" } Block { BlockType From Name "From21" SID "979" Position [270, 215, 420, 235] ZOrder -9 ShowName off GotoTag "DSSS_RX_DATA_DONE" TagVisibility "global" } Block { BlockType From Name "From22" SID "980" Position [1045, 1185, 1195, 1205] ZOrder -9 ShowName off GotoTag "CS_DEC_LLR_b0" TagVisibility "global" } Block { BlockType From Name "From23" SID "981" Position [1045, 1211, 1230, 1229] ZOrder -9 ShowName off GotoTag "CS_Deint_Addr_A" } Block { BlockType From Name "From24" SID "982" Position [240, 580, 390, 600] ZOrder -9 ShowName off GotoTag "CS_DEC_BYTE_OUT" TagVisibility "global" } Block { BlockType From Name "From25" SID "983" Position [240, 600, 390, 620] ZOrder -9 ShowName off GotoTag "CS_DEC_VOUT" TagVisibility "global" } Block { BlockType From Name "From26" SID "984" Position [240, 625, 390, 645] ZOrder -9 ShowName off GotoTag "CS_DEC_BYTE_INDEX" TagVisibility "global" } Block { BlockType From Name "From27" SID "985" Position [1520, 616, 1705, 634] ZOrder -9 ShowName off GotoTag "CS_SYMFIFO_IN_READY" } Block { BlockType From Name "From28" SID "986" Position [1520, 375, 1670, 395] ZOrder -9 ShowName off GotoTag "CS_FFT_VALID_OUT" TagVisibility "global" } Block { BlockType From Name "From29" SID "987" Position [1520, 355, 1670, 375] ZOrder -9 ShowName off GotoTag "CS_FFT_VALID_IN" TagVisibility "global" } Block { BlockType From Name "From3" SID "988" Position [510, 550, 665, 570] ZOrder -9 ShowName off GotoTag "CS_EQ_Q" TagVisibility "global" } Block { BlockType From Name "From30" SID "989" Position [1520, 955, 1670, 975] ZOrder -9 ShowName off GotoTag "CS_FFT_XKIND_OUT" TagVisibility "global" } Block { BlockType From Name "From31" SID "990" Position [1520, 636, 1705, 654] ZOrder -9 ShowName off GotoTag "CS_SYMFIFO_IN_VALID" } Block { BlockType From Name "From32" SID "991" Position [1520, 656, 1705, 674] ZOrder -9 ShowName off GotoTag "CS_SYMFIFO_IN_TUSER" } Block { BlockType From Name "From33" SID "992" Position [1520, 716, 1705, 734] ZOrder -9 ShowName off GotoTag "CS_SYMFIFO_OUT_TUSER" } Block { BlockType From Name "From34" SID "993" Position [1520, 676, 1705, 694] ZOrder -9 ShowName off GotoTag "CS_SYMFIFO_OUT_READY" } Block { BlockType From Name "From35" SID "994" Position [1045, 1056, 1230, 1074] ZOrder -9 ShowName off GotoTag "CS_SYMFIFO_OUT_VALID" } Block { BlockType From Name "From36" SID "995" Position [1045, 1085, 1200, 1105] ZOrder -9 ShowName off GotoTag "CS_SYMFIFO_OCC" } Block { BlockType From Name "From37" SID "996" Position [1535, 1071, 1720, 1089] ZOrder -9 ShowName off GotoTag "CS_Deint_RdAddr_B" } Block { BlockType From Name "From38" SID "997" Position [1045, 1236, 1230, 1254] ZOrder -9 ShowName off GotoTag "CS_SYMFIFO_IN_READY" } Block { BlockType From Name "From39" SID "998" Position [510, 675, 665, 695] ZOrder -9 ShowName off GotoTag "CS_MAC_OUT_RX_END" TagVisibility "global" } Block { BlockType From Name "From4" SID "14870" Position [510, 750, 660, 770] ZOrder -9 ShowName off GotoTag "CS_LTS_Peak" TagVisibility "global" } Block { BlockType From Name "From40" SID "999" Position [510, 700, 665, 720] ZOrder -9 ShowName off GotoTag "CS_MAC_OUT_RX_START" TagVisibility "global" } Block { BlockType From Name "From41" SID "1000" Position [510, 725, 665, 745] ZOrder -9 ShowName off GotoTag "CS_MAC_OUT_FCS_GOOD" TagVisibility "global" } Block { BlockType From Name "From42" SID "1001" Position [510, 575, 660, 595] ZOrder -9 ShowName off GotoTag "CS_RFA_RSSI" TagVisibility "global" } Block { BlockType From Name "From43" SID "1002" Position [545, 300, 695, 320] ZOrder -9 ShowName off GotoTag "CS_SW_TRIG" TagVisibility "global" } Block { BlockType From Name "From44" SID "1003" Position [1560, 1340, 1710, 1360] ZOrder -9 ShowName off GotoTag "CS_RX_SIGS_INVALID" TagVisibility "global" } Block { BlockType From Name "From45" SID "1004" Position [1535, 1140, 1685, 1160] ZOrder -9 ShowName off GotoTag "CS_LTS_Timeout" TagVisibility "global" } Block { BlockType From Name "From46" SID "1005" Position [1535, 1165, 1685, 1185] ZOrder -9 ShowName off GotoTag "CS_LTS_Det_1" } Block { BlockType From Name "From47" SID "1006" Position [1535, 1190, 1685, 1210] ZOrder -9 ShowName off GotoTag "CS_LTS_Det_2" } Block { BlockType From Name "From48" SID "1007" Position [1520, 756, 1705, 774] ZOrder -9 ShowName off GotoTag "CS_DEC_START" TagVisibility "global" } Block { BlockType From Name "From49" SID "1008" Position [1045, 1026, 1230, 1044] ZOrder -9 ShowName off GotoTag "CS_DEC_VIN" TagVisibility "global" } Block { BlockType From Name "From5" SID "1009" Position [545, 225, 700, 245] ZOrder -9 ShowName off GotoTag "CS_Pktdet_OFDM" TagVisibility "global" } Block { BlockType From Name "From50" SID "1010" Position [1520, 796, 1705, 814] ZOrder -9 ShowName off GotoTag "CS_DEC_RESET" TagVisibility "global" } Block { BlockType From Name "From51" SID "1011" Position [1520, 776, 1705, 794] ZOrder -9 ShowName off GotoTag "CS_DEC_END" TagVisibility "global" } Block { BlockType From Name "From52" SID "1012" Position [1560, 1270, 1715, 1290] ZOrder -9 ShowName off GotoTag "CS_LTS_Corr" TagVisibility "global" } Block { BlockType From Name "From53" SID "1013" Position [510, 800, 665, 820] ZOrder -9 ShowName off GotoTag "CS_Phase_Err" TagVisibility "global" } Block { BlockType From Name "From54" SID "1014" Position [1500, 901, 1630, 919] ShowName off CloseFcn "tagdialog Close" GotoTag "DSSS_RX_RUNNING" TagVisibility "global" } Block { BlockType From Name "From55" SID "1015" Position [1045, 1131, 1230, 1149] ZOrder -9 ShowName off GotoTag "CS_SYMFIFO_I_OUT" } Block { BlockType From Name "From56" SID "1016" Position [1045, 1286, 1230, 1304] ZOrder -9 ShowName off GotoTag "CS_Deint_Addr_A" } Block { BlockType From Name "From57" SID "1017" Position [1045, 1311, 1230, 1329] ZOrder -9 ShowName off GotoTag "CS_Deint_Wen" } Block { BlockType From Name "From58" SID "1018" Position [545, 325, 695, 345] ZOrder -9 ShowName off GotoTag "CS_EQ_Valid" TagVisibility "global" } Block { BlockType From Name "From59" SID "1019" Position [510, 600, 660, 620] ShowName off CloseFcn "tagdialog Close" GotoTag "OFDM_RX_SIGNAL_VALID" TagVisibility "global" } Block { BlockType From Name "From6" SID "1020" Position [545, 275, 695, 295] ZOrder -9 ShowName off GotoTag "CS_ADC_IQ_Valid" TagVisibility "global" } Block { BlockType From Name "From60" SID "1021" Position [510, 625, 710, 645] ShowName off CloseFcn "tagdialog Close" GotoTag "RX_START_DSSS_SIGNAL_VALID" TagVisibility "global" } Block { BlockType From Name "From61" SID "1022" Position [510, 650, 660, 670] ShowName off CloseFcn "tagdialog Close" GotoTag "CS_MAC_OUT_MCS" TagVisibility "global" } Block { BlockType From Name "From64" SID "1025" Position [545, 250, 700, 270] ZOrder -9 ShowName off GotoTag "CS_Pktdet_DSSS" TagVisibility "global" } Block { BlockType From Name "From7" SID "14873" Position [510, 775, 660, 795] ZOrder -9 ShowName off GotoTag "CS_LTS_Det" TagVisibility "global" } Block { BlockType From Name "From8" SID "1027" Position [1520, 496, 1705, 514] ZOrder -9 ShowName off GotoTag "CS_DeInt_Vin" } Block { BlockType From Name "From9" SID "1028" Position [1520, 516, 1705, 534] ZOrder -9 ShowName off GotoTag "CS_DeInt_ModSel" } Block { BlockType Reference Name "Register" SID "1029" Ports [1, 1] Position [945, 272, 975, 298] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[16.33 16.33 " "19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 13.33 16.33 16.33" " 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ])" ";\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label" "('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprint" "f('','COMMENT: end icon text');" Port { PortNumber 1 Name "ADC_IQ_Valid" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Register1" SID "1030" Ports [1, 1] Position [855, 647, 885, 673] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[16.33 16.33 " "19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 13.33 16.33 16.33" " 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ])" ";\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label" "('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprint" "f('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register10" SID "1031" Ports [1, 1] Position [855, 522, 885, 548] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[16.33 16.33 " "19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 13.33 16.33 16.33" " 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ])" ";\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label" "('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprint" "f('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register11" SID "1032" Ports [1, 1] Position [855, 547, 885, 573] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[16.33 16.33 " "19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 13.33 16.33 16.33" " 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ])" ";\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label" "('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprint" "f('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register12" SID "1033" Ports [1, 1] Position [855, 172, 885, 198] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[16.33 16.33 " "19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 13.33 16.33 16.33" " 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ])" ";\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label" "('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprint" "f('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register13" SID "1034" Ports [1, 1] Position [945, 172, 975, 198] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[16.33 16.33 " "19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 13.33 16.33 16.33" " 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ])" ";\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label" "('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprint" "f('','COMMENT: end icon text');" Port { PortNumber 1 Name "FCS_Good" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Register14" SID "1035" Ports [1, 1] Position [945, 197, 975, 223] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[16.33 16.33 " "19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 13.33 16.33 16.33" " 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ])" ";\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label" "('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprint" "f('','COMMENT: end icon text');" Port { PortNumber 1 Name "Pkt_Done" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Register15" SID "1036" Ports [1, 1] Position [855, 197, 885, 223] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[16.33 16.33 " "19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 13.33 16.33 16.33" " 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ])" ";\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label" "('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprint" "f('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register16" SID "1037" Ports [1, 1] Position [855, 222, 885, 248] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[16.33 16.33 " "19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 13.33 16.33 16.33" " 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ])" ";\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label" "('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprint" "f('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register17" SID "1038" Ports [1, 1] Position [945, 222, 975, 248] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[16.33 16.33 " "19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 13.33 16.33 16.33" " 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ])" ";\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label" "('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprint" "f('','COMMENT: end icon text');" Port { PortNumber 1 Name "Pkt_Det_OFDM" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Register18" SID "1039" Ports [1, 1] Position [855, 672, 885, 698] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[16.33 16.33 " "19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 13.33 16.33 16.33" " 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ])" ";\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label" "('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprint" "f('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register19" SID "1040" Ports [1, 1] Position [945, 672, 975, 698] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[16.33 16.33 " "19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 13.33 16.33 16.33" " 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ])" ";\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label" "('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprint" "f('','COMMENT: end icon text');" Port { PortNumber 1 Name "MAC_RX_END" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Register2" SID "1041" Ports [1, 1] Position [945, 472, 975, 498] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[16.33 16.33 " "19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 13.33 16.33 16.33" " 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ])" ";\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label" "('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprint" "f('','COMMENT: end icon text');" Port { PortNumber 1 Name "ADC_I" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Register20" SID "1042" Ports [1, 1] Position [855, 697, 885, 723] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[16.33 16.33 " "19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 13.33 16.33 16.33" " 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ])" ";\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label" "('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprint" "f('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register21" SID "1043" Ports [1, 1] Position [945, 697, 975, 723] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[16.33 16.33 " "19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 13.33 16.33 16.33" " 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ])" ";\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label" "('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprint" "f('','COMMENT: end icon text');" Port { PortNumber 1 Name "MAC_RX_START" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Register22" SID "1044" Ports [1, 1] Position [855, 297, 885, 323] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[16.33 16.33 " "19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 13.33 16.33 16.33" " 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ])" ";\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label" "('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprint" "f('','COMMENT: end icon text');" Port { PortNumber 1 Name "Sw Trig" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Register23" SID "1045" Ports [1, 1] Position [855, 622, 885, 648] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[16.33 16.33 " "19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 13.33 16.33 16.33" " 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ])" ";\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label" "('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprint" "f('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register24" SID "1046" Ports [1, 1] Position [945, 722, 975, 748] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[16.33 16.33 " "19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 13.33 16.33 16.33" " 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ])" ";\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label" "('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprint" "f('','COMMENT: end icon text');" Port { PortNumber 1 Name "MAC_FCS_GOOD" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Register25" SID "1047" Ports [1, 1] Position [945, 747, 975, 773] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[16.33 16.33 " "19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 13.33 16.33 16.33" " 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ])" ";\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label" "('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprint" "f('','COMMENT: end icon text');" Port { PortNumber 1 Name "LTS_Peak" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Register26" SID "1048" Ports [1, 1] Position [945, 772, 975, 798] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[16.33 16.33 " "19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 13.33 16.33 16.33" " 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ])" ";\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label" "('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprint" "f('','COMMENT: end icon text');" Port { PortNumber 1 Name "LTS_Det" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Register27" SID "1049" Ports [1, 1] Position [945, 572, 975, 598] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[16.33 16.33 " "19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 13.33 16.33 16.33" " 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ])" ";\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label" "('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprint" "f('','COMMENT: end icon text');" Port { PortNumber 1 Name "RSSI" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Register28" SID "1050" Ports [1, 1] Position [855, 722, 885, 748] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[16.33 16.33 " "19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 13.33 16.33 16.33" " 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ])" ";\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label" "('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprint" "f('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register29" SID "1051" Ports [1, 1] Position [855, 572, 885, 598] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[16.33 16.33 " "19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 13.33 16.33 16.33" " 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ])" ";\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label" "('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprint" "f('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register3" SID "1052" Ports [1, 1] Position [945, 497, 975, 523] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[16.33 16.33 " "19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 13.33 16.33 16.33" " 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ])" ";\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label" "('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprint" "f('','COMMENT: end icon text');" Port { PortNumber 1 Name "ADC_Q" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Register30" SID "1053" Ports [1, 1] Position [855, 247, 885, 273] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[16.33 16.33 " "19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 13.33 16.33 16.33" " 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ])" ";\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label" "('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprint" "f('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register31" SID "1054" Ports [1, 1] Position [855, 747, 885, 773] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[16.33 16.33 " "19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 13.33 16.33 16.33" " 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ])" ";\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label" "('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprint" "f('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register32" SID "1055" Ports [1, 1] Position [945, 247, 975, 273] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[16.33 16.33 " "19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 13.33 16.33 16.33" " 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ])" ";\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label" "('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprint" "f('','COMMENT: end icon text');" Port { PortNumber 1 Name "Pkt_Det_DSSS" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Register33" SID "1056" Ports [1, 1] Position [855, 772, 885, 798] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[16.33 16.33 " "19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 13.33 16.33 16.33" " 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ])" ";\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label" "('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprint" "f('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register34" SID "1057" Ports [1, 1] Position [855, 797, 885, 823] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[16.33 16.33 " "19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 13.33 16.33 16.33" " 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ])" ";\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label" "('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprint" "f('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register35" SID "1058" Ports [1, 1] Position [945, 797, 975, 823] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[16.33 16.33 " "19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 13.33 16.33 16.33" " 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ])" ";\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label" "('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprint" "f('','COMMENT: end icon text');" Port { PortNumber 1 Name "Phase_Err" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Register36" SID "1059" Ports [1, 1] Position [945, 597, 975, 623] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[16.33 16.33 " "19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 13.33 16.33 16.33" " 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ])" ";\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label" "('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprint" "f('','COMMENT: end icon text');" Port { PortNumber 1 Name "OFDM_Rx_Start" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Register38" SID "1060" Ports [1, 1] Position [855, 597, 885, 623] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[16.33 16.33 " "19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 13.33 16.33 16.33" " 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ])" ";\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label" "('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprint" "f('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register4" SID "1061" Ports [1, 1] Position [945, 522, 975, 548] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[16.33 16.33 " "19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 13.33 16.33 16.33" " 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ])" ";\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label" "('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprint" "f('','COMMENT: end icon text');" Port { PortNumber 1 Name "EQ_I" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Register40" SID "1062" Ports [1, 1] Position [945, 622, 975, 648] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[16.33 16.33 " "19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 13.33 16.33 16.33" " 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ])" ";\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label" "('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprint" "f('','COMMENT: end icon text');" Port { PortNumber 1 Name "DSSS_Rx_Start" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Register41" SID "1063" Ports [1, 1] Position [855, 322, 885, 348] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[16.33 16.33 " "19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 13.33 16.33 16.33" " 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ])" ";\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label" "('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprint" "f('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register42" SID "1064" Ports [1, 1] Position [945, 322, 975, 348] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[16.33 16.33 " "19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 13.33 16.33 16.33" " 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ])" ";\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label" "('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprint" "f('','COMMENT: end icon text');" Port { PortNumber 1 Name "EQ_Valid" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Register5" SID "1065" Ports [1, 1] Position [945, 547, 975, 573] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[16.33 16.33 " "19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 13.33 16.33 16.33" " 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ])" ";\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label" "('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprint" "f('','COMMENT: end icon text');" Port { PortNumber 1 Name "EQ_Q" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Register6" SID "1066" Ports [1, 1] Position [855, 272, 885, 298] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[16.33 16.33 " "19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 13.33 16.33 16.33" " 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ])" ";\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label" "('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprint" "f('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register7" SID "1067" Ports [1, 1] Position [945, 647, 975, 673] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[16.33 16.33 " "19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 13.33 16.33 16.33" " 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ])" ";\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label" "('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprint" "f('','COMMENT: end icon text');" Port { PortNumber 1 Name "MAC_RX_RATE" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Register8" SID "1068" Ports [1, 1] Position [855, 472, 885, 498] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[16.33 16.33 " "19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 13.33 16.33 16.33" " 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ])" ";\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label" "('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprint" "f('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register9" SID "1069" Ports [1, 1] Position [855, 497, 885, 523] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[16.33 16.33 " "19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 13.33 16.33 16.33" " 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ])" ";\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label" "('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprint" "f('','COMMENT: end icon text');" } Block { BlockType Reference Name "Up Sample" SID "1070" Ports [1, 1] Position [755, 572, 780, 598] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Up Sample" SourceType "Xilinx Up Sampler Block" infoedit "Up samples input data. Inserted values can be zeros or copies of the most recent input sample.
Hardware notes: No hardware is needed if inserted values are copies of the input sample; otherwise, a mux and sin" "gle bit flip-flop are used." sample_ratio "16" copy_samples on en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "usamp" sg_icon_stat "25,26,1,1,white,blue,0,2d01a39a,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('{\\fontsiz" "e{14pt}\\bf\\uparrow}16','texmode','on');\nfprintf('','COMMENT: end icon text');" } Line { SrcBlock "Register6" SrcPort 1 DstBlock "Register" DstPort 1 } Line { Name "ADC_IQ_Valid" Labels [0, 0] SrcBlock "Register" SrcPort 1 Points [105, 0] Branch { Points [0, 175; 110, 0] } Branch { Points [110, 0] } } Line { SrcBlock "Register8" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "Register9" SrcPort 1 DstBlock "Register3" DstPort 1 } Line { SrcBlock "Register10" SrcPort 1 DstBlock "Register4" DstPort 1 } Line { SrcBlock "Register11" SrcPort 1 DstBlock "Register5" DstPort 1 } Line { SrcBlock "Register29" SrcPort 1 DstBlock "Register27" DstPort 1 } Line { SrcBlock "Register38" SrcPort 1 DstBlock "Register36" DstPort 1 } Line { Name "ADC_I" Labels [-1, 0] SrcBlock "Register2" SrcPort 1 Points [215, 0] } Line { Name "ADC_Q" Labels [-1, 0] SrcBlock "Register3" SrcPort 1 Points [215, 0] } Line { Name "EQ_I" Labels [-1, 0] SrcBlock "Register4" SrcPort 1 Points [215, 0] } Line { Name "EQ_Q" Labels [-1, 0] SrcBlock "Register5" SrcPort 1 Points [215, 0] } Line { Name "RSSI" Labels [-1, 0] SrcBlock "Register27" SrcPort 1 Points [215, 0] } Line { Name "OFDM_Rx_Start" Labels [-1, 0] SrcBlock "Register36" SrcPort 1 Points [215, 0] } Line { SrcBlock "Register23" SrcPort 1 DstBlock "Register40" DstPort 1 } Line { Name "DSSS_Rx_Start" Labels [-1, 0] SrcBlock "Register40" SrcPort 1 Points [215, 0] } Line { SrcBlock "Register12" SrcPort 1 DstBlock "Register13" DstPort 1 } Line { Name "FCS_Good" Labels [0, 0] SrcBlock "Register13" SrcPort 1 Points [135, 0] Branch { Points [0, 175; 80, 0] } Branch { Points [80, 0] } } Line { SrcBlock "Register15" SrcPort 1 DstBlock "Register14" DstPort 1 } Line { Name "Pkt_Done" Labels [0, 0] SrcBlock "Register14" SrcPort 1 Points [130, 0] Branch { Points [0, 175; 85, 0] } Branch { Points [85, 0] } } Line { SrcBlock "Register16" SrcPort 1 DstBlock "Register17" DstPort 1 } Line { Name "Pkt_Det_OFDM" Labels [0, 0] SrcBlock "Register17" SrcPort 1 Points [125, 0] Branch { Points [0, 175; 90, 0] } Branch { Points [90, 0] } } Line { SrcBlock "From6" SrcPort 1 DstBlock "Register6" DstPort 1 } Line { SrcBlock "From" SrcPort 1 DstBlock "Convert4" DstPort 1 } Line { SrcBlock "From1" SrcPort 1 DstBlock "Convert5" DstPort 1 } Line { SrcBlock "From2" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "From3" SrcPort 1 DstBlock "Convert2" DstPort 1 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Register10" DstPort 1 } Line { SrcBlock "Convert2" SrcPort 1 DstBlock "Register11" DstPort 1 } Line { SrcBlock "Up Sample" SrcPort 1 DstBlock "Register29" DstPort 1 } Line { SrcBlock "Concat1" SrcPort 1 DstBlock "Register12" DstPort 1 } Line { SrcBlock "From5" SrcPort 1 DstBlock "Register16" DstPort 1 } Line { SrcBlock "Convert4" SrcPort 1 DstBlock "Register8" DstPort 1 } Line { SrcBlock "Convert5" SrcPort 1 DstBlock "Register9" DstPort 1 } Line { SrcBlock "From19" SrcPort 1 DstBlock "Concat1" DstPort 1 } Line { SrcBlock "From13" SrcPort 1 DstBlock "Concat1" DstPort 2 } Line { SrcBlock "From21" SrcPort 1 DstBlock "Concat2" DstPort 1 } Line { SrcBlock "From20" SrcPort 1 DstBlock "Concat2" DstPort 2 } Line { SrcBlock "Concat2" SrcPort 1 Points [15, 0; 0, -25] DstBlock "Register15" DstPort 1 } Line { SrcBlock "Register1" SrcPort 1 DstBlock "Register7" DstPort 1 } Line { Name "MAC_RX_RATE" Labels [-1, 0] SrcBlock "Register7" SrcPort 1 Points [215, 0] } Line { SrcBlock "Register18" SrcPort 1 DstBlock "Register19" DstPort 1 } Line { Name "MAC_RX_END" Labels [-1, 0] SrcBlock "Register19" SrcPort 1 Points [215, 0] } Line { SrcBlock "Register20" SrcPort 1 DstBlock "Register21" DstPort 1 } Line { Name "MAC_RX_START" Labels [-1, 0] SrcBlock "Register21" SrcPort 1 Points [215, 0] } Line { SrcBlock "From42" SrcPort 1 DstBlock "Up Sample" DstPort 1 } Line { SrcBlock "From61" SrcPort 1 DstBlock "Register1" DstPort 1 } Line { SrcBlock "From40" SrcPort 1 DstBlock "Register20" DstPort 1 } Line { SrcBlock "From43" SrcPort 1 DstBlock "Register22" DstPort 1 } Line { Name "Sw Trig" Labels [0, 0] SrcBlock "Register22" SrcPort 1 Points [305, 0] } Line { SrcBlock "From59" SrcPort 1 DstBlock "Register38" DstPort 1 } Line { Name "MAC_FCS_GOOD" Labels [-1, 0] SrcBlock "Register24" SrcPort 1 Points [215, 0] } Line { Name "LTS_Peak" Labels [-1, 0] SrcBlock "Register25" SrcPort 1 Points [215, 0] } Line { Name "LTS_Det" Labels [-1, 0] SrcBlock "Register26" SrcPort 1 Points [215, 0] } Line { SrcBlock "From41" SrcPort 1 DstBlock "Register28" DstPort 1 } Line { SrcBlock "Register28" SrcPort 1 DstBlock "Register24" DstPort 1 } Line { SrcBlock "Register31" SrcPort 1 DstBlock "Register25" DstPort 1 } Line { SrcBlock "Register33" SrcPort 1 DstBlock "Register26" DstPort 1 } Line { SrcBlock "Register34" SrcPort 1 DstBlock "Register35" DstPort 1 } Line { Name "Phase_Err" Labels [-1, 0] SrcBlock "Register35" SrcPort 1 Points [215, 0] } Line { SrcBlock "From53" SrcPort 1 DstBlock "Register34" DstPort 1 } Line { SrcBlock "From39" SrcPort 1 DstBlock "Register18" DstPort 1 } Line { SrcBlock "From58" SrcPort 1 DstBlock "Register41" DstPort 1 } Line { SrcBlock "Register41" SrcPort 1 DstBlock "Register42" DstPort 1 } Line { Name "EQ_Valid" Labels [0, 0] SrcBlock "Register42" SrcPort 1 Points [215, 0] } Line { SrcBlock "Register30" SrcPort 1 DstBlock "Register32" DstPort 1 } Line { SrcBlock "From64" SrcPort 1 DstBlock "Register30" DstPort 1 } Line { Name "Pkt_Det_DSSS" Labels [0, 0] SrcBlock "Register32" SrcPort 1 Points [115, 0] Branch { Points [0, 175; 100, 0] } Branch { Points [100, 0] } } Line { SrcBlock "From52" SrcPort 1 DstBlock "Convert3" DstPort 1 } Line { SrcBlock "From4" SrcPort 1 DstBlock "Register31" DstPort 1 } Line { SrcBlock "From7" SrcPort 1 DstBlock "Register33" DstPort 1 } Line { SrcBlock "From60" SrcPort 1 DstBlock "Register23" DstPort 1 } } } Block { BlockType SubSystem Name "DSSS Rx" SID "16611" Ports [4, 1] Position [905, 86, 1010, 134] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "DSSS Rx" Location [202, 74, 1902, 1160] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "125" Block { BlockType Inport Name "Pkt Det" SID "16612" Position [70, 153, 100, 167] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "I" SID "16613" Position [15, 173, 45, 187] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "Q" SID "16614" Position [15, 193, 45, 207] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "IQ Valid" SID "16615" Position [70, 213, 100, 227] Port "4" IconDisplay "Port number" } Block { BlockType BusCreator Name "Bus\nCreator" SID "16616" Ports [4, 1] Position [925, 148, 930, 257] ZOrder -2 ShowName off DisplayOption "bar" } Block { BlockType SubSystem Name "Demod" SID "16617" Ports [5, 4] Position [220, 148, 375, 252] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Demod" Location [202, 74, 1918, 1176] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Pkt Det" SID "16618" Position [60, 813, 90, 827] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "I" SID "16619" Position [120, 553, 150, 567] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "Q" SID "16620" Position [120, 573, 150, 587] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "IQ Valid" SID "16621" Position [70, 533, 100, 547] NamePlacement "alternate" Port "4" IconDisplay "Port number" } Block { BlockType Inport Name "2Mb_Payload" SID "16622" Position [70, 593, 100, 607] Port "5" IconDisplay "Port number" } Block { BlockType SubSystem Name "Bit-to-Byte" SID "16623" Ports [2, 3] Position [1160, 444, 1255, 496] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Bit-to-Byte" Location [2, 70, 1830, 1180] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Bit" SID "16624" Position [220, 498, 250, 512] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "Bit Valid" SID "16625" Position [375, 583, 405, 597] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Concat" SID "16626" Ports [8, 1] Position [535, 425, 1140, 460] BlockRotation 270 LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point at z" "ero." num_inputs "8" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "605,35,8,1,white,blue,0,6fe74153,up,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 605 605 0 0 ],[0 0 35 35 0 ],[0.77 0.82 0" ".91 ]);\nplot([0 605 605 0 0 ],[0 0 35 35 0 ]);\npatch([290.875 298.1 303.1 308.1 313.1 303.1 295.875 290.875 ],[2" "2.55 22.55 27.55 22.55 27.55 27.55 27.55 22.55 ],[1 1 1 ]);\npatch([295.875 303.1 298.1 290.875 295.875 ],[17.55 1" "7.55 22.55 22.55 17.55 ],[0.931 0.946 0.973 ]);\npatch([290.875 298.1 303.1 295.875 290.875 ],[12.55 12.55 17.55 1" "7.55 12.55 ],[1 1 1 ]);\npatch([295.875 313.1 308.1 303.1 298.1 290.875 295.875 ],[7.55 7.55 12.55 7.55 12.55 12.5" "5 7.55 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\ncolor('black');port_label('input',1,'hi');\n\n\n\n\n\n\ncolor('black');port_label('input',8,'lo');\n\ncolor('bl" "ack');disp('\\fontsize{20}\\}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant" SID "16627" Ports [0, 1] Position [660, 347, 685, 373] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "8" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "4" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,26,0,1,white,blue,0,7a8c02d8,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 " "19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 1" "3.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\n" "patch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('out" "put',1,'8');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Counter" SID "16628" Ports [2, 1] Position [580, 300, 640, 360] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited counter i" "s implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "Inf" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "8" bin_pt "0" load_pin off rst on en on explicit_period "off" period "1" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "counter" sg_icon_stat "60,60,2,1,white,blue,0,ae3608d6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 60 60 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[38.88 38.88 46" ".88 38.88 46.88 46.88 46.88 38.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[30.88 30.88 38.88 38.88 30.88" " ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[22.88 22.88 30.88 30.88 22.88 ],[1 1 1 ]);\npatch(" "[20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[14.88 14.88 22.88 14.88 22.88 22.88 14.88 ],[0.931 0.946 0.973 ]);\nfpr" "intf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'" ",1,'rst');\ncolor('black');port_label('input',2,'en');\n\ncolor('black');disp('{\\fontsize{14}\\bf++}','texmode','" "on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Counter1" SID "16629" Ports [2, 1] Position [1110, 155, 1170, 215] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited counter i" "s implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "Inf" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "ceil(log2(MAX_NUM_BYTES))" bin_pt "0" load_pin off rst on en on explicit_period "off" period "1" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "counter" sg_icon_stat "60,60,2,1,white,blue,0,ae3608d6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 60 60 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[38.88 38.88 46" ".88 38.88 46.88 46.88 46.88 38.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[30.88 30.88 38.88 38.88 30.88" " ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[22.88 22.88 30.88 30.88 22.88 ],[1 1 1 ]);\npatch(" "[20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[14.88 14.88 22.88 14.88 22.88 22.88 14.88 ],[0.931 0.946 0.973 ]);\nfpr" "intf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'" ",1,'rst');\ncolor('black');port_label('input',2,'en');\n\ncolor('black');disp('{\\fontsize{14}\\bf++}','texmode','" "on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay" SID "16630" Ports [1, 1] Position [1035, 375, 1060, 405] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "25,30,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 30 30 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[18.33 18.33 " "21.33 18.33 21.33 21.33 21.33 18.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[15.33 15.33 18.33 18.33 1" "5.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[12.33 12.33 15.33 15.33 12.33 ],[1 1 1 ]);\n" "patch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[9.33 9.33 12.33 9.33 12.33 12.33 9.33 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-1" "}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay1" SID "16631" Ports [1, 1] Position [1035, 185, 1060, 215] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "25,30,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 30 30 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[18.33 18.33 " "21.33 18.33 21.33 21.33 21.33 18.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[15.33 15.33 18.33 18.33 1" "5.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[12.33 12.33 15.33 15.33 12.33 ],[1 1 1 ]);\n" "patch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[9.33 9.33 12.33 9.33 12.33 12.33 9.33 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-1" "}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "16632" Position [240, 614, 350, 636] ZOrder -9 ShowName off GotoTag "DSSS_RX_RESET" TagVisibility "global" } Block { BlockType From Name "From1" SID "16633" Position [865, 309, 975, 331] ZOrder -9 ShowName off GotoTag "DSSS_RX_RESET" TagVisibility "global" } Block { BlockType From Name "From2" SID "16634" Position [865, 159, 975, 181] ZOrder -9 ShowName off GotoTag "DSSS_RX_RESET" TagVisibility "global" } Block { BlockType Reference Name "Logical1" SID "16635" Ports [2, 1] Position [515, 298, 550, 327] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,29,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 29 29 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 29 29 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[18.44 18.44 22.4" "4 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[14.44 14.44 18.44 18.44 14.44 ]," "[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\npatch([12.1" " 25.88 21.88 17.88 13.88 8.1 12.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('or');\nfprintf('" "','COMMENT: end icon text');" } Block { BlockType Reference Name "Register" SID "16636" Ports [3, 1] Position [520, 495, 560, 565] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "40,70,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 70 70 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 70 70 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[40.55 40.55 45." "55 40.55 45.55 45.55 45.55 40.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[35.55 35.55 40.55 40.55 35." "55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[30.55 30.55 35.55 35.55 30.55 ],[1 1 1 ]);\npa" "tch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[25.55 25.55 30.55 25.55 30.55 30.55 25.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i" "nput',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'en');\ncolor('bla" "ck');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" } Block { BlockType Reference Name "Register1" SID "16637" Ports [3, 1] Position [595, 495, 635, 565] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "40,70,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 70 70 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 70 70 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[40.55 40.55 45." "55 40.55 45.55 45.55 45.55 40.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[35.55 35.55 40.55 40.55 35." "55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[30.55 30.55 35.55 35.55 30.55 ],[1 1 1 ]);\npa" "tch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[25.55 25.55 30.55 25.55 30.55 30.55 25.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i" "nput',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'en');\ncolor('bla" "ck');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" } Block { BlockType Reference Name "Register2" SID "16638" Ports [3, 1] Position [670, 495, 710, 565] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "40,70,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 70 70 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 70 70 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[40.55 40.55 45." "55 40.55 45.55 45.55 45.55 40.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[35.55 35.55 40.55 40.55 35." "55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[30.55 30.55 35.55 35.55 30.55 ],[1 1 1 ]);\npa" "tch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[25.55 25.55 30.55 25.55 30.55 30.55 25.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i" "nput',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'en');\ncolor('bla" "ck');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" } Block { BlockType Reference Name "Register3" SID "16639" Ports [3, 1] Position [745, 495, 785, 565] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "40,70,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 70 70 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 70 70 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[40.55 40.55 45." "55 40.55 45.55 45.55 45.55 40.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[35.55 35.55 40.55 40.55 35." "55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[30.55 30.55 35.55 35.55 30.55 ],[1 1 1 ]);\npa" "tch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[25.55 25.55 30.55 25.55 30.55 30.55 25.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i" "nput',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'en');\ncolor('bla" "ck');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" } Block { BlockType Reference Name "Register4" SID "16640" Ports [3, 1] Position [820, 495, 860, 565] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "40,70,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 70 70 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 70 70 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[40.55 40.55 45." "55 40.55 45.55 45.55 45.55 40.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[35.55 35.55 40.55 40.55 35." "55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[30.55 30.55 35.55 35.55 30.55 ],[1 1 1 ]);\npa" "tch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[25.55 25.55 30.55 25.55 30.55 30.55 25.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i" "nput',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'en');\ncolor('bla" "ck');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" } Block { BlockType Reference Name "Register5" SID "16641" Ports [3, 1] Position [895, 495, 935, 565] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "40,70,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 70 70 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 70 70 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[40.55 40.55 45." "55 40.55 45.55 45.55 45.55 40.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[35.55 35.55 40.55 40.55 35." "55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[30.55 30.55 35.55 35.55 30.55 ],[1 1 1 ]);\npa" "tch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[25.55 25.55 30.55 25.55 30.55 30.55 25.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i" "nput',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'en');\ncolor('bla" "ck');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" } Block { BlockType Reference Name "Register6" SID "16642" Ports [3, 1] Position [970, 495, 1010, 565] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "40,70,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 70 70 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 70 70 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[40.55 40.55 45." "55 40.55 45.55 45.55 45.55 40.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[35.55 35.55 40.55 40.55 35." "55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[30.55 30.55 35.55 35.55 30.55 ],[1 1 1 ]);\npa" "tch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[25.55 25.55 30.55 25.55 30.55 30.55 25.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i" "nput',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'en');\ncolor('bla" "ck');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" } Block { BlockType Reference Name "Register7" SID "16643" Ports [3, 1] Position [1045, 495, 1085, 565] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "40,70,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 70 70 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 70 70 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[40.55 40.55 45." "55 40.55 45.55 45.55 45.55 40.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[35.55 35.55 40.55 40.55 35." "55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[30.55 30.55 35.55 35.55 30.55 ],[1 1 1 ]);\npa" "tch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[25.55 25.55 30.55 25.55 30.55 30.55 25.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i" "nput',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'en');\ncolor('bla" "ck');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" } Block { BlockType Reference Name "Register8" SID "16644" Ports [3, 1] Position [1030, 285, 1070, 355] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "40,70,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 70 70 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 70 70 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[40.55 40.55 45." "55 40.55 45.55 45.55 45.55 40.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[35.55 35.55 40.55 40.55 35." "55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[30.55 30.55 35.55 35.55 30.55 ],[1 1 1 ]);\npa" "tch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[25.55 25.55 30.55 25.55 30.55 30.55 25.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i" "nput',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'en');\ncolor('bla" "ck');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" } Block { BlockType Reference Name "Relational" SID "16645" Ports [2, 1] Position [715, 317, 770, 373] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "55,56,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 55 55 0 0 ],[0 0 56 56 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ],[35.77 35" ".77 42.77 35.77 42.77 42.77 42.77 35.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[28.77 28.77 35.77" " 35.77 28.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[21.77 21.77 28.77 28.77 21.77 ]," "[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[14.77 14.77 21.77 14.77 21.77 21.77 14.77 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1," "'\\bfa = b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Byte" SID "16646" Position [1260, 313, 1290, 327] ZOrder -9 IconDisplay "Port number" } Block { BlockType Outport Name "Byte Valid" SID "16647" Position [1260, 383, 1290, 397] ZOrder -9 Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "Byte Ind" SID "16648" Position [1260, 178, 1290, 192] Port "3" IconDisplay "Port number" } Line { SrcBlock "Register" SrcPort 1 Points [10, 0; 0, -25] Branch { DstBlock "Register1" DstPort 1 } Branch { DstBlock "Concat" DstPort 1 } } Line { SrcBlock "Register1" SrcPort 1 Points [10, 0; 0, -25] Branch { DstBlock "Register2" DstPort 1 } Branch { DstBlock "Concat" DstPort 2 } } Line { SrcBlock "Register2" SrcPort 1 Points [10, 0; 0, -25] Branch { DstBlock "Register3" DstPort 1 } Branch { DstBlock "Concat" DstPort 3 } } Line { SrcBlock "Register3" SrcPort 1 Points [10, 0; 0, -25] Branch { DstBlock "Register4" DstPort 1 } Branch { DstBlock "Concat" DstPort 4 } } Line { SrcBlock "Register4" SrcPort 1 Points [10, 0; 0, -25] Branch { DstBlock "Register5" DstPort 1 } Branch { DstBlock "Concat" DstPort 5 } } Line { SrcBlock "Register5" SrcPort 1 Points [10, 0; 0, -25] Branch { DstBlock "Register6" DstPort 1 } Branch { DstBlock "Concat" DstPort 6 } } Line { SrcBlock "Register6" SrcPort 1 Points [10, 0; 0, -25] Branch { DstBlock "Register7" DstPort 1 } Branch { DstBlock "Concat" DstPort 7 } } Line { SrcBlock "Bit Valid" SrcPort 1 Points [85, 0] Branch { Points [85, 0] Branch { DstBlock "Register1" DstPort 3 } Branch { Points [75, 0] Branch { DstBlock "Register2" DstPort 3 } Branch { Points [75, 0] Branch { DstBlock "Register3" DstPort 3 } Branch { Points [75, 0] Branch { DstBlock "Register4" DstPort 3 } Branch { Points [75, 0] Branch { DstBlock "Register5" DstPort 3 } Branch { Points [75, 0] Branch { DstBlock "Register6" DstPort 3 } Branch { Points [75, 0] DstBlock "Register7" DstPort 3 } } } } } } } Branch { Points [0, -35] Branch { DstBlock "Register" DstPort 3 } Branch { Points [0, -210] DstBlock "Counter" DstPort 2 } } } Line { SrcBlock "From" SrcPort 1 Points [130, 0] Branch { Points [85, 0] Branch { Points [75, 0] Branch { Points [75, 0] Branch { Points [75, 0] Branch { Points [75, 0] Branch { Points [80, 0] Branch { Points [0, -95] DstBlock "Register6" DstPort 2 } Branch { Points [75, 0; 0, -95] DstBlock "Register7" DstPort 2 } } Branch { Points [0, -95] DstBlock "Register5" DstPort 2 } } Branch { Points [0, -95] DstBlock "Register4" DstPort 2 } } Branch { Points [0, -95] DstBlock "Register3" DstPort 2 } } Branch { Points [0, -95] DstBlock "Register2" DstPort 2 } } Branch { Points [0, -95] DstBlock "Register1" DstPort 2 } } Branch { Points [0, -95] Branch { DstBlock "Register" DstPort 2 } Branch { Points [0, -210] DstBlock "Logical1" DstPort 2 } } } Line { SrcBlock "Bit" SrcPort 1 DstBlock "Register" DstPort 1 } Line { SrcBlock "Register7" SrcPort 1 Points [10, 0] DstBlock "Concat" DstPort 8 } Line { SrcBlock "Concat" SrcPort 1 Points [0, -125] DstBlock "Register8" DstPort 1 } Line { SrcBlock "Constant" SrcPort 1 DstBlock "Relational" DstPort 2 } Line { SrcBlock "Counter" SrcPort 1 DstBlock "Relational" DstPort 1 } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Counter" DstPort 1 } Line { SrcBlock "Relational" SrcPort 1 Points [20, 0] Branch { Points [0, -80; -305, 0; 0, 40] DstBlock "Logical1" DstPort 1 } Branch { Points [210, 0] Branch { DstBlock "Register8" DstPort 3 } Branch { Points [0, -145] DstBlock "Delay1" DstPort 1 } Branch { Points [0, 45] DstBlock "Delay" DstPort 1 } } } Line { SrcBlock "From1" SrcPort 1 DstBlock "Register8" DstPort 2 } Line { SrcBlock "Register8" SrcPort 1 DstBlock "Byte" DstPort 1 } Line { SrcBlock "Delay" SrcPort 1 DstBlock "Byte Valid" DstPort 1 } Line { SrcBlock "From2" SrcPort 1 DstBlock "Counter1" DstPort 1 } Line { SrcBlock "Counter1" SrcPort 1 DstBlock "Byte Ind" DstPort 1 } Line { SrcBlock "Delay1" SrcPort 1 DstBlock "Counter1" DstPort 2 } } } Block { BlockType Scope Name "DSSS Demod" SID "16649" Ports [9] Position [1325, 113, 1385, 317] ZOrder -16 Floating off Location [1, 45, 1836, 1199] Open off NumInputPorts "9" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" axes9 "%" } List { ListType ScopeGraphics FigureColor "[0.5 0.5 0.5]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "45388 " YMin "0~0~0~-1~-1~-1~-1~0.95~-1" YMax "1~1~1~1~1~1~1~1.05~1" SaveName "ScopeData7" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType SubSystem Name "Demod" SID "16650" Ports [4, 3] Position [265, 531, 365, 609] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Demod" Location [202, 74, 1918, 1160] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "IQ Valid" SID "16651" Position [15, 448, 45, 462] IconDisplay "Port number" } Block { BlockType Inport Name "Rx I" SID "16652" Position [65, 428, 95, 442] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "Rx Q" SID "16653" Position [65, 478, 95, 492] NamePlacement "alternate" Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "Mod Sel" SID "17399" Position [1065, 578, 1095, 592] Port "4" IconDisplay "Port number" } Block { BlockType SubSystem Name "Abs Mag" SID "16654" Ports [3, 2] Position [1045, 631, 1110, 719] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Abs Mag" Location [2, 70, 1830, 1180] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Valid" SID "16655" Position [180, 293, 210, 307] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "A I" SID "16656" Position [180, 343, 210, 357] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "A Q" SID "16657" Position [180, 428, 210, 442] NamePlacement "alternate" Port "3" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub" SID "16658" Ports [2, 1] Position [490, 351, 520, 409] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "1" precision "User Defined" arith_type "Unsigned" n_bits "20" bin_pt "12" quantization "Truncate" overflow "Saturate" dbl_ovrd off use_behavioral_HDL off hw_selection "Fabric" pipelined off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" sg_icon_stat "30,58,2,1,white,blue,0,e85d8a90,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 58 58 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 58 58 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[33.44 33.4" "4 37.44 33.44 37.44 37.44 37.44 33.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[29.44 29.44 33.44 33.44 " "29.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[25.44 25.44 29.44 29.44 25.44 ],[1 1 1 ]);\np" "atch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[21.44 21.44 25.44 21.44 25.44 25.44 21.44 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label" "('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bf{a + b}'," "'texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\newline\\bf{}" "','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay" SID "16659" Ports [1, 1] Position [430, 286, 465, 314] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "4" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,28,1,1,white,blue,0,d390c2d8,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 28 28 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[18.44 18.4" "4 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[14.44 14.44 18.44 18.44 " "14.44 ],[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\np" "atch([12.1 25.88 21.88 17.88 13.88 8.1 12.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-" "4}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mult" SID "16660" Ports [2, 1] Position [360, 334, 395, 396] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mult" SourceType "Xilinx Multiplier Block" infoedit "Hardware notes: To check for the optimum internal pipeline stages of the dedicated multiplier you" " must select 'Test for optimum pipelining'.

Optimization Goal: For implementation into device fabric (LUT" "s), the Speed or Area optimization will take effect only if it's supported by IP for the particular device famil" "y. Otherwise, the results will be identical regardless of the selection." precision "User Defined" arith_type "Unsigned" n_bits "19" bin_pt "12" quantization "Truncate" overflow "Saturate" en off latency "3" dbl_ovrd off use_behavioral_HDL off opt "Speed" use_embedded on optimum_pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" pipeline "on" use_rpm "on" placement_style "Triangular" has_advanced_control "0" sggui_pos "936,287,348,577" block_type "mult" sg_icon_stat "35,62,2,1,white,blue,0,7028354c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 62 62 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 62 62 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[36.55 36." "55 41.55 36.55 41.55 41.55 41.55 36.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[31.55 31.55 36.55 3" "6.55 31.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[26.55 26.55 31.55 31.55 26.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[21.55 21.55 26.55 21.55 26.55 26.55 21.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bfa \\times b','texmode','on');\ncolor('black');disp('z^{-3}\\newline ','texmode','on');\ncolor('black');disp(' " "\\n ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mult1" SID "16661" Ports [2, 1] Position [360, 419, 395, 481] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mult" SourceType "Xilinx Multiplier Block" infoedit "Hardware notes: To check for the optimum internal pipeline stages of the dedicated multiplier you" " must select 'Test for optimum pipelining'.

Optimization Goal: For implementation into device fabric (LUT" "s), the Speed or Area optimization will take effect only if it's supported by IP for the particular device famil" "y. Otherwise, the results will be identical regardless of the selection." precision "User Defined" arith_type "Unsigned" n_bits "19" bin_pt "12" quantization "Truncate" overflow "Saturate" en off latency "3" dbl_ovrd off use_behavioral_HDL off opt "Speed" use_embedded on optimum_pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" pipeline "on" use_rpm "on" placement_style "Triangular" has_advanced_control "0" sggui_pos "936,287,348,577" block_type "mult" sg_icon_stat "35,62,2,1,white,blue,0,7028354c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 62 62 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 62 62 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[36.55 36." "55 41.55 36.55 41.55 41.55 41.55 36.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[31.55 31.55 36.55 3" "6.55 31.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[26.55 26.55 31.55 31.55 26.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[21.55 21.55 26.55 21.55 26.55 26.55 21.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bfa \\times b','texmode','on');\ncolor('black');disp('z^{-3}\\newline ','texmode','on');\ncolor('black');disp(' " "\\n ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name " Valid" SID "16662" Position [630, 293, 660, 307] IconDisplay "Port number" } Block { BlockType Outport Name "Mag" SID "16663" Position [630, 373, 660, 387] Port "2" IconDisplay "Port number" } Line { SrcBlock "Delay" SrcPort 1 DstBlock " Valid" DstPort 1 } Line { SrcBlock "AddSub" SrcPort 1 DstBlock "Mag" DstPort 1 } Line { SrcBlock "Mult1" SrcPort 1 Points [15, 0; 0, -55] DstBlock "AddSub" DstPort 2 } Line { SrcBlock "Mult" SrcPort 1 DstBlock "AddSub" DstPort 1 } Line { SrcBlock "A Q" SrcPort 1 Points [115, 0] Branch { DstBlock "Mult1" DstPort 1 } Branch { Points [0, 30] DstBlock "Mult1" DstPort 2 } } Line { SrcBlock "A I" SrcPort 1 Points [115, 0] Branch { DstBlock "Mult" DstPort 1 } Branch { Points [0, 30] DstBlock "Mult" DstPort 2 } } Line { SrcBlock "Valid" SrcPort 1 DstBlock "Delay" DstPort 1 } Annotation { Name "These mults can overflow with saturated IQ (pre-AGC), but no downstream\nblocks have memory that woul" "d be corrupted by this, so it's safe\nto ignore the overflows and save bits here." Position [383, 512] } } } Block { BlockType SubSystem Name "Conj Mult" SID "16664" Ports [5, 3] Position [1045, 337, 1110, 533] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Conj Mult" Location [227, 108, 1983, 1242] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Valid" SID "16665" Position [180, 293, 210, 307] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "A I" SID "16666" Position [180, 343, 210, 357] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "A Q" SID "16667" Position [180, 428, 210, 442] NamePlacement "alternate" Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "B I" SID "16668" Position [180, 373, 210, 387] NamePlacement "alternate" Port "4" IconDisplay "Port number" } Block { BlockType Inport Name "B Q" SID "16669" Position [180, 458, 210, 472] NamePlacement "alternate" Port "5" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub" SID "16670" Ports [2, 1] Position [490, 351, 520, 409] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "1" precision "User Defined" arith_type "Signed (2's comp)" n_bits "24" bin_pt "16" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL off hw_selection "Fabric" pipelined off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" sg_icon_stat "30,58,2,1,white,blue,0,e85d8a90,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 58 58 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 58 58 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[33.44 33.4" "4 37.44 33.44 37.44 37.44 37.44 33.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[29.44 29.44 33.44 33.44 " "29.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[25.44 25.44 29.44 29.44 25.44 ],[1 1 1 ]);\np" "atch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[21.44 21.44 25.44 21.44 25.44 25.44 21.44 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label" "('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bf{a + b}'," "'texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\newline\\bf{}" "','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub1" SID "17366" Ports [2, 1] Position [490, 526, 520, 584] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Subtraction" use_carryin off use_carryout off en off latency "1" precision "User Defined" arith_type "Signed (2's comp)" n_bits "24" bin_pt "16" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL off hw_selection "Fabric" pipelined off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" sg_icon_stat "30,58,2,1,white,blue,0,8a00a986,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 58 58 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 58 58 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[33.44 33.4" "4 37.44 33.44 37.44 37.44 37.44 33.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[29.44 29.44 33.44 33.44 " "29.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[25.44 25.44 29.44 29.44 25.44 ],[1 1 1 ]);\np" "atch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[21.44 21.44 25.44 21.44 25.44 25.44 21.44 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label" "('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bf{a - b}'," "'texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\newline\\bf{}" "','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay" SID "16671" Ports [1, 1] Position [430, 286, 465, 314] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "4" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,28,1,1,white,blue,0,d390c2d8,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 28 28 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[18.44 18.4" "4 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[14.44 14.44 18.44 18.44 " "14.44 ],[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\np" "atch([12.1 25.88 21.88 17.88 13.88 8.1 12.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-" "4}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mult" SID "16672" Ports [2, 1] Position [360, 334, 395, 396] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mult" SourceType "Xilinx Multiplier Block" infoedit "Hardware notes: To check for the optimum internal pipeline stages of the dedicated multiplier you" " must select 'Test for optimum pipelining'.

Optimization Goal: For implementation into device fabric (LUT" "s), the Speed or Area optimization will take effect only if it's supported by IP for the particular device famil" "y. Otherwise, the results will be identical regardless of the selection." precision "User Defined" arith_type "Signed (2's comp)" n_bits "24" bin_pt "17" quantization "Truncate" overflow "Wrap" en off latency "3" dbl_ovrd off use_behavioral_HDL off opt "Speed" use_embedded on optimum_pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" pipeline "on" use_rpm "on" placement_style "Triangular" has_advanced_control "0" sggui_pos "936,287,348,577" block_type "mult" sg_icon_stat "35,62,2,1,white,blue,0,7028354c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 62 62 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 62 62 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[36.55 36." "55 41.55 36.55 41.55 41.55 41.55 36.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[31.55 31.55 36.55 3" "6.55 31.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[26.55 26.55 31.55 31.55 26.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[21.55 21.55 26.55 21.55 26.55 26.55 21.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bfa \\times b','texmode','on');\ncolor('black');disp('z^{-3}\\newline ','texmode','on');\ncolor('black');disp(' " "\\n ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mult1" SID "16673" Ports [2, 1] Position [360, 419, 395, 481] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mult" SourceType "Xilinx Multiplier Block" infoedit "Hardware notes: To check for the optimum internal pipeline stages of the dedicated multiplier you" " must select 'Test for optimum pipelining'.

Optimization Goal: For implementation into device fabric (LUT" "s), the Speed or Area optimization will take effect only if it's supported by IP for the particular device famil" "y. Otherwise, the results will be identical regardless of the selection." precision "User Defined" arith_type "Signed (2's comp)" n_bits "24" bin_pt "17" quantization "Truncate" overflow "Wrap" en off latency "3" dbl_ovrd off use_behavioral_HDL off opt "Speed" use_embedded on optimum_pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" pipeline "on" use_rpm "on" placement_style "Triangular" has_advanced_control "0" sggui_pos "936,287,348,577" block_type "mult" sg_icon_stat "35,62,2,1,white,blue,0,7028354c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 62 62 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 62 62 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[36.55 36." "55 41.55 36.55 41.55 41.55 41.55 36.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[31.55 31.55 36.55 3" "6.55 31.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[26.55 26.55 31.55 31.55 26.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[21.55 21.55 26.55 21.55 26.55 26.55 21.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bfa \\times b','texmode','on');\ncolor('black');disp('z^{-3}\\newline ','texmode','on');\ncolor('black');disp(' " "\\n ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mult2" SID "17364" Ports [2, 1] Position [360, 509, 395, 571] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mult" SourceType "Xilinx Multiplier Block" infoedit "Hardware notes: To check for the optimum internal pipeline stages of the dedicated multiplier you" " must select 'Test for optimum pipelining'.

Optimization Goal: For implementation into device fabric (LUT" "s), the Speed or Area optimization will take effect only if it's supported by IP for the particular device famil" "y. Otherwise, the results will be identical regardless of the selection." precision "User Defined" arith_type "Signed (2's comp)" n_bits "24" bin_pt "17" quantization "Truncate" overflow "Wrap" en off latency "3" dbl_ovrd off use_behavioral_HDL off opt "Speed" use_embedded on optimum_pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" pipeline "on" use_rpm "on" placement_style "Triangular" has_advanced_control "0" sggui_pos "936,287,348,577" block_type "mult" sg_icon_stat "35,62,2,1,white,blue,0,7028354c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 62 62 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 62 62 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[36.55 36." "55 41.55 36.55 41.55 41.55 41.55 36.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[31.55 31.55 36.55 3" "6.55 31.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[26.55 26.55 31.55 31.55 26.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[21.55 21.55 26.55 21.55 26.55 26.55 21.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bfa \\times b','texmode','on');\ncolor('black');disp('z^{-3}\\newline ','texmode','on');\ncolor('black');disp(' " "\\n ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mult3" SID "17365" Ports [2, 1] Position [360, 584, 395, 646] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mult" SourceType "Xilinx Multiplier Block" infoedit "Hardware notes: To check for the optimum internal pipeline stages of the dedicated multiplier you" " must select 'Test for optimum pipelining'.

Optimization Goal: For implementation into device fabric (LUT" "s), the Speed or Area optimization will take effect only if it's supported by IP for the particular device famil" "y. Otherwise, the results will be identical regardless of the selection." precision "User Defined" arith_type "Signed (2's comp)" n_bits "24" bin_pt "17" quantization "Truncate" overflow "Wrap" en off latency "3" dbl_ovrd off use_behavioral_HDL off opt "Speed" use_embedded on optimum_pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" pipeline "on" use_rpm "on" placement_style "Triangular" has_advanced_control "0" sggui_pos "936,287,348,577" block_type "mult" sg_icon_stat "35,62,2,1,white,blue,0,7028354c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 62 62 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 62 62 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[36.55 36." "55 41.55 36.55 41.55 41.55 41.55 36.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[31.55 31.55 36.55 3" "6.55 31.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[26.55 26.55 31.55 31.55 26.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[21.55 21.55 26.55 21.55 26.55 26.55 21.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bfa \\times b','texmode','on');\ncolor('black');disp('z^{-3}\\newline ','texmode','on');\ncolor('black');disp(' " "\\n ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name " Valid" SID "16674" Position [815, 293, 845, 307] IconDisplay "Port number" } Block { BlockType Outport Name " I" SID "16675" Position [630, 373, 660, 387] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "Q" SID "17367" Position [620, 548, 650, 562] Port "3" IconDisplay "Port number" } Line { SrcBlock "B Q" SrcPort 1 Points [110, 0] Branch { DstBlock "Mult1" DstPort 2 } Branch { Points [0, 90] DstBlock "Mult2" DstPort 2 } } Line { SrcBlock "Valid" SrcPort 1 DstBlock "Delay" DstPort 1 } Line { SrcBlock "A I" SrcPort 1 Points [115, 0] Branch { DstBlock "Mult" DstPort 1 } Branch { Points [0, 175] DstBlock "Mult2" DstPort 1 } } Line { SrcBlock "B I" SrcPort 1 Points [80, 0] Branch { DstBlock "Mult" DstPort 2 } Branch { Points [0, 250] DstBlock "Mult3" DstPort 2 } } Line { SrcBlock "A Q" SrcPort 1 Points [85, 0] Branch { DstBlock "Mult1" DstPort 1 } Branch { Points [0, 165] DstBlock "Mult3" DstPort 1 } } Line { SrcBlock "Mult" SrcPort 1 DstBlock "AddSub" DstPort 1 } Line { SrcBlock "Mult1" SrcPort 1 Points [15, 0; 0, -55] DstBlock "AddSub" DstPort 2 } Line { SrcBlock "AddSub" SrcPort 1 DstBlock " I" DstPort 1 } Line { SrcBlock "Delay" SrcPort 1 DstBlock " Valid" DstPort 1 } Line { SrcBlock "Mult2" SrcPort 1 DstBlock "AddSub1" DstPort 1 } Line { SrcBlock "Mult3" SrcPort 1 Points [40, 0; 0, -45] DstBlock "AddSub1" DstPort 2 } Line { SrcBlock "AddSub1" SrcPort 1 DstBlock "Q" DstPort 1 } Annotation { Name "These mults can overflow with saturated IQ (pre-AGC), but no downstream\nblocks have memory that woul" "d be corrupted by this, so it's safe\nto ignore the overflows and save bits here." Position [398, 207] } } } Block { BlockType Reference Name "Constant1" SID "16677" Ports [0, 1] Position [55, 367, 80, 393] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Boolean" arith_type "Boolean" n_bits "16" bin_pt "14" preci_type "Single" exp_width "8" frac_width "24" explicit_period on period "8" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,26,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 " "19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 1" "3.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\n" "patch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('out" "put',1,'1');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay" SID "16678" Ports [2, 1] Position [730, 444, 785, 486] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en on latency "DSSS_SAMPS_PER_SYM" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "55,42,2,1,white,blue,0,bbd9dacd,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 42 42 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 55 55 0 0 ],[0 0 42 42 0 ]);\npatch([13.65 22.32 28.32 34.32 40.32 28.32 19.65 13.65 ],[27.66 27.66" " 33.66 27.66 33.66 33.66 33.66 27.66 ],[1 1 1 ]);\npatch([19.65 28.32 22.32 13.65 19.65 ],[21.66 21.66 27.66 27.66" " 21.66 ],[0.931 0.946 0.973 ]);\npatch([13.65 22.32 28.32 19.65 13.65 ],[15.66 15.66 21.66 21.66 15.66 ],[1 1 1 ])" ";\npatch([19.65 40.32 34.32 28.32 22.32 13.65 19.65 ],[9.66 9.66 15.66 9.66 15.66 15.66 9.66 ],[0.931 0.946 0.973 " "]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_lab" "el('input',2,'en');\n\ncolor('black');disp('z^{-20}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay1" SID "16679" Ports [2, 1] Position [730, 484, 785, 526] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en on latency "DSSS_SAMPS_PER_SYM" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "55,42,2,1,white,blue,0,bbd9dacd,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 42 42 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 55 55 0 0 ],[0 0 42 42 0 ]);\npatch([13.65 22.32 28.32 34.32 40.32 28.32 19.65 13.65 ],[27.66 27.66" " 33.66 27.66 33.66 33.66 33.66 27.66 ],[1 1 1 ]);\npatch([19.65 28.32 22.32 13.65 19.65 ],[21.66 21.66 27.66 27.66" " 21.66 ],[0.931 0.946 0.973 ]);\npatch([13.65 22.32 28.32 19.65 13.65 ],[15.66 15.66 21.66 21.66 15.66 ],[1 1 1 ])" ";\npatch([19.65 40.32 34.32 28.32 22.32 13.65 19.65 ],[9.66 9.66 15.66 9.66 15.66 15.66 9.66 ],[0.931 0.946 0.973 " "]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_lab" "el('input',2,'en');\n\ncolor('black');disp('z^{-20}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay2" SID "16680" Ports [1, 1] Position [945, 340, 980, 370] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,30,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 30 30 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[19.44 19.44 23.4" "4 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[15.44 15.44 19.44 19.44 15.44 ]," "[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([12.1" " 25.88 21.88 17.88 13.88 8.1 12.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-1}','texmode'," "'on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay3" SID "17380" Ports [1, 1] Position [1205, 685, 1240, 715] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,30,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 30 30 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[19.44 19.44 23.4" "4 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[15.44 15.44 19.44 19.44 15.44 ]," "[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([12.1" " 25.88 21.88 17.88 13.88 8.1 12.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-1}','texmode'," "'on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay4" SID "17886" Ports [2, 1] Position [1205, 792, 1240, 823] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en on latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,31,2,1,white,blue,0,7c0ac154,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 31 31 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 31 31 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[19.44 19.44 23.4" "4 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[15.44 15.44 19.44 19.44 15.44 ]," "[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([12.1" " 25.88 21.88 17.88 13.88 8.1 12.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('input',2,'en')" ";\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Scope Name "Demod" SID "16681" Ports [10] Position [1575, 87, 1630, 283] ZOrder -16 Floating off Location [1, 45, 1836, 1199] Open off NumInputPorts "10" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" axes9 "%" axes10 "%" } List { ListType ScopeGraphics FigureColor "[0.5 0.5 0.5]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "35000" YMin "-0.75~-0.5~0~0~-4~-4~-10~-10~0~0" YMax "0.5~0.5~1~1~4~4~12.5~10~1~12.5" SaveName "ScopeData4" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType SubSystem Name "Despread Filter" SID "17894" Ports [3, 3] Position [355, 366, 480, 524] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Despread Filter" Location [442, 403, 802, 754] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "IQ Valid In" SID "17896" Position [460, 348, 490, 362] IconDisplay "Port number" } Block { BlockType Inport Name "Rx I" SID "17898" Position [460, 398, 490, 412] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "Rx Q" SID "17900" Position [460, 448, 490, 462] Port "3" IconDisplay "Port number" } Block { BlockType Reference Name "FIR Compiler 6.3 " SID "16682" Ports [3, 4] Position [525, 328, 715, 482] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/FIR Compiler 6.3 " SourceType "Xilinx FIR Compiler 6.3 Block" coefficientvector "flipud(spread_seq_20(:))" coefficient_sets "1" coefficient_reload off filter_type "Single_Rate" rate_change_type "Integer" interpolation_rate "1" decimation_rate "1" zero_pack_factor "1" channel_sequence "Basic" number_channels "1" pattern_list "'P4-0,P4-1,P4-2,P4-3,P4-4'" number_paths "2" infoedit "Maximum Possible : Maximizes oversampling rate. Abstracted input handshake (no s_data_tvalid) and" " automatic rate propagation.
Hardware Oversampling Rate : Specifies oversampling rate relative to the input s" "ample period. Abstracted input handshake (no s_data_tvalid) and automatic rate propagation.
Sample Period : S" "pecifies absolute oversampling rate. No input handshake abstraction (exposes s_data_tvalid) and no rate propagat" "ion." ratespecification "Sample_Period" sampleperiod "1" hardwareoversamplingrate "1" coefficient_sign "Signed" quantization "Maximize_Dynamic_Range" coefficient_width "16" bestprecision on coefficient_fractional_bits "15" coefficient_structure "Inferred" output_rounding_mode "Non_Symmetric_Rounding_Down" output_width "24" xl_use_area off xl_area "[0,0,0,0,0,0,0]" filter_architecture "Systolic_Multiply_Accumulate" optimization_goal "Area" data_buffer_type "Automatic" coefficient_buffer_type "Automatic" input_buffer_type "Automatic" output_buffer_type "Automatic" preference_for_other_storage "Automatic" multi_column_support "Automatic" columnconfig "'20'" inter_column_pipe_length "4" data_has_tlast "Not_Required" m_data_has_tready off s_data_has_fifo off s_data_has_tuser "Not_Required" m_data_has_tuser "Not_Required" s_config_sync_mode "On_Vector" s_config_method "Single" num_reload_slots "1" has_aclken off has_aresetn off infoeditControl "ARESETn must be asserted for a minimum of 2 cycles" trim_axipin_name on passband_min "0.0" passband_max "0.5" stopband_min "0.5" stopband_max "1.0" filter_selection "1" gui_behaviour "Sysgen_GUI" data_sign "Signed" data_width "16" data_fractional_bits "0" data_tuser_width "1" wrapper_available "true" ip_wrap_arbitrary_binary_point "true" ip_name "FIR Compiler" ip_version "6.3" dsptool_ready "true" ipcore_usecache "true" ipcore_useipmodelcache "true" ipcore_xco_need_fpga_part "true" port_translation_map "{ 'aclken' => 'en', 'aresetn' => 'rst' }" run_core_at_system_period "true" ipcore_fpga_part "xlipgetpartsetting(gcb, {'virtex6', 'xc6vlx75t', '-3', 'ff784'})" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "fir_compiler_v6_3" sg_icon_stat "190,154,3,4,white,blue,0,418fbde3,right,,[2 2 2 ],[2 3 3 3 ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 0 3 3 ],[144 10 10 144 ],[5.466667e-0" "01 5.800000e-001 6.400000e-001 ]);\npatch([187 187 190 190 ],[151 123 123 151 ],[5.466667e-001 5.800000e-001 6.4" "00000e-001 ]);\npatch([187 187 190 190 ],[111 3 3 111 ],[3.233333e-001 3.400000e-001 3.700000e-001 ]);\npatch([3" " 186 186 3 3 ],[0 0 154 154 0 ],[7.700000e-001 8.200000e-001 9.100000e-001 ]);\nplot([3 186 186 3 3 ],[0 0 154 1" "54 0 ]);\n\n\npatch([46.05 77.84 99.84 121.84 143.84 99.84 68.05 46.05 ],[101.42 101.42 123.42 101.42 123.42 123" ".42 123.42 101.42 ],[1 1 1 ]);\npatch([68.05 99.84 77.84 46.05 68.05 ],[79.42 79.42 101.42 101.42 79.42 ],[0.931" " 0.946 0.973 ]);\npatch([46.05 77.84 99.84 68.05 46.05 ],[57.42 57.42 79.42 79.42 57.42 ],[1 1 1 ]);\npatch([68." "05 143.84 121.84 99.84 77.84 46.05 68.05 ],[35.42 35.42 57.42 35.42 57.42 57.42 35.42 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i" "nput',1,' data_tvalid ');\ncolor('black');port_label('input',2,' data_tdata_path1 ');\ncolor('black');port_l" "abel('input',3,' data_tdata_path0 ');\ncolor('black');port_label('output',1,' data_tready ');\ncolor('black'" ");port_label('output',2,' data_tvalid ');\ncolor('black');port_label('output',3,' data_tdata_path1 ');\ncolo" "r('black');port_label('output',4,' data_tdata_path0 ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Valid Out" SID "17897" Position [800, 378, 830, 392] IconDisplay "Port number" } Block { BlockType Outport Name "Despread I" SID "17901" Position [800, 418, 830, 432] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "Despread Q" SID "17899" Position [800, 458, 830, 472] Port "3" IconDisplay "Port number" } Line { SrcBlock "IQ Valid In" SrcPort 1 DstBlock "FIR Compiler 6.3 " DstPort 1 } Line { SrcBlock "Rx I" SrcPort 1 DstBlock "FIR Compiler 6.3 " DstPort 2 } Line { SrcBlock "Rx Q" SrcPort 1 DstBlock "FIR Compiler 6.3 " DstPort 3 } Line { SrcBlock "FIR Compiler 6.3 " SrcPort 2 DstBlock "Valid Out" DstPort 1 } Line { SrcBlock "FIR Compiler 6.3 " SrcPort 3 DstBlock "Despread I" DstPort 1 } Line { SrcBlock "FIR Compiler 6.3 " SrcPort 4 DstBlock "Despread Q" DstPort 1 } } } Block { BlockType Reference Name "Gateway Out1" SID "16683" Ports [1, 1] Position [1455, 89, 1490, 101] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Rx I" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out10" SID "17398" Ports [1, 1] Position [1455, 229, 1490, 241] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Conj Mult Q" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out11" SID "17887" Ports [1, 1] Position [1280, 804, 1315, 816] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "Gateway Out2" SID "16684" Ports [1, 1] Position [1455, 109, 1490, 121] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Rx Q" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "16685" Ports [1, 1] Position [1455, 149, 1490, 161] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Filt Vout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "16686" Ports [1, 1] Position [1455, 169, 1490, 181] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Filt I" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "16687" Ports [1, 1] Position [1455, 189, 1490, 201] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Filt Q" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "16688" Ports [1, 1] Position [1455, 209, 1490, 221] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Conj Mult I" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "16689" Ports [1, 1] Position [1455, 249, 1490, 261] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Bit Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "16690" Ports [1, 1] Position [1455, 129, 1490, 141] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Rx IQ Valid" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out9" SID "16691" Ports [1, 1] Position [1455, 269, 1490, 281] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Abs Mag" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Register" SID "16692" Ports [2, 1] Position [1345, 237, 1390, 273] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "45,36,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 36 36 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 36 36 0 ]);\npatch([10.875 18.1 23.1 28.1 33.1 23.1 15.875 10.875 ],[23.55 23.55 2" "8.55 23.55 28.55 28.55 28.55 23.55 ],[1 1 1 ]);\npatch([15.875 23.1 18.1 10.875 15.875 ],[18.55 18.55 23.55 23.55 " "18.55 ],[0.931 0.946 0.973 ]);\npatch([10.875 18.1 23.1 15.875 10.875 ],[13.55 13.55 18.55 18.55 13.55 ],[1 1 1 ])" ";\npatch([15.875 33.1 28.1 23.1 18.1 10.875 15.875 ],[8.55 8.55 13.55 8.55 13.55 13.55 8.55 ],[0.931 0.946 0.973 ]" ");\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label(" "'input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\ncolor('bl" "ack');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "16693" Ports [2, 1] Position [135, 427, 180, 463] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "45,36,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 36 36 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 36 36 0 ]);\npatch([10.875 18.1 23.1 28.1 33.1 23.1 15.875 10.875 ],[23.55 23.55 2" "8.55 23.55 28.55 28.55 28.55 23.55 ],[1 1 1 ]);\npatch([15.875 23.1 18.1 10.875 15.875 ],[18.55 18.55 23.55 23.55 " "18.55 ],[0.931 0.946 0.973 ]);\npatch([10.875 18.1 23.1 15.875 10.875 ],[13.55 13.55 18.55 18.55 13.55 ],[1 1 1 ])" ";\npatch([15.875 33.1 28.1 23.1 18.1 10.875 15.875 ],[8.55 8.55 13.55 8.55 13.55 13.55 8.55 ],[0.931 0.946 0.973 ]" ");\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label(" "'input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\ncolor('bl" "ack');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "16694" Ports [2, 1] Position [940, 377, 985, 413] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "45,36,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 36 36 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 36 36 0 ]);\npatch([10.875 18.1 23.1 28.1 33.1 23.1 15.875 10.875 ],[23.55 23.55 2" "8.55 23.55 28.55 28.55 28.55 23.55 ],[1 1 1 ]);\npatch([15.875 23.1 18.1 10.875 15.875 ],[18.55 18.55 23.55 23.55 " "18.55 ],[0.931 0.946 0.973 ]);\npatch([10.875 18.1 23.1 15.875 10.875 ],[13.55 13.55 18.55 18.55 13.55 ],[1 1 1 ])" ";\npatch([15.875 33.1 28.1 23.1 18.1 10.875 15.875 ],[8.55 8.55 13.55 8.55 13.55 13.55 8.55 ],[0.931 0.946 0.973 ]" ");\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label(" "'input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\ncolor('bl" "ack');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register3" SID "16695" Ports [2, 1] Position [940, 417, 985, 453] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "45,36,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 36 36 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 36 36 0 ]);\npatch([10.875 18.1 23.1 28.1 33.1 23.1 15.875 10.875 ],[23.55 23.55 2" "8.55 23.55 28.55 28.55 28.55 23.55 ],[1 1 1 ]);\npatch([15.875 23.1 18.1 10.875 15.875 ],[18.55 18.55 23.55 23.55 " "18.55 ],[0.931 0.946 0.973 ]);\npatch([10.875 18.1 23.1 15.875 10.875 ],[13.55 13.55 18.55 18.55 13.55 ],[1 1 1 ])" ";\npatch([15.875 33.1 28.1 23.1 18.1 10.875 15.875 ],[8.55 8.55 13.55 8.55 13.55 13.55 8.55 ],[0.931 0.946 0.973 ]" ");\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label(" "'input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\ncolor('bl" "ack');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register4" SID "16696" Ports [2, 1] Position [940, 457, 985, 493] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "45,36,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 36 36 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 36 36 0 ]);\npatch([10.875 18.1 23.1 28.1 33.1 23.1 15.875 10.875 ],[23.55 23.55 2" "8.55 23.55 28.55 28.55 28.55 23.55 ],[1 1 1 ]);\npatch([15.875 23.1 18.1 10.875 15.875 ],[18.55 18.55 23.55 23.55 " "18.55 ],[0.931 0.946 0.973 ]);\npatch([10.875 18.1 23.1 15.875 10.875 ],[13.55 13.55 18.55 18.55 13.55 ],[1 1 1 ])" ";\npatch([15.875 33.1 28.1 23.1 18.1 10.875 15.875 ],[8.55 8.55 13.55 8.55 13.55 13.55 8.55 ],[0.931 0.946 0.973 ]" ");\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label(" "'input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\ncolor('bl" "ack');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register5" SID "16697" Ports [2, 1] Position [940, 497, 985, 533] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "45,36,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 36 36 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 36 36 0 ]);\npatch([10.875 18.1 23.1 28.1 33.1 23.1 15.875 10.875 ],[23.55 23.55 2" "8.55 23.55 28.55 28.55 28.55 23.55 ],[1 1 1 ]);\npatch([15.875 23.1 18.1 10.875 15.875 ],[18.55 18.55 23.55 23.55 " "18.55 ],[0.931 0.946 0.973 ]);\npatch([10.875 18.1 23.1 15.875 10.875 ],[13.55 13.55 18.55 18.55 13.55 ],[1 1 1 ])" ";\npatch([15.875 33.1 28.1 23.1 18.1 10.875 15.875 ],[8.55 8.55 13.55 8.55 13.55 13.55 8.55 ],[0.931 0.946 0.973 ]" ");\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label(" "'input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\ncolor('bl" "ack');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register6" SID "16698" Ports [2, 1] Position [135, 477, 180, 513] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "45,36,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 36 36 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 36 36 0 ]);\npatch([10.875 18.1 23.1 28.1 33.1 23.1 15.875 10.875 ],[23.55 23.55 2" "8.55 23.55 28.55 28.55 28.55 23.55 ],[1 1 1 ]);\npatch([15.875 23.1 18.1 10.875 15.875 ],[18.55 18.55 23.55 23.55 " "18.55 ],[0.931 0.946 0.973 ]);\npatch([10.875 18.1 23.1 15.875 10.875 ],[13.55 13.55 18.55 18.55 13.55 ],[1 1 1 ])" ";\npatch([15.875 33.1 28.1 23.1 18.1 10.875 15.875 ],[8.55 8.55 13.55 8.55 13.55 13.55 8.55 ],[0.931 0.946 0.973 ]" ");\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label(" "'input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\ncolor('bl" "ack');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Sym to Bits" SID "17368" Ports [4, 2] Position [1185, 332, 1255, 603] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Sym to Bits" Location [1302, 497, 1683, 750] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Sym Valid" SID "17395" Position [825, 178, 855, 192] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "I" SID "17372" Position [210, 328, 240, 342] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "Q" SID "17374" Position [210, 398, 240, 412] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "Mod Sel" SID "17375" Position [210, 58, 240, 72] NamePlacement "alternate" Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "Absolute" SID "17381" Ports [1, 1] Position [375, 194, 415, 236] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Absolute" SourceType "Xilinx Absolute Block Block" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "abs" sg_icon_stat "40,42,1,1,white,blue,0,c9bc0535,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 42 42 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 42 42 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[26.55 26." "55 31.55 26.55 31.55 31.55 31.55 26.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[21.55 21.55 26.55 2" "6.55 21.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[16.55 16.55 21.55 21.55 16.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[11.55 11.55 16.55 11.55 16.55 16.55 11.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('output',1,'|a|');\ncolor('black');disp('\\bf{|x|}','texm" "ode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Absolute1" SID "17382" Ports [1, 1] Position [375, 244, 415, 286] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Absolute" SourceType "Xilinx Absolute Block Block" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "abs" sg_icon_stat "40,42,1,1,white,blue,0,c9bc0535,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 42 42 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 42 42 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[26.55 26." "55 31.55 26.55 31.55 31.55 31.55 26.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[21.55 21.55 26.55 2" "6.55 21.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[16.55 16.55 21.55 21.55 16.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[11.55 11.55 16.55 11.55 16.55 16.55 11.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('output',1,'|a|');\ncolor('black');disp('\\bf{|x|}','texm" "ode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Concat" SID "17388" Ports [2, 1] Position [635, 495, 670, 530] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point " "at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "35,35,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 35 35 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 35 35 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[22.55 22." "55 27.55 22.55 27.55 27.55 27.55 22.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[17.55 17.55 22.55 2" "2.55 17.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[12.55 12.55 17.55 17.55 12.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[7.55 7.55 12.55 7.55 12.55 12.55 7.55 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');por" "t_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fontsize{20}\\}'," "'texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Concat1" SID "17391" Ports [2, 1] Position [635, 576, 670, 609] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point " "at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "35,33,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 33 33 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 33 33 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[20.44 20.4" "4 24.44 20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[16.44 16.44 20.44 20.44 " "16.44 ],[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1 1 1 ]);\np" "atch([12.1 25.88 21.88 17.88 13.88 8.1 12.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('in" "put',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fontsize{20}\\}','texmode','" "on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant" SID "16676" Ports [0, 1] Position [425, 354, 455, 376] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,22,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 22 22 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[14.3" "3 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[11.33 11.33 " "14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[8.33 8.33 11.33 11.33 8.33 " "],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('blac" "k');port_label('output',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant1" SID "17386" Ports [0, 1] Position [640, 554, 670, 576] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,22,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 22 22 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[14.3" "3 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[11.33 11.33 " "14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[8.33 8.33 11.33 11.33 8.33 " "],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('blac" "k');port_label('output',1,'1');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant2" SID "17389" Ports [0, 1] Position [425, 424, 455, 446] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,22,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 22 22 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[14.3" "3 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[11.33 11.33 " "14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[8.33 8.33 11.33 11.33 8.33 " "],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('blac" "k');port_label('output',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay1" SID "17397" Ports [1, 1] Position [925, 221, 955, 249] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "30,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 18.4" "4 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 18.44 " "14.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\np" "atch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-" "1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical" SID "17377" Ports [2, 1] Position [715, 550, 770, 610] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "XOR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "55,60,2,1,white,blue,0,dc21e094,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 60 60 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ],[37" ".77 37.77 44.77 37.77 44.77 44.77 44.77 37.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[30.77 30." "77 37.77 37.77 30.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[23.77 23.77 30.77 30.7" "7 23.77 ],[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[16.77 16.77 23.77 16.77 23.77 23.77" " 16.77 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text" "');\n\n\n\ncolor('black');disp('xor');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "17396" Ports [2, 1] Position [1000, 195, 1035, 250] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,55,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 55 55 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 55 55 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[32.55 32." "55 37.55 32.55 37.55 37.55 37.55 32.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[27.55 27.55 32.55 3" "2.55 27.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[22.55 22.55 27.55 27.55 22.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[17.55 17.55 22.55 17.55 22.55 22.55 17.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('b" "lack');disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux" SID "17376" Ports [3, 1] Position [1130, 289, 1165, 411] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "1" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "35,122,3,1,white,blue,3,a150fb03,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 17.4286 104.571 122 0 " "],[0.77 0.82 0.91 ]);\nplot([0 35 35 0 0 ],[0 17.4286 104.571 122 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 1" "0.875 5.875 ],[66.55 66.55 71.55 66.55 71.55 71.55 71.55 66.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.87" "5 ],[61.55 61.55 66.55 66.55 61.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[56.55 56.55 " "61.55 61.55 56.55 ],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[51.55 51.55 56.55 51.55 56.55 " "56.55 51.55 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon" " text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black'" ");port_label('input',3,'d1');\n\ncolor('black');disp('\\bf{ z^{-1}}','texmode','on');\nfprintf('','COMMENT: end" " icon text');" } Block { BlockType Reference Name "Mux1" SID "17379" Ports [3, 1] Position [1130, 124, 1165, 246] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "1" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "35,122,3,1,white,blue,3,a150fb03,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 17.4286 104.571 122 0 " "],[0.77 0.82 0.91 ]);\nplot([0 35 35 0 0 ],[0 17.4286 104.571 122 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 1" "0.875 5.875 ],[66.55 66.55 71.55 66.55 71.55 71.55 71.55 66.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.87" "5 ],[61.55 61.55 66.55 66.55 61.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[56.55 56.55 " "61.55 61.55 56.55 ],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[51.55 51.55 56.55 51.55 56.55 " "56.55 51.55 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon" " text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black'" ");port_label('input',3,'d1');\n\ncolor('black');disp('\\bf{ z^{-1}}','texmode','on');\nfprintf('','COMMENT: end" " icon text');" } Block { BlockType Reference Name "Mux2" SID "17384" Ports [3, 1] Position [820, 414, 860, 616] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "40,202,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 28.8571 173.143 202 0 " "],[0.77 0.82 0.91 ]);\nplot([0 40 40 0 0 ],[0 28.8571 173.143 202 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 1" "3.875 8.875 ],[106.55 106.55 111.55 106.55 111.55 111.55 111.55 106.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.8" "75 13.875 ],[101.55 101.55 106.55 106.55 101.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ]," "[96.55 96.55 101.55 101.55 96.55 ],[1 1 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[91.55 91.55 96." "55 91.55 96.55 96.55 91.55 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMM" "ENT: begin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');" "\ncolor('black');port_label('input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMME" "NT: end icon text');" } Block { BlockType Reference Name "Mux3" SID "17392" Ports [3, 1] Position [1015, 371, 1050, 499] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "35,128,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 18.2857 109.714 128 0 " "],[0.77 0.82 0.91 ]);\nplot([0 35 35 0 0 ],[0 18.2857 109.714 128 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 1" "0.875 5.875 ],[69.55 69.55 74.55 69.55 74.55 74.55 74.55 69.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.87" "5 ],[64.55 64.55 69.55 69.55 64.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[59.55 59.55 " "64.55 64.55 59.55 ],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[54.55 54.55 59.55 54.55 59.55 " "59.55 54.55 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon" " text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black'" ");port_label('input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon te" "xt');" } Block { BlockType Reference Name "Relational" SID "16699" Ports [2, 1] Position [500, 322, 555, 378] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a<=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "55,56,2,1,white,blue,0,52e4b236,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 56 56 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 56 56 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ],[35" ".77 35.77 42.77 35.77 42.77 42.77 42.77 35.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[28.77 28." "77 35.77 35.77 28.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[21.77 21.77 28.77 28.7" "7 21.77 ],[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[14.77 14.77 21.77 14.77 21.77 21.77" " 14.77 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text" "');\ncolor('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_l" "abel('output',1,'\\bfa \\leq b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text'" ");" } Block { BlockType Reference Name "Relational1" SID "17383" Ports [2, 1] Position [505, 188, 545, 292] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "aHardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "25,20,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 20 20 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 20 20 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[12.22 12" ".22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[10.22 10.22 12.22 12." "22 10.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\n" "patch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('o" "utput',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b1" SID "17394" Ports [1, 1] Position [940, 465, 965, 485] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "1" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "25,20,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 20 20 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 20 20 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[12.22 12" ".22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[10.22 10.22 12.22 12." "22 10.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\n" "patch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('o" "utput',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Bit Valid" SID "17371" Position [1315, 178, 1345, 192] IconDisplay "Port number" } Block { BlockType Outport Name "Bit" SID "17373" Position [1315, 343, 1345, 357] Port "2" IconDisplay "Port number" } Line { SrcBlock "Constant" SrcPort 1 DstBlock "Relational" DstPort 2 } Line { SrcBlock "Relational" SrcPort 1 Points [25, 0] Branch { DstBlock "Mux" DstPort 2 } Branch { Points [0, 155] Branch { DstBlock "Concat" DstPort 1 } Branch { Points [0, 15] DstBlock "Concat" DstPort 2 } } } Line { SrcBlock "Mod Sel" SrcPort 1 Points [420, 0; 0, 80] Branch { Points [0, 165] DstBlock "Mux" DstPort 1 } Branch { DstBlock "Mux1" DstPort 1 } } Line { SrcBlock "I" SrcPort 1 Points [30, 0] Branch { DstBlock "Relational" DstPort 1 } Branch { Points [0, -120] DstBlock "Absolute" DstPort 1 } } Line { SrcBlock "Mux" SrcPort 1 DstBlock "Bit" DstPort 1 } Line { SrcBlock "Mux1" SrcPort 1 DstBlock "Bit Valid" DstPort 1 } Line { SrcBlock "Absolute" SrcPort 1 DstBlock "Relational1" DstPort 1 } Line { SrcBlock "Absolute1" SrcPort 1 DstBlock "Relational1" DstPort 2 } Line { SrcBlock "Constant2" SrcPort 1 DstBlock "Relational2" DstPort 2 } Line { SrcBlock "Q" SrcPort 1 Points [40, 0] Branch { DstBlock "Relational2" DstPort 1 } Branch { Points [0, -140] DstBlock "Absolute1" DstPort 1 } } Line { SrcBlock "Relational2" SrcPort 1 Points [15, 0; 0, 165] Branch { DstBlock "Concat1" DstPort 1 } Branch { Points [0, 15] DstBlock "Concat1" DstPort 2 } } Line { SrcBlock "Concat1" SrcPort 1 DstBlock "Logical" DstPort 2 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Logical" DstPort 1 } Line { SrcBlock "Logical" SrcPort 1 DstBlock "Mux2" DstPort 3 } Line { SrcBlock "Concat" SrcPort 1 DstBlock "Mux2" DstPort 2 } Line { SrcBlock "Relational1" SrcPort 1 Points [55, 0; 0, 210] DstBlock "Mux2" DstPort 1 } Line { SrcBlock "Sym Valid" SrcPort 1 Points [35, 0] Branch { DstBlock "Mux1" DstPort 2 } Branch { Points [0, 25] Branch { Points [0, 25] DstBlock "Delay1" DstPort 1 } Branch { DstBlock "Logical1" DstPort 1 } } } Line { SrcBlock "Delay1" SrcPort 1 Points [10, 0] Branch { DstBlock "Logical1" DstPort 2 } Branch { Points [0, 160] DstBlock "Mux3" DstPort 1 } } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Mux1" DstPort 3 } Line { SrcBlock "b0" SrcPort 1 DstBlock "Mux3" DstPort 2 } Line { SrcBlock "Mux2" SrcPort 1 Points [40, 0; 0, -40] Branch { DstBlock "b1" DstPort 1 } Branch { Points [0, -40] DstBlock "b0" DstPort 1 } } Line { SrcBlock "b1" SrcPort 1 DstBlock "Mux3" DstPort 3 } Line { SrcBlock "Mux3" SrcPort 1 Points [30, 0; 0, -50] DstBlock "Mux" DstPort 3 } } } Block { BlockType ToWorkspace Name "To Workspace" SID "17885" Ports [1] Position [1380, 795, 1440, 825] ZOrder -7 VariableName "despread_mag" MaxDataPoints "inf" Decimation "8" SampleTime "-1" SaveFormat "Array" } Block { BlockType Reference Name "Up Sample" SID "16700" Ports [1, 1] Position [140, 361, 175, 399] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Up Sample" SourceType "Xilinx Up Sampler Block" infoedit "Up samples input data. Inserted values can be zeros or copies of the most recent input sample.
<" "br>Hardware notes: No hardware is needed if inserted values are copies of the input sample; otherwise, a mux and s" "ingle bit flip-flop are used." sample_ratio "8" copy_samples off en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "usamp" sg_icon_stat "35,38,1,1,white,blue,0,8c255cf7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 38 38 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 38 38 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[24.55 24.55 29." "55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[19.55 19.55 24.55 24.55 19." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('{\\font" "size{14pt}\\bf\\uparrow}8','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Valid" SID "16701" Position [1380, 393, 1410, 407] IconDisplay "Port number" } Block { BlockType Outport Name "Bit" SID "16702" Position [1380, 528, 1410, 542] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "IQ Mag" SID "16703" Position [1380, 718, 1410, 732] Port "3" IconDisplay "Port number" } Line { SrcBlock "Despread Filter" SrcPort 1 Points [110, 0; 0, 20; 70, 0] Branch { Points [0, 60] Branch { DstBlock "Delay" DstPort 2 } Branch { Points [0, 40] DstBlock "Delay1" DstPort 2 } } Branch { Points [260, 0] Branch { DstBlock "Register2" DstPort 2 } Branch { Points [0, 30] Branch { DstBlock "Register3" DstPort 2 } Branch { Points [0, 40] Branch { DstBlock "Register4" DstPort 2 } Branch { DstBlock "Register5" DstPort 2 } } } } Branch { Points [0, -60] Branch { Points [0, -200] DstBlock "Gateway Out3" DstPort 1 } Branch { DstBlock "Delay2" DstPort 1 } } } Line { SrcBlock "Conj Mult" SrcPort 2 Points [30, 0] Branch { Points [0, -220] DstBlock "Gateway Out6" DstPort 1 } Branch { DstBlock "Sym to Bits" DstPort 2 } } Line { SrcBlock "Up Sample" SrcPort 1 Points [45, 0; 0, 15; 40, 0] Branch { Points [0, -260] DstBlock "Gateway Out8" DstPort 1 } Branch { Labels [0, 0] DstBlock "Despread Filter" DstPort 1 } } Line { SrcBlock "Register1" SrcPort 1 Points [75, 0] Branch { Points [0, -350] DstBlock "Gateway Out1" DstPort 1 } Branch { Labels [0, 0] DstBlock "Despread Filter" DstPort 2 } } Line { SrcBlock "Register2" SrcPort 1 Points [15, 0] Branch { DstBlock "Conj Mult" DstPort 2 } Branch { Points [0, 280] DstBlock "Abs Mag" DstPort 2 } } Line { SrcBlock "Register3" SrcPort 1 Points [10, 0] Branch { DstBlock "Conj Mult" DstPort 3 } Branch { Points [0, 270] DstBlock "Abs Mag" DstPort 3 } } Line { SrcBlock "Register4" SrcPort 1 DstBlock "Conj Mult" DstPort 4 } Line { SrcBlock "Register5" SrcPort 1 DstBlock "Conj Mult" DstPort 5 } Line { SrcBlock "Delay" SrcPort 1 DstBlock "Register4" DstPort 1 } Line { SrcBlock "Delay1" SrcPort 1 DstBlock "Register5" DstPort 1 } Line { SrcBlock "Delay2" SrcPort 1 Points [30, 0] Branch { DstBlock "Conj Mult" DstPort 1 } Branch { Points [0, 290] DstBlock "Abs Mag" DstPort 1 } } Line { Name "Rx I" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 DstBlock "Demod" DstPort 1 } Line { Name "Rx Q" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 DstBlock "Demod" DstPort 2 } Line { Name "Filt Vout" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 DstBlock "Demod" DstPort 4 } Line { Name "Filt I" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 DstBlock "Demod" DstPort 5 } Line { Name "Filt Q" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 DstBlock "Demod" DstPort 6 } Line { Name "Conj Mult I" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 DstBlock "Demod" DstPort 7 } Line { Name "Bit Out" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 DstBlock "Demod" DstPort 9 } Line { SrcBlock "Register" SrcPort 1 DstBlock "Gateway Out7" DstPort 1 } Line { Name "Rx IQ Valid" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 DstBlock "Demod" DstPort 3 } Line { SrcBlock "Abs Mag" SrcPort 2 Points [35, 0] Branch { DstBlock "Delay3" DstPort 1 } Branch { Points [0, 100] DstBlock "Delay4" DstPort 1 } } Line { Name "Abs Mag" Labels [0, 0] SrcBlock "Gateway Out9" SrcPort 1 DstBlock "Demod" DstPort 10 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Up Sample" DstPort 1 } Line { SrcBlock "IQ Valid" SrcPort 1 Points [60, 0] Branch { DstBlock "Register1" DstPort 2 } Branch { Points [0, 50] DstBlock "Register6" DstPort 2 } } Line { SrcBlock "Rx I" SrcPort 1 DstBlock "Register1" DstPort 1 } Line { SrcBlock "Register6" SrcPort 1 Points [70, 0] Branch { Points [0, -380] DstBlock "Gateway Out2" DstPort 1 } Branch { Labels [0, 0] DstBlock "Despread Filter" DstPort 3 } } Line { SrcBlock "Rx Q" SrcPort 1 DstBlock "Register6" DstPort 1 } Line { SrcBlock "Sym to Bits" SrcPort 1 Points [40, 0] Branch { DstBlock "Valid" DstPort 1 } Branch { Points [0, -135] DstBlock "Register" DstPort 2 } } Line { SrcBlock "Sym to Bits" SrcPort 2 Points [35, 0] Branch { DstBlock "Bit" DstPort 1 } Branch { Points [0, -290] DstBlock "Register" DstPort 1 } } Line { SrcBlock "Delay3" SrcPort 1 Points [30, 0] Branch { Points [35, 0] Branch { Points [115, 0; 0, -425] DstBlock "Gateway Out9" DstPort 1 } Branch { Points [0, 25] DstBlock "IQ Mag" DstPort 1 } } Branch { Points [0, 75; 35, 0] } } Line { Name "Conj Mult Q" Labels [0, 0] SrcBlock "Gateway Out10" SrcPort 1 DstBlock "Demod" DstPort 8 } Line { SrcBlock "Conj Mult" SrcPort 3 Points [40, 0] Branch { Points [0, -265] DstBlock "Gateway Out10" DstPort 1 } Branch { DstBlock "Sym to Bits" DstPort 3 } } Line { SrcBlock "Conj Mult" SrcPort 1 DstBlock "Sym to Bits" DstPort 1 } Line { SrcBlock "Mod Sel" SrcPort 1 Points [35, 0; 0, -20] DstBlock "Sym to Bits" DstPort 4 } Line { SrcBlock "Abs Mag" SrcPort 1 Points [70, 0; 0, 160] DstBlock "Delay4" DstPort 2 } Line { SrcBlock "Delay4" SrcPort 1 DstBlock "Gateway Out11" DstPort 1 } Line { SrcBlock "Gateway Out11" SrcPort 1 DstBlock "To Workspace" DstPort 1 } Line { SrcBlock "Despread Filter" SrcPort 2 Points [80, 0; 0, 10; 130, 0] Branch { Points [0, -70] Branch { Points [0, -210] DstBlock "Gateway Out4" DstPort 1 } Branch { DstBlock "Register2" DstPort 1 } } Branch { DstBlock "Delay" DstPort 1 } } Line { SrcBlock "Despread Filter" SrcPort 3 Points [215, 0] Branch { Points [0, -70] Branch { Points [0, -230] DstBlock "Gateway Out5" DstPort 1 } Branch { DstBlock "Register3" DstPort 1 } } Branch { DstBlock "Delay1" DstPort 1 } } Annotation { Name "Re-capture the IQ samples here using\na 1-in-8 pulse whose phase is aligned\nto the free-running counter" "s in the\ndownstream matching logic. This is safe\nhere since the DSSS Rx only supports\n20MSps mode (160/8), so e" "ffectively\nignoring the rate of the IQ Valid input\nis ok at this stage." Position [112, 605] } } } Block { BlockType SubSystem Name "Descramble" SID "16704" Ports [2, 2] Position [595, 541, 685, 599] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Descramble" Location [2, 70, 1830, 1180] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Bit" SID "16705" Position [465, 528, 495, 542] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "Bit Valid" SID "16706" Position [440, 723, 470, 737] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Convert" SID "16707" Ports [1, 1] Position [520, 695, 545, 715] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "16" bin_pt "14" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,20,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 20 20 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[12.22 12.22 14" ".22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[10.22 10.22 12.22 12.22 10.22" " ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatch([9." "55 16.44 14.44 12.44 10.44 7.55 9.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cas" "t');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "16708" Ports [1, 1] Position [520, 720, 545, 740] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "16" bin_pt "14" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,20,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 20 20 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[12.22 12.22 14" ".22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[10.22 10.22 12.22 12.22 10.22" " ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatch([9." "55 16.44 14.44 12.44 10.44 7.55 9.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cas" "t');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "16709" Ports [1, 1] Position [670, 371, 700, 389] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "30,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 18 18 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[11.22 11.22" " 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[9.22 9.22 11.22 11.22 9" ".22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch" "([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output'" ",1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "16710" Position [360, 694, 470, 716] ZOrder -9 ShowName off GotoTag "DSSS_RX_RESET" TagVisibility "global" } Block { BlockType Reference Name "Logical" SID "16711" Ports [2, 1] Position [790, 453, 835, 497] BlockMirror on NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "XOR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,2,1,white,blue,0,dc21e094,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 28.66 3" "4.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 28.66 22" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('" "xor');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "16712" Ports [2, 1] Position [558, 415, 602, 460] BlockRotation 270 ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "XOR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "44,45,2,1,white,blue,0,dc21e094,up,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 44 44 0 0 ],[0 0 45 45 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 44 44 0 0 ],[0 0 45 45 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 28.66 3" "4.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 28.66 22" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('" "xor');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register" SID "16713" Ports [3, 1] Position [615, 526, 660, 574] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "1" rst on en on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 30.66 3" "6.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 30.66 24" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('" "input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'en');\ncolor('bl" "ack');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon te" "xt');" } Block { BlockType Reference Name "Register1" SID "16714" Ports [3, 1] Position [700, 526, 745, 574] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "1" rst on en on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 30.66 3" "6.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 30.66 24" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('" "input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'en');\ncolor('bl" "ack');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon te" "xt');" } Block { BlockType Reference Name "Register2" SID "16715" Ports [3, 1] Position [790, 526, 835, 574] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "1" rst on en on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 30.66 3" "6.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 30.66 24" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('" "input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'en');\ncolor('bl" "ack');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon te" "xt');" } Block { BlockType Reference Name "Register3" SID "16716" Ports [3, 1] Position [880, 526, 925, 574] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "1" rst on en on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 30.66 3" "6.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 30.66 24" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('" "input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'en');\ncolor('bl" "ack');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon te" "xt');" } Block { BlockType Reference Name "Register4" SID "16717" Ports [3, 1] Position [1040, 526, 1085, 574] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "1" rst on en on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 30.66 3" "6.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 30.66 24" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('" "input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'en');\ncolor('bl" "ack');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon te" "xt');" } Block { BlockType Reference Name "Register5" SID "16718" Ports [3, 1] Position [1130, 526, 1175, 574] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "1" rst on en on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 30.66 3" "6.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 30.66 24" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('" "input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'en');\ncolor('bl" "ack');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon te" "xt');" } Block { BlockType Reference Name "Register6" SID "16719" Ports [3, 1] Position [1215, 526, 1260, 574] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "1" rst on en on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 30.66 3" "6.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 30.66 24" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('" "input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'en');\ncolor('bl" "ack');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon te" "xt');" } Block { BlockType Reference Name "Register7" SID "16720" Ports [1, 1] Position [1275, 361, 1315, 399] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "40,38,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 38 38 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 38 38 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[24.55 24.55 29." "55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[19.55 19.55 24.55 24.55 19." "55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1 1 ]);\npa" "tch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input" "',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','" "COMMENT: end icon text');" } Block { BlockType Reference Name "Register8" SID "16721" Ports [1, 1] Position [1280, 711, 1320, 749] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "40,38,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 38 38 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 38 38 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[24.55 24.55 29." "55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[19.55 19.55 24.55 24.55 19." "55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1 1 ]);\npa" "tch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input" "',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','" "COMMENT: end icon text');" } Block { BlockType Outport Name " Bit" SID "16722" Position [1410, 373, 1440, 387] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Outport Name " Bit Valid" SID "16723" Position [1410, 723, 1440, 737] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Line { SrcBlock "Register8" SrcPort 1 DstBlock " Bit Valid" DstPort 1 } Line { SrcBlock "Register7" SrcPort 1 DstBlock " Bit" DstPort 1 } Line { SrcBlock "Logical1" SrcPort 1 Points [0, -30] DstBlock "Convert2" DstPort 1 } Line { SrcBlock "Logical" SrcPort 1 DstBlock "Logical1" DstPort 2 } Line { SrcBlock "Bit" SrcPort 1 Points [70, 0] Branch { DstBlock "Logical1" DstPort 1 } Branch { DstBlock "Register" DstPort 1 } } Line { SrcBlock "Convert2" SrcPort 1 DstBlock "Register7" DstPort 1 } Line { SrcBlock "Convert1" SrcPort 1 Points [40, 0] Branch { Points [0, -165] DstBlock "Register" DstPort 3 } Branch { Points [95, 0] Branch { DstBlock "Register1" DstPort 3 } Branch { Points [80, 0] Branch { Points [0, -165] DstBlock "Register2" DstPort 3 } Branch { Points [100, 0] Branch { DstBlock "Register3" DstPort 3 } Branch { Points [150, 0] Branch { Points [0, -165] DstBlock "Register4" DstPort 3 } Branch { Points [100, 0] Branch { Points [75, 0] Branch { DstBlock "Register8" DstPort 1 } Branch { Points [0, -165] DstBlock "Register6" DstPort 3 } } Branch { DstBlock "Register5" DstPort 3 } } } } } } } Line { SrcBlock "Convert" SrcPort 1 Points [30, 0] Branch { Points [0, -155] DstBlock "Register" DstPort 2 } Branch { Points [95, 0] Branch { Points [0, -155] DstBlock "Register1" DstPort 2 } Branch { Points [80, 0] Branch { Points [0, -155] DstBlock "Register2" DstPort 2 } Branch { Points [100, 0] Branch { Points [0, -155] DstBlock "Register3" DstPort 2 } Branch { Points [150, 0] Branch { Points [0, -155] DstBlock "Register4" DstPort 2 } Branch { Points [100, 0] Branch { Points [80, 0; 0, -155] DstBlock "Register6" DstPort 2 } Branch { Points [0, -155] DstBlock "Register5" DstPort 2 } } } } } } } Line { SrcBlock "Bit Valid" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Register" SrcPort 1 Points [5, 0; 0, -15] DstBlock "Register1" DstPort 1 } Line { Labels [0, 0] SrcBlock "Register1" SrcPort 1 Points [0, -15] DstBlock "Register2" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 Points [10, 0; 0, -15] DstBlock "Register3" DstPort 1 } Line { SrcBlock "Register3" SrcPort 1 Points [45, 0; 0, -15] Branch { Points [0, -50] DstBlock "Logical" DstPort 2 } Branch { DstBlock "Register4" DstPort 1 } } Line { SrcBlock "Register4" SrcPort 1 Points [10, 0; 0, -15] DstBlock "Register5" DstPort 1 } Line { SrcBlock "Register5" SrcPort 1 Points [0, -15] DstBlock "Register6" DstPort 1 } Line { SrcBlock "Register6" SrcPort 1 Points [20, 0; 0, -85] DstBlock "Logical" DstPort 1 } Line { SrcBlock "From" SrcPort 1 DstBlock "Convert" DstPort 1 } Annotation { Position [1263, 566] } } } Block { BlockType Reference Name "Gateway Out1" SID "16724" Ports [1, 1] Position [1180, 129, 1215, 141] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Synced Bit" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "16725" Ports [1, 1] Position [1180, 149, 1215, 161] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Synced Bit Valid" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "16726" Ports [1, 1] Position [1180, 169, 1215, 181] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Descrambled Bit" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "16727" Ports [1, 1] Position [1180, 269, 1215, 281] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Synced" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "16728" Ports [1, 1] Position [1180, 289, 1215, 301] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "SFD Found" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "17407" Ports [1, 1] Position [1325, 539, 1360, 551] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out7" SID "17408" Ports [1, 1] Position [1325, 569, 1360, 581] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Goto Name "Goto" SID "16729" Position [1295, 774, 1425, 796] ZOrder -10 ShowName off GotoTag "DSSS_RX_TIMEOUT" TagVisibility "global" } Block { BlockType SubSystem Name "Header CRC" SID "16730" Ports [2, 1] Position [1160, 371, 1255, 424] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Header CRC" Location [2, 70, 1830, 1180] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "133" Block { BlockType Inport Name "Bit" SID "16731" Position [470, 218, 500, 232] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "Bit Valid" SID "16732" Position [110, 318, 140, 332] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType SubSystem Name "CRC LFSR" SID "16733" Ports [2, 1] Position [610, 212, 695, 263] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "CRC LFSR" Location [397, 418, 2353, 1440] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Bit" SID "16734" Position [30, 393, 60, 407] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "Bit Valid" SID "16735" Position [170, 463, 200, 477] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Concat" SID "16736" Ports [16, 1] Position [248, 205, 1777, 265] BlockRotation 270 LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point " "at zero." num_inputs "16" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "1529,60,16,1,white,blue,0,e51e01c8,up,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 1529 1529 0 0 ],[0 0 60 60 0 ],[0.77 " "0.82 0.91 ]);\nplot([0 1529 1529 0 0 ],[0 0 60 60 0 ]);\npatch([746.2 757.76 765.76 773.76 781.76 765.76 754.2 7" "46.2 ],[38.88 38.88 46.88 38.88 46.88 46.88 46.88 38.88 ],[1 1 1 ]);\npatch([754.2 765.76 757.76 746.2 754.2 ],[" "30.88 30.88 38.88 38.88 30.88 ],[0.931 0.946 0.973 ]);\npatch([746.2 757.76 765.76 754.2 746.2 ],[22.88 22.88 30" ".88 30.88 22.88 ],[1 1 1 ]);\npatch([754.2 781.76 773.76 765.76 757.76 746.2 754.2 ],[14.88 14.88 22.88 14.88 22" ".88 22.88 14.88 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin " "icon text');\ncolor('black');port_label('input',1,'hi');\n\n\n\n\n\n\n\n\n\n\n\n\n\n\ncolor('black');port_label(" "'input',16,'lo');\n\ncolor('black');disp('\\fontsize{20}\\}','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" } Block { BlockType From Name "From3" SID "16737" Position [90, 494, 200, 516] ZOrder -9 ShowName off GotoTag "DSSS_RX_RESET" TagVisibility "global" } Block { BlockType Reference Name "Inverter" SID "16738" Ports [1, 1] Position [1060, 94, 1090, 116] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "30,22,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 22 22 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[14.3" "3 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[11.33 11.33 " "14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[8.33 8.33 11.33 11.33 8.33 " "],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('" "black');disp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical" SID "16739" Ports [2, 1] Position [120, 355, 175, 415] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "XOR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "55,60,2,1,white,blue,0,dc21e094,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 60 60 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ],[37" ".77 37.77 44.77 37.77 44.77 44.77 44.77 37.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[30.77 30." "77 37.77 37.77 30.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[23.77 23.77 30.77 30.7" "7 23.77 ],[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[16.77 16.77 23.77 16.77 23.77 23.77" " 16.77 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text" "');\n\n\n\ncolor('black');disp('xor');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "16740" Ports [2, 1] Position [680, 320, 700, 355] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "XOR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "20,35,2,1,white,blue,0,dc21e094,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 35 35 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 20 20 0 0 ],[0 0 35 35 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[19.22 19." "22 21.22 19.22 21.22 21.22 21.22 19.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[17.22 17.22 19.22 19.22" " 17.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[15.22 15.22 17.22 17.22 15.22 ],[1 1 1 ]);\n" "patch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[13.22 13.22 15.22 13.22 15.22 15.22 13.22 ],[0.931 0.946 0.973 ]" ");\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');dis" "p('xor');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "16741" Ports [2, 1] Position [1335, 315, 1360, 350] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "XOR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "25,35,2,1,white,blue,0,dc21e094,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 35 35 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 35 35 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[20.33 " "20.33 23.33 20.33 23.33 23.33 23.33 20.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[17.33 17.33 20.33" " 20.33 17.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[14.33 14.33 17.33 17.33 14.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[11.33 11.33 14.33 11.33 14.33 14.33 11.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor" "('black');disp('xor');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "16742" Ports [3, 1] Position [245, 376, 290, 424] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "1" rst on en on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Reference Name "Register10" SID "16743" Ports [3, 1] Position [1080, 376, 1125, 424] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "1" rst on en on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Reference Name "Register11" SID "16744" Ports [3, 1] Position [1170, 376, 1215, 424] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "1" rst on en on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Reference Name "Register12" SID "16745" Ports [3, 1] Position [1590, 376, 1635, 424] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "1" rst on en on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Reference Name "Register13" SID "16746" Ports [3, 1] Position [1680, 376, 1725, 424] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "1" rst on en on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Reference Name "Register14" SID "16747" Ports [3, 1] Position [1265, 376, 1310, 424] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "1" rst on en on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Reference Name "Register15" SID "16748" Ports [3, 1] Position [1410, 376, 1455, 424] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "1" rst on en on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Reference Name "Register16" SID "16749" Ports [3, 1] Position [1500, 376, 1545, 424] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "1" rst on en on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "16750" Ports [3, 1] Position [330, 376, 375, 424] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "1" rst on en on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Reference Name "Register3" SID "16751" Ports [3, 1] Position [420, 376, 465, 424] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "1" rst on en on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Reference Name "Register4" SID "16752" Ports [3, 1] Position [510, 376, 555, 424] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "1" rst on en on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Reference Name "Register5" SID "16753" Ports [3, 1] Position [605, 376, 650, 424] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "1" rst on en on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Reference Name "Register6" SID "16754" Ports [3, 1] Position [720, 376, 765, 424] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "1" rst on en on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Reference Name "Register7" SID "16755" Ports [3, 1] Position [810, 376, 855, 424] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "1" rst on en on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Reference Name "Register8" SID "16756" Ports [3, 1] Position [900, 376, 945, 424] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "1" rst on en on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Reference Name "Register9" SID "16757" Ports [3, 1] Position [990, 376, 1035, 424] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "1" rst on en on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Outport Name "CRC16" SID "16758" Position [1175, 96, 1205, 114] IconDisplay "Port number" } Line { SrcBlock "Register1" SrcPort 1 Points [0, -15; 5, 0] Branch { DstBlock "Register2" DstPort 1 } Branch { DstBlock "Concat" DstPort 1 } } Line { SrcBlock "Register2" SrcPort 1 Points [0, -15; 15, 0] Branch { DstBlock "Register3" DstPort 1 } Branch { DstBlock "Concat" DstPort 2 } } Line { SrcBlock "Register3" SrcPort 1 Points [0, -15; 15, 0] Branch { DstBlock "Register4" DstPort 1 } Branch { Points [0, -105] DstBlock "Concat" DstPort 3 } } Line { SrcBlock "Register5" SrcPort 1 Points [0, -15; 10, 0; 0, -20] Branch { DstBlock "Logical1" DstPort 2 } Branch { Points [15, 0] DstBlock "Concat" DstPort 5 } } Line { SrcBlock "Register6" SrcPort 1 Points [0, -15; 5, 0] Branch { DstBlock "Register7" DstPort 1 } Branch { DstBlock "Concat" DstPort 6 } } Line { SrcBlock "Register7" SrcPort 1 Points [0, -15; 10, 0] Branch { DstBlock "Register8" DstPort 1 } Branch { DstBlock "Concat" DstPort 7 } } Line { SrcBlock "Register4" SrcPort 1 Points [5, 0; 0, -15; 15, 0] Branch { DstBlock "Register5" DstPort 1 } Branch { Points [5, 0] DstBlock "Concat" DstPort 4 } } Line { SrcBlock "Bit Valid" SrcPort 1 Points [20, 0] Branch { Points [0, -55] DstBlock "Register1" DstPort 3 } Branch { Points [90, 0] Branch { DstBlock "Register2" DstPort 3 } Branch { Points [90, 0] Branch { DstBlock "Register3" DstPort 3 } Branch { Points [90, 0] Branch { DstBlock "Register4" DstPort 3 } Branch { Points [80, 0] Branch { Points [0, -55] DstBlock "Register5" DstPort 3 } Branch { Points [130, 0] Branch { DstBlock "Register6" DstPort 3 } Branch { Points [90, 0] Branch { DstBlock "Register7" DstPort 3 } Branch { Points [90, 0] Branch { DstBlock "Register8" DstPort 3 } Branch { Points [90, 0] Branch { DstBlock "Register9" DstPort 3 } Branch { Points [90, 0] Branch { DstBlock "Register10" DstPort 3 } Branch { Points [90, 0] Branch { DstBlock "Register11" DstPort 3 } Branch { Points [95, 0] Branch { DstBlock "Register14" DstPort 3 } Branch { Points [90, 0] Branch { Points [0, -55] DstBlock "Register15" DstPort 3 } Branch { Points [145, 0] Branch { DstBlock "Register16" DstPort 3 } Branch { Points [90, 0] Branch { DstBlock "Register12" DstPort 3 } Branch { Points [90, 0] DstBlock "Register13" DstPort 3 } } } } } } } } } } } } } } } } Line { SrcBlock "From3" SrcPort 1 Points [15, 0] Branch { Points [0, -105] DstBlock "Register1" DstPort 2 } Branch { Points [85, 0] Branch { Points [90, 0] Branch { Points [85, 0] Branch { Points [90, 0] Branch { Points [125, 0] Branch { Points [90, 0] Branch { Points [0, -105] DstBlock "Register7" DstPort 2 } Branch { Points [90, 0] Branch { Points [0, -105] DstBlock "Register8" DstPort 2 } Branch { Points [90, 0] Branch { Points [90, 0] Branch { Points [0, -105] DstBlock "Register10" DstPort 2 } Branch { Points [90, 0] Branch { Points [0, -105] DstBlock "Register11" DstPort 2 } Branch { Points [95, 0] Branch { Points [0, -105] DstBlock "Register14" DstPort 2 } Branch { Points [90, 0] Branch { Points [0, -105] DstBlock "Register15" DstPort 2 } Branch { Points [145, 0] Branch { Points [90, 0] Branch { Points [0, -105] DstBlock "Register12" DstPort 2 } Branch { Points [90, 0; 0, -105] DstBlock "Register13" DstPort 2 } } Branch { Points [0, -105] DstBlock "Register16" DstPort 2 } } } } } } Branch { Points [0, -105] DstBlock "Register9" DstPort 2 } } } } Branch { Points [0, -105] DstBlock "Register6" DstPort 2 } } Branch { Points [0, -105] DstBlock "Register5" DstPort 2 } } Branch { Points [0, -105] DstBlock "Register4" DstPort 2 } } Branch { Points [0, -105] DstBlock "Register3" DstPort 2 } } Branch { Points [0, -105] DstBlock "Register2" DstPort 2 } } } Line { SrcBlock "Register8" SrcPort 1 Points [0, -15; 15, 0] Branch { DstBlock "Register9" DstPort 1 } Branch { DstBlock "Concat" DstPort 8 } } Line { SrcBlock "Register9" SrcPort 1 Points [0, -15; 15, 0] Branch { DstBlock "Register10" DstPort 1 } Branch { Points [0, -105] DstBlock "Concat" DstPort 9 } } Line { SrcBlock "Register10" SrcPort 1 Points [0, -15; 15, 0] Branch { DstBlock "Register11" DstPort 1 } Branch { Points [10, 0] DstBlock "Concat" DstPort 10 } } Line { SrcBlock "Bit" SrcPort 1 DstBlock "Logical" DstPort 2 } Line { SrcBlock "Register11" SrcPort 1 Points [0, -15; 5, 0] Branch { DstBlock "Register14" DstPort 1 } Branch { Points [0, -105] DstBlock "Concat" DstPort 11 } } Line { SrcBlock "Register14" SrcPort 1 Points [0, -35] Branch { Points [0, -25] DstBlock "Logical2" DstPort 2 } Branch { Points [30, 0] DstBlock "Concat" DstPort 12 } } Line { SrcBlock "Register15" SrcPort 1 Points [0, -15] Branch { DstBlock "Register16" DstPort 1 } Branch { Points [0, -110; -20, 0] DstBlock "Concat" DstPort 13 } } Line { SrcBlock "Register16" SrcPort 1 Points [0, -15; 10, 0] Branch { DstBlock "Register12" DstPort 1 } Branch { Points [0, -85; -25, 0] DstBlock "Concat" DstPort 14 } } Line { SrcBlock "Register12" SrcPort 1 Points [0, -15; 15, 0] Branch { DstBlock "Register13" DstPort 1 } Branch { Points [0, -65; -25, 0] DstBlock "Concat" DstPort 15 } } Line { SrcBlock "Logical2" SrcPort 1 Points [15, 0; 0, 50] DstBlock "Register15" DstPort 1 } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Register6" DstPort 1 } Line { SrcBlock "Logical" SrcPort 1 Points [35, 0] Branch { DstBlock "Register1" DstPort 1 } Branch { Points [0, -55; 440, 0] Branch { DstBlock "Logical1" DstPort 1 } Branch { Points [0, -20; 480, 0; 0, 15] DstBlock "Logical2" DstPort 1 } } } Line { SrcBlock "Register13" SrcPort 1 Points [0, -90; -5, 0; 0, -15] Branch { DstBlock "Concat" DstPort 16 } Branch { Points [-1620, 0] DstBlock "Logical" DstPort 1 } } Line { SrcBlock "Concat" SrcPort 1 Points [0, -95] DstBlock "Inverter" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "CRC16" DstPort 1 } } } Block { BlockType Reference Name "Constant" SID "16759" Ports [0, 1] Position [380, 327, 405, 353] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "32" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "6" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,26,0,1,white,blue,0,b5591290,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 " "19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 1" "3.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\n" "patch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('out" "put',1,'32');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Counter1" SID "16760" Ports [2, 1] Position [305, 290, 365, 350] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited counter i" "s implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "Inf" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "8" bin_pt "0" load_pin off rst on en on explicit_period "off" period "1" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "counter" sg_icon_stat "60,60,2,1,white,blue,0,ae3608d6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 60 60 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[38.88 38.88 46" ".88 38.88 46.88 46.88 46.88 38.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[30.88 30.88 38.88 38.88 30.88" " ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[22.88 22.88 30.88 30.88 22.88 ],[1 1 1 ]);\npatch(" "[20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[14.88 14.88 22.88 14.88 22.88 22.88 14.88 ],[0.931 0.946 0.973 ]);\nfpr" "intf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'" ",1,'rst');\ncolor('black');port_label('input',2,'en');\n\ncolor('black');disp('{\\fontsize{14}\\bf++}','texmode','" "on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Display Name "Display" SID "16761" Ports [1] Position [845, 225, 960, 255] ZOrder -1 Format "long" Decimation "1" Lockdown off } Block { BlockType From Name "From1" SID "16762" Position [110, 270, 225, 290] ZOrder -9 ShowName off GotoTag "DSSS_RX_RESET" TagVisibility "global" } Block { BlockType Reference Name "Gateway Out1" SID "16763" Ports [1, 1] Position [805, 594, 835, 606] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 30 30 0 0 ],[0 0 12 12 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[13.775 17.22 16.22 15.22 14.22 12.775 13.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "Gateway Out2" SID "16764" Ports [1, 1] Position [805, 574, 835, 586] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 30 30 0 0 ],[0 0 12 12 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[13.775 17.22 16.22 15.22 14.22 12.775 13.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "Gateway Out3" SID "16765" Ports [1, 1] Position [805, 554, 835, 566] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 30 30 0 0 ],[0 0 12 12 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[13.775 17.22 16.22 15.22 14.22 12.775 13.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "Gateway Out4" SID "16766" Ports [1, 1] Position [790, 234, 820, 246] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 30 30 0 0 ],[0 0 12 12 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[13.775 17.22 16.22 15.22 14.22 12.775 13.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "Gateway Out5" SID "16767" Ports [1, 1] Position [805, 614, 835, 626] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 30 30 0 0 ],[0 0 12 12 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[13.775 17.22 16.22 15.22 14.22 12.775 13.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "Gateway Out6" SID "16768" Ports [1, 1] Position [805, 494, 835, 506] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 30 30 0 0 ],[0 0 12 12 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[13.775 17.22 16.22 15.22 14.22 12.775 13.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "Logical1" SID "16769" Ports [2, 1] Position [190, 318, 230, 347] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,29,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 29 29 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 29 29 0 ]);\npatch([11.1 16.88 20.88 24.88 28.88 20.88 15.1 11.1 ],[18.44 18.44 22" ".44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([15.1 20.88 16.88 11.1 15.1 ],[14.44 14.44 18.44 18.44 14.44" " ],[0.931 0.946 0.973 ]);\npatch([11.1 16.88 20.88 15.1 11.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\npatch(" "[15.1 28.88 24.88 20.88 16.88 11.1 15.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nfprintf" "('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('and');\nfp" "rintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register8" SID "16770" Ports [2, 1] Position [710, 521, 750, 554] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "40,33,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 33 33 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 33 33 0 ]);\npatch([11.1 16.88 20.88 24.88 28.88 20.88 15.1 11.1 ],[20.44 20.44 24" ".44 20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([15.1 20.88 16.88 11.1 15.1 ],[16.44 16.44 20.44 20.44 16.44" " ],[0.931 0.946 0.973 ]);\npatch([11.1 16.88 20.88 15.1 11.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1 1 1 ]);\npatch(" "[15.1 28.88 24.88 20.88 16.88 11.1 15.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946 0.973 ]);\nfprintf" "('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp(" "'z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational1" SID "16771" Ports [2, 1] Position [435, 310, 475, 350] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" } List { ListType ScopeGraphics FigureColor "[0.5 0.5 0.5]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "100000" YMin "-1~-1~-1~-0.5~0~0~0" YMax "1~1~1~1.5~150~1~1" SaveName "ScopeData3" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType Outport Name "CRC Calc" SID "16773" Position [770, 163, 800, 177] IconDisplay "Port number" } Line { SrcBlock "From1" SrcPort 1 Points [55, 0; 0, 25] Branch { DstBlock "Counter1" DstPort 1 } Branch { Points [0, 195] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "Counter1" SrcPort 1 Points [45, 0] Branch { DstBlock "Relational1" DstPort 1 } Branch { Points [0, 260] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "Constant" SrcPort 1 DstBlock "Relational1" DstPort 2 } Line { SrcBlock "Relational1" SrcPort 1 Points [15, 0; 0, 45; -320, 0] DstBlock "Logical1" DstPort 2 } Line { SrcBlock "Bit" SrcPort 1 Points [75, 0] Branch { DstBlock "CRC LFSR" DstPort 1 } Branch { Points [0, 305] DstBlock "Register8" DstPort 1 } } Line { SrcBlock "CRC LFSR" SrcPort 1 Points [40, 0] Branch { DstBlock "Gateway Out4" DstPort 1 } Branch { Points [0, -70] DstBlock "CRC Calc" DstPort 1 } } Line { SrcBlock "Gateway Out4" SrcPort 1 DstBlock "Display" DstPort 1 } Line { SrcBlock "Gateway Out1" SrcPort 1 DstBlock "Scope" DstPort 6 } Line { SrcBlock "Gateway Out5" SrcPort 1 DstBlock "Scope" DstPort 7 } Line { SrcBlock "Gateway Out2" SrcPort 1 DstBlock "Scope" DstPort 5 } Line { SrcBlock "Gateway Out3" SrcPort 1 DstBlock "Scope" DstPort 4 } Line { SrcBlock "Register8" SrcPort 1 Points [15, 0; 0, 20] DstBlock "Gateway Out3" DstPort 1 } Line { SrcBlock "Gateway Out6" SrcPort 1 DstBlock "Scope" DstPort 1 } Line { SrcBlock "Bit Valid" SrcPort 1 Points [5, 0] Branch { DstBlock "Logical1" DstPort 1 } Branch { Points [0, 275] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "Logical1" SrcPort 1 Points [20, 0] Branch { DstBlock "Counter1" DstPort 2 } Branch { Points [0, -85; 320, 0] Branch { DstBlock "CRC LFSR" DstPort 2 } Branch { Points [0, 295] Branch { Points [0, 75] DstBlock "Gateway Out5" DstPort 1 } Branch { DstBlock "Register8" DstPort 2 } } } } } } Block { BlockType Reference Name "Logical" SID "16774" Ports [2, 1] Position [915, 591, 945, 624] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,33,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 33 33 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 33 33 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[20.44 " "20.44 24.44 20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[16.44 16.44 20.44 2" "0.44 16.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');" "disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "16775" Ports [2, 1] Position [1075, 466, 1105, 499] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,33,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 33 33 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 33 33 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[20.44 " "20.44 24.44 20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[16.44 16.44 20.44 2" "0.44 16.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');" "disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register" SID "16776" Ports [2, 1] Position [1030, 161, 1065, 194] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,33,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 33 33 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 33 33 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[20.44 " "20.44 24.44 20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[16.44 16.44 20.44 2" "0.44 16.44 ],[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1 1 1 " "]);\npatch([12.1 25.88 21.88 17.88 13.88 8.1 12.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\nc" "olor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Resets" SID "16777" Ports [1, 1] Position [265, 655, 355, 715] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Resets" Location [-1703, 711, -1233, 821] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Pkt Det" SID "16778" Position [185, 383, 215, 397] IconDisplay "Port number" } Block { BlockType Reference Name "Convert" SID "16779" Ports [1, 1] Position [310, 284, 345, 306] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "16" bin_pt "14" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "35,22,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 22 22 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[14.33 14" ".33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 " "1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');po" "rt_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "16780" Ports [1, 1] Position [310, 319, 345, 341] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "16" bin_pt "14" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "35,22,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 22 22 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[14.33 14" ".33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 " "1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');po" "rt_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "16781" Ports [1, 1] Position [310, 379, 345, 401] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "16" bin_pt "14" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "35,22,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 22 22 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[14.33 14" ".33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 " "1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');po" "rt_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From1" SID "16782" Position [85, 285, 255, 305] ZOrder -9 ShowName off GotoTag "DSSS_RX_RESET" TagVisibility "global" } Block { BlockType From Name "From2" SID "16783" Position [85, 320, 260, 340] ZOrder -9 ShowName off GotoTag "regRx_DSSS_RX_Req_PktDet" TagVisibility "global" } Block { BlockType From Name "From3" SID "16784" Position [85, 255, 255, 275] ZOrder -9 ShowName off GotoTag "DSSS_RX_RUNNING" TagVisibility "global" } Block { BlockType From Name "From9" SID "16785" Position [85, 219, 300, 241] ShowName off CloseFcn "tagdialog Close" GotoTag "MAC_PHY_BLOCK_PKT_DET" TagVisibility "global" } Block { BlockType Reference Name "Inverter" SID "16786" Ports [1, 1] Position [400, 337, 430, 353] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "30,16,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 16 16 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 16 16 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[10.22 10.22" " 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[8.22 8.22 10.22 10.22 8" ".22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatch" "([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfpr" "intf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter1" SID "16787" Ports [1, 1] Position [385, 257, 415, 273] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "30,16,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 16 16 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 16 16 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[10.22 10.22" " 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[8.22 8.22 10.22 10.22 8" ".22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatch" "([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfpr" "intf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "16788" Ports [2, 1] Position [460, 241, 490, 274] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,33,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 33 33 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 33 33 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[20.44 20.44 24.4" "4 20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[16.44 16.44 20.44 20.44 16.44 ]," "[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1 1 1 ]);\npatch([10.1" " 23.88 19.88 15.88 11.88 6.1 10.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('and');\nfprintf(" "'','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "16789" Ports [3, 1] Position [460, 306, 490, 354] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,48,3,1,white,blue,0,98d76266,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 48 48 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 48 48 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[28.44 28.44 32.4" "4 28.44 32.44 32.44 32.44 28.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[24.44 24.44 28.44 28.44 24.44 ]," "[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[20.44 20.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([10.1" " 23.88 19.88 15.88 11.88 6.1 10.1 ],[16.44 16.44 20.44 16.44 20.44 20.44 16.44 ],[0.931 0.946 0.973 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\ncolor('black');disp('and');\nfp" "rintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical3" SID "16790" Ports [3, 1] Position [530, 239, 560, 351] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,112,3,1,white,blue,0,a2abe52d,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 112 112 0 ],[0.77 0.82 0" ".91 ]);\nplot([0 30 30 0 0 ],[0 0 112 112 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[60.44 60.44 " "64.44 60.44 64.44 64.44 64.44 60.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[56.44 56.44 60.44 60.44 56.4" "4 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[52.44 52.44 56.44 56.44 52.44 ],[1 1 1 ]);\npatch([" "10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[48.44 48.44 52.44 48.44 52.44 52.44 48.44 ],[0.931 0.946 0.973 ]);\nfprin" "tf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\ncolor('black');disp('or');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Reset" SID "16791" Position [645, 288, 675, 302] IconDisplay "Port number" } Line { SrcBlock "From2" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical2" DstPort 3 } Line { SrcBlock "From1" SrcPort 1 DstBlock "Convert" DstPort 1 } Line { SrcBlock "Logical2" SrcPort 1 DstBlock "Logical3" DstPort 3 } Line { SrcBlock "Pkt Det" SrcPort 1 DstBlock "Convert2" DstPort 1 } Line { SrcBlock "Logical3" SrcPort 1 DstBlock "Reset" DstPort 1 } Line { SrcBlock "Convert" SrcPort 1 DstBlock "Logical3" DstPort 2 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Logical2" DstPort 2 } Line { SrcBlock "Convert2" SrcPort 1 Points [30, 0; 0, -45] DstBlock "Inverter" DstPort 1 } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Logical3" DstPort 1 } Line { SrcBlock "Inverter1" SrcPort 1 Points [10, 0] Branch { DstBlock "Logical1" DstPort 2 } Branch { Points [0, 50] DstBlock "Logical2" DstPort 1 } } Line { SrcBlock "From9" SrcPort 1 Points [70, 0; 0, 20] DstBlock "Logical1" DstPort 1 } Line { SrcBlock "From3" SrcPort 1 DstBlock "Inverter1" DstPort 1 } Annotation { Name "Optionally support DSSS Rx events even when no DSSS Pkt Det\nhas occurred. This can occur at low SNR whe" "re the DSSS Rx\ndemod block can extract bits from noisy waveforms more\nreliably than the autocorrelation block ca" "n see them. At \nthese SNRs the pre-AGC gains are fine, so there's no\npoint doing packet detection anyway\n\nThe " "MAC_PHY_BLOCK_PKT_DET siganl asserts when the MAC core\nhas received an RX_START event. That acts as a reset here " "*unless*\nthe DSSS pipeilne is the source of that RX_START event. In that case\nwe do not want to reset the DSSS R" "x - it should finish normally, then\nsit in reset until the MAC is ready for a new Rx event.\n\nHandling changes t" "o Req_PktDet is tricky. If that config bit goes high\nwhile a pkt-det-less Rx is ongoing, it can't be allowed to r" "eset the PHY.\nIf it does it would leave the MAC in a bad state (RX_END but no\nDATA_DONE). The extra (!DSSS_RX_RU" "NNING) condition will\nprevent this by ignoring the assertiong of Req_PktDet until the DSSS\nRx pipeline is idle." Position [172, 550] HorizontalAlignment "left" } } } Block { BlockType SubSystem Name "S-R Latch" SID "16792" Ports [2, 1] Position [1000, 589, 1040, 671] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "S-R Latch" Location [351, 366, 2001, 1172] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "16793" Position [140, 103, 170, 117] IconDisplay "Port number" } Block { BlockType Inport Name "R" SID "16794" Position [140, 88, 170, 102] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "16795" Ports [0, 1] Position [195, 71, 210, 89] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "15,18,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11.22 13.22 " "11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 9.22 ],[0.931" " 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([4.55 11.44 9.44" " 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon" " graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "16796" Ports [1, 1] Position [210, 86, 235, 104] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cast');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "16797" Ports [1, 1] Position [210, 101, 235, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cast');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "16798" Ports [3, 1] Position [255, 71, 300, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 30.66 3" "6.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 30.66 24" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('" "input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'en');\ncolor('bl" "ack');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon te" "xt');" } Block { BlockType Outport Name "Q" SID "16799" Position [325, 88, 355, 102] IconDisplay "Port number" } Line { SrcBlock "Convert2" SrcPort 1 DstBlock "Register2" DstPort 3 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "S" SrcPort 1 DstBlock "Convert2" DstPort 1 } } } Block { BlockType SubSystem Name "SFD Search" SID "16800" Ports [2, 1] Position [755, 539, 850, 601] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "SFD Search" Location [2, 70, 1830, 1180] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Bit" SID "16801" Position [390, 263, 420, 277] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "Bit Valid" SID "16802" Position [390, 348, 420, 362] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType SubSystem Name "8 Shift Reg" SID "16803" Ports [3, 2] Position [790, 259, 845, 311] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "8 Shift Reg" Location [90, 283, 1901, 1532] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "16804" Position [230, 333, 260, 347] IconDisplay "Port number" } Block { BlockType Inport Name "En" SID "16805" Position [260, 418, 290, 432] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "Rst" SID "16806" Position [255, 453, 285, 467] Port "3" IconDisplay "Port number" } Block { BlockType Reference Name "Concat" SID "16807" Ports [8, 1] Position [267, 235, 968, 270] BlockRotation 270 LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point " "at zero." num_inputs "8" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "701,35,8,1,white,blue,0,6fe74153,up,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 701 701 0 0 ],[0 0 35 35 0 ],[0.77 0." "82 0.91 ]);\nplot([0 701 701 0 0 ],[0 0 35 35 0 ]);\npatch([338.875 346.1 351.1 356.1 361.1 351.1 343.875 338.87" "5 ],[22.55 22.55 27.55 22.55 27.55 27.55 27.55 22.55 ],[1 1 1 ]);\npatch([343.875 351.1 346.1 338.875 343.875 ]," "[17.55 17.55 22.55 22.55 17.55 ],[0.931 0.946 0.973 ]);\npatch([338.875 346.1 351.1 343.875 338.875 ],[12.55 12." "55 17.55 17.55 12.55 ],[1 1 1 ]);\npatch([343.875 361.1 356.1 351.1 346.1 338.875 343.875 ],[7.55 7.55 12.55 7.5" "5 12.55 12.55 7.55 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: beg" "in icon text');\ncolor('black');port_label('input',1,'hi');\n\n\n\n\n\n\ncolor('black');port_label('input',8,'lo" "');\n\ncolor('black');disp('\\fontsize{20}\\}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "16808" Ports [3, 1] Position [330, 331, 375, 379] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "1" rst on en on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "16809" Ports [3, 1] Position [415, 331, 460, 379] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "1" rst on en on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Reference Name "Register3" SID "16810" Ports [3, 1] Position [505, 331, 550, 379] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "1" rst on en on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Reference Name "Register4" SID "16811" Ports [3, 1] Position [595, 331, 640, 379] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "1" rst on en on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Reference Name "Register5" SID "16812" Ports [3, 1] Position [680, 331, 725, 379] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "1" rst on en on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Reference Name "Register6" SID "16813" Ports [3, 1] Position [765, 331, 810, 379] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "1" rst on en on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Reference Name "Register7" SID "16814" Ports [3, 1] Position [855, 331, 900, 379] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "1" rst on en on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Reference Name "Register8" SID "16815" Ports [3, 1] Position [945, 331, 990, 379] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "1" rst on en on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "16816" Position [1045, 348, 1075, 362] IconDisplay "Port number" } Block { BlockType Outport Name "8b" SID "16817" Position [1045, 133, 1075, 147] Port "2" IconDisplay "Port number" } Line { SrcBlock "Register1" SrcPort 1 Points [0, -15; 20, 0] Branch { DstBlock "Register2" DstPort 1 } Branch { Points [5, 0] DstBlock "Concat" DstPort 2 } } Line { SrcBlock "Register2" SrcPort 1 Points [0, -15; 25, 0] Branch { DstBlock "Register3" DstPort 1 } Branch { DstBlock "Concat" DstPort 3 } } Line { SrcBlock "Register3" SrcPort 1 Points [0, -15; 20, 0] Branch { DstBlock "Register4" DstPort 1 } Branch { DstBlock "Concat" DstPort 4 } } Line { SrcBlock "Register5" SrcPort 1 Points [0, -15; 10, 0] Branch { DstBlock "Register6" DstPort 1 } Branch { Points [0, -35; 5, 0] DstBlock "Concat" DstPort 6 } } Line { SrcBlock "Register6" SrcPort 1 Points [0, -15] Branch { DstBlock "Register7" DstPort 1 } Branch { Points [0, -55] DstBlock "Concat" DstPort 7 } } Line { SrcBlock "Register7" SrcPort 1 Points [0, -15] Branch { DstBlock "Register8" DstPort 1 } Branch { Points [0, -35] Branch { Points [0, -20] DstBlock "Concat" DstPort 8 } Branch { Points [65, 0] } } } Line { SrcBlock "Register4" SrcPort 1 Points [5, 0; 0, -15; 10, 0] Branch { DstBlock "Register5" DstPort 1 } Branch { DstBlock "Concat" DstPort 5 } } Line { SrcBlock "En" SrcPort 1 Points [15, 0] Branch { Points [0, -55] DstBlock "Register1" DstPort 3 } Branch { Points [90, 0] Branch { DstBlock "Register2" DstPort 3 } Branch { Points [90, 0] Branch { DstBlock "Register3" DstPort 3 } Branch { Points [90, 0] Branch { DstBlock "Register4" DstPort 3 } Branch { Points [85, 0] Branch { DstBlock "Register5" DstPort 3 } Branch { Points [85, 0] Branch { DstBlock "Register6" DstPort 3 } Branch { Points [90, 0] Branch { DstBlock "Register7" DstPort 3 } Branch { Points [90, 0] DstBlock "Register8" DstPort 3 } } } } } } } } Line { SrcBlock "Rst" SrcPort 1 Points [15, 0] Branch { Points [0, -105] DstBlock "Register1" DstPort 2 } Branch { Points [85, 0] Branch { Points [90, 0] Branch { Points [85, 0] Branch { Points [85, 0] Branch { Points [90, 0] Branch { Points [90, 0] Branch { Points [0, -105] DstBlock "Register7" DstPort 2 } Branch { Points [90, 0; 0, -105] DstBlock "Register8" DstPort 2 } } Branch { Points [0, -105] DstBlock "Register6" DstPort 2 } } Branch { Points [0, -105] DstBlock "Register5" DstPort 2 } } Branch { Points [0, -105] DstBlock "Register4" DstPort 2 } } Branch { Points [0, -105] DstBlock "Register3" DstPort 2 } } Branch { Points [0, -105] DstBlock "Register2" DstPort 2 } } } Line { SrcBlock "D" SrcPort 1 Points [45, 0] Branch { DstBlock "Register1" DstPort 1 } Branch { Points [10, 0] DstBlock "Concat" DstPort 1 } } Line { SrcBlock "Register8" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "Concat" SrcPort 1 Points [0, -90] DstBlock "8b" DstPort 1 } } } Block { BlockType SubSystem Name "8 Shift Reg1" SID "16818" Ports [3, 2] Position [910, 264, 965, 316] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "8 Shift Reg1" Location [90, 283, 1901, 1532] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "16819" Position [230, 333, 260, 347] IconDisplay "Port number" } Block { BlockType Inport Name "En" SID "16820" Position [260, 418, 290, 432] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "Rst" SID "16821" Position [255, 453, 285, 467] Port "3" IconDisplay "Port number" } Block { BlockType Reference Name "Concat" SID "16822" Ports [8, 1] Position [267, 235, 968, 270] BlockRotation 270 LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point " "at zero." num_inputs "8" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "701,35,8,1,white,blue,0,6fe74153,up,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 701 701 0 0 ],[0 0 35 35 0 ],[0.77 0." "82 0.91 ]);\nplot([0 701 701 0 0 ],[0 0 35 35 0 ]);\npatch([338.875 346.1 351.1 356.1 361.1 351.1 343.875 338.87" "5 ],[22.55 22.55 27.55 22.55 27.55 27.55 27.55 22.55 ],[1 1 1 ]);\npatch([343.875 351.1 346.1 338.875 343.875 ]," "[17.55 17.55 22.55 22.55 17.55 ],[0.931 0.946 0.973 ]);\npatch([338.875 346.1 351.1 343.875 338.875 ],[12.55 12." "55 17.55 17.55 12.55 ],[1 1 1 ]);\npatch([343.875 361.1 356.1 351.1 346.1 338.875 343.875 ],[7.55 7.55 12.55 7.5" "5 12.55 12.55 7.55 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: beg" "in icon text');\ncolor('black');port_label('input',1,'hi');\n\n\n\n\n\n\ncolor('black');port_label('input',8,'lo" "');\n\ncolor('black');disp('\\fontsize{20}\\}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "16823" Ports [3, 1] Position [330, 331, 375, 379] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "1" rst on en on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "16824" Ports [3, 1] Position [415, 331, 460, 379] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "1" rst on en on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Reference Name "Register3" SID "16825" Ports [3, 1] Position [505, 331, 550, 379] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "1" rst on en on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Reference Name "Register4" SID "16826" Ports [3, 1] Position [595, 331, 640, 379] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "1" rst on en on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Reference Name "Register5" SID "16827" Ports [3, 1] Position [680, 331, 725, 379] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "1" rst on en on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Reference Name "Register6" SID "16828" Ports [3, 1] Position [765, 331, 810, 379] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "1" rst on en on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Reference Name "Register7" SID "16829" Ports [3, 1] Position [855, 331, 900, 379] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "1" rst on en on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Reference Name "Register8" SID "16830" Ports [3, 1] Position [945, 331, 990, 379] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "1" rst on en on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "16831" Position [1045, 348, 1075, 362] IconDisplay "Port number" } Block { BlockType Outport Name "8b" SID "16832" Position [1045, 133, 1075, 147] Port "2" IconDisplay "Port number" } Line { SrcBlock "Concat" SrcPort 1 Points [0, -90] DstBlock "8b" DstPort 1 } Line { SrcBlock "Register8" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "D" SrcPort 1 Points [45, 0] Branch { Points [10, 0] DstBlock "Concat" DstPort 1 } Branch { DstBlock "Register1" DstPort 1 } } Line { SrcBlock "Rst" SrcPort 1 Points [15, 0] Branch { Points [85, 0] Branch { Points [0, -105] DstBlock "Register2" DstPort 2 } Branch { Points [90, 0] Branch { Points [0, -105] DstBlock "Register3" DstPort 2 } Branch { Points [85, 0] Branch { Points [0, -105] DstBlock "Register4" DstPort 2 } Branch { Points [85, 0] Branch { Points [0, -105] DstBlock "Register5" DstPort 2 } Branch { Points [90, 0] Branch { Points [0, -105] DstBlock "Register6" DstPort 2 } Branch { Points [90, 0] Branch { Points [90, 0; 0, -105] DstBlock "Register8" DstPort 2 } Branch { Points [0, -105] DstBlock "Register7" DstPort 2 } } } } } } } Branch { Points [0, -105] DstBlock "Register1" DstPort 2 } } Line { SrcBlock "En" SrcPort 1 Points [15, 0] Branch { Points [90, 0] Branch { Points [90, 0] Branch { Points [90, 0] Branch { Points [85, 0] Branch { Points [85, 0] Branch { Points [90, 0] Branch { Points [90, 0] DstBlock "Register8" DstPort 3 } Branch { DstBlock "Register7" DstPort 3 } } Branch { DstBlock "Register6" DstPort 3 } } Branch { DstBlock "Register5" DstPort 3 } } Branch { DstBlock "Register4" DstPort 3 } } Branch { DstBlock "Register3" DstPort 3 } } Branch { DstBlock "Register2" DstPort 3 } } Branch { Points [0, -55] DstBlock "Register1" DstPort 3 } } Line { SrcBlock "Register4" SrcPort 1 Points [5, 0; 0, -15; 10, 0] Branch { DstBlock "Concat" DstPort 5 } Branch { DstBlock "Register5" DstPort 1 } } Line { SrcBlock "Register7" SrcPort 1 Points [0, -15] Branch { Points [0, -35] Branch { Points [65, 0] } Branch { Points [0, -20] DstBlock "Concat" DstPort 8 } } Branch { DstBlock "Register8" DstPort 1 } } Line { SrcBlock "Register6" SrcPort 1 Points [0, -15] Branch { Points [0, -55] DstBlock "Concat" DstPort 7 } Branch { DstBlock "Register7" DstPort 1 } } Line { SrcBlock "Register5" SrcPort 1 Points [0, -15; 10, 0] Branch { Points [0, -35; 5, 0] DstBlock "Concat" DstPort 6 } Branch { DstBlock "Register6" DstPort 1 } } Line { SrcBlock "Register3" SrcPort 1 Points [0, -15; 20, 0] Branch { DstBlock "Concat" DstPort 4 } Branch { DstBlock "Register4" DstPort 1 } } Line { SrcBlock "Register2" SrcPort 1 Points [0, -15; 25, 0] Branch { DstBlock "Concat" DstPort 3 } Branch { DstBlock "Register3" DstPort 1 } } Line { SrcBlock "Register1" SrcPort 1 Points [0, -15; 20, 0] Branch { Points [5, 0] DstBlock "Concat" DstPort 2 } Branch { DstBlock "Register2" DstPort 1 } } } } Block { BlockType Reference Name "Concat1" SID "16833" Ports [2, 1] Position [1015, 368, 1050, 452] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point at z" "ero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "35,84,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 84 84 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 84 84 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[47.55 47.55 52." "55 47.55 52.55 52.55 52.55 47.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[42.55 42.55 47.55 47.55 42." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[37.55 37.55 42.55 42.55 37.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[32.55 32.55 37.55 32.55 37.55 37.55 32.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i" "nput',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fontsize{20}\\}','texmode','o" "n');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant2" SID "16834" Ports [0, 1] Position [1065, 357, 1090, 383] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "hex2dec('F3A0')" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "16" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,26,0,1,white,blue,0,20fe8b54,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 " "19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 1" "3.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\n" "patch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('out" "put',1,'62368');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From1" SID "16835" Position [350, 379, 460, 401] ZOrder -9 ShowName off GotoTag "DSSS_RX_RESET" TagVisibility "global" } Block { BlockType Reference Name "Logical" SID "16836" Ports [2, 1] Position [1230, 371, 1260, 404] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,33,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 33 33 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 33 33 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[20.44 20.44 24.4" "4 20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[16.44 16.44 20.44 20.44 16.44 ]," "[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1 1 1 ]);\npatch([10.1" " 23.88 19.88 15.88 11.88 6.1 10.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('and');\nfprintf(" "'','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Posedge" SID "16837" Ports [1, 1] Position [1315, 383, 1360, 397] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Posedge" Location [90, 283, 1701, 1127] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "16838" Position [265, 183, 295, 197] IconDisplay "Port number" } Block { BlockType Reference Name "Delay" SID "16839" Ports [1, 1] Position [425, 153, 460, 177] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. " "If register retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[15" ".33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.33 12." "33 15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 12.33 " "9.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\nc" "olor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "16840" Ports [1, 1] Position [490, 156, 515, 174] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "16841" Ports [2, 1] Position [540, 151, 585, 204] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,53,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 53 53 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 53 53 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[32.66 3" "2.66 38.66 32.66 38.66 38.66 38.66 32.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[26.66 26.66 32.66 " "32.66 26.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[20.66 20.66 26.66 26.66 20.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[14.66 14.66 20.66 14.66 20.66 20.66 14.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('" "black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "16842" Position [610, 173, 640, 187] IconDisplay "Port number" } Line { SrcBlock "D" SrcPort 1 Points [85, 0] Branch { DstBlock "Logical1" DstPort 2 } Branch { Points [0, -25] DstBlock "Delay" DstPort 1 } } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Delay" SrcPort 1 DstBlock "Inverter" DstPort 1 } } } Block { BlockType Reference Name "Relational1" SID "16843" Ports [2, 1] Position [1135, 360, 1175, 400] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "40,40,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25.55 30." "55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 25.55 20." "55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1 1 ]);\npa" "tch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i" "nput',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa = b','texmod" "e','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Found" SID "16844" Position [1415, 383, 1445, 397] IconDisplay "Port number" } Line { SrcBlock "Logical" SrcPort 1 DstBlock "Posedge" DstPort 1 } Line { SrcBlock "Bit" SrcPort 1 DstBlock "8 Shift Reg" DstPort 1 } Line { Labels [0, 0] SrcBlock "Bit Valid" SrcPort 1 Points [340, 0] Branch { Points [0, 0; 0, -70] DstBlock "8 Shift Reg" DstPort 2 } Branch { Points [45, 0] Branch { Points [0, 180; 390, 0; 0, -140] DstBlock "Logical" DstPort 2 } Branch { Points [70, 0; 0, -65] DstBlock "8 Shift Reg1" DstPort 2 } } } Line { Labels [0, 0] SrcBlock "From1" SrcPort 1 Points [310, 0; 0, -65] Branch { DstBlock "8 Shift Reg" DstPort 3 } Branch { Points [115, 0; 0, -20] DstBlock "8 Shift Reg1" DstPort 3 } } Line { SrcBlock "8 Shift Reg" SrcPort 1 DstBlock "8 Shift Reg1" DstPort 1 } Line { SrcBlock "8 Shift Reg" SrcPort 2 Points [20, 0; 0, 90] DstBlock "Concat1" DstPort 1 } Line { SrcBlock "8 Shift Reg1" SrcPort 2 Points [15, 0; 0, 125] DstBlock "Concat1" DstPort 2 } Line { SrcBlock "Concat1" SrcPort 1 Points [30, 0; 0, -20] DstBlock "Relational1" DstPort 2 } Line { SrcBlock "Constant2" SrcPort 1 DstBlock "Relational1" DstPort 1 } Line { SrcBlock "Relational1" SrcPort 1 DstBlock "Logical" DstPort 1 } Line { SrcBlock "Posedge" SrcPort 1 DstBlock "Found" DstPort 1 } } } Block { BlockType SubSystem Name "SYNC and Phase Sel" SID "16845" Ports [4, 3] Position [440, 536, 530, 629] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "SYNC and Phase Sel" Location [2, 70, 1830, 1180] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Valid" SID "16846" Position [60, 433, 90, 447] ZOrder -1 IconDisplay "Port number" } Block { BlockType Inport Name "Bit" SID "16847" Position [60, 398, 90, 412] ZOrder -1 Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "IQ Mag" SID "16848" Position [60, 698, 90, 712] ZOrder -1 Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "Reset" SID "16849" Position [135, 753, 165, 767] ZOrder -1 Port "4" IconDisplay "Port number" } Block { BlockType SubSystem Name "Address Gen" SID "16850" Ports [1, 6] Position [245, 483, 340, 597] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Address Gen" Location [2, 70, 1830, 1180] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "125" Block { BlockType Inport Name "Bit Valid" SID "17851" Position [45, 88, 75, 102] ZOrder -1 IconDisplay "Port number" } Block { BlockType Reference Name "4MSB" SID "16851" Ports [1, 1] Position [790, 737, 835, 753] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1+log2(DSSS_CLKS_PER_SAMP)" boolean_output off mode "Upper Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "45,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 16 16 0 ]);\npatch([17.55 20.44 22.44 24.44 26.44 22.44 19.55 17.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([19.55 22.44 20.44 17.55 19.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([17.55 20.44 22.44 19.55 17.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([19.55 26.44 24.44 22.44 20.44 17.55 19.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "4MSB1" SID "16852" Ports [1, 1] Position [790, 822, 835, 838] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1+log2(DSSS_CLKS_PER_SAMP)" boolean_output off mode "Upper Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "45,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 16 16 0 ]);\npatch([17.55 20.44 22.44 24.44 26.44 22.44 19.55 17.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([19.55 22.44 20.44 17.55 19.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([17.55 20.44 22.44 19.55 17.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([19.55 26.44 24.44 22.44 20.44 17.55 19.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "5LSB" SID "16853" Ports [1, 1] Position [375, 794, 415, 816] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "log2(DSSS_BIT_MATCH_RAM_WIDTH)" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,22,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 22 22 0 ]);\npatch([13.325 17.66 20.66 23.66 26.66 20.66 16.325 13.325 ],[14" ".33 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([16.325 20.66 17.66 13.325 16.325 ],[11.33 11." "33 14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([13.325 17.66 20.66 16.325 13.325 ],[8.33 8.33 11.33 11.33 " "8.33 ],[1 1 1 ]);\npatch([16.325 26.66 23.66 20.66 17.66 13.325 16.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncol" "or('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub" SID "16854" Ports [2, 1] Position [670, 318, 715, 382] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Subtraction" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Unsigned" n_bits "log2(DSSS_NUM_SYMS_PER_OFFSET)" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL off hw_selection "Fabric" pipelined off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" sg_icon_stat "45,64,2,1,white,blue,0,32e1f85f,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 64 64 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 64 64 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[38.66 3" "8.66 44.66 38.66 44.66 44.66 44.66 38.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[32.66 32.66 38.66 " "38.66 32.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[26.66 26.66 32.66 32.66 26.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[20.66 20.66 26.66 20.66 26.66 26.66 20.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bf{a - b}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub1" SID "16855" Ports [2, 1] Position [670, 433, 715, 497] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Subtraction" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Unsigned" n_bits "log2(DSSS_NUM_SYMS_PER_OFFSET)" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL off hw_selection "Fabric" pipelined off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" sg_icon_stat "45,64,2,1,white,blue,0,32e1f85f,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 64 64 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 64 64 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[38.66 3" "8.66 44.66 38.66 44.66 44.66 44.66 38.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[32.66 32.66 38.66 " "38.66 32.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[26.66 26.66 32.66 32.66 26.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[20.66 20.66 26.66 20.66 26.66 26.66 20.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bf{a - b}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Clks per Samp Counter" SID "16856" Ports [1, 1] Position [220, 347, 270, 373] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited count" "er is implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "inf" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "log2(DSSS_CLKS_PER_SAMP)" bin_pt "0" load_pin off rst on en off explicit_period "off" period "1" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "counter" sg_icon_stat "50,26,1,1,white,blue,0,803eba70,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 26 26 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 26 26 0 ]);\npatch([18.325 22.66 25.66 28.66 31.66 25.66 21.325 18.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([21.325 25.66 22.66 18.325 21.325 ],[13.33 13." "33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([18.325 22.66 25.66 21.325 18.325 ],[10.33 10.33 13.33 13.3" "3 10.33 ],[1 1 1 ]);\npatch([21.325 31.66 28.66 25.66 22.66 18.325 21.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7." "33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n" "color('black');port_label('input',1,'rst');\n\ncolor('black');disp('{\\fontsize{14}\\bf++}','texmode','on');\nfp" "rintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Clks per Samp Counter1" SID "16857" Ports [1, 1] Position [220, 627, 270, 653] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited count" "er is implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "inf" operation "Down" start_count "DSSS_CLKS_PER_SAMP-1" cnt_by_val "1" arith_type "Unsigned" n_bits "log2(DSSS_CLKS_PER_SAMP)" bin_pt "0" load_pin off rst on en off explicit_period "off" period "1" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "counter" sg_icon_stat "50,26,1,1,white,blue,0,d47ba05d,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 26 26 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 26 26 0 ]);\npatch([18.325 22.66 25.66 28.66 31.66 25.66 21.325 18.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([21.325 25.66 22.66 18.325 21.325 ],[13.33 13." "33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([18.325 22.66 25.66 21.325 18.325 ],[10.33 10.33 13.33 13.3" "3 10.33 ],[1 1 1 ]);\npatch([21.325 31.66 28.66 25.66 22.66 18.325 21.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7." "33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n" "color('black');port_label('input',1,'rst');\n\ncolor('black');disp('{\\fontsize{14}\\bf--}','texmode','on');\nfp" "rintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Concat" SID "16858" Ports [2, 1] Position [895, 193, 955, 277] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point " "at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "60,84,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 84 84 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 84 84 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[50.88 50" ".88 58.88 50.88 58.88 58.88 58.88 50.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[42.88 42.88 50.88 50." "88 42.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[34.88 34.88 42.88 42.88 34.88 ],[1 1 1 ]" ");\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[26.88 26.88 34.88 26.88 34.88 34.88 26.88 ],[0.931 0.946 0." "973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port" "_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fontsize{20}\\}','" "texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Concat1" SID "16859" Ports [2, 1] Position [440, 435, 480, 490] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point " "at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "40,55,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 55 55 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 55 55 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[32.55 32." "55 37.55 32.55 37.55 37.55 37.55 32.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[27.55 27.55 32.55 3" "2.55 27.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[22.55 22.55 27.55 27.55 22.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[17.55 17.55 22.55 17.55 22.55 22.55 17.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fontsize{20}\\" "}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Concat2" SID "16860" Ports [2, 1] Position [570, 335, 610, 390] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point " "at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "40,55,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 55 55 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 55 55 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[32.55 32." "55 37.55 32.55 37.55 37.55 37.55 32.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[27.55 27.55 32.55 3" "2.55 27.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[22.55 22.55 27.55 27.55 22.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[17.55 17.55 22.55 17.55 22.55 22.55 17.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fontsize{20}\\" "}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Concat3" SID "16861" Ports [2, 1] Position [895, 403, 955, 487] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point " "at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "60,84,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 84 84 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 84 84 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[50.88 50" ".88 58.88 50.88 58.88 58.88 58.88 50.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[42.88 42.88 50.88 50." "88 42.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[34.88 34.88 42.88 42.88 34.88 ],[1 1 1 ]" ");\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[26.88 26.88 34.88 26.88 34.88 34.88 26.88 ],[0.931 0.946 0." "973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port" "_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fontsize{20}\\}','" "texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Concat4" SID "16862" Ports [2, 1] Position [575, 450, 615, 505] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point " "at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "40,55,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 55 55 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 55 55 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[32.55 32." "55 37.55 32.55 37.55 37.55 37.55 32.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[27.55 27.55 32.55 3" "2.55 27.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[22.55 22.55 27.55 27.55 22.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[17.55 17.55 22.55 17.55 22.55 22.55 17.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fontsize{20}\\" "}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Concat5" SID "16863" Ports [2, 1] Position [440, 320, 480, 375] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point " "at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "40,55,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 55 55 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 55 55 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[32.55 32." "55 37.55 32.55 37.55 37.55 37.55 32.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[27.55 27.55 32.55 3" "2.55 27.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[22.55 22.55 27.55 27.55 22.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[17.55 17.55 22.55 17.55 22.55 22.55 17.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fontsize{20}\\" "}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Concat6" SID "16864" Ports [2, 1] Position [915, 705, 955, 760] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point " "at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "40,55,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 55 55 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 55 55 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[32.55 32." "55 37.55 32.55 37.55 37.55 37.55 32.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[27.55 27.55 32.55 3" "2.55 27.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[22.55 22.55 27.55 27.55 22.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[17.55 17.55 22.55 17.55 22.55 22.55 17.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fontsize{20}\\" "}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Concat7" SID "16865" Ports [2, 1] Position [915, 790, 955, 845] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point " "at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "40,55,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 55 55 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 55 55 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[32.55 32." "55 37.55 32.55 37.55 37.55 37.55 32.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[27.55 27.55 32.55 3" "2.55 27.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[22.55 22.55 27.55 27.55 22.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[17.55 17.55 22.55 17.55 22.55 22.55 17.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fontsize{20}\\" "}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Concat8" SID "16866" Ports [2, 1] Position [440, 600, 480, 655] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point " "at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "40,55,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 55 55 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 55 55 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[32.55 32." "55 37.55 32.55 37.55 37.55 37.55 32.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[27.55 27.55 32.55 3" "2.55 27.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[22.55 22.55 27.55 27.55 22.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[17.55 17.55 22.55 17.55 22.55 22.55 17.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fontsize{20}\\" "}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Concat9" SID "16867" Ports [2, 1] Position [440, 690, 480, 745] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point " "at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "40,55,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 55 55 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 55 55 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[32.55 32." "55 37.55 32.55 37.55 37.55 37.55 32.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[27.55 27.55 32.55 3" "2.55 27.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[22.55 22.55 27.55 27.55 22.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[17.55 17.55 22.55 17.55 22.55 22.55 17.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fontsize{20}\\" "}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant1" SID "16868" Ports [0, 1] Position [515, 364, 530, 386] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "log2(DSSS_BIT_MATCH_RAM_WIDTH)" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "8" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "15,22,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 15 15 0 0 ],[0 0 22 22 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[13.22 13.22 " "15.22 13.22 15.22 15.22 15.22 13.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[11.22 11.22 13.22 13.22 11." "22 ],[0.931 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[9.22 9.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([" "4.55 11.44 9.44 7.44 5.44 2.55 4.55 ],[7.22 7.22 9.22 7.22 9.22 9.22 7.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'0'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant2" SID "16869" Ports [0, 1] Position [385, 439, 400, 461] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "8" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "15,22,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 15 15 0 0 ],[0 0 22 22 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[13.22 13.22 " "15.22 13.22 15.22 15.22 15.22 13.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[11.22 11.22 13.22 13.22 11." "22 ],[0.931 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[9.22 9.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([" "4.55 11.44 9.44 7.44 5.44 2.55 4.55 ],[7.22 7.22 9.22 7.22 9.22 9.22 7.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant3" SID "16870" Ports [0, 1] Position [385, 324, 400, 346] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "8" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "15,22,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 15 15 0 0 ],[0 0 22 22 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[13.22 13.22 " "15.22 13.22 15.22 15.22 15.22 13.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[11.22 11.22 13.22 13.22 11." "22 ],[0.931 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[9.22 9.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([" "4.55 11.44 9.44 7.44 5.44 2.55 4.55 ],[7.22 7.22 9.22 7.22 9.22 9.22 7.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'0'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant4" SID "16871" Ports [0, 1] Position [385, 694, 400, 716] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "8" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "15,22,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 15 15 0 0 ],[0 0 22 22 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[13.22 13.22 " "15.22 13.22 15.22 15.22 15.22 13.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[11.22 11.22 13.22 13.22 11." "22 ],[0.931 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[9.22 9.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([" "4.55 11.44 9.44 7.44 5.44 2.55 4.55 ],[7.22 7.22 9.22 7.22 9.22 9.22 7.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'0'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant5" SID "16872" Ports [0, 1] Position [385, 604, 400, 626] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "8" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "15,22,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 15 15 0 0 ],[0 0 22 22 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[13.22 13.22 " "15.22 13.22 15.22 15.22 15.22 13.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[11.22 11.22 13.22 13.22 11." "22 ],[0.931 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[9.22 9.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([" "4.55 11.44 9.44 7.44 5.44 2.55 4.55 ],[7.22 7.22 9.22 7.22 9.22 9.22 7.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant6" SID "17858" Ports [0, 1] Position [35, 305, 65, 325] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "DSSS_SAMPS_PER_SYM - 1" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "ceil(log2(DSSS_SAMPS_PER_SYM - 1))" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "8" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,20,0,1,white,blue,0,9df9935b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 20 20 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 20 20 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[12.22" " 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[10.22 10.22 12." "22 12.22 10.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1" " 1 1 ]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');po" "rt_label('output',1,'19');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant7" SID "16873" Ports [0, 1] Position [855, 599, 870, 621] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "8" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "15,22,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 15 15 0 0 ],[0 0 22 22 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[13.22 13.22 " "15.22 13.22 15.22 15.22 15.22 13.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[11.22 11.22 13.22 13.22 11." "22 ],[0.931 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[9.22 9.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([" "4.55 11.44 9.44 7.44 5.44 2.55 4.55 ],[7.22 7.22 9.22 7.22 9.22 9.22 7.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'0'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Goto Name "Goto1" SID "16874" Position [1100, 120, 1210, 140] ZOrder -10 ShowName off GotoTag "sym_index" TagVisibility "global" } Block { BlockType Goto Name "Goto2" SID "16875" Position [1100, 85, 1210, 105] ZOrder -10 ShowName off GotoTag "sym_offset" TagVisibility "global" } Block { BlockType Reference Name "Logical" SID "17860" Ports [2, 1] Position [180, 283, 210, 312] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "30,29,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 29 29 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 29 29 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 18.4" "4 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 18.44 " "14.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\np" "atch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('an" "d');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Posedge1" SID "17852" Ports [1, 1] Position [115, 86, 160, 104] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Posedge1" Location [88, 301, 2330, 1301] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "17853" Position [200, 253, 230, 267] IconDisplay "Port number" } Block { BlockType Reference Name "Delay" SID "17854" Ports [1, 1] Position [425, 153, 460, 177] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. " "If register retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[15" ".33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.33 12." "33 15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 12.33 " "9.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\nc" "olor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "17855" Ports [1, 1] Position [490, 156, 515, 174] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "17856" Ports [2, 1] Position [540, 151, 585, 204] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,53,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 53 53 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 53 53 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[32.66 3" "2.66 38.66 32.66 38.66 38.66 38.66 32.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[26.66 26.66 32.66 " "32.66 26.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[20.66 20.66 26.66 26.66 20.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[14.66 14.66 20.66 14.66 20.66 20.66 14.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('" "black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "17857" Position [610, 173, 640, 187] IconDisplay "Port number" } Line { SrcBlock "Delay" SrcPort 1 DstBlock "Inverter" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "D" SrcPort 1 Points [150, 0; 0, -70] Branch { Points [0, -25] DstBlock "Delay" DstPort 1 } Branch { DstBlock "Logical1" DstPort 2 } } Annotation { Name "Rising Edge Detection" Position [500, 112] } } } Block { BlockType Reference Name "Relational1" SID "17859" Ports [2, 1] Position [105, 287, 140, 323] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,36,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 36 36 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 36 36 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[23.55 23." "55 28.55 23.55 28.55 28.55 28.55 23.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[18.55 18.55 23.55 2" "3.55 18.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[13.55 13.55 18.55 18.55 13.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[8.55 8.55 13.55 8.55 13.55 13.55 8.55 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');por" "t_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa " "= b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational2" SID "16876" Ports [2, 1] Position [910, 582, 945, 618] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,36,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 36 36 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 36 36 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[23.55 23." "55 28.55 23.55 28.55 28.55 28.55 23.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[18.55 18.55 23.55 2" "3.55 18.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[13.55 13.55 18.55 18.55 13.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[8.55 8.55 13.55 8.55 13.55 13.55 8.55 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');por" "t_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa " "= b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Rx Sym Counter" SID "16877" Ports [1, 1] Position [220, 232, 270, 258] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited count" "er is implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "inf" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "log2(DSSS_NUM_SYMS_PER_OFFSET)" bin_pt "0" load_pin off rst off en on explicit_period "off" period "DSSS_CLKS_PER_SAMP * DSSS_SAMPS_PER_SYM" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "counter" sg_icon_stat "50,26,1,1,white,blue,0,b089e9c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 26 26 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 26 26 0 ]);\npatch([18.325 22.66 25.66 28.66 31.66 25.66 21.325 18.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([21.325 25.66 22.66 18.325 21.325 ],[13.33 13." "33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([18.325 22.66 25.66 21.325 18.325 ],[10.33 10.33 13.33 13.3" "3 10.33 ],[1 1 1 ]);\npatch([21.325 31.66 28.66 25.66 22.66 18.325 21.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7." "33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n" "color('black');port_label('input',1,'en');\n\ncolor('black');disp('{\\fontsize{14}\\bf++}','texmode','on');\nfpr" "intf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Sym Offset Counter" SID "16878" Ports [1, 1] Position [220, 202, 270, 228] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited count" "er is implemented by combining a counter with a comparator." cnt_type "Count Limited" cnt_to "DSSS_SAMPS_PER_SYM - 1" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "ceil(log2(DSSS_SAMPS_PER_SYM))" bin_pt "0" load_pin off rst off en on explicit_period "off" period "DSSS_CLKS_PER_SAMP" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "counter" sg_icon_stat "50,26,1,1,white,blue,0,6de68f4a,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 26 26 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 26 26 0 ]);\npatch([18.325 22.66 25.66 28.66 31.66 25.66 21.325 18.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([21.325 25.66 22.66 18.325 21.325 ],[13.33 13." "33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([18.325 22.66 25.66 21.325 18.325 ],[10.33 10.33 13.33 13.3" "3 10.33 ],[1 1 1 ]);\npatch([21.325 31.66 28.66 25.66 22.66 18.325 21.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7." "33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n" "color('black');port_label('input',1,'en');\n\ncolor('black');disp('{\\fontsize{14}\\bf\\lceil++\\rceil}','texmod" "e','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Rx Bit WrEn" SID "16881" Position [1075, 593, 1105, 607] IconDisplay "Port number" } Block { BlockType Outport Name "Bit Hist Addr A" SID "16882" Position [1055, 228, 1085, 242] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "Bit Hist Addr B" SID "16883" Position [1070, 438, 1100, 452] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "Match Addr A" SID "16884" Position [1090, 813, 1120, 827] Port "4" IconDisplay "Port number" } Block { BlockType Outport Name "Match Addr B" SID "16885" Position [1090, 728, 1120, 742] Port "5" IconDisplay "Port number" } Block { BlockType Outport Name "Despread Phase" SID "16886" Position [1055, 148, 1085, 162] Port "6" IconDisplay "Port number" } Line { SrcBlock "Sym Offset Counter" SrcPort 1 Points [30, 0] Branch { Points [0, -40; -225, 0; 0, 120] DstBlock "Relational1" DstPort 1 } Branch { Points [320, 0] Branch { Points [225, 0] Branch { DstBlock "Concat" DstPort 1 } Branch { Points [0, 210] DstBlock "Concat3" DstPort 1 } Branch { Points [0, -60] DstBlock "Despread Phase" DstPort 1 } } Branch { Points [0, -120] DstBlock "Goto2" DstPort 1 } } } Line { SrcBlock "Rx Sym Counter" SrcPort 1 Points [45, 0] Branch { Points [0, 560] DstBlock "5LSB" DstPort 1 } Branch { Points [310, 0] Branch { Points [0, 90] Branch { DstBlock "AddSub" DstPort 1 } Branch { Points [0, 115] DstBlock "AddSub1" DstPort 1 } } Branch { Points [0, -115] DstBlock "Goto1" DstPort 1 } } } Line { SrcBlock "Constant7" SrcPort 1 DstBlock "Relational2" DstPort 2 } Line { SrcBlock "Concat" SrcPort 1 DstBlock "Bit Hist Addr A" DstPort 1 } Line { SrcBlock "Relational2" SrcPort 1 DstBlock "Rx Bit WrEn" DstPort 1 } Line { SrcBlock "AddSub" SrcPort 1 Points [50, 0; 0, -95] DstBlock "Concat" DstPort 2 } Line { SrcBlock "Concat3" SrcPort 1 DstBlock "Bit Hist Addr B" DstPort 1 } Line { SrcBlock "Concat2" SrcPort 1 DstBlock "AddSub" DstPort 2 } Line { SrcBlock "Constant1" SrcPort 1 Points [10, 0] Branch { DstBlock "Concat2" DstPort 2 } Branch { Points [0, 115] DstBlock "Concat4" DstPort 2 } } Line { SrcBlock "AddSub1" SrcPort 1 DstBlock "Concat3" DstPort 2 } Line { SrcBlock "Clks per Samp Counter" SrcPort 1 Points [60, 0; 0, 0] Branch { Points [0, 230] DstBlock "Relational2" DstPort 1 } Branch { Points [0, 0; 30, 0] Branch { DstBlock "Concat5" DstPort 2 } Branch { Points [0, 115] DstBlock "Concat1" DstPort 2 } } } Line { SrcBlock "Concat4" SrcPort 1 DstBlock "AddSub1" DstPort 2 } Line { SrcBlock "Concat1" SrcPort 1 DstBlock "Concat4" DstPort 1 } Line { SrcBlock "Constant2" SrcPort 1 DstBlock "Concat1" DstPort 1 } Line { SrcBlock "Concat5" SrcPort 1 DstBlock "Concat2" DstPort 1 } Line { SrcBlock "Constant3" SrcPort 1 DstBlock "Concat5" DstPort 1 } Line { SrcBlock "5LSB" SrcPort 1 Points [190, 0] Branch { Points [0, -85] DstBlock "Concat6" DstPort 1 } Branch { DstBlock "Concat7" DstPort 1 } } Line { SrcBlock "Concat6" SrcPort 1 DstBlock "Match Addr B" DstPort 1 } Line { SrcBlock "Concat7" SrcPort 1 DstBlock "Match Addr A" DstPort 1 } Line { SrcBlock "4MSB" SrcPort 1 DstBlock "Concat6" DstPort 2 } Line { SrcBlock "4MSB1" SrcPort 1 DstBlock "Concat7" DstPort 2 } Line { SrcBlock "Constant5" SrcPort 1 DstBlock "Concat8" DstPort 1 } Line { SrcBlock "Clks per Samp Counter1" SrcPort 1 Points [90, 0] Branch { DstBlock "Concat8" DstPort 2 } Branch { Points [0, 90] DstBlock "Concat9" DstPort 2 } } Line { SrcBlock "Constant4" SrcPort 1 DstBlock "Concat9" DstPort 1 } Line { SrcBlock "Concat8" SrcPort 1 Points [55, 0; 0, 115] DstBlock "4MSB" DstPort 1 } Line { SrcBlock "Concat9" SrcPort 1 Points [50, 0; 0, 110] DstBlock "4MSB1" DstPort 1 } Line { SrcBlock "Bit Valid" SrcPort 1 DstBlock "Posedge1" DstPort 1 } Line { SrcBlock "Posedge1" SrcPort 1 Points [0, 120] Branch { DstBlock "Sym Offset Counter" DstPort 1 } Branch { Points [0, 75] Branch { DstBlock "Logical" DstPort 1 } Branch { Points [0, 70] Branch { DstBlock "Clks per Samp Counter" DstPort 1 } Branch { Points [0, 280] DstBlock "Clks per Samp Counter1" DstPort 1 } } } } Line { SrcBlock "Constant6" SrcPort 1 DstBlock "Relational1" DstPort 2 } Line { SrcBlock "Relational1" SrcPort 1 DstBlock "Logical" DstPort 2 } Line { SrcBlock "Logical" SrcPort 1 Points [0, -20; -15, 0; 0, -30] DstBlock "Rx Sym Counter" DstPort 1 } Annotation { Name "Addr B = (Addr A + 8) % 16" Position [830, 523] } } } Block { BlockType SubSystem Name "Bit Hist RAM" SID "16887" Ports [4, 2] Position [565, 460, 670, 540] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Bit Hist RAM" Location [2, 70, 1830, 1180] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Rx Bit" SID "16888" Position [265, 443, 295, 457] IconDisplay "Port number" } Block { BlockType Inport Name "Rx Bit WrEn" SID "16889" Position [265, 478, 295, 492] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "Addr A" SID "16890" Position [265, 513, 295, 527] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "Addr B" SID "16891" Position [265, 548, 295, 562] Port "4" IconDisplay "Port number" } Block { BlockType Scope Name "Bit History RAM" SID "16892" Ports [9] Position [1005, 244, 1060, 426] ZOrder -16 Floating off Location [1, 45, 1833, 1199] Open off NumInputPorts "9" ZoomMode "yonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" axes9 "%" } List { ListType ScopeGraphics FigureColor "[0.5 0.5 0.5]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "60000" YMin "0~0~-0.1~0~0~0~0~-1~-1" YMax "20~400~1.1~1~15000~15000~6000000000~1~1" SaveName "ScopeData2" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType Reference Name "Convert1" SID "16893" Ports [1, 1] Position [365, 508, 410, 532] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "15" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "45,24,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 24 24 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 24 24 0 ]);\npatch([15.325 19.66 22.66 25.66 28.66 22.66 18.325 15.325 ],[15" ".33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([18.325 22.66 19.66 15.325 18.325 ],[12.33 12." "33 15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([15.325 19.66 22.66 18.325 15.325 ],[9.33 9.33 12.33 12.33 " "9.33 ],[1 1 1 ]);\npatch([18.325 28.66 25.66 22.66 19.66 15.325 18.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncol" "or('black');port_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "16894" Ports [1, 1] Position [365, 543, 410, 567] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "15" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "45,24,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 24 24 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 24 24 0 ]);\npatch([15.325 19.66 22.66 25.66 28.66 22.66 18.325 15.325 ],[15" ".33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([18.325 22.66 19.66 15.325 18.325 ],[12.33 12." "33 15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([15.325 19.66 22.66 18.325 15.325 ],[9.33 9.33 12.33 12.33 " "9.33 ],[1 1 1 ]);\npatch([18.325 28.66 25.66 22.66 19.66 15.325 18.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncol" "or('black');port_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Demod Bit History RAM" SID "16895" Ports [4, 2] Position [505, 435, 625, 570] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Black Box" SourceType "Xilinx Black Box Block" infoedit " Incorporates black box HDL and simulation model into a System Generator design.

You must " "supply a Black Box with certain information about the HDL component you would like to bring into System Generato" "r. This information is provided through a Matlab function.

When \"Simulation mode\" is set to \"Inactive\"" ", you will typically want to provide a separate simulation model by using a Simulation Multiplexer.
When \"Si" "mulation mode\" is set to \"External co-simulator\", you must include a ModelSim block in the design." init_code "bit_match_ram_config" sim_method "ISE Simulator" verbose off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "blackbox2" sg_icon_stat "120,135,4,2,white,blue,0,b5734dd4,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 120 120 0 0 ],[0 0 135 135 0 ],[0.77 " "0.82 0.91 ]);\nplot([0 120 120 0 0 ],[0 0 135 135 0 ]);\npatch([22.175 46.74 63.74 80.74 97.74 63.74 39.175 22.1" "75 ],[85.87 85.87 102.87 85.87 102.87 102.87 102.87 85.87 ],[1 1 1 ]);\npatch([39.175 63.74 46.74 22.175 39.175 " "],[68.87 68.87 85.87 85.87 68.87 ],[0.931 0.946 0.973 ]);\npatch([22.175 46.74 63.74 39.175 22.175 ],[51.87 51.8" "7 68.87 68.87 51.87 ],[1 1 1 ]);\npatch([39.175 97.74 80.74 63.74 46.74 22.175 39.175 ],[34.87 34.87 51.87 34.87" " 51.87 51.87 34.87 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: beg" "in icon text');\ncolor('black');port_label('input',1,'bit_in');\ncolor('black');port_label('input',2,'bit_in_wr_" "en');\ncolor('black');port_label('input',3,'addr_a');\ncolor('black');port_label('input',4,'addr_b');\ncolor('bl" "ack');port_label('output',1,'dout_a');\ncolor('black');port_label('output',2,'dout_b');\nfprintf('','COMMENT: en" "d icon text');" } Block { BlockType From Name "From" SID "16896" Position [615, 265, 725, 285] ZOrder -9 ShowName off GotoTag "sym_index" TagVisibility "global" } Block { BlockType From Name "From1" SID "16897" Position [615, 245, 725, 265] ZOrder -9 ShowName off GotoTag "sym_offset" TagVisibility "global" } Block { BlockType Reference Name "Gateway Out1" SID "16898" Ports [1, 1] Position [855, 249, 890, 261] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Sym Offset Index" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "16899" Ports [1, 1] Position [855, 269, 890, 281] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Sym Index" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "16900" Ports [1, 1] Position [855, 289, 890, 301] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Rx Bit In" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "16901" Ports [1, 1] Position [855, 309, 890, 321] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Bit Wr En" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "16902" Ports [1, 1] Position [855, 329, 890, 341] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Addr A" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "16903" Ports [1, 1] Position [855, 349, 890, 361] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Addr B" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "16904" Ports [1, 1] Position [855, 369, 890, 381] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Data Out A" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Outport Name "RAM Out B" SID "16905" Position [740, 528, 770, 542] IconDisplay "Port number" } Block { BlockType Outport Name "RAM Out A" SID "16906" Position [740, 463, 770, 477] Port "2" IconDisplay "Port number" } Line { Name "Sym Offset Index" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 DstBlock "Bit History RAM" DstPort 1 } Line { SrcBlock "Rx Bit" SrcPort 1 Points [165, 0] Branch { Labels [2, 0] Points [0, -155] DstBlock "Gateway Out3" DstPort 1 } Branch { DstBlock "Demod Bit History RAM" DstPort 1 } } Line { SrcBlock "Convert1" SrcPort 1 Points [60, 0] Branch { DstBlock "Demod Bit History RAM" DstPort 3 } Branch { Labels [2, 0] Points [0, -185] DstBlock "Gateway Out5" DstPort 1 } } Line { SrcBlock "Convert2" SrcPort 1 Points [65, 0] Branch { DstBlock "Demod Bit History RAM" DstPort 4 } Branch { Labels [2, 0] Points [0, -200] DstBlock "Gateway Out6" DstPort 1 } } Line { Name "Sym Index" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 DstBlock "Bit History RAM" DstPort 2 } Line { Name "Rx Bit In" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 DstBlock "Bit History RAM" DstPort 3 } Line { Name "Bit Wr En" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 DstBlock "Bit History RAM" DstPort 4 } Line { Name "Addr A" Labels [1, 0] SrcBlock "Gateway Out5" SrcPort 1 DstBlock "Bit History RAM" DstPort 5 } Line { Name "Addr B" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 DstBlock "Bit History RAM" DstPort 6 } Line { SrcBlock "Demod Bit History RAM" SrcPort 1 Points [30, 0] Branch { Labels [2, 0] Points [0, -95] DstBlock "Gateway Out7" DstPort 1 } Branch { DstBlock "RAM Out A" DstPort 1 } } Line { Name "Data Out A" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 DstBlock "Bit History RAM" DstPort 7 } Line { SrcBlock "From1" SrcPort 1 DstBlock "Gateway Out1" DstPort 1 } Line { SrcBlock "From" SrcPort 1 DstBlock "Gateway Out2" DstPort 1 } Line { SrcBlock "Rx Bit WrEn" SrcPort 1 Points [170, 0] Branch { Points [0, -170] DstBlock "Gateway Out4" DstPort 1 } Branch { DstBlock "Demod Bit History RAM" DstPort 2 } } Line { SrcBlock "Addr A" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Demod Bit History RAM" SrcPort 2 DstBlock "RAM Out B" DstPort 1 } Line { SrcBlock "Addr B" SrcPort 1 DstBlock "Convert2" DstPort 1 } } } Block { BlockType Reference Name "Delay" SID "16907" Ports [1, 1] Position [650, 547, 685, 573] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,26,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 26 26 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[16.33 16" ".33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[13.33 13.33 16.33" " 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[10.33 10.33 13.33 13.33 10.33 ]," "[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('bl" "ack');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay1" SID "17904" Ports [2, 1] Position [545, 696, 585, 734] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en on latency "3" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "40,38,2,1,white,blue,0,aa1406d5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 38 38 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 38 38 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[24.55 24.55 29." "55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[19.55 19.55 24.55 24.55 19." "55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1 1 ]);\npa" "tch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('inp" "ut',2,'en');\n\ncolor('black');disp('z^{-3}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay2" SID "17905" Ports [2, 1] Position [545, 661, 585, 699] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en on latency "3" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "40,38,2,1,white,blue,0,aa1406d5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 38 38 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 38 38 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[24.55 24.55 29." "55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[19.55 19.55 24.55 24.55 19." "55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1 1 ]);\npa" "tch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('inp" "ut',2,'en');\n\ncolor('black');disp('z^{-3}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay3" SID "16910" Ports [1, 1] Position [1300, 537, 1335, 563] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,26,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 26 26 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[16.33 16" ".33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[13.33 13.33 16.33" " 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[10.33 10.33 13.33 13.33 10.33 ]," "[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('bl" "ack');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay4" SID "17862" Ports [1, 1] Position [275, 392, 310, 418] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,26,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 26 26 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[16.33 16" ".33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[13.33 13.33 16.33" " 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[10.33 10.33 13.33 13.33 10.33 ]," "[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('bl" "ack');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay5" SID "17863" Ports [1, 1] Position [275, 427, 310, 453] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,26,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 26 26 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[16.33 16" ".33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[13.33 13.33 16.33" " 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[10.33 10.33 13.33 13.33 10.33 ]," "[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('bl" "ack');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay6" SID "17906" Ports [1, 1] Position [650, 667, 685, 693] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,26,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 26 26 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[16.33 16" ".33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[13.33 13.33 16.33" " 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[10.33 10.33 13.33 13.33 10.33 ]," "[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('bl" "ack');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay7" SID "17870" Ports [1, 1] Position [845, 332, 880, 358] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,26,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 26 26 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[16.33 16" ".33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[13.33 13.33 16.33" " 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[10.33 10.33 13.33 13.33 10.33 ]," "[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('bl" "ack');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay8" SID "17907" Ports [1, 1] Position [650, 707, 685, 733] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,26,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 26 26 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[16.33 16" ".33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[13.33 13.33 16.33" " 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[10.33 10.33 13.33 13.33 10.33 ]," "[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('bl" "ack');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out1" SID "16911" Ports [1, 1] Position [1410, 259, 1445, 271] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Output Bit Valid" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out10" SID "17873" Ports [1, 1] Position [1410, 199, 1445, 211] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Output Bit Latch En" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "16912" Ports [1, 1] Position [1405, 99, 1440, 111] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Input Bit Valid" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "16913" Ports [1, 1] Position [1405, 119, 1440, 131] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Input Bit" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "16914" Ports [1, 1] Position [1405, 139, 1440, 151] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Input IQ Mag" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "16915" Ports [1, 1] Position [1410, 239, 1445, 251] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Sel Phase Valid" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "17404" Ports [1, 1] Position [1410, 219, 1445, 231] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Correct Phase" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "17844" Ports [1, 1] Position [1410, 279, 1445, 291] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Output Bit" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "17865" Ports [1, 1] Position [1410, 159, 1445, 171] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Despread Phase" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out9" SID "17872" Ports [1, 1] Position [1410, 179, 1445, 191] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Outbut Bit Latch Input" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Logical3" SID "16916" Ports [3, 1] Position [1155, 502, 1200, 598] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "45,96,3,1,white,blue,0,98d76266,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 96 96 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 96 96 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[54.66 54.66 6" "0.66 54.66 60.66 60.66 60.66 54.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[48.66 48.66 54.66 54.66 48" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[42.66 42.66 48.66 48.66 42.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[36.66 36.66 42.66 36.66 42.66 42.66 36.66 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\ncolor('black');disp" "('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Matching" SID "16917" Ports [8, 2] Position [780, 460, 945, 780] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Matching" Location [2, 70, 1830, 1180] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Hist RAM A" SID "16918" Position [340, 158, 370, 172] IconDisplay "Port number" } Block { BlockType Inport Name "Hist RAM B" SID "16919" Position [340, 198, 370, 212] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "New Bit" SID "16920" Position [340, 88, 370, 102] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "Match Addr A" SID "16921" Position [340, 278, 370, 292] ZOrder -1 NamePlacement "alternate" Port "4" IconDisplay "Port number" } Block { BlockType Inport Name "Match Addr B" SID "16922" Position [340, 293, 370, 307] ZOrder -1 Port "5" IconDisplay "Port number" } Block { BlockType Inport Name "Despread Phase " SID "16923" Position [340, 603, 370, 617] ZOrder -1 Port "6" IconDisplay "Port number" } Block { BlockType Inport Name "IQ Mag" SID "16924" Position [340, 643, 370, 657] ZOrder -1 Port "7" IconDisplay "Port number" } Block { BlockType Inport Name "Reset" SID "16925" Position [340, 703, 370, 717] ZOrder -1 Port "8" IconDisplay "Port number" } Block { BlockType Reference Name "Constant" SID "17878" Ports [0, 1] Position [1365, 342, 1420, 368] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "4" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "5" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "55,26,0,1,white,blue,0,85f36853,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 26 26 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\npatch([20.325 24.66 27.66 30.66 33.66 27.66 23.325 20.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([23.325 27.66 24.66 20.325 23.325 ],[13.33 13." "33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([20.325 24.66 27.66 23.325 20.325 ],[10.33 10.33 13.33 13.3" "3 10.33 ],[1 1 1 ]);\npatch([23.325 33.66 30.66 27.66 24.66 20.325 23.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7." "33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n" "color('black');port_label('output',1,'4');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out1" SID "16926" Ports [1, 1] Position [1365, 159, 1400, 171] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Despread Phase" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out18" SID "16930" Ports [1, 1] Position [1365, 99, 1400, 111] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Match" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "16931" Ports [1, 1] Position [1365, 119, 1400, 131] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Search Done" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "16932" Ports [1, 1] Position [1365, 139, 1400, 151] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "IQ Mag" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "16933" Ports [1, 1] Position [1365, 179, 1400, 191] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Sel Phase" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "16934" Ports [1, 1] Position [1365, 199, 1400, 211] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Sel Phase Valid" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "17847" Ports [1, 1] Position [1365, 39, 1400, 51] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "New Bit" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "17848" Ports [1, 1] Position [1365, 59, 1400, 71] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Score" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "17849" Ports [1, 1] Position [1365, 79, 1400, 91] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Score Valid" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType SubSystem Name "Mask 1 RAM" SID "16935" Ports [2, 2] Position [440, 505, 540, 540] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Mask 1 RAM" Location [2, 70, 1830, 1180] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Rd Addr A" SID "16936" Position [180, 318, 210, 332] IconDisplay "Port number" } Block { BlockType Inport Name "Rd Addr B" SID "16937" Position [180, 393, 210, 407] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Constant4" SID "16938" Ports [0, 1] Position [740, 439, 755, 461] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Boolean" arith_type "Boolean" n_bits "16" bin_pt "14" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "8" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "15,22,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 15 15 0 0 ],[0 0 22 22 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[13.22 13.22 " "15.22 13.22 15.22 15.22 15.22 13.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[11.22 11.22 13.22 13.22 11." "22 ],[0.931 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[9.22 9.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([" "4.55 11.44 9.44 7.44 5.44 2.55 4.55 ],[7.22 7.22 9.22 7.22 9.22 9.22 7.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'0'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant6" SID "16939" Ports [0, 1] Position [740, 414, 755, 436] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "8" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "15,22,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 15 15 0 0 ],[0 0 22 22 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[13.22 13.22 " "15.22 13.22 15.22 15.22 15.22 13.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[11.22 11.22 13.22 13.22 11." "22 ],[0.931 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[9.22 9.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([" "4.55 11.44 9.44 7.44 5.44 2.55 4.55 ],[7.22 7.22 9.22 7.22 9.22 9.22 7.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'0'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert" SID "16940" Ports [1, 1] Position [350, 345, 390, 365] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "ceil(log2(DSSS_NUM_SYMS_PER_OFFSET))" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "40,20,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 20 20 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 20 20 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[12.22" " 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[10.22 10.22 12." "22 12.22 10.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1" " 1 1 ]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');" "port_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From1" SID "16941" Position [175, 286, 405, 304] ZOrder -9 ShowName off GotoTag "reg_Mask_1_WrEn" TagVisibility "global" } Block { BlockType From Name "From3" SID "16942" Position [495, 341, 725, 359] ZOrder -9 ShowName off GotoTag "reg_Mask_1_RAM_Wr_Data" TagVisibility "global" } Block { BlockType From Name "From6" SID "16943" Position [80, 346, 310, 364] ZOrder -9 ShowName off GotoTag "reg_RAMs_Wr_Addr" TagVisibility "global" } Block { BlockType Reference Name "Mask 1 RAM" SID "16944" Ports [6, 2] Position [805, 306, 920, 469] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Dual Port RAM" SourceType "Xilinx Dual Port Random Access Memory Block" depth "DSSS_NUM_SYMS_PER_OFFSET" initVector "mask_1_ram_init" distributed_mem "Block RAM" init_a "0" init_b "0" rst_a off rst_b off en_a off en_b off latency "1" write_mode_A "Read After Write" write_mode_B "Read After Write" dbl_ovrd off optimize "Area" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "dpram" sg_icon_stat "115,163,6,2,white,blue,0,28af736d,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 115 115 0 0 ],[0 0 163 163 0 ],[0.77 " "0.82 0.91 ]);\nplot([0 115 115 0 0 ],[0 0 163 163 0 ]);\npatch([21.4 44.52 60.52 76.52 92.52 60.52 37.4 21.4 ],[" "98.76 98.76 114.76 98.76 114.76 114.76 114.76 98.76 ],[1 1 1 ]);\npatch([37.4 60.52 44.52 21.4 37.4 ],[82.76 82." "76 98.76 98.76 82.76 ],[0.931 0.946 0.973 ]);\npatch([21.4 44.52 60.52 37.4 21.4 ],[66.76 66.76 82.76 82.76 66.7" "6 ],[1 1 1 ]);\npatch([37.4 92.52 76.52 60.52 44.52 21.4 37.4 ],[50.76 50.76 66.76 50.76 66.76 66.76 50.76 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'addra');\ncolor('black');port_label('input',2,'dina');\ncolor('black');port_label(" "'input',3,'wea');\ncolor('black');port_label('input',4,'addrb');\ncolor('black');port_label('input',5,'dinb');\n" "color('black');port_label('input',6,'web');\ncolor('black');port_label('output',1,'A');\ncolor('black');port_lab" "el('output',2,'B');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux" SID "16945" Ports [3, 1] Position [445, 278, 480, 372] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "35,94,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 13.4286 80.5714 94 0 ]" ",[0.77 0.82 0.91 ]);\nplot([0 35 35 0 0 ],[0 13.4286 80.5714 94 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10." "875 5.875 ],[52.55 52.55 57.55 52.55 57.55 57.55 57.55 52.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 " "],[47.55 47.55 52.55 52.55 47.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[42.55 42.55 47" ".55 47.55 42.55 ],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[37.55 37.55 42.55 37.55 42.55 42" ".55 37.55 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon t" "ext');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');" "port_label('input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text" "');" } Block { BlockType Outport Name "Data A" SID "16946" Position [1000, 343, 1030, 357] IconDisplay "Port number" } Block { BlockType Outport Name "Data B" SID "16947" Position [1000, 423, 1030, 437] Port "2" IconDisplay "Port number" } Line { SrcBlock "From3" SrcPort 1 DstBlock "Mask 1 RAM" DstPort 2 } Line { SrcBlock "Rd Addr A" SrcPort 1 DstBlock "Mux" DstPort 2 } Line { SrcBlock "From6" SrcPort 1 DstBlock "Convert" DstPort 1 } Line { SrcBlock "From1" SrcPort 1 Points [10, 0] Branch { DstBlock "Mux" DstPort 1 } Branch { Points [0, 80] DstBlock "Mask 1 RAM" DstPort 3 } } Line { SrcBlock "Mask 1 RAM" SrcPort 2 DstBlock "Data B" DstPort 1 } Line { SrcBlock "Mask 1 RAM" SrcPort 1 DstBlock "Data A" DstPort 1 } Line { SrcBlock "Rd Addr B" SrcPort 1 DstBlock "Mask 1 RAM" DstPort 4 } Line { SrcBlock "Mux" SrcPort 1 DstBlock "Mask 1 RAM" DstPort 1 } Line { SrcBlock "Constant4" SrcPort 1 DstBlock "Mask 1 RAM" DstPort 6 } Line { SrcBlock "Constant6" SrcPort 1 DstBlock "Mask 1 RAM" DstPort 5 } Line { SrcBlock "Convert" SrcPort 1 DstBlock "Mux" DstPort 3 } } } Block { BlockType SubSystem Name "Match Search" SID "16948" Ports [3, 2] Position [895, 445, 1010, 495] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Match Search" Location [2, 70, 1830, 1180] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Score 1" SID "16949" Position [145, 563, 175, 577] IconDisplay "Port number" } Block { BlockType Inport Name "Score 1 Valid" SID "16950" Position [145, 533, 175, 547] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "Reset" SID "16951" Position [560, 343, 590, 357] ZOrder -1 Port "3" IconDisplay "Port number" } Block { BlockType Reference Name "Constant" SID "16952" Ports [0, 1] Position [1040, 472, 1095, 498] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "39" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "6" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "55,26,0,1,white,blue,0,2cb85581,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 26 26 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\npatch([20.325 24.66 27.66 30.66 33.66 27.66 23.325 20.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([23.325 27.66 24.66 20.325 23.325 ],[13.33 13." "33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([20.325 24.66 27.66 23.325 20.325 ],[10.33 10.33 13.33 13.3" "3 10.33 ],[1 1 1 ]);\npatch([23.325 33.66 30.66 27.66 24.66 20.325 23.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7." "33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n" "color('black');port_label('output',1,'39');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay1" SID "16953" Ports [1, 1] Position [480, 397, 515, 423] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,26,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 26 26 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 26 26 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[13.33 13." "33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[10.33 10.33 13.33 13.3" "3 10.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7." "33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n" "\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay5" SID "16955" Ports [1, 1] Position [1280, 637, 1315, 663] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,26,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 26 26 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 26 26 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[13.33 13." "33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[10.33 10.33 13.33 13.3" "3 10.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7." "33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n" "\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay6" SID "16956" Ports [1, 1] Position [485, 137, 520, 163] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,26,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 26 26 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 26 26 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[13.33 13." "33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[10.33 10.33 13.33 13.3" "3 10.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7." "33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n" "\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From1" SID "16957" Position [95, 607, 280, 633] ZOrder -9 ShowName off GotoTag "reg_Match_Thresh_Mask_1" TagVisibility "global" } Block { BlockType From Name "From2" SID "16958" Position [1040, 447, 1225, 473] ZOrder -9 ShowName off GotoTag "regRx_DSSS_SYNC_Search_Time" TagVisibility "global" } Block { BlockType Reference Name "Gateway Out1" SID "16959" Ports [1, 1] Position [1520, 64, 1555, 76] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Score Valid" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "16960" Ports [1, 1] Position [1520, 84, 1555, 96] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Candidate Bit Match" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "16962" Ports [1, 1] Position [1520, 124, 1555, 136] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Searcn Len Count" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "16963" Ports [1, 1] Position [1520, 224, 1555, 236] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Search Done" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "16964" Ports [1, 1] Position [1520, 204, 1555, 216] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Search Event" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "16965" Ports [1, 1] Position [1520, 144, 1555, 156] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Score 1" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Inverter" SID "16966" Ports [1, 1] Position [1425, 503, 1455, 527] BlockMirror on NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "30,24,1,1,white,blue,0,267846e5,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 24 24 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 24 24 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[15.3" "3 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[12.33 12.33 " "15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[9.33 9.33 12.33 12.33 9.33 " "],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('" "black');disp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical" SID "16968" Ports [2, 1] Position [545, 518, 595, 607] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "1" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "50,89,2,1,white,blue,0,e7f9d02e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 89 89 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 89 89 0 ]);\npatch([9.425 19.54 26.54 33.54 40.54 26.54 16.425 9.425 ],[51.7" "7 51.77 58.77 51.77 58.77 58.77 58.77 51.77 ],[1 1 1 ]);\npatch([16.425 26.54 19.54 9.425 16.425 ],[44.77 44.77 " "51.77 51.77 44.77 ],[0.931 0.946 0.973 ]);\npatch([9.425 19.54 26.54 16.425 9.425 ],[37.77 37.77 44.77 44.77 37." "77 ],[1 1 1 ]);\npatch([16.425 40.54 33.54 26.54 19.54 9.425 16.425 ],[30.77 30.77 37.77 30.77 37.77 37.77 30.77" " ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n" "\n\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\nand');\nfprintf('','COMMEN" "T: end icon text');" } Block { BlockType Reference Name "Logical1" SID "16969" Ports [3, 1] Position [985, 399, 1030, 451] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "45,52,3,1,white,blue,0,98d76266,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 52 52 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 52 52 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[32.66 3" "2.66 38.66 32.66 38.66 38.66 38.66 32.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[26.66 26.66 32.66 " "32.66 26.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[20.66 20.66 26.66 26.66 20.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[14.66 14.66 20.66 14.66 20.66 20.66 14.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\ncolor" "('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical6" SID "16973" Ports [3, 1] Position [1485, 609, 1530, 661] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "45,52,3,1,white,blue,0,98d76266,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 52 52 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 52 52 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[32.66 3" "2.66 38.66 32.66 38.66 38.66 38.66 32.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[26.66 26.66 32.66 " "32.66 26.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[20.66 20.66 26.66 26.66 20.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[14.66 14.66 20.66 14.66 20.66 20.66 14.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\ncolor" "('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational2" SID "16975" Ports [2, 1] Position [410, 557, 460, 608] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a>=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "50,51,2,1,white,blue,0,6218dc92,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 51 51 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 51 51 0 ]);\npatch([9.425 19.54 26.54 33.54 40.54 26.54 16.425 9.425 ],[32.7" "7 32.77 39.77 32.77 39.77 39.77 39.77 32.77 ],[1 1 1 ]);\npatch([16.425 26.54 19.54 9.425 16.425 ],[25.77 25.77 " "32.77 32.77 25.77 ],[0.931 0.946 0.973 ]);\npatch([9.425 19.54 26.54 16.425 9.425 ],[18.77 18.77 25.77 25.77 18." "77 ],[1 1 1 ]);\npatch([16.425 40.54 33.54 26.54 19.54 9.425 16.425 ],[11.77 11.77 18.77 11.77 18.77 18.77 11.77" " ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nc" "olor('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('" "output',1,'\\bfa \\geq b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational3" SID "16976" Ports [2, 1] Position [1275, 376, 1325, 489] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a>b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "50,113,2,1,white,blue,0,b5131c97,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 113 113 0 ],[0.77 0." "82 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 113 113 0 ]);\npatch([9.425 19.54 26.54 33.54 40.54 26.54 16.425 9.425 ],[" "63.77 63.77 70.77 63.77 70.77 70.77 70.77 63.77 ],[1 1 1 ]);\npatch([16.425 26.54 19.54 9.425 16.425 ],[56.77 56" ".77 63.77 63.77 56.77 ],[0.931 0.946 0.973 ]);\npatch([9.425 19.54 26.54 16.425 9.425 ],[49.77 49.77 56.77 56.77" " 49.77 ],[1 1 1 ]);\npatch([16.425 40.54 33.54 26.54 19.54 9.425 16.425 ],[42.77 42.77 49.77 42.77 49.77 49.77 4" "2.77 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\ncolor('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_lab" "el('output',1,'\\bfa > b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "S-R Latch" SID "16978" Ports [2, 1] Position [770, 553, 815, 602] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "S-R Latch" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "16979" Position [140, 103, 170, 117] IconDisplay "Port number" } Block { BlockType Inport Name "R" SID "16980" Position [140, 88, 170, 102] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "16981" Ports [0, 1] Position [195, 71, 210, 89] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "15,18,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11.22 " "13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 9.22 " "],[0.931 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([4.55 " "11.44 9.44 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "16982" Ports [1, 1] Position [210, 86, 235, 104] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('outpu" "t',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "16983" Ports [1, 1] Position [210, 101, 235, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('outpu" "t',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "16984" Ports [3, 1] Position [255, 71, 300, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "16985" Position [325, 88, 355, 102] IconDisplay "Port number" } Line { SrcBlock "S" SrcPort 1 DstBlock "Convert2" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "Convert2" SrcPort 1 DstBlock "Register2" DstPort 3 } } } Block { BlockType SubSystem Name "S-R Latch1" SID "16986" Ports [2, 1] Position [1425, 418, 1470, 467] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "S-R Latch1" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "16987" Position [140, 103, 170, 117] IconDisplay "Port number" } Block { BlockType Inport Name "R" SID "16988" Position [140, 88, 170, 102] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "16989" Ports [0, 1] Position [195, 71, 210, 89] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "15,18,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11.22 " "13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 9.22 " "],[0.931 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([4.55 " "11.44 9.44 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "16990" Ports [1, 1] Position [210, 86, 235, 104] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('outpu" "t',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "16991" Ports [1, 1] Position [210, 101, 235, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('outpu" "t',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "16992" Ports [3, 1] Position [255, 71, 300, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "16993" Position [325, 88, 355, 102] IconDisplay "Port number" } Line { SrcBlock "Convert2" SrcPort 1 DstBlock "Register2" DstPort 3 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "S" SrcPort 1 DstBlock "Convert2" DstPort 1 } } } Block { BlockType Scope Name "Search" SID "16994" Ports [9] Position [1670, 48, 1730, 252] ZOrder -16 Floating off Location [1, 45, 1836, 1199] Open off NumInputPorts "9" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" axes9 "%" } List { ListType ScopeGraphics FigureColor "[0.5 0.5 0.5]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "60000" YMin "0~0~0~0~5~-1~-1~-1~-1" YMax "1~1~1~40~60~1~1~1~1" SaveName "ScopeData3" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType Reference Name "Search Len Counter" SID "16995" Ports [2, 1] Position [1170, 367, 1225, 443] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited count" "er is implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "inf" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "8" bin_pt "0" load_pin off rst on en on explicit_period "off" period "1" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "counter" sg_icon_stat "55,76,2,1,white,blue,0,ae3608d6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 76 76 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 76 76 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ],[45" ".77 45.77 52.77 45.77 52.77 52.77 52.77 45.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[38.77 38." "77 45.77 45.77 38.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[31.77 31.77 38.77 38.7" "7 31.77 ],[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[24.77 24.77 31.77 24.77 31.77 31.77" " 24.77 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text" "');\ncolor('black');port_label('input',1,'rst');\ncolor('black');port_label('input',2,'en');\n\ncolor('black');d" "isp('{\\fontsize{14}\\bf++}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Match" SID "16996" Position [1600, 628, 1630, 642] IconDisplay "Port number" } Block { BlockType Outport Name "Search Done" SID "16997" Position [1575, 438, 1605, 452] Port "2" IconDisplay "Port number" } Line { SrcBlock "From1" SrcPort 1 Points [0, -25] DstBlock "Relational2" DstPort 2 } Line { SrcBlock "Score 1" SrcPort 1 Points [120, 0] Branch { DstBlock "Relational2" DstPort 1 } Branch { Points [0, -420] DstBlock "Delay6" DstPort 1 } } Line { SrcBlock "Relational2" SrcPort 1 DstBlock "Logical" DstPort 2 } Line { SrcBlock "Score 1 Valid" SrcPort 1 Points [235, 0] Branch { DstBlock "Logical" DstPort 1 } Branch { Points [0, -130] DstBlock "Delay1" DstPort 1 } } Line { SrcBlock "Search Len Counter" SrcPort 1 Points [15, 0] Branch { DstBlock "Relational3" DstPort 1 } Branch { Points [0, -275] DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "From2" SrcPort 1 DstBlock "Relational3" DstPort 2 } Line { SrcBlock "Logical" SrcPort 1 Points [20, 0] Branch { Points [110, 0] Branch { DstBlock "S-R Latch" DstPort 1 } Branch { Points [0, -470] DstBlock "Gateway Out2" DstPort 1 } } Branch { Points [0, 85] DstBlock "Delay5" DstPort 1 } } Line { SrcBlock "Relational3" SrcPort 1 DstBlock "S-R Latch1" DstPort 1 } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Search Len Counter" DstPort 2 } Line { SrcBlock "S-R Latch" SrcPort 1 Points [20, 0] Branch { Points [0, -155] Branch { DstBlock "Logical1" DstPort 2 } Branch { Points [0, -215] DstBlock "Gateway Out6" DstPort 1 } } Branch { Points [600, 0; 0, 40] DstBlock "Logical6" DstPort 1 } } Line { SrcBlock "Reset" SrcPort 1 Points [145, 0] Branch { Points [0, 240] DstBlock "S-R Latch" DstPort 2 } Branch { Points [300, 0] Branch { Points [345, 0; 0, 105] DstBlock "S-R Latch1" DstPort 2 } Branch { Points [0, 35] DstBlock "Search Len Counter" DstPort 1 } } } Line { SrcBlock "Inverter" SrcPort 1 Points [-45, 0] Branch { Points [0, 120] DstBlock "Logical6" DstPort 2 } Branch { Points [-405, 0] DstBlock "Logical1" DstPort 3 } } Line { SrcBlock "S-R Latch1" SrcPort 1 Points [30, 0] Branch { Points [0, 70] DstBlock "Inverter" DstPort 1 } Branch { DstBlock "Search Done" DstPort 1 } Branch { DstBlock "Gateway Out5" DstPort 1 } } Line { Name "Score Valid" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 DstBlock "Search" DstPort 1 } Line { Name "Candidate Bit Match" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 DstBlock "Search" DstPort 2 } Line { Name "Searcn Len Count" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 DstBlock "Search" DstPort 4 } Line { Name "Search Done" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 DstBlock "Search" DstPort 9 } Line { Name "Search Event" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 DstBlock "Search" DstPort 8 } Line { Name "Score 1" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 DstBlock "Search" DstPort 5 } Line { SrcBlock "Delay1" SrcPort 1 Points [135, 0] Branch { DstBlock "Logical1" DstPort 1 } Branch { Points [0, -340] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "Delay6" SrcPort 1 DstBlock "Gateway Out7" DstPort 1 } Line { SrcBlock "Logical6" SrcPort 1 DstBlock "Match" DstPort 1 } Line { SrcBlock "Delay5" SrcPort 1 DstBlock "Logical6" DstPort 3 } } } Block { BlockType Scope Name "Matching" SID "16998" Ports [9] Position [1510, 23, 1570, 227] ZOrder -16 Floating off Location [1, 45, 1836, 1199] Open off NumInputPorts "9" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" axes9 "%" } List { ListType ScopeGraphics FigureColor "[0.5 0.5 0.5]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "82800 " YMin "0~0~0~0~0~0~0~0~0.95" YMax "1~50~1~1~1~1~20~20~1.05" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType SubSystem Name "Matching - Mask 1" SID "16999" Ports [7, 2] Position [670, 426, 800, 544] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Matching - Mask 1" Location [2, 70, 1830, 1180] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "New Bit" SID "17000" Position [265, 248, 295, 262] IconDisplay "Port number" } Block { BlockType Inport Name "Hist A" SID "17001" Position [275, 353, 305, 367] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "Hist B" SID "17002" Position [275, 473, 305, 487] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "Target A" SID "17003" Position [275, 393, 305, 407] Port "4" IconDisplay "Port number" } Block { BlockType Inport Name "Target B" SID "17004" Position [275, 513, 305, 527] Port "5" IconDisplay "Port number" } Block { BlockType Inport Name "Mask A" SID "17005" Position [275, 433, 305, 447] Port "6" IconDisplay "Port number" } Block { BlockType Inport Name "Mask B" SID "17006" Position [275, 553, 305, 567] Port "7" IconDisplay "Port number" } Block { BlockType SubSystem Name "32b Match A" SID "17007" Ports [3, 1] Position [445, 343, 540, 457] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "32b Match A" Location [2, 70, 1830, 1180] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Hist" SID "17008" Position [25, 33, 55, 47] IconDisplay "Port number" } Block { BlockType Inport Name "Target" SID "17009" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "Mask" SID "17010" Position [25, 113, 55, 127] Port "3" IconDisplay "Port number" } Block { BlockType Reference Name "Count Ones" SID "17011" Ports [1, 1] Position [345, 40, 425, 90] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Black Box" SourceType "Xilinx Black Box Block" infoedit " Incorporates black box HDL and simulation model into a System Generator design.

You must " "supply a Black Box with certain information about the HDL component you would like to bring into System Generato" "r. This information is provided through a Matlab function.

When \"Simulation mode\" is set to \"Inactive\"" ", you will typically want to provide a separate simulation model by using a Simulation Multiplexer.
When \"Si" "mulation mode\" is set to \"External co-simulator\", you must include a ModelSim block in the design." init_code "count_ones_32b_config" sim_method "ISE Simulator" verbose off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "blackbox2" sg_icon_stat "80,50,1,1,white,blue,0,fb991cc3,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 80 80 0 0 ],[0 0 50 50 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 80 80 0 0 ],[0 0 50 50 0 ]);\npatch([24.425 34.54 41.54 48.54 55.54 41.54 31.425 24.425 ],[32" ".77 32.77 39.77 32.77 39.77 39.77 39.77 32.77 ],[1 1 1 ]);\npatch([31.425 41.54 34.54 24.425 31.425 ],[25.77 25." "77 32.77 32.77 25.77 ],[0.931 0.946 0.973 ]);\npatch([24.425 34.54 41.54 31.425 24.425 ],[18.77 18.77 25.77 25.7" "7 18.77 ],[1 1 1 ]);\npatch([31.425 55.54 48.54 41.54 34.54 24.425 31.425 ],[11.77 11.77 18.77 11.77 18.77 18.77" " 11.77 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text" "');\ncolor('black');port_label('input',1,'x');\ncolor('black');port_label('output',1,'num_ones');\nfprintf('','C" "OMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "17012" Ports [2, 1] Position [245, 46, 280, 84] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,38,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 38 38 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 38 38 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[24.55 24." "55 29.55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[19.55 19.55 24.55 2" "4.55 19.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black" "');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical3" SID "17013" Ports [2, 1] Position [120, 26, 160, 84] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "XNOR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,58,2,1,white,blue,0,11dbf875,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 58 58 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 58 58 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[34.55 34." "55 39.55 34.55 39.55 39.55 39.55 34.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[29.55 29.55 34.55 3" "4.55 29.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[24.55 24.55 29.55 29.55 24.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[19.55 19.55 24.55 19.55 24.55 24.55 19.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('b" "lack');disp('xnor');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Num Match" SID "17014" Position [480, 58, 510, 72] IconDisplay "Port number" } Line { SrcBlock "Target" SrcPort 1 DstBlock "Logical3" DstPort 2 } Line { SrcBlock "Hist" SrcPort 1 DstBlock "Logical3" DstPort 1 } Line { SrcBlock "Logical3" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Mask" SrcPort 1 Points [125, 0; 0, -45] DstBlock "Logical1" DstPort 2 } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Count Ones" DstPort 1 } Line { SrcBlock "Count Ones" SrcPort 1 DstBlock "Num Match" DstPort 1 } } } Block { BlockType SubSystem Name "32b Match B" SID "17015" Ports [3, 1] Position [445, 463, 540, 577] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "32b Match B" Location [-1918, 70, -2, 1180] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Hist" SID "17016" Position [25, 33, 55, 47] IconDisplay "Port number" } Block { BlockType Inport Name "Target" SID "17017" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "Mask" SID "17018" Position [25, 113, 55, 127] Port "3" IconDisplay "Port number" } Block { BlockType Reference Name "Count Ones" SID "17019" Ports [1, 1] Position [345, 40, 425, 90] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Black Box" SourceType "Xilinx Black Box Block" infoedit " Incorporates black box HDL and simulation model into a System Generator design.

You must " "supply a Black Box with certain information about the HDL component you would like to bring into System Generato" "r. This information is provided through a Matlab function.

When \"Simulation mode\" is set to \"Inactive\"" ", you will typically want to provide a separate simulation model by using a Simulation Multiplexer.
When \"Si" "mulation mode\" is set to \"External co-simulator\", you must include a ModelSim block in the design." init_code "count_ones_32b_config" sim_method "ISE Simulator" verbose off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "blackbox2" sg_icon_stat "80,50,1,1,white,blue,0,fb991cc3,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 80 80 0 0 ],[0 0 50 50 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 80 80 0 0 ],[0 0 50 50 0 ]);\npatch([24.425 34.54 41.54 48.54 55.54 41.54 31.425 24.425 ],[32" ".77 32.77 39.77 32.77 39.77 39.77 39.77 32.77 ],[1 1 1 ]);\npatch([31.425 41.54 34.54 24.425 31.425 ],[25.77 25." "77 32.77 32.77 25.77 ],[0.931 0.946 0.973 ]);\npatch([24.425 34.54 41.54 31.425 24.425 ],[18.77 18.77 25.77 25.7" "7 18.77 ],[1 1 1 ]);\npatch([31.425 55.54 48.54 41.54 34.54 24.425 31.425 ],[11.77 11.77 18.77 11.77 18.77 18.77" " 11.77 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text" "');\ncolor('black');port_label('input',1,'x');\ncolor('black');port_label('output',1,'num_ones');\nfprintf('','C" "OMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "17020" Ports [2, 1] Position [245, 46, 280, 84] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,38,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 38 38 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 38 38 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[24.55 24." "55 29.55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[19.55 19.55 24.55 2" "4.55 19.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black" "');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical3" SID "17021" Ports [2, 1] Position [120, 26, 160, 84] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "XNOR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,58,2,1,white,blue,0,11dbf875,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 58 58 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 58 58 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[34.55 34." "55 39.55 34.55 39.55 39.55 39.55 34.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[29.55 29.55 34.55 3" "4.55 29.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[24.55 24.55 29.55 29.55 24.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[19.55 19.55 24.55 19.55 24.55 24.55 19.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('b" "lack');disp('xnor');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Num Match" SID "17022" Position [480, 58, 510, 72] IconDisplay "Port number" } Line { SrcBlock "Count Ones" SrcPort 1 DstBlock "Num Match" DstPort 1 } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Count Ones" DstPort 1 } Line { SrcBlock "Mask" SrcPort 1 Points [125, 0; 0, -45] DstBlock "Logical1" DstPort 2 } Line { SrcBlock "Logical3" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Hist" SrcPort 1 DstBlock "Logical3" DstPort 1 } Line { SrcBlock "Target" SrcPort 1 DstBlock "Logical3" DstPort 2 } } } Block { BlockType Reference Name "Accumulator" SID "17023" Ports [2, 1] Position [775, 401, 835, 459] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Accumulator" SourceType "Xilinx Accumulator Block" infoedit "Adder or subtracter-based accumulator. Output type and binary point position match the input.
Hardware notes: When \"Reinitialize with input 'b' on reset\" is selected, the accumulator is forced to ru" "n at the system rate even if the input 'b' is running at a slower rate." operation "Add" n_bits "log2(DSSS_BIT_MATCH_RAM_WIDTH) + 2 + log2(DSSS_CLKS_PER_SAMP)" overflow "Flag as error" scale "1" rst on infoeditControl "reset for floating point data type must be asserted for a minimum of 2 cycles" hasbypass on en off latency "0" dbl_ovrd off msb_inp "100" msb "100" lsb "-100" use_behavioral_HDL on implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "accum" sg_icon_stat "60,58,2,1,white,blue,0,6949434e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 58 58 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 58 58 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[37.88 37" ".88 45.88 37.88 45.88 45.88 45.88 37.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[29.88 29.88 37.88 37." "88 29.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[21.88 21.88 29.88 29.88 21.88 ],[1 1 1 ]" ");\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[13.88 13.88 21.88 13.88 21.88 21.88 13.88 ],[0.931 0.946 0." "973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port" "_label('input',1,'b');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'\\bf+" "=b','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay" SID "17024" Ports [1, 1] Position [475, 241, 505, 269] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "2" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "30,28,1,1,white,blue,0,85ce9542,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 18.4" "4 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 18.44 " "14.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\np" "atch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-" "2}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out1" SID "17025" Ports [1, 1] Position [1060, 219, 1095, 231] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out2" SID "17026" Ports [1, 1] Position [1060, 239, 1095, 251] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out3" SID "17027" Ports [1, 1] Position [1060, 259, 1095, 271] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out4" SID "17028" Ports [1, 1] Position [1060, 279, 1095, 291] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out5" SID "17029" Ports [1, 1] Position [1060, 199, 1095, 211] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Mask Sum" SID "17030" Ports [2, 1] Position [625, 386, 685, 444] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL off hw_selection "Fabric" pipelined off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" sg_icon_stat "60,58,2,1,white,blue,0,e139daf6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 58 58 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 58 58 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[37.88 37" ".88 45.88 37.88 45.88 45.88 45.88 37.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[29.88 29.88 37.88 37." "88 29.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[21.88 21.88 29.88 29.88 21.88 ],[1 1 1 ]" ");\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[13.88 13.88 21.88 13.88 21.88 21.88 13.88 ],[0.931 0.946 0." "973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port" "_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bf{a " "+ b}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Scope Name "Masked Matching" SID "17031" Ports [5] Position [1150, 191, 1190, 299] ZOrder -16 Floating off Location [6, 40, 1838, 1194] Open off NumInputPorts "5" ZoomMode "yonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" } List { ListType ScopeGraphics FigureColor "[0.5 0.5 0.5]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "60000" YMin "0~0~0~0~0" YMax "25~25~40~200~1" SaveName "ScopeData1" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType SubSystem Name "Safe ToUint10" SID "17032" Ports [1, 1] Position [920, 415, 965, 445] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Safe ToUint10" Location [202, 74, 1830, 1176] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" SID "17033" Position [160, 218, 190, 232] IconDisplay "Port number" } Block { BlockType SubSystem Name "Indet Check" SID "17034" Ports [1, 1] Position [325, 210, 380, 240] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Indet Check" Location [149, 142, 2075, 1366] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "In1" SID "17035" Position [25, 53, 55, 67] IconDisplay "Port number" } Block { BlockType Reference Name "Constant" SID "17036" Ports [0, 1] Position [185, 79, 210, 101] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "10" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,400,346" block_type "constant" block_version "10.1.3" sg_icon_stat "25,22,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 22 22 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[14.33 " "14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 1 " "1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('output',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Disregard Subsystem" SID "17037" Tag "discardX" Ports [] Position [348, 257, 406, 315] ShowName off AttributesFormatString "Disregard Subsystem\\nFor Generation" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Disregard Subsystem" SourceType "Xilinx Disregard Subsystem For Generation Block" infoedit "Place this block into a subsystem to have System Generator ignore the subsystem during code gener" "ation. This block can be used in combination with the Simulation Multiplexer block to provide an alternative sim" "ulation model for another subsystem (e.g., to provide a simulation model for a black box)." has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "disregard" sg_icon_stat "58,58,-1,-1,darkgray,black,0,07734,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 58 58 0 0 ],[0 0 58 58 0 ],[0.1 0.1 0" ".1 ]);\nplot([0 58 58 0 0 ],[0 0 58 58 0 ]);\npatch([11.2 22.76 30.76 38.76 46.76 30.76 19.2 11.2 ],[37.88 37.88" " 45.88 37.88 45.88 45.88 45.88 37.88 ],[0.33 0.33 0.33 ]);\npatch([19.2 30.76 22.76 11.2 19.2 ],[29.88 29.88 37." "88 37.88 29.88 ],[0.261 0.261 0.261 ]);\npatch([11.2 22.76 30.76 19.2 11.2 ],[21.88 21.88 29.88 29.88 21.88 ],[0" ".33 0.33 0.33 ]);\npatch([19.2 46.76 38.76 30.76 22.76 11.2 19.2 ],[13.88 13.88 21.88 13.88 21.88 21.88 13.88 ]," "[0.261 0.261 0.261 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nfpri" "ntf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway In" SID "17038" Ports [1, 1] Position [165, 30, 230, 50] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to X" "ilinx fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top level" " input ports." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "16" bin_pt "14" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0.93" " 0.65 ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12.22" " 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 12." "22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1" " 1 1 ]);\npatch([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 " "0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');po" "rt_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfpri" "ntf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Indeterminate Probe" SID "17039" Ports [1, 1] Position [120, 27, 145, 53] LibraryVersion "1.2" LinkData { BlockName "Gateway Out" DialogParameters { sg_icon_stat "40,20,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0.93" " 0.65 ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12.22" " 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 12." "22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1" " 1 1 ]);\npatch([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 " "0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');po" "rt_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfpr" "intf('','COMMENT: end icon text');" } } SourceBlock "xbsIndex_r4/Indeterminate Probe" SourceType "Xilinx Indeterminate Probe Block" infoedit "Produces an output 1 of type double when input data is indeterminate. Output is 0 otherwise.
<" "br>Hardware notes: This block and any downstream blocks will be trimmed when hardware is generated." has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "indetprobe" sg_icon_stat "25,26,1,1,white,yellow,4,1c4257669fa6f259d9bb3743f2c8140f,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([25 24.7598 24.0485 22.8934 21.3388 19.4" "446 17.2835 14.9386 12.5 10.0614 7.71646 5.55537 3.66117 2.10663 0.951506 0.240184 0 0.240184 0.951506 2.10663 3" ".66117 5.55537 7.71646 10.0614 12.5 14.9386 17.2835 19.4446 21.3388 22.8934 24.0485 24.7598 25 25 ],[13 15.5362 " "17.9749 20.2224 22.1924 23.8091 25.0104 25.7502 26 25.7502 25.0104 23.8091 22.1924 20.2224 17.9749 15.5362 13 10" ".4638 8.02512 5.77759 3.80761 2.1909 0.989566 0.249791 0 0.249791 0.989566 2.1909 3.80761 5.77759 8.02512 10.463" "8 13 13 ],[0.95 0.93 0.65 ]);\nplot([25 24.7598 24.0485 22.8934 21.3388 19.4446 17.2835 14.9386 12.5 10.0614 7.7" "1646 5.55537 3.66117 2.10663 0.951506 0.240184 0 0.240184 0.951506 2.10663 3.66117 5.55537 7.71646 10.0614 12.5 " "14.9386 17.2835 19.4446 21.3388 22.8934 24.0485 24.7598 25 25 ],[13 15.5362 17.9749 20.2224 22.1924 23.8091 25.0" "104 25.7502 26 25.7502 25.0104 23.8091 22.1924 20.2224 17.9749 15.5362 13 10.4638 8.02512 5.77759 3.80761 2.1909" " 0.989566 0.249791 0 0.249791 0.989566 2.1909 3.80761 5.77759 8.02512 10.4638 13 13 ]);\npatch([5.325 9.66 12.66" " 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12." "66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.33 ],[0.985 0.979 0.895 ]);\npatch([5.325 9.66 12.66 8.325 5.3" "25 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 1" "0.33 7.33 10.33 10.33 7.33 ],[0.985 0.979 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMM" "ENT: begin icon text');\nfprintf('','COMMENT: end icon text');disp('!def');\n" } Block { BlockType Reference Name "Mux1" SID "17040" Ports [3, 1] Position [260, 27, 290, 103] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" block_version "10.1.3" sg_icon_stat "30,76,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 10.8571 65.1429 76 0 ]" ",[0.77 0.82 0.91 ]);\nplot([0 30 30 0 0 ],[0 10.8571 65.1429 76 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 " "10.1 6.1 ],[42.44 42.44 46.44 42.44 46.44 46.44 46.44 42.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[38" ".44 38.44 42.44 42.44 38.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[34.44 34.44 38.44 38.44" " 34.44 ],[1 1 1 ]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[30.44 30.44 34.44 30.44 34.44 34.44 30.44 ]" ",[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncol" "or('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label(" "'input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Out1" SID "17041" Position [370, 58, 400, 72] IconDisplay "Port number" } Line { SrcBlock "Gateway In" SrcPort 1 DstBlock "Mux1" DstPort 1 } Line { SrcBlock "Constant" SrcPort 1 DstBlock "Mux1" DstPort 3 } Line { SrcBlock "Indeterminate Probe" SrcPort 1 DstBlock "Gateway In" DstPort 1 } Line { SrcBlock "Mux1" SrcPort 1 DstBlock "Out1" DstPort 1 } Line { SrcBlock "In1" SrcPort 1 Points [15, 0] Branch { Points [90, 0; 0, 5] DstBlock "Mux1" DstPort 2 } Branch { Points [0, -20] DstBlock "Indeterminate Probe" DstPort 1 } } } } Block { BlockType Reference Name "Simulation Multiplexer" SID "17042" Ports [2, 1] Position [505, 212, 555, 263] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Simulation Multiplexer" SourceType "Xilinx Simulation Multiplexer Block" infoedit "Distinguish input subsystems as \"simulation only\" and \"generation only\". The input specified" " For Simulation will be used during Simulink simulation. The input specified For Generation will be used during" " code generation. This block will typically be used on the output of a HW Co-Simulation, Black Box, or ModelSim" " subsystem.

Hardware Notes: This block costs nothing." sim_sel "1" hw_sel "2" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "simmux" sg_icon_stat "50,51,2,1,white,blue,0,4170dd71,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 51 51 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 51 51 0 ]);\npatch([9.425 19.54 26.54 33.54 40.54 26.54 16.425 9.425 ],[32.7" "7 32.77 39.77 32.77 39.77 39.77 39.77 32.77 ],[1 1 1 ]);\npatch([16.425 26.54 19.54 9.425 16.425 ],[25.77 25.77 " "32.77 32.77 25.77 ],[0.931 0.946 0.973 ]);\npatch([9.425 19.54 26.54 16.425 9.425 ],[18.77 18.77 25.77 25.77 18." "77 ],[1 1 1 ]);\npatch([16.425 40.54 33.54 26.54 19.54 9.425 16.425 ],[11.77 11.77 18.77 11.77 18.77 18.77 11.77" " ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n" "\n\nfprintf('','COMMENT: end icon text');color('red');\nplot(swLineX,simSwLineY);\ncolor('black');\nplot(swLineX" ",hwSwLineY);\n" } Block { BlockType Outport Name "B" SID "17043" Position [675, 233, 705, 247] IconDisplay "Port number" } Line { SrcBlock "A" SrcPort 1 Points [15, 0] Branch { Labels [0, 0] DstBlock "Indet Check" DstPort 1 } Branch { Points [0, 25] DstBlock "Simulation Multiplexer" DstPort 2 } } Line { SrcBlock "Indet Check" SrcPort 1 DstBlock "Simulation Multiplexer" DstPort 1 } Line { SrcBlock "Simulation Multiplexer" SrcPort 1 DstBlock "B" DstPort 1 } Annotation { Name "Simulation-only block: Sets output to 0\nif input is indeterminate, which occurs at\nthe blackbox out" "puts before the first reset" Position [311, 304] } } } Block { BlockType Outport Name "Score" SID "17044" Position [1045, 423, 1075, 437] IconDisplay "Port number" } Block { BlockType Outport Name "Score Valid" SID "17045" Position [1045, 348, 1075, 362] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Line { SrcBlock "New Bit" SrcPort 1 DstBlock "Delay" DstPort 1 } Line { SrcBlock "32b Match A" SrcPort 1 Points [20, 0] Branch { DstBlock "Mask Sum" DstPort 1 } Branch { Points [0, -195] DstBlock "Gateway Out5" DstPort 1 } } Line { SrcBlock "Hist A" SrcPort 1 DstBlock "32b Match A" DstPort 1 } Line { SrcBlock "Target A" SrcPort 1 DstBlock "32b Match A" DstPort 2 } Line { SrcBlock "Mask A" SrcPort 1 DstBlock "32b Match A" DstPort 3 } Line { SrcBlock "Hist B" SrcPort 1 DstBlock "32b Match B" DstPort 1 } Line { SrcBlock "Target B" SrcPort 1 DstBlock "32b Match B" DstPort 2 } Line { SrcBlock "Mask B" SrcPort 1 DstBlock "32b Match B" DstPort 3 } Line { SrcBlock "32b Match B" SrcPort 1 Points [30, 0; 0, -90] Branch { DstBlock "Mask Sum" DstPort 2 } Branch { Points [0, -205] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "Mask Sum" SrcPort 1 Points [50, 0] Branch { DstBlock "Accumulator" DstPort 1 } Branch { Points [0, -170] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "Accumulator" SrcPort 1 DstBlock "Safe ToUint10" DstPort 1 } Line { SrcBlock "Safe ToUint10" SrcPort 1 Points [25, 0] Branch { DstBlock "Score" DstPort 1 } Branch { Points [0, -165] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "Delay" SrcPort 1 Points [210, 0; 0, 100] Branch { Points [0, 90] DstBlock "Accumulator" DstPort 2 } Branch { Points [280, 0] Branch { DstBlock "Score Valid" DstPort 1 } Branch { Points [0, -70] DstBlock "Gateway Out4" DstPort 1 } } } Line { SrcBlock "Gateway Out5" SrcPort 1 DstBlock "Masked Matching" DstPort 1 } Line { SrcBlock "Gateway Out1" SrcPort 1 DstBlock "Masked Matching" DstPort 2 } Line { SrcBlock "Gateway Out2" SrcPort 1 DstBlock "Masked Matching" DstPort 3 } Line { SrcBlock "Gateway Out3" SrcPort 1 DstBlock "Masked Matching" DstPort 4 } Line { SrcBlock "Gateway Out4" SrcPort 1 DstBlock "Masked Matching" DstPort 5 } } } Block { BlockType SubSystem Name "Phase Sel" SID "17046" Ports [6, 2] Position [1130, 439, 1275, 606] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Phase Sel" Location [2, 70, 1830, 1180] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "80" Block { BlockType Inport Name "Match" SID "17047" Position [50, 778, 80, 792] IconDisplay "Port number" } Block { BlockType Inport Name "Matching Done" SID "17048" Position [140, 433, 170, 447] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "New Sym" SID "17049" Position [160, 718, 190, 732] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "Despread Phase " SID "17050" Position [1320, 493, 1350, 507] ZOrder -1 Port "4" IconDisplay "Port number" } Block { BlockType Inport Name "IQ Mag" SID "17051" Position [1055, 573, 1085, 587] ZOrder -1 NamePlacement "alternate" Port "5" IconDisplay "Port number" } Block { BlockType Inport Name "Reset" SID "17052" Position [160, 748, 190, 762] Port "6" IconDisplay "Port number" } Block { BlockType Reference Name "Constant" SID "17053" Ports [0, 1] Position [1040, 448, 1070, 472] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "2*DSSS_SAMPS_PER_SYM-1" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "ceil(log2(2*DSSS_SAMPS_PER_SYM))" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,24,0,1,white,blue,0,2cb85581,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 24 24 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 24 24 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[15.3" "3 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[12.33 12.33 " "15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[9.33 9.33 12.33 12.33 9.33 " "],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('blac" "k');port_label('output',1,'39');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay" SID "17893" Ports [1, 1] Position [110, 771, 145, 799] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "4" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,28,1,1,white,blue,0,d390c2d8,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 28 28 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[18.44 18.4" "4 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[14.44 14.44 18.44 18.44 " "14.44 ],[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\np" "atch([12.1 25.88 21.88 17.88 13.88 8.1 12.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-" "4}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out1" SID "17054" Ports [1, 1] Position [1625, 49, 1660, 61] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "New Sym" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out10" SID "17846" Ports [1, 1] Position [1625, 229, 1660, 241] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Matched Phase" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "17055" Ports [1, 1] Position [1625, 109, 1660, 121] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "IQ Mag" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "17056" Ports [1, 1] Position [1625, 129, 1660, 141] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "IQ Mag Max Update" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "17057" Ports [1, 1] Position [1625, 69, 1660, 81] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Match" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "17058" Ports [1, 1] Position [1625, 89, 1660, 101] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Matching Done" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "17059" Ports [1, 1] Position [1625, 169, 1660, 181] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Despread Phase" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "17060" Ports [1, 1] Position [1625, 189, 1660, 201] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Final Phase Capt" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "17061" Ports [1, 1] Position [1625, 209, 1660, 221] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Final Phase" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out9" SID "17062" Ports [1, 1] Position [1625, 149, 1660, 161] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Max Mag" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Inverter" SID "17892" Ports [1, 1] Position [1025, 591, 1050, 609] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "17064" Ports [2, 1] Position [865, 417, 910, 468] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "45,51,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 51 51 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 51 51 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[31.66 3" "1.66 37.66 31.66 37.66 37.66 37.66 31.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[25.66 25.66 31.66 " "31.66 25.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[19.66 19.66 25.66 25.66 19.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[13.66 13.66 19.66 13.66 19.66 19.66 13.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('" "black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical3" SID "17065" Ports [2, 1] Position [1225, 407, 1270, 458] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "45,51,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 51 51 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 51 51 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[31.66 3" "1.66 37.66 31.66 37.66 37.66 37.66 31.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[25.66 25.66 31.66 " "31.66 25.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[19.66 19.66 25.66 25.66 19.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[13.66 13.66 19.66 13.66 19.66 19.66 13.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('" "black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical6" SID "17067" Ports [4, 1] Position [880, 639, 920, 711] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "4" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,72,4,1,white,blue,0,50b60d37,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 72 72 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 72 72 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[41.55 41." "55 46.55 41.55 46.55 46.55 46.55 41.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[36.55 36.55 41.55 4" "1.55 36.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[31.55 31.55 36.55 36.55 31.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[26.55 26.55 31.55 26.55 31.55 31.55 26.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\n\ncolo" "r('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical8" SID "17069" Ports [2, 1] Position [645, 463, 680, 492] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,29,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 29 29 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 29 29 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[18.44 18.4" "4 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[14.44 14.44 18.44 18.44 " "14.44 ],[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\np" "atch([12.1 25.88 21.88 17.88 13.88 8.1 12.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('or" "');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Marching One" SID "17070" Ports [1, 1] Position [300, 706, 400, 744] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Marching One" Location [2, 70, 1830, 1180] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "New Sym" SID "17071" Position [395, 403, 425, 417] IconDisplay "Port number" } Block { BlockType Reference Name "20LSB" SID "17072" Ports [1, 1] Position [510, 310, 555, 330] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "DSSS_SAMPS_PER_SYM" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "45,20,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 20 20 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 20 20 0 ]);\npatch([17.55 20.44 22.44 24.44 26.44 22.44 19.55 17.55 ],[12.22" " 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([19.55 22.44 20.44 17.55 19.55 ],[10.22 10.22 12." "22 12.22 10.22 ],[0.931 0.946 0.973 ]);\npatch([17.55 20.44 22.44 19.55 17.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1" " 1 1 ]);\npatch([19.55 26.44 24.44 22.44 20.44 17.55 19.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');" "port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant1" SID "17073" Ports [0, 1] Position [350, 351, 400, 379] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "2^(DSSS_SAMPS_PER_SYM)" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "DSSS_SAMPS_PER_SYM+1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "50,28,0,1,white,blue,0,7dc5ad05,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 28 28 0 ]);\npatch([16.1 21.88 25.88 29.88 33.88 25.88 20.1 16.1 ],[18.44 18" ".44 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([20.1 25.88 21.88 16.1 20.1 ],[14.44 14.44 18.44 18." "44 14.44 ],[0.931 0.946 0.973 ]);\npatch([16.1 21.88 25.88 20.1 16.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]" ");\npatch([20.1 33.88 29.88 25.88 21.88 16.1 20.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 " "]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_lab" "el('output',1,'1048576');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert" SID "17074" Ports [1, 1] Position [600, 226, 635, 244] BlockMirror on NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "DSSS_SAMPS_PER_SYM+1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "35,18,1,1,white,blue,0,edca21da,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 18 18 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical5" SID "17075" Ports [2, 1] Position [515, 346, 550, 384] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,38,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 38 38 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 38 38 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[24.55 24." "55 29.55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[19.55 19.55 24.55 2" "4.55 19.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black" "');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "17076" Ports [3, 1] Position [585, 300, 645, 430] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "1" rst on en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "60,130,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 130 130 0 ],[0.77 0." "82 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 130 130 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[73.8" "8 73.88 81.88 73.88 81.88 81.88 81.88 73.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[65.88 65.88 73.88" " 73.88 65.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[57.88 57.88 65.88 65.88 57.88 ],[1 1" " 1 ]);\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[49.88 49.88 57.88 49.88 57.88 57.88 49.88 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'en" "');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Relational3" SID "17077" Ports [2, 1] Position [445, 335, 485, 375] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "40,40,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bfa = b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Shift" SID "17078" Ports [1, 1] Position [495, 222, 535, 248] BlockMirror on NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Shift" SourceType "Xilinx Binary Shift Operator Block" infoedit "Hardware notes: In hardware this block costs nothing if full output precision is used." shift_dir "Left" shift_bits "1" en off latency "0" precision "User Defined" arith_type "Unsigned" n_bits "DSSS_SAMPS_PER_SYM+1" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "shift" sg_icon_stat "40,26,1,1,white,blue,0,6c6aa2df,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 26 26 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 26 26 0 ]);\npatch([13.325 17.66 20.66 23.66 26.66 20.66 16.325 13.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([16.325 20.66 17.66 13.325 16.325 ],[13.33 13." "33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([13.325 17.66 20.66 16.325 13.325 ],[10.33 10.33 13.33 13.3" "3 10.33 ],[1 1 1 ]);\npatch([16.325 26.66 23.66 20.66 17.66 13.325 16.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7." "33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n" "\n\ncolor('black');disp('\\bf{X << 1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "One Hot" SID "17079" Position [745, 228, 775, 242] IconDisplay "Port number" } Line { SrcBlock "Shift" SrcPort 1 Points [-60, 0; 0, 85] Branch { DstBlock "Relational3" DstPort 1 } Branch { DstBlock "20LSB" DstPort 1 } } Line { SrcBlock "Relational3" SrcPort 1 DstBlock "Logical5" DstPort 1 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Relational3" DstPort 2 } Line { SrcBlock "Register2" SrcPort 1 Points [30, 0; 0, -130] Branch { DstBlock "Convert" DstPort 1 } Branch { DstBlock "One Hot" DstPort 1 } } Line { SrcBlock "Logical5" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "20LSB" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "Convert" SrcPort 1 DstBlock "Shift" DstPort 1 } Line { SrcBlock "New Sym" SrcPort 1 Points [70, 0] Branch { DstBlock "Register2" DstPort 3 } Branch { DstBlock "Logical5" DstPort 2 } } } } Block { BlockType SubSystem Name "Match Masking" SID "17080" Ports [3, 1] Position [460, 711, 570, 799] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Match Masking" Location [2, 70, 1830, 1180] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "One Hot Phase" SID "17081" Position [180, 253, 210, 267] IconDisplay "Port number" } Block { BlockType Inport Name "Reset" SID "17082" Position [180, 288, 210, 302] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "Match" SID "17083" Position [180, 323, 210, 337] Port "3" IconDisplay "Port number" } Block { BlockType Reference Name "Constant" SID "17084" Ports [0, 1] Position [665, 368, 695, 392] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,24,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 24 24 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 24 24 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[15.3" "3 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[12.33 12.33 " "15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[9.33 9.33 12.33 12.33 9.33 " "],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('blac" "k');port_label('output',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "17085" Ports [2, 1] Position [580, 317, 625, 368] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "45,51,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 51 51 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 51 51 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[31.66 3" "1.66 37.66 31.66 37.66 37.66 37.66 31.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[25.66 25.66 31.66 " "31.66 25.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[19.66 19.66 25.66 25.66 19.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[13.66 13.66 19.66 13.66 19.66 19.66 13.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('" "black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical5" SID "17086" Ports [2, 1] Position [300, 220, 350, 275] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "50,55,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 55 55 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 55 55 0 ]);\npatch([9.425 19.54 26.54 33.54 40.54 26.54 16.425 9.425 ],[34.7" "7 34.77 41.77 34.77 41.77 41.77 41.77 34.77 ],[1 1 1 ]);\npatch([16.425 26.54 19.54 9.425 16.425 ],[27.77 27.77 " "34.77 34.77 27.77 ],[0.931 0.946 0.973 ]);\npatch([9.425 19.54 26.54 16.425 9.425 ],[20.77 20.77 27.77 27.77 20." "77 ],[1 1 1 ]);\npatch([16.425 40.54 33.54 26.54 19.54 9.425 16.425 ],[13.77 13.77 20.77 13.77 20.77 20.77 13.77" " ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n" "\n\ncolor('black');disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "17087" Ports [3, 1] Position [425, 237, 485, 293] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "60,56,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36" ".88 44.88 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36." "88 28.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]" ");\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0." "973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port" "_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'en');\n" "color('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: " "end icon text');" } Block { BlockType Reference Name "Relational1" SID "17088" Ports [2, 1] Position [740, 329, 790, 396] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a!=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "50,67,2,1,white,blue,0,850de6e7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 67 67 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 67 67 0 ]);\npatch([9.425 19.54 26.54 33.54 40.54 26.54 16.425 9.425 ],[40.7" "7 40.77 47.77 40.77 47.77 47.77 47.77 40.77 ],[1 1 1 ]);\npatch([16.425 26.54 19.54 9.425 16.425 ],[33.77 33.77 " "40.77 40.77 33.77 ],[0.931 0.946 0.973 ]);\npatch([9.425 19.54 26.54 16.425 9.425 ],[26.77 26.77 33.77 33.77 26." "77 ],[1 1 1 ]);\npatch([16.425 40.54 33.54 26.54 19.54 9.425 16.425 ],[19.77 19.77 26.77 19.77 26.77 26.77 19.77" " ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nc" "olor('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('" "output',1,'\\bfa \\neq b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Matched Phase" SID "17089" Position [880, 358, 910, 372] ZOrder -23 IconDisplay "Port number" } Line { SrcBlock "Logical5" SrcPort 1 Points [0, -5] DstBlock "Register2" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 Points [10, 0] Branch { Points [0, -70; -225, 0; 0, 40] DstBlock "Logical5" DstPort 1 } Branch { Points [0, 65] DstBlock "Logical1" DstPort 1 } } Line { SrcBlock "Reset" SrcPort 1 Points [140, 0; 0, -30] DstBlock "Register2" DstPort 2 } Line { SrcBlock "One Hot Phase" SrcPort 1 Points [50, 0] Branch { DstBlock "Logical5" DstPort 2 } Branch { Points [0, 95] DstBlock "Logical1" DstPort 2 } } Line { SrcBlock "Match" SrcPort 1 Points [180, 0; 0, -45] DstBlock "Register2" DstPort 3 } Line { SrcBlock "Constant" SrcPort 1 DstBlock "Relational1" DstPort 2 } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Relational1" DstPort 1 } Line { SrcBlock "Relational1" SrcPort 1 DstBlock "Matched Phase" DstPort 1 } } } Block { BlockType Scope Name "Phase Sel" SID "17090" Ports [10] Position [1760, 43, 1820, 247] ZOrder -16 Floating off Location [1, 45, 1836, 1199] Open off NumInputPorts "10" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" axes9 "%" axes10 "%" } List { ListType ScopeGraphics FigureColor "[0.5 0.5 0.5]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "40000" YMin "0~0~0~0~0~0~0~-1~-1~-1" YMax "1~1~1~1~1~1~20~1~1~1" SaveName "ScopeData5" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType SubSystem Name "Posedge1" SID "17091" Ports [1, 1] Position [605, 431, 650, 449] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Posedge1" Location [88, 301, 2330, 1301] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "17092" Position [200, 253, 230, 267] IconDisplay "Port number" } Block { BlockType Reference Name "Delay" SID "17093" Ports [1, 1] Position [425, 153, 460, 177] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. " "If register retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[15" ".33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.33 12." "33 15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 12.33 " "9.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\nc" "olor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "17094" Ports [1, 1] Position [490, 156, 515, 174] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "17095" Ports [2, 1] Position [540, 151, 585, 204] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,53,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 53 53 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 53 53 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[32.66 3" "2.66 38.66 32.66 38.66 38.66 38.66 32.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[26.66 26.66 32.66 " "32.66 26.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[20.66 20.66 26.66 26.66 20.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[14.66 14.66 20.66 14.66 20.66 20.66 14.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('" "black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "17096" Position [610, 173, 640, 187] IconDisplay "Port number" } Line { SrcBlock "Delay" SrcPort 1 DstBlock "Inverter" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "D" SrcPort 1 Points [150, 0; 0, -70] Branch { Points [0, -25] DstBlock "Delay" DstPort 1 } Branch { DstBlock "Logical1" DstPort 2 } } Annotation { Name "Rising Edge Detection" Position [500, 112] } } } Block { BlockType Reference Name "Register" SID "17097" Ports [3, 1] Position [1170, 572, 1230, 628] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "60,56,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36" ".88 44.88 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36." "88 28.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]" ");\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0." "973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port" "_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'en');\n" "color('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: " "end icon text');" } Block { BlockType Reference Name "Register1" SID "17098" Ports [3, 1] Position [1495, 292, 1555, 348] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "60,56,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36" ".88 44.88 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36." "88 28.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]" ");\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0." "973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port" "_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'en');\n" "color('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: " "end icon text');" } Block { BlockType Reference Name "Register2" SID "17099" Ports [2, 1] Position [1390, 487, 1450, 543] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "60,56,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36" ".88 44.88 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36." "88 28.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]" ");\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0." "973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port" "_label('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\n" "color('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational1" SID "17100" Ports [2, 1] Position [1115, 409, 1165, 476] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a>=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "50,67,2,1,white,blue,0,6218dc92,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 67 67 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 67 67 0 ]);\npatch([9.425 19.54 26.54 33.54 40.54 26.54 16.425 9.425 ],[40.7" "7 40.77 47.77 40.77 47.77 47.77 47.77 40.77 ],[1 1 1 ]);\npatch([16.425 26.54 19.54 9.425 16.425 ],[33.77 33.77 " "40.77 40.77 33.77 ],[0.931 0.946 0.973 ]);\npatch([9.425 19.54 26.54 16.425 9.425 ],[26.77 26.77 33.77 33.77 26." "77 ],[1 1 1 ]);\npatch([16.425 40.54 33.54 26.54 19.54 9.425 16.425 ],[19.77 19.77 26.77 19.77 26.77 26.77 19.77" " ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nc" "olor('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('" "output',1,'\\bfa \\geq b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational4" SID "17101" Ports [2, 1] Position [1045, 693, 1095, 737] BlockMirror on NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a>b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "50,44,2,1,white,blue,0,b5131c97,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 44 44 0 ]);\npatch([11.65 20.32 26.32 32.32 38.32 26.32 17.65 11.65 ],[28.66" " 28.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([17.65 26.32 20.32 11.65 17.65 ],[22.66 22.66 28." "66 28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([11.65 20.32 26.32 17.65 11.65 ],[16.66 16.66 22.66 22.66 16.66 ]" ",[1 1 1 ]);\npatch([17.65 38.32 32.32 26.32 20.32 11.65 17.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output" "',1,'\\bfa > b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "S-R Latch" SID "17102" Ports [2, 1] Position [720, 428, 765, 477] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "S-R Latch" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "17103" Position [140, 103, 170, 117] IconDisplay "Port number" } Block { BlockType Inport Name "R" SID "17104" Position [140, 88, 170, 102] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "17105" Ports [0, 1] Position [195, 71, 210, 89] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "15,18,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11.22 " "13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 9.22 " "],[0.931 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([4.55 " "11.44 9.44 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "17106" Ports [1, 1] Position [210, 86, 235, 104] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('outpu" "t',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "17107" Ports [1, 1] Position [210, 101, 235, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('outpu" "t',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "17108" Ports [3, 1] Position [255, 71, 300, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "17109" Position [325, 88, 355, 102] IconDisplay "Port number" } Line { SrcBlock "S" SrcPort 1 DstBlock "Convert2" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "Convert2" SrcPort 1 DstBlock "Register2" DstPort 3 } } } Block { BlockType SubSystem Name "S-R Latch1" SID "17110" Ports [2, 1] Position [1505, 363, 1550, 412] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "S-R Latch1" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "17111" Position [140, 103, 170, 117] IconDisplay "Port number" } Block { BlockType Inport Name "R" SID "17112" Position [140, 88, 170, 102] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "17113" Ports [0, 1] Position [195, 71, 210, 89] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "15,18,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11.22 " "13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 9.22 " "],[0.931 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([4.55 " "11.44 9.44 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "17114" Ports [1, 1] Position [210, 86, 235, 104] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('outpu" "t',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "17115" Ports [1, 1] Position [210, 101, 235, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('outpu" "t',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "17116" Ports [3, 1] Position [255, 71, 300, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "17117" Position [325, 88, 355, 102] IconDisplay "Port number" } Line { SrcBlock "Convert2" SrcPort 1 DstBlock "Register2" DstPort 3 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "S" SrcPort 1 DstBlock "Convert2" DstPort 1 } } } Block { BlockType Reference Name "Search Len Counter" SID "17118" Ports [2, 1] Position [975, 387, 1030, 463] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited count" "er is implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "inf" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "8" bin_pt "0" load_pin off rst on en on explicit_period "off" period "1" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "counter" sg_icon_stat "55,76,2,1,white,blue,0,ae3608d6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 76 76 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 76 76 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ],[45" ".77 45.77 52.77 45.77 52.77 52.77 52.77 45.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[38.77 38." "77 45.77 45.77 38.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[31.77 31.77 38.77 38.7" "7 31.77 ],[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[24.77 24.77 31.77 24.77 31.77 31.77" " 24.77 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text" "');\ncolor('black');port_label('input',1,'rst');\ncolor('black');port_label('input',2,'en');\n\ncolor('black');d" "isp('{\\fontsize{14}\\bf++}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Sel Phase" SID "17119" Position [1630, 313, 1660, 327] ZOrder -23 IconDisplay "Port number" } Block { BlockType Outport Name "Sel Phase Valid" SID "17120" Position [1615, 383, 1645, 397] ZOrder -23 Port "2" IconDisplay "Port number" } Line { SrcBlock "Marching One" SrcPort 1 DstBlock "Match Masking" DstPort 1 } Line { SrcBlock "Reset" SrcPort 1 Points [45, 0] Branch { Labels [0, 0] DstBlock "Match Masking" DstPort 2 } Branch { Points [0, -285] Branch { DstBlock "Logical8" DstPort 1 } Branch { Points [0, -150; 1160, 0] Branch { DstBlock "Register1" DstPort 2 } Branch { Points [0, 80] DstBlock "S-R Latch1" DstPort 2 } } } } Line { SrcBlock "New Sym" SrcPort 1 Points [40, 0] Branch { DstBlock "Marching One" DstPort 1 } Branch { Points [0, -115] Branch { Points [0, -255] Branch { Points [565, 0] Branch { Points [0, 75] DstBlock "Logical2" DstPort 1 } Branch { Points [410, 0] DstBlock "Logical3" DstPort 1 } } Branch { Points [0, -300] DstBlock "Gateway Out1" DstPort 1 } } Branch { Points [545, 0; 0, 55] DstBlock "Logical6" DstPort 2 } } } Line { SrcBlock "Match" SrcPort 1 DstBlock "Delay" DstPort 1 } Line { Name "New Sym" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 DstBlock "Phase Sel" DstPort 1 } Line { Name "Matching Done" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 DstBlock "Phase Sel" DstPort 3 } Line { Name "Match" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 DstBlock "Phase Sel" DstPort 2 } Line { Name "IQ Mag" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 DstBlock "Phase Sel" DstPort 4 } Line { Name "IQ Mag Max Update" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 DstBlock "Phase Sel" DstPort 5 } Line { SrcBlock "Matching Done" SrcPort 1 Points [35, 0] Branch { DstBlock "Posedge1" DstPort 1 } Branch { Points [0, -345] DstBlock "Gateway Out5" DstPort 1 } } Line { SrcBlock "Posedge1" SrcPort 1 DstBlock "S-R Latch" DstPort 1 } Line { SrcBlock "Logical2" SrcPort 1 DstBlock "Search Len Counter" DstPort 2 } Line { SrcBlock "S-R Latch" SrcPort 1 Points [15, 0] Branch { DstBlock "Logical2" DstPort 2 } Branch { Points [0, 145] Branch { Points [0, 45] DstBlock "Logical6" DstPort 1 } Branch { Points [0, 0] DstBlock "Inverter" DstPort 1 } } } Line { SrcBlock "Search Len Counter" SrcPort 1 DstBlock "Relational1" DstPort 1 } Line { SrcBlock "Constant" SrcPort 1 DstBlock "Relational1" DstPort 2 } Line { SrcBlock "Relational1" SrcPort 1 DstBlock "Logical3" DstPort 2 } Line { SrcBlock "Logical3" SrcPort 1 Points [10, 0] Branch { Points [0, 80; -655, 0] DstBlock "Logical8" DstPort 2 } Branch { Points [0, -95; 125, 0] Branch { DstBlock "Register1" DstPort 3 } Branch { Points [0, -145] DstBlock "Gateway Out7" DstPort 1 } Branch { Points [0, 35] DstBlock "S-R Latch1" DstPort 1 } } } Line { SrcBlock "Register1" SrcPort 1 Points [20, 0] Branch { Points [0, -105] DstBlock "Gateway Out8" DstPort 1 } Branch { DstBlock "Sel Phase" DstPort 1 } } Line { SrcBlock "Logical6" SrcPort 1 Points [30, 0; 0, -55; 180, 0] Branch { Points [0, -90] Branch { Points [0, -395] DstBlock "Gateway Out3" DstPort 1 } Branch { DstBlock "Register2" DstPort 2 } } Branch { DstBlock "Register" DstPort 3 } } Line { SrcBlock "IQ Mag" SrcPort 1 Points [40, 0] Branch { DstBlock "Register" DstPort 1 } Branch { Points [0, 125] DstBlock "Relational4" DstPort 1 } Branch { Points [0, -465] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "Relational4" SrcPort 1 Points [-175, 0] DstBlock "Logical6" DstPort 4 } Line { SrcBlock "Register" SrcPort 1 Points [20, 0] Branch { Points [0, 125] DstBlock "Relational4" DstPort 2 } Branch { Points [0, -445] DstBlock "Gateway Out9" DstPort 1 } } Line { SrcBlock "Logical8" SrcPort 1 Points [10, 0] Branch { Points [0, -15] DstBlock "S-R Latch" DstPort 2 } Branch { Points [0, 20; 265, 0] DstBlock "Search Len Counter" DstPort 1 } } Line { SrcBlock "Match Masking" SrcPort 1 Points [165, 0; 0, -70] Branch { DstBlock "Logical6" DstPort 3 } Branch { Points [0, -450] DstBlock "Gateway Out10" DstPort 1 } } Line { SrcBlock "Despread Phase " SrcPort 1 Points [10, 0] Branch { Points [0, -325] DstBlock "Gateway Out6" DstPort 1 } Branch { DstBlock "Register2" DstPort 1 } } Line { SrcBlock "Register2" SrcPort 1 Points [15, 0; 0, -215] DstBlock "Register1" DstPort 1 } Line { Name "Despread Phase" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 DstBlock "Phase Sel" DstPort 7 } Line { Name "Final Phase Capt" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 DstBlock "Phase Sel" DstPort 8 } Line { Name "Final Phase" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 DstBlock "Phase Sel" DstPort 9 } Line { Name "Max Mag" Labels [0, 0] SrcBlock "Gateway Out9" SrcPort 1 DstBlock "Phase Sel" DstPort 6 } Line { SrcBlock "S-R Latch1" SrcPort 1 DstBlock "Sel Phase Valid" DstPort 1 } Line { Name "Matched Phase" Labels [0, 0] SrcBlock "Gateway Out10" SrcPort 1 DstBlock "Phase Sel" DstPort 10 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Register" DstPort 2 } Line { SrcBlock "Delay" SrcPort 1 Points [70, 0] Branch { DstBlock "Match Masking" DstPort 3 } Branch { Points [0, -710] DstBlock "Gateway Out4" DstPort 1 } } Annotation { Name "Delay the Match pulse to align it with\nthe New Sym pulse. This delays the match pulse\nby 1 symbol p" "eriod, but this is fine since it's\nonly used to mark \"matched phases\" and the\nphases repeat every 20 cycles." Position [140, 848] } } } Block { BlockType SubSystem Name "Target RAM" SID "17121" Ports [2, 2] Position [440, 276, 540, 309] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Target RAM" Location [2, 70, 1830, 1180] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Rd Addr A" SID "17122" Position [155, 318, 185, 332] IconDisplay "Port number" } Block { BlockType Inport Name "Rd Addr B" SID "17123" Position [155, 393, 185, 407] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Constant4" SID "17124" Ports [0, 1] Position [740, 439, 755, 461] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Boolean" arith_type "Boolean" n_bits "16" bin_pt "14" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "8" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "15,22,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 15 15 0 0 ],[0 0 22 22 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[13.22 13.22 " "15.22 13.22 15.22 15.22 15.22 13.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[11.22 11.22 13.22 13.22 11." "22 ],[0.931 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[9.22 9.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([" "4.55 11.44 9.44 7.44 5.44 2.55 4.55 ],[7.22 7.22 9.22 7.22 9.22 9.22 7.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'0'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant6" SID "17125" Ports [0, 1] Position [740, 414, 755, 436] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "8" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "15,22,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 15 15 0 0 ],[0 0 22 22 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[13.22 13.22 " "15.22 13.22 15.22 15.22 15.22 13.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[11.22 11.22 13.22 13.22 11." "22 ],[0.931 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[9.22 9.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([" "4.55 11.44 9.44 7.44 5.44 2.55 4.55 ],[7.22 7.22 9.22 7.22 9.22 9.22 7.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'0'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert" SID "17126" Ports [1, 1] Position [335, 345, 375, 365] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "ceil(log2(DSSS_NUM_SYMS_PER_OFFSET))" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "40,20,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 20 20 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 20 20 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[12.22" " 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[10.22 10.22 12." "22 12.22 10.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1" " 1 1 ]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');" "port_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From1" SID "17127" Position [175, 286, 405, 304] ZOrder -9 ShowName off GotoTag "reg_Target_RAM_WrEn" TagVisibility "global" } Block { BlockType From Name "From3" SID "17128" Position [495, 341, 725, 359] ZOrder -9 ShowName off GotoTag "reg_Target_RAM_Wr_Data" TagVisibility "global" } Block { BlockType From Name "From6" SID "17129" Position [55, 346, 285, 364] ZOrder -9 ShowName off GotoTag "reg_RAMs_Wr_Addr" TagVisibility "global" } Block { BlockType Reference Name "Mux" SID "17130" Ports [3, 1] Position [445, 278, 480, 372] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "35,94,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 13.4286 80.5714 94 0 ]" ",[0.77 0.82 0.91 ]);\nplot([0 35 35 0 0 ],[0 13.4286 80.5714 94 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10." "875 5.875 ],[52.55 52.55 57.55 52.55 57.55 57.55 57.55 52.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 " "],[47.55 47.55 52.55 52.55 47.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[42.55 42.55 47" ".55 47.55 42.55 ],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[37.55 37.55 42.55 37.55 42.55 42" ".55 37.55 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon t" "ext');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');" "port_label('input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text" "');" } Block { BlockType Reference Name "Target Bits RAM" SID "17131" Ports [6, 2] Position [805, 306, 920, 469] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Dual Port RAM" SourceType "Xilinx Dual Port Random Access Memory Block" depth "DSSS_NUM_SYMS_PER_OFFSET" initVector "target_bits_ram_init" distributed_mem "Block RAM" init_a "0" init_b "0" rst_a off rst_b off en_a off en_b off latency "1" write_mode_A "Read After Write" write_mode_B "Read After Write" dbl_ovrd off optimize "Area" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "dpram" sg_icon_stat "115,163,6,2,white,blue,0,28af736d,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 115 115 0 0 ],[0 0 163 163 0 ],[0.77 " "0.82 0.91 ]);\nplot([0 115 115 0 0 ],[0 0 163 163 0 ]);\npatch([21.4 44.52 60.52 76.52 92.52 60.52 37.4 21.4 ],[" "98.76 98.76 114.76 98.76 114.76 114.76 114.76 98.76 ],[1 1 1 ]);\npatch([37.4 60.52 44.52 21.4 37.4 ],[82.76 82." "76 98.76 98.76 82.76 ],[0.931 0.946 0.973 ]);\npatch([21.4 44.52 60.52 37.4 21.4 ],[66.76 66.76 82.76 82.76 66.7" "6 ],[1 1 1 ]);\npatch([37.4 92.52 76.52 60.52 44.52 21.4 37.4 ],[50.76 50.76 66.76 50.76 66.76 66.76 50.76 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'addra');\ncolor('black');port_label('input',2,'dina');\ncolor('black');port_label(" "'input',3,'wea');\ncolor('black');port_label('input',4,'addrb');\ncolor('black');port_label('input',5,'dinb');\n" "color('black');port_label('input',6,'web');\ncolor('black');port_label('output',1,'A');\ncolor('black');port_lab" "el('output',2,'B');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Data A" SID "17132" Position [1000, 343, 1030, 357] IconDisplay "Port number" } Block { BlockType Outport Name "Data B" SID "17133" Position [1000, 423, 1030, 437] Port "2" IconDisplay "Port number" } Line { SrcBlock "Constant6" SrcPort 1 DstBlock "Target Bits RAM" DstPort 5 } Line { SrcBlock "Constant4" SrcPort 1 DstBlock "Target Bits RAM" DstPort 6 } Line { SrcBlock "Mux" SrcPort 1 DstBlock "Target Bits RAM" DstPort 1 } Line { SrcBlock "Rd Addr B" SrcPort 1 DstBlock "Target Bits RAM" DstPort 4 } Line { SrcBlock "Target Bits RAM" SrcPort 1 DstBlock "Data A" DstPort 1 } Line { SrcBlock "Target Bits RAM" SrcPort 2 DstBlock "Data B" DstPort 1 } Line { SrcBlock "From1" SrcPort 1 Points [10, 0] Branch { DstBlock "Mux" DstPort 1 } Branch { Points [0, 80] DstBlock "Target Bits RAM" DstPort 3 } } Line { SrcBlock "From6" SrcPort 1 DstBlock "Convert" DstPort 1 } Line { SrcBlock "Rd Addr A" SrcPort 1 DstBlock "Mux" DstPort 2 } Line { SrcBlock "From3" SrcPort 1 DstBlock "Target Bits RAM" DstPort 2 } Line { SrcBlock "Convert" SrcPort 1 DstBlock "Mux" DstPort 3 } } } Block { BlockType Outport Name "Sel Phase" SID "17134" Position [1480, 473, 1510, 487] ZOrder -23 IconDisplay "Port number" } Block { BlockType Outport Name "Sel Phase Valid" SID "17135" Position [1370, 558, 1400, 572] ZOrder -23 Port "2" IconDisplay "Port number" } Line { SrcBlock "Match Addr A" SrcPort 1 Points [25, 0] Branch { Labels [0, 0] DstBlock "Target RAM" DstPort 1 } Branch { Points [0, 230] DstBlock "Mask 1 RAM" DstPort 1 } } Line { SrcBlock "Hist RAM A" SrcPort 1 Points [245, 0; 0, 290] DstBlock "Matching - Mask 1" DstPort 2 } Line { SrcBlock "Hist RAM B" SrcPort 1 Points [240, 0; 0, 265] DstBlock "Matching - Mask 1" DstPort 3 } Line { SrcBlock "Target RAM" SrcPort 1 Points [55, 0; 0, 200] DstBlock "Matching - Mask 1" DstPort 4 } Line { SrcBlock "Target RAM" SrcPort 2 Points [50, 0; 0, 200] DstBlock "Matching - Mask 1" DstPort 5 } Line { SrcBlock "New Bit" SrcPort 1 Points [10, 0] Branch { Labels [0, 0] Points [0, 475; 670, 0; 0, -60] DstBlock "Phase Sel" DstPort 3 } Branch { Points [250, 0] Branch { Points [0, 345] DstBlock "Matching - Mask 1" DstPort 1 } Branch { Points [90, 0; 0, -50] DstBlock "Gateway Out6" DstPort 1 } } } Line { SrcBlock "Mask 1 RAM" SrcPort 1 DstBlock "Matching - Mask 1" DstPort 6 } Line { SrcBlock "Mask 1 RAM" SrcPort 2 DstBlock "Matching - Mask 1" DstPort 7 } Line { SrcBlock "Matching - Mask 1" SrcPort 1 Points [50, 0] Branch { DstBlock "Match Search" DstPort 1 } Branch { Points [0, -390] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "Matching - Mask 1" SrcPort 2 Points [45, 0; 0, -45; 10, 0] Branch { DstBlock "Match Search" DstPort 2 } Branch { Points [0, -385] DstBlock "Gateway Out8" DstPort 1 } } Line { SrcBlock "Match Addr B" SrcPort 1 Points [20, 0] Branch { DstBlock "Target RAM" DstPort 2 } Branch { Points [0, 230] DstBlock "Mask 1 RAM" DstPort 2 } } Line { SrcBlock "Match Search" SrcPort 1 Points [30, 0] Branch { DstBlock "Phase Sel" DstPort 1 } Branch { Points [0, -355] DstBlock "Gateway Out18" DstPort 1 } } Line { SrcBlock "IQ Mag" SrcPort 1 Points [735, 0; 0, -90] Branch { DstBlock "Phase Sel" DstPort 5 } Branch { Points [0, -415] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "Reset" SrcPort 1 Points [485, 0] Branch { Points [0, -225] DstBlock "Match Search" DstPort 3 } Branch { Points [255, 0] DstBlock "Phase Sel" DstPort 6 } } Line { SrcBlock "Match Search" SrcPort 2 Points [35, 0] Branch { DstBlock "Phase Sel" DstPort 2 } Branch { Points [0, -360] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "Phase Sel" SrcPort 1 Points [15, 0] Branch { Points [0, -295] DstBlock "Gateway Out4" DstPort 1 } Branch { DstBlock "Sel Phase" DstPort 1 } } Line { SrcBlock "Phase Sel" SrcPort 2 Points [25, 0] Branch { DstBlock "Sel Phase Valid" DstPort 1 } Branch { Points [0, -360] DstBlock "Gateway Out5" DstPort 1 } } Line { Name "Despread Phase" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 DstBlock "Matching" DstPort 7 } Line { Name "Sel Phase" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 DstBlock "Matching" DstPort 8 } Line { Name "Sel Phase Valid" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 DstBlock "Matching" DstPort 9 } Line { Name "IQ Mag" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 DstBlock "Matching" DstPort 6 } Line { Name "Search Done" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 DstBlock "Matching" DstPort 5 } Line { Name "Match" Labels [0, 0] SrcBlock "Gateway Out18" SrcPort 1 DstBlock "Matching" DstPort 4 } Line { Name "New Bit" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 DstBlock "Matching" DstPort 1 } Line { Name "Score" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 DstBlock "Matching" DstPort 2 } Line { Name "Score Valid" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 DstBlock "Matching" DstPort 3 } Line { SrcBlock "Despread Phase " SrcPort 1 Points [540, 0; 0, 10; 160, 0; 0, -85] Branch { DstBlock "Phase Sel" DstPort 4 } Branch { Points [0, -370] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "Constant" SrcPort 1 Points [20, 0; 0, 125; 5, 0; 0, -30] } } } Block { BlockType Scope Name "Phase Sel Decision" SID "17136" Ports [10] Position [1540, 93, 1600, 297] ZOrder -16 Floating off Location [1, 45, 1836, 1199] Open off NumInputPorts "10" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" axes9 "%" axes10 "%" } List { ListType ScopeGraphics FigureColor "[0.5 0.5 0.5]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "45388 " YMin "0~0~0~0~0~0~0~1~0~0" YMax "1~1~10~20~1~1~1~1~1~1" SaveName "ScopeData9" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType Reference Name "Register" SID "17143" Ports [2, 1] Position [415, 388, 455, 457] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "40,69,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 69 69 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 69 69 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[39.55 39.55 44." "55 39.55 44.55 44.55 44.55 39.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[34.55 34.55 39.55 39.55 34." "55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[29.55 29.55 34.55 34.55 29.55 ],[1 1 1 ]);\npa" "tch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[24.55 24.55 29.55 24.55 29.55 29.55 24.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i" "nput',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\ncolor('blac" "k');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "17145" Ports [2, 1] Position [1300, 408, 1340, 477] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "40,69,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 69 69 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 69 69 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[39.55 39.55 44." "55 39.55 44.55 44.55 44.55 39.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[34.55 34.55 39.55 39.55 34." "55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[29.55 29.55 34.55 34.55 29.55 ],[1 1 1 ]);\npa" "tch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[24.55 24.55 29.55 24.55 29.55 29.55 24.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i" "nput',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\ncolor('blac" "k');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational1" SID "17146" Ports [2, 1] Position [1030, 528, 1080, 572] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "50,44,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 44 44 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 50 50 0 0 ],[0 0 44 44 0 ]);\npatch([11.65 20.32 26.32 32.32 38.32 26.32 17.65 11.65 ],[28.66 28.66" " 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([17.65 26.32 20.32 11.65 17.65 ],[22.66 22.66 28.66 28.66" " 22.66 ],[0.931 0.946 0.973 ]);\npatch([11.65 20.32 26.32 17.65 11.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1 1 ])" ";\npatch([17.65 38.32 32.32 26.32 20.32 11.65 17.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0.946 0." "973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa = b'," "'texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name " Bit" SID "17147" Position [1420, 438, 1450, 452] ZOrder -23 IconDisplay "Port number" } Block { BlockType Outport Name "Bit Valid" SID "17148" Position [1420, 543, 1450, 557] ZOrder -23 Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "Synced" SID "17149" Position [1420, 693, 1450, 707] ZOrder -23 Port "3" IconDisplay "Port number" } Line { SrcBlock "Address Gen" SrcPort 1 Points [160, 0] Branch { DstBlock "Bit Hist RAM" DstPort 2 } Branch { Points [0, 70] DstBlock "Delay" DstPort 1 } } Line { SrcBlock "Address Gen" SrcPort 2 DstBlock "Bit Hist RAM" DstPort 3 } Line { SrcBlock "Address Gen" SrcPort 3 DstBlock "Bit Hist RAM" DstPort 4 } Line { SrcBlock "Delay" SrcPort 1 DstBlock "Matching" DstPort 3 } Line { SrcBlock "Address Gen" SrcPort 4 Points [130, 0; 0, 50] DstBlock "Matching" DstPort 4 } Line { SrcBlock "Address Gen" SrcPort 5 Points [120, 0; 0, 70] DstBlock "Matching" DstPort 5 } Line { SrcBlock "Bit Hist RAM" SrcPort 1 DstBlock "Matching" DstPort 1 } Line { SrcBlock "Bit Hist RAM" SrcPort 2 DstBlock "Matching" DstPort 2 } Line { SrcBlock "Bit" SrcPort 1 Points [70, 0] Branch { Points [0, -280] DstBlock "Gateway Out3" DstPort 1 } Branch { DstBlock "Delay4" DstPort 1 } } Line { SrcBlock "Valid" SrcPort 1 Points [60, 0] Branch { DstBlock "Delay5" DstPort 1 } Branch { Points [0, 100] DstBlock "Address Gen" DstPort 1 } Branch { Points [0, -335] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "Register" SrcPort 1 Points [35, 0] Branch { Points [0, 45] DstBlock "Bit Hist RAM" DstPort 1 } Branch { Points [750, 0] Branch { DstBlock "Register2" DstPort 1 } Branch { Points [0, -240] DstBlock "Gateway Out9" DstPort 1 } } } Line { SrcBlock "IQ Mag" SrcPort 1 Points [45, 0] Branch { Points [0, -560] DstBlock "Gateway Out4" DstPort 1 } Branch { DstBlock "Delay1" DstPort 1 } } Line { SrcBlock "Address Gen" SrcPort 6 Points [130, 0; 0, 80] Branch { Points [0, 125; 500, 0; 0, -235] Branch { DstBlock "Relational1" DstPort 2 } Branch { Points [0, -395] DstBlock "Gateway Out8" DstPort 1 } } Branch { DstBlock "Delay2" DstPort 1 } } Line { SrcBlock "Matching" SrcPort 1 DstBlock "Relational1" DstPort 1 } Line { SrcBlock "Relational1" SrcPort 1 Points [5, 0] Branch { DstBlock "Logical3" DstPort 2 } Branch { Points [0, -325] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "Matching" SrcPort 2 Points [40, 0] Branch { DstBlock "Synced" DstPort 1 } Branch { Points [0, -120] Branch { Points [0, -335] DstBlock "Gateway Out5" DstPort 1 } Branch { DstBlock "Logical3" DstPort 3 } } } Line { SrcBlock "Register2" SrcPort 1 Points [25, 0] Branch { DstBlock " Bit" DstPort 1 } Branch { Points [0, -160] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "Delay3" SrcPort 1 Points [25, 0] Branch { DstBlock "Bit Valid" DstPort 1 } Branch { Points [0, -285] DstBlock "Gateway Out1" DstPort 1 } } Line { Name "Sel Phase Valid" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 DstBlock "Phase Sel Decision" DstPort 8 } Line { Name "Output Bit Valid" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 DstBlock "Phase Sel Decision" DstPort 9 } Line { Name "Input Bit Valid" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 DstBlock "Phase Sel Decision" DstPort 1 } Line { Name "Input Bit" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 DstBlock "Phase Sel Decision" DstPort 2 } Line { Name "Input IQ Mag" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 DstBlock "Phase Sel Decision" DstPort 3 } Line { SrcBlock "Delay1" SrcPort 1 DstBlock "Delay8" DstPort 1 } Line { SrcBlock "Reset" SrcPort 1 DstBlock "Matching" DstPort 8 } Line { SrcBlock "Logical3" SrcPort 1 Points [65, 0] Branch { DstBlock "Delay3" DstPort 1 } Branch { Points [0, -90] Branch { DstBlock "Register2" DstPort 2 } Branch { Points [0, -255] DstBlock "Gateway Out10" DstPort 1 } } } Line { Name "Correct Phase" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 DstBlock "Phase Sel Decision" DstPort 7 } Line { Name "Output Bit" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 DstBlock "Phase Sel Decision" DstPort 10 } Line { SrcBlock "Delay4" SrcPort 1 DstBlock "Register" DstPort 1 } Line { SrcBlock "Delay5" SrcPort 1 Points [60, 0] Branch { DstBlock "Register" DstPort 2 } Branch { Points [0, -95] DstBlock "Delay7" DstPort 1 } Branch { Points [0, 285; 140, 0] Branch { DstBlock "Delay1" DstPort 2 } Branch { Points [0, -35] DstBlock "Delay2" DstPort 2 } } } Line { Name "Despread Phase" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 DstBlock "Phase Sel Decision" DstPort 4 } Line { SrcBlock "Delay7" SrcPort 1 Points [220, 0; 0, 175] DstBlock "Logical3" DstPort 1 } Line { Name "Outbut Bit Latch Input" Labels [0, 0] SrcBlock "Gateway Out9" SrcPort 1 DstBlock "Phase Sel Decision" DstPort 5 } Line { Name "Output Bit Latch En" Labels [0, 0] SrcBlock "Gateway Out10" SrcPort 1 DstBlock "Phase Sel Decision" DstPort 6 } Line { SrcBlock "Delay2" SrcPort 1 DstBlock "Delay6" DstPort 1 } Line { SrcBlock "Delay6" SrcPort 1 DstBlock "Matching" DstPort 6 } Line { SrcBlock "Delay8" SrcPort 1 DstBlock "Matching" DstPort 7 } Annotation { Name "The delay on Despread Phase above accounts for the latency through the matching and search logic.\nThe l" "atency from bit input to \"Match\" assertion is about 2 bit periods. Delaying the\ndespread phase signal here caus" "es the Phase Sel block to select the \"wrong\" phase\nwhen the Match signal asserts. This \"wrong\" phase is actua" "lly the phase that matches \nthe largest IQ Mag selected by the search. The 2-bit-period delay is not applied to\n" "the despread phase signal one subsystem up, where it is used to select the 1-sample-per-symbol\noffset used for de" "coding the rest of the packet." Position [628, 864] } } } Block { BlockType SubSystem Name "Timeouts" SID "17150" Ports [4, 1] Position [1095, 734, 1195, 831] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Timeouts" Location [202, 70, 1830, 1180] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "SFD Found" SID "17151" Position [60, 593, 90, 607] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "Synced" SID "17152" Position [60, 363, 90, 377] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "IQ Valid" SID "17153" Position [545, 388, 575, 402] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "Pkt Det" SID "17154" Position [60, 328, 90, 342] NamePlacement "alternate" Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "Concat" SID "17155" Ports [2, 1] Position [810, 665, 870, 725] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point at z" "ero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "60,60,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 60 60 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[38.88 38.88 46" ".88 38.88 46.88 46.88 46.88 38.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[30.88 30.88 38.88 38.88 30.88" " ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[22.88 22.88 30.88 30.88 22.88 ],[1 1 1 ]);\npatch(" "[20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[14.88 14.88 22.88 14.88 22.88 22.88 14.88 ],[0.931 0.946 0.973 ]);\nfpr" "intf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'" ",1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fontsize{20}\\}','texmode','on');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Concat1" SID "17156" Ports [2, 1] Position [810, 740, 870, 800] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point at z" "ero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "60,60,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 60 60 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[38.88 38.88 46" ".88 38.88 46.88 46.88 46.88 38.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[30.88 30.88 38.88 38.88 30.88" " ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[22.88 22.88 30.88 30.88 22.88 ],[1 1 1 ]);\npatch(" "[20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[14.88 14.88 22.88 14.88 22.88 22.88 14.88 ],[0.931 0.946 0.973 ]);\nfpr" "intf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'" ",1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fontsize{20}\\}','texmode','on');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant1" SID "17157" Ports [0, 1] Position [1015, 383, 1060, 407] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "2^12-10" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "12" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "45,24,0,1,white,blue,0,c59ccb43,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 24 24 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 24 24 0 ]);\npatch([15.325 19.66 22.66 25.66 28.66 22.66 18.325 15.325 ],[15.33 15" ".33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([18.325 22.66 19.66 15.325 18.325 ],[12.33 12.33 15.33" " 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([15.325 19.66 22.66 18.325 15.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 " "1 1 ]);\npatch([18.325 28.66 25.66 22.66 19.66 15.325 18.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port" "_label('output',1,'4086');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant3" SID "17158" Ports [0, 1] Position [735, 697, 760, 723] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "5" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,26,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 " "19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 1" "3.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\n" "patch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('out" "put',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant4" SID "17159" Ports [0, 1] Position [735, 772, 760, 798] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "5" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,26,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 " "19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 1" "3.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\n" "patch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('out" "put',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Scope Name "DSSS Timeouts" SID "17160" Ports [9] Position [1510, 43, 1570, 247] ZOrder -16 Floating off Location [1, 45, 1836, 1199] Open off NumInputPorts "9" ZoomMode "yonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" axes9 "%" } List { ListType ScopeGraphics FigureColor "[0.5 0.5 0.5]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "41980 " YMin "-1~0~-1~0~-1~-1~-1~-1~-1" YMax "1~1750~1~1~1~1~1~1~1" SaveName "ScopeData8" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType Display Name "Display" SID "17161" Ports [1] Position [1115, 680, 1205, 710] ZOrder -1 ShowName off Decimation "1" Lockdown off } Block { BlockType Display Name "Display1" SID "17162" Ports [1] Position [1115, 755, 1205, 785] ZOrder -1 ShowName off Decimation "1" Lockdown off } Block { BlockType From Name "From1" SID "17163" Position [530, 670, 725, 690] ZOrder -9 ShowName off GotoTag "regRx_DSSS_SYNC_Timeout" TagVisibility "global" } Block { BlockType From Name "From2" SID "17164" Position [600, 235, 715, 255] ZOrder -9 ShowName off GotoTag "DSSS_RX_RESET" TagVisibility "global" } Block { BlockType From Name "From3" SID "17165" Position [530, 745, 725, 765] ZOrder -9 ShowName off GotoTag "regRx_DSSS_SFD_Timeout" TagVisibility "global" } Block { BlockType From Name "From4" SID "17166" Position [130, 385, 245, 405] ZOrder -9 ShowName off GotoTag "DSSS_RX_RESET" TagVisibility "global" } Block { BlockType From Name "From5" SID "18020" Position [375, 892, 600, 908] ZOrder -9 ShowName off GotoTag "regRx_DSSS_SYNC_Blocks_Late_PktDet" TagVisibility "global" } Block { BlockType Reference Name "Gateway Out1" SID "17167" Ports [1, 1] Position [1400, 139, 1435, 151] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "SFD Found" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "17168" Ports [1, 1] Position [1400, 159, 1435, 171] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Timeout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "17169" Ports [1, 1] Position [1400, 79, 1435, 91] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Samp Count" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "17170" Ports [1, 1] Position [1400, 119, 1435, 131] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Synced" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "17171" Ports [1, 1] Position [1400, 59, 1435, 71] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Pkt Det" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "17172" Ports [1, 1] Position [1030, 689, 1065, 701] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "Gateway Out7" SID "17173" Ports [1, 1] Position [1035, 764, 1070, 776] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Goto Name "Goto1" SID "18017" Position [875, 891, 1085, 909] ZOrder -10 ShowName off GotoTag "DSSS_SYNC_PktDet_Block" TagVisibility "global" } Block { BlockType Reference Name "Inverter1" SID "18019" Ports [1, 1] Position [615, 869, 645, 891] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "30,22,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 22 22 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[14.33 14.3" "3 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[11.33 11.33 14.33 14" ".33 11.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 1 1 ]" ");\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 0.973 " "]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('" "not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter2" SID "17174" Ports [1, 1] Position [855, 514, 885, 536] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "30,22,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 22 22 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[14.33 14.3" "3 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[11.33 11.33 14.33 14" ".33 11.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 1 1 ]" ");\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 0.973 " "]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('" "not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter3" SID "17175" Ports [1, 1] Position [855, 589, 885, 611] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "30,22,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 22 22 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[14.33 14.3" "3 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[11.33 11.33 14.33 14" ".33 11.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 1 1 ]" ");\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 0.973 " "]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('" "not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "17176" Ports [3, 1] Position [655, 361, 685, 429] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,68,3,1,white,blue,0,98d76266,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 68 68 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 68 68 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[38.44 38.44 42.4" "4 38.44 42.44 42.44 42.44 38.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[34.44 34.44 38.44 38.44 34.44 ]," "[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[30.44 30.44 34.44 34.44 30.44 ],[1 1 1 ]);\npatch([10.1" " 23.88 19.88 15.88 11.88 6.1 10.1 ],[26.44 26.44 30.44 26.44 30.44 30.44 26.44 ],[0.931 0.946 0.973 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\ncolor('black');disp('and');\nfp" "rintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "17177" Ports [3, 1] Position [800, 227, 835, 323] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,96,3,1,white,blue,0,a2abe52d,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 96 96 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 96 96 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[53.55 53.55 58." "55 53.55 58.55 58.55 58.55 53.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[48.55 48.55 53.55 53.55 48." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[43.55 43.55 48.55 48.55 43.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[38.55 38.55 43.55 38.55 43.55 43.55 38.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\ncolor('black');disp(" "'or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical3" SID "17178" Ports [2, 1] Position [1215, 471, 1245, 544] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,73,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 73 73 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 73 73 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[40.44 40.44 44.4" "4 40.44 44.44 44.44 44.44 40.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[36.44 36.44 40.44 40.44 36.44 ]," "[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[32.44 32.44 36.44 36.44 32.44 ],[1 1 1 ]);\npatch([10.1" " 23.88 19.88 15.88 11.88 6.1 10.1 ],[28.44 28.44 32.44 28.44 32.44 32.44 28.44 ],[0.931 0.946 0.973 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('and');\nfpri" "ntf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical4" SID "17179" Ports [2, 1] Position [1305, 491, 1335, 564] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,73,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 73 73 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 73 73 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[40.44 40.44 44.4" "4 40.44 44.44 44.44 44.44 40.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[36.44 36.44 40.44 40.44 36.44 ]," "[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[32.44 32.44 36.44 36.44 32.44 ],[1 1 1 ]);\npatch([10.1" " 23.88 19.88 15.88 11.88 6.1 10.1 ],[28.44 28.44 32.44 28.44 32.44 32.44 28.44 ],[0.931 0.946 0.973 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('or');\nfprin" "tf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical5" SID "17180" Ports [3, 1] Position [1215, 550, 1245, 650] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,100,3,1,white,blue,0,98d76266,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 100 100 0 ],[0.77 0.82 0" ".91 ]);\nplot([0 30 30 0 0 ],[0 0 100 100 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[54.44 54.44 " "58.44 54.44 58.44 58.44 58.44 54.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[50.44 50.44 54.44 54.44 50.4" "4 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[46.44 46.44 50.44 50.44 46.44 ],[1 1 1 ]);\npatch([" "10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[42.44 42.44 46.44 42.44 46.44 46.44 42.44 ],[0.931 0.946 0.973 ]);\nfprin" "tf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\ncolor('black');disp('and');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical6" SID "17181" Ports [2, 1] Position [215, 316, 245, 389] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,73,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 73 73 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 73 73 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[40.44 40.44 44.4" "4 40.44 44.44 44.44 44.44 40.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[36.44 36.44 40.44 40.44 36.44 ]," "[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[32.44 32.44 36.44 36.44 32.44 ],[1 1 1 ]);\npatch([10.1" " 23.88 19.88 15.88 11.88 6.1 10.1 ],[28.44 28.44 32.44 28.44 32.44 32.44 28.44 ],[0.931 0.946 0.973 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('or');\nfprin" "tf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical7" SID "18018" Ports [3, 1] Position [730, 866, 760, 934] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,68,3,1,white,blue,0,98d76266,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 68 68 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 68 68 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[38.44 38.44 42.4" "4 38.44 42.44 42.44 42.44 38.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[34.44 34.44 38.44 38.44 34.44 ]," "[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[30.44 30.44 34.44 34.44 30.44 ],[1 1 1 ]);\npatch([10.1" " 23.88 19.88 15.88 11.88 6.1 10.1 ],[26.44 26.44 30.44 26.44 30.44 30.44 26.44 ],[0.931 0.946 0.973 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\ncolor('black');disp('and');\nfp" "rintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Posedge" SID "17182" Ports [1, 1] Position [490, 268, 535, 282] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Posedge" Location [90, 283, 1701, 1127] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "17183" Position [265, 183, 295, 197] IconDisplay "Port number" } Block { BlockType Reference Name "Delay" SID "17184" Ports [1, 1] Position [425, 153, 460, 177] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. " "If register retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[15" ".33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.33 12." "33 15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 12.33 " "9.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\nc" "olor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "17185" Ports [1, 1] Position [490, 156, 515, 174] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "17186" Ports [2, 1] Position [540, 151, 585, 204] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,53,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 53 53 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 53 53 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[32.66 3" "2.66 38.66 32.66 38.66 38.66 38.66 32.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[26.66 26.66 32.66 " "32.66 26.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[20.66 20.66 26.66 26.66 20.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[14.66 14.66 20.66 14.66 20.66 20.66 14.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('" "black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "17187" Position [610, 173, 640, 187] IconDisplay "Port number" } Line { SrcBlock "D" SrcPort 1 Points [85, 0] Branch { DstBlock "Logical1" DstPort 2 } Branch { Points [0, -25] DstBlock "Delay" DstPort 1 } } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Delay" SrcPort 1 DstBlock "Inverter" DstPort 1 } } } Block { BlockType SubSystem Name "Posedge1" SID "17188" Ports [1, 1] Position [490, 298, 535, 312] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Posedge1" Location [90, 283, 1701, 1127] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "17189" Position [265, 183, 295, 197] IconDisplay "Port number" } Block { BlockType Reference Name "Delay" SID "17190" Ports [1, 1] Position [425, 153, 460, 177] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. " "If register retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[15" ".33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.33 12." "33 15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 12.33 " "9.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\nc" "olor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "17191" Ports [1, 1] Position [490, 156, 515, 174] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "17192" Ports [2, 1] Position [540, 151, 585, 204] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,53,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 53 53 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 53 53 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[32.66 3" "2.66 38.66 32.66 38.66 38.66 38.66 32.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[26.66 26.66 32.66 " "32.66 26.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[20.66 20.66 26.66 26.66 20.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[14.66 14.66 20.66 14.66 20.66 20.66 14.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('" "black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "17193" Position [610, 173, 640, 187] IconDisplay "Port number" } Line { SrcBlock "Delay" SrcPort 1 DstBlock "Inverter" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "D" SrcPort 1 Points [85, 0] Branch { Points [0, -25] DstBlock "Delay" DstPort 1 } Branch { DstBlock "Logical1" DstPort 2 } } } } Block { BlockType Reference Name "Relational1" SID "17194" Ports [2, 1] Position [1100, 365, 1140, 405] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "40,40,2,1,white,blue,0,6218dc92,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25.55 30." "55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 25.55 20." "55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1 1 ]);\npa" "tch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i" "nput',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa \\geq b','te" "xmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational3" SID "17196" Ports [2, 1] Position [1100, 545, 1140, 585] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a>=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "40,40,2,1,white,blue,0,6218dc92,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25.55 30." "55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 25.55 20." "55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1 1 ]);\npa" "tch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i" "nput',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa \\geq b','te" "xmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "S-R Latch" SID "17197" Ports [2, 1] Position [335, 334, 375, 416] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "S-R Latch" Location [351, 366, 2001, 1172] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "17198" Position [140, 103, 170, 117] IconDisplay "Port number" } Block { BlockType Inport Name "R" SID "17199" Position [140, 88, 170, 102] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "17200" Ports [0, 1] Position [195, 71, 210, 89] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "15,18,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11.22 " "13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 9.22 " "],[0.931 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([4.55 " "11.44 9.44 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "17201" Ports [1, 1] Position [210, 86, 235, 104] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('outpu" "t',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "17202" Ports [1, 1] Position [210, 101, 235, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('outpu" "t',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "17203" Ports [3, 1] Position [255, 71, 300, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "17204" Position [325, 88, 355, 102] IconDisplay "Port number" } Line { SrcBlock "Convert2" SrcPort 1 DstBlock "Register2" DstPort 3 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "S" SrcPort 1 DstBlock "Convert2" DstPort 1 } } } Block { BlockType Reference Name "Sample Counter" SID "17205" Ports [2, 1] Position [895, 336, 955, 414] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited counter i" "s implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "Inf" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "12" bin_pt "0" load_pin off rst on en on explicit_period "off" period "1" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "counter" sg_icon_stat "60,78,2,1,white,blue,0,ae3608d6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 78 78 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 60 60 0 0 ],[0 0 78 78 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[47.88 47.88 55" ".88 47.88 55.88 55.88 55.88 47.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[39.88 39.88 47.88 47.88 39.88" " ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[31.88 31.88 39.88 39.88 31.88 ],[1 1 1 ]);\npatch(" "[20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[23.88 23.88 31.88 23.88 31.88 31.88 23.88 ],[0.931 0.946 0.973 ]);\nfpr" "intf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'" ",1,'rst');\ncolor('black');port_label('input',2,'en');\n\ncolor('black');disp('{\\fontsize{14}\\bf++}','texmode','" "on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Timeout" SID "17206" Position [1495, 523, 1525, 537] ZOrder -23 IconDisplay "Port number" } Line { SrcBlock "Concat1" SrcPort 1 Points [145, 0] Branch { Points [0, -195] DstBlock "Relational3" DstPort 2 } Branch { DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "Constant4" SrcPort 1 DstBlock "Concat1" DstPort 2 } Line { SrcBlock "From3" SrcPort 1 DstBlock "Concat1" DstPort 1 } Line { SrcBlock "Concat" SrcPort 1 Points [140, 0] Branch { Points [0, -195] DstBlock "Relational2" DstPort 2 } Branch { DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "Constant3" SrcPort 1 DstBlock "Concat" DstPort 2 } Line { SrcBlock "From1" SrcPort 1 DstBlock "Concat" DstPort 1 } Line { Name "Pkt Det" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 DstBlock "DSSS Timeouts" DstPort 1 } Line { Name "Samp Count" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 DstBlock "DSSS Timeouts" DstPort 2 } Line { Name "Timeout" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 DstBlock "DSSS Timeouts" DstPort 6 } Line { Name "SFD Found" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 DstBlock "DSSS Timeouts" DstPort 5 } Line { Name "Synced" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 DstBlock "DSSS Timeouts" DstPort 4 } Line { SrcBlock "Logical4" SrcPort 1 Points [15, 0] Branch { DstBlock "Timeout" DstPort 1 } Branch { Points [0, -365] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "Logical5" SrcPort 1 Points [35, 0; 0, -55] DstBlock "Logical4" DstPort 2 } Line { SrcBlock "Logical3" SrcPort 1 DstBlock "Logical4" DstPort 1 } Line { SrcBlock "Inverter3" SrcPort 1 DstBlock "Logical5" DstPort 2 } Line { SrcBlock "SFD Found" SrcPort 1 Points [75, 0] Branch { DstBlock "Inverter3" DstPort 1 } Branch { Points [0, -455] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "Relational3" SrcPort 1 DstBlock "Logical5" DstPort 1 } Line { SrcBlock "Inverter2" SrcPort 1 DstBlock "Logical3" DstPort 2 } Line { SrcBlock "Relational2" SrcPort 1 DstBlock "Logical3" DstPort 1 } Line { SrcBlock "Relational1" SrcPort 1 Points [20, 0; 0, 70; -545, 0; 0, -40] DstBlock "Logical1" DstPort 3 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Relational1" DstPort 2 } Line { SrcBlock "Sample Counter" SrcPort 1 Points [25, 0] Branch { Points [0, 105] Branch { Points [0, 75] DstBlock "Relational3" DstPort 1 } Branch { DstBlock "Relational2" DstPort 1 } } Branch { DstBlock "Relational1" DstPort 1 } Branch { Points [0, -290] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "From2" SrcPort 1 DstBlock "Logical2" DstPort 1 } Line { SrcBlock "Logical2" SrcPort 1 Points [30, 0; 0, 80] DstBlock "Sample Counter" DstPort 1 } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Sample Counter" DstPort 2 } Line { SrcBlock "IQ Valid" SrcPort 1 DstBlock "Logical1" DstPort 2 } Line { SrcBlock "Posedge" SrcPort 1 DstBlock "Logical2" DstPort 2 } Line { SrcBlock "Pkt Det" SrcPort 1 Points [50, 0] Branch { Points [45, 0] Branch { DstBlock "Logical6" DstPort 1 } Branch { Points [0, -60] Branch { Points [0, -210] DstBlock "Gateway Out5" DstPort 1 } Branch { DstBlock "Posedge" DstPort 1 } } } Branch { Points [0, 545] DstBlock "Inverter1" DstPort 1 } } Line { SrcBlock "Synced" SrcPort 1 Points [85, 0] Branch { Points [10, 0] Branch { DstBlock "Logical6" DstPort 2 } Branch { Points [0, 155; 615, 0] Branch { DstBlock "Inverter2" DstPort 1 } Branch { Points [0, 110] DstBlock "Logical5" DstPort 3 } } } Branch { Points [0, -65] Branch { Points [0, -180] DstBlock "Gateway Out4" DstPort 1 } Branch { DstBlock "Posedge1" DstPort 1 } } Branch { Points [0, 550] DstBlock "Logical7" DstPort 3 } } Line { SrcBlock "Logical6" SrcPort 1 DstBlock "S-R Latch" DstPort 1 } Line { SrcBlock "S-R Latch" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "From4" SrcPort 1 DstBlock "S-R Latch" DstPort 2 } Line { SrcBlock "Gateway Out6" SrcPort 1 DstBlock "Display" DstPort 1 } Line { SrcBlock "Gateway Out7" SrcPort 1 DstBlock "Display1" DstPort 1 } Line { SrcBlock "Posedge1" SrcPort 1 DstBlock "Logical2" DstPort 3 } Line { SrcBlock "Inverter1" SrcPort 1 DstBlock "Logical7" DstPort 1 } Line { SrcBlock "From5" SrcPort 1 DstBlock "Logical7" DstPort 2 } Line { SrcBlock "Logical7" SrcPort 1 DstBlock "Goto1" DstPort 1 } Annotation { Name "Optionally block OFDM and DSSS pkt det events when\nDSSS PHY has found SYNC field without pkt det. A \np" "ost-SYNC pkt det event will trigger AGC mid-waveform\nwhich can corrupt the DSSS waveform being received." Position [720, 994] } } } Block { BlockType ToWorkspace Name "To Workspace" SID "17405" Ports [1] Position [1425, 534, 1530, 556] ZOrder -7 ShowName off VariableName "dsss_rx_byte" MaxDataPoints "inf" SampleTime "-1" SaveFormat "Array" } Block { BlockType ToWorkspace Name "To Workspace1" SID "17406" Ports [1] Position [1425, 565, 1530, 585] ZOrder -7 ShowName off VariableName "dsss_rx_byte_valid" MaxDataPoints "inf" SampleTime "-1" SaveFormat "Array" } Block { BlockType Outport Name "Byte" SID "17207" Position [1325, 448, 1355, 462] ZOrder -9 NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Outport Name "Byte Valid" SID "17208" Position [1380, 463, 1410, 477] ZOrder -9 Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "Byte Ind" SID "17209" Position [1325, 478, 1355, 492] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "CRC Calc" SID "17210" Position [1325, 393, 1355, 407] Port "4" IconDisplay "Port number" } Line { SrcBlock "IQ Valid" SrcPort 1 Points [120, 0] Branch { DstBlock "Demod" DstPort 1 } Branch { Points [0, 255] DstBlock "Timeouts" DstPort 3 } } Line { SrcBlock "I" SrcPort 1 DstBlock "Demod" DstPort 2 } Line { SrcBlock "Q" SrcPort 1 DstBlock "Demod" DstPort 3 } Line { SrcBlock "Demod" SrcPort 2 DstBlock "SYNC and Phase Sel" DstPort 2 } Line { SrcBlock "Demod" SrcPort 1 DstBlock "SYNC and Phase Sel" DstPort 1 } Line { SrcBlock "Demod" SrcPort 3 DstBlock "SYNC and Phase Sel" DstPort 3 } Line { SrcBlock "Header CRC" SrcPort 1 DstBlock "CRC Calc" DstPort 1 } Line { SrcBlock "SYNC and Phase Sel" SrcPort 1 Points [10, 0] Branch { DstBlock "Descramble" DstPort 1 } Branch { Points [0, -420] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "SYNC and Phase Sel" SrcPort 2 Points [15, 0] Branch { DstBlock "Descramble" DstPort 2 } Branch { Points [0, -430] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "Descramble" SrcPort 1 Points [20, 0] Branch { DstBlock "SFD Search" DstPort 1 } Branch { Points [0, -95] Branch { DstBlock "Bit-to-Byte" DstPort 1 } Branch { Points [0, -75] Branch { DstBlock "Header CRC" DstPort 1 } Branch { Points [0, -215] DstBlock "Register" DstPort 1 } } } } Line { SrcBlock "Descramble" SrcPort 2 Points [25, 0] Branch { DstBlock "SFD Search" DstPort 2 } Branch { Points [0, -110] Branch { DstBlock "Logical1" DstPort 1 } Branch { Points [0, -290] DstBlock "Register" DstPort 2 } } } Line { SrcBlock "SYNC and Phase Sel" SrcPort 3 Points [20, 0] Branch { DstBlock "Logical" DstPort 2 } Branch { Points [0, -340] DstBlock "Gateway Out4" DstPort 1 } Branch { Points [0, 155] DstBlock "Timeouts" DstPort 2 } } Line { SrcBlock "SFD Search" SrcPort 1 Points [35, 0; 0, 30] DstBlock "Logical" DstPort 1 } Line { SrcBlock "Logical" SrcPort 1 DstBlock "S-R Latch" DstPort 1 } Line { SrcBlock "S-R Latch" SrcPort 1 Points [10, 0] Branch { Points [0, -140] Branch { DstBlock "Logical1" DstPort 2 } Branch { Points [0, -195] DstBlock "Gateway Out5" DstPort 1 } } Branch { Points [0, 115] DstBlock "Timeouts" DstPort 1 } } Line { SrcBlock "Bit-to-Byte" SrcPort 1 Points [35, 0] Branch { DstBlock "Byte" DstPort 1 } Branch { Points [0, 90] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "Bit-to-Byte" SrcPort 3 DstBlock "Byte Ind" DstPort 1 } Line { SrcBlock "Bit-to-Byte" SrcPort 2 Points [30, 0] Branch { DstBlock "Byte Valid" DstPort 1 } Branch { Points [0, 105] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "Logical1" SrcPort 1 Points [15, 0] Branch { Points [0, -75] DstBlock "Header CRC" DstPort 2 } Branch { DstBlock "Bit-to-Byte" DstPort 2 } } Line { Name "SFD Found" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 DstBlock "DSSS Demod" DstPort 9 } Line { Name "Synced" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 DstBlock "DSSS Demod" DstPort 8 } Line { Name "Synced Bit" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 DstBlock "DSSS Demod" DstPort 1 } Line { Name "Synced Bit Valid" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 DstBlock "DSSS Demod" DstPort 2 } Line { Name "Descrambled Bit" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 DstBlock "DSSS Demod" DstPort 3 } Line { SrcBlock "Register" SrcPort 1 Points [0, -5] DstBlock "Gateway Out3" DstPort 1 } Line { SrcBlock "Pkt Det" SrcPort 1 Points [70, 0] Branch { Labels [0, 0] Points [0, -135] DstBlock "Resets" DstPort 1 } Branch { DstBlock "Timeouts" DstPort 4 } } Line { SrcBlock "Timeouts" SrcPort 1 DstBlock "Goto" DstPort 1 } Line { SrcBlock "Resets" SrcPort 1 Points [55, 0; 0, -35] Branch { Points [0, -30] DstBlock "SYNC and Phase Sel" DstPort 4 } Branch { DstBlock "S-R Latch" DstPort 2 } } Line { SrcBlock "2Mb_Payload" SrcPort 1 DstBlock "Demod" DstPort 4 } Line { SrcBlock "Gateway Out6" SrcPort 1 DstBlock "To Workspace" DstPort 1 } Line { SrcBlock "Gateway Out7" SrcPort 1 DstBlock "To Workspace1" DstPort 1 } } } Block { BlockType From Name "From1" SID "18153" Position [275, 565, 435, 585] ShowName off CloseFcn "tagdialog Close" GotoTag "RX_STARTED_TO_MAC" TagVisibility "global" } Block { BlockType From Name "From3" SID "17211" Position [425, 615, 585, 635] ZOrder -9 ShowName off GotoTag "DSSS_RX_TIMEOUT" TagVisibility "global" } Block { BlockType From Name "From4" SID "17212" Position [425, 595, 585, 615] ZOrder -9 ShowName off GotoTag "DSSS_RX_DATA_DONE" TagVisibility "global" } Block { BlockType From Name "From6" SID "17213" Position [275, 540, 435, 560] ZOrder -9 ShowName off GotoTag "regRx_DSSS_RX_EN" TagVisibility "global" } Block { BlockType From Name "From7" SID "17214" Position [425, 655, 645, 675] ShowName off CloseFcn "tagdialog Close" GotoTag "OFDM_RX_RUNNING_DSSS_BLOCK" TagVisibility "global" } Block { BlockType From Name "From8" SID "17215" Position [425, 635, 585, 655] ZOrder -9 ShowName off GotoTag "RX_GLOBAL_RESET" TagVisibility "global" } Block { BlockType Goto Name "Goto1" SID "17216" Position [1180, 601, 1285, 629] ZOrder -10 ShowName off GotoTag "DSSS_RX_RESET" TagVisibility "global" } Block { BlockType Goto Name "Goto2" SID "17217" Position [710, 281, 945, 299] ZOrder -10 ShowName off GotoTag "DSSS_SIGNAL_LENGTH" TagVisibility "global" } Block { BlockType Goto Name "Goto3" SID "17218" Position [710, 311, 945, 329] ZOrder -10 ShowName off GotoTag "RX_START_DSSS_SIGNAL_VALID" TagVisibility "global" } Block { BlockType Goto Name "Goto4" SID "17219" Position [1075, 471, 1310, 489] ZOrder -10 ShowName off GotoTag "DSSS_RX_RUNNING" TagVisibility "global" } Block { BlockType Goto Name "Goto5" SID "17220" Position [1075, 531, 1310, 549] ZOrder -10 ShowName off GotoTag "DSSS_RX_END" TagVisibility "global" } Block { BlockType Goto Name "Goto6" SID "17412" Position [710, 371, 945, 389] ZOrder -10 ShowName off GotoTag "RX_START_DSSS_PHY_HDR_MCS" TagVisibility "global" } Block { BlockType Reference Name "Inverter1" SID "17221" Ports [1, 1] Position [475, 542, 505, 558] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "30,16,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 16 16 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 16 16 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[10.22 10.22 1" "2.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[8.22 8.22 10.22 10.22 8.22" " ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatch([12" ".55 19.44 17.44 15.44 13.44 10.55 12.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprintf(''," "'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfprintf('" "','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter2" SID "18154" Ports [1, 1] Position [475, 566, 505, 584] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "30,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 18 18 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[11.22 11.22 1" "3.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[9.22 9.22 11.22 11.22 9.22" " ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([12" ".55 19.44 17.44 15.44 13.44 10.55 12.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf(''," "'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfprintf('" "','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "17222" Ports [2, 1] Position [985, 520, 1025, 555] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,35,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 35 35 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 35 35 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[22.55 22.55 27.55" " 22.55 27.55 27.55 27.55 22.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[17.55 17.55 22.55 22.55 17.55 " "],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[12.55 12.55 17.55 17.55 12.55 ],[1 1 1 ]);\npatch(" "[13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[7.55 7.55 12.55 7.55 12.55 12.55 7.55 ],[0.931 0.946 0.973 ]);\nfprintf" "('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('and');\nfpr" "intf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical4" SID "17223" Ports [6, 1] Position [820, 549, 855, 681] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "6" en off latency "1" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,132,6,1,white,blue,0,858f29b1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 132 132 0 ],[0.77 0.82 0." "91 ]);\nplot([0 35 35 0 0 ],[0 0 132 132 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[71.55 71.55 7" "6.55 71.55 76.55 76.55 76.55 71.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[66.55 66.55 71.55 71.55 66" ".55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[61.55 61.55 66.55 66.55 61.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[56.55 56.55 61.55 56.55 61.55 61.55 56.55 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\n\n\n\ncolor('black');di" "sp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\nor');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical7" SID "18155" Ports [2, 1] Position [560, 535, 600, 590] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,55,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 55 55 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 55 55 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[32.55 32.55 37.55" " 32.55 37.55 37.55 37.55 32.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[27.55 27.55 32.55 32.55 27.55 " "],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[22.55 22.55 27.55 27.55 22.55 ],[1 1 1 ]);\npatch(" "[13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[17.55 17.55 22.55 17.55 22.55 22.55 17.55 ],[0.931 0.946 0.973 ]);\nfpr" "intf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('and');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register" SID "17224" Ports [1, 1] Position [760, 151, 785, 179] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,28,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 17.33 20" ".33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33 17.33 14.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" Port { PortNumber 1 Name "byte" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Register1" SID "17225" Ports [1, 1] Position [760, 176, 785, 204] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,28,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 17.33 20" ".33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33 17.33 14.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" Port { PortNumber 1 Name "byte_valid" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Register2" SID "17226" Ports [1, 1] Position [760, 201, 785, 229] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,28,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 17.33 20" ".33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33 17.33 14.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" Port { PortNumber 1 Name "byte_index" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Register3" SID "17227" Ports [1, 1] Position [1180, 416, 1205, 444] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,28,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 17.33 20" ".33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33 17.33 14.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register4" SID "17228" Ports [1, 1] Position [1120, 416, 1145, 444] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,28,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 17.33 20" ".33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33 17.33 14.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register5" SID "17229" Ports [1, 1] Position [1065, 416, 1090, 444] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,28,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 17.33 20" ".33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33 17.33 14.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register6" SID "17230" Ports [1, 1] Position [500, 151, 525, 179] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,28,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 17.33 20" ".33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33 17.33 14.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register7" SID "17231" Ports [1, 1] Position [500, 176, 525, 204] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,28,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 17.33 20" ".33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33 17.33 14.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register8" SID "17232" Ports [1, 1] Position [500, 201, 525, 229] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,28,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 17.33 20" ".33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33 17.33 14.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register9" SID "17233" Ports [1, 1] Position [760, 226, 785, 254] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,28,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 17.33 20" ".33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33 17.33 14.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" Port { PortNumber 1 Name "last_byte" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Relational5" SID "17234" Ports [2, 1] Position [675, 219, 710, 261] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a>b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,42,2,1,white,blue,0,b5131c97,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 42 42 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 42 42 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[26.55 26.55 31.55" " 26.55 31.55 31.55 31.55 26.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[21.55 21.55 26.55 26.55 21.55 " "],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[16.55 16.55 21.55 21.55 16.55 ],[1 1 1 ]);\npatch(" "[10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[11.55 11.55 16.55 11.55 16.55 16.55 11.55 ],[0.931 0.946 0.973 ]);\nfpr" "intf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa > b','texmode','on'" ");\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Reset Gen" SID "17235" Ports [1, 1] Position [950, 595, 1110, 635] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Reset Gen" Location [2, 70, 1830, 1180] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Reset" SID "17236" Position [340, 393, 370, 407] IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "17237" Ports [0, 1] Position [905, 579, 935, 601] BlockMirror on NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "127" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "7" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,22,0,1,white,blue,0,a8544230,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 22 22 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 22 22 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[" "14.33 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[11.33 1" "1.33 14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[8.33 8.33 11.33 11.33" " 8.33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ]," "[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncol" "or('black');port_label('output',1,'127');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Counter1" SID "17238" Ports [2, 1] Position [820, 475, 880, 535] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited co" "unter is implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "Inf" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "7" bin_pt "0" load_pin off rst on en on explicit_period "off" period "1" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "counter" sg_icon_stat "60,60,2,1,white,blue,0,ae3608d6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 60 60 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[38.8" "8 38.88 46.88 38.88 46.88 46.88 46.88 38.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[30.88 30.88 38.8" "8 38.88 30.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[22.88 22.88 30.88 30.88 22.88 ],[1" " 1 1 ]);\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[14.88 14.88 22.88 14.88 22.88 22.88 14.88 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('blac" "k');port_label('input',1,'rst');\ncolor('black');port_label('input',2,'en');\n\ncolor('black');disp('{\\fontsiz" "e{14}\\bf++}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter2" SID "17239" Ports [1, 1] Position [635, 487, 665, 503] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "30,16,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 16 16 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 16 16 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[1" "0.22 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[8.22 8.22 " "10.22 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[6.22 6.22 8.22 8.22 6.22 ],[" "1 1 1 ]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('bla" "ck');disp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "17240" Ports [2, 1] Position [695, 471, 730, 504] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,33,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 33 33 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 33 33 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[20.44 " "20.44 24.44 20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[16.44 16.44 20.44 2" "0.44 16.44 ],[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1 1 1 " "]);\npatch([12.1 25.88 21.88 17.88 13.88 8.1 12.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');" "disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "17241" Ports [2, 1] Position [760, 391, 795, 424] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,33,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 33 33 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 33 33 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[20.44 " "20.44 24.44 20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[16.44 16.44 20.44 2" "0.44 16.44 ],[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1 1 1 " "]);\npatch([12.1 25.88 21.88 17.88 13.88 8.1 12.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');" "disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Posedge" SID "17242" Ports [1, 1] Position [455, 393, 500, 407] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Posedge" Location [90, 283, 1701, 1127] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "17243" Position [265, 183, 295, 197] IconDisplay "Port number" } Block { BlockType Reference Name "Delay" SID "17244" Ports [1, 1] Position [425, 153, 460, 177] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. If r" "egister retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[15.33 15" ".33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.33 12.33 15.33" " 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 " "1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');" "disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "17245" Ports [1, 1] Position [490, 156, 515, 174] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "17246" Ports [2, 1] Position [540, 151, 585, 204] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,53,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 53 53 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 53 53 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[32.66 32.66 3" "8.66 32.66 38.66 38.66 38.66 32.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[26.66 26.66 32.66 32.66 26" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[20.66 20.66 26.66 26.66 20.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[14.66 14.66 20.66 14.66 20.66 20.66 14.66 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('" "and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "17247" Position [610, 173, 640, 187] IconDisplay "Port number" } Line { SrcBlock "D" SrcPort 1 Points [85, 0] Branch { DstBlock "Logical1" DstPort 2 } Branch { Points [0, -25] DstBlock "Delay" DstPort 1 } } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Delay" SrcPort 1 DstBlock "Inverter" DstPort 1 } } } Block { BlockType Reference Name "Relational1" SID "17248" Ports [2, 1] Position [830, 560, 870, 600] BlockMirror on NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "40,40,2,1,white,blue,0,2a81ff49,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55" " 25.55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25" ".55 25.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 " "],[1 1 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor(" "'black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('outp" "ut',1,'\\bfa = b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "S-R Latch" SID "17249" Ports [2, 1] Position [650, 388, 695, 437] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "S-R Latch" Location [13, 209, 2156, 1324] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "17250" Position [140, 103, 170, 117] IconDisplay "Port number" } Block { BlockType Inport Name "R" SID "17251" Position [140, 88, 170, 102] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "17252" Ports [0, 1] Position [195, 71, 210, 89] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "15,18,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11.22 13.22 " "11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 9.22 ],[0.931" " 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([4.55 11.44 9.44" " 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon" " graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "17253" Ports [1, 1] Position [210, 86, 235, 104] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cast');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "17254" Ports [1, 1] Position [210, 101, 235, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cast');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "17255" Ports [3, 1] Position [255, 71, 300, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 30.66 3" "6.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 30.66 24" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('" "input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'en');\ncolor('bl" "ack');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon te" "xt');" } Block { BlockType Outport Name "Q" SID "17256" Position [325, 88, 355, 102] IconDisplay "Port number" } Line { SrcBlock "Convert2" SrcPort 1 DstBlock "Register2" DstPort 3 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "S" SrcPort 1 DstBlock "Convert2" DstPort 1 } } } Block { BlockType SubSystem Name "S-R Latch2" SID "17257" Ports [2, 1] Position [555, 468, 600, 517] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "S-R Latch2" Location [161, 165, 1994, 1406] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "17258" Position [140, 103, 170, 117] IconDisplay "Port number" } Block { BlockType Inport Name "R" SID "17259" Position [140, 88, 170, 102] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "17260" Ports [0, 1] Position [195, 71, 210, 89] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "15,18,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11.22 13.22 " "11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 9.22 ],[0.931" " 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([4.55 11.44 9.44" " 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon" " graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "17261" Ports [1, 1] Position [210, 86, 235, 104] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cast');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "17262" Ports [1, 1] Position [210, 101, 235, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cast');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "17263" Ports [3, 1] Position [255, 71, 300, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 30.66 3" "6.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 30.66 24" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('" "input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'en');\ncolor('bl" "ack');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon te" "xt');" } Block { BlockType Outport Name "Q" SID "17264" Position [325, 88, 355, 102] IconDisplay "Port number" } Line { SrcBlock "S" SrcPort 1 DstBlock "Convert2" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "Convert2" SrcPort 1 DstBlock "Register2" DstPort 3 } } } Block { BlockType SubSystem Name "negedge" SID "17265" Ports [1, 1] Position [455, 473, 500, 487] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "negedge" Location [90, 283, 1701, 1127] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "17266" Position [265, 183, 295, 197] IconDisplay "Port number" } Block { BlockType Reference Name "Delay" SID "17267" Ports [1, 1] Position [425, 153, 460, 177] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. If r" "egister retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[15.33 15" ".33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.33 12.33 15.33" " 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 " "1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');" "disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "17268" Ports [1, 1] Position [490, 181, 515, 199] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "17269" Ports [2, 1] Position [540, 151, 585, 204] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,53,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 53 53 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 53 53 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[32.66 32.66 3" "8.66 32.66 38.66 38.66 38.66 32.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[26.66 26.66 32.66 32.66 26" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[20.66 20.66 26.66 26.66 20.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[14.66 14.66 20.66 14.66 20.66 20.66 14.66 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('" "and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "17270" Position [610, 173, 640, 187] IconDisplay "Port number" } Line { SrcBlock "Delay" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "D" SrcPort 1 Points [85, 0] Branch { Points [0, -25] DstBlock "Delay" DstPort 1 } Branch { DstBlock "Inverter" DstPort 1 } } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical1" DstPort 2 } } } Block { BlockType Outport Name "DSSS Rx Reset" SID "17271" Position [1030, 403, 1060, 417] IconDisplay "Port number" } Line { SrcBlock "Posedge" SrcPort 1 Points [115, 0] Branch { DstBlock "S-R Latch" DstPort 1 } Branch { Points [0, 80] DstBlock "Logical1" DstPort 1 } } Line { SrcBlock "S-R Latch" SrcPort 1 DstBlock "Logical2" DstPort 2 } Line { SrcBlock "Counter1" SrcPort 1 Points [10, 0; 0, 65] DstBlock "Relational1" DstPort 1 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Relational1" DstPort 2 } Line { SrcBlock "negedge" SrcPort 1 DstBlock "S-R Latch2" DstPort 1 } Line { SrcBlock "S-R Latch2" SrcPort 1 Points [10, 0] Branch { Points [0, 25] DstBlock "Counter1" DstPort 2 } Branch { DstBlock "Inverter2" DstPort 1 } } Line { SrcBlock "Relational1" SrcPort 1 Points [-300, 0; 0, -75] Branch { DstBlock "S-R Latch2" DstPort 2 } Branch { Points [0, -80] DstBlock "S-R Latch" DstPort 2 } } Line { SrcBlock "Inverter2" SrcPort 1 DstBlock "Logical1" DstPort 2 } Line { SrcBlock "Reset" SrcPort 1 Points [40, 0] Branch { DstBlock "Posedge" DstPort 1 } Branch { Points [0, 80] DstBlock "negedge" DstPort 1 } Branch { Points [0, -55; 330, 0] DstBlock "Logical2" DstPort 1 } } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Counter1" DstPort 1 } Line { SrcBlock "Logical2" SrcPort 1 DstBlock "DSSS Rx Reset" DstPort 1 } Annotation { Name "Extend the DSSS reset event long enough to flush\nthe DSSS PHY pipeline and to reduce the\nchance " "of spurious double-detections" Position [645, 618] } } } Block { BlockType SubSystem Name "S-R Latch1" SID "17272" Ports [2, 1] Position [900, 453, 945, 502] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "S-R Latch1" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "17273" Position [140, 103, 170, 117] IconDisplay "Port number" } Block { BlockType Inport Name "R" SID "17274" Position [140, 88, 170, 102] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "17275" Ports [0, 1] Position [195, 71, 210, 89] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "15,18,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 " "9.22 ],[0.931 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch(" "[4.55 11.44 9.44 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf(''" ",'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1," "'1');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "17276" Ports [1, 1] Position [210, 86, 235, 104] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do" " not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.2" "2 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 " "11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);" "\npatch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label" "('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "17277" Ports [1, 1] Position [210, 101, 235, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do" " not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.2" "2 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 " "11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);" "\npatch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label" "('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "17278" Ports [3, 1] Position [255, 71, 300, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30." "66 30.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 3" "0.66 30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 " "],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0" ".931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor" "('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('i" "nput',3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfpri" "ntf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "17279" Position [325, 88, 355, 102] IconDisplay "Port number" } Line { SrcBlock "S" SrcPort 1 DstBlock "Convert2" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "Convert2" SrcPort 1 DstBlock "Register2" DstPort 3 } } } Block { BlockType SubSystem Name "SIGNAL Dec" SID "17280" Ports [4, 4] Position [485, 278, 600, 392] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "SIGNAL Dec" Location [687, 487, 2459, 1414] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "80" Block { BlockType Inport Name "Byte" SID "17281" Position [170, 258, 200, 272] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "Byte Valid" SID "17282" Position [170, 283, 200, 297] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "Byte Ind" SID "17283" Position [170, 453, 200, 467] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "CRC Calc" SID "17284" Position [305, 863, 335, 877] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub" SID "17285" Ports [2, 1] Position [1235, 431, 1295, 489] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "1" precision "User Defined" arith_type "Unsigned" n_bits "ceil(log2(MAX_NUM_BYTES))" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL off hw_selection "Fabric" pipelined off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" sg_icon_stat "60,58,2,1,white,blue,0,e85d8a90,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 58 58 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 58 58 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[37.8" "8 37.88 45.88 37.88 45.88 45.88 45.88 37.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[29.88 29.88 37.8" "8 37.88 29.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[21.88 21.88 29.88 29.88 21.88 ],[1" " 1 1 ]);\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[13.88 13.88 21.88 13.88 21.88 21.88 13.88 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('blac" "k');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1" ",'\\bf{a + b}','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp('" " \\newline\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Concat" SID "17286" Ports [2, 1] Position [610, 480, 670, 540] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary poi" "nt at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "60,60,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 60 60 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[38.8" "8 38.88 46.88 38.88 46.88 46.88 46.88 38.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[30.88 30.88 38.8" "8 38.88 30.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[22.88 22.88 30.88 30.88 22.88 ],[1" " 1 1 ]);\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[14.88 14.88 22.88 14.88 22.88 22.88 14.88 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('blac" "k');port_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fontsize{" "20}\\}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Concat1" SID "17287" Ports [2, 1] Position [595, 685, 655, 745] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary poi" "nt at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "60,60,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 60 60 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[38.8" "8 38.88 46.88 38.88 46.88 46.88 46.88 38.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[30.88 30.88 38.8" "8 38.88 30.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[22.88 22.88 30.88 30.88 22.88 ],[1" " 1 1 ]);\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[14.88 14.88 22.88 14.88 22.88 22.88 14.88 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('blac" "k');port_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fontsize{" "20}\\}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant1" SID "17288" Ports [0, 1] Position [270, 469, 295, 491] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "2" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,22,0,1,white,blue,0,fca86624,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 22 22 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 22 22 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[14" ".33 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[11.33 11.33 " "14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[8.33 8.33 11.33 11.33 8.33 ]" ",[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('output',1,'2');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant2" SID "17289" Ports [0, 1] Position [270, 319, 295, 341] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,22,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 22 22 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 22 22 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[14" ".33 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[11.33 11.33 " "14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[8.33 8.33 11.33 11.33 8.33 ]" ",[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('output',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant4" SID "17291" Ports [0, 1] Position [270, 544, 295, 566] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "3" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,22,0,1,white,blue,0,279a71c8,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 22 22 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 22 22 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[14" ".33 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[11.33 11.33 " "14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[8.33 8.33 11.33 11.33 8.33 ]" ",[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('output',1,'3');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant6" SID "17292" Ports [0, 1] Position [270, 704, 295, 726] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "4" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,22,0,1,white,blue,0,85f36853,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 22 22 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 22 22 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[14" ".33 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[11.33 11.33 " "14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[8.33 8.33 11.33 11.33 8.33 ]" ",[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('output',1,'4');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant7" SID "17293" Ports [0, 1] Position [270, 764, 295, 786] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "5" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,22,0,1,white,blue,0,98872051,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 22 22 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 22 22 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[14" ".33 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[11.33 11.33 " "14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[8.33 8.33 11.33 11.33 8.33 ]" ",[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('output',1,'5');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant9" SID "17294" Ports [0, 1] Position [1160, 464, 1185, 486] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "5" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "8" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,22,0,1,white,blue,0,98872051,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 22 22 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 22 22 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[14" ".33 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[11.33 11.33 " "14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[8.33 8.33 11.33 11.33 8.33 ]" ",[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('output',1,'5');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "DOUT" SID "17295" Ports [3, 1] Position [495, 278, 530, 322] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,44,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 44 44 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 44 44 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[27.55" " 27.55 32.55 27.55 32.55 32.55 32.55 27.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[22.55 22.55 27" ".55 27.55 22.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[17.55 17.55 22.55 22.55 17.55 " "],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[12.55 12.55 17.55 12.55 17.55 17.55 12.55 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor(" "'black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('in" "put',3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprin" "tf('','COMMENT: end icon text');" } Block { BlockType Reference Name "DOUT1" SID "17296" Ports [1, 1] Position [1255, 787, 1285, 823] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,36,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 36 36 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 36 36 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[22.44 " "22.44 26.44 22.44 26.44 26.44 26.44 22.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[18.44 18.44 22.44 2" "2.44 18.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[14.44 14.44 18.44 18.44 14.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[10.44 10.44 14.44 10.44 14.44 14.44 10.44 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');po" "rt_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','o" "n');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "DOUT2" SID "17297" Ports [3, 1] Position [495, 428, 530, 472] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,44,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 44 44 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 44 44 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[27.55" " 27.55 32.55 27.55 32.55 32.55 32.55 27.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[22.55 22.55 27" ".55 27.55 22.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[17.55 17.55 22.55 22.55 17.55 " "],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[12.55 12.55 17.55 12.55 17.55 17.55 12.55 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor(" "'black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('in" "put',3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprin" "tf('','COMMENT: end icon text');" } Block { BlockType Reference Name "DOUT3" SID "17298" Ports [3, 1] Position [495, 503, 530, 547] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "4" rst on en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,44,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 44 44 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 44 44 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[27.55" " 27.55 32.55 27.55 32.55 32.55 32.55 27.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[22.55 22.55 27" ".55 27.55 22.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[17.55 17.55 22.55 22.55 17.55 " "],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[12.55 12.55 17.55 12.55 17.55 17.55 12.55 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor(" "'black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('in" "put',3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprin" "tf('','COMMENT: end icon text');" } Block { BlockType Reference Name "DOUT4" SID "17299" Ports [3, 1] Position [495, 723, 530, 767] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,44,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 44 44 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 44 44 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[27.55" " 27.55 32.55 27.55 32.55 32.55 32.55 27.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[22.55 22.55 27" ".55 27.55 22.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[17.55 17.55 22.55 22.55 17.55 " "],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[12.55 12.55 17.55 12.55 17.55 17.55 12.55 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor(" "'black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('in" "put',3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprin" "tf('','COMMENT: end icon text');" } Block { BlockType Reference Name "DOUT5" SID "17300" Ports [3, 1] Position [495, 663, 530, 707] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,44,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 44 44 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 44 44 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[27.55" " 27.55 32.55 27.55 32.55 32.55 32.55 27.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[22.55 22.55 27" ".55 27.55 22.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[17.55 17.55 22.55 22.55 17.55 " "],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[12.55 12.55 17.55 12.55 17.55 17.55 12.55 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor(" "'black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('in" "put',3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprin" "tf('','COMMENT: end icon text');" } Block { BlockType Reference Name "DOUT6" SID "17301" Ports [1, 1] Position [1255, 857, 1285, 893] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,36,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 36 36 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 36 36 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[22.44 " "22.44 26.44 22.44 26.44 26.44 26.44 22.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[18.44 18.44 22.44 2" "2.44 18.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[14.44 14.44 18.44 18.44 14.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[10.44 10.44 14.44 10.44 14.44 14.44 10.44 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');po" "rt_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','o" "n');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "DOUT7" SID "17402" Ports [3, 1] Position [1265, 258, 1295, 312] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,54,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 54 54 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 54 54 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[31.44 " "31.44 35.44 31.44 35.44 35.44 35.44 31.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[27.44 27.44 31.44 3" "1.44 27.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[23.44 23.44 27.44 27.44 23.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[19.44 19.44 23.44 19.44 23.44 23.44 19.44 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');po" "rt_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'en'" ");\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Scope Name "DSSS SIGNAL Decode" SID "17303" Ports [7] Position [1830, 60, 1875, 230] ZOrder -3 Floating off Location [697, 55, 1821, 1190] Open off NumInputPorts "7" ZoomMode "yonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" } List { ListType ScopeGraphics FigureColor "[0.5 0.5 0.5]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "14500 " YMin "-1~-1~972.8~0~-1~-1~-1" YMax "1~1~1075.2~1~1~1~1" SaveName "ScopeData44" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType Reference Name "Delay1" SID "17304" Ports [1, 1] Position [500, 800, 530, 830] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "30,30,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 30 30 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 30 30 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 " "19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 1" "9.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');di" "sp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Display Name "Display" SID "17305" Ports [1] Position [780, 585, 870, 615] ZOrder -1 Decimation "1" Lockdown off } Block { BlockType From Name "From1" SID "17403" Position [1120, 274, 1230, 296] ZOrder -9 ShowName off GotoTag "DSSS_RX_RESET" TagVisibility "global" } Block { BlockType From Name "From3" SID "17306" Position [295, 224, 405, 246] ZOrder -9 ShowName off GotoTag "DSSS_RX_RESET" TagVisibility "global" } Block { BlockType Reference Name "Gateway Out" SID "17307" Ports [1, 1] Position [710, 594, 740, 606] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 30 30 0 0 ],[0 0 12 12 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([13.775 17.22 16.22 15.22 14.22 12.775 13.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out2" SID "17308" Ports [1, 1] Position [1625, 64, 1655, 76] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 30 30 0 0 ],[0 0 12 12 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([13.775 17.22 16.22 15.22 14.22 12.775 13.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Byte" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "17309" Ports [1, 1] Position [1625, 89, 1655, 101] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 30 30 0 0 ],[0 0 12 12 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([13.775 17.22 16.22 15.22 14.22 12.775 13.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Byte Valid" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "17310" Ports [1, 1] Position [1625, 189, 1655, 201] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 30 30 0 0 ],[0 0 12 12 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([13.775 17.22 16.22 15.22 14.22 12.775 13.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Valid Header" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "17311" Ports [1, 1] Position [1625, 214, 1655, 226] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 30 30 0 0 ],[0 0 12 12 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([13.775 17.22 16.22 15.22 14.22 12.775 13.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Invalid Header" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "17312" Ports [1, 1] Position [1625, 114, 1655, 126] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 30 30 0 0 ],[0 0 12 12 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([13.775 17.22 16.22 15.22 14.22 12.775 13.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Length (bits)" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "17313" Ports [1, 1] Position [1625, 139, 1655, 151] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 30 30 0 0 ],[0 0 12 12 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([13.775 17.22 16.22 15.22 14.22 12.775 13.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "CRC Error" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Inverter1" SID "17314" Ports [1, 1] Position [1040, 717, 1070, 733] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "30,16,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 16 16 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 16 16 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[1" "0.22 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[8.22 8.22 " "10.22 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[6.22 6.22 8.22 8.22 6.22 ],[" "1 1 1 ]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('bla" "ck');disp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Length\nCheck" SID "17315" Ports [2, 1] Position [750, 485, 835, 520] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Length\nCheck" Location [719, 549, 929, 642] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Rate" SID "17833" Position [170, 403, 200, 417] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "Len" SID "17316" Position [230, 288, 260, 302] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "17317" Ports [0, 1] Position [155, 439, 200, 461] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "8*14/2 %was 8*14 for 1Mb-only PHY" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "8" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "45,22,0,1,white,blue,0,069f21a3,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 22 22 0 ]);\npatch([15.325 19.66 22.66 25.66 28.66 22.66 18.325 15.325 ],[14.33 14" ".33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([18.325 22.66 19.66 15.325 18.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([15.325 19.66 22.66 18.325 15.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 " "1 1 ]);\npatch([18.325 28.66 25.66 22.66 19.66 15.325 18.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port" "_label('output',1,'56');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant2" SID "17835" Ports [0, 1] Position [155, 419, 200, 441] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "8*14" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "8" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "45,22,0,1,white,blue,0,82fd0260,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 22 22 0 ]);\npatch([15.325 19.66 22.66 25.66 28.66 22.66 18.325 15.325 ],[14.33 14" ".33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([18.325 22.66 19.66 15.325 18.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([15.325 19.66 22.66 18.325 15.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 " "1 1 ]);\npatch([18.325 28.66 25.66 22.66 19.66 15.325 18.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port" "_label('output',1,'112');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant5" SID "17318" Ports [0, 1] Position [315, 304, 360, 326] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "8*1500" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "14" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "45,22,0,1,white,blue,0,2f749938,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 22 22 0 ]);\npatch([15.325 19.66 22.66 25.66 28.66 22.66 18.325 15.325 ],[14.33 14" ".33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([18.325 22.66 19.66 15.325 18.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([15.325 19.66 22.66 18.325 15.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 " "1 1 ]);\npatch([18.325 28.66 25.66 22.66 19.66 15.325 18.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port" "_label('output',1,'12000');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical9" SID "17319" Ports [2, 1] Position [505, 298, 530, 327] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "25,29,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 29 29 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 29 29 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 17.33 " "20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33 17.33 1" "4.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1 1 1 ]);\n" "patch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('or'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux" SID "17834" Ports [3, 1] Position [290, 398, 315, 462] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "25,64,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 9.14286 54.8571 64 0 ],[0." "77 0.82 0.91 ]);\nplot([0 25 25 0 0 ],[0 9.14286 54.8571 64 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325" " 5.325 ],[35.33 35.33 38.33 35.33 38.33 38.33 38.33 35.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[32." "33 32.33 35.33 35.33 32.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[29.33 29.33 32.33 32.3" "3 29.33 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[26.33 26.33 29.33 26.33 29.33 29.33 26.33" " ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncol" "or('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('i" "nput',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational1" SID "17320" Ports [2, 1] Position [385, 365, 420, 405] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "ab" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,40,2,1,white,blue,0,b5131c97,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 40 40 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 40 40 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[25.55 25.55 30." "55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[20.55 20.55 25.55 25.55 20." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i" "nput',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa > b','texmod" "e','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Invalid" SID "17322" Position [615, 308, 645, 322] IconDisplay "Port number" } Line { SrcBlock "Constant5" SrcPort 1 DstBlock "Relational5" DstPort 2 } Line { SrcBlock "Len" SrcPort 1 Points [35, 0] Branch { DstBlock "Relational5" DstPort 1 } Branch { Points [0, 80] DstBlock "Relational1" DstPort 1 } } Line { SrcBlock "Relational5" SrcPort 1 DstBlock "Logical9" DstPort 1 } Line { SrcBlock "Mux" SrcPort 1 Points [40, 0; 0, -35] DstBlock "Relational1" DstPort 2 } Line { SrcBlock "Relational1" SrcPort 1 Points [45, 0; 0, -65] DstBlock "Logical9" DstPort 2 } Line { SrcBlock "Logical9" SrcPort 1 DstBlock "Invalid" DstPort 1 } Line { SrcBlock "Rate" SrcPort 1 DstBlock "Mux" DstPort 1 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Mux" DstPort 3 } Line { SrcBlock "Constant2" SrcPort 1 DstBlock "Mux" DstPort 2 } Annotation { Name "Require [14,1500] bytes - reject anything else\nas invalid. Reduces wasted time attempting\ndecoding of " "bogus LENGTH pkts." Position [362, 233] } } } Block { BlockType Reference Name "Logical" SID "17323" Ports [2, 1] Position [420, 448, 445, 477] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "25,29,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 29 29 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 29 29 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17" ".33 17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 " "17.33 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\nc" "olor('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "17324" Ports [2, 1] Position [1195, 858, 1220, 887] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "25,29,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 29 29 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 29 29 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17" ".33 17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 " "17.33 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\nc" "olor('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical10" SID "17325" Ports [2, 1] Position [1195, 786, 1220, 824] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "25,38,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 38 38 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 38 38 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[22" ".33 22.33 25.33 22.33 25.33 25.33 25.33 22.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[19.33 19.33 " "22.33 22.33 19.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[16.33 16.33 19.33 19.33 16.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 13.33 16.33 16.33 13.33 ]," "[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n" "\ncolor('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "17326" Ports [2, 1] Position [420, 298, 445, 327] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "25,29,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 29 29 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 29 29 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17" ".33 17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 " "17.33 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\nc" "olor('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical3" SID "17327" Ports [2, 1] Position [420, 523, 445, 552] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "25,29,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 29 29 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 29 29 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17" ".33 17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 " "17.33 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\nc" "olor('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical6" SID "17329" Ports [3, 1] Position [965, 711, 995, 739] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "30,28,3,1,white,blue,0,a2abe52d,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 " "18.44 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 1" "8.44 14.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\ncolor('black'" ");disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical7" SID "17330" Ports [2, 1] Position [420, 683, 445, 712] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "25,29,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 29 29 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 29 29 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17" ".33 17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 " "17.33 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\nc" "olor('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical8" SID "17331" Ports [2, 1] Position [420, 743, 445, 772] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "25,29,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 29 29 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 29 29 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17" ".33 17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 " "17.33 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\nc" "olor('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical9" SID "17332" Ports [2, 1] Position [880, 718, 905, 747] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "25,29,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 29 29 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 29 29 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17" ".33 17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 " "17.33 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\nc" "olor('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux" SID "17409" Ports [3, 1] Position [1100, 391, 1130, 499] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "30,108,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 15.4286 92.5714 108" " 0 ],[0.77 0.82 0.91 ]);\nplot([0 30 30 0 0 ],[0 15.4286 92.5714 108 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 " "15.88 10.1 6.1 ],[58.44 58.44 62.44 58.44 62.44 62.44 62.44 58.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10." "1 ],[54.44 54.44 58.44 58.44 54.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[50.44 50.44 54." "44 54.44 50.44 ],[1 1 1 ]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[46.44 46.44 50.44 46.44 50.44 50.4" "4 46.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon te" "xt');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');" "port_label('input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" } Block { BlockType SubSystem Name "RATE Check" SID "17333" Ports [1, 2] Position [625, 231, 695, 364] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "RATE Check" Location [787, 335, 992, 428] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "B0" SID "17334" Position [400, 358, 430, 372] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Reference Name "Constant3" SID "17338" Ports [0, 1] Position [485, 374, 510, 396] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "hex2dec('0A')" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "8" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,22,0,1,white,blue,0,46ffeebb,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 22 22 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[14.33 14.33 " "17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[11.33 11.33 14.33 14.33 1" "1.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 1 1 ]);\npat" "ch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 0.973 ]);\nfprin" "tf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output'," "1,'10');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant4" SID "17339" Ports [0, 1] Position [485, 509, 510, 531] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "hex2dec('14')" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "8" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,22,0,1,white,blue,0,a4afb800,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 22 22 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[14.33 14.33 " "17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[11.33 11.33 14.33 14.33 1" "1.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 1 1 ]);\npat" "ch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 0.973 ]);\nfprin" "tf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output'," "1,'20');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical3" SID "17342" Ports [2, 1] Position [765, 347, 800, 458] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "NOR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,111,2,1,white,blue,0,affe8783,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 111 111 0 ],[0.77 0.82 0" ".91 ]);\nplot([0 35 35 0 0 ],[0 0 111 111 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[60.55 60.55" " 65.55 60.55 65.55 65.55 65.55 60.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[55.55 55.55 60.55 60.55" " 55.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[50.55 50.55 55.55 55.55 50.55 ],[1 1 1 ]);" "\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[45.55 45.55 50.55 45.55 50.55 50.55 45.55 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');dis" "p('nor');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational3" SID "17344" Ports [2, 1] Position [600, 355, 635, 395] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,40,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 40 40 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 40 40 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[25.55 25.55 30." "55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[20.55 20.55 25.55 25.55 20." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i" "nput',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa = b','texmod" "e','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational5" SID "17346" Ports [2, 1] Position [600, 490, 635, 530] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,40,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 40 40 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 40 40 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[25.55 25.55 30." "55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[20.55 20.55 25.55 25.55 20." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i" "nput',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa = b','texmod" "e','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "2Mb_Rate" SID "17347" Position [890, 503, 920, 517] IconDisplay "Port number" } Block { BlockType Outport Name "Invalid" SID "17348" Position [890, 398, 920, 412] Port "2" IconDisplay "Port number" } Line { SrcBlock "Constant3" SrcPort 1 DstBlock "Relational3" DstPort 2 } Line { SrcBlock "B0" SrcPort 1 Points [25, 0] Branch { DstBlock "Relational3" DstPort 1 } Branch { Points [0, 135] DstBlock "Relational5" DstPort 1 } } Line { SrcBlock "Constant4" SrcPort 1 DstBlock "Relational5" DstPort 2 } Line { SrcBlock "Relational5" SrcPort 1 Points [80, 0] Branch { DstBlock "2Mb_Rate" DstPort 1 } Branch { Points [0, -80] DstBlock "Logical3" DstPort 2 } } Line { SrcBlock "Relational3" SrcPort 1 DstBlock "Logical3" DstPort 1 } Line { SrcBlock "Logical3" SrcPort 1 DstBlock "Invalid" DstPort 1 } Annotation { Name "RATE = 0x0A for 1Mb\n0x14 for 2Mb" Position [578, 438] HorizontalAlignment "right" } } } Block { BlockType Reference Name "Relational1" SID "17349" Ports [2, 1] Position [335, 450, 370, 490] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,40,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 40 40 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 40 40 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[25.55" " 25.55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[20.55 20.55 25" ".55 25.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[15.55 15.55 20.55 20.55 15.55 " "],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor(" "'black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('outp" "ut',1,'\\bfa = b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational2" SID "17350" Ports [2, 1] Position [335, 300, 370, 340] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,40,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 40 40 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 40 40 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[25.55" " 25.55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[20.55 20.55 25" ".55 25.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[15.55 15.55 20.55 20.55 15.55 " "],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor(" "'black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('outp" "ut',1,'\\bfa = b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational4" SID "17352" Ports [2, 1] Position [335, 525, 370, 565] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,40,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 40 40 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 40 40 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[25.55" " 25.55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[20.55 20.55 25" ".55 25.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[15.55 15.55 20.55 20.55 15.55 " "],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor(" "'black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('outp" "ut',1,'\\bfa = b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational6" SID "17353" Ports [2, 1] Position [335, 685, 370, 725] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,40,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 40 40 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 40 40 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[25.55" " 25.55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[20.55 20.55 25" ".55 25.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[15.55 15.55 20.55 20.55 15.55 " "],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor(" "'black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('outp" "ut',1,'\\bfa = b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational7" SID "17354" Ports [2, 1] Position [335, 745, 370, 785] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,40,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 40 40 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 40 40 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[25.55" " 25.55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[20.55 20.55 25" ".55 25.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[15.55 15.55 20.55 20.55 15.55 " "],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor(" "'black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('outp" "ut',1,'\\bfa = b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational8" SID "17355" Ports [2, 1] Position [760, 705, 795, 745] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a!=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,40,2,1,white,blue,0,850de6e7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 40 40 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 40 40 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[25.55" " 25.55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[20.55 20.55 25" ".55 25.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[15.55 15.55 20.55 20.55 15.55 " "],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor(" "'black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('outp" "ut',1,'\\bfa \\neq b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Shift" SID "17356" Ports [1, 1] Position [1000, 430, 1040, 460] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Shift" SourceType "Xilinx Binary Shift Operator Block" infoedit "Hardware notes: In hardware this block costs nothing if full output precision is used." shift_dir "Right" shift_bits "3" en off latency "0" precision "Full" arith_type "Signed (2's comp)" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "shift" sg_icon_stat "40,30,1,1,white,blue,0,42eb502d,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 30 30 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 30 30 0 ]);\npatch([11.1 16.88 20.88 24.88 28.88 20.88 15.1 11.1 ],[19.4" "4 19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([15.1 20.88 16.88 11.1 15.1 ],[15.44 15.44 19.4" "4 19.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([11.1 16.88 20.88 15.1 11.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1" " 1 1 ]);\npatch([15.1 28.88 24.88 20.88 16.88 11.1 15.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946" " 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('blac" "k');disp('\\bf{X >> 3}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Shift1" SID "17411" Ports [1, 1] Position [1000, 465, 1040, 495] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Shift" SourceType "Xilinx Binary Shift Operator Block" infoedit "Hardware notes: In hardware this block costs nothing if full output precision is used." shift_dir "Right" shift_bits "2" en off latency "0" precision "Full" arith_type "Signed (2's comp)" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "shift" sg_icon_stat "40,30,1,1,white,blue,0,b3ac20f4,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 30 30 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 30 30 0 ]);\npatch([11.1 16.88 20.88 24.88 28.88 20.88 15.1 11.1 ],[19.4" "4 19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([15.1 20.88 16.88 11.1 15.1 ],[15.44 15.44 19.4" "4 19.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([11.1 16.88 20.88 15.1 11.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1" " 1 1 ]);\npatch([15.1 28.88 24.88 20.88 16.88 11.1 15.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946" " 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('blac" "k');disp('\\bf{X >> 2}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "LENGTH" SID "17357" Position [1360, 453, 1390, 467] ZOrder -9 IconDisplay "Port number" } Block { BlockType Outport Name "Valid Header" SID "17358" Position [1370, 798, 1400, 812] ZOrder -9 Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "Error" SID "17359" Position [1370, 868, 1400, 882] ZOrder -9 Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "2Mb_Payload" SID "17360" Position [1500, 278, 1530, 292] Port "4" IconDisplay "Port number" } Line { SrcBlock "Constant2" SrcPort 1 DstBlock "Relational2" DstPort 2 } Line { SrcBlock "Relational1" SrcPort 1 DstBlock "Logical" DstPort 2 } Line { SrcBlock "Relational2" SrcPort 1 DstBlock "Logical2" DstPort 2 } Line { SrcBlock "Logical" SrcPort 1 DstBlock "DOUT2" DstPort 3 } Line { SrcBlock "Logical2" SrcPort 1 DstBlock "DOUT" DstPort 3 } Line { SrcBlock "Byte" SrcPort 1 Points [265, 0] Branch { Points [0, 20] Branch { DstBlock "DOUT" DstPort 1 } Branch { Points [0, 150] Branch { DstBlock "DOUT2" DstPort 1 } Branch { Points [0, 75] Branch { DstBlock "DOUT3" DstPort 1 } Branch { Points [0, 160] Branch { Points [0, 60] DstBlock "DOUT4" DstPort 1 } Branch { DstBlock "DOUT5" DstPort 1 } } } } } Branch { Points [0, -195] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "From3" SrcPort 1 Points [70, 0; 0, 65] Branch { DstBlock "DOUT" DstPort 2 } Branch { Points [0, 150] Branch { DstBlock "DOUT2" DstPort 2 } Branch { Points [0, 75] Branch { DstBlock "DOUT3" DstPort 2 } Branch { Points [0, 160] Branch { DstBlock "DOUT4" DstPort 2 } Branch { DstBlock "DOUT5" DstPort 2 } } } } } Line { SrcBlock "Byte Valid" SrcPort 1 Points [190, 0] Branch { Points [0, 15] Branch { DstBlock "Logical2" DstPort 1 } Branch { Points [0, 150] Branch { DstBlock "Logical" DstPort 1 } Branch { Points [0, 75] Branch { DstBlock "Logical3" DstPort 1 } Branch { Points [0, 160] Branch { Points [0, 60] DstBlock "Logical8" DstPort 1 } Branch { DstBlock "Logical7" DstPort 1 } } } } } Branch { Points [0, -195] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Relational1" DstPort 2 } Line { SrcBlock "Byte Ind" SrcPort 1 Points [110, 0] Branch { DstBlock "Relational1" DstPort 1 } Branch { Points [0, 75] Branch { DstBlock "Relational4" DstPort 1 } Branch { Points [0, 160] Branch { Points [0, 60] DstBlock "Relational7" DstPort 1 } Branch { DstBlock "Relational6" DstPort 1 } } } Branch { Points [0, -150] DstBlock "Relational2" DstPort 1 } } Line { SrcBlock "DOUT" SrcPort 1 DstBlock "RATE Check" DstPort 1 } Line { SrcBlock "Relational4" SrcPort 1 DstBlock "Logical3" DstPort 2 } Line { SrcBlock "Constant4" SrcPort 1 DstBlock "Relational4" DstPort 2 } Line { SrcBlock "Logical3" SrcPort 1 DstBlock "DOUT3" DstPort 3 } Line { SrcBlock "DOUT2" SrcPort 1 Points [40, 0; 0, 75] DstBlock "Concat" DstPort 2 } Line { SrcBlock "DOUT3" SrcPort 1 Points [10, 0; 0, -30] DstBlock "Concat" DstPort 1 } Line { SrcBlock "Concat" SrcPort 1 Points [5, 0] Branch { Points [0, 90] DstBlock "Gateway Out" DstPort 1 } Branch { Points [0, 0] Branch { Points [0, -65; 270, 0] Branch { DstBlock "Shift" DstPort 1 } Branch { Points [0, -325] DstBlock "Gateway Out6" DstPort 1 } Branch { Points [0, 35] DstBlock "Shift1" DstPort 1 } } Branch { Labels [0, 0] DstBlock "Length\nCheck" DstPort 2 } } } Line { SrcBlock "Length\nCheck" SrcPort 1 Points [85, 0; 0, 220] DstBlock "Logical6" DstPort 2 } Line { SrcBlock "RATE Check" SrcPort 2 Points [235, 0; 0, 385] DstBlock "Logical6" DstPort 1 } Line { SrcBlock "Gateway Out" SrcPort 1 DstBlock "Display" DstPort 1 } Line { SrcBlock "Constant6" SrcPort 1 DstBlock "Relational6" DstPort 2 } Line { SrcBlock "Logical8" SrcPort 1 Points [5, 0] Branch { DstBlock "DOUT4" DstPort 3 } Branch { Points [0, 55] DstBlock "Delay1" DstPort 1 } } Line { SrcBlock "Relational6" SrcPort 1 DstBlock "Logical7" DstPort 2 } Line { SrcBlock "Relational7" SrcPort 1 DstBlock "Logical8" DstPort 2 } Line { SrcBlock "Constant7" SrcPort 1 DstBlock "Relational7" DstPort 2 } Line { SrcBlock "DOUT4" SrcPort 1 Points [20, 0; 0, -45] DstBlock "Concat1" DstPort 1 } Line { SrcBlock "DOUT5" SrcPort 1 Points [0, 45] DstBlock "Concat1" DstPort 2 } Line { SrcBlock "Concat1" SrcPort 1 DstBlock "Relational8" DstPort 1 } Line { SrcBlock "CRC Calc" SrcPort 1 Points [385, 0; 0, -135] DstBlock "Relational8" DstPort 2 } Line { SrcBlock "Relational8" SrcPort 1 Points [35, 0] Branch { DstBlock "Logical9" DstPort 1 } Branch { Points [0, -580] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "Delay1" SrcPort 1 Points [290, 0] Branch { Points [0, -75] DstBlock "Logical9" DstPort 2 } Branch { Points [0, 65] DstBlock "Logical1" DstPort 2 } Branch { DstBlock "Logical10" DstPort 2 } } Line { SrcBlock "Logical9" SrcPort 1 DstBlock "Logical6" DstPort 3 } Line { SrcBlock "Logical7" SrcPort 1 DstBlock "DOUT5" DstPort 3 } Line { SrcBlock "Constant9" SrcPort 1 DstBlock "AddSub" DstPort 2 } Line { SrcBlock "Logical6" SrcPort 1 Points [15, 0] Branch { DstBlock "Inverter1" DstPort 1 } Branch { Points [0, 140] DstBlock "Logical1" DstPort 1 } } Line { SrcBlock "Inverter1" SrcPort 1 Points [25, 0; 0, 70] DstBlock "Logical10" DstPort 1 } Line { SrcBlock "Logical10" SrcPort 1 DstBlock "DOUT1" DstPort 1 } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "DOUT6" DstPort 1 } Line { SrcBlock "Shift" SrcPort 1 DstBlock "Mux" DstPort 2 } Line { Name "Byte" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 DstBlock "DSSS SIGNAL Decode" DstPort 1 } Line { Name "Byte Valid" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 DstBlock "DSSS SIGNAL Decode" DstPort 2 } Line { Name "Valid Header" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 DstBlock "DSSS SIGNAL Decode" DstPort 6 } Line { Name "Invalid Header" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 DstBlock "DSSS SIGNAL Decode" DstPort 7 } Line { Name "Length (bits)" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 DstBlock "DSSS SIGNAL Decode" DstPort 3 } Line { Name "CRC Error" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 DstBlock "DSSS SIGNAL Decode" DstPort 4 } Line { SrcBlock "DOUT1" SrcPort 1 Points [30, 0] Branch { DstBlock "Valid Header" DstPort 1 } Branch { Points [0, -445] Branch { Points [0, -165] DstBlock "Gateway Out4" DstPort 1 } Branch { Points [-70, 0] DstBlock "DOUT7" DstPort 3 } } } Line { SrcBlock "DOUT6" SrcPort 1 Points [40, 0] Branch { DstBlock "Error" DstPort 1 } Branch { Points [0, -655] DstBlock "Gateway Out5" DstPort 1 } } Line { SrcBlock "RATE Check" SrcPort 1 Points [20, 0] Branch { Points [335, 0] Branch { DstBlock "DOUT7" DstPort 1 } Branch { Points [0, 145] DstBlock "Mux" DstPort 1 } } Branch { Points [0, 230] DstBlock "Length\nCheck" DstPort 1 } } Line { SrcBlock "From1" SrcPort 1 DstBlock "DOUT7" DstPort 2 } Line { SrcBlock "DOUT7" SrcPort 1 DstBlock "2Mb_Payload" DstPort 1 } Line { SrcBlock "AddSub" SrcPort 1 DstBlock "LENGTH" DstPort 1 } Line { SrcBlock "Shift1" SrcPort 1 DstBlock "Mux" DstPort 3 } Line { SrcBlock "Mux" SrcPort 1 DstBlock "AddSub" DstPort 1 } Annotation { Name "LENGTH*8 + 6 - 1:\nLength in usec = Number of bits (BSPK) or half number of bits (QPSK)\n/8 (1Mb) " "or /4 (2Mb): Convert to bytes\n+6: Add SIGNAL, SERVICE and CRC bytes\n-1: Downstream logic requires zero-indexe" "d length\nto compare vs. byte index" Position [984, 558] HorizontalAlignment "left" } } } Block { BlockType Reference Name "dbg_DSSS_RX_ACTIVE" SID "17361" Ports [1, 1] Position [1275, 328, 1310, 342] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,14,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 14 14 0 ],[0.95 0.93 0.65" " ]);\nplot([0 35 35 0 0 ],[0 0 14 14 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[9.22 9.22 11." "22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0." "985 0.979 0.895 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([14.55 21" ".44 19.44 17.44 15.44 12.55 14.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.985 0.979 0.895 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ');\ncolor" "('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "DSSS data" SID "17362" Position [1015, 198, 1045, 212] IconDisplay "Port number" } Line { SrcBlock "Demod" SrcPort 1 Points [70, 0] Branch { Points [0, 125] DstBlock "SIGNAL Dec" DstPort 1 } Branch { DstBlock "Register6" DstPort 1 } } Line { SrcBlock "Demod" SrcPort 2 Points [65, 0] Branch { Points [0, 130] DstBlock "SIGNAL Dec" DstPort 2 } Branch { DstBlock "Register7" DstPort 1 } } Line { SrcBlock "Demod" SrcPort 3 Points [60, 0] Branch { Points [0, 15] Branch { Points [0, 120] DstBlock "SIGNAL Dec" DstPort 3 } Branch { DstBlock "Relational5" DstPort 1 } } Branch { DstBlock "Register8" DstPort 1 } } Line { SrcBlock "Demod" SrcPort 4 Points [55, 0; 0, 140] DstBlock "SIGNAL Dec" DstPort 4 } Line { Name "byte_index" Labels [0, 0] SrcBlock "Register2" SrcPort 1 DstBlock "Bus\nCreator" DstPort 3 } Line { SrcBlock "SIGNAL Dec" SrcPort 1 Points [25, 0] Branch { Points [0, -40] DstBlock "Relational5" DstPort 2 } Branch { DstBlock "Goto2" DstPort 1 } } Line { SrcBlock "Relational5" SrcPort 1 DstBlock "Register9" DstPort 1 } Line { Name "byte_valid" Labels [0, 0] SrcBlock "Register1" SrcPort 1 DstBlock "Bus\nCreator" DstPort 2 } Line { Name "byte" Labels [0, 0] SrcBlock "Register" SrcPort 1 DstBlock "Bus\nCreator" DstPort 1 } Line { SrcBlock "Bus\nCreator" SrcPort 1 DstBlock "DSSS data" DstPort 1 } Line { SrcBlock "SIGNAL Dec" SrcPort 2 Points [65, 0] Branch { DstBlock "Goto3" DstPort 1 } Branch { Points [0, 145] DstBlock "S-R Latch1" DstPort 1 } } Line { SrcBlock "S-R Latch1" SrcPort 1 Points [10, 0] Branch { Points [0, 50] DstBlock "Logical2" DstPort 1 } Branch { Points [50, 0] Branch { DstBlock "Goto4" DstPort 1 } Branch { Points [0, -50] DstBlock "Register5" DstPort 1 } } } Line { SrcBlock "Logical2" SrcPort 1 DstBlock "Goto5" DstPort 1 } Line { SrcBlock "Register3" SrcPort 1 Points [0, -95] DstBlock "dbg_DSSS_RX_ACTIVE" DstPort 1 } Line { SrcBlock "Register4" SrcPort 1 DstBlock "Register3" DstPort 1 } Line { SrcBlock "Register5" SrcPort 1 DstBlock "Register4" DstPort 1 } Line { SrcBlock "From4" SrcPort 1 DstBlock "Logical4" DstPort 3 } Line { SrcBlock "From3" SrcPort 1 DstBlock "Logical4" DstPort 4 } Line { SrcBlock "From6" SrcPort 1 DstBlock "Inverter1" DstPort 1 } Line { SrcBlock "From8" SrcPort 1 DstBlock "Logical4" DstPort 5 } Line { SrcBlock "Logical7" SrcPort 1 Points [25, 0; 0, 20] DstBlock "Logical4" DstPort 2 } Line { Labels [0, 0] SrcBlock "Reset Gen" SrcPort 1 DstBlock "Goto1" DstPort 1 } Line { SrcBlock "Logical4" SrcPort 1 Points [15, 0] Branch { DstBlock "Reset Gen" DstPort 1 } Branch { Points [0, -70] Branch { Points [0, -55] DstBlock "S-R Latch1" DstPort 2 } Branch { DstBlock "Logical2" DstPort 2 } } } Line { SrcBlock "Pkt Det" SrcPort 1 DstBlock "Demod" DstPort 1 } Line { SrcBlock "From7" SrcPort 1 DstBlock "Logical4" DstPort 6 } Line { Name "last_byte" Labels [0, 0] SrcBlock "Register9" SrcPort 1 DstBlock "Bus\nCreator" DstPort 4 } Line { SrcBlock "Register6" SrcPort 1 DstBlock "Register" DstPort 1 } Line { SrcBlock "Register7" SrcPort 1 DstBlock "Register1" DstPort 1 } Line { SrcBlock "Register8" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "SIGNAL Dec" SrcPort 3 Points [45, 0; 0, 215] DstBlock "Logical4" DstPort 1 } Line { SrcBlock "SIGNAL Dec" SrcPort 4 Points [25, 0] Branch { Points [0, 30; -460, 0; 0, -170] DstBlock "Demod" DstPort 5 } Branch { DstBlock "Goto6" DstPort 1 } } Line { SrcBlock "I" SrcPort 1 DstBlock "Demod" DstPort 2 } Line { SrcBlock "Q" SrcPort 1 DstBlock "Demod" DstPort 3 } Line { SrcBlock "IQ Valid" SrcPort 1 DstBlock "Demod" DstPort 4 } Line { SrcBlock "From1" SrcPort 1 DstBlock "Inverter2" DstPort 1 } Line { SrcBlock "Inverter2" SrcPort 1 DstBlock "Logical7" DstPort 2 } Line { SrcBlock "Inverter1" SrcPort 1 DstBlock "Logical7" DstPort 1 } Annotation { Name "Wait for current Rx to finish before\nasserting DSSS reset when software\ndisables DSSS pipeline" Position [363, 513] } } } Block { BlockType SubSystem Name "Detect & Decode" SID "1593" Ports [5, 2] Position [905, 162, 1005, 238] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Detect & Decode" Location [2, 74, 2464, 1576] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "132" Block { BlockType Inport Name "Eq I" SID "1594" Position [135, 68, 165, 82] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "Eq Q" SID "1595" Position [135, 83, 165, 97] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "iq_valid" SID "1596" Position [175, 98, 205, 112] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "sc_ind" SID "1597" Position [215, 113, 245, 127] Port "4" IconDisplay "Port number" } Block { BlockType Inport Name "sym_ind" SID "1598" Position [255, 128, 285, 142] Port "5" IconDisplay "Port number" } Block { BlockType BusCreator Name "Bus\nCreator" SID "1599" Ports [4, 1] Position [1300, 62, 1305, 178] ZOrder -2 ShowName off DisplayOption "bar" } Block { BlockType SubSystem Name "De-Interleave" SID "8640" Ports [5, 3] Position [740, 63, 850, 147] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "De-Interleave" Location [-1678, 227, -2, 1187] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "LLR Valid" SID "8641" Position [455, 238, 485, 252] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "LLR Vec" SID "8644" Position [460, 563, 490, 577] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "Demod cfg" SID "8642" Position [360, 283, 390, 297] NamePlacement "alternate" Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "mod_sel" SID "8643" Position [455, 413, 485, 427] Port "4" IconDisplay "Port number" } Block { BlockType Inport Name "Reset" SID "8645" Position [455, 328, 485, 342] Port "5" IconDisplay "Port number" } Block { BlockType From Name "From5" SID "8646" Position [325, 462, 500, 478] ZOrder -9 ShowName off GotoTag "OFDM_RX_DATA_Code_Rate" TagVisibility "global" } Block { BlockType SubSystem Name "Mem Sel" SID "8647" Ports [2, 2] Position [955, 153, 1015, 202] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Mem Sel" Location [2, 70, 2469, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Reset" SID "8648" Position [750, 773, 780, 787] IconDisplay "Port number" } Block { BlockType Inport Name "En" SID "8649" Position [750, 728, 780, 742] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Inverter" SID "8650" Ports [1, 1] Position [1100, 711, 1130, 729] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "30,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 18 18 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[11.22 11.22" " 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[9.22 9.22 11.22 11.22 9" ".22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch" "([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfpr" "intf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical" SID "8651" Ports [2, 1] Position [850, 713, 885, 742] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,29,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 29 29 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 29 29 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[18.44 18.44 22.4" "4 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[14.44 14.44 18.44 18.44 14.44 ]," "[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\npatch([12.1" " 25.88 21.88 17.88 13.88 8.1 12.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('and');\nfprintf(" "'','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "8652" Ports [2, 1] Position [850, 747, 885, 778] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,31,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 31 31 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 31 31 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[19.44 19.44 23.4" "4 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[15.44 15.44 19.44 19.44 15.44 ]," "[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([12.1" " 25.88 21.88 17.88 13.88 8.1 12.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('and');\nfprintf(" "'','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "8653" Ports [2, 1] Position [925, 758, 960, 787] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,29,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 29 29 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 29 29 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[18.44 18.44 22.4" "4 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[14.44 14.44 18.44 18.44 14.44 ]," "[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\npatch([12.1" " 25.88 21.88 17.88 13.88 8.1 12.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('or');\nfprintf('" "','COMMENT: end icon text');" } Block { BlockType SubSystem Name "S-R Latch1" SID "8654" Ports [2, 1] Position [1000, 709, 1035, 796] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "S-R Latch1" Location [351, 366, 2001, 1172] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "8655" Position [140, 103, 170, 117] IconDisplay "Port number" } Block { BlockType Inport Name "R" SID "8656" Position [140, 88, 170, 102] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "8657" Ports [0, 1] Position [195, 71, 210, 89] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "15,18,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11.22 " "13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 9.22 " "],[0.931 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([4.55 " "11.44 9.44 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "8658" Ports [1, 1] Position [210, 86, 235, 104] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('outpu" "t',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "8659" Ports [1, 1] Position [210, 101, 235, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('outpu" "t',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "8660" Ports [3, 1] Position [255, 71, 300, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "8661" Position [325, 88, 355, 102] IconDisplay "Port number" } Line { SrcBlock "Convert2" SrcPort 1 DstBlock "Register2" DstPort 3 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "S" SrcPort 1 DstBlock "Convert2" DstPort 1 } } } Block { BlockType Outport Name "Rd" SID "8662" Position [1190, 748, 1220, 762] IconDisplay "Port number" } Block { BlockType Outport Name "Wr" SID "8663" Position [1190, 713, 1220, 727] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Line { SrcBlock "S-R Latch1" SrcPort 1 Points [15, 0] Branch { Points [0, -35] DstBlock "Inverter" DstPort 1 } Branch { DstBlock "Rd" DstPort 1 } Branch { Points [0, 60; -240, 0; 0, -45] DstBlock "Logical1" DstPort 2 } } Line { SrcBlock "Logical2" SrcPort 1 DstBlock "S-R Latch1" DstPort 2 } Line { SrcBlock "Logical" SrcPort 1 DstBlock "S-R Latch1" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 Points [20, 0] Branch { DstBlock "Wr" DstPort 1 } Branch { Points [0, -35; -340, 0; 0, 35] DstBlock "Logical" DstPort 1 } } Line { SrcBlock "En" SrcPort 1 Points [30, 0] Branch { DstBlock "Logical" DstPort 2 } Branch { Points [0, 20] DstBlock "Logical1" DstPort 1 } } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Logical2" DstPort 1 } Line { SrcBlock "Reset" SrcPort 1 DstBlock "Logical2" DstPort 2 } Annotation { Name "Simple circuit to toggle between 0 and 1 each time the En signal asserts." Position [966, 845] } } } Block { BlockType SubSystem Name "RAMs" SID "8664" Ports [10, 3] Position [1130, 133, 1235, 557] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "RAMs" Location [-1678, 227, -2, 1187] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Rd Sel" SID "8665" Position [985, 263, 1015, 277] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "Wr Sel" SID "8666" Position [400, 222, 430, 238] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "Wr Addr A" SID "8667" Position [400, 368, 430, 382] NamePlacement "alternate" Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "Wr En" SID "8668" Position [400, 258, 430, 272] NamePlacement "alternate" Port "4" IconDisplay "Port number" } Block { BlockType Inport Name "Rd Addr A" SID "8669" Position [400, 293, 430, 307] NamePlacement "alternate" Port "5" IconDisplay "Port number" } Block { BlockType Inport Name "Rd Addr B" SID "8670" Position [400, 323, 430, 337] NamePlacement "alternate" Port "6" IconDisplay "Port number" } Block { BlockType Inport Name "Skip A" SID "8671" Position [985, 163, 1015, 177] NamePlacement "alternate" Port "7" IconDisplay "Port number" } Block { BlockType Inport Name "Skip B" SID "8672" Position [985, 183, 1015, 197] Port "8" IconDisplay "Port number" } Block { BlockType Inport Name "Vout" SID "8673" Position [815, 713, 845, 727] Port "9" IconDisplay "Port number" } Block { BlockType Inport Name "LLR Vec" SID "8674" Position [900, 298, 930, 312] NamePlacement "alternate" Port "10" IconDisplay "Port number" } Block { BlockType Reference Name "Concat" SID "8675" Ports [2, 1] Position [1420, 326, 1450, 364] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point at z" "ero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "30,38,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 38 38 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 38 38 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[23.44 23.44 27.4" "4 23.44 27.44 27.44 27.44 23.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[19.44 19.44 23.44 23.44 19.44 ]," "[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[15.44 15.44 19.44 19.44 15.44 ],[1 1 1 ]);\npatch([10.1" " 23.88 19.88 15.88 11.88 6.1 10.1 ],[11.44 11.44 15.44 11.44 15.44 15.44 11.44 ],[0.931 0.946 0.973 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'hi" "');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fontsize{20}\\}','texmode','on');\nfprin" "tf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Concat1" SID "8676" Ports [2, 1] Position [1435, 541, 1465, 579] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point at z" "ero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "30,38,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 38 38 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 38 38 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[23.44 23.44 27.4" "4 23.44 27.44 27.44 27.44 23.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[19.44 19.44 23.44 23.44 19.44 ]," "[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[15.44 15.44 19.44 19.44 15.44 ],[1 1 1 ]);\npatch([10.1" " 23.88 19.88 15.88 11.88 6.1 10.1 ],[11.44 11.44 15.44 11.44 15.44 15.44 11.44 ],[0.931 0.946 0.973 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'hi" "');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fontsize{20}\\}','texmode','on');\nfprin" "tf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Concat2" SID "9277" Ports [2, 1] Position [560, 435, 585, 475] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point at z" "ero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "25,40,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 40 40 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 40 40 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[23.33 23.33 " "26.33 23.33 26.33 26.33 26.33 23.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[20.33 20.33 23.33 23.33 2" "0.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[17.33 17.33 20.33 20.33 17.33 ],[1 1 1 ]);\n" "patch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33 14.33 17.33 17.33 14.33 ],[0.931 0.946 0.973 " "]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label" "('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fontsize{20}\\}','texmode'" ",'on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant" SID "8677" Ports [0, 1] Position [1000, 440, 1025, 460] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Boolean" arith_type "Boolean" n_bits "16" bin_pt "14" preci_type "Single" exp_width "8" frac_width "24" explicit_period on period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,20,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 20 20 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[12.22 12.22 14" ".22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[10.22 10.22 12.22 12.22 10.22" " ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatch([9." "55 16.44 14.44 12.44 10.44 7.55 9.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'0');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant1" SID "8678" Ports [0, 1] Position [1000, 605, 1025, 625] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Boolean" arith_type "Boolean" n_bits "16" bin_pt "14" preci_type "Single" exp_width "8" frac_width "24" explicit_period on period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,20,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 20 20 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[12.22 12.22 14" ".22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[10.22 10.22 12.22 12.22 10.22" " ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatch([9." "55 16.44 14.44 12.44 10.44 7.55 9.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'0');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant2" SID "8679" Ports [0, 1] Position [1000, 415, 1025, 435] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period on period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,20,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 20 20 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[12.22 12.22 14" ".22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[10.22 10.22 12.22 12.22 10.22" " ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatch([9." "55 16.44 14.44 12.44 10.44 7.55 9.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'0');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant3" SID "8680" Ports [0, 1] Position [1000, 580, 1025, 600] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period on period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,20,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 20 20 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[12.22 12.22 14" ".22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[10.22 10.22 12.22 12.22 10.22" " ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatch([9." "55 16.44 14.44 12.44 10.44 7.55 9.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'0');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant4" SID "8681" Ports [0, 1] Position [1425, 425, 1450, 445] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "4" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period on period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,20,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 20 20 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[12.22 12.22 14" ".22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[10.22 10.22 12.22 12.22 10.22" " ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatch([9." "55 16.44 14.44 12.44 10.44 7.55 9.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'0');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant5" SID "8682" Ports [0, 1] Position [1425, 640, 1450, 660] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "4" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period on period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,20,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 20 20 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[12.22 12.22 14" ".22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[10.22 10.22 12.22 12.22 10.22" " ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatch([9." "55 16.44 14.44 12.44 10.44 7.55 9.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'0');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant6" SID "9278" Ports [0, 1] Position [470, 455, 495, 475] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,20,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 20 20 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[12.22 12.22 14" ".22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[10.22 10.22 12.22 12.22 10.22" " ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatch([9." "55 16.44 14.44 12.44 10.44 7.55 9.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'0');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert" SID "9265" Ports [1, 1] Position [980, 296, 1015, 314] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "35,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 18 18 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[11.22 11.22" " 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[9.22 9.22 11.22 11.22 9" ".22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch" "([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output'" ",1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "De-Interleave RAM 0" SID "8683" Ports [6, 2] Position [1100, 332, 1220, 493] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Black Box" SourceType "Xilinx Black Box Block" infoedit " Incorporates black box HDL and simulation model into a System Generator design.

You must supp" "ly a Black Box with certain information about the HDL component you would like to bring into System Generator. Thi" "s information is provided through a Matlab function.

When \"Simulation mode\" is set to \"Inactive\", you w" "ill typically want to provide a separate simulation model by using a Simulation Multiplexer.
When \"Simulation " "mode\" is set to \"External co-simulator\", you must include a ModelSim block in the design." init_code "deinterleaver_ram" sim_method "ISE Simulator" verbose off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "blackbox2" sg_icon_stat "120,161,6,2,white,blue,0,643faf2d,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 120 120 0 0 ],[0 0 161 161 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 120 120 0 0 ],[0 0 161 161 0 ]);\npatch([22.175 46.74 63.74 80.74 97.74 63.74 39.175 22.175 ],[" "98.87 98.87 115.87 98.87 115.87 115.87 115.87 98.87 ],[1 1 1 ]);\npatch([39.175 63.74 46.74 22.175 39.175 ],[81.87" " 81.87 98.87 98.87 81.87 ],[0.931 0.946 0.973 ]);\npatch([22.175 46.74 63.74 39.175 22.175 ],[64.87 64.87 81.87 81" ".87 64.87 ],[1 1 1 ]);\npatch([39.175 97.74 80.74 63.74 46.74 22.175 39.175 ],[47.87 47.87 64.87 47.87 64.87 64.87" " 47.87 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\ncolor('black');port_label('input',1,'dina');\ncolor('black');port_label('input',2,'wea');\ncolor('black');port_" "label('input',3,'addra');\ncolor('black');port_label('input',4,'dinb');\ncolor('black');port_label('input',5,'web'" ");\ncolor('black');port_label('input',6,'addrb');\ncolor('black');port_label('output',1,'douta');\ncolor('black');" "port_label('output',2,'doutb');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "De-Interleave RAM 1" SID "8684" Ports [6, 2] Position [1100, 497, 1220, 658] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Black Box" SourceType "Xilinx Black Box Block" infoedit " Incorporates black box HDL and simulation model into a System Generator design.

You must supp" "ly a Black Box with certain information about the HDL component you would like to bring into System Generator. Thi" "s information is provided through a Matlab function.

When \"Simulation mode\" is set to \"Inactive\", you w" "ill typically want to provide a separate simulation model by using a Simulation Multiplexer.
When \"Simulation " "mode\" is set to \"External co-simulator\", you must include a ModelSim block in the design." init_code "deinterleaver_ram" sim_method "ISE Simulator" verbose off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "blackbox2" sg_icon_stat "120,161,6,2,white,blue,0,643faf2d,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 120 120 0 0 ],[0 0 161 161 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 120 120 0 0 ],[0 0 161 161 0 ]);\npatch([22.175 46.74 63.74 80.74 97.74 63.74 39.175 22.175 ],[" "98.87 98.87 115.87 98.87 115.87 115.87 115.87 98.87 ],[1 1 1 ]);\npatch([39.175 63.74 46.74 22.175 39.175 ],[81.87" " 81.87 98.87 98.87 81.87 ],[0.931 0.946 0.973 ]);\npatch([22.175 46.74 63.74 39.175 22.175 ],[64.87 64.87 81.87 81" ".87 64.87 ],[1 1 1 ]);\npatch([39.175 97.74 80.74 63.74 46.74 22.175 39.175 ],[47.87 47.87 64.87 47.87 64.87 64.87" " 47.87 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\ncolor('black');port_label('input',1,'dina');\ncolor('black');port_label('input',2,'wea');\ncolor('black');port_" "label('input',3,'addra');\ncolor('black');port_label('input',4,'dinb');\ncolor('black');port_label('input',5,'web'" ");\ncolor('black');port_label('input',6,'addrb');\ncolor('black');port_label('output',1,'douta');\ncolor('black');" "port_label('output',2,'doutb');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Scope Name "DeInt RAMs" SID "8685" Ports [9] Position [1680, 60, 1715, 270] ZOrder -3 Floating off Location [230, 117, 2357, 1548] Open off NumInputPorts "9" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" axes9 "%" } List { ListType ScopeGraphics FigureColor "[0.501960784313725 0.501960784313725 0.501960784313725]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[2 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "6000" YMin "0~0~0~0~0~0~0~-10~0" YMax "1~3~1~1~300~300~1~10~1" SaveName "ScopeData49" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType Reference Name "Delay1" SID "9295" Ports [1, 1] Position [1150, 159, 1175, 181] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "25,22,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 22 22 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[14.33 14.33 " "17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[11.33 11.33 14.33 14.33 1" "1.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 1 1 ]);\npat" "ch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 0.973 ]);\nfprin" "tf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay2" SID "9296" Ports [1, 1] Position [1150, 179, 1175, 201] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "25,22,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 22 22 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[14.33 14.33 " "17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[11.33 11.33 14.33 14.33 1" "1.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 1 1 ]);\npat" "ch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 0.973 ]);\nfprin" "tf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay3" SID "8686" Ports [1, 1] Position [1140, 702, 1175, 738] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,36,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 36 36 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 36 36 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[23.55 23.55 28." "55 23.55 28.55 28.55 28.55 23.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[18.55 18.55 23.55 23.55 18." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[13.55 13.55 18.55 18.55 13.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[8.55 8.55 13.55 8.55 13.55 13.55 8.55 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-1}'" ",'texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "8687" Position [635, 355, 710, 375] ZOrder -9 ShowName off GotoTag "WrEn" } Block { BlockType From Name "From1" SID "8688" Position [635, 375, 710, 395] ZOrder -9 ShowName off GotoTag "WrMemSel" } Block { BlockType From Name "From11" SID "8689" Position [1425, 155, 1500, 175] ZOrder -9 ShowName off GotoTag "RdAddrB" } Block { BlockType From Name "From15" SID "8691" Position [420, 435, 495, 455] ZOrder -9 ShowName off GotoTag "WrAddrA" } Block { BlockType From Name "From16" SID "8692" Position [635, 420, 710, 440] ZOrder -9 ShowName off GotoTag "RdAddrA" } Block { BlockType From Name "From17" SID "8693" Position [635, 580, 710, 600] ZOrder -9 ShowName off GotoTag "RdAddrA" } Block { BlockType From Name "From18" SID "8694" Position [635, 630, 710, 650] ZOrder -9 ShowName off GotoTag "RdAddrB" } Block { BlockType From Name "From19" SID "8695" Position [635, 465, 710, 485] ZOrder -9 ShowName off GotoTag "RdAddrB" } Block { BlockType From Name "From2" SID "8696" Position [1425, 55, 1500, 75] ZOrder -9 ShowName off GotoTag "WrEn" } Block { BlockType From Name "From3" SID "8697" Position [635, 520, 710, 540] ZOrder -9 ShowName off GotoTag "WrEn" } Block { BlockType From Name "From4" SID "8698" Position [635, 540, 710, 560] ZOrder -9 ShowName off GotoTag "WrMemSel" } Block { BlockType From Name "From5" SID "8699" Position [1425, 80, 1500, 100] ZOrder -9 ShowName off GotoTag "WrAddrA" } Block { BlockType From Name "From8" SID "8701" Position [1425, 105, 1500, 125] ZOrder -9 ShowName off GotoTag "WrMemSel" } Block { BlockType From Name "From9" SID "8702" Position [1425, 130, 1500, 150] ZOrder -9 ShowName off GotoTag "RdAddrA" } Block { BlockType Reference Name "Gateway Out1" SID "8703" Ports [1, 1] Position [1565, 84, 1600, 96] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Wr Addr A" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "8704" Ports [1, 1] Position [1565, 134, 1600, 146] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Rd Addr A" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "9419" Ports [1, 1] Position [1565, 209, 1600, 221] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Skip A" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "8706" Ports [1, 1] Position [1565, 109, 1600, 121] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Wr Sel" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "8707" Ports [1, 1] Position [1565, 59, 1600, 71] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Wr En" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "8708" Ports [1, 1] Position [1565, 159, 1600, 171] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Rd Addr B" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "8709" Ports [1, 1] Position [1565, 184, 1600, 196] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Rd Sel" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "9420" Ports [1, 1] Position [1565, 234, 1600, 246] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Skip B" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Goto Name "Goto3" SID "8710" Position [505, 220, 585, 240] ZOrder -10 ShowName off GotoTag "WrMemSel" TagVisibility "local" } Block { BlockType Goto Name "Goto4" SID "8711" Position [505, 365, 585, 385] ZOrder -10 ShowName off GotoTag "WrAddrA" TagVisibility "local" } Block { BlockType Goto Name "Goto6" SID "8712" Position [505, 290, 585, 310] ZOrder -10 ShowName off GotoTag "RdAddrA" TagVisibility "local" } Block { BlockType Goto Name "Goto7" SID "8713" Position [505, 320, 585, 340] ZOrder -10 ShowName off GotoTag "RdAddrB" TagVisibility "local" } Block { BlockType Goto Name "Goto8" SID "8714" Position [505, 255, 585, 275] ZOrder -10 ShowName off GotoTag "WrEn" TagVisibility "local" } Block { BlockType Reference Name "Inverter3" SID "8715" Ports [1, 1] Position [755, 376, 785, 394] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "30,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 18 18 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[11.22 11.22" " 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[9.22 9.22 11.22 11.22 9" ".22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch" "([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfpr" "intf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "8716" Ports [2, 1] Position [845, 357, 880, 393] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,36,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 36 36 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 36 36 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[23.55 23.55 28." "55 23.55 28.55 28.55 28.55 23.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[18.55 18.55 23.55 23.55 18." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[13.55 13.55 18.55 18.55 13.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[8.55 8.55 13.55 8.55 13.55 13.55 8.55 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('and')" ";\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical5" SID "8717" Ports [2, 1] Position [845, 522, 880, 558] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,36,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 36 36 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 36 36 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[23.55 23.55 28." "55 23.55 28.55 28.55 28.55 23.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[18.55 18.55 23.55 23.55 18." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[13.55 13.55 18.55 18.55 13.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[8.55 8.55 13.55 8.55 13.55 13.55 8.55 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('and')" ";\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux1" SID "8718" Ports [5, 1] Position [1490, 543, 1515, 697] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "4" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "25,154,5,1,white,blue,3,d6c79293,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 22 132 154 0 ],[0.77 0.82 " "0.91 ]);\nplot([0 25 25 0 0 ],[0 22 132 154 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[80.33 " "80.33 83.33 80.33 83.33 83.33 83.33 80.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[77.33 77.33 80.33 8" "0.33 77.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[74.33 74.33 77.33 77.33 74.33 ],[1 1 1" " ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[71.33 71.33 74.33 71.33 74.33 74.33 71.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port" "_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3,'d1');\n" "color('black');port_label('input',4,'d2');\ncolor('black');port_label('input',5,'d3');\n\ncolor('black');disp('\\b" "f{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux2" SID "8719" Ports [3, 1] Position [925, 391, 945, 469] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "20,78,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 11.1429 66.8571 78 0 ],[0." "77 0.82 0.91 ]);\nplot([0 20 20 0 0 ],[0 11.1429 66.8571 78 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5" ".55 ],[41.22 41.22 43.22 41.22 43.22 43.22 43.22 41.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[39.22 39." "22 41.22 41.22 39.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[37.22 37.22 39.22 39.22 37.22 ]" ",[1 1 1 ]);\npatch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[35.22 35.22 37.22 35.22 37.22 37.22 35.22 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3,'d1'" ");\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux3" SID "8720" Ports [5, 1] Position [1490, 328, 1515, 482] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "4" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "25,154,5,1,white,blue,3,d6c79293,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 22 132 154 0 ],[0.77 0.82 " "0.91 ]);\nplot([0 25 25 0 0 ],[0 22 132 154 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[80.33 " "80.33 83.33 80.33 83.33 83.33 83.33 80.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[77.33 77.33 80.33 8" "0.33 77.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[74.33 74.33 77.33 77.33 74.33 ],[1 1 1" " ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[71.33 71.33 74.33 71.33 74.33 74.33 71.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port" "_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3,'d1');\n" "color('black');port_label('input',4,'d2');\ncolor('black');port_label('input',5,'d3');\n\ncolor('black');disp('\\b" "f{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux5" SID "8721" Ports [3, 1] Position [925, 551, 945, 629] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "20,78,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 11.1429 66.8571 78 0 ],[0." "77 0.82 0.91 ]);\nplot([0 20 20 0 0 ],[0 11.1429 66.8571 78 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5" ".55 ],[41.22 41.22 43.22 41.22 43.22 43.22 43.22 41.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[39.22 39." "22 41.22 41.22 39.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[37.22 37.22 39.22 39.22 37.22 ]" ",[1 1 1 ]);\npatch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[35.22 35.22 37.22 35.22 37.22 37.22 35.22 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3,'d1'" ");\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Reinterpret" SID "8722" Ports [1, 1] Position [1275, 365, 1305, 385] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can change the signal between s" "igned and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.
Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsig" "ned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111" "000 in binary)." force_arith_type on arith_type "Signed (2's comp)" force_bin_pt off bin_pt "0" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "reinterpret" sg_icon_stat "30,20,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 20 20 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[12.22 12.22" " 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[10.22 10.22 12.22 12.22" " 10.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\n" "patch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('reinte" "rpret');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Reinterpret1" SID "8723" Ports [1, 1] Position [1275, 445, 1305, 465] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can change the signal between s" "igned and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.
Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsig" "ned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111" "000 in binary)." force_arith_type on arith_type "Signed (2's comp)" force_bin_pt off bin_pt "0" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "reinterpret" sg_icon_stat "30,20,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 20 20 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[12.22 12.22" " 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[10.22 10.22 12.22 12.22" " 10.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\n" "patch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('reinte" "rpret');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Reinterpret2" SID "8724" Ports [1, 1] Position [1275, 530, 1305, 550] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can change the signal between s" "igned and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.
Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsig" "ned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111" "000 in binary)." force_arith_type on arith_type "Signed (2's comp)" force_bin_pt off bin_pt "0" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "reinterpret" sg_icon_stat "30,20,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 20 20 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[12.22 12.22" " 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[10.22 10.22 12.22 12.22" " 10.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\n" "patch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('reinte" "rpret');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Reinterpret3" SID "8725" Ports [1, 1] Position [1275, 610, 1305, 630] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can change the signal between s" "igned and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.
Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsig" "ned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111" "000 in binary)." force_arith_type on arith_type "Signed (2's comp)" force_bin_pt off bin_pt "0" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "reinterpret" sg_icon_stat "30,20,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 20 20 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[12.22 12.22" " 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[10.22 10.22 12.22 12.22" " 10.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\n" "patch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('reinte" "rpret');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name " LLR A" SID "8726" Position [1625, 398, 1655, 412] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Outport Name " LLR B" SID "8727" Position [1625, 613, 1655, 627] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name " tvalid" SID "8728" Position [1625, 713, 1655, 727] Port "3" IconDisplay "Port number" } Line { SrcBlock "Mux3" SrcPort 1 DstBlock " LLR A" DstPort 1 } Line { SrcBlock "Delay3" SrcPort 1 DstBlock " tvalid" DstPort 1 } Line { SrcBlock "Vout" SrcPort 1 DstBlock "Delay3" DstPort 1 } Line { Labels [0, 0] SrcBlock "Logical2" SrcPort 1 Points [15, 0] Branch { Points [0, 30] DstBlock "Mux2" DstPort 1 } Branch { DstBlock "De-Interleave RAM 0" DstPort 2 } } Line { SrcBlock "From16" SrcPort 1 DstBlock "Mux2" DstPort 2 } Line { SrcBlock "Concat2" SrcPort 1 Points [35, 0] Branch { DstBlock "Mux2" DstPort 3 } Branch { Points [0, 160] DstBlock "Mux5" DstPort 3 } } Line { SrcBlock "Rd Addr A" SrcPort 1 DstBlock "Goto6" DstPort 1 } Line { SrcBlock "Rd Addr B" SrcPort 1 DstBlock "Goto7" DstPort 1 } Line { SrcBlock "Wr Addr A" SrcPort 1 DstBlock "Goto4" DstPort 1 } Line { SrcBlock "Wr En" SrcPort 1 DstBlock "Goto8" DstPort 1 } Line { SrcBlock "From" SrcPort 1 DstBlock "Logical2" DstPort 1 } Line { SrcBlock "From1" SrcPort 1 DstBlock "Inverter3" DstPort 1 } Line { SrcBlock "Inverter3" SrcPort 1 DstBlock "Logical2" DstPort 2 } Line { SrcBlock "Logical5" SrcPort 1 Points [15, 0] Branch { Points [0, 25] DstBlock "Mux5" DstPort 1 } Branch { DstBlock "De-Interleave RAM 1" DstPort 2 } } Line { SrcBlock "From4" SrcPort 1 DstBlock "Logical5" DstPort 2 } Line { SrcBlock "From3" SrcPort 1 DstBlock "Logical5" DstPort 1 } Line { SrcBlock "From17" SrcPort 1 DstBlock "Mux5" DstPort 2 } Line { SrcBlock "Wr Sel" SrcPort 1 DstBlock "Goto3" DstPort 1 } Line { Name "Wr En" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 DstBlock "DeInt RAMs" DstPort 1 } Line { Name "Wr Addr A" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 DstBlock "DeInt RAMs" DstPort 2 } Line { Name "Rd Addr A" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 DstBlock "DeInt RAMs" DstPort 4 } Line { Name "Wr Sel" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 DstBlock "DeInt RAMs" DstPort 3 } Line { Name "Rd Addr B" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 DstBlock "DeInt RAMs" DstPort 5 } Line { Name "Rd Sel" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 DstBlock "DeInt RAMs" DstPort 6 } Line { SrcBlock "From2" SrcPort 1 DstBlock "Gateway Out5" DstPort 1 } Line { SrcBlock "From5" SrcPort 1 DstBlock "Gateway Out1" DstPort 1 } Line { SrcBlock "From8" SrcPort 1 DstBlock "Gateway Out4" DstPort 1 } Line { SrcBlock "From9" SrcPort 1 DstBlock "Gateway Out2" DstPort 1 } Line { SrcBlock "From11" SrcPort 1 DstBlock "Gateway Out6" DstPort 1 } Line { SrcBlock "Convert" SrcPort 1 Points [55, 0; 0, 45] Branch { DstBlock "De-Interleave RAM 0" DstPort 1 } Branch { Points [0, 165] DstBlock "De-Interleave RAM 1" DstPort 1 } } Line { SrcBlock "Constant2" SrcPort 1 DstBlock "De-Interleave RAM 0" DstPort 4 } Line { SrcBlock "Constant" SrcPort 1 DstBlock "De-Interleave RAM 0" DstPort 5 } Line { SrcBlock "Mux5" SrcPort 1 Points [25, 0; 0, -25] DstBlock "De-Interleave RAM 1" DstPort 3 } Line { SrcBlock "Mux2" SrcPort 1 Points [15, 0; 0, -30] DstBlock "De-Interleave RAM 0" DstPort 3 } Line { SrcBlock "Constant3" SrcPort 1 DstBlock "De-Interleave RAM 1" DstPort 4 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "De-Interleave RAM 1" DstPort 5 } Line { SrcBlock "From18" SrcPort 1 DstBlock "De-Interleave RAM 1" DstPort 6 } Line { SrcBlock "From19" SrcPort 1 DstBlock "De-Interleave RAM 0" DstPort 6 } Line { SrcBlock "De-Interleave RAM 0" SrcPort 1 DstBlock "Reinterpret" DstPort 1 } Line { SrcBlock "Constant4" SrcPort 1 Points [5, 0] Branch { DstBlock "Mux3" DstPort 4 } Branch { Points [0, 30] DstBlock "Mux3" DstPort 5 } } Line { SrcBlock "De-Interleave RAM 1" SrcPort 1 DstBlock "Reinterpret2" DstPort 1 } Line { SrcBlock "Concat" SrcPort 1 DstBlock "Mux3" DstPort 1 } Line { SrcBlock "Skip A" SrcPort 1 DstBlock "Delay1" DstPort 1 } Line { SrcBlock "Rd Sel" SrcPort 1 Points [370, 0] Branch { Points [0, 85] Branch { DstBlock "Concat" DstPort 2 } Branch { Points [0, 215] DstBlock "Concat1" DstPort 2 } } Branch { Points [0, -80] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "De-Interleave RAM 1" SrcPort 2 DstBlock "Reinterpret3" DstPort 1 } Line { SrcBlock "De-Interleave RAM 0" SrcPort 2 DstBlock "Reinterpret1" DstPort 1 } Line { SrcBlock "Concat1" SrcPort 1 DstBlock "Mux1" DstPort 1 } Line { SrcBlock "Skip B" SrcPort 1 DstBlock "Delay2" DstPort 1 } Line { SrcBlock "Constant5" SrcPort 1 Points [10, 0] Branch { DstBlock "Mux1" DstPort 4 } Branch { Points [0, 30] DstBlock "Mux1" DstPort 5 } } Line { SrcBlock "Mux1" SrcPort 1 DstBlock " LLR B" DstPort 1 } Line { SrcBlock "Reinterpret" SrcPort 1 DstBlock "Mux3" DstPort 2 } Line { SrcBlock "Reinterpret1" SrcPort 1 Points [25, 0; 0, 135] DstBlock "Mux1" DstPort 2 } Line { SrcBlock "Reinterpret2" SrcPort 1 Points [15, 0; 0, -135] DstBlock "Mux3" DstPort 3 } Line { SrcBlock "Reinterpret3" SrcPort 1 DstBlock "Mux1" DstPort 3 } Line { SrcBlock "LLR Vec" SrcPort 1 DstBlock "Convert" DstPort 1 } Line { SrcBlock "From15" SrcPort 1 DstBlock "Concat2" DstPort 1 } Line { SrcBlock "Constant6" SrcPort 1 DstBlock "Concat2" DstPort 2 } Line { SrcBlock "Delay1" SrcPort 1 Points [195, 0; 0, 45] Branch { Points [0, 120] DstBlock "Concat" DstPort 1 } Branch { DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "Delay2" SrcPort 1 Points [190, 0; 0, 50] Branch { Points [0, 310] DstBlock "Concat1" DstPort 1 } Branch { DstBlock "Gateway Out8" DstPort 1 } } Line { Name "Skip A" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 DstBlock "DeInt RAMs" DstPort 7 } Line { Name "Skip B" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 DstBlock "DeInt RAMs" DstPort 8 } Annotation { Name "These RAMs contain one OFDM symbol's worth of coded bits, represented as log-likelihood ratios (LLR).\nT" "hese soft bits are written to the RAM in pairs (except for BPSK) in linear order. Once a full symbol's\nworth of b" "its is written the same bits are then read in de-interleaved order. The bits are read in pairs and\nfed directly i" "nto the rate 1/2 Viterbi decoder. Operating on pairs-of-bits here significantly decreases the latency\nof the de-i" "nterleaving process and is necessary to finish decoding 64QAM 3/4 payloads inside the \nalloted 6usec post-Rx time" ".\nDe-puncturing is realized by setting the appropriate LLR output (A or B) to 0, indicating a zero-confidence\nva" "lue for the decoder. The Read Address Generator logic tracks which bit positions should have these\ninserted zero-" "confidence values." Position [912, 806] HorizontalAlignment "left" } } } Block { BlockType SubSystem Name "Read Addr Gen" SID "8729" Ports [5, 5] Position [645, 387, 800, 503] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Read Addr Gen" Location [-1678, 227, -2, 1187] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "125" Block { BlockType Inport Name "Block Wr Done" SID "8730" Position [25, 483, 55, 497] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "mod_sel" SID "8731" Position [205, 403, 235, 417] ZOrder -1 NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "SIGNAL sym" SID "8732" Position [25, 663, 55, 677] NamePlacement "alternate" Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "rate_sel" SID "8733" Position [205, 433, 235, 447] ZOrder -1 Port "4" IconDisplay "Port number" } Block { BlockType Inport Name "Reset" SID "8734" Position [25, 508, 55, 522] ZOrder -1 Port "5" IconDisplay "Port number" } Block { BlockType BusCreator Name "Bus\nCreator" SID "8735" Ports [2, 1] Position [960, 209, 965, 236] ZOrder -2 ShowName off Inputs "2" DisplayOption "bar" Port { PortNumber 1 Name "Skip AB" PropagatedSignals ", " RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType BusCreator Name "Bus\nCreator1" SID "8736" Ports [2, 1] Position [960, 164, 965, 191] ZOrder -2 ShowName off Inputs "2" DisplayOption "bar" Port { PortNumber 1 Name "Rd Addr AB" PropagatedSignals ", " RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType BusCreator Name "Bus\nCreator2" SID "8737" Ports [2, 1] Position [930, 89, 935, 116] ZOrder -2 ShowName off Inputs "2" DisplayOption "bar" Port { PortNumber 1 Name "Rd Ind AB" PropagatedSignals ", " RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType SubSystem Name "Ctrl" SID "8738" Ports [5, 6] Position [405, 388, 510, 547] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Ctrl" Location [405, 440, 1408, 1362] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "mod_sel" SID "8739" Position [570, 218, 600, 232] IconDisplay "Port number" } Block { BlockType Inport Name "rate_sel" SID "8740" Position [530, 398, 560, 412] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "Reset" SID "8741" Position [305, 918, 335, 932] NamePlacement "alternate" Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "En" SID "8742" Position [305, 953, 335, 967] Port "4" IconDisplay "Port number" } Block { BlockType Inport Name "SIGNAL sym" SID "8743" Position [570, 288, 600, 302] NamePlacement "alternate" Port "5" IconDisplay "Port number" } Block { BlockType SubSystem Name "Bit Index Calc" SID "8744" Ports [5, 2] Position [860, 423, 955, 487] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off Port { PortNumber 2 Name "B" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } System { Name "Bit Index Calc" Location [1115, 418, 2079, 877] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Mod" SID "8745" Position [975, 383, 1000, 397] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "SIGNAL Sym" SID "8746" Position [750, 303, 780, 317] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "Inc" SID "8747" Position [715, 383, 745, 397] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "Rst" SID "8748" Position [750, 398, 780, 412] Port "4" IconDisplay "Port number" } Block { BlockType Inport Name "En" SID "8749" Position [790, 413, 820, 427] Port "5" IconDisplay "Port number" } Block { BlockType Reference Name "Accumulator" SID "8750" Ports [3, 1] Position [890, 382, 950, 428] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Accumulator" SourceType "Xilinx Accumulator Block" infoedit "Adder or subtracter-based accumulator. Output type and binary point position match the input.
Hardware notes: When \"Reinitialize with input 'b' on reset\" is selected, the accumulator is forced to ru" "n at the system rate even if the input 'b' is running at a slower rate." operation "Add" n_bits "ceil(log2(MAX_NCBPS))" overflow "Wrap" scale "1" rst on infoeditControl "reset for floating point data type must be asserted for a minimum of 2 cycles" hasbypass off en on latency "0" dbl_ovrd off msb_inp "100" msb "100" lsb "-100" use_behavioral_HDL on implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "accum" sg_icon_stat "60,46,3,1,white,blue,0,ee9eb47a,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 46 46 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 46 46 0 ]);\npatch([16.65 25.32 31.32 37.32 43.32 31.32 22.65 16.65 ],[29.66" " 29.66 35.66 29.66 35.66 35.66 35.66 29.66 ],[1 1 1 ]);\npatch([22.65 31.32 25.32 16.65 22.65 ],[23.66 23.66 29." "66 29.66 23.66 ],[0.931 0.946 0.973 ]);\npatch([16.65 25.32 31.32 22.65 16.65 ],[17.66 17.66 23.66 23.66 17.66 ]" ",[1 1 1 ]);\npatch([22.65 43.32 37.32 31.32 25.32 16.65 22.65 ],[11.66 11.66 17.66 11.66 17.66 17.66 11.66 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'b');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('inpu" "t',3,'en');\ncolor('black');port_label('output',1,'\\bf+=b','texmode','on');\nfprintf('','COMMENT: end icon text" "');" } Block { BlockType Reference Name "AddSub" SID "8751" Ports [2, 1] Position [1010, 507, 1040, 538] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Unsigned" n_bits "ceil(log2(MAX_NCBPS))" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL off hw_selection "Fabric" pipelined off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" sg_icon_stat "30,31,2,1,white,blue,0,e139daf6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 31 31 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 31 31 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 19.4" "4 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 19.44 " "15.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\np" "atch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('in" "put',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bf{a + b}','tex" "mode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Concat" SID "8752" Ports [3, 1] Position [1085, 368, 1110, 412] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point " "at zero." num_inputs "3" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "25,44,3,1,white,blue,0,61ef8218,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 44 44 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[25.33 " "25.33 28.33 25.33 28.33 28.33 28.33 25.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[22.33 22.33 25.33" " 25.33 22.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[19.33 19.33 22.33 22.33 19.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[16.33 16.33 19.33 16.33 19.33 19.33 16.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('blac" "k');port_label('input',1,'hi');\n\ncolor('black');port_label('input',3,'lo');\n\ncolor('black');disp('\\fontsize" "{20}\\}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Concat1" SID "8753" Ports [3, 1] Position [1085, 488, 1110, 532] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point " "at zero." num_inputs "3" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "25,44,3,1,white,blue,0,61ef8218,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 44 44 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[25.33 " "25.33 28.33 25.33 28.33 28.33 28.33 25.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[22.33 22.33 25.33" " 25.33 22.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[19.33 19.33 22.33 22.33 19.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[16.33 16.33 19.33 16.33 19.33 19.33 16.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('blac" "k');port_label('input',1,'hi');\n\ncolor('black');port_label('input',3,'lo');\n\ncolor('black');disp('\\fontsize" "{20}\\}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant2" SID "8754" Ports [0, 1] Position [940, 522, 960, 538] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "20,16,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 20 20 0 0 ],[0 0 16 16 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[10.22 10." "22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[8.22 8.22 10.22 10.22 8" ".22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatch([" "7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprintf(''" ",'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'" "1');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From2" SID "8755" Position [750, 318, 915, 342] ZOrder -9 ShowName off GotoTag "RX_PHY_MODE_11N" TagVisibility "global" } Block { BlockType Reference Name "Inverter" SID "8756" Ports [1, 1] Position [870, 299, 895, 321] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "25,22,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 22 22 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[14.33 " "14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 1 " "1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');di" "sp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical" SID "8757" Ports [2, 1] Position [940, 301, 975, 339] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,38,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 38 38 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 38 38 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[24.55 24." "55 29.55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[19.55 19.55 24.55 2" "4.55 19.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black" "');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Ind A" SID "8758" Position [1280, 383, 1310, 397] IconDisplay "Port number" } Block { BlockType Outport Name "Ind B" SID "8759" Position [1280, 503, 1310, 517] Port "2" IconDisplay "Port number" } Line { SrcBlock "Accumulator" SrcPort 1 Points [15, 0] Branch { Points [0, 110] DstBlock "AddSub" DstPort 1 } Branch { DstBlock "Concat" DstPort 3 } } Line { SrcBlock "Concat" SrcPort 1 DstBlock "Ind A" DstPort 1 } Line { SrcBlock "Concat1" SrcPort 1 DstBlock "Ind B" DstPort 1 } Line { SrcBlock "AddSub" SrcPort 1 DstBlock "Concat1" DstPort 3 } Line { SrcBlock "Constant2" SrcPort 1 DstBlock "AddSub" DstPort 2 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical" DstPort 1 } Line { SrcBlock "From2" SrcPort 1 DstBlock "Logical" DstPort 2 } Line { SrcBlock "Logical" SrcPort 1 Points [75, 0; 0, 55] Branch { DstBlock "Concat" DstPort 1 } Branch { Points [0, 120] DstBlock "Concat1" DstPort 1 } } Line { SrcBlock "SIGNAL Sym" SrcPort 1 DstBlock "Inverter" DstPort 1 } Line { SrcBlock "Mod" SrcPort 1 Points [45, 0] Branch { DstBlock "Concat" DstPort 2 } Branch { Points [0, 120] DstBlock "Concat1" DstPort 2 } } Line { SrcBlock "Rst" SrcPort 1 DstBlock "Accumulator" DstPort 2 } Line { SrcBlock "En" SrcPort 1 DstBlock "Accumulator" DstPort 3 } Line { SrcBlock "Inc" SrcPort 1 DstBlock "Accumulator" DstPort 1 } Annotation { Name "Accumulator increments by 1 or 2 bits per cycle, depending\non whether current LLR pair had a punctur" "ed value.\nOutputs are used as memory addresses in de-interleaver\nmapping ROMs. PHY Mode (11ag vs 11n) is MSB,\n" "modulation index is next, then the actual bit indexes." Position [736, 603] HorizontalAlignment "left" } } } Block { BlockType SubSystem Name "Data Bits\nCount" SID "8760" Ports [2, 1] Position [860, 219, 935, 321] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Data Bits\nCount" Location [481, 83, 1524, 616] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "En" SID "8761" Position [755, 273, 785, 287] IconDisplay "Port number" } Block { BlockType Inport Name "SIGNAL sym" SID "8762" Position [610, 398, 640, 412] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub" SID "8763" Ports [2, 1] Position [480, 421, 525, 459] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Subtraction" use_carryin off use_carryout off en off latency "1" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL off hw_selection "Fabric" pipelined off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" sg_icon_stat "45,38,2,1,white,blue,0,8a00a986,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 38 38 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 38 38 0 ]);\npatch([10.875 18.1 23.1 28.1 33.1 23.1 15.875 10.875 ],[24.55 2" "4.55 29.55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([15.875 23.1 18.1 10.875 15.875 ],[19.55 19.55 24.5" "5 24.55 19.55 ],[0.931 0.946 0.973 ]);\npatch([10.875 18.1 23.1 15.875 10.875 ],[14.55 14.55 19.55 19.55 14.55 ]" ",[1 1 1 ]);\npatch([15.875 33.1 28.1 23.1 18.1 10.875 15.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'" "\\bf{a - b}','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\" "newline\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant17" SID "8764" Ports [0, 1] Position [400, 442, 430, 458] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period on period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,16,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 16 16 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_la" "bel('output',1,'1');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant19" SID "8765" Ports [0, 1] Position [610, 467, 640, 483] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "NDBPS_11a_BPSK12-1" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "ceil(log2(MAX_NCBPS))" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,16,0,1,white,blue,0,0f04cd3c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 16 16 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_la" "bel('output',1,'23');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Counter" SID "8766" Ports [2, 1] Position [820, 235, 880, 295] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited count" "er is implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "Inf" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "ceil(log2(MAX_NCBPS))" bin_pt "0" load_pin off rst on en on explicit_period "off" period "1" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "11,12,348,661" block_type "counter" sg_icon_stat "60,60,2,1,white,blue,0,ae3608d6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 60 60 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[38.88 38" ".88 46.88 38.88 46.88 46.88 46.88 38.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[30.88 30.88 38.88 38." "88 30.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[22.88 22.88 30.88 30.88 22.88 ],[1 1 1 ]" ");\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[14.88 14.88 22.88 14.88 22.88 22.88 14.88 ],[0.931 0.946 0." "973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port" "_label('input',1,'rst');\ncolor('black');port_label('input',2,'en');\n\ncolor('black');disp('{\\fontsize{14}\\bf" "++}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From1" SID "8767" Position [205, 421, 430, 439] ZOrder -9 ShowName off GotoTag "OFDM_RX_DATA_N_DBPS_2" TagVisibility "global" } Block { BlockType Reference Name "Mux4" SID "8768" Ports [3, 1] Position [710, 390, 740, 490] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "30,100,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 14.2857 85.7143 100 0 " "],[0.77 0.82 0.91 ]);\nplot([0 30 30 0 0 ],[0 14.2857 85.7143 100 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.8" "8 10.1 6.1 ],[54.44 54.44 58.44 54.44 58.44 58.44 58.44 54.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[" "50.44 50.44 54.44 54.44 50.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[46.44 46.44 50.44 50." "44 46.44 ],[1 1 1 ]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[42.44 42.44 46.44 42.44 46.44 46.44 42.44" " ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nc" "olor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_labe" "l('input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational1" SID "8769" Ports [2, 1] Position [1065, 415, 1100, 450] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a>=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,35,2,1,white,blue,0,6218dc92,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 35 35 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 35 35 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[22.55 22." "55 27.55 22.55 27.55 27.55 27.55 22.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[17.55 17.55 22.55 2" "2.55 17.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[12.55 12.55 17.55 17.55 12.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[7.55 7.55 12.55 7.55 12.55 12.55 7.55 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');por" "t_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa " "\\geq b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Done" SID "8770" Position [1165, 428, 1195, 442] NamePlacement "alternate" IconDisplay "Port number" } Line { SrcBlock "Relational1" SrcPort 1 Points [20, 0] Branch { DstBlock "Done" DstPort 1 } Branch { Points [0, -220; -355, 0; 0, 35] DstBlock "Counter" DstPort 1 } } Line { SrcBlock "Counter" SrcPort 1 Points [45, 0; 0, 160] DstBlock "Relational1" DstPort 1 } Line { SrcBlock "En" SrcPort 1 DstBlock "Counter" DstPort 2 } Line { SrcBlock "SIGNAL sym" SrcPort 1 DstBlock "Mux4" DstPort 1 } Line { SrcBlock "Constant19" SrcPort 1 DstBlock "Mux4" DstPort 3 } Line { SrcBlock "From1" SrcPort 1 DstBlock "AddSub" DstPort 1 } Line { SrcBlock "Constant17" SrcPort 1 DstBlock "AddSub" DstPort 2 } Line { SrcBlock "AddSub" SrcPort 1 DstBlock "Mux4" DstPort 2 } Line { SrcBlock "Mux4" SrcPort 1 DstBlock "Relational1" DstPort 2 } Annotation { Name "This subsystem counts how many LLR pairs are input to\nthe decoder. Each LLR pair encodes 2 coded bit" "s (1 data bit). It would be possible\nto replace this block with a more efficient one based on the control\nbloc" "ks one level up, but this design will enable easier addition of\nadditional rates in the future." Position [842, 151] } Annotation { Name "IMPORTANT: the N_DBPS values used here assume 1 spatial stream.\nThese values represent the number of" " data bits in a single OFDM symbol,\n*not* the number of bits in each OFDM symbol interval. When this model\nis " "extended to 2 spatial streams this block will require modifications \nto divide N_DBPS by 2 when N_SS = 2!" Position [205, 367] HorizontalAlignment "left" } } } Block { BlockType Scope Name "De Int ctrl" SID "8771" Ports [8] Position [1470, 113, 1505, 322] ZOrder -3 Floating off Location [5, 40, 1925, 1194] Open off NumInputPorts "8" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" } List { ListType ScopeGraphics FigureColor "[0.5 0.5 0.5]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "18000" YMin "0~0~0~0~0~0~-1~0" YMax "1~2~1~1~100~800~1~1" SaveName "ScopeData38" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType From Name "From1" SID "8772" Position [520, 421, 620, 439] ZOrder -9 ShowName off GotoTag "R12_INC_A" } Block { BlockType From Name "From10" SID "8773" Position [520, 811, 620, 829] ZOrder -9 ShowName off GotoTag "R56_SKIP_B" } Block { BlockType From Name "From11" SID "8774" Position [520, 626, 620, 644] ZOrder -9 ShowName off GotoTag "R34_SKIP_A" } Block { BlockType From Name "From12" SID "8775" Position [520, 786, 620, 804] ZOrder -9 ShowName off GotoTag "R34_SKIP_B" } Block { BlockType From Name "From2" SID "8776" Position [520, 496, 620, 514] ZOrder -9 ShowName off GotoTag "R56_INC_A" } Block { BlockType From Name "From3" SID "8777" Position [520, 576, 620, 594] ZOrder -9 ShowName off GotoTag "R12_SKIP_A" } Block { BlockType From Name "From4" SID "8778" Position [520, 736, 620, 754] ZOrder -9 ShowName off GotoTag "R12_SKIP_B" } Block { BlockType From Name "From5" SID "8779" Position [520, 446, 620, 464] ZOrder -9 ShowName off GotoTag "R23_INC_A" } Block { BlockType From Name "From6" SID "8780" Position [520, 651, 620, 669] ZOrder -9 ShowName off GotoTag "R56_SKIP_A" } Block { BlockType From Name "From7" SID "8781" Position [520, 601, 620, 619] ZOrder -9 ShowName off GotoTag "R23_SKIP_A" } Block { BlockType From Name "From8" SID "8782" Position [520, 761, 620, 779] ZOrder -9 ShowName off GotoTag "R23_SKIP_B" } Block { BlockType From Name "From9" SID "8783" Position [520, 471, 620, 489] ZOrder -9 ShowName off GotoTag "R34_INC_A" } Block { BlockType Reference Name "Gateway Out1" SID "8784" Ports [1, 1] Position [1340, 149, 1375, 161] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Rate" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "8785" Ports [1, 1] Position [1340, 124, 1375, 136] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Mod" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "8786" Ports [1, 1] Position [1340, 174, 1375, 186] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Rst" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "8787" Ports [1, 1] Position [1340, 199, 1375, 211] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "En" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "8788" Ports [1, 1] Position [1340, 224, 1375, 236] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "A" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "8789" Ports [1, 1] Position [1340, 249, 1375, 261] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "B" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "8790" Ports [1, 1] Position [1340, 299, 1375, 311] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Vout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "8791" Ports [1, 1] Position [1340, 274, 1375, 286] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Done" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Goto Name "Goto" SID "8792" Position [540, 1001, 640, 1019] ZOrder -10 ShowName off GotoTag "R23_INC_A" TagVisibility "local" } Block { BlockType Goto Name "Goto1" SID "8793" Position [540, 1191, 640, 1209] ZOrder -10 ShowName off GotoTag "R56_INC_A" TagVisibility "local" } Block { BlockType Goto Name "Goto10" SID "8794" Position [540, 931, 640, 949] ZOrder -10 ShowName off GotoTag "R12_SKIP_A" TagVisibility "local" } Block { BlockType Goto Name "Goto11" SID "8795" Position [540, 951, 640, 969] ZOrder -10 ShowName off GotoTag "R12_SKIP_B" TagVisibility "local" } Block { BlockType Goto Name "Goto2" SID "8796" Position [540, 1021, 640, 1039] ZOrder -10 ShowName off GotoTag "R23_SKIP_A" TagVisibility "local" } Block { BlockType Goto Name "Goto3" SID "8797" Position [540, 1041, 640, 1059] ZOrder -10 ShowName off GotoTag "R23_SKIP_B" TagVisibility "local" } Block { BlockType Goto Name "Goto4" SID "8798" Position [540, 1091, 640, 1109] ZOrder -10 ShowName off GotoTag "R34_INC_A" TagVisibility "local" } Block { BlockType Goto Name "Goto5" SID "8799" Position [540, 1216, 640, 1234] ZOrder -10 ShowName off GotoTag "R56_SKIP_A" TagVisibility "local" } Block { BlockType Goto Name "Goto6" SID "8800" Position [540, 1116, 640, 1134] ZOrder -10 ShowName off GotoTag "R34_SKIP_A" TagVisibility "local" } Block { BlockType Goto Name "Goto7" SID "8801" Position [540, 1141, 640, 1159] ZOrder -10 ShowName off GotoTag "R34_SKIP_B" TagVisibility "local" } Block { BlockType Goto Name "Goto8" SID "8802" Position [540, 911, 640, 929] ZOrder -10 ShowName off GotoTag "R12_INC_A" TagVisibility "local" } Block { BlockType Goto Name "Goto9" SID "8803" Position [540, 1241, 640, 1259] ZOrder -10 ShowName off GotoTag "R56_SKIP_B" TagVisibility "local" } Block { BlockType Reference Name "Mux1" SID "8804" Ports [5, 1] Position [675, 704, 695, 836] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "4" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "20,132,5,1,white,blue,3,d6c79293,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 18.8571 113.143 132 0 " "],[0.77 0.82 0.91 ]);\nplot([0 20 20 0 0 ],[0 18.8571 113.143 132 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.4" "4 7.55 5.55 ],[68.22 68.22 70.22 68.22 70.22 70.22 70.22 68.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ]," "[66.22 66.22 68.22 68.22 66.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[64.22 64.22 66.22 6" "6.22 64.22 ],[1 1 1 ]);\npatch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[62.22 62.22 64.22 62.22 64.22 64.22 62." "22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n" "color('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_lab" "el('input',3,'d1');\ncolor('black');port_label('input',4,'d2');\ncolor('black');port_label('input',5,'d3');\n\nc" "olor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux3" SID "8805" Ports [5, 1] Position [675, 544, 695, 676] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "4" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "20,132,5,1,white,blue,3,d6c79293,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 18.8571 113.143 132 0 " "],[0.77 0.82 0.91 ]);\nplot([0 20 20 0 0 ],[0 18.8571 113.143 132 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.4" "4 7.55 5.55 ],[68.22 68.22 70.22 68.22 70.22 70.22 70.22 68.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ]," "[66.22 66.22 68.22 68.22 66.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[64.22 64.22 66.22 6" "6.22 64.22 ],[1 1 1 ]);\npatch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[62.22 62.22 64.22 62.22 64.22 64.22 62." "22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n" "color('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_lab" "el('input',3,'d1');\ncolor('black');port_label('input',4,'d2');\ncolor('black');port_label('input',5,'d3');\n\nc" "olor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux4" SID "8806" Ports [5, 1] Position [675, 389, 695, 521] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "4" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "20,132,5,1,white,blue,3,d6c79293,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 18.8571 113.143 132 0 " "],[0.77 0.82 0.91 ]);\nplot([0 20 20 0 0 ],[0 18.8571 113.143 132 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.4" "4 7.55 5.55 ],[68.22 68.22 70.22 68.22 70.22 70.22 70.22 68.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ]," "[66.22 66.22 68.22 68.22 66.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[64.22 64.22 66.22 6" "6.22 64.22 ],[1 1 1 ]);\npatch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[62.22 62.22 64.22 62.22 64.22 64.22 62." "22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n" "color('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_lab" "el('input',3,'d1');\ncolor('black');port_label('input',4,'d2');\ncolor('black');port_label('input',5,'d3');\n\nc" "olor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Rate 1/2" SID "8807" Ports [2, 3] Position [410, 906, 485, 974] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Rate 1/2" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Rst" SID "8808" Position [210, 263, 240, 277] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "En" SID "8809" Position [210, 288, 240, 302] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Constant2" SID "8810" Ports [0, 1] Position [375, 219, 405, 241] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Boolean" arith_type "Boolean" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period on period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,22,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 22 22 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[14.3" "3 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[11.33 11.33 " "14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[8.33 8.33 11.33 11.33 8.33 " "],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('blac" "k');port_label('output',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant3" SID "8811" Ports [0, 1] Position [375, 334, 405, 356] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "2" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,22,0,1,white,blue,0,fca86624,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 22 22 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[14.3" "3 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[11.33 11.33 " "14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[8.33 8.33 11.33 11.33 8.33 " "],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('blac" "k');port_label('output',1,'2');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Ind Inc" SID "8812" Position [525, 338, 555, 352] IconDisplay "Port number" } Block { BlockType Outport Name "Skip A" SID "8813" Position [525, 223, 555, 237] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "Skip B" SID "8814" Position [525, 268, 555, 282] Port "3" IconDisplay "Port number" } Line { SrcBlock "Constant2" SrcPort 1 Points [70, 0] Branch { DstBlock "Skip A" DstPort 1 } Branch { Points [0, 45] DstBlock "Skip B" DstPort 1 } } Line { SrcBlock "Constant3" SrcPort 1 DstBlock "Ind Inc" DstPort 1 } } } Block { BlockType SubSystem Name "Rate 2/3" SID "8815" Ports [2, 3] Position [410, 996, 485, 1064] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Rate 2/3" Location [88, 301, 1810, 1515] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Rst" SID "8816" Position [210, 263, 240, 277] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "En" SID "8817" Position [210, 288, 240, 302] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "8818" Ports [0, 1] Position [375, 294, 405, 316] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,22,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 22 22 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[14.3" "3 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[11.33 11.33 " "14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[8.33 8.33 11.33 11.33 8.33 " "],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('blac" "k');port_label('output',1,'1');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant2" SID "8819" Ports [0, 1] Position [375, 219, 405, 241] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Boolean" arith_type "Boolean" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period on period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,22,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 22 22 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[14.3" "3 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[11.33 11.33 " "14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[8.33 8.33 11.33 11.33 8.33 " "],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('blac" "k');port_label('output',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant3" SID "8820" Ports [0, 1] Position [445, 424, 475, 446] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "2" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,22,0,1,white,blue,0,fca86624,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 22 22 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[14.3" "3 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[11.33 11.33 " "14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[8.33 8.33 11.33 11.33 8.33 " "],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('blac" "k');port_label('output',1,'2');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant4" SID "8821" Ports [0, 1] Position [445, 474, 475, 496] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,22,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 22 22 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[14.3" "3 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[11.33 11.33 " "14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[8.33 8.33 11.33 11.33 8.33 " "],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('blac" "k');port_label('output',1,'1');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux3" SID "8822" Ports [3, 1] Position [530, 357, 550, 513] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "20,156,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 22.2857 133.714 156 0 " "],[0.77 0.82 0.91 ]);\nplot([0 20 20 0 0 ],[0 22.2857 133.714 156 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.4" "4 7.55 5.55 ],[80.22 80.22 82.22 80.22 82.22 82.22 82.22 80.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ]," "[78.22 78.22 80.22 80.22 78.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[76.22 76.22 78.22 7" "8.22 76.22 ],[1 1 1 ]);\npatch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[74.22 74.22 76.22 74.22 76.22 76.22 74." "22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n" "color('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_lab" "el('input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational" SID "8823" Ports [2, 1] Position [445, 276, 480, 314] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,38,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 38 38 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 38 38 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[24.55 24." "55 29.55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[19.55 19.55 24.55 2" "4.55 19.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');por" "t_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa " "= b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "[0:1]" SID "8824" Ports [2, 1] Position [275, 259, 330, 306] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited count" "er is implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "5" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "1" bin_pt "0" load_pin off rst on en on explicit_period "off" period "1" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "counter" sg_icon_stat "55,47,2,1,white,blue,0,ae3608d6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 47 47 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 47 47 0 ]);\npatch([13.65 22.32 28.32 34.32 40.32 28.32 19.65 13.65 ],[29.66" " 29.66 35.66 29.66 35.66 35.66 35.66 29.66 ],[1 1 1 ]);\npatch([19.65 28.32 22.32 13.65 19.65 ],[23.66 23.66 29." "66 29.66 23.66 ],[0.931 0.946 0.973 ]);\npatch([13.65 22.32 28.32 19.65 13.65 ],[17.66 17.66 23.66 23.66 17.66 ]" ",[1 1 1 ]);\npatch([19.65 40.32 34.32 28.32 22.32 13.65 19.65 ],[11.66 11.66 17.66 11.66 17.66 17.66 11.66 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'rst');\ncolor('black');port_label('input',2,'en');\n\ncolor('black');disp('{\\font" "size{14}\\bf++}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Ind Inc" SID "8825" Position [630, 428, 660, 442] IconDisplay "Port number" } Block { BlockType Outport Name "Skip A" SID "8826" Position [525, 223, 555, 237] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "Skip B" SID "8827" Position [525, 288, 555, 302] Port "3" IconDisplay "Port number" } Line { SrcBlock "[0:1]" SrcPort 1 DstBlock "Relational" DstPort 1 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Relational" DstPort 2 } Line { SrcBlock "Relational" SrcPort 1 Points [15, 0] Branch { DstBlock "Skip B" DstPort 1 } Branch { Points [0, 90] DstBlock "Mux3" DstPort 1 } } Line { SrcBlock "Rst" SrcPort 1 DstBlock "[0:1]" DstPort 1 } Line { SrcBlock "En" SrcPort 1 DstBlock "[0:1]" DstPort 2 } Line { SrcBlock "Constant2" SrcPort 1 DstBlock "Skip A" DstPort 1 } Line { SrcBlock "Mux3" SrcPort 1 DstBlock "Ind Inc" DstPort 1 } Line { SrcBlock "Constant3" SrcPort 1 DstBlock "Mux3" DstPort 2 } Line { SrcBlock "Constant4" SrcPort 1 DstBlock "Mux3" DstPort 3 } } } Block { BlockType SubSystem Name "Rate 3/4" SID "8828" Ports [2, 3] Position [410, 1090, 485, 1160] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Rate 3/4" Location [88, 301, 1810, 1515] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Rst" SID "8829" Position [530, 443, 560, 457] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "En" SID "8830" Position [530, 468, 560, 482] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Concat" SID "8831" Ports [2, 1] Position [905, 588, 930, 632] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point " "at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "25,44,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 44 44 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[25.33 " "25.33 28.33 25.33 28.33 28.33 28.33 25.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[22.33 22.33 25.33" " 25.33 22.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[19.33 19.33 22.33 22.33 19.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[16.33 16.33 19.33 16.33 19.33 19.33 16.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('blac" "k');port_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fontsize{2" "0}\\}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant1" SID "8832" Ports [0, 1] Position [695, 474, 725, 496] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "2" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,22,0,1,white,blue,0,fca86624,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 22 22 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[14.3" "3 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[11.33 11.33 " "14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[8.33 8.33 11.33 11.33 8.33 " "],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('blac" "k');port_label('output',1,'2');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant2" SID "8833" Ports [0, 1] Position [695, 514, 725, 536] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,22,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 22 22 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[14.3" "3 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[11.33 11.33 " "14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[8.33 8.33 11.33 11.33 8.33 " "],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('blac" "k');port_label('output',1,'1');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant3" SID "8834" Ports [0, 1] Position [900, 644, 930, 666] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "2" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,22,0,1,white,blue,0,fca86624,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 22 22 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[14.3" "3 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[11.33 11.33 " "14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[8.33 8.33 11.33 11.33 8.33 " "],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('blac" "k');port_label('output',1,'2');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant4" SID "8835" Ports [0, 1] Position [900, 689, 930, 711] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "2" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,22,0,1,white,blue,0,fca86624,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 22 22 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[14.3" "3 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[11.33 11.33 " "14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[8.33 8.33 11.33 11.33 8.33 " "],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('blac" "k');port_label('output',1,'2');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant7" SID "8836" Ports [0, 1] Position [900, 734, 930, 756] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,22,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 22 22 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[14.3" "3 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[11.33 11.33 " "14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[8.33 8.33 11.33 11.33 8.33 " "],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('blac" "k');port_label('output',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux3" SID "8837" Ports [4, 1] Position [985, 589, 1005, 766] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "20,177,4,1,white,blue,3,58b3489d,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 25.2857 151.714 177 0 " "],[0.77 0.82 0.91 ]);\nplot([0 20 20 0 0 ],[0 25.2857 151.714 177 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.4" "4 7.55 5.55 ],[90.22 90.22 92.22 90.22 92.22 92.22 92.22 90.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ]," "[88.22 88.22 90.22 90.22 88.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[86.22 86.22 88.22 8" "8.22 86.22 ],[1 1 1 ]);\npatch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[84.22 84.22 86.22 84.22 86.22 86.22 84." "22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n" "color('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_lab" "el('input',3,'d1');\ncolor('black');port_label('input',4,'d2');\n\ncolor('black');disp('\\bf{}','texmode','on');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational" SID "8838" Ports [2, 1] Position [765, 456, 800, 494] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,38,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 38 38 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 38 38 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[24.55 24." "55 29.55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[19.55 19.55 24.55 2" "4.55 19.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');por" "t_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa " "= b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational2" SID "8839" Ports [2, 1] Position [765, 496, 800, 534] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,38,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 38 38 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 38 38 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[24.55 24." "55 29.55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[19.55 19.55 24.55 2" "4.55 19.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');por" "t_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa " "= b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "[0:2]" SID "8840" Ports [2, 1] Position [595, 439, 650, 486] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited count" "er is implemented by combining a counter with a comparator." cnt_type "Count Limited" cnt_to "2" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "2" bin_pt "0" load_pin off rst on en on explicit_period "off" period "1" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "counter" sg_icon_stat "55,47,2,1,white,blue,0,131a2a7a,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 47 47 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 47 47 0 ]);\npatch([13.65 22.32 28.32 34.32 40.32 28.32 19.65 13.65 ],[29.66" " 29.66 35.66 29.66 35.66 35.66 35.66 29.66 ],[1 1 1 ]);\npatch([19.65 28.32 22.32 13.65 19.65 ],[23.66 23.66 29." "66 29.66 23.66 ],[0.931 0.946 0.973 ]);\npatch([13.65 22.32 28.32 19.65 13.65 ],[17.66 17.66 23.66 23.66 17.66 ]" ",[1 1 1 ]);\npatch([19.65 40.32 34.32 28.32 22.32 13.65 19.65 ],[11.66 11.66 17.66 11.66 17.66 17.66 11.66 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'rst');\ncolor('black');port_label('input',2,'en');\n\ncolor('black');disp('{\\font" "size{14}\\bf\\lceil++\\rceil}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Ind Inc" SID "8841" Position [1085, 673, 1115, 687] IconDisplay "Port number" } Block { BlockType Outport Name "Skip A" SID "8842" Position [965, 468, 995, 482] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "Skip B" SID "8843" Position [965, 508, 995, 522] Port "3" IconDisplay "Port number" } Line { SrcBlock "En" SrcPort 1 DstBlock "[0:2]" DstPort 2 } Line { SrcBlock "Rst" SrcPort 1 DstBlock "[0:2]" DstPort 1 } Line { SrcBlock "Relational2" SrcPort 1 Points [65, 0] Branch { DstBlock "Skip B" DstPort 1 } Branch { Points [0, 85] DstBlock "Concat" DstPort 1 } } Line { SrcBlock "Relational" SrcPort 1 Points [60, 0] Branch { DstBlock "Skip A" DstPort 1 } Branch { Points [0, 145] DstBlock "Concat" DstPort 2 } } Line { SrcBlock "Constant2" SrcPort 1 DstBlock "Relational2" DstPort 2 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Relational" DstPort 2 } Line { SrcBlock "[0:2]" SrcPort 1 Points [85, 0] Branch { Points [0, 40] DstBlock "Relational2" DstPort 1 } Branch { DstBlock "Relational" DstPort 1 } } Line { SrcBlock "Mux3" SrcPort 1 DstBlock "Ind Inc" DstPort 1 } Line { SrcBlock "Constant3" SrcPort 1 DstBlock "Mux3" DstPort 2 } Line { SrcBlock "Constant4" SrcPort 1 DstBlock "Mux3" DstPort 3 } Line { SrcBlock "Concat" SrcPort 1 DstBlock "Mux3" DstPort 1 } Line { SrcBlock "Constant7" SrcPort 1 DstBlock "Mux3" DstPort 4 } } } Block { BlockType SubSystem Name "Rate 5/6" SID "8844" Ports [2, 3] Position [410, 1190, 485, 1260] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Rate 5/6" Location [88, 301, 1810, 1515] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "124" Block { BlockType Inport Name "Rst" SID "8845" Position [125, 138, 155, 152] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "En" SID "8846" Position [125, 163, 155, 177] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Concat" SID "8847" Ports [2, 1] Position [515, 338, 540, 382] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point " "at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "25,44,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 44 44 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[25.33 " "25.33 28.33 25.33 28.33 28.33 28.33 25.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[22.33 22.33 25.33" " 25.33 22.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[19.33 19.33 22.33 22.33 19.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[16.33 16.33 19.33 16.33 19.33 19.33 16.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('blac" "k');port_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fontsize{2" "0}\\}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant1" SID "8848" Ports [0, 1] Position [285, 249, 315, 271] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,22,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 22 22 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[14.3" "3 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[11.33 11.33 " "14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[8.33 8.33 11.33 11.33 8.33 " "],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('blac" "k');port_label('output',1,'1');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant2" SID "8849" Ports [0, 1] Position [285, 169, 315, 191] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "2" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,22,0,1,white,blue,0,fca86624,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 22 22 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[14.3" "3 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[11.33 11.33 " "14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[8.33 8.33 11.33 11.33 8.33 " "],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('blac" "k');port_label('output',1,'2');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant3" SID "8850" Ports [0, 1] Position [510, 394, 540, 416] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "2" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,22,0,1,white,blue,0,fca86624,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 22 22 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[14.3" "3 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[11.33 11.33 " "14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[8.33 8.33 11.33 11.33 8.33 " "],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('blac" "k');port_label('output',1,'2');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant4" SID "8851" Ports [0, 1] Position [510, 439, 540, 461] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "2" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,22,0,1,white,blue,0,fca86624,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 22 22 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[14.3" "3 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[11.33 11.33 " "14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[8.33 8.33 11.33 11.33 8.33 " "],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('blac" "k');port_label('output',1,'2');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant5" SID "8852" Ports [0, 1] Position [285, 289, 315, 311] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "3" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,22,0,1,white,blue,0,279a71c8,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 22 22 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[14.3" "3 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[11.33 11.33 " "14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[8.33 8.33 11.33 11.33 8.33 " "],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('blac" "k');port_label('output',1,'3');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant6" SID "8853" Ports [0, 1] Position [285, 209, 315, 231] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "4" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,22,0,1,white,blue,0,85f36853,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 22 22 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[14.3" "3 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[11.33 11.33 " "14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[8.33 8.33 11.33 11.33 8.33 " "],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('blac" "k');port_label('output',1,'4');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant7" SID "8854" Ports [0, 1] Position [510, 484, 540, 506] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,22,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 22 22 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[14.3" "3 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[11.33 11.33 " "14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[8.33 8.33 11.33 11.33 8.33 " "],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('blac" "k');port_label('output',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical" SID "8855" Ports [2, 1] Position [430, 151, 460, 229] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "30,78,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 78 78 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 78 78 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[43.44 43.4" "4 47.44 43.44 47.44 47.44 47.44 43.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[39.44 39.44 43.44 43.44 " "39.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[35.44 35.44 39.44 39.44 35.44 ],[1 1 1 ]);\np" "atch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[31.44 31.44 35.44 31.44 35.44 35.44 31.44 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp" "('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "8856" Ports [2, 1] Position [430, 231, 460, 309] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "30,78,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 78 78 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 78 78 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[43.44 43.4" "4 47.44 43.44 47.44 47.44 47.44 43.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[39.44 39.44 43.44 43.44 " "39.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[35.44 35.44 39.44 39.44 35.44 ],[1 1 1 ]);\np" "atch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[31.44 31.44 35.44 31.44 35.44 35.44 31.44 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp" "('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux3" SID "8857" Ports [4, 1] Position [595, 339, 615, 516] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "20,177,4,1,white,blue,3,58b3489d,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 25.2857 151.714 177 0 " "],[0.77 0.82 0.91 ]);\nplot([0 20 20 0 0 ],[0 25.2857 151.714 177 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.4" "4 7.55 5.55 ],[90.22 90.22 92.22 90.22 92.22 92.22 92.22 90.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ]," "[88.22 88.22 90.22 90.22 88.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[86.22 86.22 88.22 8" "8.22 86.22 ],[1 1 1 ]);\npatch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[84.22 84.22 86.22 84.22 86.22 86.22 84." "22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n" "color('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_lab" "el('input',3,'d1');\ncolor('black');port_label('input',4,'d2');\n\ncolor('black');disp('\\bf{}','texmode','on');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational" SID "8858" Ports [2, 1] Position [360, 151, 395, 189] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,38,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 38 38 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 38 38 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[24.55 24." "55 29.55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[19.55 19.55 24.55 2" "4.55 19.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');por" "t_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa " "= b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational1" SID "8859" Ports [2, 1] Position [360, 231, 395, 269] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,38,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 38 38 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 38 38 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[24.55 24." "55 29.55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[19.55 19.55 24.55 2" "4.55 19.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');por" "t_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa " "= b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational2" SID "8860" Ports [2, 1] Position [360, 191, 395, 229] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,38,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 38 38 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 38 38 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[24.55 24." "55 29.55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[19.55 19.55 24.55 2" "4.55 19.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');por" "t_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa " "= b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational3" SID "8861" Ports [2, 1] Position [360, 271, 395, 309] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,38,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 38 38 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 38 38 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[24.55 24." "55 29.55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[19.55 19.55 24.55 2" "4.55 19.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');por" "t_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa " "= b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "[0:4]" SID "8862" Ports [2, 1] Position [190, 134, 245, 181] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited count" "er is implemented by combining a counter with a comparator." cnt_type "Count Limited" cnt_to "4" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "3" bin_pt "0" load_pin off rst on en on explicit_period "off" period "1" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "counter" sg_icon_stat "55,47,2,1,white,blue,0,131a2a7a,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 47 47 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 47 47 0 ]);\npatch([13.65 22.32 28.32 34.32 40.32 28.32 19.65 13.65 ],[29.66" " 29.66 35.66 29.66 35.66 35.66 35.66 29.66 ],[1 1 1 ]);\npatch([19.65 28.32 22.32 13.65 19.65 ],[23.66 23.66 29." "66 29.66 23.66 ],[0.931 0.946 0.973 ]);\npatch([13.65 22.32 28.32 19.65 13.65 ],[17.66 17.66 23.66 23.66 17.66 ]" ",[1 1 1 ]);\npatch([19.65 40.32 34.32 28.32 22.32 13.65 19.65 ],[11.66 11.66 17.66 11.66 17.66 17.66 11.66 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'rst');\ncolor('black');port_label('input',2,'en');\n\ncolor('black');disp('{\\font" "size{14}\\bf\\lceil++\\rceil}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Ind Inc" SID "8863" Position [695, 423, 725, 437] IconDisplay "Port number" } Block { BlockType Outport Name "Skip A" SID "8864" Position [525, 183, 555, 197] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "Skip B" SID "8865" Position [525, 263, 555, 277] Port "3" IconDisplay "Port number" } Line { SrcBlock "Constant7" SrcPort 1 DstBlock "Mux3" DstPort 4 } Line { SrcBlock "Concat" SrcPort 1 DstBlock "Mux3" DstPort 1 } Line { SrcBlock "Constant4" SrcPort 1 DstBlock "Mux3" DstPort 3 } Line { SrcBlock "Constant3" SrcPort 1 DstBlock "Mux3" DstPort 2 } Line { SrcBlock "Mux3" SrcPort 1 DstBlock "Ind Inc" DstPort 1 } Line { SrcBlock "[0:4]" SrcPort 1 Points [85, 0] Branch { DstBlock "Relational" DstPort 1 } Branch { Points [0, 40] Branch { DstBlock "Relational2" DstPort 1 } Branch { Points [0, 40] Branch { DstBlock "Relational1" DstPort 1 } Branch { Points [0, 40] DstBlock "Relational3" DstPort 1 } } } } Line { SrcBlock "Constant2" SrcPort 1 DstBlock "Relational" DstPort 2 } Line { SrcBlock "Constant6" SrcPort 1 DstBlock "Relational2" DstPort 2 } Line { SrcBlock "Rst" SrcPort 1 DstBlock "[0:4]" DstPort 1 } Line { SrcBlock "En" SrcPort 1 DstBlock "[0:4]" DstPort 2 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Relational1" DstPort 2 } Line { SrcBlock "Constant5" SrcPort 1 DstBlock "Relational3" DstPort 2 } Line { SrcBlock "Relational" SrcPort 1 DstBlock "Logical" DstPort 1 } Line { SrcBlock "Relational2" SrcPort 1 DstBlock "Logical" DstPort 2 } Line { SrcBlock "Logical" SrcPort 1 Points [25, 0] Branch { DstBlock "Skip A" DstPort 1 } Branch { Points [0, 180] DstBlock "Concat" DstPort 2 } } Line { SrcBlock "Relational1" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Relational3" SrcPort 1 DstBlock "Logical1" DstPort 2 } Line { SrcBlock "Logical1" SrcPort 1 Points [30, 0] Branch { DstBlock "Skip B" DstPort 1 } Branch { Points [0, 80] DstBlock "Concat" DstPort 1 } } } } Block { BlockType Outport Name "Ind A" SID "8866" Position [1260, 433, 1290, 447] IconDisplay "Port number" } Block { BlockType Outport Name "Ind B" SID "8867" Position [1260, 463, 1290, 477] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "Skip A" SID "8868" Position [1260, 603, 1290, 617] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "Skip B" SID "8869" Position [1260, 763, 1290, 777] Port "4" IconDisplay "Port number" } Block { BlockType Outport Name "Vout" SID "8870" Position [1330, 883, 1360, 897] Port "5" IconDisplay "Port number" } Block { BlockType Outport Name "Done" SID "8871" Position [990, 263, 1020, 277] NamePlacement "alternate" Port "6" IconDisplay "Port number" } Line { SrcBlock "Mux3" SrcPort 1 DstBlock "Skip A" DstPort 1 } Line { SrcBlock "Rate 1/2" SrcPort 1 DstBlock "Goto8" DstPort 1 } Line { SrcBlock "Rate 1/2" SrcPort 2 DstBlock "Goto10" DstPort 1 } Line { SrcBlock "Rate 1/2" SrcPort 3 DstBlock "Goto11" DstPort 1 } Line { SrcBlock "Rate 2/3" SrcPort 1 DstBlock "Goto" DstPort 1 } Line { SrcBlock "Rate 2/3" SrcPort 2 DstBlock "Goto2" DstPort 1 } Line { SrcBlock "Rate 2/3" SrcPort 3 DstBlock "Goto3" DstPort 1 } Line { SrcBlock "Rate 3/4" SrcPort 1 DstBlock "Goto4" DstPort 1 } Line { SrcBlock "Rate 3/4" SrcPort 2 DstBlock "Goto6" DstPort 1 } Line { SrcBlock "Rate 3/4" SrcPort 3 DstBlock "Goto7" DstPort 1 } Line { SrcBlock "From3" SrcPort 1 DstBlock "Mux3" DstPort 2 } Line { SrcBlock "From7" SrcPort 1 DstBlock "Mux3" DstPort 3 } Line { SrcBlock "From11" SrcPort 1 DstBlock "Mux3" DstPort 4 } Line { SrcBlock "Mux1" SrcPort 1 DstBlock "Skip B" DstPort 1 } Line { SrcBlock "From4" SrcPort 1 DstBlock "Mux1" DstPort 2 } Line { SrcBlock "From8" SrcPort 1 DstBlock "Mux1" DstPort 3 } Line { SrcBlock "From12" SrcPort 1 DstBlock "Mux1" DstPort 4 } Line { SrcBlock "From1" SrcPort 1 DstBlock "Mux4" DstPort 2 } Line { SrcBlock "From5" SrcPort 1 DstBlock "Mux4" DstPort 3 } Line { SrcBlock "From9" SrcPort 1 DstBlock "Mux4" DstPort 4 } Line { SrcBlock "Mux4" SrcPort 1 DstBlock "Bit Index Calc" DstPort 3 } Line { Name "Mod" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 DstBlock "De Int ctrl" DstPort 1 } Line { Name "Rate" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 DstBlock "De Int ctrl" DstPort 2 } Line { Name "Rst" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 DstBlock "De Int ctrl" DstPort 3 } Line { Name "En" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 DstBlock "De Int ctrl" DstPort 4 } Line { Name "A" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 DstBlock "De Int ctrl" DstPort 5 } Line { Name "Vout" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 DstBlock "De Int ctrl" DstPort 8 } Line { SrcBlock "Data Bits\nCount" SrcPort 1 Points [25, 0] Branch { DstBlock "Done" DstPort 1 } Branch { Points [0, 10] DstBlock "Gateway Out8" DstPort 1 } } Line { Name "Done" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 DstBlock "De Int ctrl" DstPort 7 } Line { Labels [1, 0] SrcBlock "mod_sel" SrcPort 1 Points [120, 0] Branch { Points [0, -95] DstBlock "Gateway Out2" DstPort 1 } Branch { Labels [0, 0] Points [0, 210] DstBlock "Bit Index Calc" DstPort 1 } } Line { SrcBlock "rate_sel" SrcPort 1 Points [85, 0] Branch { DstBlock "Mux4" DstPort 1 } Branch { Points [0, 155] Branch { DstBlock "Mux3" DstPort 1 } Branch { Points [0, 160] DstBlock "Mux1" DstPort 1 } } Branch { Points [0, -250] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "Reset" SrcPort 1 Points [40, 0] Branch { Points [0, -40] Branch { Points [0, -705] DstBlock "Gateway Out3" DstPort 1 } Branch { Labels [0, 0] Points [350, 0; 0, -420] DstBlock "Bit Index Calc" DstPort 4 } } Branch { Points [0, 90] Branch { DstBlock "Rate 2/3" DstPort 1 } Branch { Points [0, 95] Branch { DstBlock "Rate 3/4" DstPort 1 } Branch { Points [0, 100] DstBlock "Rate 5/6" DstPort 1 } } } Branch { DstBlock "Rate 1/2" DstPort 1 } } Line { SrcBlock "En" SrcPort 1 Points [15, 0] Branch { Points [30, 0] Branch { Points [0, -70; 350, 0] Branch { Points [570, 0] Branch { DstBlock "Vout" DstPort 1 } Branch { Points [0, -585] DstBlock "Gateway Out7" DstPort 1 } } Branch { Labels [0, 0] Points [0, -415] DstBlock "Bit Index Calc" DstPort 5 } } Branch { Points [0, 90] Branch { DstBlock "Rate 2/3" DstPort 2 } Branch { Points [0, 95] Branch { DstBlock "Rate 3/4" DstPort 2 } Branch { Points [0, 100] DstBlock "Rate 5/6" DstPort 2 } } } Branch { DstBlock "Rate 1/2" DstPort 2 } } Branch { Labels [0, 0] Points [0, -590] Branch { Points [0, -165] DstBlock "Gateway Out4" DstPort 1 } Branch { Points [350, 0; 0, -125] DstBlock "Data Bits\nCount" DstPort 1 } } } Line { SrcBlock "SIGNAL sym" SrcPort 1 Points [115, 0] Branch { DstBlock "Data Bits\nCount" DstPort 2 } Branch { Labels [0, 0] Points [0, 150] DstBlock "Bit Index Calc" DstPort 2 } } Line { SrcBlock "Bit Index Calc" SrcPort 1 Points [245, 0] Branch { DstBlock "Ind A" DstPort 1 } Branch { Points [0, -210] DstBlock "Gateway Out5" DstPort 1 } } Line { Name "B" SrcBlock "Bit Index Calc" SrcPort 2 Points [250, 0] Branch { DstBlock "Ind B" DstPort 1 } Branch { Points [0, -215] DstBlock "Gateway Out6" DstPort 1 } } Line { Name "B" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 DstBlock "De Int ctrl" DstPort 6 } Line { SrcBlock "From2" SrcPort 1 DstBlock "Mux4" DstPort 5 } Line { SrcBlock "From6" SrcPort 1 DstBlock "Mux3" DstPort 5 } Line { SrcBlock "Rate 5/6" SrcPort 1 DstBlock "Goto1" DstPort 1 } Line { SrcBlock "Rate 5/6" SrcPort 2 DstBlock "Goto5" DstPort 1 } Line { SrcBlock "Rate 5/6" SrcPort 3 DstBlock "Goto9" DstPort 1 } Line { SrcBlock "From10" SrcPort 1 DstBlock "Mux1" DstPort 5 } Annotation { Name "This accumulator counts the number of actual bits that have been read\nfrom the de-interleaver RAM. F" "or 1/2 rate code this is easy (2 bits per read).\nFor the punctured code rates some read cycles represent 0, 1 o" "r 2 bits. This is \nimportant as the de-interleaver RAM only contains received bits and not the \nzero-confidenc" "e values for de-punctured bits. De-puncturing is achieved by\nnot incrementing the read address and forcing the " "corresponding LLR\noutput to be zero (the value which means 'coin flip' for the decoder)" Position [961, 951] } } } Block { BlockType SubSystem Name "De-Interleave\nDP-ROM" SID "8872" Ports [2, 2] Position [645, 392, 710, 443] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "De-Interleave\nDP-ROM" Location [-1678, 227, -2, 1187] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Ind A" SID "8873" Position [410, 248, 440, 262] IconDisplay "Port number" } Block { BlockType Inport Name "Ind B" SID "8874" Position [410, 323, 440, 337] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Constant8" SID "8875" Ports [0, 1] Position [490, 272, 510, 288] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "ceil(log2(MAX_NCBPS))" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "20,16,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 20 20 0 0 ],[0 0 16 16 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[10.22 10." "22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[8.22 8.22 10.22 10.22 8" ".22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatch([" "7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprintf(''" ",'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'" "0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant9" SID "8876" Ports [0, 1] Position [490, 297, 510, 313] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Boolean" arith_type "Boolean" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "20,16,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 20 20 0 0 ],[0 0 16 16 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[10.22 10." "22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[8.22 8.22 10.22 10.22 8" ".22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatch([" "7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprintf(''" ",'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'" "0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "De-Interleave\nROM" SID "8877" Ports [6, 2] Position [570, 235, 645, 400] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Dual Port RAM" SourceType "Xilinx Dual Port Random Access Memory Block" depth "length(wlan_rx_deinterleave_rom_gen())" initVector "wlan_rx_deinterleave_rom_gen" distributed_mem "Block RAM" init_a "0" init_b "0" rst_a off rst_b off en_a off en_b off latency "1" write_mode_A "Read After Write" write_mode_B "Read After Write" dbl_ovrd off optimize "Area" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "dpram" sg_icon_stat "75,165,6,2,white,blue,0,28af736d,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 75 75 0 0 ],[0 0 165 165 0 ],[0.77 0." "82 0.91 ]);\nplot([0 75 75 0 0 ],[0 0 165 165 0 ]);\npatch([14.75 29.2 39.2 49.2 59.2 39.2 24.75 14.75 ],[93.1 9" "3.1 103.1 93.1 103.1 103.1 103.1 93.1 ],[1 1 1 ]);\npatch([24.75 39.2 29.2 14.75 24.75 ],[83.1 83.1 93.1 93.1 83" ".1 ],[0.931 0.946 0.973 ]);\npatch([14.75 29.2 39.2 24.75 14.75 ],[73.1 73.1 83.1 83.1 73.1 ],[1 1 1 ]);\npatch(" "[24.75 59.2 49.2 39.2 29.2 14.75 24.75 ],[63.1 63.1 73.1 63.1 73.1 73.1 63.1 ],[0.931 0.946 0.973 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "addra');\ncolor('black');port_label('input',2,'dina');\ncolor('black');port_label('input',3,'wea');\ncolor('blac" "k');port_label('input',4,'addrb');\ncolor('black');port_label('input',5,'dinb');\ncolor('black');port_label('inp" "ut',6,'web');\ncolor('black');port_label('output',1,'A');\ncolor('black');port_label('output',2,'B');\nfprintf('" "','COMMENT: end icon text');" } Block { BlockType Outport Name "Addr A" SID "8878" Position [710, 273, 740, 287] IconDisplay "Port number" } Block { BlockType Outport Name "Addr B" SID "8879" Position [710, 353, 740, 367] Port "2" IconDisplay "Port number" } Line { SrcBlock "Constant8" SrcPort 1 Points [20, 0] Branch { DstBlock "De-Interleave\nROM" DstPort 2 } Branch { Points [0, 75] DstBlock "De-Interleave\nROM" DstPort 5 } } Line { SrcBlock "Constant9" SrcPort 1 Points [15, 0] Branch { DstBlock "De-Interleave\nROM" DstPort 3 } Branch { Points [0, 75] DstBlock "De-Interleave\nROM" DstPort 6 } } Line { SrcBlock "Ind A" SrcPort 1 DstBlock "De-Interleave\nROM" DstPort 1 } Line { SrcBlock "De-Interleave\nROM" SrcPort 1 DstBlock "Addr A" DstPort 1 } Line { SrcBlock "Ind B" SrcPort 1 DstBlock "De-Interleave\nROM" DstPort 4 } Line { SrcBlock "De-Interleave\nROM" SrcPort 2 DstBlock "Addr B" DstPort 1 } } } Block { BlockType Reference Name "Delay1" SID "8880" Ports [1, 1] Position [670, 468, 690, 492] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "20,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 24 24 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 20 20 0 0 ],[0 0 24 24 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[14.22 14.22 16." "22 14.22 16.22 16.22 16.22 14.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[12.22 12.22 14.22 14.22 12.22 ]" ",[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[10.22 10.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([7." "55 14.44 12.44 10.44 8.44 5.55 7.55 ],[8.22 8.22 10.22 8.22 10.22 10.22 8.22 ],[0.931 0.946 0.973 ]);\nfprintf(''," "'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-1}','texmode" "','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay2" SID "8881" Ports [1, 1] Position [670, 493, 690, 517] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "20,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 24 24 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 20 20 0 0 ],[0 0 24 24 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[14.22 14.22 16." "22 14.22 16.22 16.22 16.22 14.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[12.22 12.22 14.22 14.22 12.22 ]" ",[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[10.22 10.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([7." "55 14.44 12.44 10.44 8.44 5.55 7.55 ],[8.22 8.22 10.22 8.22 10.22 10.22 8.22 ],[0.931 0.946 0.973 ]);\nfprintf(''," "'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-1}','texmode" "','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay3" SID "8882" Ports [1, 1] Position [95, 479, 120, 501] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "25,22,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 22 22 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[14.33 14.33 " "17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[11.33 11.33 14.33 14.33 1" "1.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 1 1 ]);\npat" "ch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 0.973 ]);\nfprin" "tf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay4" SID "8883" Ports [1, 1] Position [670, 443, 690, 467] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "20,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 24 24 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 20 20 0 0 ],[0 0 24 24 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[14.22 14.22 16." "22 14.22 16.22 16.22 16.22 14.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[12.22 12.22 14.22 14.22 12.22 ]" ",[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[10.22 10.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([7." "55 14.44 12.44 10.44 8.44 5.55 7.55 ],[8.22 8.22 10.22 8.22 10.22 10.22 8.22 ],[0.931 0.946 0.973 ]);\nfprintf(''," "'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-1}','texmode" "','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out1" SID "8884" Ports [1, 1] Position [820, 89, 855, 101] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "Gateway Out10" SID "8885" Ports [1, 1] Position [890, 224, 925, 236] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "Gateway Out11" SID "8886" Ports [1, 1] Position [890, 179, 925, 191] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "Gateway Out2" SID "8887" Ports [1, 1] Position [930, 24, 965, 36] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Rate Sel" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "8888" Ports [1, 1] Position [930, 49, 965, 61] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Rd done" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "8889" Ports [1, 1] Position [930, 74, 965, 86] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Count En" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "8890" Ports [1, 1] Position [820, 104, 855, 116] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "Gateway Out6" SID "8891" Ports [1, 1] Position [890, 164, 925, 176] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "Gateway Out7" SID "9293" Ports [1, 1] Position [930, 124, 965, 136] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "SIG Sym" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "8892" Ports [1, 1] Position [930, 149, 965, 161] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Vout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out9" SID "8893" Ports [1, 1] Position [890, 209, 925, 221] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Scope Name "Int Rd Addr Gen" SID "8894" Ports [8] Position [1060, 13, 1095, 222] ZOrder -3 Floating off Location [1, 45, 2472, 1599] Open off NumInputPorts "8" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" } List { ListType ScopeGraphics FigureColor "[0.5 0.5 0.5]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "9000" YMin "-1~-1~-1~0~-0.1~-1~190~-0.1" YMax "1~1~1~1~1.1~1~217.5~1.1" SaveName "ScopeData12" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType Reference Name "Logical5" SID "8895" Ports [2, 1] Position [185, 498, 210, 522] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "25,24,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 24 24 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 24 24 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[15.33 15.33 " "18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[12.33 12.33 15.33 15.33 1" "2.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 1 1 ]);\npat" "ch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 0.973 ]);\nfprin" "tf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('or');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "S-R Latch1" SID "8896" Ports [2, 1] Position [260, 480, 295, 520] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "S-R Latch1" Location [351, 366, 2001, 1172] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "8897" Position [140, 103, 170, 117] IconDisplay "Port number" } Block { BlockType Inport Name "R" SID "8898" Position [140, 88, 170, 102] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "8899" Ports [0, 1] Position [195, 71, 210, 89] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "15,18,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11.22 " "13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 9.22 " "],[0.931 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([4.55 " "11.44 9.44 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "8900" Ports [1, 1] Position [210, 86, 235, 104] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('outpu" "t',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "8901" Ports [1, 1] Position [210, 101, 235, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('outpu" "t',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "8902" Ports [3, 1] Position [255, 71, 300, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "8903" Position [325, 88, 355, 102] IconDisplay "Port number" } Line { SrcBlock "Convert2" SrcPort 1 DstBlock "Register2" DstPort 3 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "S" SrcPort 1 DstBlock "Convert2" DstPort 1 } } } Block { BlockType Outport Name "Rd Addr A" SID "8904" Position [780, 398, 810, 412] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Outport Name "Rd Addr B" SID "8905" Position [780, 423, 810, 437] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "Skip A" SID "8906" Position [880, 448, 910, 462] NamePlacement "alternate" Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "Skip B" SID "8907" Position [880, 473, 910, 487] Port "4" IconDisplay "Port number" } Block { BlockType Outport Name "Vout" SID "8908" Position [780, 498, 810, 512] Port "5" IconDisplay "Port number" } Line { SrcBlock "Ctrl" SrcPort 5 DstBlock "Delay2" DstPort 1 } Line { Name "Count En" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 DstBlock "Int Rd Addr Gen" DstPort 3 } Line { Name "Rd done" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 DstBlock "Int Rd Addr Gen" DstPort 2 } Line { Name "Rate Sel" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 DstBlock "Int Rd Addr Gen" DstPort 1 } Line { Name "Vout" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 DstBlock "Int Rd Addr Gen" DstPort 6 } Line { SrcBlock "Logical5" SrcPort 1 Points [20, 0] Branch { DstBlock "S-R Latch1" DstPort 2 } Branch { Labels [0, 0] Points [0, -40] DstBlock "Ctrl" DstPort 3 } } Line { SrcBlock "Block Wr Done" SrcPort 1 DstBlock "Delay3" DstPort 1 } Line { SrcBlock "S-R Latch1" SrcPort 1 Points [10, 0] Branch { DstBlock "Ctrl" DstPort 4 } Branch { Points [0, -420] DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "Reset" SrcPort 1 DstBlock "Logical5" DstPort 2 } Line { SrcBlock "Delay4" SrcPort 1 Points [135, 0] Branch { Points [0, -240] DstBlock "Gateway Out9" DstPort 1 } Branch { DstBlock "Skip A" DstPort 1 } } Line { SrcBlock "Delay3" SrcPort 1 DstBlock "S-R Latch1" DstPort 1 } Line { SrcBlock "Ctrl" SrcPort 6 Points [40, 0] Branch { Points [0, 20; -405, 0; 0, -45] DstBlock "Logical5" DstPort 1 } Branch { Points [0, -475] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "Delay1" SrcPort 1 Points [140, 0] Branch { Points [0, -250] DstBlock "Gateway Out10" DstPort 1 } Branch { DstBlock "Skip B" DstPort 1 } } Line { SrcBlock "De-Interleave\nDP-ROM" SrcPort 1 Points [40, 0] Branch { DstBlock "Rd Addr A" DstPort 1 } Branch { Points [0, -235] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "De-Interleave\nDP-ROM" SrcPort 2 Points [45, 0] Branch { DstBlock "Rd Addr B" DstPort 1 } Branch { Points [0, -245] DstBlock "Gateway Out11" DstPort 1 } } Line { Name "Rd Addr AB" Labels [0, 0] SrcBlock "Bus\nCreator1" SrcPort 1 DstBlock "Int Rd Addr Gen" DstPort 7 } Line { SrcBlock "Gateway Out6" SrcPort 1 DstBlock "Bus\nCreator1" DstPort 1 } Line { SrcBlock "Gateway Out11" SrcPort 1 DstBlock "Bus\nCreator1" DstPort 2 } Line { Labels [0, 0] SrcBlock "mod_sel" SrcPort 1 DstBlock "Ctrl" DstPort 1 } Line { Labels [0, 0] SrcBlock "rate_sel" SrcPort 1 Points [45, 0] Branch { DstBlock "Ctrl" DstPort 2 } Branch { Points [0, -410] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "Ctrl" SrcPort 1 Points [65, 0] Branch { DstBlock "De-Interleave\nDP-ROM" DstPort 1 } Branch { Points [0, -310] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "Ctrl" SrcPort 2 Points [75, 0] Branch { DstBlock "De-Interleave\nDP-ROM" DstPort 2 } Branch { Points [0, -320] DstBlock "Gateway Out5" DstPort 1 } } Line { SrcBlock "Ctrl" SrcPort 3 DstBlock "Delay4" DstPort 1 } Line { SrcBlock "Ctrl" SrcPort 4 DstBlock "Delay1" DstPort 1 } Line { SrcBlock "Delay2" SrcPort 1 Points [45, 0] Branch { DstBlock "Vout" DstPort 1 } Branch { Points [0, -350] DstBlock "Gateway Out8" DstPort 1 } } Line { SrcBlock "Gateway Out9" SrcPort 1 DstBlock "Bus\nCreator" DstPort 1 } Line { SrcBlock "Gateway Out10" SrcPort 1 DstBlock "Bus\nCreator" DstPort 2 } Line { Name "Skip AB" Labels [0, 0] SrcBlock "Bus\nCreator" SrcPort 1 Points [40, 0; 0, -20] DstBlock "Int Rd Addr Gen" DstPort 8 } Line { Name "Rd Ind AB" Labels [0, 0] SrcBlock "Bus\nCreator2" SrcPort 1 DstBlock "Int Rd Addr Gen" DstPort 4 } Line { SrcBlock "Gateway Out1" SrcPort 1 DstBlock "Bus\nCreator2" DstPort 1 } Line { SrcBlock "Gateway Out5" SrcPort 1 DstBlock "Bus\nCreator2" DstPort 2 } Line { SrcBlock "SIGNAL sym" SrcPort 1 Points [270, 0; 0, -140] Branch { DstBlock "Ctrl" DstPort 5 } Branch { Points [0, -400] DstBlock "Gateway Out7" DstPort 1 } } Line { Name "SIG Sym" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 DstBlock "Int Rd Addr Gen" DstPort 5 } Annotation { Name "This is a brute force de-interleaver- the ROM stores the\nde-interleaving pattern for each mod scheme se" "parately.\nThe 802.11 standard interleavers have enough structure that\na non-ROM implementation is possible. But " "this design will\nenable other interleaving patterns without changes to logic." Position [712, 630] } } } Block { BlockType Reference Name "Register" SID "9294" Ports [3, 1] Position [555, 380, 585, 410] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,30,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 30 30 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 30 30 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 " "19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 1" "9.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'en');\n" "color('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT:" " end icon text');" } Block { BlockType SubSystem Name "Write Addr Gen" SID "8909" Ports [3, 3] Position [645, 222, 800, 358] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Write Addr Gen" Location [-1678, 227, -2, 1187] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "tvalid" SID "8910" Position [605, 478, 635, 492] IconDisplay "Port number" } Block { BlockType Inport Name "SIGNAL Sym" SID "8911" Position [585, 713, 615, 727] ZOrder -1 NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "Reset" SID "8912" Position [375, 438, 405, 452] NamePlacement "alternate" Port "3" IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "9282" Ports [0, 1] Position [705, 757, 735, 773] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "51" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "ceil(log2(MAX_NUM_SC))" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,16,0,1,white,blue,0,b654bd3a,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 16 16 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 16 16 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[10.22 10.22" " 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[8.22 8.22 10.22 10.22 8" ".22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatch" "([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1" ",'51');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant10" SID "8914" Ports [0, 1] Position [705, 792, 735, 808] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "47" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "ceil(log2(MAX_NUM_SC))" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,16,0,1,white,blue,0,625dc73c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 16 16 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 16 16 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[10.22 10.22" " 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[8.22 8.22 10.22 10.22 8" ".22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatch" "([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1" ",'47');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Counter" SID "8916" Ports [2, 1] Position [705, 440, 765, 500] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited counter i" "s implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "1" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "ceil(log2(MAX_NUM_SC))" bin_pt "0" load_pin off rst on en on explicit_period "off" period "1" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "counter" sg_icon_stat "60,60,2,1,white,blue,0,ae3608d6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 60 60 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[38.88 38.88 46" ".88 38.88 46.88 46.88 46.88 38.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[30.88 30.88 38.88 38.88 30.88" " ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[22.88 22.88 30.88 30.88 22.88 ],[1 1 1 ]);\npatch(" "[20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[14.88 14.88 22.88 14.88 22.88 22.88 14.88 ],[0.931 0.946 0.973 ]);\nfpr" "intf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'" ",1,'rst');\ncolor('black');port_label('input',2,'en');\n\ncolor('black');disp('{\\fontsize{14}\\bf++}','texmode','" "on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Scope Name "DeInt Wr Addr" SID "8917" Ports [8] Position [1310, 93, 1345, 302] ZOrder -3 Floating off Location [258, 580, 2412, 1557] Open off NumInputPorts "8" ZoomMode "yonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" } List { ListType ScopeGraphics FigureColor "[0.5 0.5 0.5]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "20000" YMin "0~-0.1~0~0~0~-1~-1~-1" YMax "1~1.1~100~1~1~1~1~1" SaveName "ScopeData6" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType Reference Name "Delay" SID "8918" Ports [1, 1] Position [695, 613, 720, 637] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "25,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 24 24 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 24 24 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[15.33 15.33 " "18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[12.33 12.33 15.33 15.33 1" "2.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 1 1 ]);\npat" "ch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 0.973 ]);\nfprin" "tf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From1" SID "9279" Position [360, 728, 525, 752] ZOrder -9 ShowName off GotoTag "RX_PHY_MODE_11N_AC" TagVisibility "global" } Block { BlockType Reference Name "Gateway Out1" SID "8920" Ports [1, 1] Position [1150, 204, 1185, 216] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Wr En" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "8921" Ports [1, 1] Position [1150, 104, 1185, 116] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Reset" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "8922" Ports [1, 1] Position [1150, 129, 1185, 141] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Valid In" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "8923" Ports [1, 1] Position [1150, 154, 1185, 166] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Wr Addr A" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "8924" Ports [1, 1] Position [1150, 229, 1185, 241] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Block Done" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Inverter" SID "9281" Ports [1, 1] Position [585, 731, 615, 749] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "30,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 18 18 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[11.22 11.22" " 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[9.22 9.22 11.22 11.22 9" ".22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch" "([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfpr" "intf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "8925" Ports [2, 1] Position [770, 596, 810, 634] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,38,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 38 38 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 38 38 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[24.55 24.55 29." "55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[19.55 19.55 24.55 24.55 19." "55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1 1 ]);\npa" "tch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('and')" ";\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "9280" Ports [2, 1] Position [700, 711, 740, 749] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,38,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 38 38 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 38 38 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[24.55 24.55 29." "55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[19.55 19.55 24.55 24.55 19." "55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1 1 ]);\npa" "tch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('or');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical5" SID "8926" Ports [2, 1] Position [540, 436, 580, 474] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,38,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 38 38 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 38 38 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[24.55 24.55 29." "55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[19.55 19.55 24.55 24.55 19." "55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1 1 ]);\npa" "tch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('or');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux4" SID "8927" Ports [3, 1] Position [830, 713, 865, 817] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "35,104,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 14.8571 89.1429 104 0 ],[0" ".77 0.82 0.91 ]);\nplot([0 35 35 0 0 ],[0 14.8571 89.1429 104 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 " "5.875 ],[57.55 57.55 62.55 57.55 62.55 62.55 62.55 57.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[52." "55 52.55 57.55 57.55 52.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[47.55 47.55 52.55 52.5" "5 47.55 ],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[42.55 42.55 47.55 42.55 47.55 47.55 42.55 " "],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolo" "r('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('in" "put',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational1" SID "8928" Ports [2, 1] Position [715, 535, 750, 570] BlockMirror on NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a>=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,35,2,1,white,blue,0,6218dc92,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 35 35 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 35 35 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[22.55 22.55 27." "55 22.55 27.55 27.55 27.55 22.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[17.55 17.55 22.55 22.55 17." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[12.55 12.55 17.55 17.55 12.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[7.55 7.55 12.55 7.55 12.55 12.55 7.55 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input" "',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa \\geq b','texmod" "e','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Wr Addr A" SID "8929" Position [1010, 463, 1040, 477] IconDisplay "Port number" } Block { BlockType Outport Name "Wr En" SID "8930" Position [1010, 513, 1040, 527] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "Block Wr Done" SID "8931" Position [1010, 608, 1040, 622] Port "3" IconDisplay "Port number" } Line { SrcBlock "Logical5" SrcPort 1 Points [30, 0] Branch { DstBlock "Counter" DstPort 1 } Branch { Points [0, -345] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "Counter" SrcPort 1 Points [20, 0] Branch { Points [0, 75] DstBlock "Relational1" DstPort 1 } Branch { Points [180, 0] Branch { DstBlock "Wr Addr A" DstPort 1 } Branch { Points [0, -310] DstBlock "Gateway Out4" DstPort 1 } } } Line { SrcBlock "tvalid" SrcPort 1 Points [30, 0] Branch { DstBlock "Counter" DstPort 2 } Branch { Points [0, -350] DstBlock "Gateway Out3" DstPort 1 } Branch { Points [0, 35] Branch { Points [0, 0; 130, 0] Branch { DstBlock "Wr En" DstPort 1 } Branch { Points [0, -310] DstBlock "Gateway Out1" DstPort 1 } } Branch { Points [0, 105] DstBlock "Delay" DstPort 1 } } } Line { SrcBlock "Relational1" SrcPort 1 Points [-30, 0] Branch { Points [-170, 0; 0, -90] DstBlock "Logical5" DstPort 2 } Branch { Points [0, 50] DstBlock "Logical1" DstPort 1 } } Line { SrcBlock "Reset" SrcPort 1 DstBlock "Logical5" DstPort 1 } Line { Name "Reset" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 DstBlock "DeInt Wr Addr" DstPort 1 } Line { Name "Valid In" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 DstBlock "DeInt Wr Addr" DstPort 2 } Line { Name "Wr Addr A" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 DstBlock "DeInt Wr Addr" DstPort 3 } Line { Name "Wr En" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 DstBlock "DeInt Wr Addr" DstPort 5 } Line { Name "Block Done" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 DstBlock "DeInt Wr Addr" DstPort 6 } Line { SrcBlock "Mux4" SrcPort 1 Points [15, 0; 0, -205] DstBlock "Relational1" DstPort 2 } Line { SrcBlock "Logical2" SrcPort 1 DstBlock "Mux4" DstPort 1 } Line { SrcBlock "Constant10" SrcPort 1 DstBlock "Mux4" DstPort 3 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Mux4" DstPort 2 } Line { SrcBlock "Logical1" SrcPort 1 Points [170, 0] Branch { DstBlock "Block Wr Done" DstPort 1 } Branch { Points [0, -380] DstBlock "Gateway Out5" DstPort 1 } } Line { SrcBlock "Delay" SrcPort 1 DstBlock "Logical1" DstPort 2 } Line { SrcBlock "SIGNAL Sym" SrcPort 1 DstBlock "Logical2" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical2" DstPort 2 } Line { SrcBlock "From1" SrcPort 1 DstBlock "Inverter" DstPort 1 } Annotation { Name "SIGNAL symbols are always 48-subcarrier BPSK 1/2. N_CBPS\nfor post-SIGNAL symbols depends on decoded RAT" "E/MCS values.\n\"From\" tag here comes from SIGNAL Decode (11a) or\nHT-SIG Decode (11n) blocks post-decoder." Position [650, 948] HorizontalAlignment "left" } } } Block { BlockType Reference Name "b0" SID "8932" Ports [1, 1] Position [450, 279, 485, 301] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "35,22,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 22 22 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 22 22 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ]" ",[14.33 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[11.3" "3 11.33 14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[8.33 8.33 11.33 " "11.33 8.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\n\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name " LLR A" SID "8933" Position [1315, 198, 1345, 212] IconDisplay "Port number" } Block { BlockType Outport Name " LLR B" SID "8934" Position [1315, 338, 1345, 352] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name " tvalid" SID "8935" Position [1315, 478, 1345, 492] Port "3" IconDisplay "Port number" } Line { SrcBlock "Demod cfg" SrcPort 1 DstBlock "b0" DstPort 1 } Line { SrcBlock "LLR Valid" SrcPort 1 DstBlock "Write Addr Gen" DstPort 1 } Line { SrcBlock "Reset" SrcPort 1 Points [15, 0] Branch { Points [90, 0] Branch { DstBlock "Write Addr Gen" DstPort 3 } Branch { Points [0, 160] DstBlock "Read Addr Gen" DstPort 5 } Branch { Points [0, -170] DstBlock "Mem Sel" DstPort 1 } } Branch { Points [0, 60] DstBlock "Register" DstPort 2 } } Line { SrcBlock "b0" SrcPort 1 Points [20, 0] Branch { DstBlock "Write Addr Gen" DstPort 2 } Branch { Points [0, 95] DstBlock "Register" DstPort 1 } } Line { SrcBlock "Write Addr Gen" SrcPort 3 Points [50, 0] Branch { Points [0, -145] DstBlock "Mem Sel" DstPort 2 } Branch { Points [0, 40; -235, 0] Branch { Points [0, 20] DstBlock "Read Addr Gen" DstPort 1 } Branch { Points [-125, 0; 0, 30] DstBlock "Register" DstPort 3 } } } Line { SrcBlock "mod_sel" SrcPort 1 DstBlock "Read Addr Gen" DstPort 2 } Line { SrcBlock "From5" SrcPort 1 DstBlock "Read Addr Gen" DstPort 4 } Line { SrcBlock "Mem Sel" SrcPort 1 DstBlock "RAMs" DstPort 1 } Line { SrcBlock "Mem Sel" SrcPort 2 Points [35, 0; 0, 15] DstBlock "RAMs" DstPort 2 } Line { SrcBlock "Write Addr Gen" SrcPort 1 DstBlock "RAMs" DstPort 3 } Line { SrcBlock "Write Addr Gen" SrcPort 2 Points [310, 0] DstBlock "RAMs" DstPort 4 } Line { SrcBlock "Read Addr Gen" SrcPort 1 Points [110, 0; 0, -70] DstBlock "RAMs" DstPort 5 } Line { SrcBlock "Read Addr Gen" SrcPort 2 Points [135, 0; 0, -55] DstBlock "RAMs" DstPort 6 } Line { SrcBlock "Read Addr Gen" SrcPort 3 Points [160, 0; 0, -40] DstBlock "RAMs" DstPort 7 } Line { SrcBlock "Read Addr Gen" SrcPort 4 Points [185, 0; 0, -25] DstBlock "RAMs" DstPort 8 } Line { SrcBlock "Read Addr Gen" SrcPort 5 Points [310, 0] DstBlock "RAMs" DstPort 9 } Line { SrcBlock "LLR Vec" SrcPort 1 Points [535, 0; 0, -45] DstBlock "RAMs" DstPort 10 } Line { SrcBlock "RAMs" SrcPort 1 DstBlock " LLR A" DstPort 1 } Line { SrcBlock "RAMs" SrcPort 2 DstBlock " LLR B" DstPort 1 } Line { SrcBlock "RAMs" SrcPort 3 DstBlock " tvalid" DstPort 1 } Line { SrcBlock "Register" SrcPort 1 Points [15, 0; 0, 50] DstBlock "Read Addr Gen" DstPort 3 } } } Block { BlockType SubSystem Name "Decode" SID "1846" Ports [5, 5] Position [935, 54, 1035, 216] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Decode" Location [2, 74, 2464, 1576] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "LLR A" SID "1847" Position [75, 498, 105, 512] IconDisplay "Port number" } Block { BlockType Inport Name "LLR B" SID "1848" Position [75, 533, 105, 547] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "Vin" SID "1849" Position [75, 568, 105, 582] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "Start" SID "1850" Position [75, 658, 105, 672] Port "4" IconDisplay "Port number" } Block { BlockType Inport Name "Reset" SID "1851" Position [75, 613, 105, 627] Port "5" IconDisplay "Port number" } Block { BlockType Reference Name "Assert" SID "9267" Ports [1, 1] Position [175, 496, 205, 514] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Assert" SourceType "Xilinx Assert Block" infoedit "Asserts a user-defined sample rate and/or type on a signal.

Hardware notes: In hardware" " this block costs nothing." assert_type off type_source "Explicitly" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "16" bin_pt "14" preci_type "Single" exp_width "8" frac_width "24" assert_rate on rate_source "Explicitly" period "1" output_port on has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "assert" sg_icon_stat "30,18,1,1,white,blue,0,9657e937,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 18 18 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[1" "1.22 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[9.22 9.22 " "11.22 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[7.22 7.22 9.22 9.22 7.22 ],[" "1 1 1 ]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('bla" "ck');disp('Assert');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Assert1" SID "9268" Ports [1, 1] Position [175, 531, 205, 549] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Assert" SourceType "Xilinx Assert Block" infoedit "Asserts a user-defined sample rate and/or type on a signal.

Hardware notes: In hardware" " this block costs nothing." assert_type off type_source "Explicitly" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "16" bin_pt "14" preci_type "Single" exp_width "8" frac_width "24" assert_rate on rate_source "Explicitly" period "1" output_port on has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "assert" sg_icon_stat "30,18,1,1,white,blue,0,9657e937,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 18 18 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[1" "1.22 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[9.22 9.22 " "11.22 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[7.22 7.22 9.22 9.22 7.22 ],[" "1 1 1 ]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('bla" "ck');disp('Assert');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Assert11" SID "1852" Ports [1, 1] Position [1680, 938, 1715, 952] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Assert" SourceType "Xilinx Assert Block" infoedit "Asserts a user-defined sample rate and/or type on a signal.

Hardware notes: In hardware" " this block costs nothing." assert_type off type_source "Explicitly" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "16" bin_pt "14" preci_type "Single" exp_width "8" frac_width "24" assert_rate on rate_source "Explicitly" period "1" output_port on has_advanced_control "0" sggui_pos "20,20,356,423" block_type "assert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,14,1,1,white,blue,0,9657e937,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 14 14 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 14 14 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[9" ".22 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[7.22 7.22 9.22" " 9.22 7.22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 " "]);\npatch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');d" "isp('Assert');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Assert2" SID "9269" Ports [1, 1] Position [175, 566, 205, 584] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Assert" SourceType "Xilinx Assert Block" infoedit "Asserts a user-defined sample rate and/or type on a signal.

Hardware notes: In hardware" " this block costs nothing." assert_type off type_source "Explicitly" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "16" bin_pt "14" preci_type "Single" exp_width "8" frac_width "24" assert_rate on rate_source "Explicitly" period "1" output_port on has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "assert" sg_icon_stat "30,18,1,1,white,blue,0,9657e937,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 18 18 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[1" "1.22 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[9.22 9.22 " "11.22 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[7.22 7.22 9.22 9.22 7.22 ],[" "1 1 1 ]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('bla" "ck');disp('Assert');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Assert3" SID "9270" Ports [1, 1] Position [175, 611, 205, 629] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Assert" SourceType "Xilinx Assert Block" infoedit "Asserts a user-defined sample rate and/or type on a signal.

Hardware notes: In hardware" " this block costs nothing." assert_type off type_source "Explicitly" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "16" bin_pt "14" preci_type "Single" exp_width "8" frac_width "24" assert_rate on rate_source "Explicitly" period "1" output_port on has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "assert" sg_icon_stat "30,18,1,1,white,blue,0,9657e937,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 18 18 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[1" "1.22 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[9.22 9.22 " "11.22 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[7.22 7.22 9.22 9.22 7.22 ],[" "1 1 1 ]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('bla" "ck');disp('Assert');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Assert4" SID "9271" Ports [1, 1] Position [175, 656, 205, 674] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Assert" SourceType "Xilinx Assert Block" infoedit "Asserts a user-defined sample rate and/or type on a signal.

Hardware notes: In hardware" " this block costs nothing." assert_type off type_source "Explicitly" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "16" bin_pt "14" preci_type "Single" exp_width "8" frac_width "24" assert_rate on rate_source "Explicitly" period "1" output_port on has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "assert" sg_icon_stat "30,18,1,1,white,blue,0,9657e937,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 18 18 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[1" "1.22 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[9.22 9.22 " "11.22 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[7.22 7.22 9.22 9.22 7.22 ],[" "1 1 1 ]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('bla" "ck');disp('Assert');\nfprintf('','COMMENT: end icon text');" } Block { BlockType BusCreator Name "Bus Creator" SID "18104" Ports [2, 1] Position [295, 161, 300, 199] ZOrder -2 ShowName off Inputs "2" DisplayOption "bar" } Block { BlockType SubSystem Name "Byte Count" SID "1853" Ports [3, 3] Position [1005, 783, 1115, 847] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Byte Count" Location [966, 749, 1176, 841] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Byte Valid" SID "1854" Position [250, 463, 280, 477] IconDisplay "Port number" } Block { BlockType Inport Name "Decode Start" SID "1855" Position [250, 393, 280, 407] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "Last Byte Ind" SID "1856" Position [250, 543, 280, 557] Port "3" IconDisplay "Port number" } Block { BlockType Reference Name "Byte\nCounter" SID "1857" Ports [2, 1] Position [615, 413, 655, 482] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited counter i" "s implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "1" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "ceil(log2(MAX_NUM_BYTES))" bin_pt "0" load_pin off rst on en on explicit_period "off" period "1" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "counter" sg_icon_stat "40,69,2,1,white,blue,0,ae3608d6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 69 69 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 69 69 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[39.55 39.55 44." "55 39.55 44.55 44.55 44.55 39.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[34.55 34.55 39.55 39.55 34." "55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[29.55 29.55 34.55 34.55 29.55 ],[1 1 1 ]);\npa" "tch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[24.55 24.55 29.55 24.55 29.55 29.55 24.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i" "nput',1,'rst');\ncolor('black');port_label('input',2,'en');\n\ncolor('black');disp('{\\fontsize{14}\\bf++}','texmo" "de','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter1" SID "1858" Ports [1, 1] Position [450, 426, 480, 444] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "30,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 18 18 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[11.22 11.22" " 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[9.22 9.22 11.22 11.22 9" ".22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch" "([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfpr" "intf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical" SID "1859" Ports [2, 1] Position [445, 447, 485, 478] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,31,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 31 31 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 31 31 0 ]);\npatch([11.1 16.88 20.88 24.88 28.88 20.88 15.1 11.1 ],[19.44 19.44 23" ".44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([15.1 20.88 16.88 11.1 15.1 ],[15.44 15.44 19.44 19.44 15.44" " ],[0.931 0.946 0.973 ]);\npatch([11.1 16.88 20.88 15.1 11.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch(" "[15.1 28.88 24.88 20.88 16.88 11.1 15.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf" "('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('and');\nfp" "rintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "1860" Ports [2, 1] Position [530, 412, 570, 443] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,31,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 31 31 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 31 31 0 ]);\npatch([11.1 16.88 20.88 24.88 28.88 20.88 15.1 11.1 ],[19.44 19.44 23" ".44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([15.1 20.88 16.88 11.1 15.1 ],[15.44 15.44 19.44 19.44 15.44" " ],[0.931 0.946 0.973 ]);\npatch([11.1 16.88 20.88 15.1 11.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch(" "[15.1 28.88 24.88 20.88 16.88 11.1 15.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf" "('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('or');\nfpr" "intf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical3" SID "1861" Ports [2, 1] Position [865, 501, 890, 554] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "25,53,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 53 53 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 53 53 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[29.33 29.33 " "32.33 29.33 32.33 32.33 32.33 29.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[26.33 26.33 29.33 29.33 2" "6.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[23.33 23.33 26.33 26.33 23.33 ],[1 1 1 ]);\n" "patch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[20.33 20.33 23.33 20.33 23.33 23.33 20.33 ],[0.931 0.946 0.973 " "]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp" "('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational2" SID "1862" Ports [2, 1] Position [740, 521, 785, 559] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a>=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "45,38,2,1,white,blue,0,6218dc92,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 38 38 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 38 38 0 ]);\npatch([10.875 18.1 23.1 28.1 33.1 23.1 15.875 10.875 ],[24.55 24.55 2" "9.55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([15.875 23.1 18.1 10.875 15.875 ],[19.55 19.55 24.55 24.55 " "19.55 ],[0.931 0.946 0.973 ]);\npatch([10.875 18.1 23.1 15.875 10.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1 1 ])" ";\npatch([15.875 33.1 28.1 23.1 18.1 10.875 15.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0.973 ]" ");\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label(" "'input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa \\geq b','" "texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "S-R Latch1" SID "1863" Ports [2, 1] Position [345, 393, 380, 422] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "S-R Latch1" Location [351, 366, 2001, 1172] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "1864" Position [140, 103, 170, 117] IconDisplay "Port number" } Block { BlockType Inport Name "R" SID "1865" Position [140, 88, 170, 102] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "1866" Ports [0, 1] Position [195, 71, 210, 89] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "15,18,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11.22 " "13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 9.22 " "],[0.931 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([4.55 " "11.44 9.44 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "1867" Ports [1, 1] Position [210, 86, 235, 104] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('outpu" "t',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "1868" Ports [1, 1] Position [210, 101, 235, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('outpu" "t',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "1869" Ports [3, 1] Position [255, 71, 300, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "1870" Position [325, 88, 355, 102] IconDisplay "Port number" } Line { SrcBlock "Convert2" SrcPort 1 DstBlock "Register2" DstPort 3 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "S" SrcPort 1 DstBlock "Convert2" DstPort 1 } } } Block { BlockType Outport Name " Byte Valid" SID "1871" Position [1110, 643, 1140, 657] IconDisplay "Port number" } Block { BlockType Outport Name "Byte Index" SID "1872" Position [765, 443, 795, 457] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "Last Byte" SID "1873" Position [1045, 523, 1075, 537] Port "3" IconDisplay "Port number" } Line { SrcBlock "Logical" SrcPort 1 Points [25, 0] Branch { DstBlock "Byte\nCounter" DstPort 2 } Branch { Points [0, 185] DstBlock " Byte Valid" DstPort 1 } } Line { SrcBlock "Byte\nCounter" SrcPort 1 Points [40, 0] Branch { DstBlock "Byte Index" DstPort 1 } Branch { Points [0, 80] DstBlock "Relational2" DstPort 1 } } Line { SrcBlock "Logical3" SrcPort 1 Points [80, 0] Branch { Points [0, -180; -690, 0; 0, 65] DstBlock "S-R Latch1" DstPort 2 } Branch { DstBlock "Last Byte" DstPort 1 } } Line { SrcBlock "Decode Start" SrcPort 1 Points [35, 0] Branch { DstBlock "S-R Latch1" DstPort 1 } Branch { Points [0, -20; 195, 0] DstBlock "Logical1" DstPort 1 } } Line { SrcBlock "S-R Latch1" SrcPort 1 Points [20, 0; 0, 25] Branch { Points [0, 20] DstBlock "Logical" DstPort 1 } Branch { DstBlock "Inverter1" DstPort 1 } } Line { SrcBlock "Byte Valid" SrcPort 1 Points [105, 0] Branch { DstBlock "Logical" DstPort 2 } Branch { Points [0, 45] DstBlock "Logical3" DstPort 1 } } Line { SrcBlock "Relational2" SrcPort 1 DstBlock "Logical3" DstPort 2 } Line { SrcBlock "Last Byte Ind" SrcPort 1 DstBlock "Relational2" DstPort 2 } Line { SrcBlock "Inverter1" SrcPort 1 DstBlock "Logical1" DstPort 2 } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Byte\nCounter" DstPort 1 } } } Block { BlockType SubSystem Name "Control" SID "1874" Ports [5, 6] Position [350, 551, 485, 774] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Control" Location [371, 718, 769, 868] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "124" Block { BlockType Inport Name "dec_vin" SID "1875" Position [155, 748, 185, 762] IconDisplay "Port number" } Block { BlockType Inport Name "Reset" SID "1876" Position [190, 373, 220, 387] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "Start" SID "1877" Position [175, 538, 205, 552] NamePlacement "alternate" Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "Num Bytes" SID "1878" Position [230, 598, 260, 612] Port "4" IconDisplay "Port number" } Block { BlockType Inport Name "dec_vout" SID "1879" Position [570, 488, 600, 502] Port "5" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub" SID "1880" Ports [2, 1] Position [530, 748, 570, 777] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL off hw_selection "Fabric" pipelined off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" sg_icon_stat "40,29,2,1,white,blue,0,e139daf6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 29 29 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 29 29 0 ]);\npatch([11.1 16.88 20.88 24.88 28.88 20.88 15.1 11.1 ],[18.44 18.44 22" ".44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([15.1 20.88 16.88 11.1 15.1 ],[14.44 14.44 18.44 18.44 14.44" " ],[0.931 0.946 0.973 ]);\npatch([11.1 16.88 20.88 15.1 11.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\npatch(" "[15.1 28.88 24.88 20.88 16.88 11.1 15.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nfprintf" "('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bf{a + b}','texmode','on'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Coded Bit\nCounter" SID "1881" Ports [2, 1] Position [415, 534, 470, 576] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited counter i" "s implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "1" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "3+ceil(log2(MAX_NUM_BYTES))" bin_pt "0" load_pin off rst on en on explicit_period "off" period "1" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "counter" sg_icon_stat "55,42,2,1,white,blue,0,ae3608d6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 42 42 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 55 55 0 0 ],[0 0 42 42 0 ]);\npatch([13.65 22.32 28.32 34.32 40.32 28.32 19.65 13.65 ],[27.66 27.66" " 33.66 27.66 33.66 33.66 33.66 27.66 ],[1 1 1 ]);\npatch([19.65 28.32 22.32 13.65 19.65 ],[21.66 21.66 27.66 27.66" " 21.66 ],[0.931 0.946 0.973 ]);\npatch([13.65 22.32 28.32 19.65 13.65 ],[15.66 15.66 21.66 21.66 15.66 ],[1 1 1 ])" ";\npatch([19.65 40.32 34.32 28.32 22.32 13.65 19.65 ],[9.66 9.66 15.66 9.66 15.66 15.66 9.66 ],[0.931 0.946 0.973 " "]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label" "('input',1,'rst');\ncolor('black');port_label('input',2,'en');\n\ncolor('black');disp('{\\fontsize{14}\\bf++}','te" "xmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Concat" SID "1882" Ports [2, 1] Position [415, 594, 470, 641] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point at z" "ero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "55,47,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 47 47 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 55 55 0 0 ],[0 0 47 47 0 ]);\npatch([13.65 22.32 28.32 34.32 40.32 28.32 19.65 13.65 ],[29.66 29.66" " 35.66 29.66 35.66 35.66 35.66 29.66 ],[1 1 1 ]);\npatch([19.65 28.32 22.32 13.65 19.65 ],[23.66 23.66 29.66 29.66" " 23.66 ],[0.931 0.946 0.973 ]);\npatch([13.65 22.32 28.32 19.65 13.65 ],[17.66 17.66 23.66 23.66 17.66 ],[1 1 1 ])" ";\npatch([19.65 40.32 34.32 28.32 22.32 13.65 19.65 ],[11.66 11.66 17.66 11.66 17.66 17.66 11.66 ],[0.931 0.946 0." "973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fontsize{20}\\}','texm" "ode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant1" SID "1883" Ports [0, 1] Position [440, 762, 470, 778] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "14" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "5" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,16,0,1,white,blue,0,9e70b1fa,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 16 16 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 16 16 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[10.22 10.22" " 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[8.22 8.22 10.22 10.22 8" ".22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatch" "([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1" ",'14');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant2" SID "1884" Ports [0, 1] Position [340, 622, 370, 638] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,16,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 16 16 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 16 16 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[10.22 10.22" " 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[8.22 8.22 10.22 10.22 8" ".22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatch" "([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1" ",'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert" SID "1885" Ports [1, 1] Position [900, 383, 925, 397] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.22 11.2" "2 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0.931" " 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.55 16.44 14" ".44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end" " icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cast');\nfprin" "tf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "1886" Ports [1, 1] Position [875, 758, 900, 772] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.22 11.2" "2 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0.931" " 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.55 16.44 14" ".44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end" " icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cast');\nfprin" "tf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert7" SID "1887" Ports [1, 1] Position [900, 423, 925, 437] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.22 11.2" "2 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0.931" " 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.55 16.44 14" ".44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end" " icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cast');\nfprin" "tf('','COMMENT: end icon text');" } Block { BlockType Scope Name "Decoder Ctrl" SID "1888" Ports [8] Position [1325, 117, 1365, 293] ZOrder -3 Floating off Location [20, 123, 1700, 1127] Open off NumInputPorts "8" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" } List { ListType ScopeGraphics FigureColor "[0.5 0.5 0.5]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "10000" YMin "-1~-1~1998.8~0~11100~-1~-1~0" YMax "1~1~2209.2~1~11275~1~1~1" SaveName "ScopeData40" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType Reference Name "Delay1" SID "1889" Ports [1, 1] Position [800, 420, 830, 440] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "2" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "30,20,1,1,white,blue,0,85ce9542,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 20 20 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[12.22 12.22" " 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[10.22 10.22 12.22 12.22" " 10.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\n" "patch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-2}" "','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay2" SID "1890" Ports [1, 1] Position [875, 705, 905, 725] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "2" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "30,20,1,1,white,blue,0,85ce9542,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 20 20 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[12.22 12.22" " 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[10.22 10.22 12.22 12.22" " 10.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\n" "patch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-2}" "','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Early Trace Ctrl" SID "1891" Ports [3, 2] Position [715, 464, 810, 526] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Early Trace Ctrl" Location [1167, 962, 1586, 1169] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "124" Block { BlockType Inport Name "Byte Ind" SID "1892" Position [370, 228, 400, 242] IconDisplay "Port number" } Block { BlockType Inport Name "dec_vout" SID "1893" Position [530, 433, 560, 447] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "reset" SID "1894" Position [530, 468, 560, 482] Port "3" IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "1895" Ports [0, 1] Position [425, 312, 455, 328] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "9*8 - 2" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "7" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,16,0,1,white,blue,0,8c6adb57,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 16 16 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_la" "bel('output',1,'70');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant3" SID "1896" Ports [0, 1] Position [425, 207, 455, 223] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "3*8 - 2" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "5" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,16,0,1,white,blue,0,4438d68f,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 16 16 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_la" "bel('output',1,'22');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert" SID "1897" Ports [1, 1] Position [640, 430, 665, 450] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "16" bin_pt "14" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,20,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 20 20 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 20 20 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[12.22 12" ".22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[10.22 10.22 12.22 12." "22 10.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\n" "patch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('o" "utput',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "1898" Ports [1, 1] Position [640, 465, 665, 485] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "16" bin_pt "14" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,20,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 20 20 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 20 20 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[12.22 12" ".22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[10.22 10.22 12.22 12." "22 10.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\n" "patch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('o" "utput',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "1899" Position [200, 363, 365, 387] ZOrder -9 ShowName off GotoTag "RX_PHY_MODE_11N_AC" TagVisibility "global" } Block { BlockType Reference Name "Logical1" SID "1900" Ports [2, 1] Position [630, 298, 670, 347] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,49,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 49 49 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 49 49 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[29.55 29." "55 34.55 29.55 34.55 34.55 34.55 29.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[24.55 24.55 29.55 2" "9.55 24.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[19.55 19.55 24.55 24.55 19.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[14.55 14.55 19.55 14.55 19.55 19.55 14.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('b" "lack');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "1901" Ports [2, 1] Position [710, 420, 750, 495] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,75,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 75 75 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 75 75 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[42.55 42." "55 47.55 42.55 47.55 47.55 47.55 42.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[37.55 37.55 42.55 4" "2.55 37.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[32.55 32.55 37.55 37.55 32.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[27.55 27.55 32.55 27.55 32.55 32.55 27.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('b" "lack');disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational1" SID "1902" Ports [2, 1] Position [500, 291, 545, 329] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "45,38,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 38 38 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 38 38 0 ]);\npatch([10.875 18.1 23.1 28.1 33.1 23.1 15.875 10.875 ],[24.55 2" "4.55 29.55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([15.875 23.1 18.1 10.875 15.875 ],[19.55 19.55 24.5" "5 24.55 19.55 ],[0.931 0.946 0.973 ]);\npatch([10.875 18.1 23.1 15.875 10.875 ],[14.55 14.55 19.55 19.55 14.55 ]" ",[1 1 1 ]);\npatch([15.875 33.1 28.1 23.1 18.1 10.875 15.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'" "\\bfa = b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational3" SID "1903" Ports [2, 1] Position [500, 206, 545, 244] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "45,38,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 38 38 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 38 38 0 ]);\npatch([10.875 18.1 23.1 28.1 33.1 23.1 15.875 10.875 ],[24.55 2" "4.55 29.55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([15.875 23.1 18.1 10.875 15.875 ],[19.55 19.55 24.5" "5 24.55 19.55 ],[0.931 0.946 0.973 ]);\npatch([10.875 18.1 23.1 15.875 10.875 ],[14.55 14.55 19.55 19.55 14.55 ]" ",[1 1 1 ]);\npatch([15.875 33.1 28.1 23.1 18.1 10.875 15.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'" "\\bfa = b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "S-R Latch1" SID "1904" Ports [2, 1] Position [820, 218, 855, 247] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "S-R Latch1" Location [679, 186, 1980, 1508] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "1905" Position [140, 103, 170, 117] IconDisplay "Port number" } Block { BlockType Inport Name "R" SID "1906" Position [140, 88, 170, 102] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "1907" Ports [0, 1] Position [195, 71, 210, 89] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "15,18,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11.22 " "13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 9.22 " "],[0.931 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([4.55 " "11.44 9.44 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "1908" Ports [1, 1] Position [210, 86, 235, 104] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('outpu" "t',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "1909" Ports [1, 1] Position [210, 101, 235, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('outpu" "t',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "1910" Ports [3, 1] Position [255, 71, 300, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "1911" Position [325, 88, 355, 102] IconDisplay "Port number" } Line { SrcBlock "Convert2" SrcPort 1 DstBlock "Register2" DstPort 3 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "S" SrcPort 1 DstBlock "Convert2" DstPort 1 } } } Block { BlockType SubSystem Name "S-R Latch3" SID "1912" Ports [2, 1] Position [820, 318, 855, 347] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "S-R Latch3" Location [679, 186, 1980, 1508] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "1913" Position [140, 103, 170, 117] IconDisplay "Port number" } Block { BlockType Inport Name "R" SID "1914" Position [140, 88, 170, 102] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "1915" Ports [0, 1] Position [195, 71, 210, 89] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "15,18,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11.22 " "13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 9.22 " "],[0.931 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([4.55 " "11.44 9.44 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "1916" Ports [1, 1] Position [210, 86, 235, 104] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('outpu" "t',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "1917" Ports [1, 1] Position [210, 101, 235, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('outpu" "t',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "1918" Ports [3, 1] Position [255, 71, 300, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "1919" Position [325, 88, 355, 102] IconDisplay "Port number" } Line { SrcBlock "S" SrcPort 1 DstBlock "Convert2" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "Convert2" SrcPort 1 DstBlock "Register2" DstPort 3 } } } Block { BlockType SubSystem Name "posedge" SID "1920" Ports [1, 1] Position [710, 218, 755, 232] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "posedge" Location [214, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "1921" Position [215, 188, 245, 202] IconDisplay "Port number" } Block { BlockType Reference Name "Delay" SID "1922" Ports [1, 1] Position [425, 178, 460, 202] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. " "If register retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[15" ".33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.33 12." "33 15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 12.33 " "9.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\nc" "olor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "1923" Ports [1, 1] Position [490, 181, 515, 199] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "1924" Ports [2, 1] Position [540, 151, 585, 204] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,53,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 53 53 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 53 53 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[32.66 3" "2.66 38.66 32.66 38.66 38.66 38.66 32.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[26.66 26.66 32.66 " "32.66 26.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[20.66 20.66 26.66 26.66 20.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[14.66 14.66 20.66 14.66 20.66 20.66 14.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('" "black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "1925" Position [610, 173, 640, 187] IconDisplay "Port number" } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical1" DstPort 2 } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "D" SrcPort 1 Points [135, 0; 0, -5] Branch { DstBlock "Delay" DstPort 1 } Branch { Points [0, -25] DstBlock "Logical1" DstPort 1 } } Line { SrcBlock "Delay" SrcPort 1 DstBlock "Inverter" DstPort 1 } } } Block { BlockType SubSystem Name "posedge1" SID "1926" Ports [1, 1] Position [705, 318, 750, 332] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "posedge1" Location [214, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "1927" Position [215, 188, 245, 202] IconDisplay "Port number" } Block { BlockType Reference Name "Delay" SID "1928" Ports [1, 1] Position [425, 178, 460, 202] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. " "If register retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[15" ".33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.33 12." "33 15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 12.33 " "9.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\nc" "olor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "1929" Ports [1, 1] Position [490, 181, 515, 199] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "1930" Ports [2, 1] Position [540, 151, 585, 204] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,53,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 53 53 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 53 53 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[32.66 3" "2.66 38.66 32.66 38.66 38.66 38.66 32.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[26.66 26.66 32.66 " "32.66 26.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[20.66 20.66 26.66 26.66 20.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[14.66 14.66 20.66 14.66 20.66 20.66 14.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('" "black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "1931" Position [610, 173, 640, 187] IconDisplay "Port number" } Line { SrcBlock "Delay" SrcPort 1 DstBlock "Inverter" DstPort 1 } Line { SrcBlock "D" SrcPort 1 Points [135, 0; 0, -5] Branch { Points [0, -25] DstBlock "Logical1" DstPort 1 } Branch { DstBlock "Delay" DstPort 1 } } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical1" DstPort 2 } } } Block { BlockType Outport Name "Early Trace 1" SID "1932" Position [960, 228, 990, 242] IconDisplay "Port number" } Block { BlockType Outport Name "Early Trace 2" SID "1933" Position [960, 328, 990, 342] Port "2" IconDisplay "Port number" } Line { SrcBlock "Constant3" SrcPort 1 DstBlock "Relational3" DstPort 1 } Line { SrcBlock "Byte Ind" SrcPort 1 Points [65, 0] Branch { DstBlock "Relational3" DstPort 2 } Branch { Points [0, 65] DstBlock "Relational1" DstPort 1 } } Line { SrcBlock "Relational3" SrcPort 1 DstBlock "posedge" DstPort 1 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Relational1" DstPort 2 } Line { SrcBlock "Relational1" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "From" SrcPort 1 Points [225, 0; 0, -40] DstBlock "Logical1" DstPort 2 } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "posedge1" DstPort 1 } Line { SrcBlock "posedge" SrcPort 1 DstBlock "S-R Latch1" DstPort 1 } Line { SrcBlock "posedge1" SrcPort 1 DstBlock "S-R Latch3" DstPort 1 } Line { SrcBlock "dec_vout" SrcPort 1 DstBlock "Convert" DstPort 1 } Line { SrcBlock "reset" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Logical2" SrcPort 1 Points [30, 0; 0, -120] Branch { Points [0, -100] DstBlock "S-R Latch1" DstPort 2 } Branch { DstBlock "S-R Latch3" DstPort 2 } } Line { SrcBlock "S-R Latch1" SrcPort 1 DstBlock "Early Trace 1" DstPort 1 } Line { SrcBlock "S-R Latch3" SrcPort 1 DstBlock "Early Trace 2" DstPort 1 } Line { SrcBlock "Convert" SrcPort 1 DstBlock "Logical2" DstPort 1 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Logical2" DstPort 2 } Annotation { Name "22: (NUM_SIGNAL_BYTES * 8) - 2" Position [253, 204] } Annotation { Name "70: ((NUM_SIGNAL_BYTES + NUM_HT_SIGNAL_BYTES)* 8) - 2" Position [248, 319] } Annotation { Name "early_trace inputs require pulse coincident\nwith last vin for early bits, staying asserted\nuntil at" " least first decoder vout." Position [967, 422] } } } Block { BlockType Reference Name "Gateway Out1" SID "1934" Ports [1, 1] Position [1160, 149, 1195, 161] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Start" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out10" SID "1935" Ports [1, 1] Position [1160, 129, 1195, 141] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Reset" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "1936" Ports [1, 1] Position [1160, 169, 1195, 181] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Num Bytes" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "1937" Ports [1, 1] Position [1160, 189, 1195, 201] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Vin in" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "1938" Ports [1, 1] Position [1160, 209, 1195, 221] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Bit Counter" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "1939" Ports [1, 1] Position [1160, 229, 1195, 241] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Early Trace En" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "1940" Ports [1, 1] Position [1160, 249, 1195, 261] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "End" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "1941" Ports [1, 1] Position [1160, 269, 1195, 281] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Vin Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Inverter" SID "1942" Ports [1, 1] Position [765, 383, 790, 397] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "25,14,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.22 11.2" "2 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0.931" " 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.55 16.44 14" ".44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end" " icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfprintf('','COMMENT: " "end icon text');" } Block { BlockType Reference Name "Logical1" SID "1943" Ports [2, 1] Position [790, 747, 830, 778] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,31,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 31 31 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 31 31 0 ]);\npatch([11.1 16.88 20.88 24.88 28.88 20.88 15.1 11.1 ],[19.44 19.44 23" ".44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([15.1 20.88 16.88 11.1 15.1 ],[15.44 15.44 19.44 19.44 15.44" " ],[0.931 0.946 0.973 ]);\npatch([11.1 16.88 20.88 15.1 11.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch(" "[15.1 28.88 24.88 20.88 16.88 11.1 15.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf" "('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('and');\nfp" "rintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical3" SID "1944" Ports [2, 1] Position [635, 372, 675, 403] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,31,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 31 31 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 31 31 0 ]);\npatch([11.1 16.88 20.88 24.88 28.88 20.88 15.1 11.1 ],[19.44 19.44 23" ".44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([15.1 20.88 16.88 11.1 15.1 ],[15.44 15.44 19.44 19.44 15.44" " ],[0.931 0.946 0.973 ]);\npatch([11.1 16.88 20.88 15.1 11.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch(" "[15.1 28.88 24.88 20.88 16.88 11.1 15.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf" "('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('or');\nfpr" "intf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational2" SID "1945" Ports [2, 1] Position [630, 736, 675, 774] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" axes9 "%" axes10 "%" axes11 "%" axes12 "%" } List { ListType ScopeGraphics FigureColor "[0.5 0.5 0.5]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "30000" YMin "-10~-10~0~-1~0~0~0~0~0~0~0~0" YMax "10~10~1~1~1~1~1~1~1~100~1~1" SaveName "ScopeData3" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType Reference Name "Delay" SID "1960" Ports [1, 1] Position [1425, 910, 1455, 930] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "30,20,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 20 20 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 20 20 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[1" "2.22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[10.22 10.2" "2 12.22 12.22 10.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[8.22 8.22 10.22 10.22 8.2" "2 ],[1 1 1 ]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931" " 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor" "('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Endian Swap" SID "1961" Ports [1, 1] Position [885, 717, 940, 743] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Endian Swap" Location [36, 222, 2218, 1427] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "B" SID "1962" Position [270, 313, 300, 327] IconDisplay "Port number" } Block { BlockType Reference Name "Concat" SID "1963" Ports [8, 1] Position [530, 296, 565, 589] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point at z" "ero." num_inputs "8" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "35,293,8,1,white,blue,0,6fe74153,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 293 293 0 ],[0.77 0.82 0" ".91 ]);\nplot([0 35 35 0 0 ],[0 0 293 293 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[151.55 151." "55 156.55 151.55 156.55 156.55 156.55 151.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[146.55 146.55 1" "51.55 151.55 146.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[141.55 141.55 146.55 146.55 1" "41.55 ],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[136.55 136.55 141.55 136.55 141.55 141.55 13" "6.55 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n" "color('black');port_label('input',1,'hi');\n\n\n\n\n\n\ncolor('black');port_label('input',8,'lo');\n\ncolor('black" "');disp('\\fontsize{20}\\}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b0" SID "1964" Ports [1, 1] Position [435, 311, 475, 329] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type" " is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardw" "are notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22 11.22" " 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22 11.22 9" ".22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch" "([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output'" ",1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b1" SID "1965" Ports [1, 1] Position [435, 346, 475, 364] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type" " is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardw" "are notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "1" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22 11.22" " 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22 11.22 9" ".22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch" "([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output'" ",1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b2" SID "1966" Ports [1, 1] Position [435, 381, 475, 399] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type" " is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardw" "are notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "2" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22 11.22" " 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22 11.22 9" ".22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch" "([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output'" ",1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b3" SID "1967" Ports [1, 1] Position [435, 416, 475, 434] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type" " is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardw" "are notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "3" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22 11.22" " 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22 11.22 9" ".22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch" "([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output'" ",1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b4" SID "1968" Ports [1, 1] Position [435, 451, 475, 469] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type" " is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardw" "are notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "4" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22 11.22" " 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22 11.22 9" ".22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch" "([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output'" ",1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b5" SID "1969" Ports [1, 1] Position [435, 486, 475, 504] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type" " is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardw" "are notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "5" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22 11.22" " 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22 11.22 9" ".22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch" "([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output'" ",1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b6" SID "1970" Ports [1, 1] Position [435, 521, 475, 539] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type" " is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardw" "are notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "6" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22 11.22" " 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22 11.22 9" ".22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch" "([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output'" ",1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b7" SID "1971" Ports [1, 1] Position [435, 556, 475, 574] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type" " is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardw" "are notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "7" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22 11.22" " 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22 11.22 9" ".22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch" "([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output'" ",1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "I" SID "1972" Position [650, 438, 680, 452] IconDisplay "Port number" } Line { SrcBlock "b7" SrcPort 1 DstBlock "Concat" DstPort 8 } Line { SrcBlock "Concat" SrcPort 1 DstBlock "I" DstPort 1 } Line { SrcBlock "b6" SrcPort 1 DstBlock "Concat" DstPort 7 } Line { SrcBlock "b5" SrcPort 1 DstBlock "Concat" DstPort 6 } Line { SrcBlock "b4" SrcPort 1 DstBlock "Concat" DstPort 5 } Line { SrcBlock "b3" SrcPort 1 DstBlock "Concat" DstPort 4 } Line { SrcBlock "b2" SrcPort 1 DstBlock "Concat" DstPort 3 } Line { SrcBlock "b1" SrcPort 1 DstBlock "Concat" DstPort 2 } Line { SrcBlock "b0" SrcPort 1 DstBlock "Concat" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [100, 0] Branch { Points [0, 35] Branch { Points [0, 35] Branch { Points [0, 35] Branch { Points [0, 35] Branch { Points [0, 35] Branch { Points [0, 35] Branch { Points [0, 35] DstBlock "b7" DstPort 1 } Branch { DstBlock "b6" DstPort 1 } } Branch { DstBlock "b5" DstPort 1 } } Branch { DstBlock "b4" DstPort 1 } } Branch { DstBlock "b3" DstPort 1 } } Branch { DstBlock "b2" DstPort 1 } } Branch { DstBlock "b1" DstPort 1 } } Branch { DstBlock "b0" DstPort 1 } } } } Block { BlockType From Name "From1" SID "1973" Position [1395, 936, 1525, 954] ShowName off CloseFcn "tagdialog Close" GotoTag "RX_GLOBAL_RESET" TagVisibility "global" } Block { BlockType From Name "From2" SID "2569" Position [1815, 951, 1945, 969] ShowName off CloseFcn "tagdialog Close" GotoTag "DSSS_RX_RUNNING" TagVisibility "global" } Block { BlockType Reference Name "Gateway Out1" SID "1974" Ports [1, 1] Position [1450, 434, 1485, 446] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Vout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out10" SID "1975" Ports [1, 1] Position [1450, 184, 1485, 196] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "LLR B0" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out11" SID "1976" Ports [1, 1] Position [1450, 209, 1485, 221] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "LLR B1" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out12" SID "1977" Ports [1, 1] Position [1450, 234, 1485, 246] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Early Trace 1" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out13" SID "18105" Ports [1, 1] Position [200, 189, 235, 201] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out14" SID "18098" Ports [1, 1] Position [335, 229, 370, 241] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out16" SID "18099" Ports [1, 1] Position [200, 164, 235, 176] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out2" SID "1978" Ports [1, 1] Position [1450, 334, 1485, 346] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Start" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "1979" Ports [1, 1] Position [1450, 359, 1485, 371] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "End" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "1980" Ports [1, 1] Position [1450, 309, 1485, 321] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "LLR Valid" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "1981" Ports [1, 1] Position [1450, 409, 1485, 421] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Byte Index" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "1982" Ports [1, 1] Position [1450, 384, 1485, 396] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Last Byte" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "1983" Ports [1, 1] Position [1450, 259, 1485, 271] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Early Trace 2" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "1984" Ports [1, 1] Position [1450, 459, 1485, 471] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Reset Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out9" SID "1985" Ports [1, 1] Position [1450, 284, 1485, 296] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Reset#" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Goto Name "Goto1" SID "1986" Position [645, 95, 845, 115] ShowName off GotoTag "CS_DEC_VIN" TagVisibility "global" } Block { BlockType Goto Name "Goto10" SID "1987" Position [645, 35, 845, 55] ShowName off GotoTag "CS_DEC_LLR_b0" TagVisibility "global" } Block { BlockType Goto Name "Goto2" SID "1988" Position [645, 115, 845, 135] ShowName off GotoTag "CS_DEC_START" TagVisibility "global" } Block { BlockType Goto Name "Goto3" SID "1989" Position [645, 135, 845, 155] ShowName off GotoTag "CS_DEC_END" TagVisibility "global" } Block { BlockType Goto Name "Goto4" SID "1990" Position [995, 420, 1195, 440] ShowName off GotoTag "CS_DEC_VOUT" TagVisibility "global" } Block { BlockType Goto Name "Goto5" SID "1991" Position [995, 440, 1195, 460] ShowName off GotoTag "CS_DEC_BYTE_OUT" TagVisibility "global" } Block { BlockType Goto Name "Goto6" SID "1992" Position [1515, 710, 1715, 730] ShowName off GotoTag "CS_DEC_BYTE_VALID_OUT" TagVisibility "global" } Block { BlockType Goto Name "Goto7" SID "1993" Position [1515, 680, 1715, 700] ShowName off GotoTag "CS_DEC_BYTE_INDEX" TagVisibility "global" } Block { BlockType Goto Name "Goto8" SID "1994" Position [645, 75, 845, 95] ShowName off GotoTag "CS_DEC_RESET" TagVisibility "global" } Block { BlockType Goto Name "Goto9" SID "1995" Position [645, 55, 845, 75] ShowName off GotoTag "CS_DEC_LLR_b1" TagVisibility "global" } Block { BlockType Reference Name "Logical1" SID "1996" Ports [3, 1] Position [1595, 909, 1635, 981] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,72,3,1,white,blue,0,a2abe52d,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 72 72 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 72 72 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[41.55" " 41.55 46.55 41.55 46.55 46.55 46.55 41.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[36.55 36.55 41" ".55 41.55 36.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[31.55 31.55 36.55 36.55 31.55 " "],[1 1 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[26.55 26.55 31.55 26.55 31.55 31.55 26.55 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n" "\ncolor('black');disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "1997" Ports [2, 1] Position [890, 962, 930, 993] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,31,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 31 31 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 31 31 0 ]);\npatch([11.1 16.88 20.88 24.88 28.88 20.88 15.1 11.1 ],[19.4" "4 19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([15.1 20.88 16.88 11.1 15.1 ],[15.44 15.44 19.4" "4 19.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([11.1 16.88 20.88 15.1 11.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1" " 1 1 ]);\npatch([15.1 28.88 24.88 20.88 16.88 11.1 15.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946" " 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('bl" "ack');disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical3" SID "2570" Ports [2, 1] Position [2010, 937, 2050, 968] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,31,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 31 31 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 31 31 0 ]);\npatch([11.1 16.88 20.88 24.88 28.88 20.88 15.1 11.1 ],[19.4" "4 19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([15.1 20.88 16.88 11.1 15.1 ],[15.44 15.44 19.4" "4 19.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([11.1 16.88 20.88 15.1 11.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1" " 1 1 ]);\npatch([15.1 28.88 24.88 20.88 16.88 11.1 15.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946" " 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('bl" "ack');disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register" SID "1998" Ports [1, 1] Position [250, 489, 280, 521] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,32,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 32 32 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 32 32 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[20.44 " "20.44 24.44 20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[16.44 16.44 20.44 2" "0.44 16.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register4" SID "1999" Ports [1, 1] Position [250, 524, 280, 556] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,32,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 32 32 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 32 32 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[20.44 " "20.44 24.44 20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[16.44 16.44 20.44 2" "0.44 16.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register5" SID "2000" Ports [1, 1] Position [250, 559, 280, 591] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,32,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 32 32 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 32 32 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[20.44 " "20.44 24.44 20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[16.44 16.44 20.44 2" "0.44 16.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Reinterpret" SID "2001" Ports [1, 1] Position [570, 497, 595, 513] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can change the signal be" "tween signed and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs n" "othing.

Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is fo" "rced to unsigned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an o" "utput of 56 (111000 in binary)." force_arith_type on arith_type "Unsigned" force_bin_pt on bin_pt "0" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "reinterpret" sg_icon_stat "25,16,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 16 16 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 16 16 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[10.2" "2 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[8.22 8.22 10.22 " "10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);" "\npatch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('re" "interpret');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Reinterpret2" SID "2002" Ports [1, 1] Position [570, 532, 595, 548] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can change the signal be" "tween signed and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs n" "othing.

Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is fo" "rced to unsigned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an o" "utput of 56 (111000 in binary)." force_arith_type on arith_type "Unsigned" force_bin_pt on bin_pt "0" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "reinterpret" sg_icon_stat "25,16,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 16 16 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 16 16 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[10.2" "2 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[8.22 8.22 10.22 " "10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);" "\npatch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('re" "interpret');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "SIGNAL & HT-SIG\nDecode" SID "10299" Ports [4, 2] Position [1165, 911, 1275, 989] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "SIGNAL & HT-SIG\nDecode" Location [-1678, 227, -18, 1171] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "124" Block { BlockType Inport Name "byte_ind" SID "10300" Position [90, 203, 120, 217] IconDisplay "Port number" } Block { BlockType Inport Name "byte_valid" SID "10301" Position [90, 243, 120, 257] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "byte" SID "10302" Position [90, 283, 120, 297] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "rst" SID "10303" Position [90, 323, 120, 337] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub1" SID "10304" Ports [2, 1] Position [1215, 878, 1260, 922] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "0" precision "Full" arith_type "Signed (2's comp)" n_bits "ceil(log2(MAX_NUM_BYTES))" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL off hw_selection "Fabric" pipelined off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" sg_icon_stat "45,44,2,1,white,blue,0,e139daf6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 28.66 3" "4.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 28.66 22" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('" "input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bf{a + b}','tex" "mode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Concat" SID "10305" Ports [3, 1] Position [1095, 137, 1125, 203] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point at z" "ero." num_inputs "3" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "30,66,3,1,white,blue,0,61ef8218,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 66 66 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 66 66 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[37.44 37.44 41.4" "4 37.44 41.44 41.44 41.44 37.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[33.44 33.44 37.44 37.44 33.44 ]," "[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[29.44 29.44 33.44 33.44 29.44 ],[1 1 1 ]);\npatch([10.1" " 23.88 19.88 15.88 11.88 6.1 10.1 ],[25.44 25.44 29.44 25.44 29.44 29.44 25.44 ],[0.931 0.946 0.973 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'hi" "');\n\ncolor('black');port_label('input',3,'lo');\n\ncolor('black');disp('\\fontsize{20}\\}','texmode','on');\nfpr" "intf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Concat1" SID "10306" Ports [2, 1] Position [1030, 1196, 1080, 1249] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point at z" "ero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "50,53,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 53 53 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 50 50 0 0 ],[0 0 53 53 0 ]);\npatch([9.425 19.54 26.54 33.54 40.54 26.54 16.425 9.425 ],[33.77 33.7" "7 40.77 33.77 40.77 40.77 40.77 33.77 ],[1 1 1 ]);\npatch([16.425 26.54 19.54 9.425 16.425 ],[26.77 26.77 33.77 33" ".77 26.77 ],[0.931 0.946 0.973 ]);\npatch([9.425 19.54 26.54 16.425 9.425 ],[19.77 19.77 26.77 26.77 19.77 ],[1 1 " "1 ]);\npatch([16.425 40.54 33.54 26.54 19.54 9.425 16.425 ],[12.77 12.77 19.77 12.77 19.77 19.77 12.77 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fontsize{20}\\}'" ",'texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant2" SID "10307" Ports [0, 1] Position [1040, 242, 1055, 258] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Boolean" arith_type "Boolean" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "15,16,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 16 16 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 15 15 0 0 ],[0 0 16 16 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[10.22 10.22 12.22 " "10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[8.22 8.22 10.22 10.22 8.22 ],[0.931" " 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatch([4.55 11.44 9.44" " 7.44 5.44 2.55 4.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon" " graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'0');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Constant4" SID "10308" Ports [0, 1] Position [1030, 899, 1055, 921] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "4" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,22,0,1,white,blue,0,85f36853,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 22 22 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[14.33 14.33 " "17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[11.33 11.33 14.33 14.33 1" "1.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 1 1 ]);\npat" "ch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 0.973 ]);\nfprin" "tf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output'," "1,'4');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant6" SID "10309" Ports [0, 1] Position [1030, 919, 1055, 941] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "4+6" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "4" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,22,0,1,white,blue,0,46ffeebb,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 22 22 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[14.33 14.33 " "17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[11.33 11.33 14.33 14.33 1" "1.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 1 1 ]);\npat" "ch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 0.973 ]);\nfprin" "tf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output'," "1,'10');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "DOUT1" SID "10310" Ports [2, 1] Position [1140, 1198, 1180, 1302] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "40,104,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 104 104 0 ],[0.77 0.82 0" ".91 ]);\nplot([0 40 40 0 0 ],[0 0 104 104 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[57.55 57.55" " 62.55 57.55 62.55 62.55 62.55 57.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[52.55 52.55 57.55 57.55" " 52.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[47.55 47.55 52.55 52.55 47.55 ],[1 1 1 ]);" "\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[42.55 42.55 47.55 42.55 47.55 47.55 42.55 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_labe" "l('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\ncolor('" "black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "DOUT2" SID "10776" Ports [2, 1] Position [1140, 1308, 1180, 1412] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "40,104,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 104 104 0 ],[0.77 0.82 0" ".91 ]);\nplot([0 40 40 0 0 ],[0 0 104 104 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[57.55 57.55" " 62.55 57.55 62.55 62.55 62.55 57.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[52.55 52.55 57.55 57.55" " 52.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[47.55 47.55 52.55 52.55 47.55 ],[1 1 1 ]);" "\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[42.55 42.55 47.55 42.55 47.55 47.55 42.55 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_labe" "l('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\ncolor('" "black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay" SID "10311" Ports [1, 1] Position [1260, 1087, 1290, 1113] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "4" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "30,26,1,1,white,blue,0,d390c2d8,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[16.33 16.3" "3 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 13.33 16.33 16" ".33 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 " "1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');" "disp('z^{-4}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay1" SID "10312" Ports [1, 1] Position [1095, 87, 1125, 113] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "30,26,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[16.33 16.3" "3 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 13.33 16.33 16" ".33 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 " "1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');" "disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From1" SID "10313" Position [865, 182, 1000, 198] ZOrder -9 ShowName off GotoTag "RX_PHY_MODE_11AG" TagVisibility "global" } Block { BlockType From Name "From10" SID "10314" Position [865, 412, 1000, 428] ZOrder -9 ShowName off GotoTag "Code_Rate_11n" } Block { BlockType From Name "From11" SID "10315" Position [865, 487, 1000, 503] ZOrder -9 ShowName off GotoTag "Mod_Sel_11n" } Block { BlockType From Name "From12" SID "10316" Position [865, 542, 1000, 558] ZOrder -9 ShowName off GotoTag "N_DBPS_11ag" } Block { BlockType From Name "From13" SID "10317" Position [865, 467, 1000, 483] ZOrder -9 ShowName off GotoTag "Mod_Sel_11ag" } Block { BlockType From Name "From14" SID "10318" Position [865, 627, 1000, 643] ZOrder -9 ShowName off GotoTag "N_CBPS_11ag" } Block { BlockType From Name "From15" SID "10319" Position [865, 647, 1000, 663] ZOrder -9 ShowName off GotoTag "N_CBPS_11n" } Block { BlockType From Name "From16" SID "10320" Position [865, 392, 1000, 408] ZOrder -9 ShowName off GotoTag "Code_Rate_11ag" } Block { BlockType From Name "From17" SID "10321" Position [865, 337, 1000, 353] ZOrder -9 ShowName off GotoTag "MCS_11n" } Block { BlockType From Name "From18" SID "10322" Position [865, 317, 1000, 333] ZOrder -9 ShowName off GotoTag "MCS_11ag" } Block { BlockType From Name "From19" SID "10323" Position [865, 142, 1000, 158] ZOrder -9 ShowName off GotoTag "RX_PHY_MODE_11AC" TagVisibility "global" } Block { BlockType From Name "From2" SID "10324" Position [685, 1277, 820, 1293] ZOrder -9 ShowName off GotoTag "SIGNAL_Valid" } Block { BlockType From Name "From20" SID "10325" Position [865, 52, 1000, 68] ZOrder -9 ShowName off GotoTag "SIGNAL_Valid" } Block { BlockType From Name "From21" SID "10326" Position [865, 92, 1000, 108] ZOrder -9 ShowName off GotoTag "HT_SIG_Done" } Block { BlockType From Name "From22" SID "10327" Position [865, 262, 1000, 278] ZOrder -9 ShowName off GotoTag "HT_SIG_Unsupported" } Block { BlockType From Name "From23" SID "10328" Position [685, 1107, 820, 1123] ZOrder -9 ShowName off GotoTag "HT_SIG_Unsupported" } Block { BlockType From Name "From24" SID "10329" Position [685, 1092, 820, 1108] ZOrder -9 ShowName off GotoTag "HT_SIG_Valid" } Block { BlockType From Name "From25" SID "10330" Position [685, 1047, 820, 1063] ZOrder -9 ShowName off GotoTag "SIGNAL_Invalid" } Block { BlockType From Name "From26" SID "10331" Position [685, 1142, 820, 1158] ZOrder -9 ShowName off GotoTag "HT_SIG_Invalid" } Block { BlockType From Name "From27" SID "10332" Position [865, 697, 1000, 713] ZOrder -9 ShowName off GotoTag "N_SS_11ag" } Block { BlockType From Name "From28" SID "10333" Position [865, 717, 1000, 733] ZOrder -9 ShowName off GotoTag "N_SS_11n" } Block { BlockType From Name "From29" SID "10334" Position [685, 1127, 820, 1143] ZOrder -9 ShowName off GotoTag "RX_PHY_MODE_11N" TagVisibility "global" } Block { BlockType From Name "From3" SID "10335" Position [865, 22, 1000, 38] ZOrder -9 ShowName off GotoTag "SIGNAL_Invalid" } Block { BlockType From Name "From30" SID "10336" Position [685, 1077, 820, 1093] ZOrder -9 ShowName off GotoTag "RX_PHY_MODE_11N" TagVisibility "global" } Block { BlockType From Name "From4" SID "10337" Position [500, 857, 635, 873] ZOrder -9 ShowName off GotoTag "RX_PHY_MODE_11N" TagVisibility "global" } Block { BlockType From Name "From5" SID "10338" Position [865, 162, 1000, 178] ZOrder -9 ShowName off GotoTag "RX_PHY_MODE_11N" TagVisibility "global" } Block { BlockType From Name "From6" SID "10339" Position [500, 872, 635, 888] ZOrder -9 ShowName off GotoTag "HT_SIG_Valid" } Block { BlockType From Name "From7" SID "10340" Position [865, 812, 1000, 828] ZOrder -9 ShowName off GotoTag "LENGTH_11ag" } Block { BlockType From Name "From8" SID "10341" Position [865, 832, 1000, 848] ZOrder -9 ShowName off GotoTag "LENGTH_11n" } Block { BlockType From Name "From9" SID "10342" Position [865, 562, 1000, 578] ZOrder -9 ShowName off GotoTag "N_DBPS_11n" } Block { BlockType Goto Name "Goto1" SID "10343" Position [390, 202, 525, 218] ShowName off GotoTag "SIGNAL_Invalid" TagVisibility "local" } Block { BlockType Goto Name "Goto10" SID "10344" Position [390, 247, 525, 263] ShowName off GotoTag "Mod_Sel_11ag" TagVisibility "local" } Block { BlockType Goto Name "Goto11" SID "10345" Position [390, 477, 525, 493] ShowName off GotoTag "Mod_Sel_11n" TagVisibility "local" } Block { BlockType Goto Name "Goto12" SID "10346" Position [390, 262, 525, 278] ShowName off GotoTag "Code_Rate_11ag" TagVisibility "local" } Block { BlockType Goto Name "Goto13" SID "10347" Position [390, 492, 525, 508] ShowName off GotoTag "Code_Rate_11n" TagVisibility "local" } Block { BlockType Goto Name "Goto14" SID "10348" Position [390, 292, 525, 308] ShowName off GotoTag "N_DBPS_11ag" TagVisibility "local" } Block { BlockType Goto Name "Goto15" SID "10349" Position [390, 522, 525, 538] ShowName off GotoTag "N_DBPS_11n" TagVisibility "local" } Block { BlockType Goto Name "Goto16" SID "10350" Position [390, 307, 525, 323] ShowName off GotoTag "N_CBPS_11ag" TagVisibility "local" } Block { BlockType Goto Name "Goto17" SID "10351" Position [390, 537, 525, 553] ShowName off GotoTag "N_CBPS_11n" TagVisibility "local" } Block { BlockType Goto Name "Goto18" SID "10352" Position [390, 552, 525, 568] ShowName off GotoTag "N_SS_11n" TagVisibility "local" } Block { BlockType Goto Name "Goto19" SID "10353" Position [390, 322, 525, 338] ShowName off GotoTag "N_SS_11ag" TagVisibility "local" } Block { BlockType Goto Name "Goto2" SID "10354" Position [390, 187, 525, 203] ShowName off GotoTag "SIGNAL_Valid" TagVisibility "local" } Block { BlockType Goto Name "Goto20" SID "10355" Position [390, 277, 525, 293] ShowName off GotoTag "Chan_BW_11ag" TagVisibility "local" } Block { BlockType Goto Name "Goto21" SID "10356" Position [390, 507, 525, 523] ShowName off GotoTag "Chan_BW_11n" TagVisibility "local" } Block { BlockType Goto Name "Goto22" SID "10357" Position [1275, 465, 1475, 485] ShowName off GotoTag "OFDM_RX_DATA_Mod_Sel" TagVisibility "global" } Block { BlockType Goto Name "Goto23" SID "10358" Position [1275, 160, 1475, 180] ShowName off GotoTag "OFDM_RX_PHY_MODE" TagVisibility "global" } Block { BlockType Goto Name "Goto24" SID "10359" Position [390, 402, 525, 418] ShowName off GotoTag "HT_SIG_Valid" TagVisibility "local" } Block { BlockType Goto Name "Goto25" SID "10360" Position [390, 417, 525, 433] ShowName off GotoTag "HT_SIG_Invalid" TagVisibility "local" } Block { BlockType Goto Name "Goto26" SID "10361" Position [1275, 390, 1475, 410] ShowName off GotoTag "OFDM_RX_DATA_Code_Rate" TagVisibility "global" } Block { BlockType Goto Name "Goto27" SID "10362" Position [1275, 540, 1475, 560] ShowName off GotoTag "OFDM_RX_DATA_N_DBPS_1" TagVisibility "global" } Block { BlockType Goto Name "Goto28" SID "10363" Position [1275, 625, 1475, 645] ShowName off GotoTag "OFDM_RX_DATA_N_CBPS" TagVisibility "global" } Block { BlockType Goto Name "Goto29" SID "10364" Position [1275, 50, 1475, 70] ShowName off GotoTag "OFDM_RX_SIGNAL_VALID" TagVisibility "global" } Block { BlockType Goto Name "Goto3" SID "10365" Position [1275, 315, 1475, 335] ShowName off GotoTag "OFDM_RX_DATA_MCS" TagVisibility "global" } Block { BlockType Goto Name "Goto30" SID "10366" Position [390, 567, 525, 583] ShowName off GotoTag "HT_SIG_Done" TagVisibility "local" } Block { BlockType Goto Name "Goto31" SID "10367" Position [1275, 90, 1475, 110] ShowName off GotoTag "OFDM_RX_PARAMS_READY" TagVisibility "global" } Block { BlockType Goto Name "Goto32" SID "10368" Position [1275, 240, 1475, 260] ShowName off GotoTag "OFDM_RX_UNSUPPORTED" TagVisibility "global" } Block { BlockType Goto Name "Goto33" SID "10369" Position [1295, 1241, 1570, 1259] ShowName off GotoTag "OFDM_RX_ERROR_NO_PAYLOAD_REASON" TagVisibility "global" } Block { BlockType Goto Name "Goto34" SID "10370" Position [1275, 695, 1475, 715] ShowName off GotoTag "OFDM_RX_DATA_N_SS" TagVisibility "global" } Block { BlockType Goto Name "Goto35" SID "10371" Position [1365, 846, 1600, 864] ShowName off GotoTag "OFDM_RX_DATA_LAST_BYTE_INDEX" TagVisibility "global" } Block { BlockType Goto Name "Goto36" SID "10372" Position [390, 337, 525, 353] ShowName off GotoTag "SIGNAL_Done" TagVisibility "local" } Block { BlockType Goto Name "Goto37" SID "10373" Position [1275, 570, 1475, 590] ShowName off GotoTag "OFDM_RX_DATA_N_DBPS_2" TagVisibility "global" } Block { BlockType Goto Name "Goto38" SID "10374" Position [1275, 20, 1475, 40] ShowName off GotoTag "OFDM_RX_SIGNAL_INVALID" TagVisibility "global" } Block { BlockType Goto Name "Goto39" SID "10375" Position [1405, 1450, 1605, 1470] ShowName off GotoTag "HT_SIG_ERROR" TagVisibility "global" } Block { BlockType Goto Name "Goto4" SID "10376" Position [390, 447, 525, 463] ShowName off GotoTag "LENGTH_11n" TagVisibility "local" } Block { BlockType Goto Name "Goto40" SID "10777" Position [1370, 1351, 1645, 1369] ShowName off GotoTag "OFDM_RX_ERROR_NO_PAYLOAD" TagVisibility "global" } Block { BlockType Goto Name "Goto41" SID "10917" Position [1275, 760, 1475, 780] ShowName off GotoTag "OFDM_RX_SIGNAL_LENGTH" TagVisibility "global" } Block { BlockType Goto Name "Goto5" SID "10377" Position [1275, 810, 1475, 830] ShowName off GotoTag "OFDM_RX_DATA_LENGTH" TagVisibility "global" } Block { BlockType Goto Name "Goto6" SID "10378" Position [390, 432, 525, 448] ShowName off GotoTag "HT_SIG_Unsupported" TagVisibility "local" } Block { BlockType Goto Name "Goto7" SID "10379" Position [390, 217, 525, 233] ShowName off GotoTag "LENGTH_11ag" TagVisibility "local" } Block { BlockType Goto Name "Goto8" SID "10380" Position [390, 232, 525, 248] ShowName off GotoTag "MCS_11ag" TagVisibility "local" } Block { BlockType Goto Name "Goto9" SID "10381" Position [390, 462, 525, 478] ShowName off GotoTag "MCS_11n" TagVisibility "local" } Block { BlockType SubSystem Name "HT-SIG Decode" SID "10382" Ports [5, 12] Position [205, 400, 320, 585] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "HT-SIG Decode" Location [84, 107, 2305, 1310] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "120" Block { BlockType Inport Name "L-SIG Rate" SID "11763" Position [90, 298, 120, 312] IconDisplay "Port number" } Block { BlockType Inport Name "byte_ind" SID "10383" Position [90, 463, 120, 477] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "byte_valid" SID "10384" Position [90, 423, 120, 437] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "byte" SID "10385" Position [90, 353, 120, 367] Port "4" IconDisplay "Port number" } Block { BlockType Inport Name "rst" SID "10386" Position [90, 388, 120, 402] Port "5" IconDisplay "Port number" } Block { BlockType SubSystem Name "CRC8 Calc" SID "10387" Ports [4, 1] Position [735, 908, 850, 1017] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "CRC8 Calc" Location [300, 183, 2288, 1192] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "byte_ind" SID "10388" Position [130, 283, 160, 297] IconDisplay "Port number" } Block { BlockType Inport Name "data_valid" SID "10389" Position [200, 103, 230, 117] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "data_byte" SID "10390" Position [60, 373, 90, 387] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "reset" SID "10391" Position [60, 533, 90, 547] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "2LSB2" SID "10392" Ports [1, 1] Position [185, 427, 225, 443] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "2" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 16 16 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "2LSB3" SID "10393" Ports [1, 1] Position [185, 472, 225, 488] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "2" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 16 16 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "6MSB" SID "10394" Ports [1, 1] Position [185, 407, 225, 423] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "6" boolean_output off mode "Upper Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 16 16 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Assert1" SID "10395" Ports [1, 1] Position [1370, 418, 1405, 432] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Assert" SourceType "Xilinx Assert Block" infoedit "Asserts a user-defined sample rate and/or type on a signal.

Hardware notes: In hardware th" "is block costs nothing." assert_type off type_source "Explicitly" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "16" bin_pt "14" preci_type "Single" exp_width "8" frac_width "24" assert_rate on rate_source "Explicitly" period "1" output_port on has_advanced_control "0" sggui_pos "20,20,356,423" block_type "assert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,14,1,1,white,blue,0,9657e937,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 14 14 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[9.22 " "9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[7.22 7.22 9.22 9.22" " 7.22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\np" "atch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('Ass" "ert');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "CRC8 Lookup" SID "10396" Ports [1, 1] Position [1000, 379, 1050, 431] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/ROM" SourceType "Xilinx Single Port Read-Only Memory Block" depth "256" initVector "CRC_Table8" distributed_mem "Distributed memory" rst off init_reg "0" en off latency "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "8" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" dbl_ovrd off optimize "Area" use_rpm off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "20,20,348,308" block_type "sprom" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,52,1,1,white,blue,0,eff69a7e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 52 52 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 52 52 0 ]);\npatch([9.425 19.54 26.54 33.54 40.54 26.54 16.425 9.425 ],[33.7" "7 33.77 40.77 33.77 40.77 40.77 40.77 33.77 ],[1 1 1 ]);\npatch([16.425 26.54 19.54 9.425 16.425 ],[26.77 26.77 " "33.77 33.77 26.77 ],[0.931 0.946 0.973 ]);\npatch([9.425 19.54 26.54 16.425 9.425 ],[19.77 19.77 26.77 26.77 19." "77 ],[1 1 1 ]);\npatch([16.425 40.54 33.54 26.54 19.54 9.425 16.425 ],[12.77 12.77 19.77 12.77 19.77 19.77 12.77" " ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nc" "olor('black');port_label('input',1,'addr');\n\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Concat1" SID "10397" Ports [2, 1] Position [345, 239, 390, 321] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point " "at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "45,82,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 82 82 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 82 82 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[47.66 4" "7.66 53.66 47.66 53.66 53.66 53.66 47.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[41.66 41.66 47.66 " "47.66 41.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[35.66 35.66 41.66 41.66 35.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[29.66 29.66 35.66 29.66 35.66 35.66 29.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fontsize{20}" "\\}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Concat2" SID "10398" Ports [2, 1] Position [320, 449, 380, 491] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point " "at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "60,42,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 42 42 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 42 42 0 ]);\npatch([16.65 25.32 31.32 37.32 43.32 31.32 22.65 16.65 ],[27.66" " 27.66 33.66 27.66 33.66 33.66 33.66 27.66 ],[1 1 1 ]);\npatch([22.65 31.32 25.32 16.65 22.65 ],[21.66 21.66 27." "66 27.66 21.66 ],[0.931 0.946 0.973 ]);\npatch([16.65 25.32 31.32 22.65 16.65 ],[15.66 15.66 21.66 21.66 15.66 ]" ",[1 1 1 ]);\npatch([22.65 43.32 37.32 31.32 25.32 16.65 22.65 ],[9.66 9.66 15.66 9.66 15.66 15.66 9.66 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('blac" "k');port_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fontsize{2" "0}\\}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Concat4" SID "10399" Ports [2, 1] Position [320, 404, 380, 446] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point " "at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "60,42,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 42 42 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 42 42 0 ]);\npatch([16.65 25.32 31.32 37.32 43.32 31.32 22.65 16.65 ],[27.66" " 27.66 33.66 27.66 33.66 33.66 33.66 27.66 ],[1 1 1 ]);\npatch([22.65 31.32 25.32 16.65 22.65 ],[21.66 21.66 27." "66 27.66 21.66 ],[0.931 0.946 0.973 ]);\npatch([16.65 25.32 31.32 22.65 16.65 ],[15.66 15.66 21.66 21.66 15.66 ]" ",[1 1 1 ]);\npatch([22.65 43.32 37.32 31.32 25.32 16.65 22.65 ],[9.66 9.66 15.66 9.66 15.66 15.66 9.66 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('blac" "k');port_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fontsize{2" "0}\\}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant" SID "10400" Ports [0, 1] Position [1470, 444, 1495, 466] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "8" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,22,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 22 22 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[14.33 " "14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 1 " "1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('output',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant1" SID "10401" Ports [0, 1] Position [230, 449, 255, 471] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "6" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,22,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 22 22 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[14.33 " "14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 1 " "1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('output',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant2" SID "10402" Ports [0, 1] Position [200, 239, 225, 261] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "8" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "4" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,22,0,1,white,blue,0,7a8c02d8,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 22 22 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[14.33 " "14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 1 " "1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('output',1,'8');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant3" SID "10403" Ports [0, 1] Position [200, 144, 225, 166] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "3" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "4" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,22,0,1,white,blue,0,279a71c8,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 22 22 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[14.33 " "14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 1 " "1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('output',1,'3');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant4" SID "10404" Ports [0, 1] Position [200, 179, 225, 201] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "8" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "4" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,22,0,1,white,blue,0,7a8c02d8,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 22 22 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[14.33 " "14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 1 " "1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('output',1,'8');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant5" SID "10405" Ports [0, 1] Position [200, 299, 225, 321] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "7" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,22,0,1,white,blue,0,2a6960a5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 22 22 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[14.33 " "14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 1 " "1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('output',1,'7');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay" SID "10406" Ports [1, 1] Position [610, 486, 650, 524] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "40,38,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 38 38 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 38 38 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[24.55 24." "55 29.55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[19.55 19.55 24.55 2" "4.55 19.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black')" ";disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Endian Swap" SID "10407" Ports [1, 1] Position [755, 412, 810, 438] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Endian Swap" Location [36, 222, 2218, 1427] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "B" SID "10408" Position [270, 313, 300, 327] IconDisplay "Port number" } Block { BlockType Reference Name "Concat" SID "10409" Ports [8, 1] Position [530, 296, 565, 589] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point " "at zero." num_inputs "8" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "35,293,8,1,white,blue,0,6fe74153,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 293 293 0 ],[0.77 0." "82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 293 293 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[151.5" "5 151.55 156.55 151.55 156.55 156.55 156.55 151.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[146.55 " "146.55 151.55 151.55 146.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[141.55 141.55 146.5" "5 146.55 141.55 ],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[136.55 136.55 141.55 136.55 141." "55 141.55 136.55 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin" " icon text');\ncolor('black');port_label('input',1,'hi');\n\n\n\n\n\n\ncolor('black');port_label('input',8,'lo')" ";\n\ncolor('black');disp('\\fontsize{20}\\}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b0" SID "10410" Ports [1, 1] Position [435, 311, 475, 329] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b1" SID "10411" Ports [1, 1] Position [435, 346, 475, 364] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "1" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b2" SID "10412" Ports [1, 1] Position [435, 381, 475, 399] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "2" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b3" SID "10413" Ports [1, 1] Position [435, 416, 475, 434] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "3" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b4" SID "10414" Ports [1, 1] Position [435, 451, 475, 469] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "4" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b5" SID "10415" Ports [1, 1] Position [435, 486, 475, 504] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "5" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b6" SID "10416" Ports [1, 1] Position [435, 521, 475, 539] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "6" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b7" SID "10417" Ports [1, 1] Position [435, 556, 475, 574] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "7" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "I" SID "10418" Position [650, 438, 680, 452] IconDisplay "Port number" } Line { SrcBlock "B" SrcPort 1 Points [100, 0] Branch { DstBlock "b0" DstPort 1 } Branch { Points [0, 35] Branch { DstBlock "b1" DstPort 1 } Branch { Points [0, 35] Branch { DstBlock "b2" DstPort 1 } Branch { Points [0, 35] Branch { DstBlock "b3" DstPort 1 } Branch { Points [0, 35] Branch { DstBlock "b4" DstPort 1 } Branch { Points [0, 35] Branch { DstBlock "b5" DstPort 1 } Branch { Points [0, 35] Branch { DstBlock "b6" DstPort 1 } Branch { Points [0, 35] DstBlock "b7" DstPort 1 } } } } } } } } Line { SrcBlock "b0" SrcPort 1 DstBlock "Concat" DstPort 1 } Line { SrcBlock "b1" SrcPort 1 DstBlock "Concat" DstPort 2 } Line { SrcBlock "b2" SrcPort 1 DstBlock "Concat" DstPort 3 } Line { SrcBlock "b3" SrcPort 1 DstBlock "Concat" DstPort 4 } Line { SrcBlock "b4" SrcPort 1 DstBlock "Concat" DstPort 5 } Line { SrcBlock "b5" SrcPort 1 DstBlock "Concat" DstPort 6 } Line { SrcBlock "b6" SrcPort 1 DstBlock "Concat" DstPort 7 } Line { SrcBlock "Concat" SrcPort 1 DstBlock "I" DstPort 1 } Line { SrcBlock "b7" SrcPort 1 DstBlock "Concat" DstPort 8 } } } Block { BlockType Reference Name "Gateway Out1" SID "10419" Ports [1, 1] Position [1565, 774, 1600, 786] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Reset" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out10" SID "10420" Ports [1, 1] Position [1565, 749, 1600, 761] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Vin" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "10421" Ports [1, 1] Position [1565, 799, 1600, 811] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Byte" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "10422" Ports [1, 1] Position [1565, 824, 1600, 836] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Good" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "10423" Ports [1, 1] Position [1565, 849, 1600, 861] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "CRC" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "14905" Ports [1, 1] Position [1565, 924, 1600, 936] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Input Bytes" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Scope Name "HT-SIG CRC" SID "10424" Ports [8] Position [1715, 738, 1750, 947] ZOrder -3 Floating off Location [729, 154, 2135, 1498] Open off NumInputPorts "8" ZoomMode "yonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" } List { ListType ScopeGraphics FigureColor "[0.5 0.5 0.5]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "14500 " YMin "0~0~0~0~0~-1~-1~0" YMax "1~1~100~1~275~1~1~275" SaveName "ScopeData15" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType Reference Name "Inverter" SID "10425" Ports [1, 1] Position [260, 401, 295, 429] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "35,28,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 28 28 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[18.44 18.4" "4 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[14.44 14.44 18.44 18.44 " "14.44 ],[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\np" "atch([12.1 25.88 21.88 17.88 13.88 8.1 12.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter1" SID "10426" Ports [1, 1] Position [260, 466, 295, 494] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "35,28,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 28 28 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[18.44 18.4" "4 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[14.44 14.44 18.44 18.44 " "14.44 ],[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\np" "atch([12.1 25.88 21.88 17.88 13.88 8.1 12.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "10427" Ports [3, 1] Position [350, 91, 385, 199] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,108,3,1,white,blue,0,98d76266,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 108 108 0 ],[0.77 0." "82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 108 108 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[59.55" " 59.55 64.55 59.55 64.55 64.55 64.55 59.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[54.55 54.55 59." "55 59.55 54.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[49.55 49.55 54.55 54.55 49.55 ]," "[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[44.55 44.55 49.55 44.55 49.55 49.55 44.55 ],[0.931" " 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\nco" "lor('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical3" SID "10428" Ports [2, 1] Position [870, 365, 915, 445] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "XOR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,80,2,1,white,blue,0,dc21e094,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 80 80 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 80 80 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[46.66 4" "6.66 52.66 46.66 52.66 52.66 52.66 46.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[40.66 40.66 46.66 " "46.66 40.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[34.66 34.66 40.66 40.66 34.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[28.66 28.66 34.66 28.66 34.66 34.66 28.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('" "black');disp('xor');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux" SID "10429" Ports [4, 1] Position [485, 316, 515, 489] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "30,173,4,1,white,blue,3,58b3489d,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 24.7143 148.286 173 0 " "],[0.77 0.82 0.91 ]);\nplot([0 30 30 0 0 ],[0 24.7143 148.286 173 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.8" "8 10.1 6.1 ],[90.44 90.44 94.44 90.44 94.44 94.44 94.44 90.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[" "86.44 86.44 90.44 90.44 86.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[82.44 82.44 86.44 86." "44 82.44 ],[1 1 1 ]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[78.44 78.44 82.44 78.44 82.44 82.44 78.44" " ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nc" "olor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_labe" "l('input',3,'d1');\ncolor('black');port_label('input',4,'d2');\n\ncolor('black');disp('\\bf{}','texmode','on');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational1" SID "10430" Ports [2, 1] Position [1550, 412, 1605, 468] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "55,56,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 56 56 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 56 56 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ],[35" ".77 35.77 42.77 35.77 42.77 42.77 42.77 35.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[28.77 28." "77 35.77 35.77 28.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[21.77 21.77 28.77 28.7" "7 21.77 ],[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[14.77 14.77 21.77 14.77 21.77 21.77" " 14.77 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text" "');\ncolor('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_l" "abel('output',1,'\\bfa = b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational2" SID "10431" Ports [2, 1] Position [275, 240, 310, 280] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,40,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 40 40 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bfa = b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational3" SID "10432" Ports [2, 1] Position [275, 125, 310, 165] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a>=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,40,2,1,white,blue,0,6218dc92,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 40 40 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bfa \\geq b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational4" SID "10433" Ports [2, 1] Position [275, 160, 310, 200] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a<=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,40,2,1,white,blue,0,52e4b236,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 40 40 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bfa \\leq b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational5" SID "10434" Ports [2, 1] Position [275, 280, 310, 320] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,40,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 40 40 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bfa = b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "byte" SID "10435" Ports [3, 1] Position [610, 398, 655, 452] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,54,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 54 54 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 54 54 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[33.66 3" "3.66 39.66 33.66 39.66 39.66 39.66 33.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[27.66 27.66 33.66 " "33.66 27.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[21.66 21.66 27.66 27.66 21.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[15.66 15.66 21.66 15.66 21.66 21.66 15.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Reference Name "crc_accum" SID "10436" Ports [3, 1] Position [1265, 398, 1310, 452] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "hex2dec('FF') % ('27')" rst on en on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,54,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 54 54 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 54 54 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[33.66 3" "3.66 39.66 33.66 39.66 39.66 39.66 33.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[27.66 27.66 33.66 " "33.66 27.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[21.66 21.66 27.66 27.66 21.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[15.66 15.66 21.66 15.66 21.66 21.66 15.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Outport Name "CRC Good" SID "10437" Position [1675, 433, 1705, 447] IconDisplay "Port number" } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Concat2" DstPort 1 } Line { SrcBlock "Inverter1" SrcPort 1 DstBlock "Concat2" DstPort 2 } Line { SrcBlock "2LSB3" SrcPort 1 DstBlock "Inverter1" DstPort 1 } Line { SrcBlock "2LSB2" SrcPort 1 DstBlock "Concat4" DstPort 2 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Concat4" DstPort 1 } Line { SrcBlock "6MSB" SrcPort 1 DstBlock "Inverter" DstPort 1 } Line { SrcBlock "Endian Swap" SrcPort 1 DstBlock "Logical3" DstPort 2 } Line { SrcBlock "Delay" SrcPort 1 Points [570, 0] Branch { Points [0, 250] DstBlock "Gateway Out10" DstPort 1 } Branch { Points [0, -60] DstBlock "crc_accum" DstPort 3 } } Line { SrcBlock "Mux" SrcPort 1 DstBlock "byte" DstPort 1 } Line { SrcBlock "CRC8 Lookup" SrcPort 1 DstBlock "crc_accum" DstPort 1 } Line { Name "CRC" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 DstBlock "HT-SIG CRC" DstPort 5 } Line { SrcBlock "Constant" SrcPort 1 DstBlock "Relational1" DstPort 2 } Line { Name "Good" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 DstBlock "HT-SIG CRC" DstPort 4 } Line { Name "Byte" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 DstBlock "HT-SIG CRC" DstPort 3 } Line { Name "Reset" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 DstBlock "HT-SIG CRC" DstPort 2 } Line { Name "Vin" Labels [0, 0] SrcBlock "Gateway Out10" SrcPort 1 DstBlock "HT-SIG CRC" DstPort 1 } Line { SrcBlock "Relational1" SrcPort 1 Points [30, 0] Branch { Points [0, 275; -160, 0; 0, 115] DstBlock "Gateway Out3" DstPort 1 } Branch { DstBlock "CRC Good" DstPort 1 } } Line { SrcBlock "byte" SrcPort 1 Points [25, 0] Branch { DstBlock "Endian Swap" DstPort 1 } Branch { Points [0, 380] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "Assert1" SrcPort 1 Points [25, 0] Branch { Points [0, -80; -620, 0; 0, 40] DstBlock "Logical3" DstPort 1 } Branch { Points [0, 430] DstBlock "Gateway Out4" DstPort 1 } Branch { DstBlock "Relational1" DstPort 1 } } Line { Labels [0, 0] SrcBlock "crc_accum" SrcPort 1 DstBlock "Assert1" DstPort 1 } Line { SrcBlock "Logical3" SrcPort 1 DstBlock "CRC8 Lookup" DstPort 1 } Line { SrcBlock "data_byte" SrcPort 1 Points [25, 0] Branch { DstBlock "Mux" DstPort 2 } Branch { Points [0, 35] Branch { Points [40, 0] Branch { Points [0, 20] DstBlock "2LSB2" DstPort 1 } Branch { DstBlock "6MSB" DstPort 1 } } Branch { Points [0, 65] Branch { DstBlock "2LSB3" DstPort 1 } Branch { Points [0, 450] DstBlock "Gateway Out5" DstPort 1 } } } } Line { SrcBlock "Concat2" SrcPort 1 DstBlock "Mux" DstPort 4 } Line { SrcBlock "Concat4" SrcPort 1 DstBlock "Mux" DstPort 3 } Line { SrcBlock "byte_ind" SrcPort 1 Points [80, 0] Branch { DstBlock "Relational5" DstPort 1 } Branch { Points [0, -20] Branch { DstBlock "Relational2" DstPort 2 } Branch { Points [0, -100] Branch { DstBlock "Relational4" DstPort 1 } Branch { Points [0, -35] DstBlock "Relational3" DstPort 1 } } } } Line { SrcBlock "Relational5" SrcPort 1 DstBlock "Concat1" DstPort 2 } Line { SrcBlock "Constant5" SrcPort 1 DstBlock "Relational5" DstPort 2 } Line { SrcBlock "Constant2" SrcPort 1 DstBlock "Relational2" DstPort 1 } Line { SrcBlock "Relational2" SrcPort 1 DstBlock "Concat1" DstPort 1 } Line { SrcBlock "Concat1" SrcPort 1 Points [65, 0; 0, 55] DstBlock "Mux" DstPort 1 } Line { SrcBlock "Constant3" SrcPort 1 DstBlock "Relational3" DstPort 2 } Line { SrcBlock "Constant4" SrcPort 1 DstBlock "Relational4" DstPort 2 } Line { SrcBlock "data_valid" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Relational3" SrcPort 1 DstBlock "Logical1" DstPort 2 } Line { SrcBlock "Relational4" SrcPort 1 DstBlock "Logical1" DstPort 3 } Line { SrcBlock "Logical1" SrcPort 1 Points [170, 0; 0, 300] Branch { Points [0, 60] DstBlock "Delay" DstPort 1 } Branch { Points [0, 0] DstBlock "byte" DstPort 3 } } Line { SrcBlock "reset" SrcPort 1 Points [445, 0] Branch { Points [0, -115] DstBlock "byte" DstPort 2 } Branch { Points [620, 0] Branch { Points [0, -115] DstBlock "crc_accum" DstPort 2 } Branch { Points [0, 240] DstBlock "Gateway Out1" DstPort 1 } } } Line { Name "Input Bytes" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 DstBlock "HT-SIG CRC" DstPort 8 } Annotation { Name "HT-SIG is 6 bytes (48 bits) long.\nBits 34:41 are an inverted 8-bit checkusm calculated over bits 0:3" "3.\nThis subsystem is a parallel version of the serial CRC calculation shown in IEEE 802.11-2012 Figure 20-8.\nT" "his block consumes the 6 bytes of the HT-SIG. A valid checksum will result in the crc_accum register\nbeing 0 af" "ter the last input byte.\nBytes 7 and 8 are pre-processed:\nB7: the 6 bits of CRC in byte 7 are inverted, revers" "ing the inversion at the Tx CRC calc\nB8: the 2 bits of CRC in byte 8 are inverted. The remaining bits are set t" "o zero. If the CRC of the first 42\n bits (data+crc) is valid crc_accum will be 0 and these 6 zeros will not ch" "ange the crc value." Position [138, 635] HorizontalAlignment "left" } } } Block { BlockType Reference Name "Constant" SID "10438" Ports [0, 1] Position [180, 574, 205, 596] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "4" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,22,0,1,white,blue,0,85f36853,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 22 22 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[14.33 " "14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 1 " "1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('output',1,'4');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant1" SID "10439" Ports [0, 1] Position [180, 624, 205, 646] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "5" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,22,0,1,white,blue,0,98872051,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 22 22 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[14.33 " "14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 1 " "1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('output',1,'5');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant2" SID "10440" Ports [0, 1] Position [180, 479, 205, 501] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "3" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,22,0,1,white,blue,0,279a71c8,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 22 22 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[14.33 " "14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 1 " "1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('output',1,'3');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant3" SID "10441" Ports [0, 1] Position [180, 809, 205, 831] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "7" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,22,0,1,white,blue,0,2a6960a5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 22 22 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[14.33 " "14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 1 " "1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('output',1,'7');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant4" SID "10442" Ports [0, 1] Position [180, 859, 205, 881] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "8" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "4" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,22,0,1,white,blue,0,7a8c02d8,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 22 22 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[14.33 " "14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 1 " "1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('output',1,'8');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant5" SID "10443" Ports [0, 1] Position [180, 759, 205, 781] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "6" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,22,0,1,white,blue,0,f0403ad7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 22 22 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[14.33 " "14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 1 " "1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('output',1,'6');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant6" SID "11765" Ports [0, 1] Position [180, 314, 205, 336] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,22,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 22 22 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[14.33 " "14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 1 " "1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('output',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "DOUT" SID "10444" Ports [3, 1] Position [610, 438, 645, 482] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,44,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 44 44 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[27.55 27." "55 32.55 27.55 32.55 32.55 32.55 27.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[22.55 22.55 27.55 2" "7.55 22.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[17.55 17.55 22.55 22.55 17.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[12.55 12.55 17.55 12.55 17.55 17.55 12.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'e" "n');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "DOUT1" SID "10445" Ports [3, 1] Position [610, 533, 645, 577] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "100" rst on en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,44,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 44 44 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[27.55 27." "55 32.55 27.55 32.55 32.55 32.55 27.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[22.55 22.55 27.55 2" "7.55 22.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[17.55 17.55 22.55 22.55 17.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[12.55 12.55 17.55 12.55 17.55 17.55 12.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'e" "n');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "DOUT2" SID "10446" Ports [3, 1] Position [610, 583, 645, 627] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,44,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 44 44 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[27.55 27." "55 32.55 27.55 32.55 32.55 32.55 27.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[22.55 22.55 27.55 2" "7.55 22.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[17.55 17.55 22.55 22.55 17.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[12.55 12.55 17.55 12.55 17.55 17.55 12.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'e" "n');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "DOUT3" SID "10447" Ports [3, 1] Position [610, 718, 645, 762] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "hex2dec('03')" rst on en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,44,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 44 44 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[27.55 27." "55 32.55 27.55 32.55 32.55 32.55 27.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[22.55 22.55 27.55 2" "7.55 22.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[17.55 17.55 22.55 22.55 17.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[12.55 12.55 17.55 12.55 17.55 17.55 12.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'e" "n');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "DOUT4" SID "10448" Ports [3, 1] Position [610, 768, 645, 812] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "hex2dec('E0')" rst on en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,44,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 44 44 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[27.55 27." "55 32.55 27.55 32.55 32.55 32.55 27.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[22.55 22.55 27.55 2" "7.55 22.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[17.55 17.55 22.55 22.55 17.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[12.55 12.55 17.55 12.55 17.55 17.55 12.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'e" "n');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "DOUT5" SID "10449" Ports [3, 1] Position [610, 818, 645, 862] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,44,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 44 44 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[27.55 27." "55 32.55 27.55 32.55 32.55 32.55 27.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[22.55 22.55 27.55 2" "7.55 22.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[17.55 17.55 22.55 22.55 17.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[12.55 12.55 17.55 12.55 17.55 17.55 12.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'e" "n');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Delay" SID "10450" Ports [1, 1] Position [610, 1025, 650, 1055] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "40,30,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 30 30 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 30 30 0 ]);\npatch([11.1 16.88 20.88 24.88 28.88 20.88 15.1 11.1 ],[19.44 19" ".44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([15.1 20.88 16.88 11.1 15.1 ],[15.44 15.44 19.44 19." "44 15.44 ],[0.931 0.946 0.973 ]);\npatch([11.1 16.88 20.88 15.1 11.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]" ");\npatch([15.1 28.88 24.88 20.88 16.88 11.1 15.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 " "]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp" "('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay1" SID "10451" Ports [1, 1] Position [760, 1025, 800, 1055] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "40,30,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 30 30 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 30 30 0 ]);\npatch([11.1 16.88 20.88 24.88 28.88 20.88 15.1 11.1 ],[19.44 19" ".44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([15.1 20.88 16.88 11.1 15.1 ],[15.44 15.44 19.44 19." "44 15.44 ],[0.931 0.946 0.973 ]);\npatch([11.1 16.88 20.88 15.1 11.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]" ");\npatch([15.1 28.88 24.88 20.88 16.88 11.1 15.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 " "]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp" "('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "10452" Position [1080, 594, 1230, 616] ZOrder -9 ShowName off GotoTag "LAST_SIG_BYTE_DONE" } Block { BlockType Reference Name "Gateway Out1" SID "10453" Ports [1, 1] Position [1390, 84, 1425, 96] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Length" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out10" SID "10454" Ports [1, 1] Position [1390, 259, 1425, 271] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "HT-SIG Valid" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out11" SID "11750" Ports [1, 1] Position [1120, 884, 1155, 896] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Tail valid" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out12" SID "11751" Ports [1, 1] Position [1120, 909, 1155, 921] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "CRC valid" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out13" SID "11766" Ports [1, 1] Position [1120, 934, 1155, 946] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "L-SIG Rate" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "10455" Ports [1, 1] Position [1390, 109, 1425, 121] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "MCS" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "10456" Ports [1, 1] Position [1390, 134, 1425, 146] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Mod Order" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "10457" Ports [1, 1] Position [1390, 159, 1425, 171] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Code Rate" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "10458" Ports [1, 1] Position [1390, 184, 1425, 196] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Chan BW" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "10459" Ports [1, 1] Position [1390, 209, 1425, 221] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Unsupported" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "10460" Ports [1, 1] Position [1390, 234, 1425, 246] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "HT-SIG Invalid" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "11748" Ports [1, 1] Position [1120, 834, 1155, 846] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "MCS valid" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out9" SID "11749" Ports [1, 1] Position [1120, 859, 1155, 871] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Flags valid" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Goto Name "Goto2" SID "10461" Position [910, 1075, 1050, 1095] ShowName off GotoTag "LAST_SIG_BYTE_DONE" TagVisibility "local" } Block { BlockType SubSystem Name "HT Length" SID "10462" Ports [2, 2] Position [735, 540, 850, 600] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "HT Length" Location [84, 107, 2305, 1310] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "B4" SID "10463" Position [275, 443, 305, 457] IconDisplay "Port number" } Block { BlockType Inport Name "B5" SID "10464" Position [275, 408, 305, 422] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Concat1" SID "10465" Ports [2, 1] Position [415, 396, 475, 469] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point " "at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "60,73,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 73 73 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 73 73 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[44.88 44" ".88 52.88 44.88 52.88 52.88 52.88 44.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[36.88 36.88 44.88 44." "88 36.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[28.88 28.88 36.88 36.88 28.88 ],[1 1 1 ]" ");\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[20.88 20.88 28.88 20.88 28.88 28.88 20.88 ],[0.931 0.946 0." "973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port" "_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fontsize{20}\\}','" "texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Concat2" SID "10466" Ports [2, 1] Position [415, 535, 475, 595] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point " "at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "60,60,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 60 60 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[38.88 38" ".88 46.88 38.88 46.88 46.88 46.88 38.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[30.88 30.88 38.88 38." "88 30.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[22.88 22.88 30.88 30.88 22.88 ],[1 1 1 ]" ");\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[14.88 14.88 22.88 14.88 22.88 22.88 14.88 ],[0.931 0.946 0." "973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port" "_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fontsize{20}\\}','" "texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant" SID "10467" Ports [0, 1] Position [340, 570, 370, 590] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "10" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,20,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 20 20 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 20 20 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[12.22" " 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[10.22 10.22 12." "22 12.22 10.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1" " 1 1 ]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');po" "rt_label('output',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant1" SID "10772" Ports [0, 1] Position [495, 600, 525, 620] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "6" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,20,0,1,white,blue,0,f0403ad7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 20 20 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 20 20 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[12.22" " 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[10.22 10.22 12." "22 12.22 10.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1" " 1 1 ]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');po" "rt_label('output',1,'6');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant2" SID "11753" Ports [0, 1] Position [265, 325, 295, 345] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "8" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period on period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,20,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 20 20 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 20 20 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[12.22" " 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[10.22 10.22 12." "22 12.22 10.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1" " 1 1 ]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');po" "rt_label('output',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "10468" Position [75, 540, 270, 560] ZOrder -9 ShowName off GotoTag "regRx_MAX_SIGNAL_LENGTH_KB" TagVisibility "global" } Block { BlockType Reference Name "Logical" SID "10470" Ports [2, 1] Position [665, 534, 700, 621] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,87,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 87 87 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 87 87 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[48.55 48." "55 53.55 48.55 53.55 53.55 53.55 48.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[43.55 43.55 48.55 4" "8.55 43.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[38.55 38.55 43.55 43.55 38.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[33.55 33.55 38.55 33.55 38.55 38.55 33.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('b" "lack');disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "10472" Ports [1, 1] Position [310, 537, 340, 563] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[16.3" "3 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 13.33 " "16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13.33 10." "33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor" "('black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','" "texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational1" SID "10473" Ports [2, 1] Position [575, 580, 610, 620] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "ab" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,40,2,1,white,blue,0,b5131c97,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 40 40 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bfa > b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "length" SID "10475" Position [750, 428, 780, 442] IconDisplay "Port number" } Block { BlockType Outport Name "Unsupported" SID "10476" Position [750, 573, 780, 587] Port "2" IconDisplay "Port number" } Line { SrcBlock "Concat1" SrcPort 1 Points [50, 0] Branch { DstBlock "length" DstPort 1 } Branch { Points [0, 110] Branch { DstBlock "Relational2" DstPort 1 } Branch { Points [0, 45] DstBlock "Relational1" DstPort 1 } } } Line { SrcBlock "From" SrcPort 1 DstBlock "Register1" DstPort 1 } Line { SrcBlock "Constant" SrcPort 1 DstBlock "Concat2" DstPort 2 } Line { SrcBlock "Relational2" SrcPort 1 DstBlock "Logical" DstPort 1 } Line { SrcBlock "Concat2" SrcPort 1 DstBlock "Relational2" DstPort 2 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Relational1" DstPort 2 } Line { SrcBlock "Register1" SrcPort 1 DstBlock "Concat2" DstPort 1 } Line { SrcBlock "Relational1" SrcPort 1 DstBlock "Logical" DstPort 2 } Line { SrcBlock "Logical" SrcPort 1 DstBlock "Unsupported" DstPort 1 } Line { SrcBlock "B5" SrcPort 1 DstBlock "Concat1" DstPort 1 } Line { SrcBlock "B4" SrcPort 1 DstBlock "Concat1" DstPort 2 } Annotation { Name "HT-SIG.LENGTH can be 0, indicating\na null-data frame used for channel sounding\n(IEEE 802.11-2012 20" ".3.9.4.3)\n\nHowever our MAC/PHY do not currently support\nthe beamforming modes that use NDP packets \nfor chan" "nel sounding. So we require a non-zero\nHT-SIG.LENGTH for any packet that is passed\nto the lower MAC code. This" " check in hardware\nreduces the impact of bad SIGNAL fields with\nbogus, small LENGTH fields. The downstream \nl" "ogic assumes every packet will have at least\n6 bytes after the SIGNAL field." Position [635, 730] HorizontalAlignment "left" } } } Block { BlockType Scope Name "HT-SIG Decode" SID "10477" Ports [8] Position [1550, 73, 1585, 282] ZOrder -3 Floating off Location [735, 158, 2141, 1502] Open off NumInputPorts "8" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" } List { ListType ScopeGraphics FigureColor "[0.5 0.5 0.5]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "25000" YMin "99~0~0~-1~-1~-1~0~-1" YMax "101~1~1~1~1~1~1~1" SaveName "ScopeData45" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType Scope Name "HT-SIG Decode Errs" SID "11752" Ports [8] Position [1280, 823, 1315, 1032] ZOrder -3 Floating off Location [729, 154, 2135, 1498] Open off NumInputPorts "8" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" } List { ListType ScopeGraphics FigureColor "[0.5 0.5 0.5]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "25000" YMin "99~0~0~-1~-1~-1~0~-1" YMax "101~1~1~1~1~1~1~1" SaveName "ScopeData52" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType SubSystem Name "HT-SIG Flags" SID "10478" Ports [3, 2] Position [735, 710, 850, 770] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "HT-SIG Flags" Location [84, 107, 2286, 1449] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "125" Block { BlockType Inport Name "B3" SID "10479" Position [300, 233, 330, 247] IconDisplay "Port number" } Block { BlockType Inport Name "B6" SID "10480" Position [300, 268, 330, 282] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "B7" SID "10481" Position [300, 573, 330, 587] Port "3" IconDisplay "Port number" } Block { BlockType Reference Name "Constant" SID "10482" Ports [0, 1] Position [440, 754, 475, 776] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "35,22,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 22 22 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[14" ".33 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[11.33 11." "33 14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[8.33 8.33 11.33 11.33 " "8.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor" "('black');port_label('output',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant1" SID "10483" Ports [0, 1] Position [440, 714, 475, 736] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "35,22,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 22 22 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[14" ".33 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[11.33 11." "33 14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[8.33 8.33 11.33 11.33 " "8.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor" "('black');port_label('output',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Goto Name "Goto" SID "10484" Position [715, 231, 835, 249] ZOrder -10 ShowName off GotoTag "CHAN_BW" TagVisibility "local" } Block { BlockType Goto Name "Goto1" SID "10485" Position [715, 266, 835, 284] ZOrder -10 ShowName off GotoTag "SMOOTHING" TagVisibility "local" } Block { BlockType Goto Name "Goto2" SID "10486" Position [715, 301, 835, 319] ZOrder -10 ShowName off GotoTag "NOT_SOUNDING" TagVisibility "local" } Block { BlockType Goto Name "Goto3" SID "10487" Position [715, 381, 835, 399] ZOrder -10 ShowName off GotoTag "AGGREGATION" TagVisibility "local" } Block { BlockType Goto Name "Goto4" SID "10488" Position [715, 421, 835, 439] ZOrder -10 ShowName off GotoTag "STBC" TagVisibility "local" } Block { BlockType Goto Name "Goto5" SID "10489" Position [715, 461, 835, 479] ZOrder -10 ShowName off GotoTag "FEC" TagVisibility "local" } Block { BlockType Goto Name "Goto6" SID "10490" Position [715, 496, 835, 514] ZOrder -10 ShowName off GotoTag "SHORT_GI" TagVisibility "local" } Block { BlockType Goto Name "Goto7" SID "10491" Position [715, 571, 835, 589] ZOrder -10 ShowName off GotoTag "N_ESS" TagVisibility "local" } Block { BlockType Reference Name "Inverter" SID "10492" Ports [1, 1] Position [695, 636, 725, 654] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "30,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 18 18 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');dis" "p('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical" SID "10493" Ports [6, 1] Position [780, 612, 815, 753] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "6" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,141,6,1,white,blue,0,31bf5775,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 141 141 0 ],[0.77 0." "82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 141 141 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[75.55" " 75.55 80.55 75.55 80.55 80.55 80.55 75.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[70.55 70.55 75." "55 75.55 70.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[65.55 65.55 70.55 70.55 65.55 ]," "[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[60.55 60.55 65.55 60.55 65.55 65.55 60.55 ],[0.931" " 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\n\n" "\n\ncolor('black');disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational" SID "10494" Ports [2, 1] Position [540, 740, 585, 775] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a!=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "45,35,2,1,white,blue,0,850de6e7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 35 35 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 35 35 0 ]);\npatch([10.875 18.1 23.1 28.1 33.1 23.1 15.875 10.875 ],[22.55 2" "2.55 27.55 22.55 27.55 27.55 27.55 22.55 ],[1 1 1 ]);\npatch([15.875 23.1 18.1 10.875 15.875 ],[17.55 17.55 22.5" "5 22.55 17.55 ],[0.931 0.946 0.973 ]);\npatch([10.875 18.1 23.1 15.875 10.875 ],[12.55 12.55 17.55 17.55 12.55 ]" ",[1 1 1 ]);\npatch([15.875 33.1 28.1 23.1 18.1 10.875 15.875 ],[7.55 7.55 12.55 7.55 12.55 12.55 7.55 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'" "\\bfa \\neq b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational1" SID "10495" Ports [2, 1] Position [540, 700, 585, 735] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a!=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "45,35,2,1,white,blue,0,850de6e7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 35 35 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 35 35 0 ]);\npatch([10.875 18.1 23.1 28.1 33.1 23.1 15.875 10.875 ],[22.55 2" "2.55 27.55 22.55 27.55 27.55 27.55 22.55 ],[1 1 1 ]);\npatch([15.875 23.1 18.1 10.875 15.875 ],[17.55 17.55 22.5" "5 22.55 17.55 ],[0.931 0.946 0.973 ]);\npatch([10.875 18.1 23.1 15.875 10.875 ],[12.55 12.55 17.55 17.55 12.55 ]" ",[1 1 1 ]);\npatch([15.875 33.1 28.1 23.1 18.1 10.875 15.875 ],[7.55 7.55 12.55 7.55 12.55 12.55 7.55 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'" "\\bfa \\neq b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[0]" SID "10496" Ports [1, 1] Position [425, 267, 465, 283] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 16 16 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[1:0]" SID "10497" Ports [1, 1] Position [425, 572, 465, 588] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "2" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 16 16 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[1]" SID "10498" Ports [1, 1] Position [425, 302, 465, 318] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "1" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 16 16 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[2]" SID "10499" Ports [1, 1] Position [425, 342, 465, 358] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "2" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 16 16 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[3]" SID "10500" Ports [1, 1] Position [425, 382, 465, 398] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "3" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 16 16 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[5:4]" SID "10501" Ports [1, 1] Position [425, 422, 465, 438] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "2" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "4" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 16 16 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[6]" SID "10502" Ports [1, 1] Position [425, 462, 465, 478] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "6" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 16 16 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[7]" SID "10503" Ports [1, 1] Position [425, 232, 465, 248] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "7" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 16 16 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[7] " SID "10504" Ports [1, 1] Position [425, 497, 465, 513] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "7" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 16 16 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Unsupported" SID "10505" Position [910, 678, 940, 692] IconDisplay "Port number" } Block { BlockType Outport Name "Valid" SID "10506" Position [910, 343, 940, 357] Port "2" IconDisplay "Port number" } Line { SrcBlock "B3" SrcPort 1 DstBlock "b[7]" DstPort 1 } Line { SrcBlock "B6" SrcPort 1 Points [65, 0] Branch { DstBlock "b[0]" DstPort 1 } Branch { Points [0, 35] Branch { DstBlock "b[1]" DstPort 1 } Branch { Points [0, 40] Branch { DstBlock "b[2]" DstPort 1 } Branch { Points [0, 40] Branch { DstBlock "b[3]" DstPort 1 } Branch { Points [0, 40] Branch { DstBlock "b[5:4]" DstPort 1 } Branch { Points [0, 40] Branch { DstBlock "b[6]" DstPort 1 } Branch { Points [0, 35] DstBlock "b[7] " DstPort 1 } } } } } } } Line { SrcBlock "b[7]" SrcPort 1 Points [195, 0] Branch { DstBlock "Goto" DstPort 1 } Branch { Points [0, 380] DstBlock "Logical" DstPort 1 } } Line { SrcBlock "b[3]" SrcPort 1 DstBlock "Goto3" DstPort 1 } Line { SrcBlock "b[1]" SrcPort 1 Points [190, 0] Branch { DstBlock "Goto2" DstPort 1 } Branch { Points [0, 335] DstBlock "Inverter" DstPort 1 } } Line { SrcBlock "b[0]" SrcPort 1 DstBlock "Goto1" DstPort 1 } Line { SrcBlock "b[5:4]" SrcPort 1 Points [35, 0] Branch { DstBlock "Goto4" DstPort 1 } Branch { Points [0, 280] DstBlock "Relational1" DstPort 1 } } Line { SrcBlock "b[6]" SrcPort 1 Points [185, 0] Branch { DstBlock "Goto5" DstPort 1 } Branch { Points [0, 200] DstBlock "Logical" DstPort 3 } } Line { SrcBlock "b[7] " SrcPort 1 Points [180, 0] Branch { DstBlock "Goto6" DstPort 1 } Branch { Points [0, 190] DstBlock "Logical" DstPort 4 } } Line { SrcBlock "B7" SrcPort 1 DstBlock "b[1:0]" DstPort 1 } Line { SrcBlock "b[1:0]" SrcPort 1 Points [30, 0] Branch { DstBlock "Goto7" DstPort 1 } Branch { Points [0, 170] DstBlock "Relational" DstPort 1 } } Line { SrcBlock "Constant" SrcPort 1 DstBlock "Relational" DstPort 2 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Relational1" DstPort 2 } Line { SrcBlock "Logical" SrcPort 1 DstBlock "Unsupported" DstPort 1 } Line { SrcBlock "Relational1" SrcPort 1 DstBlock "Logical" DstPort 5 } Line { SrcBlock "Relational" SrcPort 1 Points [55, 0; 0, -15] DstBlock "Logical" DstPort 6 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical" DstPort 2 } Line { SrcBlock "b[2]" SrcPort 1 DstBlock "Valid" DstPort 1 } Annotation { Name "HT-SIG Flags\n(IEEE 802.11-2012 Figure 20-6)\n\nB3[7]: Channel bandwidth (0=20, 1=40)\n\nB6[0]: Smoot" "hing\nB6[1]: Not sounding\nB6[2]: Reserved (always 1)\nB6[3]: Aggregation\nB6[5:4]: STBC\nB6[6]: FEC (0=BCC, 1=L" "DPC)\nB6[7]: Short GI\n\nB7[1:0]: Num extension spatial streams" Position [1008, 354] HorizontalAlignment "left" FontName "Consolas" FontSize 12 } } } Block { BlockType Reference Name "Inverter4" SID "10507" Ports [1, 1] Position [1200, 616, 1230, 634] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "30,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 18 18 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');dis" "p('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical" SID "10508" Ports [2, 1] Position [375, 603, 400, 632] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "25,29,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 29 29 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 29 29 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 " "17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33" " 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('bl" "ack');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "10509" Ports [2, 1] Position [375, 553, 400, 582] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "25,29,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 29 29 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 29 29 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 " "17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33" " 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('bl" "ack');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "10510" Ports [2, 1] Position [375, 458, 400, 487] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "25,29,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 29 29 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 29 29 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 " "17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33" " 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('bl" "ack');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical3" SID "10511" Ports [2, 1] Position [375, 838, 400, 867] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "25,29,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 29 29 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 29 29 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 " "17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33" " 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('bl" "ack');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical4" SID "10512" Ports [2, 1] Position [375, 788, 400, 817] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "25,29,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 29 29 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 29 29 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 " "17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33" " 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('bl" "ack');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical5" SID "10513" Ports [2, 1] Position [375, 738, 400, 767] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "25,29,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 29 29 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 29 29 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 " "17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33" " 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('bl" "ack');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical6" SID "10514" Ports [2, 1] Position [1275, 595, 1315, 635] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,40,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('b" "lack');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical7" SID "10515" Ports [5, 1] Position [1050, 722, 1090, 788] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "5" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,66,5,1,white,blue,0,2904cdfe,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 66 66 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 66 66 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[38.55 38." "55 43.55 38.55 43.55 43.55 43.55 38.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[33.55 33.55 38.55 3" "8.55 33.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[28.55 28.55 33.55 33.55 28.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[23.55 23.55 28.55 23.55 28.55 28.55 23.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\n\n\nco" "lor('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical8" SID "10516" Ports [2, 1] Position [1275, 725, 1315, 765] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,40,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('b" "lack');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical9" SID "10517" Ports [3, 1] Position [1045, 480, 1085, 520] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,40,3,1,white,blue,0,a2abe52d,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\ncolor(" "'black');disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "MCS Decode" SID "10518" Ports [2, 9] Position [735, 267, 850, 523] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "MCS Decode" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "124" Block { BlockType Inport Name "B3" SID "10519" Position [110, 253, 140, 267] IconDisplay "Port number" } Block { BlockType Inport Name "B6" SID "10520" Position [110, 203, 140, 217] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "5LSB" SID "10521" Ports [1, 1] Position [220, 252, 260, 268] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "5" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 16 16 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "7LSB" SID "10522" Ports [1, 1] Position [220, 457, 260, 473] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "7" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 16 16 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Concat" SID "10523" Ports [2, 1] Position [325, 199, 370, 246] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point " "at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "45,47,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 47 47 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 47 47 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[29.66 2" "9.66 35.66 29.66 35.66 35.66 35.66 29.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[23.66 23.66 29.66 " "29.66 23.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[17.66 17.66 23.66 23.66 17.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[11.66 11.66 17.66 11.66 17.66 17.66 11.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fontsize{20}" "\\}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant1" SID "10524" Ports [0, 1] Position [375, 692, 400, 708] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "76" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "7" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,16,0,1,white,blue,0,d2990f9d,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 16 16 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[10.22 10" ".22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[8.22 8.22 10.22 10.22" " 8.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output'" ",1,'76');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant17" SID "10525" Ports [0, 1] Position [375, 552, 400, 568] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "7" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,16,0,1,white,blue,0,2a6960a5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 16 16 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[10.22 10" ".22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[8.22 8.22 10.22 10.22" " 8.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output'" ",1,'7');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant18" SID "10526" Ports [0, 1] Position [375, 657, 400, 673] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "31" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "7" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,16,0,1,white,blue,0,8a5cc997,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 16 16 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[10.22 10" ".22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[8.22 8.22 10.22 10.22" " 8.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output'" ",1,'31');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert" SID "10527" Ports [1, 1] Position [635, 511, 660, 529] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('outpu" "t',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "10528" Ports [2, 1] Position [700, 508, 725, 557] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "25,49,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 49 49 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 49 49 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[27.33 " "27.33 30.33 27.33 30.33 30.33 30.33 27.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[24.33 24.33 27.33" " 27.33 24.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[21.33 21.33 24.33 24.33 21.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[18.33 18.33 21.33 18.33 21.33 21.33 18.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor" "('black');disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "ROM" SID "10529" Ports [1, 1] Position [420, 197, 480, 253] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/ROM" SourceType "Xilinx Single Port Read-Only Memory Block" depth "numel(mcs_rom_11n)" initVector "mcs_rom_11n" distributed_mem "Block RAM" rst off init_reg "0" en off latency "1" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "32" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" dbl_ovrd off optimize "Area" use_rpm on xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "sprom" sg_icon_stat "60,56,1,1,white,blue,0,bbc23d60,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36" ".88 44.88 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36." "88 28.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]" ");\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0." "973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port" "_label('input',1,'addr');\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text')" ";" } Block { BlockType Reference Name "Relational" SID "10530" Ports [2, 1] Position [445, 517, 500, 573] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a>b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "55,56,2,1,white,blue,0,b5131c97,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 56 56 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 56 56 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ],[35" ".77 35.77 42.77 35.77 42.77 42.77 42.77 35.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[28.77 28." "77 35.77 35.77 28.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[21.77 21.77 28.77 28.7" "7 21.77 ],[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[14.77 14.77 21.77 14.77 21.77 21.77" " 14.77 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text" "');\ncolor('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_l" "abel('output',1,'\\bfa > b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational1" SID "10531" Ports [2, 1] Position [445, 622, 500, 678] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a<=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "55,56,2,1,white,blue,0,52e4b236,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 56 56 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 56 56 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ],[35" ".77 35.77 42.77 35.77 42.77 42.77 42.77 35.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[28.77 28." "77 35.77 35.77 28.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[21.77 21.77 28.77 28.7" "7 21.77 ],[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[14.77 14.77 21.77 14.77 21.77 21.77" " 14.77 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text" "');\ncolor('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_l" "abel('output',1,'\\bfa \\leq b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text'" ");" } Block { BlockType Reference Name "b[0]" SID "10532" Ports [1, 1] Position [550, 217, 590, 233] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 16 16 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[16:7]" SID "10533" Ports [1, 1] Position [550, 372, 590, 388] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "10" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "7" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 16 16 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[26:17]" SID "10534" Ports [1, 1] Position [550, 412, 590, 428] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "10" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "17" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 16 16 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[2:1]" SID "10535" Ports [1, 1] Position [550, 252, 590, 268] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "2" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "1" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 16 16 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[4:3]" SID "10536" Ports [1, 1] Position [550, 292, 590, 308] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "2" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "3" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 16 16 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[6:5]" SID "10537" Ports [1, 1] Position [550, 332, 590, 348] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "2" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "5" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 16 16 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[7]" SID "10538" Ports [1, 1] Position [220, 202, 260, 218] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "7" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 16 16 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "MCS" SID "10539" Position [775, 458, 805, 472] IconDisplay "Port number" } Block { BlockType Outport Name "mod_sel" SID "10540" Position [775, 293, 805, 307] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "code_rate" SID "10541" Position [775, 333, 805, 347] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "N_CBPS" SID "10542" Position [775, 373, 805, 387] Port "4" IconDisplay "Port number" } Block { BlockType Outport Name "N_DBPS" SID "10543" Position [775, 413, 805, 427] Port "5" IconDisplay "Port number" } Block { BlockType Outport Name "N_SS" SID "10544" Position [775, 253, 805, 267] Port "6" IconDisplay "Port number" } Block { BlockType Outport Name "Chan_BW" SID "10545" Position [775, 218, 805, 232] Port "7" IconDisplay "Port number" } Block { BlockType Outport Name "Unsupported" SID "10546" Position [775, 528, 805, 542] Port "8" IconDisplay "Port number" } Block { BlockType Outport Name "MCS Valid" SID "10547" Position [775, 643, 805, 657] Port "9" IconDisplay "Port number" } Line { SrcBlock "Constant18" SrcPort 1 DstBlock "Relational1" DstPort 2 } Line { SrcBlock "Relational1" SrcPort 1 DstBlock "MCS Valid" DstPort 1 } Line { SrcBlock "Constant17" SrcPort 1 DstBlock "Relational" DstPort 2 } Line { SrcBlock "Relational" SrcPort 1 DstBlock "Logical1" DstPort 2 } Line { SrcBlock "B3" SrcPort 1 Points [25, 0] Branch { DstBlock "5LSB" DstPort 1 } Branch { Points [0, 205] DstBlock "7LSB" DstPort 1 } } Line { SrcBlock "B6" SrcPort 1 DstBlock "b[7]" DstPort 1 } Line { SrcBlock "ROM" SrcPort 1 Points [35, 0] Branch { DstBlock "b[0]" DstPort 1 } Branch { Points [0, 35] Branch { DstBlock "b[2:1]" DstPort 1 } Branch { Points [0, 40] Branch { DstBlock "b[4:3]" DstPort 1 } Branch { Points [0, 40] Branch { DstBlock "b[6:5]" DstPort 1 } Branch { Points [0, 40] Branch { DstBlock "b[16:7]" DstPort 1 } Branch { Points [0, 40] DstBlock "b[26:17]" DstPort 1 } } } } } } Line { SrcBlock "b[7]" SrcPort 1 DstBlock "Concat" DstPort 1 } Line { SrcBlock "5LSB" SrcPort 1 Points [20, 0; 0, -25] DstBlock "Concat" DstPort 2 } Line { SrcBlock "Concat" SrcPort 1 DstBlock "ROM" DstPort 1 } Line { SrcBlock "7LSB" SrcPort 1 Points [95, 0] Branch { DstBlock "MCS" DstPort 1 } Branch { Points [0, 65] Branch { DstBlock "Relational" DstPort 1 } Branch { Points [0, 105] DstBlock "Relational1" DstPort 1 } } } Line { SrcBlock "b[6:5]" SrcPort 1 DstBlock "code_rate" DstPort 1 } Line { SrcBlock "b[4:3]" SrcPort 1 DstBlock "mod_sel" DstPort 1 } Line { SrcBlock "b[0]" SrcPort 1 Points [15, 0] Branch { DstBlock "Chan_BW" DstPort 1 } Branch { Points [0, 295] DstBlock "Convert" DstPort 1 } } Line { SrcBlock "b[26:17]" SrcPort 1 DstBlock "N_DBPS" DstPort 1 } Line { SrcBlock "b[16:7]" SrcPort 1 DstBlock "N_CBPS" DstPort 1 } Line { SrcBlock "b[2:1]" SrcPort 1 DstBlock "N_SS" DstPort 1 } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Unsupported" DstPort 1 } Line { SrcBlock "Convert" SrcPort 1 DstBlock "Logical1" DstPort 1 } Annotation { Name "IEEE 802.11-2012 Table 20-30\nSingle spatial stream 20MHz MCS indexes:\n\n0: BPSK 1/2\n1: QPSK 1/2\n2" ": QPSK 3/4\n3: 16-QAM 1/2\n4: 16-QAM 3/4\n5: 64-QAM 2/3\n6: 64-QAM 3/4\n7: 64-QAM 5/6\n\nMod Order values:\n0: B" "PSK\n1: QPSK\n2: 16-QAM\n3: 64-QAM\n\nCode Rate values:\n0: 1/2\n1: 2/3\n2: 3/4\n3: 5/6 (HT/VHT only)\n\nN_DBPS " "values:\nBPSK 1/2: 26\nQPSK 1/2: 52\nQPSK 3/4: 78\n16-QAM 1/2: 104\n16-QAM 3/4: 156\n64-QAM 2/3: 208\n64-QAM 3/4" ": 234\n64-QAM 5/6: 260" Position [965, 322] HorizontalAlignment "left" } Annotation { Name "Byte_6[7] = Channel bandwidth (0=20, 1=40)\nByte_3[6:0]: MCS (5LSB used here)" Position [131, 165] HorizontalAlignment "left" } Annotation { Name "% Ouptut word contents:\n% b[ 0]: Chan bandwidth\n% b[ 2: 1]: Num spatial streams\n% b[ 4: 3]: " "Mod order index\n% b[ 6: 5]: Code rate index\n% b[16: 7]: Coded bits per symbol per stream\n% b[26:17]: Data " "bits per symbol per stream" Position [445, 128] HorizontalAlignment "left" FontName "Consolas" FontSize 12 } Annotation { Name "MCS index values up to 76 are valid. But this block only decodes MCS indexes\nup to 31. This shortcut" " is based on observing no use of unequal-modulation\nMCS indexes in any actual system, and that all UQM schemes " "were dropped \nin 802.11ac.\n\nI'm technically cheating by calling the UQM MCS indexes invalid. The only real \n" "effect of this would be falling back on energy detection for deferring to UQM \nreceptions, since the rate*lengt" "h block won't attempt a deferral for \nMCS values declared invalid here." Position [342, 775] HorizontalAlignment "left" } Annotation { Name "PHY currently supports MCS 0-7 for BW=20" Position [789, 567] } } } Block { BlockType Reference Name "Relational" SID "10548" Ports [2, 1] Position [290, 555, 325, 595] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,40,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 40 40 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bfa = b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational1" SID "10549" Ports [2, 1] Position [290, 605, 325, 645] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,40,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 40 40 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bfa = b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational2" SID "10550" Ports [2, 1] Position [290, 460, 325, 500] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,40,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 40 40 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bfa = b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational3" SID "10551" Ports [2, 1] Position [290, 790, 325, 830] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,40,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 40 40 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bfa = b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational4" SID "10552" Ports [2, 1] Position [290, 840, 325, 880] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,40,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 40 40 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bfa = b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational5" SID "10553" Ports [2, 1] Position [290, 740, 325, 780] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,40,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 40 40 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bfa = b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational6" SID "11764" Ports [2, 1] Position [290, 295, 325, 335] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,40,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 40 40 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bfa = b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "TAIL" SID "10554" Ports [1, 1] Position [735, 822, 850, 858] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "TAIL" Location [2, 70, 2469, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "125" Block { BlockType Inport Name "B8" SID "10555" Position [300, 233, 330, 247] IconDisplay "Port number" } Block { BlockType Reference Name "6MSB" SID "10556" Ports [1, 1] Position [405, 232, 445, 248] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "6" boolean_output off mode "Upper Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 16 16 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant2" SID "10557" Ports [0, 1] Position [405, 254, 440, 276] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "35,22,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 22 22 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[14" ".33 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[11.33 11." "33 14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[8.33 8.33 11.33 11.33 " "8.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor" "('black');port_label('output',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational2" SID "10558" Ports [2, 1] Position [520, 230, 565, 265] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "45,35,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 35 35 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 35 35 0 ]);\npatch([10.875 18.1 23.1 28.1 33.1 23.1 15.875 10.875 ],[22.55 2" "2.55 27.55 22.55 27.55 27.55 27.55 22.55 ],[1 1 1 ]);\npatch([15.875 23.1 18.1 10.875 15.875 ],[17.55 17.55 22.5" "5 22.55 17.55 ],[0.931 0.946 0.973 ]);\npatch([10.875 18.1 23.1 15.875 10.875 ],[12.55 12.55 17.55 17.55 12.55 ]" ",[1 1 1 ]);\npatch([15.875 33.1 28.1 23.1 18.1 10.875 15.875 ],[7.55 7.55 12.55 7.55 12.55 12.55 7.55 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'" "\\bfa = b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Valid" SID "10559" Position [625, 243, 655, 257] IconDisplay "Port number" } Line { SrcBlock "B8" SrcPort 1 DstBlock "6MSB" DstPort 1 } Line { SrcBlock "6MSB" SrcPort 1 DstBlock "Relational2" DstPort 1 } Line { SrcBlock "Constant2" SrcPort 1 Points [25, 0; 0, -10] DstBlock "Relational2" DstPort 2 } Line { SrcBlock "Relational2" SrcPort 1 DstBlock "Valid" DstPort 1 } Annotation { Name "Ensure 6 TAIL bits (6 MSB of byte 8 here)\nare zero. Non-zero indicates bit error. In\nthis case we m" "ark HT-SIG as invalid, even\nif the checksum is ok." Position [368, 314] HorizontalAlignment "left" FontName "Consolas" FontSize 12 } } } Block { BlockType Outport Name "HT-SIG Valid" SID "10560" Position [1385, 738, 1415, 752] IconDisplay "Port number" } Block { BlockType Outport Name "HT-SIG Invalid" SID "10561" Position [1385, 608, 1415, 622] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "Unsupported" SID "10562" Position [1260, 493, 1290, 507] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "Length" SID "10563" Position [1260, 548, 1290, 562] Port "4" IconDisplay "Port number" } Block { BlockType Outport Name "MCS" SID "10564" Position [1260, 268, 1290, 282] Port "5" IconDisplay "Port number" } Block { BlockType Outport Name "mod_sel" SID "10565" Position [1260, 298, 1290, 312] Port "6" IconDisplay "Port number" } Block { BlockType Outport Name "code_rate" SID "10566" Position [1260, 328, 1290, 342] Port "7" IconDisplay "Port number" } Block { BlockType Outport Name "Chan_BW" SID "10567" Position [1260, 448, 1290, 462] Port "8" IconDisplay "Port number" } Block { BlockType Outport Name "N_DBPS" SID "10568" Position [1260, 388, 1290, 402] Port "9" IconDisplay "Port number" } Block { BlockType Outport Name "N_CBPS" SID "10569" Position [1260, 358, 1290, 372] Port "10" IconDisplay "Port number" } Block { BlockType Outport Name "N_SS" SID "10570" Position [1260, 418, 1290, 432] Port "11" IconDisplay "Port number" } Block { BlockType Outport Name "HT-SIG Done" SID "10571" Position [935, 1033, 965, 1047] Port "12" IconDisplay "Port number" } Line { SrcBlock "rst" SrcPort 1 Points [450, 0; 0, 65] Branch { Points [0, 95] Branch { DstBlock "DOUT1" DstPort 2 } Branch { Points [0, 50] Branch { DstBlock "DOUT2" DstPort 2 } Branch { Points [0, 135] Branch { DstBlock "DOUT3" DstPort 2 } Branch { Points [0, 50] Branch { DstBlock "DOUT4" DstPort 2 } Branch { Points [0, 50] Branch { Points [0, 160] DstBlock "CRC8 Calc" DstPort 4 } Branch { DstBlock "DOUT5" DstPort 2 } } } } } } Branch { DstBlock "DOUT" DstPort 2 } } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "DOUT1" DstPort 3 } Line { SrcBlock "Logical2" SrcPort 1 DstBlock "DOUT" DstPort 3 } Line { SrcBlock "Logical" SrcPort 1 DstBlock "DOUT2" DstPort 3 } Line { SrcBlock "Relational" SrcPort 1 DstBlock "Logical1" DstPort 2 } Line { SrcBlock "Relational2" SrcPort 1 DstBlock "Logical2" DstPort 2 } Line { SrcBlock "Relational1" SrcPort 1 DstBlock "Logical" DstPort 2 } Line { SrcBlock "Constant2" SrcPort 1 DstBlock "Relational2" DstPort 2 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Relational1" DstPort 2 } Line { SrcBlock "Constant" SrcPort 1 DstBlock "Relational" DstPort 2 } Line { SrcBlock "byte" SrcPort 1 Points [460, 0; 0, 85] Branch { Points [0, 95] Branch { DstBlock "DOUT1" DstPort 1 } Branch { Points [0, 50] Branch { DstBlock "DOUT2" DstPort 1 } Branch { Points [0, 135] Branch { Points [0, 50] Branch { DstBlock "DOUT4" DstPort 1 } Branch { Points [0, 50] Branch { DstBlock "DOUT5" DstPort 1 } Branch { Points [0, 150] DstBlock "CRC8 Calc" DstPort 3 } } } Branch { DstBlock "DOUT3" DstPort 1 } } } } Branch { DstBlock "DOUT" DstPort 1 } } Line { SrcBlock "byte_ind" SrcPort 1 Points [135, 0] Branch { Points [0, 95] Branch { DstBlock "Relational" DstPort 1 } Branch { Points [0, 50] Branch { DstBlock "Relational1" DstPort 1 } Branch { Points [0, 135] Branch { Points [0, 50] Branch { DstBlock "Relational3" DstPort 1 } Branch { Points [0, 50] Branch { DstBlock "Relational4" DstPort 1 } Branch { Points [0, 75] DstBlock "CRC8 Calc" DstPort 1 } } } Branch { DstBlock "Relational5" DstPort 1 } } } } Branch { DstBlock "Relational2" DstPort 1 } } Line { Labels [0, 0] SrcBlock "byte_valid" SrcPort 1 Points [225, 0; 0, 35] Branch { Points [0, 95] Branch { DstBlock "Logical1" DstPort 1 } Branch { Points [0, 50] Branch { DstBlock "Logical" DstPort 1 } Branch { Points [0, 135] Branch { Points [0, 50] Branch { DstBlock "Logical4" DstPort 1 } Branch { Points [0, 50] Branch { DstBlock "Logical3" DstPort 1 } Branch { Points [0, 105] DstBlock "CRC8 Calc" DstPort 2 } } } Branch { DstBlock "Logical5" DstPort 1 } } } } Branch { DstBlock "Logical2" DstPort 1 } } Line { SrcBlock "Logical4" SrcPort 1 DstBlock "DOUT4" DstPort 3 } Line { SrcBlock "Logical5" SrcPort 1 DstBlock "DOUT3" DstPort 3 } Line { SrcBlock "Logical3" SrcPort 1 Points [160, 0] Branch { Points [0, 185] DstBlock "Delay" DstPort 1 } Branch { DstBlock "DOUT5" DstPort 3 } } Line { SrcBlock "Relational3" SrcPort 1 DstBlock "Logical4" DstPort 2 } Line { SrcBlock "Relational5" SrcPort 1 DstBlock "Logical5" DstPort 2 } Line { SrcBlock "Relational4" SrcPort 1 DstBlock "Logical3" DstPort 2 } Line { SrcBlock "Constant5" SrcPort 1 DstBlock "Relational5" DstPort 2 } Line { SrcBlock "Constant4" SrcPort 1 DstBlock "Relational4" DstPort 2 } Line { SrcBlock "Constant3" SrcPort 1 DstBlock "Relational3" DstPort 2 } Line { SrcBlock "DOUT" SrcPort 1 Points [50, 0] Branch { Points [0, 260] DstBlock "HT-SIG Flags" DstPort 1 } Branch { Points [0, -130] DstBlock "MCS Decode" DstPort 1 } } Line { SrcBlock "DOUT1" SrcPort 1 DstBlock "HT Length" DstPort 1 } Line { SrcBlock "DOUT2" SrcPort 1 Points [20, 0; 0, -20] DstBlock "HT Length" DstPort 2 } Line { SrcBlock "DOUT3" SrcPort 1 Points [60, 0] Branch { DstBlock "HT-SIG Flags" DstPort 2 } Branch { Points [0, -280] DstBlock "MCS Decode" DstPort 2 } } Line { Name "Length" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 DstBlock "HT-SIG Decode" DstPort 1 } Line { Name "HT-SIG Valid" Labels [0, 0] SrcBlock "Gateway Out10" SrcPort 1 DstBlock "HT-SIG Decode" DstPort 8 } Line { Name "MCS" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 DstBlock "HT-SIG Decode" DstPort 2 } Line { Name "Mod Order" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 DstBlock "HT-SIG Decode" DstPort 3 } Line { Name "Code Rate" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 DstBlock "HT-SIG Decode" DstPort 4 } Line { SrcBlock "MCS Decode" SrcPort 1 Points [90, 0] Branch { DstBlock "MCS" DstPort 1 } Branch { Points [0, -160] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "MCS Decode" SrcPort 2 Points [95, 0] Branch { DstBlock "mod_sel" DstPort 1 } Branch { Points [0, -165] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "MCS Decode" SrcPort 3 Points [100, 0] Branch { DstBlock "code_rate" DstPort 1 } Branch { Points [0, -170] DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "MCS Decode" SrcPort 4 DstBlock "N_CBPS" DstPort 1 } Line { SrcBlock "MCS Decode" SrcPort 5 DstBlock "N_DBPS" DstPort 1 } Line { SrcBlock "MCS Decode" SrcPort 6 DstBlock "N_SS" DstPort 1 } Line { SrcBlock "MCS Decode" SrcPort 7 Points [110, 0] Branch { DstBlock "Chan_BW" DstPort 1 } Branch { Points [0, -265] DstBlock "Gateway Out5" DstPort 1 } } Line { SrcBlock "HT Length" SrcPort 1 Points [85, 0] Branch { DstBlock "Length" DstPort 1 } Branch { Points [0, -465] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "From" SrcPort 1 Points [10, 0] Branch { DstBlock "Logical6" DstPort 1 } Branch { Points [0, 130] DstBlock "Logical8" DstPort 1 } } Line { SrcBlock "Logical7" SrcPort 1 Points [20, 0] Branch { Points [0, -130] DstBlock "Inverter4" DstPort 1 } Branch { DstBlock "Logical8" DstPort 2 } } Line { SrcBlock "Logical6" SrcPort 1 Points [30, 0] Branch { DstBlock "HT-SIG Invalid" DstPort 1 } Branch { Points [0, -375] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "Logical8" SrcPort 1 Points [40, 0] Branch { DstBlock "HT-SIG Valid" DstPort 1 } Branch { Points [0, -480] DstBlock "Gateway Out10" DstPort 1 } } Line { SrcBlock "MCS Decode" SrcPort 9 Points [10, 0; 0, 225; 80, 0] Branch { Points [0, 100] DstBlock "Gateway Out8" DstPort 1 } Branch { DstBlock "Logical7" DstPort 2 } } Line { SrcBlock "CRC8 Calc" SrcPort 1 Points [20, 0; 0, -50] Branch { DstBlock "Gateway Out12" DstPort 1 } Branch { Points [0, -130] DstBlock "Logical7" DstPort 5 } } Line { SrcBlock "Delay" SrcPort 1 DstBlock "Delay1" DstPort 1 } Line { SrcBlock "HT-SIG Flags" SrcPort 1 Points [115, 0; 0, -210] DstBlock "Logical9" DstPort 3 } Line { SrcBlock "MCS Decode" SrcPort 8 Points [115, 0] Branch { Points [0, -270] DstBlock "Gateway Out6" DstPort 1 } Branch { DstBlock "Logical9" DstPort 1 } } Line { Name "Chan BW" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 DstBlock "HT-SIG Decode" DstPort 5 } Line { Name "Unsupported" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 DstBlock "HT-SIG Decode" DstPort 6 } Line { SrcBlock "Delay1" SrcPort 1 Points [70, 0] Branch { Points [0, 45] DstBlock "Goto2" DstPort 1 } Branch { DstBlock "HT-SIG Done" DstPort 1 } } Line { SrcBlock "DOUT4" SrcPort 1 Points [70, 0] DstBlock "HT-SIG Flags" DstPort 3 } Line { SrcBlock "Logical9" SrcPort 1 DstBlock "Unsupported" DstPort 1 } Line { Name "HT-SIG Invalid" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 DstBlock "HT-SIG Decode" DstPort 7 } Line { SrcBlock "Inverter4" SrcPort 1 DstBlock "Logical6" DstPort 2 } Line { SrcBlock "HT-SIG Flags" SrcPort 2 Points [40, 0] Branch { Points [0, 110] DstBlock "Gateway Out9" DstPort 1 } Branch { DstBlock "Logical7" DstPort 3 } } Line { SrcBlock "DOUT5" SrcPort 1 DstBlock "TAIL" DstPort 1 } Line { SrcBlock "TAIL" SrcPort 1 Points [10, 0] Branch { Points [0, 50] DstBlock "Gateway Out11" DstPort 1 } Branch { Points [0, -70] DstBlock "Logical7" DstPort 4 } } Line { SrcBlock "HT Length" SrcPort 2 Points [100, 0; 0, -85] DstBlock "Logical9" DstPort 2 } Line { Name "MCS valid" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 DstBlock "HT-SIG Decode Errs" DstPort 1 } Line { Name "Flags valid" Labels [0, 0] SrcBlock "Gateway Out9" SrcPort 1 DstBlock "HT-SIG Decode Errs" DstPort 2 } Line { Name "Tail valid" Labels [0, 0] SrcBlock "Gateway Out11" SrcPort 1 DstBlock "HT-SIG Decode Errs" DstPort 3 } Line { Name "CRC valid" Labels [0, 0] SrcBlock "Gateway Out12" SrcPort 1 DstBlock "HT-SIG Decode Errs" DstPort 4 } Line { SrcBlock "L-SIG Rate" SrcPort 1 DstBlock "Relational6" DstPort 1 } Line { SrcBlock "Constant6" SrcPort 1 DstBlock "Relational6" DstPort 2 } Line { SrcBlock "Relational6" SrcPort 1 Points [180, 0; 0, 365; 510, 0; 0, 45] Branch { DstBlock "Logical7" DstPort 1 } Branch { Points [0, 215] DstBlock "Gateway Out13" DstPort 1 } } Line { Name "L-SIG Rate" Labels [0, 0] SrcBlock "Gateway Out13" SrcPort 1 DstBlock "HT-SIG Decode Errs" DstPort 5 } Annotation { Name "HTMF waveform requires L-SIG.RATE = 6Mb. Ignore HT-SIG entirely\nif the L-SIG.RATE is anything else." Position [286, 275] } } } Block { BlockType Reference Name "Logical1" SID "10572" Ports [3, 1] Position [880, 1077, 915, 1123] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,46,3,1,white,blue,0,98d76266,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 46 46 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 46 46 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[28.55 28.55 33." "55 28.55 33.55 33.55 33.55 28.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[23.55 23.55 28.55 28.55 23." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[18.55 18.55 23.55 23.55 18.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[13.55 13.55 18.55 13.55 18.55 18.55 13.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\ncolor('black');disp(" "'and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "10573" Ports [3, 1] Position [1005, 1257, 1040, 1293] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,36,3,1,white,blue,0,a2abe52d,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 36 36 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 36 36 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[23.55 23.55 28." "55 23.55 28.55 28.55 28.55 23.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[18.55 18.55 23.55 23.55 18." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[13.55 13.55 18.55 18.55 13.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[8.55 8.55 13.55 8.55 13.55 13.55 8.55 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\ncolor('black');disp('or'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical3" SID "10574" Ports [2, 1] Position [705, 855, 740, 890] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,35,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 35 35 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 35 35 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[22.55 22.55 27." "55 22.55 27.55 27.55 27.55 22.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[17.55 17.55 22.55 22.55 17." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[12.55 12.55 17.55 17.55 12.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[7.55 7.55 12.55 7.55 12.55 12.55 7.55 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('and')" ";\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical4" SID "10575" Ports [3, 1] Position [1040, 1033, 1075, 1167] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,134,3,1,white,blue,0,a2abe52d,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 134 134 0 ],[0.77 0.82 0" ".91 ]);\nplot([0 35 35 0 0 ],[0 0 134 134 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[72.55 72.55" " 77.55 72.55 77.55 77.55 77.55 72.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[67.55 67.55 72.55 72.55" " 67.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[62.55 62.55 67.55 67.55 62.55 ],[1 1 1 ]);" "\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[57.55 57.55 62.55 57.55 62.55 62.55 57.55 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\ncolor('black');d" "isp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical5" SID "10576" Ports [2, 1] Position [880, 1125, 915, 1160] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,35,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 35 35 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 35 35 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[22.55 22.55 27." "55 22.55 27.55 27.55 27.55 22.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[17.55 17.55 22.55 22.55 17." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[12.55 12.55 17.55 17.55 12.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[7.55 7.55 12.55 7.55 12.55 12.55 7.55 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('and')" ";\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical6" SID "10915" Ports [2, 1] Position [1005, 1317, 1040, 1353] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,36,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 36 36 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 36 36 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[23.55 23.55 28." "55 23.55 28.55 28.55 28.55 23.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[18.55 18.55 23.55 23.55 18." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[13.55 13.55 18.55 18.55 13.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[8.55 8.55 13.55 8.55 13.55 13.55 8.55 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('or');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux1" SID "10577" Ports [3, 1] Position [1105, 878, 1125, 942] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "20,64,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 9.14286 54.8571 64 0 ],[0." "77 0.82 0.91 ]);\nplot([0 20 20 0 0 ],[0 9.14286 54.8571 64 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5" ".55 ],[34.22 34.22 36.22 34.22 36.22 36.22 36.22 34.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[32.22 32." "22 34.22 34.22 32.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[30.22 30.22 32.22 32.22 30.22 ]" ",[1 1 1 ]);\npatch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[28.22 28.22 30.22 28.22 30.22 30.22 28.22 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3,'d1'" ");\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux2" SID "10578" Ports [3, 1] Position [1105, 518, 1125, 582] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "20,64,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 9.14286 54.8571 64 0 ],[0." "77 0.82 0.91 ]);\nplot([0 20 20 0 0 ],[0 9.14286 54.8571 64 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5" ".55 ],[34.22 34.22 36.22 34.22 36.22 36.22 36.22 34.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[32.22 32." "22 34.22 34.22 32.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[30.22 30.22 32.22 32.22 30.22 ]" ",[1 1 1 ]);\npatch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[28.22 28.22 30.22 28.22 30.22 30.22 28.22 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3,'d1'" ");\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux3" SID "10579" Ports [3, 1] Position [1105, 788, 1125, 852] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "20,64,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 9.14286 54.8571 64 0 ],[0." "77 0.82 0.91 ]);\nplot([0 20 20 0 0 ],[0 9.14286 54.8571 64 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5" ".55 ],[34.22 34.22 36.22 34.22 36.22 36.22 36.22 34.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[32.22 32." "22 34.22 34.22 32.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[30.22 30.22 32.22 32.22 30.22 ]" ",[1 1 1 ]);\npatch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[28.22 28.22 30.22 28.22 30.22 30.22 28.22 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3,'d1'" ");\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux4" SID "10580" Ports [3, 1] Position [1105, 293, 1125, 357] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "20,64,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 9.14286 54.8571 64 0 ],[0." "77 0.82 0.91 ]);\nplot([0 20 20 0 0 ],[0 9.14286 54.8571 64 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5" ".55 ],[34.22 34.22 36.22 34.22 36.22 36.22 36.22 34.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[32.22 32." "22 34.22 34.22 32.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[30.22 30.22 32.22 32.22 30.22 ]" ",[1 1 1 ]);\npatch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[28.22 28.22 30.22 28.22 30.22 30.22 28.22 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3,'d1'" ");\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux5" SID "10581" Ports [3, 1] Position [1105, 673, 1125, 737] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "20,64,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 9.14286 54.8571 64 0 ],[0." "77 0.82 0.91 ]);\nplot([0 20 20 0 0 ],[0 9.14286 54.8571 64 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5" ".55 ],[34.22 34.22 36.22 34.22 36.22 36.22 36.22 34.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[32.22 32." "22 34.22 34.22 32.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[30.22 30.22 32.22 32.22 30.22 ]" ",[1 1 1 ]);\npatch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[28.22 28.22 30.22 28.22 30.22 30.22 28.22 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3,'d1'" ");\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux6" SID "10582" Ports [3, 1] Position [1105, 218, 1125, 282] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "20,64,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 9.14286 54.8571 64 0 ],[0." "77 0.82 0.91 ]);\nplot([0 20 20 0 0 ],[0 9.14286 54.8571 64 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5" ".55 ],[34.22 34.22 36.22 34.22 36.22 36.22 36.22 34.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[32.22 32." "22 34.22 34.22 32.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[30.22 30.22 32.22 32.22 30.22 ]" ",[1 1 1 ]);\npatch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[28.22 28.22 30.22 28.22 30.22 30.22 28.22 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3,'d1'" ");\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux7" SID "10583" Ports [3, 1] Position [1105, 368, 1125, 432] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "20,64,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 9.14286 54.8571 64 0 ],[0." "77 0.82 0.91 ]);\nplot([0 20 20 0 0 ],[0 9.14286 54.8571 64 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5" ".55 ],[34.22 34.22 36.22 34.22 36.22 36.22 36.22 34.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[32.22 32." "22 34.22 34.22 32.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[30.22 30.22 32.22 32.22 30.22 ]" ",[1 1 1 ]);\npatch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[28.22 28.22 30.22 28.22 30.22 30.22 28.22 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3,'d1'" ");\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux8" SID "10584" Ports [3, 1] Position [1105, 443, 1125, 507] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "20,64,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 9.14286 54.8571 64 0 ],[0." "77 0.82 0.91 ]);\nplot([0 20 20 0 0 ],[0 9.14286 54.8571 64 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5" ".55 ],[34.22 34.22 36.22 34.22 36.22 36.22 36.22 34.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[32.22 32." "22 34.22 34.22 32.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[30.22 30.22 32.22 32.22 30.22 ]" ",[1 1 1 ]);\npatch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[28.22 28.22 30.22 28.22 30.22 30.22 28.22 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3,'d1'" ");\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux9" SID "10585" Ports [3, 1] Position [1105, 603, 1125, 667] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "20,64,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 9.14286 54.8571 64 0 ],[0." "77 0.82 0.91 ]);\nplot([0 20 20 0 0 ],[0 9.14286 54.8571 64 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5" ".55 ],[34.22 34.22 36.22 34.22 36.22 36.22 36.22 34.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[32.22 32." "22 34.22 34.22 32.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[30.22 30.22 32.22 32.22 30.22 ]" ",[1 1 1 ]);\npatch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[28.22 28.22 30.22 28.22 30.22 30.22 28.22 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3,'d1'" ");\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "PHY_RX_DATA.BYTENUM1" SID "11771" Ports [1, 1] Position [1715, 864, 1750, 876] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "PHY_RX_DATA.BYTENUM2" SID "11772" Ports [1, 1] Position [1715, 914, 1750, 926] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "PHY_RX_DATA.BYTENUM3" SID "11773" Ports [1, 1] Position [1715, 964, 1750, 976] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "PHY_RX_DATA.BYTENUM4" SID "11774" Ports [1, 1] Position [1725, 1014, 1760, 1026] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "Register" SID "10586" Ports [1, 1] Position [1355, 886, 1385, 914] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,28,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 18.44 22.4" "4 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 18.44 14.44 ]," "[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\npatch([10.1" " 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\n" "color('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: en" "d icon text');" } Block { BlockType Reference Name "Register1" SID "10587" Ports [1, 1] Position [1170, 536, 1200, 564] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,28,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 18.44 22.4" "4 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 18.44 14.44 ]," "[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\npatch([10.1" " 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\n" "color('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: en" "d icon text');" } Block { BlockType Reference Name "Register10" SID "10588" Ports [1, 1] Position [1170, 691, 1200, 719] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,28,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 18.44 22.4" "4 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 18.44 14.44 ]," "[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\npatch([10.1" " 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\n" "color('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: en" "d icon text');" } Block { BlockType Reference Name "Register11" SID "10589" Ports [1, 1] Position [1170, 806, 1200, 834] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,28,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 18.44 22.4" "4 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 18.44 14.44 ]," "[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\npatch([10.1" " 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\n" "color('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: en" "d icon text');" } Block { BlockType Reference Name "Register12" SID "10590" Ports [1, 1] Position [1170, 566, 1200, 594] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,28,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 18.44 22.4" "4 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 18.44 14.44 ]," "[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\npatch([10.1" " 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\n" "color('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: en" "d icon text');" } Block { BlockType Reference Name "Register13" SID "10591" Ports [1, 1] Position [1170, 16, 1200, 44] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,28,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 18.44 22.4" "4 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 18.44 14.44 ]," "[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\npatch([10.1" " 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\n" "color('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: en" "d icon text');" } Block { BlockType Reference Name "Register15" SID "11768" Ports [1, 1] Position [1235, 1346, 1265, 1374] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,28,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 18.44 22.4" "4 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 18.44 14.44 ]," "[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\npatch([10.1" " 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\n" "color('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: en" "d icon text');" } Block { BlockType Reference Name "Register16" SID "11775" Ports [1, 1] Position [1240, 1446, 1270, 1474] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,28,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 18.44 22.4" "4 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 18.44 14.44 ]," "[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\npatch([10.1" " 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\n" "color('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: en" "d icon text');" } Block { BlockType Reference Name "Register2" SID "10592" Ports [1, 1] Position [1170, 461, 1200, 489] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,28,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 18.44 22.4" "4 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 18.44 14.44 ]," "[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\npatch([10.1" " 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\n" "color('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: en" "d icon text');" } Block { BlockType Reference Name "Register3" SID "10593" Ports [1, 1] Position [1170, 386, 1200, 414] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,28,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 18.44 22.4" "4 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 18.44 14.44 ]," "[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\npatch([10.1" " 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\n" "color('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: en" "d icon text');" } Block { BlockType Reference Name "Register4" SID "10594" Ports [1, 1] Position [1170, 311, 1200, 339] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,28,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 18.44 22.4" "4 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 18.44 14.44 ]," "[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\npatch([10.1" " 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\n" "color('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: en" "d icon text');" } Block { BlockType Reference Name "Register5" SID "10595" Ports [1, 1] Position [1170, 236, 1200, 264] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,28,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 18.44 22.4" "4 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 18.44 14.44 ]," "[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\npatch([10.1" " 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\n" "color('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: en" "d icon text');" } Block { BlockType Reference Name "Register6" SID "10596" Ports [1, 1] Position [1170, 156, 1200, 184] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,28,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 18.44 22.4" "4 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 18.44 14.44 ]," "[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\npatch([10.1" " 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\n" "color('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: en" "d icon text');" } Block { BlockType Reference Name "Register7" SID "10597" Ports [1, 1] Position [1170, 86, 1200, 114] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,28,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 18.44 22.4" "4 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 18.44 14.44 ]," "[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\npatch([10.1" " 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\n" "color('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: en" "d icon text');" } Block { BlockType Reference Name "Register8" SID "10598" Ports [1, 1] Position [1170, 46, 1200, 74] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,28,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 18.44 22.4" "4 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 18.44 14.44 ]," "[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\npatch([10.1" " 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\n" "color('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: en" "d icon text');" } Block { BlockType Reference Name "Register9" SID "10599" Ports [1, 1] Position [1170, 621, 1200, 649] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,28,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 18.44 22.4" "4 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 18.44 14.44 ]," "[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\npatch([10.1" " 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\n" "color('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: en" "d icon text');" } Block { BlockType SubSystem Name "S-R Latch1" SID "10600" Ports [2, 1] Position [800, 864, 835, 911] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "S-R Latch1" Location [351, 366, 2001, 1172] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "10601" Position [140, 103, 170, 117] IconDisplay "Port number" } Block { BlockType Inport Name "R" SID "10602" Position [140, 88, 170, 102] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "10603" Ports [0, 1] Position [195, 71, 210, 89] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "15,18,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11.22 " "13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 9.22 " "],[0.931 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([4.55 " "11.44 9.44 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "10604" Ports [1, 1] Position [210, 86, 235, 104] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('outpu" "t',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "10605" Ports [1, 1] Position [210, 101, 235, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('outpu" "t',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "10606" Ports [3, 1] Position [255, 71, 300, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "10607" Position [325, 88, 355, 102] IconDisplay "Port number" } Line { SrcBlock "Convert2" SrcPort 1 DstBlock "Register2" DstPort 3 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "S" SrcPort 1 DstBlock "Convert2" DstPort 1 } } } Block { BlockType Scope Name "SIG Decode Err" SID "11770" Ports [4] Position [1805, 848, 1850, 1042] ZOrder -3 Floating off Location [-1679, 202, 1, 1206] Open off NumInputPorts "4" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" } List { ListType ScopeGraphics FigureColor "[0.5 0.5 0.5]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "32908 " YMin "0~0~0~0" YMax "1~275~1100~275" SaveName "ScopeData54" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType SubSystem Name "SIGNAL Decode" SID "10608" Ports [4, 11] Position [205, 185, 320, 355] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "SIGNAL Decode" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "124" Block { BlockType Inport Name "byte_ind" SID "10609" Position [85, 468, 115, 482] IconDisplay "Port number" } Block { BlockType Inport Name "byte_valid" SID "10610" Position [85, 438, 115, 452] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "byte" SID "10611" Position [85, 378, 115, 392] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "rst" SID "10612" Position [85, 408, 115, 422] Port "4" IconDisplay "Port number" } Block { BlockType SubSystem Name "4b Shift Reg" SID "10613" Ports [1, 1] Position [1290, 618, 1350, 652] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "4b Shift Reg" Location [1520, 1301, 2132, 1572] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "En" SID "10614" Position [350, 368, 380, 382] IconDisplay "Port number" } Block { BlockType Reference Name "Assert" SID "10615" Ports [1, 1] Position [615, 385, 675, 415] BlockMirror on NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Assert" SourceType "Xilinx Assert Block" infoedit "Asserts a user-defined sample rate and/or type on a signal.

Hardware notes: In hardware th" "is block costs nothing." assert_type on type_source "Explicitly" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" assert_rate on rate_source "Explicitly" period "1" output_port on has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "assert" sg_icon_stat "60,30,1,1,white,blue,0,9657e937,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 30 30 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\npatch([21.1 26.88 30.88 34.88 38.88 30.88 25.1 21.1 ],[19.44 19" ".44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([25.1 30.88 26.88 21.1 25.1 ],[15.44 15.44 19.44 19." "44 15.44 ],[0.931 0.946 0.973 ]);\npatch([21.1 26.88 30.88 25.1 21.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]" ");\npatch([25.1 38.88 34.88 30.88 26.88 21.1 25.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 " "]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp" "('Assert');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Concat" SID "10616" Ports [4, 1] Position [515, 250, 845, 280] BlockRotation 270 ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point " "at zero." num_inputs "4" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "330,30,4,1,white,blue,0,47d3d416,up,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 330 330 0 0 ],[0 0 30 30 0 ],[0.77 0." "82 0.91 ]);\nplot([0 330 330 0 0 ],[0 0 30 30 0 ]);\npatch([156.1 161.88 165.88 169.88 173.88 165.88 160.1 156.1" " ],[19.44 19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([160.1 165.88 161.88 156.1 160.1 ],[15.4" "4 15.44 19.44 19.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([156.1 161.88 165.88 160.1 156.1 ],[11.44 11.44 15.44 " "15.44 11.44 ],[1 1 1 ]);\npatch([160.1 173.88 169.88 165.88 161.88 156.1 160.1 ],[7.44 7.44 11.44 7.44 11.44 11." "44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon tex" "t');\ncolor('black');port_label('input',1,'hi');\n\n\ncolor('black');port_label('input',4,'lo');\n\ncolor('black" "');disp('\\fontsize{20}\\}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "DOUT1" SID "10617" Ports [2, 1] Position [585, 318, 620, 362] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,44,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 44 44 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[27.55 27." "55 32.55 27.55 32.55 32.55 32.55 27.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[22.55 22.55 27.55 2" "7.55 22.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[17.55 17.55 22.55 22.55 17.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[12.55 12.55 17.55 12.55 17.55 17.55 12.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q" "');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "DOUT2" SID "10618" Ports [2, 1] Position [505, 318, 540, 362] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "1" rst off en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,44,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 44 44 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[27.55 27." "55 32.55 27.55 32.55 32.55 32.55 27.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[22.55 22.55 27.55 2" "7.55 22.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[17.55 17.55 22.55 22.55 17.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[12.55 12.55 17.55 12.55 17.55 17.55 12.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q" "');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "DOUT3" SID "10619" Ports [2, 1] Position [665, 318, 700, 362] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,44,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 44 44 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[27.55 27." "55 32.55 27.55 32.55 32.55 32.55 27.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[22.55 22.55 27.55 2" "7.55 22.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[17.55 17.55 22.55 22.55 17.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[12.55 12.55 17.55 12.55 17.55 17.55 12.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q" "');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "DOUT4" SID "10620" Ports [2, 1] Position [745, 318, 780, 362] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,44,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 44 44 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[27.55 27." "55 32.55 27.55 32.55 32.55 32.55 27.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[22.55 22.55 27.55 2" "7.55 22.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[17.55 17.55 22.55 22.55 17.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[12.55 12.55 17.55 12.55 17.55 17.55 12.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q" "');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Posedge3" SID "10621" Ports [1, 1] Position [415, 363, 470, 387] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Posedge3" Location [88, 301, 2330, 1301] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "10622" Position [200, 253, 230, 267] IconDisplay "Port number" } Block { BlockType Reference Name "Delay" SID "10623" Ports [1, 1] Position [425, 153, 460, 177] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. " "If register retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[15" ".33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.33 12." "33 15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 12.33 " "9.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\nc" "olor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "10624" Ports [1, 1] Position [490, 156, 515, 174] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "10625" Ports [2, 1] Position [540, 151, 585, 204] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,53,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 53 53 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 53 53 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[32.66 3" "2.66 38.66 32.66 38.66 38.66 38.66 32.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[26.66 26.66 32.66 " "32.66 26.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[20.66 20.66 26.66 26.66 20.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[14.66 14.66 20.66 14.66 20.66 20.66 14.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('" "black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "10626" Position [610, 173, 640, 187] IconDisplay "Port number" } Line { SrcBlock "Delay" SrcPort 1 DstBlock "Inverter" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "D" SrcPort 1 Points [150, 0; 0, -70] Branch { Points [0, -25] DstBlock "Delay" DstPort 1 } Branch { DstBlock "Logical1" DstPort 2 } } Annotation { Name "Rising Edge Detection" Position [500, 112] } } } Block { BlockType Outport Name "Q" SID "10627" Position [670, 210, 700, 225] BlockRotation 270 IconDisplay "Port number" } Line { SrcBlock "Assert" SrcPort 1 Points [-130, 0; 0, -70] DstBlock "DOUT2" DstPort 1 } Line { SrcBlock "Concat" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "En" SrcPort 1 DstBlock "Posedge3" DstPort 1 } Line { SrcBlock "Posedge3" SrcPort 1 Points [15, 0] Branch { Points [80, 0] Branch { Points [80, 0] Branch { Points [80, 0] DstBlock "DOUT4" DstPort 2 } Branch { DstBlock "DOUT3" DstPort 2 } } Branch { DstBlock "DOUT1" DstPort 2 } } Branch { DstBlock "DOUT2" DstPort 2 } } Line { SrcBlock "DOUT3" SrcPort 1 Points [15, 0; 0, -10] Branch { DstBlock "DOUT4" DstPort 1 } Branch { DstBlock "Concat" DstPort 3 } } Line { SrcBlock "DOUT1" SrcPort 1 Points [15, 0; 0, -10] Branch { DstBlock "DOUT3" DstPort 1 } Branch { DstBlock "Concat" DstPort 2 } } Line { SrcBlock "DOUT4" SrcPort 1 Points [15, 0] Branch { Points [30, 0; 0, 60] DstBlock "Assert" DstPort 1 } Branch { DstBlock "Concat" DstPort 4 } } Line { SrcBlock "DOUT2" SrcPort 1 Points [15, 0; 0, -10] Branch { DstBlock "Concat" DstPort 1 } Branch { DstBlock "DOUT1" DstPort 1 } } } } Block { BlockType Reference Name "Constant" SID "10628" Ports [0, 1] Position [155, 759, 180, 781] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,22,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 22 22 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[14.33 " "14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 1 " "1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('output',1,'1');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant1" SID "10629" Ports [0, 1] Position [155, 809, 180, 831] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "2" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,22,0,1,white,blue,0,fca86624,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 22 22 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[14.33 " "14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 1 " "1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('output',1,'2');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant2" SID "10630" Ports [0, 1] Position [155, 484, 180, 506] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,22,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 22 22 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[14.33 " "14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 1 " "1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('output',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant3" SID "11762" Ports [0, 1] Position [410, 287, 435, 303] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "13" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "8" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period on period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,16,0,1,white,blue,0,e89bb8cb,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 16 16 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[10.22 10" ".22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[8.22 8.22 10.22 10.22" " 8.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output'" ",1,'13');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "DOUT" SID "10631" Ports [3, 1] Position [425, 443, 460, 487] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "hex2dec('6B')" rst on en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,44,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 44 44 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[27.55 27." "55 32.55 27.55 32.55 32.55 32.55 27.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[22.55 22.55 27.55 2" "7.55 22.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[17.55 17.55 22.55 22.55 17.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[12.55 12.55 17.55 12.55 17.55 17.55 12.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'e" "n');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "DOUT1" SID "10632" Ports [3, 1] Position [425, 718, 460, 762] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "hex2dec('07')" rst on en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,44,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 44 44 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[27.55 27." "55 32.55 27.55 32.55 32.55 32.55 27.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[22.55 22.55 27.55 2" "7.55 22.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[17.55 17.55 22.55 22.55 17.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[12.55 12.55 17.55 12.55 17.55 17.55 12.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'e" "n');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "DOUT2" SID "10633" Ports [3, 1] Position [425, 768, 460, 812] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "hex2dec('00')" rst on en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,44,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 44 44 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[27.55 27." "55 32.55 27.55 32.55 32.55 32.55 27.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[22.55 22.55 27.55 2" "7.55 22.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[17.55 17.55 22.55 22.55 17.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[12.55 12.55 17.55 12.55 17.55 17.55 12.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'e" "n');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "DOUT6" SID "10634" Ports [1, 1] Position [1405, 620, 1435, 650] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 30 30 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 30 30 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 19.4" "4 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 19.44 " "15.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\np" "atch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('in" "put',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf" "('','COMMENT: end icon text');" } Block { BlockType Reference Name "DOUT7" SID "10635" Ports [1, 1] Position [1480, 620, 1510, 650] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 30 30 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 30 30 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 19.4" "4 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 19.44 " "15.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\np" "atch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('in" "put',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf" "('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay" SID "10636" Ports [1, 1] Position [425, 981, 455, 1009] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "30,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 18.4" "4 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 18.44 " "14.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\np" "atch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-" "1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "10637" Position [985, 549, 1135, 571] ZOrder -9 ShowName off GotoTag "LAST_SIG_BYTE_DONE" } Block { BlockType From Name "From1" SID "10638" Position [990, 724, 1140, 746] ZOrder -9 ShowName off GotoTag "LAST_SIG_BYTE_DONE" } Block { BlockType From Name "From2" SID "10639" Position [1020, 119, 1170, 141] ZOrder -9 ShowName off GotoTag "LAST_SIG_BYTE_DONE" } Block { BlockType Goto Name "Goto2" SID "10640" Position [505, 985, 645, 1005] ShowName off GotoTag "LAST_SIG_BYTE_DONE" TagVisibility "local" } Block { BlockType Reference Name "Inverter3" SID "10641" Ports [1, 1] Position [945, 596, 975, 614] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "30,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 18 18 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');dis" "p('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter4" SID "10642" Ports [1, 1] Position [1120, 706, 1150, 724] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "30,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 18 18 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');dis" "p('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "LENGTH" SID "10643" Ports [3, 2] Position [540, 703, 650, 807] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off Port { PortNumber 2 Name "Length" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } System { Name "LENGTH" Location [84, 107, 2305, 1310] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "125" Block { BlockType Inport Name "B0" SID "10644" Position [165, 288, 195, 302] IconDisplay "Port number" } Block { BlockType Inport Name "B1" SID "10645" Position [165, 253, 195, 267] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "B2" SID "10646" Position [165, 218, 195, 232] Port "3" IconDisplay "Port number" } Block { BlockType Reference Name "1LSB" SID "10647" Ports [1, 1] Position [240, 217, 280, 233] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 16 16 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "3MSB" SID "10648" Ports [1, 1] Position [240, 287, 280, 303] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "3" boolean_output off mode "Upper Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 16 16 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Concat" SID "10649" Ports [3, 1] Position [325, 206, 355, 314] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point " "at zero." num_inputs "3" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "30,108,3,1,white,blue,0,61ef8218,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 108 108 0 ],[0.77 0." "82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 108 108 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[58.44 " "58.44 62.44 58.44 62.44 62.44 62.44 58.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[54.44 54.44 58.44 58" ".44 54.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[50.44 50.44 54.44 54.44 50.44 ],[1 1 1 ])" ";\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[46.44 46.44 50.44 46.44 50.44 50.44 46.44 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'hi');\n\ncolor('black');port_label('input',3,'lo');\n\ncolor('black');disp('\\fontsize{20}\\}','" "texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Concat1" SID "10650" Ports [2, 1] Position [505, 465, 565, 525] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point " "at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "60,60,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 60 60 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[38.88 38" ".88 46.88 38.88 46.88 46.88 46.88 38.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[30.88 30.88 38.88 38." "88 30.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[22.88 22.88 30.88 30.88 22.88 ],[1 1 1 ]" ");\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[14.88 14.88 22.88 14.88 22.88 22.88 14.88 ],[0.931 0.946 0." "973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port" "_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fontsize{20}\\}','" "texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant" SID "10651" Ports [0, 1] Position [420, 500, 450, 520] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "10" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,20,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 20 20 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 20 20 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[12.22" " 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[10.22 10.22 12." "22 12.22 10.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1" " 1 1 ]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');po" "rt_label('output',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant1" SID "10775" Ports [0, 1] Position [520, 530, 550, 550] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "6" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,20,0,1,white,blue,0,f0403ad7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 20 20 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 20 20 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[12.22" " 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[10.22 10.22 12." "22 12.22 10.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1" " 1 1 ]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');po" "rt_label('output',1,'6');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant2" SID "11754" Ports [0, 1] Position [430, 330, 460, 350] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "22" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "12" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,20,0,1,white,blue,0,4438d68f,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 20 20 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 20 20 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[12.22" " 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[10.22 10.22 12." "22 12.22 10.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1" " 1 1 ]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');po" "rt_label('output',1,'22');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "10652" Position [105, 470, 300, 490] ZOrder -9 ShowName off GotoTag "regRx_MAX_SIGNAL_LENGTH_KB" TagVisibility "global" } Block { BlockType Reference Name "Logical" SID "10654" Ports [2, 1] Position [725, 464, 760, 551] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,87,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 87 87 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 87 87 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[48.55 48." "55 53.55 48.55 53.55 53.55 53.55 48.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[43.55 43.55 48.55 4" "8.55 43.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[38.55 38.55 43.55 43.55 38.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[33.55 33.55 38.55 33.55 38.55 38.55 33.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('b" "lack');disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "10656" Ports [1, 1] Position [375, 467, 405, 493] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[16.3" "3 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 13.33 " "16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13.33 10." "33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor" "('black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','" "texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational1" SID "10657" Ports [2, 1] Position [640, 510, 675, 550] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "ab" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,40,2,1,white,blue,0,b5131c97,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 40 40 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bfa > b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "len invalid" SID "10659" Position [800, 503, 830, 517] IconDisplay "Port number" } Block { BlockType Outport Name "Length" SID "10660" Position [800, 253, 830, 267] Port "2" IconDisplay "Port number" } Line { SrcBlock "Concat" SrcPort 1 Points [250, 0] Branch { DstBlock "Length" DstPort 1 } Branch { Points [0, 215] Branch { DstBlock "Relational2" DstPort 1 } Branch { Points [0, 45] DstBlock "Relational1" DstPort 1 } } } Line { SrcBlock "Concat1" SrcPort 1 DstBlock "Relational2" DstPort 2 } Line { SrcBlock "Relational2" SrcPort 1 DstBlock "Logical" DstPort 1 } Line { SrcBlock "Constant" SrcPort 1 DstBlock "Concat1" DstPort 2 } Line { SrcBlock "From" SrcPort 1 DstBlock "Register1" DstPort 1 } Line { SrcBlock "1LSB" SrcPort 1 DstBlock "Concat" DstPort 1 } Line { SrcBlock "3MSB" SrcPort 1 DstBlock "Concat" DstPort 3 } Line { SrcBlock "B1" SrcPort 1 DstBlock "Concat" DstPort 2 } Line { SrcBlock "B2" SrcPort 1 DstBlock "1LSB" DstPort 1 } Line { SrcBlock "B0" SrcPort 1 DstBlock "3MSB" DstPort 1 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Relational1" DstPort 2 } Line { SrcBlock "Register1" SrcPort 1 DstBlock "Concat1" DstPort 1 } Line { SrcBlock "Relational1" SrcPort 1 DstBlock "Logical" DstPort 2 } Line { SrcBlock "Logical" SrcPort 1 DstBlock "len invalid" DstPort 1 } Annotation { Name "IEEE 802.11-2012 Table 20-1\nRXVECTOR params:\nL_LENGTH in NON_HT: 1:4095\nL_LENGTH in HT_MF: 1:4095\n" "\nThe minimum here was 14 in the old 11a-only PHY, reflecting\nthe minimum length packet (CTS or ACK @ 14 bytes)" ".\n\n11n uses L-SIG.LENGTH to encode duration by setting RATE\nto 6Mbps and LENGTH to the number of bytes that w" "ould lead\nto a NONHT waveform being the same duration of the actual\nHTMF waveform.\n\nIf HT-SIG.LENGTH = 1 (i." "e. 1 OFDM sym after L-LTF) then\n L-SIG.LENGTH=12 per IEEE 802.11-2012 9.3.4.\n\n11n also defines a waveform wit" "h no DATA field, for channel\nsounding. Our PHY doesn't currently support this. These packets\nwill be dropped q" "uietly when their L-SIG.LENGTH is too small.\n\nThe minimum length value here *must* be at least 6. The PHY\nass" "erts the PARAMS_VALID signal to the MAC core after writing\n6 bytes. For HTMF waveforms these are the HT-SIG byt" "es. For\nNONHT waveforms these are the first 6 bytes of payload. The\nwaveform type is not known until the two H" "T-SIG symbols are\nreceived. The Rx PHY must attempt decoding of 6 post-SIGNAL\nbytes." Position [616, 736] HorizontalAlignment "left" } } } Block { BlockType Reference Name "Logical" SID "10661" Ports [2, 1] Position [350, 788, 375, 817] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "25,29,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 29 29 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 29 29 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 " "17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33" " 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('bl" "ack');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "10662" Ports [2, 1] Position [350, 738, 375, 767] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "25,29,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 29 29 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 29 29 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 " "17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33" " 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('bl" "ack');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "10663" Ports [2, 1] Position [350, 463, 375, 492] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "25,29,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 29 29 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 29 29 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 " "17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33" " 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('bl" "ack');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical3" SID "10664" Ports [2, 1] Position [1185, 550, 1225, 590] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,40,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('b" "lack');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical5" SID "10665" Ports [3, 1] Position [1020, 600, 1060, 640] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,40,3,1,white,blue,0,a2abe52d,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\ncolor(" "'black');disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical6" SID "10666" Ports [2, 1] Position [1185, 705, 1225, 745] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,40,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('b" "lack');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "RATE Decode" SID "10667" Ports [1, 8] Position [535, 349, 655, 581] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "RATE Decode" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "124" Block { BlockType Inport Name "B0" SID "10668" Position [85, 128, 115, 142] IconDisplay "Port number" } Block { BlockType Reference Name "3LSB" SID "10669" Ports [1, 1] Position [245, 182, 285, 198] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "3" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 16 16 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "4LSB" SID "10670" Ports [1, 1] Position [170, 127, 210, 143] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "4" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 16 16 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant1" SID "11755" Ports [0, 1] Position [180, 217, 205, 233] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "5" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period on period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,16,0,1,white,blue,0,98872051,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 16 16 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[10.22 10" ".22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[8.22 8.22 10.22 10.22" " 8.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output'" ",1,'5');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant17" SID "10671" Ports [0, 1] Position [250, 267, 275, 283] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,16,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 16 16 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[10.22 10" ".22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[8.22 8.22 10.22 10.22" " 8.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output'" ",1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant18" SID "10672" Ports [0, 1] Position [250, 327, 275, 343] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,16,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 16 16 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[10.22 10" ".22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[8.22 8.22 10.22 10.22" " 8.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output'" ",1,'1');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant19" SID "10673" Ports [0, 1] Position [250, 252, 275, 268] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "2" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,16,0,1,white,blue,0,fca86624,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 16 16 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[10.22 10" ".22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[8.22 8.22 10.22 10.22" " 8.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output'" ",1,'2');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant20" SID "10674" Ports [0, 1] Position [250, 312, 275, 328] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "3" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,16,0,1,white,blue,0,279a71c8,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 16 16 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[10.22 10" ".22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[8.22 8.22 10.22 10.22" " 8.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output'" ",1,'3');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant21" SID "10675" Ports [0, 1] Position [250, 237, 275, 253] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "4" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,16,0,1,white,blue,0,85f36853,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 16 16 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[10.22 10" ".22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[8.22 8.22 10.22 10.22" " 8.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output'" ",1,'4');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant22" SID "10676" Ports [0, 1] Position [250, 297, 275, 313] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "5" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,16,0,1,white,blue,0,98872051,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 16 16 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[10.22 10" ".22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[8.22 8.22 10.22 10.22" " 8.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output'" ",1,'5');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant23" SID "10677" Ports [0, 1] Position [250, 222, 275, 238] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "6" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,16,0,1,white,blue,0,f0403ad7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 16 16 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[10.22 10" ".22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[8.22 8.22 10.22 10.22" " 8.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output'" ",1,'6');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant24" SID "10678" Ports [0, 1] Position [250, 282, 275, 298] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "7" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,16,0,1,white,blue,0,2a6960a5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 16 16 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[10.22 10" ".22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[8.22 8.22 10.22 10.22" " 8.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output'" ",1,'7');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "MSB" SID "10679" Ports [1, 1] Position [590, 127, 630, 143] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Upper Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 16 16 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux3" SID "10680" Ports [9, 1] Position [330, 195, 365, 355] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "8" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "35,160,9,1,white,blue,3,9717d9a5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 22.8571 137.143 160 0 " "],[0.77 0.82 0.91 ]);\nplot([0 35 35 0 0 ],[0 22.8571 137.143 160 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 1" "0.875 5.875 ],[85.55 85.55 90.55 85.55 90.55 90.55 90.55 85.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.87" "5 ],[80.55 80.55 85.55 85.55 80.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[75.55 75.55 " "80.55 80.55 75.55 ],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[70.55 70.55 75.55 70.55 75.55 " "75.55 70.55 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon" " text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black'" ");port_label('input',3,'d1');\ncolor('black');port_label('input',4,'d2');\ncolor('black');port_label('input',5,'" "d3');\ncolor('black');port_label('input',6,'d4');\ncolor('black');port_label('input',7,'d5');\ncolor('black');po" "rt_label('input',8,'d6');\ncolor('black');port_label('input',9,'d7');\n\ncolor('black');disp('\\bf{}','texmode'," "'on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "ROM" SID "10681" Ports [1, 1] Position [430, 312, 490, 368] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/ROM" SourceType "Xilinx Single Port Read-Only Memory Block" depth "numel(mcs_rom_11ag)" initVector "mcs_rom_11ag" distributed_mem "Block RAM" rst off init_reg "0" en off latency "1" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "32" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" dbl_ovrd off optimize "Area" use_rpm on xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "sprom" sg_icon_stat "60,56,1,1,white,blue,0,bbc23d60,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36" ".88 44.88 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36." "88 28.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]" ");\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0." "973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port" "_label('input',1,'addr');\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text')" ";" } Block { BlockType Reference Name "b[0]" SID "10682" Ports [1, 1] Position [590, 332, 630, 348] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 16 16 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[16:7]" SID "10683" Ports [1, 1] Position [590, 487, 630, 503] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "10" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "7" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 16 16 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[26:17]" SID "10684" Ports [1, 1] Position [590, 527, 630, 543] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "10" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "17" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 16 16 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[2:1]" SID "10685" Ports [1, 1] Position [590, 367, 630, 383] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "2" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "1" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 16 16 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[4:3]" SID "10686" Ports [1, 1] Position [590, 407, 630, 423] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "2" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "3" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 16 16 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[6:5]" SID "10687" Ports [1, 1] Position [590, 447, 630, 463] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "2" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "5" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 16 16 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "MCS" SID "10688" Position [700, 268, 730, 282] IconDisplay "Port number" } Block { BlockType Outport Name "mod_sel" SID "10689" Position [700, 408, 730, 422] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "code_rate" SID "10690" Position [700, 448, 730, 462] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "N_CBPS" SID "10691" Position [700, 488, 730, 502] Port "4" IconDisplay "Port number" } Block { BlockType Outport Name "N_DBPS" SID "10692" Position [700, 528, 730, 542] Port "5" IconDisplay "Port number" } Block { BlockType Outport Name "N_SS" SID "10693" Position [700, 368, 730, 382] Port "6" IconDisplay "Port number" } Block { BlockType Outport Name "Chan_BW" SID "10694" Position [700, 333, 730, 347] Port "7" IconDisplay "Port number" } Block { BlockType Outport Name "RATE Valid" SID "10695" Position [700, 128, 730, 142] Port "8" IconDisplay "Port number" } Line { SrcBlock "MSB" SrcPort 1 DstBlock "RATE Valid" DstPort 1 } Line { SrcBlock "B0" SrcPort 1 DstBlock "4LSB" DstPort 1 } Line { SrcBlock "4LSB" SrcPort 1 Points [10, 0] Branch { DstBlock "MSB" DstPort 1 } Branch { Points [0, 55] DstBlock "3LSB" DstPort 1 } } Line { SrcBlock "Mux3" SrcPort 1 Points [20, 0] Branch { DstBlock "MCS" DstPort 1 } Branch { Points [0, 65] DstBlock "ROM" DstPort 1 } } Line { SrcBlock "ROM" SrcPort 1 Points [65, 0] Branch { DstBlock "b[0]" DstPort 1 } Branch { Points [0, 35] Branch { DstBlock "b[2:1]" DstPort 1 } Branch { Points [0, 40] Branch { DstBlock "b[4:3]" DstPort 1 } Branch { Points [0, 40] Branch { DstBlock "b[6:5]" DstPort 1 } Branch { Points [0, 40] Branch { DstBlock "b[16:7]" DstPort 1 } Branch { Points [0, 40] DstBlock "b[26:17]" DstPort 1 } } } } } } Line { SrcBlock "b[6:5]" SrcPort 1 DstBlock "code_rate" DstPort 1 } Line { SrcBlock "b[4:3]" SrcPort 1 DstBlock "mod_sel" DstPort 1 } Line { SrcBlock "b[0]" SrcPort 1 DstBlock "Chan_BW" DstPort 1 } Line { SrcBlock "b[26:17]" SrcPort 1 DstBlock "N_DBPS" DstPort 1 } Line { SrcBlock "b[16:7]" SrcPort 1 DstBlock "N_CBPS" DstPort 1 } Line { SrcBlock "b[2:1]" SrcPort 1 DstBlock "N_SS" DstPort 1 } Line { SrcBlock "3LSB" SrcPort 1 Points [0, 25] DstBlock "Mux3" DstPort 1 } Line { SrcBlock "Constant24" SrcPort 1 DstBlock "Mux3" DstPort 6 } Line { SrcBlock "Constant23" SrcPort 1 DstBlock "Mux3" DstPort 2 } Line { SrcBlock "Constant22" SrcPort 1 DstBlock "Mux3" DstPort 7 } Line { SrcBlock "Constant21" SrcPort 1 DstBlock "Mux3" DstPort 3 } Line { SrcBlock "Constant20" SrcPort 1 DstBlock "Mux3" DstPort 8 } Line { SrcBlock "Constant19" SrcPort 1 DstBlock "Mux3" DstPort 4 } Line { SrcBlock "Constant18" SrcPort 1 DstBlock "Mux3" DstPort 9 } Line { SrcBlock "Constant17" SrcPort 1 DstBlock "Mux3" DstPort 5 } Annotation { Name "Bit R4 is 1 for all valid rate codes" Position [650, 106] } Annotation { Name "Define MCS index values for 11a/g rates\nThese MCS values are not from the standard,\nbut are used th" "roughout this ref design for\nsanity's sake." Position [412, 238] HorizontalAlignment "left" } Annotation { Name "IEEE 802.11-2012 Table 18-6:\n[R4:R1]:\n1011: BPSK 1/2\n1111: BPSK 3/4\n1010: QPSK 1/2\n1110: QPSK 3/" "4\n1001: 16-QAM 1/2\n1101: 16-QAM 3/4\n1000: 64-QAM 2/3\n1100: 64-QAM 3/4\n\nMod Order values:\n0: BPSK\n1: QPSK" "\n2: 16-QAM\n3: 64-QAM\n\nCode Rate values:\n0: 1/2\n1: 2/3\n2: 3/4\n3: 5/6 (HT/VHT only)\n\nN_DBPS values:\nBPS" "K 1/2: 24\nBPSK 3/4: 36\nQPSK 1/2: 48\nQPSK 3/4: 72\n16-QAM 1/2: 96\n16-QAM 3/4: 144\n64-QAM 2/3: 192\n64-QAM 3/" "4: 216" Position [820, 472] HorizontalAlignment "left" } Annotation { Name "% Ouptut word contents:\n% b[ 0]: Chan bandwidth\n% b[ 2: 1]: Num spatial streams\n% b[ 4: 3]: " "Mod order index\n% b[ 6: 5]: Code rate index\n% b[16: 7]: Coded bits per symbol per stream\n% b[26:17]: Data " "bits per symbol per stream" Position [410, 668] HorizontalAlignment "left" FontName "Consolas" FontSize 12 } } } Block { BlockType Reference Name "Relational" SID "10696" Ports [2, 1] Position [265, 740, 300, 780] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,40,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 40 40 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bfa = b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational1" SID "10697" Ports [2, 1] Position [265, 790, 300, 830] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,40,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 40 40 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bfa = b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational2" SID "10698" Ports [2, 1] Position [265, 465, 300, 505] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,40,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 40 40 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bfa = b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Scope Name "SIGNAL Dec" SID "10699" Ports [8] Position [1440, 122, 1475, 243] ZOrder -3 Floating off Location [1144, 391, 2459, 1590] Open off NumInputPorts "8" ZoomMode "yonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" } List { ListType ScopeGraphics FigureColor "[0.5 0.5 0.5]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "19620" YMin "50~0~-1~10~-1~-1~-5~-5" YMax "100~1~1~11~1~1~5~5" SaveName "ScopeData18" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType Scope Name "SIGNAL Dec Errs" SID "11756" Ports [8] Position [1475, 842, 1510, 963] ZOrder -3 Floating off Location [1596, 471, 2459, 1590] Open off NumInputPorts "8" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" } List { ListType ScopeGraphics FigureColor "[0.5 0.5 0.5]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "19620" YMin "50~0~-1~10~-1~-1~-5~-5" YMax "100~1~1~11~1~1~5~5" SaveName "ScopeData53" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType SubSystem Name "Tail & Parity Check" SID "10700" Ports [3, 1] Position [535, 840, 650, 890] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Tail & Parity Check" Location [36, 222, 2218, 1427] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "112" Block { BlockType Inport Name "B0" SID "10701" Position [375, 258, 405, 272] IconDisplay "Port number" } Block { BlockType Inport Name "B1" SID "10702" Position [375, 303, 405, 317] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "B2" SID "10703" Position [375, 348, 405, 362] Port "3" IconDisplay "Port number" } Block { BlockType Reference Name "2LSB" SID "10704" Ports [1, 1] Position [460, 347, 500, 363] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "2" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 16 16 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "2b XOR" SID "10705" Ports [1, 1] Position [555, 340, 600, 370] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "2b XOR" Location [36, 222, 2218, 1427] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" SID "10706" Position [100, 38, 130, 52] IconDisplay "Port number" } Block { BlockType Reference Name "Logical" SID "10707" Ports [2, 1] Position [270, 26, 310, 99] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "XOR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,73,2,1,white,blue,0,dc21e094,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 73 73 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 73 73 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[41.55 41." "55 46.55 41.55 46.55 46.55 46.55 41.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[36.55 36.55 41.55 4" "1.55 36.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[31.55 31.55 36.55 36.55 31.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[26.55 26.55 31.55 26.55 31.55 31.55 26.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('b" "lack');disp('xor');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b0" SID "10708" Ports [1, 1] Position [185, 36, 225, 54] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b1" SID "10709" Ports [1, 1] Position [185, 71, 225, 89] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "1" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "B" SID "10710" Position [355, 53, 385, 67] IconDisplay "Port number" } Line { SrcBlock "Logical" SrcPort 1 DstBlock "B" DstPort 1 } Line { SrcBlock "b1" SrcPort 1 DstBlock "Logical" DstPort 2 } Line { SrcBlock "b0" SrcPort 1 DstBlock "Logical" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [15, 0] Branch { Points [0, 35] DstBlock "b1" DstPort 1 } Branch { DstBlock "b0" DstPort 1 } } } } Block { BlockType Reference Name "6MSB" SID "10711" Ports [1, 1] Position [460, 452, 500, 468] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "6" boolean_output off mode "Upper Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 16 16 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "8b XOR 1" SID "10712" Ports [1, 1] Position [555, 250, 600, 280] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "8b XOR 1" Location [428, 592, 836, 929] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" SID "10713" Position [100, 38, 130, 52] IconDisplay "Port number" } Block { BlockType Reference Name "Logical" SID "10714" Ports [8, 1] Position [285, 25, 330, 310] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "XOR" inputs "8" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "45,285,8,1,white,blue,0,3d04c15b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 285 285 0 ],[0.77 0." "82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 285 285 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[148" ".66 148.66 154.66 148.66 154.66 154.66 154.66 148.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[142.66" " 142.66 148.66 148.66 142.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[136.66 136.66 142.6" "6 142.66 136.66 ],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[130.66 130.66 136.66 130.66 136" ".66 136.66 130.66 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begi" "n icon text');\n\n\n\n\n\n\n\n\n\ncolor('black');disp('xor');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b0" SID "10715" Ports [1, 1] Position [185, 36, 225, 54] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b1" SID "10716" Ports [1, 1] Position [185, 71, 225, 89] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "1" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b2" SID "10717" Ports [1, 1] Position [185, 106, 225, 124] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "2" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b3" SID "10718" Ports [1, 1] Position [185, 141, 225, 159] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "3" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b4" SID "10719" Ports [1, 1] Position [185, 176, 225, 194] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "4" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b5" SID "10720" Ports [1, 1] Position [185, 211, 225, 229] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "5" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b6" SID "10721" Ports [1, 1] Position [185, 246, 225, 264] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "6" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b7" SID "10722" Ports [1, 1] Position [185, 281, 225, 299] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "7" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "B" SID "10723" Position [355, 163, 385, 177] IconDisplay "Port number" } Line { SrcBlock "Logical" SrcPort 1 DstBlock "B" DstPort 1 } Line { SrcBlock "b7" SrcPort 1 DstBlock "Logical" DstPort 8 } Line { SrcBlock "b6" SrcPort 1 DstBlock "Logical" DstPort 7 } Line { SrcBlock "b5" SrcPort 1 DstBlock "Logical" DstPort 6 } Line { SrcBlock "b4" SrcPort 1 DstBlock "Logical" DstPort 5 } Line { SrcBlock "b3" SrcPort 1 DstBlock "Logical" DstPort 4 } Line { SrcBlock "b2" SrcPort 1 DstBlock "Logical" DstPort 3 } Line { SrcBlock "b1" SrcPort 1 DstBlock "Logical" DstPort 2 } Line { SrcBlock "b0" SrcPort 1 DstBlock "Logical" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [15, 0] Branch { Points [0, 35] Branch { Points [0, 35] Branch { Points [0, 35] Branch { Points [0, 35] Branch { Points [0, 35] Branch { Points [0, 35] Branch { DstBlock "b6" DstPort 1 } Branch { Points [0, 35] DstBlock "b7" DstPort 1 } } Branch { DstBlock "b5" DstPort 1 } } Branch { DstBlock "b4" DstPort 1 } } Branch { DstBlock "b3" DstPort 1 } } Branch { DstBlock "b2" DstPort 1 } } Branch { DstBlock "b1" DstPort 1 } } Branch { DstBlock "b0" DstPort 1 } } } } Block { BlockType SubSystem Name "8b XOR 2" SID "10724" Ports [1, 1] Position [555, 295, 600, 325] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "8b XOR 2" Location [36, 222, 2218, 1427] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" SID "10725" Position [100, 38, 130, 52] IconDisplay "Port number" } Block { BlockType Reference Name "Logical" SID "10726" Ports [8, 1] Position [285, 25, 330, 310] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "XOR" inputs "8" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "45,285,8,1,white,blue,0,3d04c15b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 285 285 0 ],[0.77 0." "82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 285 285 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[148" ".66 148.66 154.66 148.66 154.66 154.66 154.66 148.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[142.66" " 142.66 148.66 148.66 142.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[136.66 136.66 142.6" "6 142.66 136.66 ],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[130.66 130.66 136.66 130.66 136" ".66 136.66 130.66 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begi" "n icon text');\n\n\n\n\n\n\n\n\n\ncolor('black');disp('xor');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b0" SID "10727" Ports [1, 1] Position [185, 36, 225, 54] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b1" SID "10728" Ports [1, 1] Position [185, 71, 225, 89] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "1" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b2" SID "10729" Ports [1, 1] Position [185, 106, 225, 124] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "2" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b3" SID "10730" Ports [1, 1] Position [185, 141, 225, 159] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "3" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b4" SID "10731" Ports [1, 1] Position [185, 176, 225, 194] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "4" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b5" SID "10732" Ports [1, 1] Position [185, 211, 225, 229] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "5" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b6" SID "10733" Ports [1, 1] Position [185, 246, 225, 264] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "6" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b7" SID "10734" Ports [1, 1] Position [185, 281, 225, 299] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "7" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "B" SID "10735" Position [355, 163, 385, 177] IconDisplay "Port number" } Line { SrcBlock "A" SrcPort 1 Points [15, 0] Branch { DstBlock "b0" DstPort 1 } Branch { Points [0, 35] Branch { DstBlock "b1" DstPort 1 } Branch { Points [0, 35] Branch { DstBlock "b2" DstPort 1 } Branch { Points [0, 35] Branch { DstBlock "b3" DstPort 1 } Branch { Points [0, 35] Branch { DstBlock "b4" DstPort 1 } Branch { Points [0, 35] Branch { DstBlock "b5" DstPort 1 } Branch { Points [0, 35] Branch { Points [0, 35] DstBlock "b7" DstPort 1 } Branch { DstBlock "b6" DstPort 1 } } } } } } } } Line { SrcBlock "b0" SrcPort 1 DstBlock "Logical" DstPort 1 } Line { SrcBlock "b1" SrcPort 1 DstBlock "Logical" DstPort 2 } Line { SrcBlock "b2" SrcPort 1 DstBlock "Logical" DstPort 3 } Line { SrcBlock "b3" SrcPort 1 DstBlock "Logical" DstPort 4 } Line { SrcBlock "b4" SrcPort 1 DstBlock "Logical" DstPort 5 } Line { SrcBlock "b5" SrcPort 1 DstBlock "Logical" DstPort 6 } Line { SrcBlock "b6" SrcPort 1 DstBlock "Logical" DstPort 7 } Line { SrcBlock "b7" SrcPort 1 DstBlock "Logical" DstPort 8 } Line { SrcBlock "Logical" SrcPort 1 DstBlock "B" DstPort 1 } } } Block { BlockType Reference Name "Constant1" SID "10736" Ports [0, 1] Position [615, 469, 640, 491] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,22,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 22 22 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[14.33 " "14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 1 " "1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('output',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "10737" Ports [1, 1] Position [785, 301, 810, 319] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('outpu" "t',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical" SID "10738" Ports [3, 1] Position [680, 240, 715, 380] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "XOR" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,140,3,1,white,blue,0,86aed425,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 140 140 0 ],[0.77 0." "82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 140 140 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[75.55" " 75.55 80.55 75.55 80.55 80.55 80.55 75.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[70.55 70.55 75." "55 75.55 70.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[65.55 65.55 70.55 70.55 65.55 ]," "[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[60.55 60.55 65.55 60.55 65.55 65.55 60.55 ],[0.931" " 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\nco" "lor('black');disp('xor');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical5" SID "10739" Ports [2, 1] Position [935, 300, 975, 340] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,40,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('b" "lack');disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational1" SID "10740" Ports [2, 1] Position [680, 450, 715, 490] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a!=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,40,2,1,white,blue,0,850de6e7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 40 40 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bfa \\neq b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Invalid" SID "10741" Position [1025, 313, 1055, 327] IconDisplay "Port number" } Line { SrcBlock "Logical5" SrcPort 1 DstBlock "Invalid" DstPort 1 } Line { SrcBlock "Relational1" SrcPort 1 Points [105, 0; 0, -140] DstBlock "Logical5" DstPort 2 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Relational1" DstPort 2 } Line { SrcBlock "6MSB" SrcPort 1 DstBlock "Relational1" DstPort 1 } Line { SrcBlock "B2" SrcPort 1 Points [20, 0] Branch { Points [0, 105] DstBlock "6MSB" DstPort 1 } Branch { DstBlock "2LSB" DstPort 1 } } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Logical5" DstPort 1 } Line { SrcBlock "Logical" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "2b XOR" SrcPort 1 DstBlock "Logical" DstPort 3 } Line { SrcBlock "8b XOR 2" SrcPort 1 DstBlock "Logical" DstPort 2 } Line { SrcBlock "8b XOR 1" SrcPort 1 DstBlock "Logical" DstPort 1 } Line { SrcBlock "2LSB" SrcPort 1 DstBlock "2b XOR" DstPort 1 } Line { SrcBlock "B1" SrcPort 1 DstBlock "8b XOR 2" DstPort 1 } Line { SrcBlock "B0" SrcPort 1 DstBlock "8b XOR 1" DstPort 1 } Annotation { Name "SIGNAL field parity bit assures first 17 bits\n(RATE, LENGTH and PARITY) XOR to 0\n(a.k.a. even parit" "y)" Position [594, 416] } } } Block { BlockType Reference Name "dbg_SIGNAL_ERR_DISP" SID "10742" Ports [1, 1] Position [1600, 625, 1660, 645] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0.93" " 0.65 ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12.22" " 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 12." "22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1" " 1 1 ]);\npatch([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 " "0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');po" "rt_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfpr" "intf('','COMMENT: end icon text');" } Block { BlockType Reference Name "int" SID "10743" Ports [1, 1] Position [1275, 123, 1310, 137] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,14,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 14 14 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 14 14 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[9.22 " "9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[7.22 7.22 9.22 9.22" " 7.22 ],[0.964 0.964 0.964 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\np" "atch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.964 0.964 0.964 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i" "nput',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMEN" "T: end icon text');" Port { PortNumber 1 Name "SIG Done" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "int1" SID "10744" Ports [1, 1] Position [1275, 138, 1310, 152] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,14,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 14 14 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 14 14 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[9.22 " "9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[7.22 7.22 9.22 9.22" " 7.22 ],[0.964 0.964 0.964 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\np" "atch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.964 0.964 0.964 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i" "nput',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMEN" "T: end icon text');" Port { PortNumber 1 Name "MCS" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "int10" SID "11759" Ports [1, 1] Position [1310, 873, 1345, 887] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,14,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 14 14 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 14 14 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[9.22 " "9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[7.22 7.22 9.22 9.22" " 7.22 ],[0.964 0.964 0.964 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\np" "atch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.964 0.964 0.964 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i" "nput',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMEN" "T: end icon text');" Port { PortNumber 1 Name "Tail-Parity Invalid" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "int11" SID "11760" Ports [1, 1] Position [1310, 888, 1345, 902] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,14,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 14 14 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 14 14 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[9.22 " "9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[7.22 7.22 9.22 9.22" " 7.22 ],[0.964 0.964 0.964 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\np" "atch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.964 0.964 0.964 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i" "nput',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMEN" "T: end icon text');" Port { PortNumber 1 Name "SIGNAL Done" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "int12" SID "11761" Ports [1, 1] Position [1310, 903, 1345, 917] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,14,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 14 14 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 14 14 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[9.22 " "9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[7.22 7.22 9.22 9.22" " 7.22 ],[0.964 0.964 0.964 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\np" "atch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.964 0.964 0.964 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i" "nput',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMEN" "T: end icon text');" Port { PortNumber 1 Name "Reset" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "int2" SID "10745" Ports [1, 1] Position [1275, 153, 1310, 167] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,14,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 14 14 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 14 14 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[9.22 " "9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[7.22 7.22 9.22 9.22" " 7.22 ],[0.964 0.964 0.964 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\np" "atch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.964 0.964 0.964 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i" "nput',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMEN" "T: end icon text');" Port { PortNumber 1 Name "Mod order" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "int3" SID "10746" Ports [1, 1] Position [1275, 168, 1310, 182] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,14,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 14 14 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 14 14 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[9.22 " "9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[7.22 7.22 9.22 9.22" " 7.22 ],[0.964 0.964 0.964 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\np" "atch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.964 0.964 0.964 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i" "nput',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMEN" "T: end icon text');" Port { PortNumber 1 Name "Code rate" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "int4" SID "10747" Ports [1, 1] Position [1275, 198, 1310, 212] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,14,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 14 14 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 14 14 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[9.22 " "9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[7.22 7.22 9.22 9.22" " 7.22 ],[0.964 0.964 0.964 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\np" "atch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.964 0.964 0.964 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i" "nput',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMEN" "T: end icon text');" Port { PortNumber 1 Name "SIG Invalid" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "int5" SID "10748" Ports [1, 1] Position [1275, 213, 1310, 227] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,14,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 14 14 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 14 14 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[9.22 " "9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[7.22 7.22 9.22 9.22" " 7.22 ],[0.964 0.964 0.964 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\np" "atch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.964 0.964 0.964 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i" "nput',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMEN" "T: end icon text');" Port { PortNumber 1 Name "SIG Valid" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "int6" SID "10749" Ports [1, 1] Position [1275, 183, 1310, 197] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,14,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 14 14 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 14 14 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[9.22 " "9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[7.22 7.22 9.22 9.22" " 7.22 ],[0.964 0.964 0.964 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\np" "atch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.964 0.964 0.964 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i" "nput',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMEN" "T: end icon text');" Port { PortNumber 1 Name "Length" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "int7" SID "10750" Ports [1, 1] Position [1275, 228, 1310, 242] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,14,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 14 14 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 14 14 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[9.22 " "9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[7.22 7.22 9.22 9.22" " 7.22 ],[0.964 0.964 0.964 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\np" "atch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.964 0.964 0.964 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i" "nput',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMEN" "T: end icon text');" Port { PortNumber 1 Name "N_DBPS" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "int8" SID "11757" Ports [1, 1] Position [1310, 843, 1345, 857] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,14,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 14 14 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 14 14 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[9.22 " "9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[7.22 7.22 9.22 9.22" " 7.22 ],[0.964 0.964 0.964 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\np" "atch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.964 0.964 0.964 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i" "nput',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMEN" "T: end icon text');" Port { PortNumber 1 Name "Rate Invalid" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "int9" SID "11758" Ports [1, 1] Position [1310, 858, 1345, 872] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,14,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 14 14 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 14 14 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[9.22 " "9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[7.22 7.22 9.22 9.22" " 7.22 ],[0.964 0.964 0.964 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\np" "atch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.964 0.964 0.964 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i" "nput',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMEN" "T: end icon text');" Port { PortNumber 1 Name "Length Invalid" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Outport Name "SIGNAL Valid" SID "10751" Position [1285, 718, 1315, 732] IconDisplay "Port number" } Block { BlockType Outport Name "SIGNAL Invalid" SID "10752" Position [1290, 563, 1320, 577] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "Length" SID "10753" Position [915, 773, 945, 787] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "MCS" SID "10754" Position [805, 353, 835, 367] Port "4" IconDisplay "Port number" } Block { BlockType Outport Name "mod_sel" SID "10755" Position [805, 383, 835, 397] Port "5" IconDisplay "Port number" } Block { BlockType Outport Name "code_rate" SID "10756" Position [805, 413, 835, 427] Port "6" IconDisplay "Port number" } Block { BlockType Outport Name "Chan_BW" SID "10757" Position [805, 533, 835, 547] Port "7" IconDisplay "Port number" } Block { BlockType Outport Name "N_DBPS" SID "10758" Position [805, 473, 835, 487] Port "8" IconDisplay "Port number" } Block { BlockType Outport Name "N_CBPS" SID "10759" Position [805, 443, 835, 457] Port "9" IconDisplay "Port number" } Block { BlockType Outport Name "N_SS" SID "10760" Position [805, 503, 835, 517] Port "10" IconDisplay "Port number" } Block { BlockType Outport Name "SIGNAL Done" SID "10761" Position [915, 1018, 945, 1032] Port "11" IconDisplay "Port number" } Line { SrcBlock "4b Shift Reg" SrcPort 1 DstBlock "DOUT6" DstPort 1 } Line { SrcBlock "DOUT7" SrcPort 1 DstBlock "dbg_SIGNAL_ERR_DISP" DstPort 1 } Line { SrcBlock "DOUT6" SrcPort 1 DstBlock "DOUT7" DstPort 1 } Line { SrcBlock "DOUT2" SrcPort 1 Points [10, 0] Branch { Points [0, 90] DstBlock "Tail & Parity Check" DstPort 3 } Branch { DstBlock "LENGTH" DstPort 3 } } Line { SrcBlock "DOUT1" SrcPort 1 Points [20, 0] Branch { Points [0, 125] DstBlock "Tail & Parity Check" DstPort 2 } Branch { Points [40, 0] DstBlock "LENGTH" DstPort 2 } } Line { SrcBlock "DOUT" SrcPort 1 Points [25, 0] Branch { Points [0, 255] Branch { Points [0, 130] DstBlock "Tail & Parity Check" DstPort 1 } Branch { DstBlock "LENGTH" DstPort 1 } } Branch { DstBlock "RATE Decode" DstPort 1 } } Line { SrcBlock "rst" SrcPort 1 Points [270, 0; 0, 50] Branch { DstBlock "DOUT" DstPort 2 } Branch { Points [0, 275] Branch { DstBlock "DOUT1" DstPort 2 } Branch { Points [0, 50] Branch { DstBlock "DOUT2" DstPort 2 } Branch { Points [0, 295; 875, 0; 0, -175] DstBlock "int12" DstPort 1 } } } } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "DOUT1" DstPort 3 } Line { SrcBlock "Logical2" SrcPort 1 DstBlock "DOUT" DstPort 3 } Line { SrcBlock "Logical" SrcPort 1 Points [15, 0] Branch { DstBlock "DOUT2" DstPort 3 } Branch { Points [0, 190] DstBlock "Delay" DstPort 1 } } Line { SrcBlock "Relational" SrcPort 1 DstBlock "Logical1" DstPort 2 } Line { SrcBlock "Relational2" SrcPort 1 DstBlock "Logical2" DstPort 2 } Line { SrcBlock "Relational1" SrcPort 1 DstBlock "Logical" DstPort 2 } Line { SrcBlock "Constant2" SrcPort 1 DstBlock "Relational2" DstPort 2 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Relational1" DstPort 2 } Line { SrcBlock "Constant" SrcPort 1 DstBlock "Relational" DstPort 2 } Line { SrcBlock "byte" SrcPort 1 Points [280, 0; 0, 65] Branch { Points [0, 275] Branch { Points [0, 50] DstBlock "DOUT2" DstPort 1 } Branch { DstBlock "DOUT1" DstPort 1 } } Branch { DstBlock "DOUT" DstPort 1 } } Line { SrcBlock "byte_ind" SrcPort 1 Points [115, 0] Branch { Points [0, 275] Branch { DstBlock "Relational" DstPort 1 } Branch { Points [0, 50] DstBlock "Relational1" DstPort 1 } } Branch { DstBlock "Relational2" DstPort 1 } } Line { Labels [0, 0] SrcBlock "byte_valid" SrcPort 1 Points [205, 0; 0, 25] Branch { Points [0, 275] Branch { Points [0, 50] DstBlock "Logical" DstPort 1 } Branch { DstBlock "Logical1" DstPort 1 } } Branch { DstBlock "Logical2" DstPort 1 } } Line { SrcBlock "Delay" SrcPort 1 Points [15, 0] Branch { DstBlock "Goto2" DstPort 1 } Branch { Points [0, 30] DstBlock "SIGNAL Done" DstPort 1 } } Line { SrcBlock "RATE Decode" SrcPort 1 Points [70, 0] Branch { DstBlock "MCS" DstPort 1 } Branch { Points [0, -215] DstBlock "int1" DstPort 1 } } Line { SrcBlock "RATE Decode" SrcPort 2 Points [75, 0] Branch { DstBlock "mod_sel" DstPort 1 } Branch { Points [0, -230] DstBlock "int2" DstPort 1 } } Line { SrcBlock "RATE Decode" SrcPort 3 Points [80, 0] Branch { DstBlock "code_rate" DstPort 1 } Branch { Points [0, -245] DstBlock "int3" DstPort 1 } } Line { SrcBlock "RATE Decode" SrcPort 4 DstBlock "N_CBPS" DstPort 1 } Line { SrcBlock "RATE Decode" SrcPort 5 Points [110, 0] Branch { DstBlock "N_DBPS" DstPort 1 } Branch { Points [0, -245] DstBlock "int7" DstPort 1 } } Line { SrcBlock "RATE Decode" SrcPort 6 DstBlock "N_SS" DstPort 1 } Line { SrcBlock "RATE Decode" SrcPort 7 DstBlock "Chan_BW" DstPort 1 } Line { SrcBlock "RATE Decode" SrcPort 8 Points [100, 0; 0, 35] DstBlock "Inverter3" DstPort 1 } Line { SrcBlock "From" SrcPort 1 DstBlock "Logical3" DstPort 1 } Line { SrcBlock "Logical3" SrcPort 1 Points [20, 0] Branch { DstBlock "SIGNAL Invalid" DstPort 1 } Branch { Points [0, 65] DstBlock "4b Shift Reg" DstPort 1 } Branch { Points [0, -365] DstBlock "int4" DstPort 1 } } Line { SrcBlock "Inverter3" SrcPort 1 Points [20, 0] Branch { DstBlock "Logical5" DstPort 1 } Branch { Points [0, 245] DstBlock "int8" DstPort 1 } } Line { SrcBlock "LENGTH" SrcPort 1 Points [105, 0; 0, -110; 235, 0] Branch { DstBlock "Logical5" DstPort 2 } Branch { Points [0, 245] DstBlock "int9" DstPort 1 } } Line { SrcBlock "Tail & Parity Check" SrcPort 1 Points [115, 0; 0, -230; 220, 0] Branch { DstBlock "Logical5" DstPort 3 } Branch { Points [0, 245] DstBlock "int10" DstPort 1 } } Line { SrcBlock "Logical5" SrcPort 1 Points [20, 0] Branch { Points [0, -40] DstBlock "Logical3" DstPort 2 } Branch { Points [0, 95] DstBlock "Inverter4" DstPort 1 } } Line { SrcBlock "From1" SrcPort 1 Points [10, 0] Branch { DstBlock "Logical6" DstPort 2 } Branch { Points [0, 160] DstBlock "int11" DstPort 1 } } Line { SrcBlock "Inverter4" SrcPort 1 DstBlock "Logical6" DstPort 1 } Line { SrcBlock "Logical6" SrcPort 1 Points [25, 0] Branch { DstBlock "SIGNAL Valid" DstPort 1 } Branch { Points [0, -505] DstBlock "int5" DstPort 1 } } Line { Name "Length" Labels [0, 0] SrcBlock "LENGTH" SrcPort 2 Points [210, 0] Branch { DstBlock "Length" DstPort 1 } Branch { Points [0, -590] DstBlock "int6" DstPort 1 } } Line { Name "SIG Done" Labels [0, 0] SrcBlock "int" SrcPort 1 DstBlock "SIGNAL Dec" DstPort 1 } Line { SrcBlock "From2" SrcPort 1 DstBlock "int" DstPort 1 } Line { Name "Mod order" Labels [0, 0] SrcBlock "int2" SrcPort 1 DstBlock "SIGNAL Dec" DstPort 3 } Line { Name "MCS" Labels [0, 0] SrcBlock "int1" SrcPort 1 DstBlock "SIGNAL Dec" DstPort 2 } Line { Name "Code rate" Labels [0, 0] SrcBlock "int3" SrcPort 1 DstBlock "SIGNAL Dec" DstPort 4 } Line { Name "SIG Invalid" Labels [0, 0] SrcBlock "int4" SrcPort 1 DstBlock "SIGNAL Dec" DstPort 6 } Line { Name "SIG Valid" Labels [0, 0] SrcBlock "int5" SrcPort 1 DstBlock "SIGNAL Dec" DstPort 7 } Line { Name "Length" Labels [0, 0] SrcBlock "int6" SrcPort 1 DstBlock "SIGNAL Dec" DstPort 5 } Line { Name "N_DBPS" Labels [0, 0] SrcBlock "int7" SrcPort 1 DstBlock "SIGNAL Dec" DstPort 8 } Line { Name "Rate Invalid" Labels [0, 0] SrcBlock "int8" SrcPort 1 DstBlock "SIGNAL Dec Errs" DstPort 1 } Line { Name "Length Invalid" Labels [0, 0] SrcBlock "int9" SrcPort 1 DstBlock "SIGNAL Dec Errs" DstPort 2 } Line { Name "Tail-Parity Invalid" Labels [0, 0] SrcBlock "int10" SrcPort 1 DstBlock "SIGNAL Dec Errs" DstPort 3 } Line { Name "SIGNAL Done" Labels [0, 0] SrcBlock "int11" SrcPort 1 DstBlock "SIGNAL Dec Errs" DstPort 4 } Line { Name "Reset" Labels [0, 0] SrcBlock "int12" SrcPort 1 DstBlock "SIGNAL Dec Errs" DstPort 5 } Annotation { Name "Init values of these regs are important\nDecoder black box requires valid params at start,\nso these " "regs are initialzied such that:\nmod_order = 0 (BSPK)\ncode_rate = 0 (1/2)\nnum_bytes = 64 (sane default)\n\nThe" " choice of BPSK with 1/2 code rate is critical to\nallow demodulation of the SIGNAL field (first OFDM\nsymbol) a" "nd potential HT/VHT-SIG fields (next 3\nOFDM symbols)." Position [134, 916] HorizontalAlignment "left" } } } Block { BlockType Outport Name "Last Byte Ind" SID "10762" Position [1490, 893, 1520, 907] IconDisplay "Port number" } Block { BlockType Outport Name "Reset PHY" SID "10763" Position [1610, 1093, 1640, 1107] Port "2" IconDisplay "Port number" } Line { SrcBlock "byte_ind" SrcPort 1 Points [55, 0] Branch { DstBlock "SIGNAL Decode" DstPort 1 } Branch { Points [0, 250] DstBlock "HT-SIG Decode" DstPort 2 } } Line { SrcBlock "byte_valid" SrcPort 1 Points [50, 0] Branch { DstBlock "SIGNAL Decode" DstPort 2 } Branch { Points [0, 245] DstBlock "HT-SIG Decode" DstPort 3 } } Line { SrcBlock "byte" SrcPort 1 Points [45, 0] Branch { DstBlock "SIGNAL Decode" DstPort 3 } Branch { Points [0, 240] DstBlock "HT-SIG Decode" DstPort 4 } } Line { SrcBlock "rst" SrcPort 1 Points [40, 0] Branch { DstBlock "SIGNAL Decode" DstPort 4 } Branch { Points [0, 235] Branch { DstBlock "HT-SIG Decode" DstPort 5 } Branch { Points [0, 335] DstBlock "S-R Latch1" DstPort 2 } } } Line { SrcBlock "SIGNAL Decode" SrcPort 3 DstBlock "Goto7" DstPort 1 } Line { SrcBlock "SIGNAL Decode" SrcPort 4 Points [40, 0] Branch { DstBlock "Goto8" DstPort 1 } Branch { Points [0, 145; -175, 0] DstBlock "HT-SIG Decode" DstPort 1 } } Line { SrcBlock "SIGNAL Decode" SrcPort 5 DstBlock "Goto10" DstPort 1 } Line { SrcBlock "SIGNAL Decode" SrcPort 1 DstBlock "Goto2" DstPort 1 } Line { SrcBlock "SIGNAL Decode" SrcPort 2 DstBlock "Goto1" DstPort 1 } Line { SrcBlock "SIGNAL Decode" SrcPort 6 DstBlock "Goto12" DstPort 1 } Line { SrcBlock "SIGNAL Decode" SrcPort 7 DstBlock "Goto20" DstPort 1 } Line { SrcBlock "SIGNAL Decode" SrcPort 8 DstBlock "Goto14" DstPort 1 } Line { SrcBlock "SIGNAL Decode" SrcPort 9 DstBlock "Goto16" DstPort 1 } Line { SrcBlock "SIGNAL Decode" SrcPort 10 DstBlock "Goto19" DstPort 1 } Line { SrcBlock "HT-SIG Decode" SrcPort 1 DstBlock "Goto24" DstPort 1 } Line { SrcBlock "HT-SIG Decode" SrcPort 2 DstBlock "Goto25" DstPort 1 } Line { SrcBlock "HT-SIG Decode" SrcPort 3 DstBlock "Goto6" DstPort 1 } Line { SrcBlock "HT-SIG Decode" SrcPort 4 DstBlock "Goto4" DstPort 1 } Line { SrcBlock "HT-SIG Decode" SrcPort 5 DstBlock "Goto9" DstPort 1 } Line { SrcBlock "HT-SIG Decode" SrcPort 6 DstBlock "Goto11" DstPort 1 } Line { SrcBlock "HT-SIG Decode" SrcPort 7 DstBlock "Goto13" DstPort 1 } Line { SrcBlock "HT-SIG Decode" SrcPort 8 DstBlock "Goto21" DstPort 1 } Line { SrcBlock "HT-SIG Decode" SrcPort 9 DstBlock "Goto15" DstPort 1 } Line { SrcBlock "HT-SIG Decode" SrcPort 10 DstBlock "Goto17" DstPort 1 } Line { SrcBlock "HT-SIG Decode" SrcPort 11 DstBlock "Goto18" DstPort 1 } Line { SrcBlock "Mux3" SrcPort 1 Points [15, 0] Branch { Points [0, 70] DstBlock "AddSub1" DstPort 1 } Branch { DstBlock "Register11" DstPort 1 } } Line { SrcBlock "AddSub1" SrcPort 1 Points [60, 0] Branch { Points [0, -45] DstBlock "Goto35" DstPort 1 } Branch { DstBlock "Register" DstPort 1 } } Line { SrcBlock "From7" SrcPort 1 Points [50, 0] Branch { DstBlock "Mux3" DstPort 2 } Branch { Points [0, -50] DstBlock "Goto41" DstPort 1 } } Line { SrcBlock "From8" SrcPort 1 DstBlock "Mux3" DstPort 3 } Line { SrcBlock "From16" SrcPort 1 DstBlock "Mux7" DstPort 2 } Line { SrcBlock "From10" SrcPort 1 DstBlock "Mux7" DstPort 3 } Line { SrcBlock "Mux7" SrcPort 1 DstBlock "Register3" DstPort 1 } Line { SrcBlock "From13" SrcPort 1 DstBlock "Mux8" DstPort 2 } Line { SrcBlock "From11" SrcPort 1 DstBlock "Mux8" DstPort 3 } Line { SrcBlock "Mux8" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "From12" SrcPort 1 DstBlock "Mux2" DstPort 2 } Line { SrcBlock "From9" SrcPort 1 DstBlock "Mux2" DstPort 3 } Line { SrcBlock "Mux2" SrcPort 1 Points [15, 0] Branch { DstBlock "Register1" DstPort 1 } Branch { Points [0, 30] DstBlock "Register12" DstPort 1 } } Line { SrcBlock "From14" SrcPort 1 DstBlock "Mux9" DstPort 2 } Line { SrcBlock "From15" SrcPort 1 DstBlock "Mux9" DstPort 3 } Line { SrcBlock "Mux9" SrcPort 1 DstBlock "Register9" DstPort 1 } Line { SrcBlock "Mux1" SrcPort 1 DstBlock "AddSub1" DstPort 2 } Line { SrcBlock "Constant4" SrcPort 1 DstBlock "Mux1" DstPort 2 } Line { SrcBlock "Constant6" SrcPort 1 DstBlock "Mux1" DstPort 3 } Line { SrcBlock "Logical3" SrcPort 1 DstBlock "S-R Latch1" DstPort 1 } Line { SrcBlock "S-R Latch1" SrcPort 1 Points [235, 0] Branch { DstBlock "Mux1" DstPort 1 } Branch { Points [0, -90] Branch { DstBlock "Mux3" DstPort 1 } Branch { Points [0, -115] Branch { Points [0, -70] Branch { DstBlock "Mux9" DstPort 1 } Branch { Points [0, -85] Branch { DstBlock "Mux2" DstPort 1 } Branch { Points [0, -75] Branch { DstBlock "Mux8" DstPort 1 } Branch { Points [0, -75] Branch { DstBlock "Mux7" DstPort 1 } Branch { Points [0, -75] Branch { DstBlock "Mux4" DstPort 1 } Branch { Points [0, -75] DstBlock "Mux6" DstPort 1 } } } } } } Branch { DstBlock "Mux5" DstPort 1 } } } } Line { SrcBlock "From18" SrcPort 1 DstBlock "Mux4" DstPort 2 } Line { SrcBlock "From17" SrcPort 1 DstBlock "Mux4" DstPort 3 } Line { SrcBlock "Mux4" SrcPort 1 DstBlock "Register4" DstPort 1 } Line { SrcBlock "From19" SrcPort 1 DstBlock "Concat" DstPort 1 } Line { SrcBlock "From5" SrcPort 1 DstBlock "Concat" DstPort 2 } Line { SrcBlock "From1" SrcPort 1 DstBlock "Concat" DstPort 3 } Line { SrcBlock "Concat" SrcPort 1 DstBlock "Register6" DstPort 1 } Line { SrcBlock "From20" SrcPort 1 DstBlock "Register8" DstPort 1 } Line { SrcBlock "HT-SIG Decode" SrcPort 12 DstBlock "Goto30" DstPort 1 } Line { SrcBlock "From21" SrcPort 1 DstBlock "Delay1" DstPort 1 } Line { SrcBlock "Delay1" SrcPort 1 DstBlock "Register7" DstPort 1 } Line { SrcBlock "From30" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "From24" SrcPort 1 DstBlock "Logical1" DstPort 2 } Line { SrcBlock "From25" SrcPort 1 DstBlock "Logical4" DstPort 1 } Line { SrcBlock "Logical5" SrcPort 1 Points [25, 0] Branch { Points [40, 0] Branch { DstBlock "Logical4" DstPort 3 } Branch { Points [0, 90] Branch { DstBlock "Concat1" DstPort 2 } Branch { Points [0, 40] Branch { DstBlock "Logical2" DstPort 2 } Branch { Points [0, 70] DstBlock "Logical6" DstPort 2 } } } } Branch { Points [0, 315; 275, 0] Branch { Points [0, -45; 490, 0] DstBlock "PHY_RX_DATA.BYTENUM4" DstPort 1 } Branch { DstBlock "Register16" DstPort 1 } } } Line { SrcBlock "Logical4" SrcPort 1 DstBlock "Delay" DstPort 1 } Line { SrcBlock "From27" SrcPort 1 DstBlock "Mux5" DstPort 2 } Line { SrcBlock "From28" SrcPort 1 DstBlock "Mux5" DstPort 3 } Line { SrcBlock "Mux5" SrcPort 1 DstBlock "Register10" DstPort 1 } Line { SrcBlock "From22" SrcPort 1 DstBlock "Mux6" DstPort 3 } Line { SrcBlock "Constant2" SrcPort 1 DstBlock "Mux6" DstPort 2 } Line { SrcBlock "Mux6" SrcPort 1 DstBlock "Register5" DstPort 1 } Line { SrcBlock "From29" SrcPort 1 DstBlock "Logical5" DstPort 1 } Line { SrcBlock "From26" SrcPort 1 DstBlock "Logical5" DstPort 2 } Line { SrcBlock "Logical1" SrcPort 1 Points [70, 0] Branch { DstBlock "Logical4" DstPort 2 } Branch { Points [0, 110] Branch { DstBlock "Concat1" DstPort 1 } Branch { Points [0, 55] Branch { DstBlock "Logical2" DstPort 1 } Branch { DstBlock "Logical6" DstPort 1 } } } } Line { SrcBlock "From23" SrcPort 1 DstBlock "Logical1" DstPort 3 } Line { SrcBlock "SIGNAL Decode" SrcPort 11 DstBlock "Goto36" DstPort 1 } Line { SrcBlock "Concat1" SrcPort 1 DstBlock "DOUT1" DstPort 1 } Line { SrcBlock "Delay" SrcPort 1 Points [215, 0] Branch { DstBlock "Reset PHY" DstPort 1 } Branch { Points [0, -95; 145, 0; 0, -135] DstBlock "PHY_RX_DATA.BYTENUM1" DstPort 1 } } Line { SrcBlock "Logical2" SrcPort 1 Points [55, 0] Branch { DstBlock "DOUT1" DstPort 2 } Branch { Points [0, 110] DstBlock "DOUT2" DstPort 2 } } Line { SrcBlock "DOUT1" SrcPort 1 Points [70, 0] Branch { DstBlock "Goto33" DstPort 1 } Branch { Points [0, -120; 425, 0; 0, -210] DstBlock "PHY_RX_DATA.BYTENUM2" DstPort 1 } } Line { SrcBlock "From2" SrcPort 1 DstBlock "Logical2" DstPort 3 } Line { SrcBlock "Register" SrcPort 1 DstBlock "Last Byte Ind" DstPort 1 } Line { SrcBlock "Register1" SrcPort 1 DstBlock "Goto27" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Goto22" DstPort 1 } Line { SrcBlock "Register3" SrcPort 1 DstBlock "Goto26" DstPort 1 } Line { SrcBlock "Register4" SrcPort 1 DstBlock "Goto3" DstPort 1 } Line { SrcBlock "Register5" SrcPort 1 DstBlock "Goto32" DstPort 1 } Line { SrcBlock "Register6" SrcPort 1 DstBlock "Goto23" DstPort 1 } Line { SrcBlock "Register7" SrcPort 1 DstBlock "Goto31" DstPort 1 } Line { SrcBlock "Register8" SrcPort 1 DstBlock "Goto29" DstPort 1 } Line { SrcBlock "Register9" SrcPort 1 DstBlock "Goto28" DstPort 1 } Line { SrcBlock "Register10" SrcPort 1 DstBlock "Goto34" DstPort 1 } Line { SrcBlock "Register11" SrcPort 1 DstBlock "Goto5" DstPort 1 } Line { SrcBlock "Register12" SrcPort 1 DstBlock "Goto37" DstPort 1 } Line { SrcBlock "From3" SrcPort 1 DstBlock "Register13" DstPort 1 } Line { SrcBlock "Register13" SrcPort 1 DstBlock "Goto38" DstPort 1 } Line { SrcBlock "From4" SrcPort 1 DstBlock "Logical3" DstPort 1 } Line { SrcBlock "From6" SrcPort 1 DstBlock "Logical3" DstPort 2 } Line { SrcBlock "DOUT2" SrcPort 1 DstBlock "Register15" DstPort 1 } Line { SrcBlock "Logical6" SrcPort 1 DstBlock "DOUT2" DstPort 1 } Line { SrcBlock "Register15" SrcPort 1 Points [75, 0] Branch { DstBlock "Goto40" DstPort 1 } Branch { Points [0, -205; 355, 0] DstBlock "PHY_RX_DATA.BYTENUM3" DstPort 1 } } Line { SrcBlock "PHY_RX_DATA.BYTENUM1" SrcPort 1 DstBlock "SIG Decode Err" DstPort 1 } Line { SrcBlock "PHY_RX_DATA.BYTENUM2" SrcPort 1 DstBlock "SIG Decode Err" DstPort 2 } Line { SrcBlock "PHY_RX_DATA.BYTENUM3" SrcPort 1 DstBlock "SIG Decode Err" DstPort 3 } Line { SrcBlock "PHY_RX_DATA.BYTENUM4" SrcPort 1 DstBlock "SIG Decode Err" DstPort 4 } Line { SrcBlock "Register16" SrcPort 1 DstBlock "Goto39" DstPort 1 } Annotation { Name "SIGNAL[2:0] + SERVICE[1:0] - 1" Position [873, 907] HorizontalAlignment "left" } Annotation { Name "SIGNAL[2:0] + SERVICE[1:0] +\nHT-SIG[5:0] - 1" Position [871, 932] HorizontalAlignment "left" } Annotation { Name "OFDM_RX_ERROR_NO_PAYLOAD indicates the Rx PHY\nwill not write a payload for this waveform. This occurs w" "hen\nthe HT-SIG has errors or when the HT-SIG indicates a\nwaveform this PHY does not support. The MAC must interp" "ret\nthis flag by not attempting to process whatever bytes are in\nthe Rx packet buffer.\n\nThis flag asserts imme" "diately after HT-SIG and can be interpretted\nby the MAC when RX_PARAMS_READY asserts, if desired.\n\nThe Rx PHY w" "ill use this flag to hold the RX_END_ERROR output\nhigh until the RX_END signal has asserted. The MAC uses RX_END\n" "to qualify RX_END_ERROR." Position [1589, 1267] HorizontalAlignment "left" } Annotation { Name "Important rules for these signals:\n-OFDM_RX_START will assert for 1 cycle after a valid SIGNAL field is" " decoded\n-OFDM_RX_DATA_PARAMS_Valid may assert sometime after OFDM_RX_START for 1 cycle. This\n does *not* indic" "ate the PHY will continue decoding bytes. The MAC must check the RX_END_ERROR\n signal to determine what the PHY " "is doing.\n-RX_END_ERROR asserts with a non-zero value when the PHY determines it cannot continue decoding\n a wa" "veform. The current conditions for this are:\n -SIGNAL is invalid (bad parity bit, invalid RATE or LENGTH value)" "\n -HT-SIG is invalid (bad MCS, bad TAIL or bad CRC)\n -HT-SIG.MCS is unsupported" Position [156, 1007] HorizontalAlignment "left" } Annotation { Name "Delay here to ensure downstream logic using\nthe RX_END_ERROR signal sees a pulse before\nthe reset clea" "rs the error condition by reverting\nthe SIGNAL/HT-SIG registers to their defaults" Position [1233, 1051] HorizontalAlignment "left" } Annotation { Name "Capture RX_ERROR value at time error is observed. MAC should\nignore RX_ERROR when (RX_END = 0) anyway, " "so\nholding potentially stale value here is ok." Position [537, 1399] HorizontalAlignment "left" } Annotation { Name "Pipeline here for timing closure; could be\nan issue for 0-length NDP in future rev?" Position [1309, 945] HorizontalAlignment "left" } Annotation { Name "Explicit fanout for better timing; two blocks\nuse this signal, but they're far apart in the pipeline" Position [1492, 560] HorizontalAlignment "left" } Annotation { Name "HT_SIG_ERROR indicates the HT-SIG field had errors. This will reset\nthe PHY pipeline (see comment above" "). It will also reset the length/rate\nblock in the PHY CCA subsystem. This reset will cause an immediate RX_END\n" "event to the MAC. In the case of an invalid HT-SIG the Rx PHY does not know \nhow long the waveform will last. Res" "etting everything and using physical CCA\nis the best fallback option." Position [1584, 1472] HorizontalAlignment "left" } Annotation { Name "Delay ERROR outputs so REASON\nvalue is captured on ERROR" Position [1297, 1395] } } } Block { BlockType SubSystem Name "Safe ToUint8" SID "2449" Ports [1, 1] Position [785, 715, 830, 745] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Safe ToUint8" Location [149, 142, 2075, 1366] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" SID "2450" Position [160, 218, 190, 232] IconDisplay "Port number" } Block { BlockType Reference Name "Convert1" SID "2451" Ports [1, 1] Position [605, 231, 625, 249] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "8" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "20,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 20 20 0 0 ],[0 0 18 18 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[11.22 11.22 13." "22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[9.22 9.22 11.22 11.22 9.22 ],[0" ".931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([7.55 14.44" " 12.44 10.44 8.44 5.55 7.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: e" "nd icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cast');\nfpr" "intf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Indet Check" SID "2452" Ports [1, 1] Position [325, 210, 380, 240] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Indet Check" Location [149, 142, 2075, 1366] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "In1" SID "2453" Position [25, 53, 55, 67] IconDisplay "Port number" } Block { BlockType Reference Name "Constant" SID "2454" Ports [0, 1] Position [185, 79, 210, 101] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "8" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,400,346" block_type "constant" block_version "10.1.3" sg_icon_stat "25,22,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 22 22 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[14.33 " "14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 1 " "1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('output',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Disregard Subsystem" SID "2455" Tag "discardX" Ports [] Position [348, 257, 406, 315] ShowName off AttributesFormatString "Disregard Subsystem\\nFor Generation" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Disregard Subsystem" SourceType "Xilinx Disregard Subsystem For Generation Block" infoedit "Place this block into a subsystem to have System Generator ignore the subsystem during code gener" "ation. This block can be used in combination with the Simulation Multiplexer block to provide an alternative sim" "ulation model for another subsystem (e.g., to provide a simulation model for a black box)." has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "disregard" sg_icon_stat "58,58,-1,-1,darkgray,black,0,07734,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 58 58 0 0 ],[0 0 58 58 0 ],[0.1 0.1 0" ".1 ]);\nplot([0 58 58 0 0 ],[0 0 58 58 0 ]);\npatch([11.2 22.76 30.76 38.76 46.76 30.76 19.2 11.2 ],[37.88 37.88" " 45.88 37.88 45.88 45.88 45.88 37.88 ],[0.33 0.33 0.33 ]);\npatch([19.2 30.76 22.76 11.2 19.2 ],[29.88 29.88 37." "88 37.88 29.88 ],[0.261 0.261 0.261 ]);\npatch([11.2 22.76 30.76 19.2 11.2 ],[21.88 21.88 29.88 29.88 21.88 ],[0" ".33 0.33 0.33 ]);\npatch([19.2 46.76 38.76 30.76 22.76 11.2 19.2 ],[13.88 13.88 21.88 13.88 21.88 21.88 13.88 ]," "[0.261 0.261 0.261 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nfpri" "ntf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway In" SID "2456" Ports [1, 1] Position [165, 30, 230, 50] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to X" "ilinx fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top level" " input ports." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "16" bin_pt "14" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0.93" " 0.65 ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12.22" " 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 12." "22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1" " 1 1 ]);\npatch([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 " "0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');po" "rt_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfpri" "ntf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Indeterminate Probe" SID "8483" Ports [1, 1] Position [120, 27, 145, 53] LibraryVersion "1.2" LinkData { BlockName "Gateway Out" DialogParameters { sg_icon_stat "40,20,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0.93" " 0.65 ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12.22" " 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 12." "22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1" " 1 1 ]);\npatch([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 " "0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');po" "rt_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfpr" "intf('','COMMENT: end icon text');" } } SourceBlock "xbsIndex_r4/Indeterminate Probe" SourceType "Xilinx Indeterminate Probe Block" infoedit "Produces an output 1 of type double when input data is indeterminate. Output is 0 otherwise.
<" "br>Hardware notes: This block and any downstream blocks will be trimmed when hardware is generated." has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "indetprobe" sg_icon_stat "25,26,1,1,white,yellow,4,1c4257669fa6f259d9bb3743f2c8140f,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([25 24.7598 24.0485 22.8934 21.3388 19.4" "446 17.2835 14.9386 12.5 10.0614 7.71646 5.55537 3.66117 2.10663 0.951506 0.240184 0 0.240184 0.951506 2.10663 3" ".66117 5.55537 7.71646 10.0614 12.5 14.9386 17.2835 19.4446 21.3388 22.8934 24.0485 24.7598 25 25 ],[13 15.5362 " "17.9749 20.2224 22.1924 23.8091 25.0104 25.7502 26 25.7502 25.0104 23.8091 22.1924 20.2224 17.9749 15.5362 13 10" ".4638 8.02512 5.77759 3.80761 2.1909 0.989566 0.249791 0 0.249791 0.989566 2.1909 3.80761 5.77759 8.02512 10.463" "8 13 13 ],[0.95 0.93 0.65 ]);\nplot([25 24.7598 24.0485 22.8934 21.3388 19.4446 17.2835 14.9386 12.5 10.0614 7.7" "1646 5.55537 3.66117 2.10663 0.951506 0.240184 0 0.240184 0.951506 2.10663 3.66117 5.55537 7.71646 10.0614 12.5 " "14.9386 17.2835 19.4446 21.3388 22.8934 24.0485 24.7598 25 25 ],[13 15.5362 17.9749 20.2224 22.1924 23.8091 25.0" "104 25.7502 26 25.7502 25.0104 23.8091 22.1924 20.2224 17.9749 15.5362 13 10.4638 8.02512 5.77759 3.80761 2.1909" " 0.989566 0.249791 0 0.249791 0.989566 2.1909 3.80761 5.77759 8.02512 10.4638 13 13 ]);\npatch([5.325 9.66 12.66" " 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12." "66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.33 ],[0.985 0.979 0.895 ]);\npatch([5.325 9.66 12.66 8.325 5.3" "25 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 1" "0.33 7.33 10.33 10.33 7.33 ],[0.985 0.979 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMM" "ENT: begin icon text');\nfprintf('','COMMENT: end icon text');disp('!def');\n" } Block { BlockType Reference Name "Mux1" SID "2458" Ports [3, 1] Position [260, 27, 290, 103] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" block_version "10.1.3" sg_icon_stat "30,76,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 10.8571 65.1429 76 0 ]" ",[0.77 0.82 0.91 ]);\nplot([0 30 30 0 0 ],[0 10.8571 65.1429 76 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 " "10.1 6.1 ],[42.44 42.44 46.44 42.44 46.44 46.44 46.44 42.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[38" ".44 38.44 42.44 42.44 38.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[34.44 34.44 38.44 38.44" " 34.44 ],[1 1 1 ]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[30.44 30.44 34.44 30.44 34.44 34.44 30.44 ]" ",[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncol" "or('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label(" "'input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Out1" SID "2459" Position [370, 58, 400, 72] IconDisplay "Port number" } Line { SrcBlock "Gateway In" SrcPort 1 DstBlock "Mux1" DstPort 1 } Line { SrcBlock "Constant" SrcPort 1 DstBlock "Mux1" DstPort 3 } Line { SrcBlock "Indeterminate Probe" SrcPort 1 DstBlock "Gateway In" DstPort 1 } Line { SrcBlock "Mux1" SrcPort 1 DstBlock "Out1" DstPort 1 } Line { SrcBlock "In1" SrcPort 1 Points [15, 0] Branch { Points [90, 0; 0, 5] DstBlock "Mux1" DstPort 2 } Branch { Points [0, -20] DstBlock "Indeterminate Probe" DstPort 1 } } } } Block { BlockType Reference Name "Simulation Multiplexer" SID "2460" Ports [2, 1] Position [505, 212, 555, 263] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Simulation Multiplexer" SourceType "Xilinx Simulation Multiplexer Block" infoedit "Distinguish input subsystems as \"simulation only\" and \"generation only\". The input specified For" " Simulation will be used during Simulink simulation. The input specified For Generation will be used during code " "generation. This block will typically be used on the output of a HW Co-Simulation, Black Box, or ModelSim subsyst" "em.

Hardware Notes: This block costs nothing." sim_sel "1" hw_sel "2" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "simmux" sg_icon_stat "50,51,2,1,white,blue,0,4170dd71,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 51 51 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 50 50 0 0 ],[0 0 51 51 0 ]);\npatch([9.425 19.54 26.54 33.54 40.54 26.54 16.425 9.425 ],[32.77 32.7" "7 39.77 32.77 39.77 39.77 39.77 32.77 ],[1 1 1 ]);\npatch([16.425 26.54 19.54 9.425 16.425 ],[25.77 25.77 32.77 32" ".77 25.77 ],[0.931 0.946 0.973 ]);\npatch([9.425 19.54 26.54 16.425 9.425 ],[18.77 18.77 25.77 25.77 18.77 ],[1 1 " "1 ]);\npatch([16.425 40.54 33.54 26.54 19.54 9.425 16.425 ],[11.77 11.77 18.77 11.77 18.77 18.77 11.77 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\nfprintf('" "','COMMENT: end icon text');color('red');\nplot(swLineX,simSwLineY);\ncolor('black');\nplot(swLineX,hwSwLineY);\n" } Block { BlockType Outport Name "B" SID "2461" Position [675, 233, 705, 247] IconDisplay "Port number" } Line { SrcBlock "A" SrcPort 1 Points [15, 0] Branch { Labels [0, 0] DstBlock "Indet Check" DstPort 1 } Branch { Points [0, 25] DstBlock "Simulation Multiplexer" DstPort 2 } } Line { SrcBlock "Indet Check" SrcPort 1 DstBlock "Simulation Multiplexer" DstPort 1 } Line { SrcBlock "Simulation Multiplexer" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "B" DstPort 1 } Annotation { Name "Simulation-only block: Sets output to 0\nif input is indeterminate, which occurs at\nthe blackbox output" "s before the first reset" Position [311, 304] } } } Block { BlockType SubSystem Name "Stretch" SID "2462" Ports [1, 1] Position [1770, 934, 1815, 956] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Stretch" Location [1799, 573, 2256, 904] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "155" Block { BlockType Inport Name "D" SID "2463" Position [85, 593, 115, 607] IconDisplay "Port number" } Block { BlockType Reference Name "Constant2" SID "2464" Ports [0, 1] Position [610, 605, 645, 635] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "160" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "8" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,30,0,1,white,blue,0,1d99491c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 30 30 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[19.44 19.44 23.4" "4 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[15.44 15.44 19.44 19.44 15.44 ]," "[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([12.1" " 25.88 21.88 17.88 13.88 8.1 12.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'160')" ";\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Counter1" SID "2465" Ports [2, 1] Position [515, 551, 575, 629] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited counter i" "s implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "Inf" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "8" bin_pt "0" load_pin off rst on en on explicit_period "off" period "1" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "counter" sg_icon_stat "60,78,2,1,white,blue,0,ae3608d6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 78 78 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 60 60 0 0 ],[0 0 78 78 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[47.88 47.88 55" ".88 47.88 55.88 55.88 55.88 47.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[39.88 39.88 47.88 47.88 39.88" " ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[31.88 31.88 39.88 39.88 31.88 ],[1 1 1 ]);\npatch(" "[20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[23.88 23.88 31.88 23.88 31.88 31.88 23.88 ],[0.931 0.946 0.973 ]);\nfpr" "intf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'" ",1,'rst');\ncolor('black');port_label('input',2,'en');\n\ncolor('black');disp('{\\fontsize{14}\\bf++}','texmode','" "on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "2466" Ports [1, 1] Position [445, 560, 480, 580] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "35,20,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 20 20 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[12.22 12.22" " 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[10.22 10.22 12.22 12.22" " 10.22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\n" "patch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter1" SID "2467" Ports [1, 1] Position [255, 625, 290, 645] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "35,20,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 20 20 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[12.22 12.22" " 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[10.22 10.22 12.22 12.22" " 10.22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\n" "patch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "2468" Ports [2, 1] Position [700, 507, 730, 538] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "30,31,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 31 31 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 31 31 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 19.44 23.4" "4 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 19.44 15.44 ]," "[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([10.1" " 23.88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('or');\nfprintf('" "','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "2469" Ports [2, 1] Position [365, 592, 395, 623] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "30,31,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 31 31 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 31 31 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 19.44 23.4" "4 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 19.44 15.44 ]," "[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([10.1" " 23.88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('and');\nfprintf(" "'','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational3" SID "2470" Ports [2, 1] Position [700, 575, 735, 635] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a>=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,60,2,1,white,blue,0,6218dc92,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 60 60 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 60 60 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[35.55 35.55 40." "55 35.55 40.55 40.55 40.55 35.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[30.55 30.55 35.55 35.55 30." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[25.55 25.55 30.55 30.55 25.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[20.55 20.55 25.55 20.55 25.55 25.55 20.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i" "nput',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa \\geq b','te" "xmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "S-R Latch1" SID "2471" Ports [2, 1] Position [255, 593, 290, 622] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "S-R Latch1" Location [351, 366, 2001, 1172] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "2472" Position [140, 103, 170, 117] IconDisplay "Port number" } Block { BlockType Inport Name "R" SID "2473" Position [140, 88, 170, 102] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "2474" Ports [0, 1] Position [195, 71, 210, 89] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "15,18,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11.22 " "13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 9.22 " "],[0.931 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([4.55 " "11.44 9.44 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "2475" Ports [1, 1] Position [230, 86, 255, 104] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('outpu" "t',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "2476" Ports [1, 1] Position [230, 101, 255, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('outpu" "t',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "2477" Ports [3, 1] Position [300, 71, 345, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "2478" Position [370, 88, 400, 102] IconDisplay "Port number" } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "S" SrcPort 1 DstBlock "Convert2" DstPort 1 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "Convert2" SrcPort 1 DstBlock "Register2" DstPort 3 } } } Block { BlockType Outport Name "Q" SID "2479" Position [830, 518, 860, 532] IconDisplay "Port number" } Line { SrcBlock "Counter1" SrcPort 1 DstBlock "Relational3" DstPort 1 } Line { SrcBlock "Constant2" SrcPort 1 DstBlock "Relational3" DstPort 2 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Counter1" DstPort 1 } Line { SrcBlock "D" SrcPort 1 Points [55, 0] Branch { Points [0, -85] DstBlock "Logical1" DstPort 1 } Branch { DstBlock "S-R Latch1" DstPort 1 } Branch { Points [0, 35] DstBlock "Inverter1" DstPort 1 } } Line { SrcBlock "Relational3" SrcPort 1 Points [0, 50; -525, 0; 0, -40] DstBlock "S-R Latch1" DstPort 2 } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "Logical2" SrcPort 1 Points [30, 0] Branch { DstBlock "Counter1" DstPort 2 } Branch { DstBlock "Inverter" DstPort 1 } } Line { SrcBlock "S-R Latch1" SrcPort 1 Points [25, 0; 0, -10] Branch { DstBlock "Logical2" DstPort 1 } Branch { Points [0, -70] DstBlock "Logical1" DstPort 2 } } Line { SrcBlock "Inverter1" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical2" DstPort 2 } Annotation { Name "Extend duration of reset pulse for use by upstream blocks.\nA few subsystems require a reset pulse longe" "r than their own\nlatency (like the logic counting input samples to the FFT).\nExtending the pulse here is more ef" "ficient that adding extensions\nin each subsystem." Position [296, 435] HorizontalAlignment "left" } } } Block { BlockType ToWorkspace Name "To Workspace2" SID "18100" Ports [1] Position [420, 165, 480, 195] ZOrder -7 VariableName "rx_bits_enc" MaxDataPoints "inf" SampleTime "-1" SaveFormat "Array" } Block { BlockType ToWorkspace Name "To Workspace3" SID "18101" Ports [1] Position [420, 220, 480, 250] ZOrder -7 VariableName "rx_bits_enc_valid" MaxDataPoints "inf" SampleTime "-1" SaveFormat "Array" } Block { BlockType Reference Name "Viberbi Decoder" SID "2480" Ports [8, 3] Position [630, 480, 745, 775] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Black Box" SourceType "Xilinx Black Box Block" infoedit " Incorporates black box HDL and simulation model into a System Generator design.

You mu" "st supply a Black Box with certain information about the HDL component you would like to bring into System Gene" "rator. This information is provided through a Matlab function.

When \"Simulation mode\" is set to \"Inac" "tive\", you will typically want to provide a separate simulation model by using a Simulation Multiplexer.
Wh" "en \"Simulation mode\" is set to \"External co-simulator\", you must include a ModelSim block in the design." init_code "vb_decoder_top_config" sim_method "ISE Simulator" verbose off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "blackbox2" sg_icon_stat "115,295,8,3,white,blue,0,d9089f87,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 115 115 0 0 ],[0 0 295 295 0 ],[0." "77 0.82 0.91 ]);\nplot([0 115 115 0 0 ],[0 0 295 295 0 ]);\npatch([21.4 44.52 60.52 76.52 92.52 60.52 37.4 21.4" " ],[164.76 164.76 180.76 164.76 180.76 180.76 180.76 164.76 ],[1 1 1 ]);\npatch([37.4 60.52 44.52 21.4 37.4 ],[" "148.76 148.76 164.76 164.76 148.76 ],[0.931 0.946 0.973 ]);\npatch([21.4 44.52 60.52 37.4 21.4 ],[132.76 132.76" " 148.76 148.76 132.76 ],[1 1 1 ]);\npatch([37.4 92.52 76.52 60.52 44.52 21.4 37.4 ],[116.76 116.76 132.76 116.7" "6 132.76 132.76 116.76 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT" ": begin icon text');\ncolor('black');port_label('input',1,'llr_b1');\ncolor('black');port_label('input',2,'llr_" "b0');\ncolor('black');port_label('input',3,'vin');\ncolor('black');port_label('input',4,'nrst');\ncolor('black'" ");port_label('input',5,'packet_start');\ncolor('black');port_label('input',6,'packet_end');\ncolor('black');por" "t_label('input',7,'early_trace1');\ncolor('black');port_label('input',8,'early_trace2');\ncolor('black');port_l" "abel('output',1,'done');\ncolor('black');port_label('output',2,'vout');\ncolor('black');port_label('output',3,'" "dout_in_byte');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Byte" SID "2481" Position [1165, 723, 1195, 737] IconDisplay "Port number" } Block { BlockType Outport Name "Byte Valid" SID "2482" Position [1390, 758, 1420, 772] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "Byte Index" SID "2483" Position [1390, 808, 1420, 822] NamePlacement "alternate" Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "Last Byte" SID "2484" Position [1390, 828, 1420, 842] Port "4" IconDisplay "Port number" } Block { BlockType Outport Name " Reset" SID "2485" Position [2100, 948, 2130, 962] NamePlacement "alternate" Port "5" IconDisplay "Port number" } Line { SrcBlock "Register" SrcPort 1 Points [220, 0] Branch { DstBlock "Reinterpret" DstPort 1 } Branch { Points [0, -290] Branch { DstBlock "Gateway Out11" DstPort 1 } Branch { Points [0, -150] DstBlock "Goto9" DstPort 1 } } } Line { SrcBlock "Register4" SrcPort 1 Points [215, 0] Branch { DstBlock "Reinterpret2" DstPort 1 } Branch { Points [0, -350] Branch { DstBlock "Gateway Out10" DstPort 1 } Branch { Points [0, -145] DstBlock "Goto10" DstPort 1 } } } Line { SrcBlock "Register5" SrcPort 1 DstBlock "Control" DstPort 1 } Line { SrcBlock "Viberbi Decoder" SrcPort 2 Points [15, 0] Branch { DstBlock "Convert3" DstPort 1 } Branch { Points [0, 170; -450, 0; 0, -45] DstBlock "Control" DstPort 5 } } Line { SrcBlock "Viberbi Decoder" SrcPort 3 DstBlock "Safe ToUint8" DstPort 1 } Line { SrcBlock "Start" SrcPort 1 DstBlock "Assert4" DstPort 1 } Line { SrcBlock "Safe ToUint8" SrcPort 1 DstBlock "Endian Swap" DstPort 1 } Line { SrcBlock "Byte Count" SrcPort 2 Points [20, 0] Branch { Points [100, 0] Branch { Points [80, 0] Branch { DstBlock "Byte Index" DstPort 1 } Branch { Points [0, -125] DstBlock "Goto7" DstPort 1 } } Branch { Points [0, -400] DstBlock "Gateway Out5" DstPort 1 } } Branch { Labels [0, 0] Points [0, 105] DstBlock "SIGNAL & HT-SIG\nDecode" DstPort 1 } } Line { Name "Vout" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 DstBlock "Decoder I/O" DstPort 11 } Line { Name "Byte Index" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 DstBlock "Decoder I/O" DstPort 10 } Line { Name "Last Byte" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 DstBlock "Decoder I/O" DstPort 9 } Line { Name "LLR Valid" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 DstBlock "Decoder I/O" DstPort 6 } Line { Name "Start" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 DstBlock "Decoder I/O" DstPort 7 } Line { Name "End" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 DstBlock "Decoder I/O" DstPort 8 } Line { SrcBlock "Assert11" SrcPort 1 Points [10, 0] Branch { Points [0, 80; -870, 0; 0, -40] DstBlock "Logical2" DstPort 2 } Branch { DstBlock "Stretch" DstPort 1 } } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Assert11" DstPort 1 } Line { Name "Reset Out" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 DstBlock "Decoder I/O" DstPort 12 } Line { SrcBlock "Logical2" SrcPort 1 DstBlock "SIGNAL & HT-SIG\nDecode" DstPort 4 } Line { SrcBlock "Vin" SrcPort 1 Points [35, 0] Branch { DstBlock "Assert2" DstPort 1 } Branch { Points [0, -340] DstBlock "Gateway Out14" DstPort 1 } } Line { SrcBlock "LLR B" SrcPort 1 Points [10, 0] Branch { DstBlock "Assert1" DstPort 1 } Branch { Points [0, -225; -40, 0; 0, -150; 10, 0; 0, 5] DstBlock "Gateway Out16" DstPort 1 } } Line { SrcBlock "LLR A" SrcPort 1 Points [15, 0] Branch { DstBlock "Assert" DstPort 1 } Branch { Points [0, -205; -45, 0; 0, -105] DstBlock "Gateway Out13" DstPort 1 } } Line { SrcBlock "Byte Count" SrcPort 3 Points [115, 0] Branch { Points [115, 0] Branch { DstBlock "Last Byte" DstPort 1 } Branch { Points [0, 85] DstBlock "Delay" DstPort 1 } } Branch { Points [0, -445] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "SIGNAL & HT-SIG\nDecode" SrcPort 1 Points [15, 0; 0, -50; -305, 0] Branch { DstBlock "Byte Count" DstPort 3 } Branch { Points [-685, 0; 0, -170] DstBlock "Control" DstPort 4 } } Line { SrcBlock "Byte Count" SrcPort 1 Points [10, 0] Branch { Points [220, 0; 0, -30] Branch { DstBlock "Byte Valid" DstPort 1 } Branch { Points [0, -45] Branch { DstBlock "Goto6" DstPort 1 } Branch { Points [0, -280] DstBlock "Gateway Out1" DstPort 1 } } } Branch { Labels [0, 0] Points [0, 145] DstBlock "SIGNAL & HT-SIG\nDecode" DstPort 2 } } Line { SrcBlock "Stretch" SrcPort 1 Points [20, 0] Branch { Points [0, -395; -455, 0; 0, -85] DstBlock "Gateway Out8" DstPort 1 } Branch { DstBlock "Logical3" DstPort 1 } } Line { SrcBlock "Convert3" SrcPort 1 Points [55, 0] Branch { Points [10, 0; 0, 165] DstBlock "Byte Count" DstPort 1 } Branch { Points [0, -200] DstBlock "Goto4" DstPort 1 } } Line { Name "Reset#" Labels [0, 0] SrcBlock "Gateway Out9" SrcPort 1 DstBlock "Decoder I/O" DstPort 5 } Line { SrcBlock "Delay" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { Name "LLR B0" Labels [0, 0] SrcBlock "Gateway Out10" SrcPort 1 DstBlock "Decoder I/O" DstPort 1 } Line { Name "LLR B1" Labels [0, 0] SrcBlock "Gateway Out11" SrcPort 1 DstBlock "Decoder I/O" DstPort 2 } Line { Name "Early Trace 1" Labels [0, 0] SrcBlock "Gateway Out12" SrcPort 1 DstBlock "Decoder I/O" DstPort 3 } Line { SrcBlock "Control" SrcPort 1 Points [25, 0] Branch { DstBlock "Viberbi Decoder" DstPort 3 } Branch { Points [0, -260] Branch { DstBlock "Gateway Out4" DstPort 1 } Branch { Points [0, -210] DstBlock "Goto1" DstPort 1 } } } Line { SrcBlock "Control" SrcPort 2 Points [20, 0] Branch { DstBlock "Viberbi Decoder" DstPort 4 } Branch { Points [0, -320] Branch { DstBlock "Gateway Out9" DstPort 1 } Branch { Points [0, -205] DstBlock "Goto8" DstPort 1 } } } Line { SrcBlock "Control" SrcPort 3 Points [30, 0] Branch { DstBlock "Viberbi Decoder" DstPort 5 } Branch { Points [0, -305] Branch { DstBlock "Gateway Out2" DstPort 1 } Branch { Points [0, -215] DstBlock "Goto2" DstPort 1 } } } Line { SrcBlock "Control" SrcPort 4 Points [40, 0] Branch { DstBlock "Viberbi Decoder" DstPort 6 } Branch { Points [0, -315] Branch { DstBlock "Gateway Out3" DstPort 1 } Branch { Points [0, -220] DstBlock "Goto3" DstPort 1 } } } Line { SrcBlock "Control" SrcPort 5 Points [50, 0] Branch { DstBlock "Viberbi Decoder" DstPort 7 } Branch { Points [0, -475] DstBlock "Gateway Out12" DstPort 1 } } Line { SrcBlock "Reset" SrcPort 1 DstBlock "Assert3" DstPort 1 } Line { SrcBlock "Reinterpret" SrcPort 1 DstBlock "Viberbi Decoder" DstPort 1 } Line { SrcBlock "Reinterpret2" SrcPort 1 DstBlock "Viberbi Decoder" DstPort 2 } Line { SrcBlock "Control" SrcPort 6 Points [65, 0] Branch { DstBlock "Viberbi Decoder" DstPort 8 } Branch { Points [0, -485] DstBlock "Gateway Out7" DstPort 1 } } Line { Name "Early Trace 2" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 DstBlock "Decoder I/O" DstPort 4 } Line { SrcBlock "Endian Swap" SrcPort 1 Points [30, 0] Branch { DstBlock "Byte" DstPort 1 } Branch { Points [0, -280] DstBlock "Goto5" DstPort 1 } Branch { Labels [0, 0] Points [0, 230] DstBlock "SIGNAL & HT-SIG\nDecode" DstPort 3 } } Line { SrcBlock "From1" SrcPort 1 DstBlock "Logical1" DstPort 2 } Line { SrcBlock "SIGNAL & HT-SIG\nDecode" SrcPort 2 DstBlock "Logical1" DstPort 3 } Line { SrcBlock "Assert" SrcPort 1 DstBlock "Register" DstPort 1 } Line { SrcBlock "Assert1" SrcPort 1 DstBlock "Register4" DstPort 1 } Line { SrcBlock "Assert2" SrcPort 1 DstBlock "Register5" DstPort 1 } Line { SrcBlock "Assert3" SrcPort 1 DstBlock "Control" DstPort 2 } Line { SrcBlock "Assert4" SrcPort 1 Points [85, 0] Branch { Points [0, 150] Branch { Labels [1, 0] DstBlock "Byte Count" DstPort 2 } Branch { Points [0, 155] DstBlock "Logical2" DstPort 1 } } Branch { DstBlock "Control" DstPort 3 } } Line { SrcBlock "From2" SrcPort 1 DstBlock "Logical3" DstPort 2 } Line { SrcBlock "Logical3" SrcPort 1 DstBlock " Reset" DstPort 1 } Line { SrcBlock "Gateway Out14" SrcPort 1 DstBlock "To Workspace3" DstPort 1 } Line { SrcBlock "Bus Creator" SrcPort 1 DstBlock "To Workspace2" DstPort 1 } Line { SrcBlock "Gateway Out16" SrcPort 1 DstBlock "Bus Creator" DstPort 1 } Line { SrcBlock "Gateway Out13" SrcPort 1 Points [40, 0] DstBlock "Bus Creator" DstPort 2 } Annotation { Name "Required to avoid combinational loop\nback to BB reset input" Position [1450, 892] } Annotation { Name "Flush the OFDM pipeline if DSSS Rx starts" Position [2019, 982] } } } Block { BlockType SubSystem Name "Descramble" SID "2486" Ports [4, 4] Position [1105, 57, 1220, 183] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off Port { PortNumber 1 Name "byte" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 2 Name "byte_valid" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 3 Name "byte_index" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 4 Name "last_byte" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } System { Name "Descramble" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "80" Block { BlockType Inport Name "Byte" SID "2487" Position [365, 278, 395, 292] IconDisplay "Port number" } Block { BlockType Inport Name "Byte Valid" SID "2488" Position [510, 333, 540, 347] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "Byte Index" SID "2489" Position [510, 448, 540, 462] NamePlacement "alternate" Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "Last Byte" SID "2490" Position [510, 578, 540, 592] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "Constant" SID "2491" Ports [0, 1] Position [355, 460, 385, 480] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "3" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "4" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,20,0,1,white,blue,0,279a71c8,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 20 20 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 20 20 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[1" "2.22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[10.22 10.2" "2 12.22 12.22 10.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[8.22 8.22 10.22 10.22 8.2" "2 ],[1 1 1 ]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931" " 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('output',1,'3');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant2" SID "2492" Ports [0, 1] Position [355, 500, 385, 520] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "9" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "4" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,20,0,1,white,blue,0,350ae870,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 20 20 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 20 20 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[1" "2.22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[10.22 10.2" "2 12.22 12.22 10.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[8.22 8.22 10.22 10.22 8.2" "2 ],[1 1 1 ]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931" " 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('output',1,'9');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "DOUT" SID "2493" Ports [2, 1] Position [1245, 376, 1280, 409] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,33,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 33 33 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 33 33 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[20.44 " "20.44 24.44 20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[16.44 16.44 20.44 2" "0.44 16.44 ],[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1 1 1 " "]);\npatch([12.1 25.88 21.88 17.88 13.88 8.1 12.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\nc" "olor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay" SID "2494" Ports [1, 1] Position [720, 267, 755, 303] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "3" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,36,1,1,white,blue,0,83e6bb61,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 36 36 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 36 36 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[23.55" " 23.55 28.55 23.55 28.55 28.55 28.55 23.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[18.55 18.55 23" ".55 23.55 18.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[13.55 13.55 18.55 18.55 13.55 " "],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[8.55 8.55 13.55 8.55 13.55 13.55 8.55 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor(" "'black');disp('z^{-3}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay1" SID "2495" Ports [1, 1] Position [720, 567, 755, 603] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "3" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,36,1,1,white,blue,0,83e6bb61,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 36 36 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 36 36 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[23.55" " 23.55 28.55 23.55 28.55 28.55 28.55 23.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[18.55 18.55 23" ".55 23.55 18.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[13.55 13.55 18.55 18.55 13.55 " "],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[8.55 8.55 13.55 8.55 13.55 13.55 8.55 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor(" "'black');disp('z^{-3}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay3" SID "2496" Ports [1, 1] Position [720, 322, 755, 358] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "3" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,36,1,1,white,blue,0,83e6bb61,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 36 36 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 36 36 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[23.55" " 23.55 28.55 23.55 28.55 28.55 28.55 23.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[18.55 18.55 23" ".55 23.55 18.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[13.55 13.55 18.55 18.55 13.55 " "],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[8.55 8.55 13.55 8.55 13.55 13.55 8.55 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor(" "'black');disp('z^{-3}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay4" SID "2497" Ports [1, 1] Position [720, 507, 755, 543] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "3" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,36,1,1,white,blue,0,83e6bb61,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 36 36 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 36 36 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[23.55" " 23.55 28.55 23.55 28.55 28.55 28.55 23.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[18.55 18.55 23" ".55 23.55 18.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[13.55 13.55 18.55 18.55 13.55 " "],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[8.55 8.55 13.55 8.55 13.55 13.55 8.55 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor(" "'black');disp('z^{-3}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Scope Name "Descram" SID "2498" Ports [6] Position [1585, 203, 1620, 302] ZOrder -3 Floating off Location [886, 677, 2143, 1591] Open off NumInputPorts "6" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" } List { ListType ScopeGraphics FigureColor "[0.5 0.5 0.5]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "10000 " YMin "0~0~32.5~-1~-1~0" YMax "1~275~52.5~1~1~250" SaveName "ScopeData18" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType SubSystem Name "Descram Byte Calc" SID "2499" Ports [4, 1] Position [680, 414, 800, 481] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Descram Byte Calc" Location [138, 279, 2039, 1431] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "105" Block { BlockType Inport Name "data_byte" SID "2500" Position [365, 368, 395, 382] IconDisplay "Port number" } Block { BlockType Inport Name "data_valid" SID "2501" Position [305, 413, 335, 427] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "data_ind" SID "2502" Position [100, 428, 130, 442] NamePlacement "alternate" Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "Svc byte ind" SID "2503" Position [100, 458, 130, 472] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "3LSB1" SID "2504" Ports [1, 1] Position [950, 411, 990, 429] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type" " is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardw" "are notes: In hardware this block costs nothing." nbits "3" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22 11.22" " 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22 11.22 9" ".22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch" "([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output'" ",1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "4MSB1" SID "2505" Ports [1, 1] Position [950, 451, 990, 469] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type" " is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardw" "are notes: In hardware this block costs nothing." nbits "4" boolean_output off mode "Upper Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22 11.22" " 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22 11.22 9" ".22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch" "([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output'" ",1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Concat1" SID "2506" Ports [2, 1] Position [1035, 401, 1090, 479] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point at z" "ero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "55,78,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 78 78 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 55 55 0 0 ],[0 0 78 78 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ],[46.77 46" ".77 53.77 46.77 53.77 53.77 53.77 46.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[39.77 39.77 46.77" " 46.77 39.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[32.77 32.77 39.77 39.77 32.77 ]," "[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[25.77 25.77 32.77 25.77 32.77 32.77 25.77 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fontsize{2" "0}\\}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant1" SID "2507" Ports [0, 1] Position [1380, 560, 1410, 580] BlockMirror on NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "126" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "7" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,20,0,1,white,blue,0,09533140,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 20 20 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[12.22 12.22" " 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[10.22 10.22 12.22 12.22" " 10.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\n" "patch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('outp" "ut',1,'126');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant2" SID "2508" Ports [0, 1] Position [1490, 405, 1520, 425] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "8" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,20,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 20 20 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[12.22 12.22" " 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[10.22 10.22 12.22 12.22" " 10.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\n" "patch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('outp" "ut',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Counter" SID "2509" Ports [4, 1] Position [1250, 417, 1310, 478] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited counter i" "s implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "126" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "7" bin_pt "0" load_pin on rst on en on explicit_period "off" period "1" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "counter" sg_icon_stat "60,61,4,1,white,blue,0,cf0879bb,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 61 61 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 60 60 0 0 ],[0 0 61 61 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[38.88 38.88 46" ".88 38.88 46.88 46.88 46.88 38.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[30.88 30.88 38.88 38.88 30.88" " ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[22.88 22.88 30.88 30.88 22.88 ],[1 1 1 ]);\npatch(" "[20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[14.88 14.88 22.88 14.88 22.88 22.88 14.88 ],[0.931 0.946 0.973 ]);\nfpr" "intf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'" ",1,'load');\ncolor('black');port_label('input',2,'din');\ncolor('black');port_label('input',3,'rst');\ncolor('blac" "k');port_label('input',4,'en');\n\ncolor('black');disp('{\\fontsize{14}\\bf++}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Delay1" SID "2510" Ports [1, 1] Position [550, 522, 585, 558] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,36,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 36 36 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 36 36 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[23.55 23.55 28." "55 23.55 28.55 28.55 28.55 23.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[18.55 18.55 23.55 23.55 18." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[13.55 13.55 18.55 18.55 13.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[8.55 8.55 13.55 8.55 13.55 13.55 8.55 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-1}'" ",'texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay2" SID "2511" Ports [1, 1] Position [725, 787, 760, 823] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,36,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 36 36 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 36 36 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[23.55 23.55 28." "55 23.55 28.55 28.55 28.55 23.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[18.55 18.55 23.55 23.55 18." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[13.55 13.55 18.55 18.55 13.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[8.55 8.55 13.55 8.55 13.55 13.55 8.55 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-1}'" ",'texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay3" SID "2512" Ports [1, 1] Position [550, 482, 585, 518] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,36,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 36 36 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 36 36 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[23.55 23.55 28." "55 23.55 28.55 28.55 28.55 23.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[18.55 18.55 23.55 23.55 18." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[13.55 13.55 18.55 18.55 13.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[8.55 8.55 13.55 8.55 13.55 13.55 8.55 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-1}'" ",'texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay4" SID "2513" Ports [1, 1] Position [780, 787, 815, 823] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,36,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 36 36 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 36 36 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[23.55 23.55 28." "55 23.55 28.55 28.55 28.55 23.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[18.55 18.55 23.55 23.55 18." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[13.55 13.55 18.55 18.55 13.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[8.55 8.55 13.55 8.55 13.55 13.55 8.55 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-1}'" ",'texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay5" SID "2514" Ports [1, 1] Position [790, 307, 825, 343] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "3" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,36,1,1,white,blue,0,83e6bb61,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 36 36 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 36 36 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[23.55 23.55 28." "55 23.55 28.55 28.55 28.55 23.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[18.55 18.55 23.55 23.55 18." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[13.55 13.55 18.55 18.55 13.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[8.55 8.55 13.55 8.55 13.55 13.55 8.55 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-3}'" ",'texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Scope Name "Descrm Ind" SID "2515" Ports [8] Position [1275, 739, 1310, 856] ZOrder -3 Floating off Location [693, 542, 2265, 1464] Open off NumInputPorts "8" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" } TimeRange "8000" YMin "70~102~50~-1~-5~-5~-5~-5" YMax "210~105~135~1~5~5~5~5" SaveName "ScopeData19" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType Reference Name "Gateway Out1" SID "2516" Ports [1, 1] Position [1185, 769, 1220, 781] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "Gateway Out2" SID "2517" Ports [1, 1] Position [1185, 784, 1220, 796] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "Gateway Out3" SID "2518" Ports [1, 1] Position [1185, 799, 1220, 811] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "Gateway Out4" SID "2519" Ports [1, 1] Position [1185, 814, 1220, 826] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "Gateway Out5" SID "2520" Ports [1, 1] Position [1185, 739, 1220, 751] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "Gateway Out6" SID "2521" Ports [1, 1] Position [1185, 754, 1220, 766] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "Gateway Out7" SID "2522" Ports [1, 1] Position [1185, 829, 1220, 841] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "Gateway Out8" SID "2523" Ports [1, 1] Position [1185, 844, 1220, 856] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "Inverter" SID "2524" Ports [1, 1] Position [1165, 602, 1190, 618] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "25,16,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 16 16 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 16 16 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[10.22 10.22 12" ".22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[8.22 8.22 10.22 10.22 8.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType SubSystem Name "LFSR Init" SID "2525" Ports [1, 1] Position [650, 403, 710, 437] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "LFSR Init" Location [829, 542, 1049, 624] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "B" SID "2526" Position [230, 313, 260, 327] IconDisplay "Port number" } Block { BlockType Reference Name "7LSB" SID "2527" Ports [1, 1] Position [315, 245, 375, 275] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "7" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "60,30,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 30 30 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\npatch([21.1 26.88 30.88 34.88 38.88 30.88 25.1 21.1 ],[19.44 19" ".44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([25.1 30.88 26.88 21.1 25.1 ],[15.44 15.44 19.44 19." "44 15.44 ],[0.931 0.946 0.973 ]);\npatch([21.1 26.88 30.88 25.1 21.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]" ");\npatch([25.1 38.88 34.88 30.88 26.88 21.1 25.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 " "]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_l" "abel('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "7MSB" SID "2528" Ports [1, 1] Position [315, 305, 375, 335] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "7" boolean_output off mode "Upper Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "60,30,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 30 30 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\npatch([21.1 26.88 30.88 34.88 38.88 30.88 25.1 21.1 ],[19.44 19" ".44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([25.1 30.88 26.88 21.1 25.1 ],[15.44 15.44 19.44 19." "44 15.44 ],[0.931 0.946 0.973 ]);\npatch([21.1 26.88 30.88 25.1 21.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]" ");\npatch([25.1 38.88 34.88 30.88 26.88 21.1 25.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 " "]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_l" "abel('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Concat" SID "2529" Ports [7, 1] Position [530, 304, 560, 546] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point " "at zero." num_inputs "7" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "30,242,7,1,white,blue,0,5db75f69,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 242 242 0 ],[0.77 0." "82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 242 242 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[125.44" " 125.44 129.44 125.44 129.44 129.44 129.44 125.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[121.44 121.4" "4 125.44 125.44 121.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[117.44 117.44 121.44 121.44 " "117.44 ],[1 1 1 ]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[113.44 113.44 117.44 113.44 117.44 117.44 1" "13.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text'" ");\ncolor('black');port_label('input',1,'hi');\n\n\n\n\n\ncolor('black');port_label('input',7,'lo');\n\ncolor('b" "lack');disp('\\fontsize{20}\\}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b0" SID "2530" Ports [1, 1] Position [435, 311, 475, 329] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b1" SID "2531" Ports [1, 1] Position [435, 346, 475, 364] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "1" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b2" SID "2532" Ports [1, 1] Position [435, 381, 475, 399] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "2" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b3" SID "2533" Ports [1, 1] Position [435, 416, 475, 434] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "3" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b4" SID "2534" Ports [1, 1] Position [435, 451, 475, 469] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "4" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b5" SID "2535" Ports [1, 1] Position [435, 486, 475, 504] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "5" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b6" SID "2536" Ports [1, 1] Position [435, 521, 475, 539] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "6" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "I" SID "2537" Position [590, 253, 620, 267] IconDisplay "Port number" } Line { SrcBlock "Concat" SrcPort 1 Points [70, 0] } Line { SrcBlock "b6" SrcPort 1 DstBlock "Concat" DstPort 7 } Line { SrcBlock "b5" SrcPort 1 DstBlock "Concat" DstPort 6 } Line { SrcBlock "b4" SrcPort 1 DstBlock "Concat" DstPort 5 } Line { SrcBlock "b3" SrcPort 1 DstBlock "Concat" DstPort 4 } Line { SrcBlock "b2" SrcPort 1 DstBlock "Concat" DstPort 3 } Line { SrcBlock "b1" SrcPort 1 DstBlock "Concat" DstPort 2 } Line { SrcBlock "b0" SrcPort 1 DstBlock "Concat" DstPort 1 } Line { SrcBlock "7MSB" SrcPort 1 Points [25, 0] Branch { Points [0, 35] Branch { Points [0, 35] Branch { Points [0, 35] Branch { Points [0, 35] Branch { Points [0, 35] Branch { Points [0, 35] DstBlock "b6" DstPort 1 } Branch { DstBlock "b5" DstPort 1 } } Branch { DstBlock "b4" DstPort 1 } } Branch { DstBlock "b3" DstPort 1 } } Branch { DstBlock "b2" DstPort 1 } } Branch { DstBlock "b1" DstPort 1 } } Branch { DstBlock "b0" DstPort 1 } } Line { SrcBlock "B" SrcPort 1 Points [20, 0] Branch { DstBlock "7MSB" DstPort 1 } Branch { Points [0, -60] DstBlock "7LSB" DstPort 1 } } Line { SrcBlock "7LSB" SrcPort 1 DstBlock "I" DstPort 1 } } } Block { BlockType Reference Name "LFSR Init\nState LUT" SID "2538" Ports [1, 1] Position [765, 392, 825, 448] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/ROM" SourceType "Xilinx Single Port Read-Only Memory Block" depth "length(scr_ind_rev)" initVector "scr_ind_rev" distributed_mem "Distributed memory" rst off init_reg "0" en off latency "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "7" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" dbl_ovrd off optimize "Area" use_rpm on xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "sprom" sg_icon_stat "60,56,1,1,white,blue,0,eff69a7e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44" ".88 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88" " ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch(" "[20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfpr" "intf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'" ",1,'addr');\n\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "LFSR by\nByte" SID "2539" Ports [1, 1] Position [1415, 422, 1475, 478] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/ROM" SourceType "Xilinx Single Port Read-Only Memory Block" depth "length(bit_scrambler_lfsr_bytes)" initVector "bit_scrambler_lfsr_bytes" distributed_mem "Block RAM" rst off init_reg "0" en off latency "1" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "8" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" dbl_ovrd off optimize "Area" use_rpm on xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "sprom" sg_icon_stat "60,56,1,1,white,blue,0,bbc23d60,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44" ".88 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88" " ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch(" "[20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfpr" "intf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'" ",1,'addr');\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical" SID "2540" Ports [2, 1] Position [410, 405, 465, 465] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "55,60,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 60 60 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ],[37.77 37" ".77 44.77 37.77 44.77 44.77 44.77 37.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[30.77 30.77 37.77" " 37.77 30.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[23.77 23.77 30.77 30.77 23.77 ]," "[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[16.77 16.77 23.77 16.77 23.77 23.77 16.77 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncol" "or('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "2541" Ports [2, 1] Position [1190, 459, 1220, 481] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "30,22,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 22 22 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[14.33 14.3" "3 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[11.33 11.33 14.33 14" ".33 11.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 1 1 ]" ");\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 0.973 " "]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp" "('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "2542" Ports [3, 1] Position [1190, 549, 1220, 571] BlockMirror on NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "30,22,3,1,white,blue,0,98d76266,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 22 22 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[14.33 14.3" "3 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[11.33 11.33 14.33 14" ".33 11.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 1 1 ]" ");\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 0.973 " "]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\ncolor('black');di" "sp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux" SID "2543" Ports [3, 1] Position [1565, 363, 1610, 467] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "45,104,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 14.8571 89.1429 104 0 ],[0" ".77 0.82 0.91 ]);\nplot([0 45 45 0 0 ],[0 14.8571 89.1429 104 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14." "65 8.65 ],[58.66 58.66 64.66 58.66 64.66 64.66 64.66 58.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[52" ".66 52.66 58.66 58.66 52.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[46.66 46.66 52.66 52.6" "6 46.66 ],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[40.66 40.66 46.66 40.66 46.66 46.66 40.66" " ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncol" "or('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('i" "nput',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational" SID "2544" Ports [2, 1] Position [220, 422, 275, 478] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "55,56,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 55 55 0 0 ],[0 0 56 56 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ],[35.77 35" ".77 42.77 35.77 42.77 42.77 42.77 35.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[28.77 28.77 35.77" " 35.77 28.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[21.77 21.77 28.77 28.77 21.77 ]," "[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[14.77 14.77 21.77 14.77 21.77 21.77 14.77 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1," "'\\bfa = b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational1" SID "2545" Ports [2, 1] Position [1255, 527, 1310, 583] BlockMirror on NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "55,56,2,1,white,blue,0,2a81ff49,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 55 55 0 0 ],[0 0 56 56 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ],[35.77 35" ".77 42.77 35.77 42.77 42.77 42.77 35.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[28.77 28.77 35.77" " 35.77 28.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[21.77 21.77 28.77 28.77 21.77 ]," "[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[14.77 14.77 21.77 14.77 21.77 21.77 14.77 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1," "'\\bfa = b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational2" SID "2546" Ports [2, 1] Position [220, 297, 275, 353] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a>=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "55,56,2,1,white,blue,0,6218dc92,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 55 55 0 0 ],[0 0 56 56 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ],[35.77 35" ".77 42.77 35.77 42.77 42.77 42.77 35.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[28.77 28.77 35.77" " 35.77 28.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[21.77 21.77 28.77 28.77 21.77 ]," "[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[14.77 14.77 21.77 14.77 21.77 21.77 14.77 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1," "'\\bfa \\geq b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "SERVICE" SID "2547" Ports [2, 1] Position [535, 392, 595, 448] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "60,56,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44" ".88 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88" " ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch(" "[20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfpr" "intf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'" ",1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');d" "isp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Descram Val" SID "2548" Position [1725, 408, 1755, 422] IconDisplay "Port number" } Line { SrcBlock "Logical2" SrcPort 1 Points [-20, 0; 0, -105] DstBlock "Counter" DstPort 3 } Line { SrcBlock "Relational1" SrcPort 1 DstBlock "Logical2" DstPort 1 } Line { SrcBlock "Delay4" SrcPort 1 DstBlock "Gateway Out3" DstPort 1 } Line { SrcBlock "Delay2" SrcPort 1 DstBlock "Delay4" DstPort 1 } Line { SrcBlock "Concat1" SrcPort 1 Points [10, 0] Branch { Points [0, 335] DstBlock "Gateway Out1" DstPort 1 } Branch { DstBlock "Counter" DstPort 2 } } Line { SrcBlock "Gateway Out4" SrcPort 1 DstBlock "Descrm Ind" DstPort 6 } Line { SrcBlock "4MSB1" SrcPort 1 DstBlock "Concat1" DstPort 2 } Line { SrcBlock "3LSB1" SrcPort 1 DstBlock "Concat1" DstPort 1 } Line { SrcBlock "Gateway Out3" SrcPort 1 DstBlock "Descrm Ind" DstPort 5 } Line { SrcBlock "Gateway Out2" SrcPort 1 DstBlock "Descrm Ind" DstPort 4 } Line { SrcBlock "Gateway Out1" SrcPort 1 DstBlock "Descrm Ind" DstPort 3 } Line { SrcBlock "Gateway Out6" SrcPort 1 DstBlock "Descrm Ind" DstPort 2 } Line { SrcBlock "Gateway Out5" SrcPort 1 DstBlock "Descrm Ind" DstPort 1 } Line { SrcBlock "Counter" SrcPort 1 Points [50, 0] Branch { DstBlock "LFSR by\nByte" DstPort 1 } Branch { Points [0, 90] Branch { Points [0, 90; -360, 0; 0, 160] DstBlock "Gateway Out2" DstPort 1 } Branch { DstBlock "Relational1" DstPort 1 } } } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Relational1" DstPort 2 } Line { SrcBlock "Delay1" SrcPort 1 Points [90, 0] Branch { Points [465, 0; 0, 0] Branch { Points [0, -65] DstBlock "Logical1" DstPort 2 } Branch { Points [0, 55; 90, 0] DstBlock "Logical2" DstPort 3 } } Branch { Points [0, 265] DstBlock "Delay2" DstPort 1 } } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Counter" DstPort 4 } Line { SrcBlock "Delay3" SrcPort 1 Points [540, 0] Branch { Points [0, -35] Branch { DstBlock "Logical1" DstPort 1 } Branch { Points [0, -40] DstBlock "Counter" DstPort 1 } } Branch { Points [0, 110] DstBlock "Inverter" DstPort 1 } } Line { SrcBlock "LFSR Init\nState LUT" SrcPort 1 Points [75, 0] Branch { Points [10, 0] Branch { Points [0, 40] DstBlock "4MSB1" DstPort 1 } Branch { DstBlock "3LSB1" DstPort 1 } } Branch { Points [0, 340] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "LFSR by\nByte" SrcPort 1 Points [35, 0] Branch { Points [0, 440; -475, 0; 0, -70] DstBlock "Gateway Out4" DstPort 1 } Branch { DstBlock "Mux" DstPort 3 } } Line { SrcBlock "data_ind" SrcPort 1 Points [25, 0] Branch { DstBlock "Relational" DstPort 1 } Branch { Points [0, -125] DstBlock "Relational2" DstPort 1 } Branch { Points [0, 415] DstBlock "Gateway Out8" DstPort 1 } } Line { SrcBlock "data_valid" SrcPort 1 Points [25, 0] Branch { Points [0, 120] DstBlock "Delay1" DstPort 1 } Branch { DstBlock "Logical" DstPort 1 } } Line { SrcBlock "data_byte" SrcPort 1 Points [100, 0; 0, 30] DstBlock "SERVICE" DstPort 1 } Line { SrcBlock "LFSR Init" SrcPort 1 Points [20, 0] Branch { Points [0, 325] DstBlock "Gateway Out5" DstPort 1 } Branch { DstBlock "LFSR Init\nState LUT" DstPort 1 } } Line { SrcBlock "SERVICE" SrcPort 1 DstBlock "LFSR Init" DstPort 1 } Line { SrcBlock "Logical" SrcPort 1 Points [30, 0] Branch { Points [0, 65] DstBlock "Delay3" DstPort 1 } Branch { DstBlock "SERVICE" DstPort 2 } } Line { SrcBlock "Relational" SrcPort 1 DstBlock "Logical" DstPort 2 } Line { SrcBlock "Svc byte ind" SrcPort 1 Points [40, 0] Branch { DstBlock "Relational" DstPort 2 } Branch { Points [0, -125] DstBlock "Relational2" DstPort 2 } } Line { SrcBlock "Mux" SrcPort 1 DstBlock "Descram Val" DstPort 1 } Line { SrcBlock "Relational2" SrcPort 1 DstBlock "Delay5" DstPort 1 } Line { SrcBlock "Constant2" SrcPort 1 DstBlock "Mux" DstPort 2 } Line { SrcBlock "Gateway Out7" SrcPort 1 DstBlock "Descrm Ind" DstPort 7 } Line { SrcBlock "Gateway Out8" SrcPort 1 DstBlock "Descrm Ind" DstPort 8 } Line { SrcBlock "Delay5" SrcPort 1 Points [650, 0] Branch { Points [45, 0; 0, 55] DstBlock "Mux" DstPort 1 } Branch { Points [0, 560; -425, 0; 0, -50] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "Inverter" SrcPort 1 Points [50, 0; 0, -50] DstBlock "Logical2" DstPort 2 } Annotation { Name "SERVICE field is used to lookup initial state\nof Tx scrambler. This state becomes the starting\nindex t" "o the bytewise descrambler logic. This\nblock is a parallel version of the bitwise scrambling\nspecified in the 80" "2.11 spec." Position [439, 230] } Annotation { Name "Don't keep the reset signal asserted if a packet\nhappens to end on byte 126 when the next\nSERVICE fiel" "d arrives. Without this not/and\nevery 126th packet will be descrambled wrong\n(when all pkts have the same length" ")" Position [1238, 675] } } } Block { BlockType From Name "From" SID "2549" Position [230, 418, 395, 442] ZOrder -9 ShowName off GotoTag "RX_PHY_MODE_11N_AC" TagVisibility "global" } Block { BlockType Reference Name "Gateway Out1" SID "2550" Ports [1, 1] Position [1400, 239, 1435, 251] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Byte Index" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "2551" Ports [1, 1] Position [1145, 679, 1180, 691] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out3" SID "2552" Ports [1, 1] Position [1145, 729, 1180, 741] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out4" SID "2553" Ports [1, 1] Position [1400, 284, 1435, 296] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Registered Output Byte" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "2554" Ports [1, 1] Position [1400, 209, 1435, 221] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Byte Valid" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "2555" Ports [1, 1] Position [1400, 224, 1435, 236] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Byte Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "2556" Ports [1, 1] Position [1145, 784, 1180, 796] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out8" SID "2557" Ports [1, 1] Position [1400, 254, 1435, 266] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Descram Byte" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out9" SID "2558" Ports [1, 1] Position [1400, 269, 1435, 281] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Input Byte" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Logical1" SID "2559" Ports [2, 1] Position [865, 405, 920, 465] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "XOR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "55,60,2,1,white,blue,0,dc21e094,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 60 60 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ]" ",[37.77 37.77 44.77 37.77 44.77 44.77 44.77 37.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[30.7" "7 30.77 37.77 37.77 30.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[23.77 23.77 30.7" "7 30.77 23.77 ],[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[16.77 16.77 23.77 16.77 23.7" "7 23.77 16.77 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin i" "con text');\n\n\n\ncolor('black');disp('xor');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux" SID "2560" Ports [3, 1] Position [440, 412, 475, 528] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "35,116,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 16.5714 99.4286 116" " 0 ],[0.77 0.82 0.91 ]);\nplot([0 35 35 0 0 ],[0 16.5714 99.4286 116 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18" ".1 10.875 5.875 ],[63.55 63.55 68.55 63.55 68.55 68.55 68.55 63.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 " "10.875 ],[58.55 58.55 63.55 63.55 58.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[53.55 " "53.55 58.55 58.55 53.55 ],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[48.55 48.55 53.55 48.55" " 53.55 53.55 48.55 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: be" "gin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolo" "r('black');port_label('input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: e" "nd icon text');" } Block { BlockType ToWorkspace Name "To Workspace" SID "2561" Ports [1] Position [1220, 670, 1280, 700] ZOrder -7 VariableName "byteout" MaxDataPoints "inf" SampleTime "-1" SaveFormat "Array" } Block { BlockType ToWorkspace Name "To Workspace1" SID "2562" Ports [1] Position [1220, 720, 1280, 750] ZOrder -7 VariableName "byteout_valid" MaxDataPoints "inf" SampleTime "-1" SaveFormat "Array" } Block { BlockType ToWorkspace Name "To Workspace2" SID "2563" Ports [1] Position [1220, 775, 1280, 805] ZOrder -7 VariableName "byteout_index" MaxDataPoints "inf" SampleTime "-1" SaveFormat "Array" } Block { BlockType Outport Name " Byte" SID "2564" Position [1315, 428, 1345, 442] IconDisplay "Port number" } Block { BlockType Outport Name " Byte Valid" SID "2565" Position [1110, 338, 1140, 352] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name " Byte Index" SID "2566" Position [1315, 518, 1345, 532] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name " Last Byte" SID "2567" Position [1315, 578, 1345, 592] Port "4" IconDisplay "Port number" } Line { Name "Registered Output Byte" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 DstBlock "Descram" DstPort 6 } Line { SrcBlock "DOUT" SrcPort 1 Points [65, 0; 0, -105] DstBlock "Gateway Out4" DstPort 1 } Line { SrcBlock "Delay" SrcPort 1 Points [50, 0] Branch { Points [0, 135] DstBlock "Logical1" DstPort 1 } Branch { Points [430, 0; 0, -10] DstBlock "Gateway Out9" DstPort 1 } } Line { Name "Byte Index" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 DstBlock "Descram" DstPort 3 } Line { Name "Byte Out" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 DstBlock "Descram" DstPort 2 } Line { Name "Byte Valid" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 DstBlock "Descram" DstPort 1 } Line { SrcBlock "Delay4" SrcPort 1 Points [305, 0] Branch { Points [120, 0] Branch { Points [0, -280] DstBlock "Gateway Out1" DstPort 1 } Branch { DstBlock " Byte Index" DstPort 1 } } Branch { Points [0, 265] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "Delay3" SrcPort 1 Points [315, 5] Branch { Points [0, -130] DstBlock "Gateway Out5" DstPort 1 } Branch { DstBlock " Byte Valid" DstPort 1 } Branch { Points [0, 55] Branch { DstBlock "DOUT" DstPort 2 } Branch { Points [0, 335] DstBlock "Gateway Out3" DstPort 1 } } } Line { SrcBlock "Logical1" SrcPort 1 Points [160, 0] Branch { DstBlock " Byte" DstPort 1 } Branch { Points [0, -50; 80, 0] Branch { Points [0, -155] DstBlock "Gateway Out6" DstPort 1 } Branch { DstBlock "DOUT" DstPort 1 } } Branch { Points [0, 250] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "Descram Byte Calc" SrcPort 1 Points [35, 0] Branch { DstBlock "Logical1" DstPort 2 } Branch { Points [0, -190] DstBlock "Gateway Out8" DstPort 1 } } Line { SrcBlock "Byte" SrcPort 1 Points [225, 0] Branch { Points [0, 140] DstBlock "Descram Byte Calc" DstPort 1 } Branch { DstBlock "Delay" DstPort 1 } } Line { SrcBlock "Byte Index" SrcPort 1 Points [45, 0] Branch { DstBlock "Descram Byte Calc" DstPort 3 } Branch { Points [0, 70] DstBlock "Delay4" DstPort 1 } } Line { Labels [0, 0] SrcBlock "Byte Valid" SrcPort 1 Points [70, 0] Branch { Points [0, 100] DstBlock "Descram Byte Calc" DstPort 2 } Branch { DstBlock "Delay3" DstPort 1 } } Line { SrcBlock "Last Byte" SrcPort 1 DstBlock "Delay1" DstPort 1 } Line { SrcBlock "Delay1" SrcPort 1 DstBlock " Last Byte" DstPort 1 } Line { SrcBlock "Gateway Out3" SrcPort 1 DstBlock "To Workspace1" DstPort 1 } Line { SrcBlock "Gateway Out2" SrcPort 1 DstBlock "To Workspace" DstPort 1 } Line { SrcBlock "Gateway Out7" SrcPort 1 DstBlock "To Workspace2" DstPort 1 } Line { Name "Descram Byte" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 DstBlock "Descram" DstPort 4 } Line { Name "Input Byte" Labels [0, 0] SrcBlock "Gateway Out9" SrcPort 1 DstBlock "Descram" DstPort 5 } Line { SrcBlock "From" SrcPort 1 DstBlock "Mux" DstPort 1 } Line { SrcBlock "Mux" SrcPort 1 DstBlock "Descram Byte Calc" DstPort 4 } Line { SrcBlock "Constant" SrcPort 1 DstBlock "Mux" DstPort 2 } Line { SrcBlock "Constant2" SrcPort 1 DstBlock "Mux" DstPort 3 } Annotation { Name "SERVICE field starts after\nSIGNAL fields, byte 3 for 11a/g\nbyte 9 for 11n/ac" Position [150, 497] HorizontalAlignment "left" } } } Block { BlockType From Name "From1" SID "2568" Position [105, 176, 235, 194] ShowName off CloseFcn "tagdialog Close" GotoTag "RX_GLOBAL_RESET" TagVisibility "global" } Block { BlockType Reference Name "Logical5" SID "2571" Ports [2, 1] Position [285, 179, 325, 206] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,27,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 27 27 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 27 27 0 ]);\npatch([13.325 17.66 20.66 23.66 26.66 20.66 16.325 13.325 ],[16.33 16.3" "3 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([16.325 20.66 17.66 13.325 16.325 ],[13.33 13.33 16.33 16" ".33 13.33 ],[0.931 0.946 0.973 ]);\npatch([13.325 17.66 20.66 16.325 13.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1" " 1 ]);\npatch([16.325 26.66 23.66 20.66 17.66 13.325 16.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946" " 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black'" ");disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Soft Demod" SID "11337" Ports [4, 4] Position [555, 65, 650, 130] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Soft Demod" Location [202, 96, 1918, 1148] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "I" SID "11338" Position [220, 413, 250, 427] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "Q" SID "11339" Position [220, 428, 250, 442] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "IQ valid" SID "11340" Position [285, 248, 315, 262] NamePlacement "alternate" Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "Demod cfg" SID "11341" Position [285, 308, 315, 322] NamePlacement "alternate" Port "4" IconDisplay "Port number" } Block { BlockType SubSystem Name "16QAM Soft De-Map" SID "11342" Ports [2, 4] Position [560, 529, 655, 596] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "16QAM Soft De-Map" Location [-1678, 227, -2, 1187] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "109" Block { BlockType Inport Name "I" SID "11343" Position [180, 293, 210, 307] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "Q" SID "11344" Position [170, 483, 200, 497] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Scope Name "16QAM Demap" SID "11345" Ports [8] Position [760, 68, 795, 277] ZOrder -3 Floating off Location [1188, 570, 2437, 1547] Open off NumInputPorts "8" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" } List { ListType ScopeGraphics FigureColor "[0.5 0.5 0.5]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "20000" YMin "0~-1~0~0~-1~0~-1~-1" YMax "1~1~1~1~1~1~1~1" SaveName "ScopeData26" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType Reference Name "Register1" SID "11346" Ports [1, 1] Position [420, 477, 445, 503] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 " "19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 1" "3.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\n" "patch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('inp" "ut',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Register16" SID "11347" Ports [1, 1] Position [420, 287, 445, 313] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 " "19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 1" "3.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\n" "patch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('inp" "ut',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType SubSystem Name "b1/b3 map1" SID "11348" Ports [1, 1] Position [410, 340, 450, 370] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "b1/b3 map1" Location [-1678, 227, -2, 1187] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "IQ" SID "11349" Position [375, 583, 405, 597] IconDisplay "Port number" } Block { BlockType Reference Name "Absolute" SID "11350" Ports [1, 1] Position [455, 579, 495, 601] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Absolute" SourceType "Xilinx Absolute Block Block" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "0" quantization "Truncate" overflow "Saturate" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "abs" sg_icon_stat "40,22,1,1,white,blue,0,c9bc0535,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 22 22 0 ]);\npatch([13.325 17.66 20.66 23.66 26.66 20.66 16.325 13.325 ],[14" ".33 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([16.325 20.66 17.66 13.325 16.325 ],[11.33 11." "33 14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([13.325 17.66 20.66 16.325 13.325 ],[8.33 8.33 11.33 11.33 " "8.33 ],[1 1 1 ]);\npatch([16.325 26.66 23.66 20.66 17.66 13.325 16.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor" "('black');port_label('input',1,'a');\ncolor('black');port_label('output',1,'|a|');\ncolor('black');disp('\\bf{|x" "|}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub" SID "11351" Ports [2, 1] Position [560, 546, 620, 604] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Subtraction" use_carryin off use_carryout off en off latency "1" precision "User Defined" arith_type "Signed (2's comp)" n_bits "18" bin_pt "16" quantization "Truncate" overflow "Saturate" dbl_ovrd off use_behavioral_HDL off hw_selection "Fabric" pipelined off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" sg_icon_stat "60,58,2,1,white,blue,0,8a00a986,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 58 58 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 58 58 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[37.88 37" ".88 45.88 37.88 45.88 45.88 45.88 37.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[29.88 29.88 37.88 37." "88 29.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[21.88 21.88 29.88 29.88 21.88 ],[1 1 1 ]" ");\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[13.88 13.88 21.88 13.88 21.88 21.88 13.88 ],[0.931 0.946 0." "973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port" "_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bf{a " "- b}','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\newline" "\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant" SID "11352" Ports [0, 1] Position [430, 547, 510, 573] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "2/sqrt(10)" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "12" bin_pt "12" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "80,26,0,1,white,blue,0,59d4c02b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 80 80 0 0 ],[0 0 26 26 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 80 80 0 0 ],[0 0 26 26 0 ]);\npatch([33.325 37.66 40.66 43.66 46.66 40.66 36.325 33.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([36.325 40.66 37.66 33.325 36.325 ],[13.33 13." "33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([33.325 37.66 40.66 36.325 33.325 ],[10.33 10.33 13.33 13.3" "3 10.33 ],[1 1 1 ]);\npatch([36.325 46.66 43.66 40.66 37.66 33.325 36.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7." "33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n" "color('black');port_label('output',1,'0.632568359375');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "b" SID "11353" Position [675, 568, 705, 582] IconDisplay "Port number" } Line { SrcBlock "AddSub" SrcPort 1 DstBlock "b" DstPort 1 } Line { SrcBlock "Constant" SrcPort 1 DstBlock "AddSub" DstPort 1 } Line { SrcBlock "Absolute" SrcPort 1 DstBlock "AddSub" DstPort 2 } Line { SrcBlock "IQ" SrcPort 1 DstBlock "Absolute" DstPort 1 } } } Block { BlockType SubSystem Name "b1/b3 map2" SID "11354" Ports [1, 1] Position [410, 565, 450, 595] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "b1/b3 map2" Location [202, 70, 2469, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "IQ" SID "11355" Position [375, 583, 405, 597] IconDisplay "Port number" } Block { BlockType Reference Name "Absolute" SID "11356" Ports [1, 1] Position [455, 579, 495, 601] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Absolute" SourceType "Xilinx Absolute Block Block" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "0" quantization "Truncate" overflow "Saturate" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "abs" sg_icon_stat "40,22,1,1,white,blue,0,c9bc0535,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 22 22 0 ]);\npatch([13.325 17.66 20.66 23.66 26.66 20.66 16.325 13.325 ],[14" ".33 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([16.325 20.66 17.66 13.325 16.325 ],[11.33 11." "33 14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([13.325 17.66 20.66 16.325 13.325 ],[8.33 8.33 11.33 11.33 " "8.33 ],[1 1 1 ]);\npatch([16.325 26.66 23.66 20.66 17.66 13.325 16.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor" "('black');port_label('input',1,'a');\ncolor('black');port_label('output',1,'|a|');\ncolor('black');disp('\\bf{|x" "|}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub" SID "11357" Ports [2, 1] Position [560, 546, 620, 604] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Subtraction" use_carryin off use_carryout off en off latency "1" precision "User Defined" arith_type "Signed (2's comp)" n_bits "18" bin_pt "16" quantization "Truncate" overflow "Saturate" dbl_ovrd off use_behavioral_HDL off hw_selection "Fabric" pipelined off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" sg_icon_stat "60,58,2,1,white,blue,0,8a00a986,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 58 58 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 58 58 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[37.88 37" ".88 45.88 37.88 45.88 45.88 45.88 37.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[29.88 29.88 37.88 37." "88 29.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[21.88 21.88 29.88 29.88 21.88 ],[1 1 1 ]" ");\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[13.88 13.88 21.88 13.88 21.88 21.88 13.88 ],[0.931 0.946 0." "973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port" "_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bf{a " "- b}','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\newline" "\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant" SID "11358" Ports [0, 1] Position [430, 547, 510, 573] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "2/sqrt(10)" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "12" bin_pt "12" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "80,26,0,1,white,blue,0,59d4c02b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 80 80 0 0 ],[0 0 26 26 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 80 80 0 0 ],[0 0 26 26 0 ]);\npatch([33.325 37.66 40.66 43.66 46.66 40.66 36.325 33.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([36.325 40.66 37.66 33.325 36.325 ],[13.33 13." "33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([33.325 37.66 40.66 36.325 33.325 ],[10.33 10.33 13.33 13.3" "3 10.33 ],[1 1 1 ]);\npatch([36.325 46.66 43.66 40.66 37.66 33.325 36.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7." "33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n" "color('black');port_label('output',1,'0.632568359375');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "b" SID "11359" Position [675, 568, 705, 582] IconDisplay "Port number" } Line { SrcBlock "IQ" SrcPort 1 DstBlock "Absolute" DstPort 1 } Line { SrcBlock "Absolute" SrcPort 1 DstBlock "AddSub" DstPort 2 } Line { SrcBlock "Constant" SrcPort 1 DstBlock "AddSub" DstPort 1 } Line { SrcBlock "AddSub" SrcPort 1 DstBlock "b" DstPort 1 } } } Block { BlockType Outport Name "b0" SID "11360" Position [700, 293, 730, 307] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Outport Name "b1" SID "11361" Position [700, 348, 730, 362] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "b2" SID "11362" Position [700, 483, 730, 497] NamePlacement "alternate" Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "b3" SID "11363" Position [700, 573, 730, 587] NamePlacement "alternate" Port "4" IconDisplay "Port number" } Line { SrcBlock "I" SrcPort 1 Points [80, 0] Branch { Points [0, 55] DstBlock "b1/b3 map1" DstPort 1 } Branch { DstBlock "Register16" DstPort 1 } } Line { Name "Ready" Labels [0, 0] Points [615, 210] DstBlock "16QAM Demap" DstPort 6 } Line { Name "Vout" Labels [0, 0] Points [615, 185] DstBlock "16QAM Demap" DstPort 5 } Line { Name "Mux Sel" Labels [0, 0] Points [615, 160] DstBlock "16QAM Demap" DstPort 4 } Line { Name "Q In" Labels [0, 0] Points [615, 135] DstBlock "16QAM Demap" DstPort 3 } Line { Name "I In" Labels [0, 0] Points [615, 110] DstBlock "16QAM Demap" DstPort 2 } Line { Name "valid in" Labels [0, 0] Points [615, 85] DstBlock "16QAM Demap" DstPort 1 } Line { SrcBlock "Q" SrcPort 1 Points [85, 0] Branch { Points [0, 90] DstBlock "b1/b3 map2" DstPort 1 } Branch { DstBlock "Register1" DstPort 1 } } Line { SrcBlock "b1/b3 map1" SrcPort 1 DstBlock "b1" DstPort 1 } Line { SrcBlock "b1/b3 map2" SrcPort 1 DstBlock "b3" DstPort 1 } Line { SrcBlock "Register16" SrcPort 1 DstBlock "b0" DstPort 1 } Line { SrcBlock "Register1" SrcPort 1 DstBlock "b2" DstPort 1 } Annotation { Name "16-QAM Demap:\nEach sym is [b0 b1 b2 b3]\nb0 = 1 if (I > 0)\nb1 = 1 if(abs(I) < 2/sqrt(10))\nb2 = 1 if(Q" " > 0)\nb3 = 1 if(abs(Q) < 2/sqrt(10))" Position [272, 192] HorizontalAlignment "left" } } } Block { BlockType SubSystem Name "64QAM Soft De-Map" SID "11364" Ports [2, 6] Position [560, 621, 655, 724] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "64QAM Soft De-Map" Location [442, 320, 2118, 1280] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "109" Block { BlockType Inport Name "I" SID "11365" Position [55, 293, 85, 307] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "Q" SID "11366" Position [45, 593, 75, 607] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Scope Name "64QAM Demap" SID "11367" Ports [8] Position [1110, 193, 1145, 402] ZOrder -3 Floating off Location [6, 40, 2477, 1594] Open off NumInputPorts "8" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" } List { ListType ScopeGraphics FigureColor "[0.501960784313725 0.501960784313725 0.501960784313725]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|.|none|none|none|none" } TimeRange "20000" YMin "0~-1~0~0~-1~0~-1~-1" YMax "1~1~1~1~1~1~1~1" SaveName "ScopeData26" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType BusCreator Name "Bus Creator" SID "11368" Ports [3, 1] Position [745, 464, 750, 556] ZOrder -2 ShowName off Inputs "3" DisplayOption "bar" Port { PortNumber 1 Name "I Bits" PropagatedSignals "I Bits, , " RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType BusCreator Name "Bus Creator1" SID "11369" Ports [3, 1] Position [745, 754, 750, 846] ZOrder -2 ShowName off Inputs "3" DisplayOption "bar" Port { PortNumber 1 Name "Q Bits" PropagatedSignals ", , " RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out1" SID "11370" Ports [1, 1] Position [650, 474, 685, 486] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "I Bits" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "11371" Ports [1, 1] Position [955, 254, 990, 266] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Q In" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "11372" Ports [1, 1] Position [955, 204, 990, 216] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "I In" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "11373" Ports [1, 1] Position [650, 504, 685, 516] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "Gateway Out6" SID "11374" Ports [1, 1] Position [650, 534, 685, 546] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "Gateway Out7" SID "11375" Ports [1, 1] Position [650, 764, 685, 776] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "Gateway Out8" SID "11376" Ports [1, 1] Position [650, 794, 685, 806] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "Gateway Out9" SID "11377" Ports [1, 1] Position [650, 824, 685, 836] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "Register1" SID "11378" Ports [1, 1] Position [410, 587, 435, 613] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 " "19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 1" "3.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\n" "patch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('inp" "ut',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Register16" SID "11379" Ports [1, 1] Position [410, 287, 435, 313] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 " "19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 1" "3.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\n" "patch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('inp" "ut',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType SubSystem Name "b1/b4 map" SID "11380" Ports [1, 1] Position [405, 340, 445, 370] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "b1/b4 map" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "IQ" SID "11381" Position [375, 583, 405, 597] IconDisplay "Port number" } Block { BlockType Reference Name "Absolute1" SID "11382" Ports [1, 1] Position [480, 579, 520, 601] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Absolute" SourceType "Xilinx Absolute Block Block" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "0" quantization "Truncate" overflow "Saturate" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "abs" sg_icon_stat "40,22,1,1,white,blue,0,c9bc0535,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 22 22 0 ]);\npatch([13.325 17.66 20.66 23.66 26.66 20.66 16.325 13.325 ],[14" ".33 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([16.325 20.66 17.66 13.325 16.325 ],[11.33 11." "33 14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([13.325 17.66 20.66 16.325 13.325 ],[8.33 8.33 11.33 11.33 " "8.33 ],[1 1 1 ]);\npatch([16.325 26.66 23.66 20.66 17.66 13.325 16.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor" "('black');port_label('input',1,'a');\ncolor('black');port_label('output',1,'|a|');\ncolor('black');disp('\\bf{|x" "|}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub1" SID "11383" Ports [2, 1] Position [565, 546, 625, 604] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Subtraction" use_carryin off use_carryout off en off latency "1" precision "User Defined" arith_type "Signed (2's comp)" n_bits "18" bin_pt "16" quantization "Truncate" overflow "Saturate" dbl_ovrd off use_behavioral_HDL off hw_selection "Fabric" pipelined off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" sg_icon_stat "60,58,2,1,white,blue,0,8a00a986,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 58 58 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 58 58 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[37.88 37" ".88 45.88 37.88 45.88 45.88 45.88 37.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[29.88 29.88 37.88 37." "88 29.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[21.88 21.88 29.88 29.88 21.88 ],[1 1 1 ]" ");\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[13.88 13.88 21.88 13.88 21.88 21.88 13.88 ],[0.931 0.946 0." "973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port" "_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bf{a " "- b}','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\newline" "\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant1" SID "11384" Ports [0, 1] Position [455, 547, 535, 573] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "4/sqrt(42)" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "12" bin_pt "12" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "80,26,0,1,white,blue,0,6db96243,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 80 80 0 0 ],[0 0 26 26 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 80 80 0 0 ],[0 0 26 26 0 ]);\npatch([33.325 37.66 40.66 43.66 46.66 40.66 36.325 33.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([36.325 40.66 37.66 33.325 36.325 ],[13.33 13." "33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([33.325 37.66 40.66 36.325 33.325 ],[10.33 10.33 13.33 13.3" "3 10.33 ],[1 1 1 ]);\npatch([36.325 46.66 43.66 40.66 37.66 33.325 36.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7." "33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n" "color('black');port_label('output',1,'0.6171875');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "b" SID "11385" Position [675, 568, 705, 582] IconDisplay "Port number" } Line { SrcBlock "AddSub1" SrcPort 1 DstBlock "b" DstPort 1 } Line { SrcBlock "IQ" SrcPort 1 DstBlock "Absolute1" DstPort 1 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "AddSub1" DstPort 1 } Line { SrcBlock "Absolute1" SrcPort 1 DstBlock "AddSub1" DstPort 2 } } } Block { BlockType SubSystem Name "b1/b4 map1" SID "11386" Ports [1, 1] Position [405, 625, 445, 655] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "b1/b4 map1" Location [202, 70, 2469, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "IQ" SID "11387" Position [415, 583, 445, 597] IconDisplay "Port number" } Block { BlockType Reference Name "Absolute1" SID "11388" Ports [1, 1] Position [480, 579, 520, 601] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Absolute" SourceType "Xilinx Absolute Block Block" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "0" quantization "Truncate" overflow "Saturate" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "abs" sg_icon_stat "40,22,1,1,white,blue,0,c9bc0535,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 22 22 0 ]);\npatch([13.325 17.66 20.66 23.66 26.66 20.66 16.325 13.325 ],[14" ".33 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([16.325 20.66 17.66 13.325 16.325 ],[11.33 11." "33 14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([13.325 17.66 20.66 16.325 13.325 ],[8.33 8.33 11.33 11.33 " "8.33 ],[1 1 1 ]);\npatch([16.325 26.66 23.66 20.66 17.66 13.325 16.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor" "('black');port_label('input',1,'a');\ncolor('black');port_label('output',1,'|a|');\ncolor('black');disp('\\bf{|x" "|}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub1" SID "11389" Ports [2, 1] Position [565, 546, 625, 604] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Subtraction" use_carryin off use_carryout off en off latency "1" precision "User Defined" arith_type "Signed (2's comp)" n_bits "18" bin_pt "16" quantization "Truncate" overflow "Saturate" dbl_ovrd off use_behavioral_HDL off hw_selection "Fabric" pipelined off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" sg_icon_stat "60,58,2,1,white,blue,0,8a00a986,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 58 58 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 58 58 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[37.88 37" ".88 45.88 37.88 45.88 45.88 45.88 37.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[29.88 29.88 37.88 37." "88 29.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[21.88 21.88 29.88 29.88 21.88 ],[1 1 1 ]" ");\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[13.88 13.88 21.88 13.88 21.88 21.88 13.88 ],[0.931 0.946 0." "973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port" "_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bf{a " "- b}','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\newline" "\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant1" SID "11390" Ports [0, 1] Position [455, 547, 535, 573] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "4/sqrt(42)" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "12" bin_pt "12" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "80,26,0,1,white,blue,0,6db96243,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 80 80 0 0 ],[0 0 26 26 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 80 80 0 0 ],[0 0 26 26 0 ]);\npatch([33.325 37.66 40.66 43.66 46.66 40.66 36.325 33.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([36.325 40.66 37.66 33.325 36.325 ],[13.33 13." "33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([33.325 37.66 40.66 36.325 33.325 ],[10.33 10.33 13.33 13.3" "3 10.33 ],[1 1 1 ]);\npatch([36.325 46.66 43.66 40.66 37.66 33.325 36.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7." "33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n" "color('black');port_label('output',1,'0.6171875');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "b" SID "11391" Position [675, 568, 705, 582] IconDisplay "Port number" } Line { SrcBlock "Absolute1" SrcPort 1 DstBlock "AddSub1" DstPort 2 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "AddSub1" DstPort 1 } Line { SrcBlock "IQ" SrcPort 1 DstBlock "Absolute1" DstPort 1 } Line { SrcBlock "AddSub1" SrcPort 1 DstBlock "b" DstPort 1 } } } Block { BlockType SubSystem Name "b2/b5 map" SID "11392" Ports [1, 1] Position [405, 395, 445, 425] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "b2/b5 map" Location [-1678, 227, -2, 1187] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "IQ" SID "11393" Position [200, 213, 230, 227] IconDisplay "Port number" } Block { BlockType Reference Name "Absolute" SID "11394" Ports [1, 1] Position [290, 209, 330, 231] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Absolute" SourceType "Xilinx Absolute Block Block" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "0" quantization "Truncate" overflow "Saturate" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "abs" sg_icon_stat "40,22,1,1,white,blue,0,c9bc0535,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 22 22 0 ]);\npatch([13.325 17.66 20.66 23.66 26.66 20.66 16.325 13.325 ],[14" ".33 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([16.325 20.66 17.66 13.325 16.325 ],[11.33 11." "33 14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([13.325 17.66 20.66 16.325 13.325 ],[8.33 8.33 11.33 11.33 " "8.33 ],[1 1 1 ]);\npatch([16.325 26.66 23.66 20.66 17.66 13.325 16.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor" "('black');port_label('input',1,'a');\ncolor('black');port_label('output',1,'|a|');\ncolor('black');disp('\\bf{|x" "|}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub" SID "11395" Ports [2, 1] Position [565, 346, 625, 404] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Subtraction" use_carryin off use_carryout off en off latency "1" precision "User Defined" arith_type "Signed (2's comp)" n_bits "18" bin_pt "16" quantization "Truncate" overflow "Saturate" dbl_ovrd off use_behavioral_HDL off hw_selection "Fabric" pipelined off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" sg_icon_stat "60,58,2,1,white,blue,0,8a00a986,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 58 58 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 58 58 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[37.88 37" ".88 45.88 37.88 45.88 45.88 45.88 37.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[29.88 29.88 37.88 37." "88 29.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[21.88 21.88 29.88 29.88 21.88 ],[1 1 1 ]" ");\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[13.88 13.88 21.88 13.88 21.88 21.88 13.88 ],[0.931 0.946 0." "973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port" "_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bf{a " "- b}','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\newline" "\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub1" SID "11396" Ports [2, 1] Position [565, 276, 625, 334] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Subtraction" use_carryin off use_carryout off en off latency "1" precision "User Defined" arith_type "Signed (2's comp)" n_bits "18" bin_pt "16" quantization "Truncate" overflow "Saturate" dbl_ovrd off use_behavioral_HDL off hw_selection "Fabric" pipelined off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" sg_icon_stat "60,58,2,1,white,blue,0,8a00a986,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 58 58 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 58 58 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[37.88 37" ".88 45.88 37.88 45.88 45.88 45.88 37.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[29.88 29.88 37.88 37." "88 29.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[21.88 21.88 29.88 29.88 21.88 ],[1 1 1 ]" ");\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[13.88 13.88 21.88 13.88 21.88 21.88 13.88 ],[0.931 0.946 0." "973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port" "_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bf{a " "- b}','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\newline" "\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant" SID "11397" Ports [0, 1] Position [405, 347, 485, 373] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "6/sqrt(42)" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "12" bin_pt "12" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "80,26,0,1,white,blue,0,6adc731b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 80 80 0 0 ],[0 0 26 26 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 80 80 0 0 ],[0 0 26 26 0 ]);\npatch([33.325 37.66 40.66 43.66 46.66 40.66 36.325 33.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([36.325 40.66 37.66 33.325 36.325 ],[13.33 13." "33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([33.325 37.66 40.66 36.325 33.325 ],[10.33 10.33 13.33 13.3" "3 10.33 ],[1 1 1 ]);\npatch([36.325 46.66 43.66 40.66 37.66 33.325 36.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7." "33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n" "color('black');port_label('output',1,'0.92578125');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant1" SID "11398" Ports [0, 1] Position [390, 237, 470, 263] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "4/sqrt(42)" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "12" bin_pt "12" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "80,26,0,1,white,blue,0,6db96243,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 80 80 0 0 ],[0 0 26 26 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 80 80 0 0 ],[0 0 26 26 0 ]);\npatch([33.325 37.66 40.66 43.66 46.66 40.66 36.325 33.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([36.325 40.66 37.66 33.325 36.325 ],[13.33 13." "33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([33.325 37.66 40.66 36.325 33.325 ],[10.33 10.33 13.33 13.3" "3 10.33 ],[1 1 1 ]);\npatch([36.325 46.66 43.66 40.66 37.66 33.325 36.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7." "33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n" "color('black');port_label('output',1,'0.6171875');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant2" SID "11399" Ports [0, 1] Position [405, 307, 485, 333] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "2/sqrt(42)" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "12" bin_pt "12" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "80,26,0,1,white,blue,0,3daca872,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 80 80 0 0 ],[0 0 26 26 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 80 80 0 0 ],[0 0 26 26 0 ]);\npatch([33.325 37.66 40.66 43.66 46.66 40.66 36.325 33.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([36.325 40.66 37.66 33.325 36.325 ],[13.33 13." "33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([33.325 37.66 40.66 36.325 33.325 ],[10.33 10.33 13.33 13.3" "3 10.33 ],[1 1 1 ]);\npatch([36.325 46.66 43.66 40.66 37.66 33.325 36.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7." "33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n" "color('black');port_label('output',1,'0.30859375');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux1" SID "11400" Ports [3, 1] Position [705, 198, 735, 412] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "30,214,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 30.5714 183.429 214 0 " "],[0.77 0.82 0.91 ]);\nplot([0 30 30 0 0 ],[0 30.5714 183.429 214 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.8" "8 10.1 6.1 ],[111.44 111.44 115.44 111.44 115.44 115.44 115.44 111.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 " "10.1 ],[107.44 107.44 111.44 111.44 107.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[103.44 1" "03.44 107.44 107.44 103.44 ],[1 1 1 ]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[99.44 99.44 103.44 99.4" "4 103.44 103.44 99.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: " "begin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncol" "or('black');port_label('input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: e" "nd icon text');" } Block { BlockType Reference Name "Relational" SID "11401" Ports [2, 1] Position [570, 207, 625, 263] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a>b" en off latency "1" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "55,56,2,1,white,blue,0,3049caaa,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 56 56 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 56 56 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ],[35" ".77 35.77 42.77 35.77 42.77 42.77 42.77 35.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[28.77 28." "77 35.77 35.77 28.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[21.77 21.77 28.77 28.7" "7 21.77 ],[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[14.77 14.77 21.77 14.77 21.77 21.77" " 14.77 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text" "');\ncolor('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_l" "abel('output',1,'\\bfa > b','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('bl" "ack');disp(' \\n ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "b" SID "11402" Position [780, 298, 810, 312] IconDisplay "Port number" } Line { SrcBlock "Mux1" SrcPort 1 DstBlock "b" DstPort 1 } Line { SrcBlock "Relational" SrcPort 1 DstBlock "Mux1" DstPort 1 } Line { SrcBlock "Constant" SrcPort 1 DstBlock "AddSub" DstPort 1 } Line { SrcBlock "IQ" SrcPort 1 DstBlock "Absolute" DstPort 1 } Line { SrcBlock "Absolute" SrcPort 1 Points [35, 0] Branch { DstBlock "Relational" DstPort 1 } Branch { Points [0, 70] Branch { DstBlock "AddSub1" DstPort 1 } Branch { Points [0, 100] DstBlock "AddSub" DstPort 2 } } } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Relational" DstPort 2 } Line { SrcBlock "AddSub" SrcPort 1 DstBlock "Mux1" DstPort 3 } Line { SrcBlock "Constant2" SrcPort 1 DstBlock "AddSub1" DstPort 2 } Line { SrcBlock "AddSub1" SrcPort 1 DstBlock "Mux1" DstPort 2 } } } Block { BlockType SubSystem Name "b2/b5 map1" SID "11403" Ports [1, 1] Position [405, 680, 445, 710] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "b2/b5 map1" Location [202, 70, 2469, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "IQ" SID "11404" Position [250, 213, 280, 227] IconDisplay "Port number" } Block { BlockType Reference Name "Absolute" SID "11405" Ports [1, 1] Position [320, 209, 360, 231] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Absolute" SourceType "Xilinx Absolute Block Block" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "0" quantization "Truncate" overflow "Saturate" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "abs" sg_icon_stat "40,22,1,1,white,blue,0,c9bc0535,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 22 22 0 ]);\npatch([13.325 17.66 20.66 23.66 26.66 20.66 16.325 13.325 ],[14" ".33 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([16.325 20.66 17.66 13.325 16.325 ],[11.33 11." "33 14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([13.325 17.66 20.66 16.325 13.325 ],[8.33 8.33 11.33 11.33 " "8.33 ],[1 1 1 ]);\npatch([16.325 26.66 23.66 20.66 17.66 13.325 16.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor" "('black');port_label('input',1,'a');\ncolor('black');port_label('output',1,'|a|');\ncolor('black');disp('\\bf{|x" "|}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub" SID "11406" Ports [2, 1] Position [515, 346, 575, 404] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Subtraction" use_carryin off use_carryout off en off latency "1" precision "User Defined" arith_type "Signed (2's comp)" n_bits "18" bin_pt "16" quantization "Truncate" overflow "Saturate" dbl_ovrd off use_behavioral_HDL off hw_selection "Fabric" pipelined off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" sg_icon_stat "60,58,2,1,white,blue,0,8a00a986,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 58 58 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 58 58 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[37.88 37" ".88 45.88 37.88 45.88 45.88 45.88 37.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[29.88 29.88 37.88 37." "88 29.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[21.88 21.88 29.88 29.88 21.88 ],[1 1 1 ]" ");\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[13.88 13.88 21.88 13.88 21.88 21.88 13.88 ],[0.931 0.946 0." "973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port" "_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bf{a " "- b}','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\newline" "\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub1" SID "11407" Ports [2, 1] Position [515, 276, 575, 334] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Subtraction" use_carryin off use_carryout off en off latency "1" precision "User Defined" arith_type "Signed (2's comp)" n_bits "18" bin_pt "16" quantization "Truncate" overflow "Saturate" dbl_ovrd off use_behavioral_HDL off hw_selection "Fabric" pipelined off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" sg_icon_stat "60,58,2,1,white,blue,0,8a00a986,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 58 58 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 58 58 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[37.88 37" ".88 45.88 37.88 45.88 45.88 45.88 37.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[29.88 29.88 37.88 37." "88 29.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[21.88 21.88 29.88 29.88 21.88 ],[1 1 1 ]" ");\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[13.88 13.88 21.88 13.88 21.88 21.88 13.88 ],[0.931 0.946 0." "973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port" "_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bf{a " "- b}','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\newline" "\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant" SID "11408" Ports [0, 1] Position [405, 347, 485, 373] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "6/sqrt(42)" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "12" bin_pt "12" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "80,26,0,1,white,blue,0,6adc731b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 80 80 0 0 ],[0 0 26 26 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 80 80 0 0 ],[0 0 26 26 0 ]);\npatch([33.325 37.66 40.66 43.66 46.66 40.66 36.325 33.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([36.325 40.66 37.66 33.325 36.325 ],[13.33 13." "33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([33.325 37.66 40.66 36.325 33.325 ],[10.33 10.33 13.33 13.3" "3 10.33 ],[1 1 1 ]);\npatch([36.325 46.66 43.66 40.66 37.66 33.325 36.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7." "33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n" "color('black');port_label('output',1,'0.92578125');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant1" SID "11409" Ports [0, 1] Position [390, 237, 470, 263] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "4/sqrt(42)" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "12" bin_pt "12" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "80,26,0,1,white,blue,0,6db96243,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 80 80 0 0 ],[0 0 26 26 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 80 80 0 0 ],[0 0 26 26 0 ]);\npatch([33.325 37.66 40.66 43.66 46.66 40.66 36.325 33.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([36.325 40.66 37.66 33.325 36.325 ],[13.33 13." "33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([33.325 37.66 40.66 36.325 33.325 ],[10.33 10.33 13.33 13.3" "3 10.33 ],[1 1 1 ]);\npatch([36.325 46.66 43.66 40.66 37.66 33.325 36.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7." "33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n" "color('black');port_label('output',1,'0.6171875');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant2" SID "11410" Ports [0, 1] Position [405, 307, 485, 333] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "2/sqrt(42)" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "12" bin_pt "12" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "80,26,0,1,white,blue,0,3daca872,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 80 80 0 0 ],[0 0 26 26 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 80 80 0 0 ],[0 0 26 26 0 ]);\npatch([33.325 37.66 40.66 43.66 46.66 40.66 36.325 33.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([36.325 40.66 37.66 33.325 36.325 ],[13.33 13." "33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([33.325 37.66 40.66 36.325 33.325 ],[10.33 10.33 13.33 13.3" "3 10.33 ],[1 1 1 ]);\npatch([36.325 46.66 43.66 40.66 37.66 33.325 36.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7." "33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n" "color('black');port_label('output',1,'0.30859375');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux1" SID "11411" Ports [3, 1] Position [655, 198, 685, 412] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "30,214,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 30.5714 183.429 214 0 " "],[0.77 0.82 0.91 ]);\nplot([0 30 30 0 0 ],[0 30.5714 183.429 214 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.8" "8 10.1 6.1 ],[111.44 111.44 115.44 111.44 115.44 115.44 115.44 111.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 " "10.1 ],[107.44 107.44 111.44 111.44 107.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[103.44 1" "03.44 107.44 107.44 103.44 ],[1 1 1 ]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[99.44 99.44 103.44 99.4" "4 103.44 103.44 99.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: " "begin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncol" "or('black');port_label('input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: e" "nd icon text');" } Block { BlockType Reference Name "Relational" SID "11412" Ports [2, 1] Position [520, 207, 575, 263] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a>b" en off latency "1" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "55,56,2,1,white,blue,0,3049caaa,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 56 56 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 56 56 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ],[35" ".77 35.77 42.77 35.77 42.77 42.77 42.77 35.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[28.77 28." "77 35.77 35.77 28.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[21.77 21.77 28.77 28.7" "7 21.77 ],[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[14.77 14.77 21.77 14.77 21.77 21.77" " 14.77 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text" "');\ncolor('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_l" "abel('output',1,'\\bfa > b','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('bl" "ack');disp(' \\n ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "b" SID "11413" Position [730, 298, 760, 312] IconDisplay "Port number" } Line { SrcBlock "AddSub1" SrcPort 1 DstBlock "Mux1" DstPort 2 } Line { SrcBlock "Constant2" SrcPort 1 DstBlock "AddSub1" DstPort 2 } Line { SrcBlock "AddSub" SrcPort 1 DstBlock "Mux1" DstPort 3 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Relational" DstPort 2 } Line { SrcBlock "Absolute" SrcPort 1 Points [5, 0] Branch { Points [0, 70] Branch { Points [0, 100] DstBlock "AddSub" DstPort 2 } Branch { DstBlock "AddSub1" DstPort 1 } } Branch { DstBlock "Relational" DstPort 1 } } Line { SrcBlock "IQ" SrcPort 1 DstBlock "Absolute" DstPort 1 } Line { SrcBlock "Constant" SrcPort 1 DstBlock "AddSub" DstPort 1 } Line { SrcBlock "Relational" SrcPort 1 DstBlock "Mux1" DstPort 1 } Line { SrcBlock "Mux1" SrcPort 1 DstBlock "b" DstPort 1 } } } Block { BlockType Outport Name "b0" SID "11414" Position [700, 293, 730, 307] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Outport Name "b1" SID "11415" Position [700, 348, 730, 362] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "b2" SID "11416" Position [700, 403, 730, 417] NamePlacement "alternate" Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "b3" SID "11417" Position [700, 593, 730, 607] NamePlacement "alternate" Port "4" IconDisplay "Port number" } Block { BlockType Outport Name "b4" SID "11418" Position [700, 633, 730, 647] NamePlacement "alternate" Port "5" IconDisplay "Port number" } Block { BlockType Outport Name "b5" SID "11419" Position [700, 688, 730, 702] NamePlacement "alternate" Port "6" IconDisplay "Port number" } Line { SrcBlock "b1/b4 map" SrcPort 1 Points [175, 0] Branch { DstBlock "b1" DstPort 1 } Branch { Points [0, 155] DstBlock "Gateway Out5" DstPort 1 } } Line { SrcBlock "b2/b5 map" SrcPort 1 Points [165, 0] Branch { DstBlock "b2" DstPort 1 } Branch { Points [0, 130] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "b1/b4 map1" SrcPort 1 Points [165, 0] Branch { DstBlock "b4" DstPort 1 } Branch { Points [0, 160] DstBlock "Gateway Out8" DstPort 1 } } Line { SrcBlock "b2/b5 map1" SrcPort 1 Points [155, 0] Branch { DstBlock "b5" DstPort 1 } Branch { Points [0, 135] DstBlock "Gateway Out9" DstPort 1 } } Line { Name "I Bits" Labels [-1, 0] SrcBlock "Bus Creator" SrcPort 1 Points [85, 0; 0, -275] DstBlock "64QAM Demap" DstPort 2 } Line { Name "I In" Labels [-1, 0] SrcBlock "Gateway Out3" SrcPort 1 DstBlock "64QAM Demap" DstPort 1 } Line { Name "Q In" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 DstBlock "64QAM Demap" DstPort 3 } Line { Name "Q Bits" Labels [-1, 0] SrcBlock "Bus Creator1" SrcPort 1 Points [140, 0; 0, -515] DstBlock "64QAM Demap" DstPort 4 } Line { Name "I Bits" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 DstBlock "Bus Creator" DstPort 1 } Line { SrcBlock "Gateway Out5" SrcPort 1 DstBlock "Bus Creator" DstPort 2 } Line { SrcBlock "Gateway Out6" SrcPort 1 DstBlock "Bus Creator" DstPort 3 } Line { SrcBlock "Gateway Out7" SrcPort 1 DstBlock "Bus Creator1" DstPort 1 } Line { SrcBlock "Gateway Out8" SrcPort 1 DstBlock "Bus Creator1" DstPort 2 } Line { SrcBlock "Gateway Out9" SrcPort 1 DstBlock "Bus Creator1" DstPort 3 } Line { SrcBlock "Register16" SrcPort 1 Points [195, 0] Branch { DstBlock "b0" DstPort 1 } Branch { DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "Register1" SrcPort 1 Points [185, 0] Branch { DstBlock "b3" DstPort 1 } Branch { Points [0, 170] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "I" SrcPort 1 Points [205, 0] Branch { Points [0, 55] Branch { DstBlock "b1/b4 map" DstPort 1 } Branch { Points [0, 55] DstBlock "b2/b5 map" DstPort 1 } } Branch { Labels [2, 0] Points [0, -90] DstBlock "Gateway Out3" DstPort 1 } Branch { DstBlock "Register16" DstPort 1 } } Line { SrcBlock "Q" SrcPort 1 Points [215, 0] Branch { Points [0, -35; 570, 0; 0, -305] DstBlock "Gateway Out2" DstPort 1 } Branch { Points [0, 40] Branch { Points [0, 55] DstBlock "b2/b5 map1" DstPort 1 } Branch { DstBlock "b1/b4 map1" DstPort 1 } } Branch { DstBlock "Register1" DstPort 1 } } Annotation { Name "64-QAM Demap:\nEach sym is [b0 b1 b2 b3 b4 b5]\nb0 = 1 if (I > 0)\nb1 = 1 if(abs(I) < 4/sqrt(42))\nb2 = " "1 if(2/sqrt(42) < abs(I) < 6/sqrt(42))\n\nb3 = 1 if(Q > 0)\nb4 = 1 if(abs(Q) < 4/sqrt(42))\nb5 = 1 if(2/sqrt(42) <" " abs(Q) < 6/sqrt(42))" Position [32, 87] HorizontalAlignment "left" } } } Block { BlockType SubSystem Name "BPSK Soft De-Map" SID "11420" Ports [3, 1] Position [560, 397, 655, 443] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "BPSK Soft De-Map" Location [-1678, 227, -2, 1187] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "109" Block { BlockType Inport Name "rot90" SID "11421" Position [180, 323, 210, 337] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "I" SID "11422" Position [180, 363, 210, 377] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "Q" SID "11423" Position [180, 403, 210, 417] NamePlacement "alternate" Port "3" IconDisplay "Port number" } Block { BlockType Sum Name "Add" SID "11424" Ports [2, 1] Position [1445, 342, 1475, 373] ZOrder -2 Inputs "+-" InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Scope Name "BPSK Demap" SID "11425" Ports [8] Position [1540, 168, 1575, 377] ZOrder -3 Floating off Location [6, 202, 1686, 1206] Open off NumInputPorts "8" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" } List { ListType ScopeGraphics FigureColor "[0.5 0.5 0.5]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "20000" YMin "0~-1~0~0~-1~0~-1~-1" YMax "1~1~1~1~1~1~1~1" SaveName "ScopeData26" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType Reference Name "Gateway Out1" SID "11426" Ports [1, 1] Position [1250, 204, 1285, 216] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Q In" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "11427" Ports [1, 1] Position [1250, 229, 1285, 241] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Mux sel" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "11428" Ports [1, 1] Position [1250, 179, 1285, 191] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "I In" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "11429" Ports [1, 1] Position [1250, 254, 1285, 266] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Out 9_7" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Mux4" SID "11430" Ports [3, 1] Position [300, 308, 325, 432] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "1" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "25,124,3,1,white,blue,3,a150fb03,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 17.7143 106.286 124 0 ],[0" ".77 0.82 0.91 ]);\nplot([0 25 25 0 0 ],[0 17.7143 106.286 124 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.3" "25 5.325 ],[65.33 65.33 68.33 65.33 68.33 68.33 68.33 65.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[6" "2.33 62.33 65.33 65.33 62.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[59.33 59.33 62.33 62" ".33 59.33 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[56.33 56.33 59.33 56.33 59.33 59.33 56." "33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nc" "olor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label(" "'input',3,'d1');\n\ncolor('black');disp('\\bf{ z^{-1}}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Signum Name "Sign" SID "11431" Position [1330, 341, 1355, 359] ZOrder -25 } Block { BlockType Signum Name "Sign1" SID "11432" Position [1360, 356, 1385, 374] ZOrder -25 } Block { BlockType Outport Name "b0" SID "11433" Position [585, 363, 615, 377] NamePlacement "alternate" IconDisplay "Port number" } Line { SrcBlock "rot90" SrcPort 1 Points [55, 0] Branch { DstBlock "Mux4" DstPort 1 } Branch { Labels [2, 0] Points [0, -95] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "I" SrcPort 1 Points [10, 0] Branch { DstBlock "Mux4" DstPort 2 } Branch { Labels [2, 0] Points [0, -185] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "Q" SrcPort 1 Points [25, 0] Branch { DstBlock "Mux4" DstPort 3 } Branch { Labels [2, 0] Points [0, -200] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "Mux4" SrcPort 1 Points [30, 0] Branch { DstBlock "b0" DstPort 1 } Branch { Labels [0, 0] Points [0, -110] DstBlock "Gateway Out4" DstPort 1 } } Line { Name "I In" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 DstBlock "BPSK Demap" DstPort 1 } Line { Name "Q In" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 DstBlock "BPSK Demap" DstPort 2 } Line { Name "Mux sel" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 DstBlock "BPSK Demap" DstPort 3 } Line { Name "Out 9_7" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 DstBlock "BPSK Demap" DstPort 4 } Line { Name "Out 8_7" Labels [0, 0] Points [1290, 285] DstBlock "BPSK Demap" DstPort 5 } Line { Points [1290, 310; 10, 0] Branch { DstBlock "BPSK Demap" DstPort 6 } Branch { Points [0, 40] DstBlock "Sign" DstPort 1 } } Line { Points [1290, 335; 5, 0] Branch { DstBlock "BPSK Demap" DstPort 7 } Branch { Points [0, 30] DstBlock "Sign1" DstPort 1 } } Line { SrcBlock "Add" SrcPort 1 DstBlock "BPSK Demap" DstPort 8 } Line { SrcBlock "Sign" SrcPort 1 DstBlock "Add" DstPort 1 } Line { SrcBlock "Sign1" SrcPort 1 DstBlock "Add" DstPort 2 } Annotation { Name "BPSK Demap:\nEach sym is [b0]\nb0 = 1 if (I > 0)" Position [202, 507] HorizontalAlignment "left" } Annotation { Name "QBPSK Demap:\nEach sym is [b0]\nb0 = 1 if (Q > 0)" Position [202, 557] HorizontalAlignment "left" } } } Block { BlockType Reference Name "Constant" SID "11434" Ports [0, 1] Position [1010, 440, 1030, 460] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "9" bin_pt "7" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "20,20,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 20 20 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 20 20 0 0 ],[0 0 20 20 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[12.22" " 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[10.22 10.22 12.22 " "12.22 10.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]" ");\npatch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label" "('output',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant1" SID "11435" Ports [0, 1] Position [750, 331, 765, 349] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "15,18,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 " "9.22 ],[0.931 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch(" "[4.55 11.44 9.44 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf(''" ",'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1," "'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert" SID "11436" Ports [1, 1] Position [375, 412, 410, 428] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do" " not." gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "18" bin_pt "16" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Saturate" en off latency "1" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "35,16,1,1,white,blue,0,0c6bad53,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 16 16 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 16 16 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[1" "0.22 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[8.22 8.22 " "10.22 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[6.22 6.22 8.22 8.22 6.22 ],[" "1 1 1 ]);\npatch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black" "');port_label('output',1,'cast');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp" "(' \\n ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "11437" Ports [1, 1] Position [375, 427, 410, 443] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do" " not." gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "18" bin_pt "16" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Saturate" en off latency "1" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "35,16,1,1,white,blue,0,0c6bad53,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 16 16 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 16 16 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[1" "0.22 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[8.22 8.22 " "10.22 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[6.22 6.22 8.22 8.22 6.22 ],[" "1 1 1 ]);\npatch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black" "');port_label('output',1,'cast');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp" "(' \\n ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Scope Name "Demod" SID "11438" Ports [8] Position [1645, 78, 1680, 287] ZOrder -3 Floating off Location [6, 40, 2481, 1594] Open off NumInputPorts "8" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" } List { ListType ScopeGraphics FigureColor "[0.501960784313725 0.501960784313725 0.501960784313725]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[2 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "9000" YMin "-1~-1~-2.09987~-2.09987~-1~-1~-1~6.65" YMax "1~1~-1.89989~-1.89989~1~1~1~7.35" SaveName "ScopeData46" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType From Name "From1" SID "11439" Position [915, 383, 1015, 397] ZOrder -9 ShowName off GotoTag "QPSK_b0" } Block { BlockType From Name "From10" SID "11440" Position [915, 568, 1015, 582] ZOrder -9 ShowName off GotoTag "QAM64_b2" } Block { BlockType From Name "From11" SID "11441" Position [915, 633, 1015, 647] ZOrder -9 ShowName off GotoTag "QAM16_b3" } Block { BlockType From Name "From12" SID "11442" Position [915, 728, 1015, 742] ZOrder -9 ShowName off GotoTag "QAM64_b4" } Block { BlockType From Name "From13" SID "11443" Position [915, 808, 1015, 822] ZOrder -9 ShowName off GotoTag "QAM64_b5" } Block { BlockType From Name "From16" SID "11444" Position [610, 356, 765, 374] ZOrder -9 ShowName off GotoTag "OFDM_RX_DATA_Mod_Sel" TagVisibility "global" } Block { BlockType From Name "From2" SID "11445" Position [915, 398, 1015, 412] ZOrder -9 ShowName off GotoTag "QAM16_b0" } Block { BlockType From Name "From3" SID "11446" Position [915, 413, 1015, 427] ZOrder -9 ShowName off GotoTag "QAM64_b0" } Block { BlockType From Name "From4" SID "11447" Position [915, 368, 1015, 382] ZOrder -9 ShowName off GotoTag "BPSK_b0" } Block { BlockType From Name "From5" SID "11448" Position [915, 458, 1015, 472] ZOrder -9 ShowName off GotoTag "QPSK_b1" } Block { BlockType From Name "From6" SID "11449" Position [915, 473, 1015, 487] ZOrder -9 ShowName off GotoTag "QAM16_b1" } Block { BlockType From Name "From7" SID "11450" Position [915, 488, 1015, 502] ZOrder -9 ShowName off GotoTag "QAM64_b1" } Block { BlockType From Name "From8" SID "11451" Position [915, 648, 1015, 662] ZOrder -9 ShowName off GotoTag "QAM64_b3" } Block { BlockType From Name "From9" SID "11452" Position [915, 553, 1015, 567] ZOrder -9 ShowName off GotoTag "QAM16_b2" } Block { BlockType Reference Name "Gateway Out1" SID "11453" Ports [1, 1] Position [1525, 89, 1560, 101] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "IQ Valid" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out12" SID "11454" Ports [1, 1] Position [490, 849, 525, 861] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out13" SID "11455" Ports [1, 1] Position [490, 864, 525, 876] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out2" SID "11456" Ports [1, 1] Position [1525, 139, 1560, 151] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "I" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "11457" Ports [1, 1] Position [1525, 164, 1560, 176] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Q" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "11458" Ports [1, 1] Position [1525, 114, 1560, 126] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Demog Cfg" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "11459" Ports [1, 1] Position [1525, 239, 1560, 251] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Mod Sel Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "11460" Ports [1, 1] Position [1525, 214, 1560, 226] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "LLRs Valid" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "11461" Ports [1, 1] Position [1525, 189, 1560, 201] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Mod Sel" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "11462" Ports [1, 1] Position [490, 779, 525, 791] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out9" SID "14907" Ports [1, 1] Position [1525, 264, 1560, 276] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "LLR Vec" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Goto Name "Goto" SID "11463" Position [720, 412, 825, 428] ZOrder -10 ShowName off GotoTag "BPSK_b0" TagVisibility "local" } Block { BlockType Goto Name "Goto1" SID "11464" Position [720, 467, 825, 483] ZOrder -10 ShowName off GotoTag "QPSK_b0" TagVisibility "local" } Block { BlockType Goto Name "Goto10" SID "11465" Position [720, 672, 825, 688] ZOrder -10 ShowName off GotoTag "QAM64_b3" TagVisibility "local" } Block { BlockType Goto Name "Goto11" SID "11466" Position [720, 687, 825, 703] ZOrder -10 ShowName off GotoTag "QAM64_b4" TagVisibility "local" } Block { BlockType Goto Name "Goto12" SID "11467" Position [720, 702, 825, 718] ZOrder -10 ShowName off GotoTag "QAM64_b5" TagVisibility "local" } Block { BlockType Goto Name "Goto2" SID "11468" Position [720, 487, 825, 503] ZOrder -10 ShowName off GotoTag "QPSK_b1" TagVisibility "local" } Block { BlockType Goto Name "Goto3" SID "11469" Position [720, 532, 825, 548] ZOrder -10 ShowName off GotoTag "QAM16_b0" TagVisibility "local" } Block { BlockType Goto Name "Goto4" SID "11470" Position [720, 547, 825, 563] ZOrder -10 ShowName off GotoTag "QAM16_b1" TagVisibility "local" } Block { BlockType Goto Name "Goto5" SID "11471" Position [720, 562, 825, 578] ZOrder -10 ShowName off GotoTag "QAM16_b2" TagVisibility "local" } Block { BlockType Goto Name "Goto6" SID "11472" Position [720, 577, 825, 593] ZOrder -10 ShowName off GotoTag "QAM16_b3" TagVisibility "local" } Block { BlockType Goto Name "Goto7" SID "11473" Position [720, 627, 825, 643] ZOrder -10 ShowName off GotoTag "QAM64_b0" TagVisibility "local" } Block { BlockType Goto Name "Goto8" SID "11474" Position [720, 642, 825, 658] ZOrder -10 ShowName off GotoTag "QAM64_b1" TagVisibility "local" } Block { BlockType Goto Name "Goto9" SID "11475" Position [720, 657, 825, 673] ZOrder -10 ShowName off GotoTag "QAM64_b2" TagVisibility "local" } Block { BlockType Reference Name "Inverter" SID "11476" Ports [1, 1] Position [685, 304, 710, 326] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "25,22,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 22 22 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 22 22 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[14" ".33 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[11.33 11.33 " "14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[8.33 8.33 11.33 11.33 8.33 ]" ",[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('bl" "ack');disp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux1" SID "11477" Ports [5, 1] Position [1080, 351, 1105, 429] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "4" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "25,78,5,1,white,blue,3,d6c79293,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 11.1429 66.8571 78 " "0 ],[0.77 0.82 0.91 ]);\nplot([0 25 25 0 0 ],[0 11.1429 66.8571 78 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 1" "2.66 8.325 5.325 ],[42.33 42.33 45.33 42.33 45.33 45.33 45.33 42.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325" " 8.325 ],[39.33 39.33 42.33 42.33 39.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[36.33 " "36.33 39.33 39.33 36.33 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[33.33 33.33 36.33 33.3" "3 36.33 36.33 33.33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: b" "egin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncol" "or('black');port_label('input',3,'d1');\ncolor('black');port_label('input',4,'d2');\ncolor('black');port_label(" "'input',5,'d3');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux2" SID "11478" Ports [5, 1] Position [1080, 426, 1105, 504] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "4" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "25,78,5,1,white,blue,3,d6c79293,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 11.1429 66.8571 78 " "0 ],[0.77 0.82 0.91 ]);\nplot([0 25 25 0 0 ],[0 11.1429 66.8571 78 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 1" "2.66 8.325 5.325 ],[42.33 42.33 45.33 42.33 45.33 45.33 45.33 42.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325" " 8.325 ],[39.33 39.33 42.33 42.33 39.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[36.33 " "36.33 39.33 39.33 36.33 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[33.33 33.33 36.33 33.3" "3 36.33 36.33 33.33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: b" "egin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncol" "or('black');port_label('input',3,'d1');\ncolor('black');port_label('input',4,'d2');\ncolor('black');port_label(" "'input',5,'d3');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux3" SID "11479" Ports [5, 1] Position [1080, 506, 1105, 584] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "4" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "25,78,5,1,white,blue,3,d6c79293,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 11.1429 66.8571 78 " "0 ],[0.77 0.82 0.91 ]);\nplot([0 25 25 0 0 ],[0 11.1429 66.8571 78 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 1" "2.66 8.325 5.325 ],[42.33 42.33 45.33 42.33 45.33 45.33 45.33 42.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325" " 8.325 ],[39.33 39.33 42.33 42.33 39.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[36.33 " "36.33 39.33 39.33 36.33 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[33.33 33.33 36.33 33.3" "3 36.33 36.33 33.33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: b" "egin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncol" "or('black');port_label('input',3,'d1');\ncolor('black');port_label('input',4,'d2');\ncolor('black');port_label(" "'input',5,'d3');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux4" SID "11480" Ports [5, 1] Position [1080, 586, 1105, 664] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "4" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "25,78,5,1,white,blue,3,d6c79293,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 11.1429 66.8571 78 " "0 ],[0.77 0.82 0.91 ]);\nplot([0 25 25 0 0 ],[0 11.1429 66.8571 78 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 1" "2.66 8.325 5.325 ],[42.33 42.33 45.33 42.33 45.33 45.33 45.33 42.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325" " 8.325 ],[39.33 39.33 42.33 42.33 39.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[36.33 " "36.33 39.33 39.33 36.33 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[33.33 33.33 36.33 33.3" "3 36.33 36.33 33.33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: b" "egin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncol" "or('black');port_label('input',3,'d1');\ncolor('black');port_label('input',4,'d2');\ncolor('black');port_label(" "'input',5,'d3');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux5" SID "11481" Ports [5, 1] Position [1080, 666, 1105, 744] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "4" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "25,78,5,1,white,blue,3,d6c79293,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 11.1429 66.8571 78 " "0 ],[0.77 0.82 0.91 ]);\nplot([0 25 25 0 0 ],[0 11.1429 66.8571 78 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 1" "2.66 8.325 5.325 ],[42.33 42.33 45.33 42.33 45.33 45.33 45.33 42.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325" " 8.325 ],[39.33 39.33 42.33 42.33 39.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[36.33 " "36.33 39.33 39.33 36.33 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[33.33 33.33 36.33 33.3" "3 36.33 36.33 33.33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: b" "egin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncol" "or('black');port_label('input',3,'d1');\ncolor('black');port_label('input',4,'d2');\ncolor('black');port_label(" "'input',5,'d3');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux6" SID "11482" Ports [5, 1] Position [1080, 746, 1105, 824] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "4" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "25,78,5,1,white,blue,3,d6c79293,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 11.1429 66.8571 78 " "0 ],[0.77 0.82 0.91 ]);\nplot([0 25 25 0 0 ],[0 11.1429 66.8571 78 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 1" "2.66 8.325 5.325 ],[42.33 42.33 45.33 42.33 45.33 45.33 45.33 42.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325" " 8.325 ],[39.33 39.33 42.33 42.33 39.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[36.33 " "36.33 39.33 39.33 36.33 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[33.33 33.33 36.33 33.3" "3 36.33 36.33 33.33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: b" "egin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncol" "or('black');port_label('input',3,'d1');\ncolor('black');port_label('input',4,'d2');\ncolor('black');port_label(" "'input',5,'d3');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux7" SID "11483" Ports [3, 1] Position [815, 299, 845, 381] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "1" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "30,82,3,1,white,blue,3,a150fb03,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 11.7143 70.2857 82 " "0 ],[0.77 0.82 0.91 ]);\nplot([0 30 30 0 0 ],[0 11.7143 70.2857 82 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15" ".88 10.1 6.1 ],[45.44 45.44 49.44 45.44 49.44 49.44 49.44 45.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 " "],[41.44 41.44 45.44 45.44 41.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[37.44 37.44 41.44" " 41.44 37.44 ],[1 1 1 ]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[33.44 33.44 37.44 33.44 37.44 37.44 " "33.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text" "');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');po" "rt_label('input',3,'d1');\n\ncolor('black');disp('\\bf{ z^{-1}}','texmode','on');\nfprintf('','COMMENT: end ic" "on text');" } Block { BlockType SubSystem Name "QPSK Soft De-Map" SID "11484" Ports [2, 2] Position [560, 466, 655, 504] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "QPSK Soft De-Map" Location [-1678, 227, -2, 1187] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "109" Block { BlockType Inport Name "I" SID "11485" Position [180, 293, 210, 307] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "Q" SID "11486" Position [180, 353, 210, 367] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Scope Name "QPSK Demap" SID "11487" Ports [8] Position [565, 93, 600, 302] ZOrder -3 Floating off Location [1188, 570, 2437, 1547] Open off NumInputPorts "8" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" } List { ListType ScopeGraphics FigureColor "[0.5 0.5 0.5]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "20000" YMin "0~-1~0~0~-1~0~-1~-1" YMax "1~1~1~1~1~1~1~1" SaveName "ScopeData26" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType Reference Name "Register1" SID "11488" Ports [1, 1] Position [280, 347, 305, 373] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 " "19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 1" "3.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\n" "patch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('inp" "ut',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Register16" SID "11489" Ports [1, 1] Position [280, 287, 305, 313] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 " "19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 1" "3.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\n" "patch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('inp" "ut',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Outport Name "b0" SID "11490" Position [375, 293, 405, 307] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Outport Name "b1" SID "11491" Position [375, 353, 405, 367] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Line { SrcBlock "Q" SrcPort 1 DstBlock "Register1" DstPort 1 } Line { Name "valid in" Labels [0, 0] Points [420, 110] DstBlock "QPSK Demap" DstPort 1 } Line { Name "I In" Labels [0, 0] Points [420, 135] DstBlock "QPSK Demap" DstPort 2 } Line { Name "Q In" Labels [0, 0] Points [420, 160] DstBlock "QPSK Demap" DstPort 3 } Line { Name "Mux Sel" Labels [0, 0] Points [420, 185] DstBlock "QPSK Demap" DstPort 4 } Line { Name "Vout" Labels [0, 0] Points [420, 210] DstBlock "QPSK Demap" DstPort 5 } Line { Name "Ready" Labels [0, 0] Points [420, 235] DstBlock "QPSK Demap" DstPort 6 } Line { SrcBlock "I" SrcPort 1 DstBlock "Register16" DstPort 1 } Line { SrcBlock "Register16" SrcPort 1 DstBlock "b0" DstPort 1 } Line { SrcBlock "Register1" SrcPort 1 DstBlock "b1" DstPort 1 } Annotation { Name "QPSK Demap:\nEach sym is [b0 b1]\nb0 = 1 if (I > 0)\nb1 = 1 if(Q > 0)" Position [252, 242] HorizontalAlignment "left" } } } Block { BlockType RealImagToComplex Name "Real-Imag to\nComplex" SID "11492" Ports [2, 1] Position [565, 848, 595, 877] ZOrder -21 Input "Real and imag" } Block { BlockType Reference Name "Register1" SID "11493" Ports [1, 1] Position [1150, 452, 1175, 478] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 " "16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register10" SID "11494" Ports [1, 1] Position [375, 242, 400, 268] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 " "16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register11" SID "11495" Ports [1, 1] Position [375, 302, 400, 328] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 " "16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register12" SID "11496" Ports [1, 1] Position [1510, 377, 1535, 403] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 " "16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register13" SID "11497" Ports [1, 1] Position [1510, 432, 1535, 458] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 " "16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register14" SID "11498" Ports [1, 1] Position [1510, 487, 1535, 513] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 " "16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register15" SID "11499" Ports [1, 1] Position [595, 242, 620, 268] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 " "16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register16" SID "11500" Ports [1, 1] Position [595, 267, 620, 293] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 " "16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register17" SID "11501" Ports [1, 1] Position [595, 302, 620, 328] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 " "16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "11502" Ports [1, 1] Position [1150, 532, 1175, 558] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 " "16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register3" SID "11503" Ports [1, 1] Position [1150, 612, 1175, 638] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 " "16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register4" SID "11504" Ports [1, 1] Position [1150, 377, 1175, 403] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 " "16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register5" SID "11505" Ports [1, 1] Position [1150, 692, 1175, 718] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 " "16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register6" SID "11506" Ports [1, 1] Position [1150, 772, 1175, 798] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 " "16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register7" SID "11507" Ports [1, 1] Position [1510, 322, 1535, 348] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 " "16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register8" SID "11508" Ports [1, 1] Position [1150, 242, 1175, 268] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 " "16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register9" SID "11509" Ports [1, 1] Position [1150, 267, 1175, 293] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 " "16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Scale &\nQuantize" SID "11510" Ports [9, 4] Position [1300, 304, 1420, 526] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Scale &\nQuantize" Location [202, 96, 1918, 1148] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Bits Valid" SID "11511" Position [735, 1083, 765, 1097] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "Demog Cfg" SID "11512" Position [735, 1133, 765, 1147] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "mod_sel" SID "11513" Position [515, 808, 545, 822] NamePlacement "alternate" Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "b0" SID "11514" Position [720, 673, 750, 687] NamePlacement "alternate" Port "4" IconDisplay "Port number" } Block { BlockType Inport Name "b1" SID "11515" Position [720, 593, 750, 607] NamePlacement "alternate" Port "5" IconDisplay "Port number" } Block { BlockType Inport Name "b2" SID "11516" Position [720, 388, 750, 402] NamePlacement "alternate" Port "6" IconDisplay "Port number" } Block { BlockType Inport Name "b3" SID "11517" Position [720, 308, 750, 322] NamePlacement "alternate" Port "7" IconDisplay "Port number" } Block { BlockType Inport Name "b4" SID "11518" Position [720, 233, 750, 247] NamePlacement "alternate" Port "8" IconDisplay "Port number" } Block { BlockType Inport Name "b5" SID "11519" Position [720, 153, 750, 167] NamePlacement "alternate" Port "9" IconDisplay "Port number" } Block { BlockType Reference Name "Concat" SID "11520" Ports [6, 1] Position [1580, 157, 1620, 318] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point at z" "ero." num_inputs "6" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "40,161,6,1,white,blue,0,c44eeefa,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 161 161 0 ],[0.77 0.82 0" ".91 ]);\nplot([0 40 40 0 0 ],[0 0 161 161 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[85.55 85.55" " 90.55 85.55 90.55 90.55 90.55 85.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[80.55 80.55 85.55 85.55" " 80.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[75.55 75.55 80.55 80.55 75.55 ],[1 1 1 ]);" "\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[70.55 70.55 75.55 70.55 75.55 75.55 70.55 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_labe" "l('input',1,'hi');\n\n\n\n\ncolor('black');port_label('input',6,'lo');\n\ncolor('black');disp('\\fontsize{20}\\}'," "'texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay" SID "11521" Ports [1, 1] Position [1030, 1072, 1065, 1108] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "3" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,36,1,1,white,blue,0,83e6bb61,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 36 36 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 36 36 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[23.55 23.55 28." "55 23.55 28.55 28.55 28.55 23.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[18.55 18.55 23.55 23.55 18." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[13.55 13.55 18.55 18.55 13.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[8.55 8.55 13.55 8.55 13.55 13.55 8.55 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-3}'" ",'texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay1" SID "14906" Ports [1, 1] Position [1040, 767, 1075, 803] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "3" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,36,1,1,white,blue,0,83e6bb61,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 36 36 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 36 36 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[23.55 23.55 28." "55 23.55 28.55 28.55 28.55 23.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[18.55 18.55 23.55 23.55 18." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[13.55 13.55 18.55 18.55 13.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[8.55 8.55 13.55 8.55 13.55 13.55 8.55 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-3}'" ",'texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay2" SID "11522" Ports [1, 1] Position [1030, 1122, 1065, 1158] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "3" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,36,1,1,white,blue,0,83e6bb61,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 36 36 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 36 36 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[23.55 23.55 28." "55 23.55 28.55 28.55 28.55 23.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[18.55 18.55 23.55 23.55 18." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[13.55 13.55 18.55 18.55 13.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[8.55 8.55 13.55 8.55 13.55 13.55 8.55 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-3}'" ",'texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Display Name "Display" SID "11523" Ports [1] Position [930, 963, 1015, 987] ZOrder -1 ShowName off Decimation "1" Lockdown off } Block { BlockType Display Name "Display1" SID "11524" Ports [1] Position [930, 998, 1015, 1022] ZOrder -1 ShowName off Decimation "1" Lockdown off } Block { BlockType Display Name "Display2" SID "11525" Ports [1] Position [930, 1033, 1015, 1057] ZOrder -1 ShowName off Decimation "1" Lockdown off } Block { BlockType Display Name "Display3" SID "11526" Ports [1] Position [930, 928, 1015, 952] ZOrder -1 ShowName off Decimation "1" Lockdown off } Block { BlockType From Name "From1" SID "11527" Position [235, 845, 435, 865] ZOrder -9 ShowName off GotoTag "regRx_FEC_SCALE_QPSK" TagVisibility "global" } Block { BlockType From Name "From2" SID "11528" Position [235, 865, 435, 885] ZOrder -9 ShowName off GotoTag "regRx_FEC_SCALE_16QAM" TagVisibility "global" } Block { BlockType From Name "From3" SID "11529" Position [235, 885, 435, 905] ZOrder -9 ShowName off GotoTag "regRx_FEC_SCALE_64QAM" TagVisibility "global" } Block { BlockType From Name "From4" SID "11530" Position [235, 825, 435, 845] ZOrder -9 ShowName off GotoTag "regRx_FEC_SCALE_BPSK" TagVisibility "global" } Block { BlockType Reference Name "Gateway Out1" SID "11531" Ports [1, 1] Position [1660, 829, 1695, 841] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Valid" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "11532" Ports [1, 1] Position [1660, 854, 1695, 866] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "b0" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "11533" Ports [1, 1] Position [1660, 879, 1695, 891] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "b0 Mult" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "11534" Ports [1, 1] Position [1660, 904, 1695, 916] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "b0 Quant" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "14910" Ports [1, 1] Position [1660, 929, 1695, 941] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "Gateway Out6" SID "11535" Ports [1, 1] Position [865, 969, 900, 981] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "Gateway Out7" SID "11536" Ports [1, 1] Position [865, 1004, 900, 1016] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "Gateway Out8" SID "11537" Ports [1, 1] Position [865, 1039, 900, 1051] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "Gateway Out9" SID "11538" Ports [1, 1] Position [865, 934, 900, 946] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "LSB" SID "11539" Ports [1, 1] Position [670, 457, 705, 473] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type" " is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardw" "are notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "35,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 16 16 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 16 16 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[10.22 10.22" " 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[8.22 8.22 10.22 10.22 8" ".22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatch" "([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output'" ",1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mult0" SID "11540" Ports [2, 1] Position [1030, 145, 1085, 200] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mult" SourceType "Xilinx Multiplier Block" infoedit "Hardware notes: To check for the optimum internal pipeline stages of the dedicated multiplier you mus" "t select 'Test for optimum pipelining'.

Optimization Goal: For implementation into device fabric (LUTs), th" "e Speed or Area optimization will take effect only if it's supported by IP for the particular device family. Other" "wise, the results will be identical regardless of the selection." precision "User Defined" arith_type "Signed (2's comp)" n_bits "13" bin_pt "0" quantization "Truncate" overflow "Saturate" en off latency "3" dbl_ovrd off use_behavioral_HDL off opt "Speed" use_embedded on optimum_pipeline on xl_use_area off xl_area "[0,0,0,0,0,0,0]" pipeline "on" use_rpm "on" placement_style "Triangular" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mult" sg_icon_stat "55,55,2,1,white,blue,0,7028354c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 55 55 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 55 55 0 0 ],[0 0 55 55 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ],[34.77 34" ".77 41.77 34.77 41.77 41.77 41.77 34.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[27.77 27.77 34.77" " 34.77 27.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[20.77 20.77 27.77 27.77 20.77 ]," "[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[13.77 13.77 20.77 13.77 20.77 20.77 13.77 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1," "'\\bfa \\times b','texmode','on');\ncolor('black');disp('z^{-3}\\newline ','texmode','on');\ncolor('black');disp('" " \\n ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mult1" SID "14864" Ports [2, 1] Position [1030, 225, 1085, 280] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mult" SourceType "Xilinx Multiplier Block" infoedit "Hardware notes: To check for the optimum internal pipeline stages of the dedicated multiplier you mus" "t select 'Test for optimum pipelining'.

Optimization Goal: For implementation into device fabric (LUTs), th" "e Speed or Area optimization will take effect only if it's supported by IP for the particular device family. Other" "wise, the results will be identical regardless of the selection." precision "User Defined" arith_type "Signed (2's comp)" n_bits "13" bin_pt "0" quantization "Truncate" overflow "Saturate" en off latency "3" dbl_ovrd off use_behavioral_HDL off opt "Speed" use_embedded on optimum_pipeline on xl_use_area off xl_area "[0,0,0,0,0,0,0]" pipeline "on" use_rpm "on" placement_style "Triangular" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mult" sg_icon_stat "55,55,2,1,white,blue,0,7028354c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 55 55 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 55 55 0 0 ],[0 0 55 55 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ],[34.77 34" ".77 41.77 34.77 41.77 41.77 41.77 34.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[27.77 27.77 34.77" " 34.77 27.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[20.77 20.77 27.77 27.77 20.77 ]," "[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[13.77 13.77 20.77 13.77 20.77 20.77 13.77 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1," "'\\bfa \\times b','texmode','on');\ncolor('black');disp('z^{-3}\\newline ','texmode','on');\ncolor('black');disp('" " \\n ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mult2" SID "14865" Ports [2, 1] Position [1030, 300, 1085, 355] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mult" SourceType "Xilinx Multiplier Block" infoedit "Hardware notes: To check for the optimum internal pipeline stages of the dedicated multiplier you mus" "t select 'Test for optimum pipelining'.

Optimization Goal: For implementation into device fabric (LUTs), th" "e Speed or Area optimization will take effect only if it's supported by IP for the particular device family. Other" "wise, the results will be identical regardless of the selection." precision "User Defined" arith_type "Signed (2's comp)" n_bits "13" bin_pt "0" quantization "Truncate" overflow "Saturate" en off latency "3" dbl_ovrd off use_behavioral_HDL off opt "Speed" use_embedded on optimum_pipeline on xl_use_area off xl_area "[0,0,0,0,0,0,0]" pipeline "on" use_rpm "on" placement_style "Triangular" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mult" sg_icon_stat "55,55,2,1,white,blue,0,7028354c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 55 55 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 55 55 0 0 ],[0 0 55 55 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ],[34.77 34" ".77 41.77 34.77 41.77 41.77 41.77 34.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[27.77 27.77 34.77" " 34.77 27.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[20.77 20.77 27.77 27.77 20.77 ]," "[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[13.77 13.77 20.77 13.77 20.77 20.77 13.77 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1," "'\\bfa \\times b','texmode','on');\ncolor('black');disp('z^{-3}\\newline ','texmode','on');\ncolor('black');disp('" " \\n ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mult3" SID "14866" Ports [2, 1] Position [1030, 380, 1085, 435] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mult" SourceType "Xilinx Multiplier Block" infoedit "Hardware notes: To check for the optimum internal pipeline stages of the dedicated multiplier you mus" "t select 'Test for optimum pipelining'.

Optimization Goal: For implementation into device fabric (LUTs), th" "e Speed or Area optimization will take effect only if it's supported by IP for the particular device family. Other" "wise, the results will be identical regardless of the selection." precision "User Defined" arith_type "Signed (2's comp)" n_bits "13" bin_pt "0" quantization "Truncate" overflow "Saturate" en off latency "3" dbl_ovrd off use_behavioral_HDL off opt "Speed" use_embedded on optimum_pipeline on xl_use_area off xl_area "[0,0,0,0,0,0,0]" pipeline "on" use_rpm "on" placement_style "Triangular" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mult" sg_icon_stat "55,55,2,1,white,blue,0,7028354c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 55 55 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 55 55 0 0 ],[0 0 55 55 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ],[34.77 34" ".77 41.77 34.77 41.77 41.77 41.77 34.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[27.77 27.77 34.77" " 34.77 27.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[20.77 20.77 27.77 27.77 20.77 ]," "[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[13.77 13.77 20.77 13.77 20.77 20.77 13.77 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1," "'\\bfa \\times b','texmode','on');\ncolor('black');disp('z^{-3}\\newline ','texmode','on');\ncolor('black');disp('" " \\n ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mult4" SID "14867" Ports [2, 1] Position [1030, 585, 1085, 640] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mult" SourceType "Xilinx Multiplier Block" infoedit "Hardware notes: To check for the optimum internal pipeline stages of the dedicated multiplier you mus" "t select 'Test for optimum pipelining'.

Optimization Goal: For implementation into device fabric (LUTs), th" "e Speed or Area optimization will take effect only if it's supported by IP for the particular device family. Other" "wise, the results will be identical regardless of the selection." precision "User Defined" arith_type "Signed (2's comp)" n_bits "13" bin_pt "0" quantization "Truncate" overflow "Saturate" en off latency "3" dbl_ovrd off use_behavioral_HDL off opt "Speed" use_embedded on optimum_pipeline on xl_use_area off xl_area "[0,0,0,0,0,0,0]" pipeline "on" use_rpm "on" placement_style "Triangular" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mult" sg_icon_stat "55,55,2,1,white,blue,0,7028354c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 55 55 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 55 55 0 0 ],[0 0 55 55 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ],[34.77 34" ".77 41.77 34.77 41.77 41.77 41.77 34.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[27.77 27.77 34.77" " 34.77 27.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[20.77 20.77 27.77 27.77 20.77 ]," "[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[13.77 13.77 20.77 13.77 20.77 20.77 13.77 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1," "'\\bfa \\times b','texmode','on');\ncolor('black');disp('z^{-3}\\newline ','texmode','on');\ncolor('black');disp('" " \\n ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mult5" SID "14868" Ports [2, 1] Position [1030, 665, 1085, 720] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mult" SourceType "Xilinx Multiplier Block" infoedit "Hardware notes: To check for the optimum internal pipeline stages of the dedicated multiplier you mus" "t select 'Test for optimum pipelining'.

Optimization Goal: For implementation into device fabric (LUTs), th" "e Speed or Area optimization will take effect only if it's supported by IP for the particular device family. Other" "wise, the results will be identical regardless of the selection." precision "User Defined" arith_type "Signed (2's comp)" n_bits "13" bin_pt "0" quantization "Truncate" overflow "Saturate" en off latency "3" dbl_ovrd off use_behavioral_HDL off opt "Speed" use_embedded on optimum_pipeline on xl_use_area off xl_area "[0,0,0,0,0,0,0]" pipeline "on" use_rpm "on" placement_style "Triangular" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mult" sg_icon_stat "55,55,2,1,white,blue,0,7028354c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 55 55 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 55 55 0 0 ],[0 0 55 55 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ],[34.77 34" ".77 41.77 34.77 41.77 41.77 41.77 34.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[27.77 27.77 34.77" " 34.77 27.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[20.77 20.77 27.77 27.77 20.77 ]," "[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[13.77 13.77 20.77 13.77 20.77 20.77 13.77 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1," "'\\bfa \\times b','texmode','on');\ncolor('black');disp('z^{-3}\\newline ','texmode','on');\ncolor('black');disp('" " \\n ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux" SID "11546" Ports [5, 1] Position [845, 803, 880, 907] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "4" en off latency "1" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "35,104,5,1,white,blue,3,9e2a33b8,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 14.8571 89.1429 104 0 ],[0" ".77 0.82 0.91 ]);\nplot([0 35 35 0 0 ],[0 14.8571 89.1429 104 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 " "5.875 ],[57.55 57.55 62.55 57.55 62.55 62.55 62.55 57.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[52." "55 52.55 57.55 57.55 52.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[47.55 47.55 52.55 52.5" "5 47.55 ],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[42.55 42.55 47.55 42.55 47.55 47.55 42.55 " "],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolo" "r('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('in" "put',3,'d1');\ncolor('black');port_label('input',4,'d2');\ncolor('black');port_label('input',5,'d3');\n\ncolor('bl" "ack');disp('\\bf{ z^{-1}}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux1" SID "11547" Ports [3, 1] Position [845, 448, 880, 552] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "1" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "35,104,3,1,white,blue,3,a150fb03,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 14.8571 89.1429 104 0 ],[0" ".77 0.82 0.91 ]);\nplot([0 35 35 0 0 ],[0 14.8571 89.1429 104 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 " "5.875 ],[57.55 57.55 62.55 57.55 62.55 62.55 62.55 57.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[52." "55 52.55 57.55 57.55 52.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[47.55 47.55 52.55 52.5" "5 47.55 ],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[42.55 42.55 47.55 42.55 47.55 47.55 42.55 " "],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolo" "r('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('in" "put',3,'d1');\n\ncolor('black');disp('\\bf{ z^{-1}}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Negate" SID "11548" Ports [1, 1] Position [1250, 165, 1285, 185] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Negate" SourceType "Xilinx Negate Block Block" precision "User Defined" arith_type "Signed (2's comp)" n_bits "4" bin_pt "0" quantization "Truncate" overflow "Saturate" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "negate" sg_icon_stat "35,20,1,1,white,blue,0,36bd7045,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 20 20 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[12.22 12.22" " 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[10.22 10.22 12.22 12.22" " 10.22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\n" "patch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('\\bf{x" "(-1)}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Negate1" SID "11549" Ports [1, 1] Position [1250, 245, 1285, 265] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Negate" SourceType "Xilinx Negate Block Block" precision "User Defined" arith_type "Signed (2's comp)" n_bits "4" bin_pt "0" quantization "Truncate" overflow "Saturate" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "negate" sg_icon_stat "35,20,1,1,white,blue,0,36bd7045,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 20 20 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[12.22 12.22" " 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[10.22 10.22 12.22 12.22" " 10.22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\n" "patch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('\\bf{x" "(-1)}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Negate2" SID "11550" Ports [1, 1] Position [1250, 320, 1285, 340] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Negate" SourceType "Xilinx Negate Block Block" precision "User Defined" arith_type "Signed (2's comp)" n_bits "4" bin_pt "0" quantization "Truncate" overflow "Saturate" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "negate" sg_icon_stat "35,20,1,1,white,blue,0,36bd7045,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 20 20 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[12.22 12.22" " 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[10.22 10.22 12.22 12.22" " 10.22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\n" "patch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('\\bf{x" "(-1)}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Negate3" SID "11551" Ports [1, 1] Position [1250, 400, 1285, 420] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Negate" SourceType "Xilinx Negate Block Block" precision "User Defined" arith_type "Signed (2's comp)" n_bits "4" bin_pt "0" quantization "Truncate" overflow "Saturate" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "negate" sg_icon_stat "35,20,1,1,white,blue,0,36bd7045,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 20 20 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[12.22 12.22" " 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[10.22 10.22 12.22 12.22" " 10.22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\n" "patch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('\\bf{x" "(-1)}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Negate4" SID "11552" Ports [1, 1] Position [1250, 605, 1285, 625] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Negate" SourceType "Xilinx Negate Block Block" precision "User Defined" arith_type "Signed (2's comp)" n_bits "4" bin_pt "0" quantization "Truncate" overflow "Saturate" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "negate" sg_icon_stat "35,20,1,1,white,blue,0,36bd7045,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 20 20 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[12.22 12.22" " 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[10.22 10.22 12.22 12.22" " 10.22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\n" "patch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('\\bf{x" "(-1)}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Negate5" SID "11553" Ports [1, 1] Position [1250, 685, 1285, 705] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Negate" SourceType "Xilinx Negate Block Block" precision "User Defined" arith_type "Signed (2's comp)" n_bits "4" bin_pt "0" quantization "Truncate" overflow "Saturate" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "negate" sg_icon_stat "35,20,1,1,white,blue,0,36bd7045,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 20 20 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[12.22 12.22" " 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[10.22 10.22 12.22 12.22" " 10.22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\n" "patch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('\\bf{x" "(-1)}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Quantize" SID "11554" Ports [1, 1] Position [1140, 165, 1190, 185] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Quantize" Location [104, 160, 2085, 1232] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "11555" Position [25, 63, 55, 77] IconDisplay "Port number" } Block { BlockType Reference Name "AddSub1" SID "11556" Ports [2, 1] Position [245, 250, 280, 290] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Signed (2's comp)" n_bits "4" bin_pt "0" quantization "Truncate" overflow "Saturate" dbl_ovrd off use_behavioral_HDL off hw_selection "Fabric" pipelined off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" sg_icon_stat "35,40,2,1,white,blue,0,e139daf6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 40 40 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bf{a + b}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant" SID "11557" Ports [0, 1] Position [275, 105, 300, 125] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,20,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 20 20 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 20 20 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[12.22 12" ".22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[10.22 10.22 12.22 12." "22 10.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\n" "patch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('out" "put',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant1" SID "11558" Ports [0, 1] Position [515, 160, 540, 180] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "7" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "4" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,20,0,1,white,blue,0,2a6960a5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 20 20 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 20 20 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[12.22 12" ".22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[10.22 10.22 12.22 12." "22 10.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\n" "patch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('out" "put',1,'7');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant2" SID "11559" Ports [0, 1] Position [515, 190, 540, 210] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "-8" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "4" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,20,0,1,white,blue,0,4407d5c1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 20 20 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 20 20 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[12.22 12" ".22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[10.22 10.22 12.22 12." "22 10.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\n" "patch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('out" "put',1,'-8');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant4" SID "11560" Ports [0, 1] Position [275, 185, 300, 205] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "3" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,20,0,1,white,blue,0,279a71c8,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 20 20 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 20 20 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[12.22 12" ".22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[10.22 10.22 12.22 12." "22 10.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\n" "patch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('out" "put',1,'3');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "11561" Ports [1, 1] Position [270, 30, 305, 50] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "35,20,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 20 20 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 20 20 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[12.22" " 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[10.22 10.22 12." "22 12.22 10.22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1" " 1 1 ]);\npatch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black'" ");disp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter1" SID "11562" Ports [1, 1] Position [610, 50, 645, 70] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "35,20,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 20 20 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 20 20 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[12.22" " 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[10.22 10.22 12." "22 12.22 10.22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1" " 1 1 ]);\npatch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black'" ");disp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical" SID "11563" Ports [2, 1] Position [435, 30, 470, 70] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,40,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 40 40 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('b" "lack');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "11564" Ports [2, 1] Position [520, 40, 555, 80] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,40,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 40 40 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('b" "lack');disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "11565" Ports [2, 1] Position [435, 140, 470, 180] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,40,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 40 40 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('b" "lack');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux1" SID "11566" Ports [3, 1] Position [685, 42, 730, 148] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "45,106,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 15.1429 90.8571 106 0 " "],[0.77 0.82 0.91 ]);\nplot([0 45 45 0 0 ],[0 15.1429 90.8571 106 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23." "32 14.65 8.65 ],[59.66 59.66 65.66 59.66 65.66 65.66 65.66 59.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14." "65 ],[53.66 53.66 59.66 59.66 53.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[47.66 47.66 " "53.66 53.66 47.66 ],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[41.66 41.66 47.66 41.66 47.66" " 47.66 41.66 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin ico" "n text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black" "');port_label('input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon t" "ext');" } Block { BlockType Reference Name "Mux2" SID "11567" Ports [3, 1] Position [575, 126, 615, 214] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "40,88,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 12.5714 75.4286 88 0 ]" ",[0.77 0.82 0.91 ]);\nplot([0 40 40 0 0 ],[0 12.5714 75.4286 88 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13." "875 8.875 ],[49.55 49.55 54.55 49.55 54.55 54.55 54.55 49.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 " "],[44.55 44.55 49.55 49.55 44.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[39.55 39.55 44" ".55 44.55 39.55 ],[1 1 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[34.55 34.55 39.55 34.55 39.55 39" ".55 34.55 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon t" "ext');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');" "port_label('input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text" "');" } Block { BlockType Reference Name "Reinterpret" SID "11568" Ports [1, 1] Position [160, 252, 195, 268] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can change the signal betwe" "en signed and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothi" "ng.

Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced " "to unsigned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output " "of 56 (111000 in binary)." force_arith_type on arith_type "Signed (2's comp)" force_bin_pt off bin_pt "0" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "reinterpret" sg_icon_stat "35,16,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 16 16 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');dis" "p('reinterpret');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational" SID "11569" Ports [2, 1] Position [345, 79, 385, 126] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a!=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "40,47,2,1,white,blue,0,850de6e7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 47 47 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 47 47 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[28.55 28." "55 33.55 28.55 33.55 33.55 33.55 28.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[23.55 23.55 28.55 2" "8.55 23.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[18.55 18.55 23.55 23.55 18.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[13.55 13.55 18.55 13.55 18.55 18.55 13.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bfa \\neq b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational1" SID "11570" Ports [2, 1] Position [345, 159, 385, 206] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a!=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "40,47,2,1,white,blue,0,850de6e7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 47 47 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 47 47 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[28.55 28." "55 33.55 28.55 33.55 33.55 33.55 28.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[23.55 23.55 28.55 2" "8.55 23.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[18.55 18.55 23.55 23.55 18.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[13.55 13.55 18.55 13.55 18.55 18.55 13.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bfa \\neq b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[10:7]" SID "11571" Ports [1, 1] Position [90, 249, 130, 271] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "4" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "7" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,22,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 22 22 0 ]);\npatch([13.325 17.66 20.66 23.66 26.66 20.66 16.325 13.325 ],[14" ".33 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([16.325 20.66 17.66 13.325 16.325 ],[11.33 11." "33 14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([13.325 17.66 20.66 16.325 13.325 ],[8.33 8.33 11.33 11.33 " "8.33 ],[1 1 1 ]);\npatch([16.325 26.66 23.66 20.66 17.66 13.325 16.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncol" "or('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[11:10]" SID "11572" Ports [1, 1] Position [120, 79, 160, 101] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "2" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "10" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,22,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 22 22 0 ]);\npatch([13.325 17.66 20.66 23.66 26.66 20.66 16.325 13.325 ],[14" ".33 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([16.325 20.66 17.66 13.325 16.325 ],[11.33 11." "33 14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([13.325 17.66 20.66 16.325 13.325 ],[8.33 8.33 11.33 11.33 " "8.33 ],[1 1 1 ]);\npatch([16.325 26.66 23.66 20.66 17.66 13.325 16.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncol" "or('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[12]" SID "11573" Ports [1, 1] Position [120, 29, 160, 51] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "12" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,22,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 22 22 0 ]);\npatch([13.325 17.66 20.66 23.66 26.66 20.66 16.325 13.325 ],[14" ".33 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([16.325 20.66 17.66 13.325 16.325 ],[11.33 11." "33 14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([13.325 17.66 20.66 16.325 13.325 ],[8.33 8.33 11.33 11.33 " "8.33 ],[1 1 1 ]);\npatch([16.325 26.66 23.66 20.66 17.66 13.325 16.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncol" "or('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[6]1" SID "11574" Ports [1, 1] Position [135, 284, 175, 306] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "6" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,22,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 22 22 0 ]);\npatch([13.325 17.66 20.66 23.66 26.66 20.66 16.325 13.325 ],[14" ".33 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([16.325 20.66 17.66 13.325 16.325 ],[11.33 11." "33 14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([13.325 17.66 20.66 16.325 13.325 ],[8.33 8.33 11.33 11.33 " "8.33 ],[1 1 1 ]);\npatch([16.325 26.66 23.66 20.66 17.66 13.325 16.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncol" "or('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "11575" Position [770, 88, 800, 102] IconDisplay "Port number" } Line { SrcBlock "D" SrcPort 1 Points [15, 0] Branch { Points [0, -30] DstBlock "b[12]" DstPort 1 } Branch { Points [0, 20] Branch { Points [0, 170] Branch { Points [0, 35] DstBlock "b[6]1" DstPort 1 } Branch { DstBlock "b[10:7]" DstPort 1 } } Branch { DstBlock "b[11:10]" DstPort 1 } } } Line { SrcBlock "b[12]" SrcPort 1 Points [55, 0] Branch { DstBlock "Inverter" DstPort 1 } Branch { Points [0, 110] Branch { DstBlock "Logical2" DstPort 1 } Branch { Points [0, 70; 285, 0; 0, -80] DstBlock "Mux2" DstPort 1 } } } Line { SrcBlock "Constant" SrcPort 1 DstBlock "Relational" DstPort 2 } Line { SrcBlock "b[11:10]" SrcPort 1 Points [80, 0] Branch { DstBlock "Relational" DstPort 1 } Branch { Points [0, 80] DstBlock "Relational1" DstPort 1 } } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical" DstPort 1 } Line { SrcBlock "Relational" SrcPort 1 Points [15, 0; 0, -45] DstBlock "Logical" DstPort 2 } Line { SrcBlock "Logical" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Relational1" SrcPort 1 Points [15, 0; 0, -15] DstBlock "Logical2" DstPort 2 } Line { SrcBlock "Constant4" SrcPort 1 DstBlock "Relational1" DstPort 2 } Line { SrcBlock "Logical2" SrcPort 1 Points [20, 0; 0, -90] DstBlock "Logical1" DstPort 2 } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Inverter1" DstPort 1 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Mux2" DstPort 2 } Line { SrcBlock "Constant2" SrcPort 1 DstBlock "Mux2" DstPort 3 } Line { SrcBlock "Mux2" SrcPort 1 Points [5, 0; 0, -75] DstBlock "Mux1" DstPort 2 } Line { SrcBlock "Inverter1" SrcPort 1 DstBlock "Mux1" DstPort 1 } Line { SrcBlock "b[6]1" SrcPort 1 Points [50, 0] DstBlock "AddSub1" DstPort 2 } Line { SrcBlock "AddSub1" SrcPort 1 Points [365, 0; 0, -140] DstBlock "Mux1" DstPort 3 } Line { SrcBlock "b[10:7]" SrcPort 1 DstBlock "Reinterpret" DstPort 1 } Line { SrcBlock "Reinterpret" SrcPort 1 DstBlock "AddSub1" DstPort 1 } Line { SrcBlock "Mux1" SrcPort 1 DstBlock "Q" DstPort 1 } Annotation { Position [50, 166] } } } Block { BlockType SubSystem Name "Quantize1" SID "11576" Ports [1, 1] Position [1140, 245, 1190, 265] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Quantize1" Location [104, 160, 2085, 1232] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "11577" Position [25, 63, 55, 77] IconDisplay "Port number" } Block { BlockType Reference Name "AddSub1" SID "11578" Ports [2, 1] Position [245, 250, 280, 290] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Signed (2's comp)" n_bits "4" bin_pt "0" quantization "Truncate" overflow "Saturate" dbl_ovrd off use_behavioral_HDL off hw_selection "Fabric" pipelined off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" sg_icon_stat "35,40,2,1,white,blue,0,e139daf6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 40 40 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bf{a + b}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant" SID "11579" Ports [0, 1] Position [275, 105, 300, 125] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,20,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 20 20 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 20 20 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[12.22 12" ".22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[10.22 10.22 12.22 12." "22 10.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\n" "patch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('out" "put',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant1" SID "11580" Ports [0, 1] Position [515, 160, 540, 180] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "7" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "4" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,20,0,1,white,blue,0,2a6960a5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 20 20 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 20 20 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[12.22 12" ".22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[10.22 10.22 12.22 12." "22 10.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\n" "patch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('out" "put',1,'7');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant2" SID "11581" Ports [0, 1] Position [515, 190, 540, 210] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "-8" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "4" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,20,0,1,white,blue,0,4407d5c1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 20 20 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 20 20 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[12.22 12" ".22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[10.22 10.22 12.22 12." "22 10.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\n" "patch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('out" "put',1,'-8');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant4" SID "11582" Ports [0, 1] Position [275, 185, 300, 205] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "3" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,20,0,1,white,blue,0,279a71c8,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 20 20 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 20 20 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[12.22 12" ".22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[10.22 10.22 12.22 12." "22 10.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\n" "patch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('out" "put',1,'3');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "11583" Ports [1, 1] Position [270, 30, 305, 50] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "35,20,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 20 20 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 20 20 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[12.22" " 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[10.22 10.22 12." "22 12.22 10.22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1" " 1 1 ]);\npatch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black'" ");disp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter1" SID "11584" Ports [1, 1] Position [610, 50, 645, 70] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "35,20,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 20 20 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 20 20 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[12.22" " 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[10.22 10.22 12." "22 12.22 10.22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1" " 1 1 ]);\npatch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black'" ");disp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical" SID "11585" Ports [2, 1] Position [435, 30, 470, 70] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,40,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 40 40 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('b" "lack');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "11586" Ports [2, 1] Position [520, 40, 555, 80] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,40,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 40 40 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('b" "lack');disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "11587" Ports [2, 1] Position [435, 140, 470, 180] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,40,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 40 40 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('b" "lack');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux1" SID "11588" Ports [3, 1] Position [685, 42, 730, 148] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "45,106,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 15.1429 90.8571 106 0 " "],[0.77 0.82 0.91 ]);\nplot([0 45 45 0 0 ],[0 15.1429 90.8571 106 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23." "32 14.65 8.65 ],[59.66 59.66 65.66 59.66 65.66 65.66 65.66 59.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14." "65 ],[53.66 53.66 59.66 59.66 53.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[47.66 47.66 " "53.66 53.66 47.66 ],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[41.66 41.66 47.66 41.66 47.66" " 47.66 41.66 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin ico" "n text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black" "');port_label('input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon t" "ext');" } Block { BlockType Reference Name "Mux2" SID "11589" Ports [3, 1] Position [575, 126, 615, 214] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "40,88,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 12.5714 75.4286 88 0 ]" ",[0.77 0.82 0.91 ]);\nplot([0 40 40 0 0 ],[0 12.5714 75.4286 88 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13." "875 8.875 ],[49.55 49.55 54.55 49.55 54.55 54.55 54.55 49.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 " "],[44.55 44.55 49.55 49.55 44.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[39.55 39.55 44" ".55 44.55 39.55 ],[1 1 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[34.55 34.55 39.55 34.55 39.55 39" ".55 34.55 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon t" "ext');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');" "port_label('input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text" "');" } Block { BlockType Reference Name "Reinterpret" SID "11590" Ports [1, 1] Position [160, 252, 195, 268] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can change the signal betwe" "en signed and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothi" "ng.

Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced " "to unsigned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output " "of 56 (111000 in binary)." force_arith_type on arith_type "Signed (2's comp)" force_bin_pt off bin_pt "0" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "reinterpret" sg_icon_stat "35,16,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 16 16 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');dis" "p('reinterpret');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational" SID "11591" Ports [2, 1] Position [345, 79, 385, 126] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a!=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "40,47,2,1,white,blue,0,850de6e7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 47 47 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 47 47 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[28.55 28." "55 33.55 28.55 33.55 33.55 33.55 28.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[23.55 23.55 28.55 2" "8.55 23.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[18.55 18.55 23.55 23.55 18.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[13.55 13.55 18.55 13.55 18.55 18.55 13.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bfa \\neq b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational1" SID "11592" Ports [2, 1] Position [345, 159, 385, 206] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a!=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "40,47,2,1,white,blue,0,850de6e7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 47 47 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 47 47 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[28.55 28." "55 33.55 28.55 33.55 33.55 33.55 28.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[23.55 23.55 28.55 2" "8.55 23.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[18.55 18.55 23.55 23.55 18.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[13.55 13.55 18.55 13.55 18.55 18.55 13.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bfa \\neq b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[10:7]" SID "11593" Ports [1, 1] Position [90, 249, 130, 271] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "4" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "7" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,22,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 22 22 0 ]);\npatch([13.325 17.66 20.66 23.66 26.66 20.66 16.325 13.325 ],[14" ".33 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([16.325 20.66 17.66 13.325 16.325 ],[11.33 11." "33 14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([13.325 17.66 20.66 16.325 13.325 ],[8.33 8.33 11.33 11.33 " "8.33 ],[1 1 1 ]);\npatch([16.325 26.66 23.66 20.66 17.66 13.325 16.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncol" "or('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[11:10]" SID "11594" Ports [1, 1] Position [120, 79, 160, 101] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "2" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "10" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,22,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 22 22 0 ]);\npatch([13.325 17.66 20.66 23.66 26.66 20.66 16.325 13.325 ],[14" ".33 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([16.325 20.66 17.66 13.325 16.325 ],[11.33 11." "33 14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([13.325 17.66 20.66 16.325 13.325 ],[8.33 8.33 11.33 11.33 " "8.33 ],[1 1 1 ]);\npatch([16.325 26.66 23.66 20.66 17.66 13.325 16.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncol" "or('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[12]" SID "11595" Ports [1, 1] Position [120, 29, 160, 51] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "12" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,22,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 22 22 0 ]);\npatch([13.325 17.66 20.66 23.66 26.66 20.66 16.325 13.325 ],[14" ".33 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([16.325 20.66 17.66 13.325 16.325 ],[11.33 11." "33 14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([13.325 17.66 20.66 16.325 13.325 ],[8.33 8.33 11.33 11.33 " "8.33 ],[1 1 1 ]);\npatch([16.325 26.66 23.66 20.66 17.66 13.325 16.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncol" "or('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[6]1" SID "11596" Ports [1, 1] Position [135, 284, 175, 306] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "6" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,22,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 22 22 0 ]);\npatch([13.325 17.66 20.66 23.66 26.66 20.66 16.325 13.325 ],[14" ".33 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([16.325 20.66 17.66 13.325 16.325 ],[11.33 11." "33 14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([13.325 17.66 20.66 16.325 13.325 ],[8.33 8.33 11.33 11.33 " "8.33 ],[1 1 1 ]);\npatch([16.325 26.66 23.66 20.66 17.66 13.325 16.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncol" "or('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "11597" Position [770, 88, 800, 102] IconDisplay "Port number" } Line { SrcBlock "Mux1" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "Reinterpret" SrcPort 1 DstBlock "AddSub1" DstPort 1 } Line { SrcBlock "b[10:7]" SrcPort 1 DstBlock "Reinterpret" DstPort 1 } Line { SrcBlock "AddSub1" SrcPort 1 Points [365, 0; 0, -140] DstBlock "Mux1" DstPort 3 } Line { SrcBlock "b[6]1" SrcPort 1 Points [50, 0] DstBlock "AddSub1" DstPort 2 } Line { SrcBlock "Inverter1" SrcPort 1 DstBlock "Mux1" DstPort 1 } Line { SrcBlock "Mux2" SrcPort 1 Points [5, 0; 0, -75] DstBlock "Mux1" DstPort 2 } Line { SrcBlock "Constant2" SrcPort 1 DstBlock "Mux2" DstPort 3 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Mux2" DstPort 2 } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Inverter1" DstPort 1 } Line { SrcBlock "Logical2" SrcPort 1 Points [20, 0; 0, -90] DstBlock "Logical1" DstPort 2 } Line { SrcBlock "Constant4" SrcPort 1 DstBlock "Relational1" DstPort 2 } Line { SrcBlock "Relational1" SrcPort 1 Points [15, 0; 0, -15] DstBlock "Logical2" DstPort 2 } Line { SrcBlock "Logical" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Relational" SrcPort 1 Points [15, 0; 0, -45] DstBlock "Logical" DstPort 2 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical" DstPort 1 } Line { SrcBlock "b[11:10]" SrcPort 1 Points [80, 0] Branch { Points [0, 80] DstBlock "Relational1" DstPort 1 } Branch { DstBlock "Relational" DstPort 1 } } Line { SrcBlock "Constant" SrcPort 1 DstBlock "Relational" DstPort 2 } Line { SrcBlock "b[12]" SrcPort 1 Points [55, 0] Branch { Points [0, 110] Branch { Points [0, 70; 285, 0; 0, -80] DstBlock "Mux2" DstPort 1 } Branch { DstBlock "Logical2" DstPort 1 } } Branch { DstBlock "Inverter" DstPort 1 } } Line { SrcBlock "D" SrcPort 1 Points [15, 0] Branch { Points [0, 20] Branch { DstBlock "b[11:10]" DstPort 1 } Branch { Points [0, 170] Branch { DstBlock "b[10:7]" DstPort 1 } Branch { Points [0, 35] DstBlock "b[6]1" DstPort 1 } } } Branch { Points [0, -30] DstBlock "b[12]" DstPort 1 } } Annotation { Position [50, 166] } } } Block { BlockType SubSystem Name "Quantize2" SID "11598" Ports [1, 1] Position [1140, 320, 1190, 340] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Quantize2" Location [104, 160, 2085, 1232] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "11599" Position [25, 63, 55, 77] IconDisplay "Port number" } Block { BlockType Reference Name "AddSub1" SID "11600" Ports [2, 1] Position [245, 250, 280, 290] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Signed (2's comp)" n_bits "4" bin_pt "0" quantization "Truncate" overflow "Saturate" dbl_ovrd off use_behavioral_HDL off hw_selection "Fabric" pipelined off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" sg_icon_stat "35,40,2,1,white,blue,0,e139daf6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 40 40 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bf{a + b}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant" SID "11601" Ports [0, 1] Position [275, 105, 300, 125] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,20,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 20 20 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 20 20 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[12.22 12" ".22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[10.22 10.22 12.22 12." "22 10.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\n" "patch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('out" "put',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant1" SID "11602" Ports [0, 1] Position [515, 160, 540, 180] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "7" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "4" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,20,0,1,white,blue,0,2a6960a5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 20 20 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 20 20 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[12.22 12" ".22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[10.22 10.22 12.22 12." "22 10.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\n" "patch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('out" "put',1,'7');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant2" SID "11603" Ports [0, 1] Position [515, 190, 540, 210] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "-8" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "4" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,20,0,1,white,blue,0,4407d5c1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 20 20 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 20 20 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[12.22 12" ".22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[10.22 10.22 12.22 12." "22 10.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\n" "patch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('out" "put',1,'-8');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant4" SID "11604" Ports [0, 1] Position [275, 185, 300, 205] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "3" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,20,0,1,white,blue,0,279a71c8,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 20 20 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 20 20 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[12.22 12" ".22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[10.22 10.22 12.22 12." "22 10.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\n" "patch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('out" "put',1,'3');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "11605" Ports [1, 1] Position [270, 30, 305, 50] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "35,20,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 20 20 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 20 20 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[12.22" " 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[10.22 10.22 12." "22 12.22 10.22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1" " 1 1 ]);\npatch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black'" ");disp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter1" SID "11606" Ports [1, 1] Position [610, 50, 645, 70] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "35,20,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 20 20 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 20 20 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[12.22" " 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[10.22 10.22 12." "22 12.22 10.22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1" " 1 1 ]);\npatch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black'" ");disp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical" SID "11607" Ports [2, 1] Position [435, 30, 470, 70] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,40,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 40 40 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('b" "lack');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "11608" Ports [2, 1] Position [520, 40, 555, 80] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,40,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 40 40 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('b" "lack');disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "11609" Ports [2, 1] Position [435, 140, 470, 180] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,40,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 40 40 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('b" "lack');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux1" SID "11610" Ports [3, 1] Position [685, 42, 730, 148] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "45,106,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 15.1429 90.8571 106 0 " "],[0.77 0.82 0.91 ]);\nplot([0 45 45 0 0 ],[0 15.1429 90.8571 106 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23." "32 14.65 8.65 ],[59.66 59.66 65.66 59.66 65.66 65.66 65.66 59.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14." "65 ],[53.66 53.66 59.66 59.66 53.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[47.66 47.66 " "53.66 53.66 47.66 ],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[41.66 41.66 47.66 41.66 47.66" " 47.66 41.66 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin ico" "n text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black" "');port_label('input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon t" "ext');" } Block { BlockType Reference Name "Mux2" SID "11611" Ports [3, 1] Position [575, 126, 615, 214] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "40,88,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 12.5714 75.4286 88 0 ]" ",[0.77 0.82 0.91 ]);\nplot([0 40 40 0 0 ],[0 12.5714 75.4286 88 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13." "875 8.875 ],[49.55 49.55 54.55 49.55 54.55 54.55 54.55 49.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 " "],[44.55 44.55 49.55 49.55 44.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[39.55 39.55 44" ".55 44.55 39.55 ],[1 1 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[34.55 34.55 39.55 34.55 39.55 39" ".55 34.55 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon t" "ext');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');" "port_label('input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text" "');" } Block { BlockType Reference Name "Reinterpret" SID "11612" Ports [1, 1] Position [160, 252, 195, 268] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can change the signal betwe" "en signed and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothi" "ng.

Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced " "to unsigned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output " "of 56 (111000 in binary)." force_arith_type on arith_type "Signed (2's comp)" force_bin_pt off bin_pt "0" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "reinterpret" sg_icon_stat "35,16,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 16 16 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');dis" "p('reinterpret');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational" SID "11613" Ports [2, 1] Position [345, 79, 385, 126] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a!=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "40,47,2,1,white,blue,0,850de6e7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 47 47 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 47 47 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[28.55 28." "55 33.55 28.55 33.55 33.55 33.55 28.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[23.55 23.55 28.55 2" "8.55 23.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[18.55 18.55 23.55 23.55 18.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[13.55 13.55 18.55 13.55 18.55 18.55 13.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bfa \\neq b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational1" SID "11614" Ports [2, 1] Position [345, 159, 385, 206] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a!=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "40,47,2,1,white,blue,0,850de6e7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 47 47 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 47 47 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[28.55 28." "55 33.55 28.55 33.55 33.55 33.55 28.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[23.55 23.55 28.55 2" "8.55 23.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[18.55 18.55 23.55 23.55 18.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[13.55 13.55 18.55 13.55 18.55 18.55 13.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bfa \\neq b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[10:7]" SID "11615" Ports [1, 1] Position [90, 249, 130, 271] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "4" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "7" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,22,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 22 22 0 ]);\npatch([13.325 17.66 20.66 23.66 26.66 20.66 16.325 13.325 ],[14" ".33 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([16.325 20.66 17.66 13.325 16.325 ],[11.33 11." "33 14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([13.325 17.66 20.66 16.325 13.325 ],[8.33 8.33 11.33 11.33 " "8.33 ],[1 1 1 ]);\npatch([16.325 26.66 23.66 20.66 17.66 13.325 16.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncol" "or('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[11:10]" SID "11616" Ports [1, 1] Position [120, 79, 160, 101] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "2" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "10" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,22,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 22 22 0 ]);\npatch([13.325 17.66 20.66 23.66 26.66 20.66 16.325 13.325 ],[14" ".33 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([16.325 20.66 17.66 13.325 16.325 ],[11.33 11." "33 14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([13.325 17.66 20.66 16.325 13.325 ],[8.33 8.33 11.33 11.33 " "8.33 ],[1 1 1 ]);\npatch([16.325 26.66 23.66 20.66 17.66 13.325 16.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncol" "or('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[12]" SID "11617" Ports [1, 1] Position [120, 29, 160, 51] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "12" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,22,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 22 22 0 ]);\npatch([13.325 17.66 20.66 23.66 26.66 20.66 16.325 13.325 ],[14" ".33 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([16.325 20.66 17.66 13.325 16.325 ],[11.33 11." "33 14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([13.325 17.66 20.66 16.325 13.325 ],[8.33 8.33 11.33 11.33 " "8.33 ],[1 1 1 ]);\npatch([16.325 26.66 23.66 20.66 17.66 13.325 16.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncol" "or('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[6]1" SID "11618" Ports [1, 1] Position [135, 284, 175, 306] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "6" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,22,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 22 22 0 ]);\npatch([13.325 17.66 20.66 23.66 26.66 20.66 16.325 13.325 ],[14" ".33 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([16.325 20.66 17.66 13.325 16.325 ],[11.33 11." "33 14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([13.325 17.66 20.66 16.325 13.325 ],[8.33 8.33 11.33 11.33 " "8.33 ],[1 1 1 ]);\npatch([16.325 26.66 23.66 20.66 17.66 13.325 16.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncol" "or('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "11619" Position [770, 88, 800, 102] IconDisplay "Port number" } Line { SrcBlock "D" SrcPort 1 Points [15, 0] Branch { Points [0, -30] DstBlock "b[12]" DstPort 1 } Branch { Points [0, 20] Branch { Points [0, 170] Branch { Points [0, 35] DstBlock "b[6]1" DstPort 1 } Branch { DstBlock "b[10:7]" DstPort 1 } } Branch { DstBlock "b[11:10]" DstPort 1 } } } Line { SrcBlock "b[12]" SrcPort 1 Points [55, 0] Branch { DstBlock "Inverter" DstPort 1 } Branch { Points [0, 110] Branch { DstBlock "Logical2" DstPort 1 } Branch { Points [0, 70; 285, 0; 0, -80] DstBlock "Mux2" DstPort 1 } } } Line { SrcBlock "Constant" SrcPort 1 DstBlock "Relational" DstPort 2 } Line { SrcBlock "b[11:10]" SrcPort 1 Points [80, 0] Branch { DstBlock "Relational" DstPort 1 } Branch { Points [0, 80] DstBlock "Relational1" DstPort 1 } } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical" DstPort 1 } Line { SrcBlock "Relational" SrcPort 1 Points [15, 0; 0, -45] DstBlock "Logical" DstPort 2 } Line { SrcBlock "Logical" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Relational1" SrcPort 1 Points [15, 0; 0, -15] DstBlock "Logical2" DstPort 2 } Line { SrcBlock "Constant4" SrcPort 1 DstBlock "Relational1" DstPort 2 } Line { SrcBlock "Logical2" SrcPort 1 Points [20, 0; 0, -90] DstBlock "Logical1" DstPort 2 } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Inverter1" DstPort 1 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Mux2" DstPort 2 } Line { SrcBlock "Constant2" SrcPort 1 DstBlock "Mux2" DstPort 3 } Line { SrcBlock "Mux2" SrcPort 1 Points [5, 0; 0, -75] DstBlock "Mux1" DstPort 2 } Line { SrcBlock "Inverter1" SrcPort 1 DstBlock "Mux1" DstPort 1 } Line { SrcBlock "b[6]1" SrcPort 1 Points [50, 0] DstBlock "AddSub1" DstPort 2 } Line { SrcBlock "AddSub1" SrcPort 1 Points [365, 0; 0, -140] DstBlock "Mux1" DstPort 3 } Line { SrcBlock "b[10:7]" SrcPort 1 DstBlock "Reinterpret" DstPort 1 } Line { SrcBlock "Reinterpret" SrcPort 1 DstBlock "AddSub1" DstPort 1 } Line { SrcBlock "Mux1" SrcPort 1 DstBlock "Q" DstPort 1 } Annotation { Position [50, 166] } } } Block { BlockType SubSystem Name "Quantize3" SID "11620" Ports [1, 1] Position [1140, 400, 1190, 420] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Quantize3" Location [104, 160, 2085, 1232] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "11621" Position [25, 63, 55, 77] IconDisplay "Port number" } Block { BlockType Reference Name "AddSub1" SID "11622" Ports [2, 1] Position [245, 250, 280, 290] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Signed (2's comp)" n_bits "4" bin_pt "0" quantization "Truncate" overflow "Saturate" dbl_ovrd off use_behavioral_HDL off hw_selection "Fabric" pipelined off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" sg_icon_stat "35,40,2,1,white,blue,0,e139daf6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 40 40 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bf{a + b}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant" SID "11623" Ports [0, 1] Position [275, 105, 300, 125] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,20,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 20 20 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 20 20 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[12.22 12" ".22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[10.22 10.22 12.22 12." "22 10.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\n" "patch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('out" "put',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant1" SID "11624" Ports [0, 1] Position [515, 160, 540, 180] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "7" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "4" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,20,0,1,white,blue,0,2a6960a5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 20 20 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 20 20 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[12.22 12" ".22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[10.22 10.22 12.22 12." "22 10.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\n" "patch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('out" "put',1,'7');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant2" SID "11625" Ports [0, 1] Position [515, 190, 540, 210] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "-8" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "4" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,20,0,1,white,blue,0,4407d5c1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 20 20 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 20 20 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[12.22 12" ".22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[10.22 10.22 12.22 12." "22 10.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\n" "patch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('out" "put',1,'-8');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant4" SID "11626" Ports [0, 1] Position [275, 185, 300, 205] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "3" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,20,0,1,white,blue,0,279a71c8,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 20 20 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 20 20 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[12.22 12" ".22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[10.22 10.22 12.22 12." "22 10.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\n" "patch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('out" "put',1,'3');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "11627" Ports [1, 1] Position [270, 30, 305, 50] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "35,20,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 20 20 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 20 20 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[12.22" " 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[10.22 10.22 12." "22 12.22 10.22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1" " 1 1 ]);\npatch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black'" ");disp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter1" SID "11628" Ports [1, 1] Position [610, 50, 645, 70] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "35,20,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 20 20 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 20 20 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[12.22" " 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[10.22 10.22 12." "22 12.22 10.22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1" " 1 1 ]);\npatch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black'" ");disp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical" SID "11629" Ports [2, 1] Position [435, 30, 470, 70] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,40,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 40 40 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('b" "lack');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "11630" Ports [2, 1] Position [520, 40, 555, 80] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,40,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 40 40 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('b" "lack');disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "11631" Ports [2, 1] Position [435, 140, 470, 180] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,40,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 40 40 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('b" "lack');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux1" SID "11632" Ports [3, 1] Position [685, 42, 730, 148] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "45,106,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 15.1429 90.8571 106 0 " "],[0.77 0.82 0.91 ]);\nplot([0 45 45 0 0 ],[0 15.1429 90.8571 106 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23." "32 14.65 8.65 ],[59.66 59.66 65.66 59.66 65.66 65.66 65.66 59.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14." "65 ],[53.66 53.66 59.66 59.66 53.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[47.66 47.66 " "53.66 53.66 47.66 ],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[41.66 41.66 47.66 41.66 47.66" " 47.66 41.66 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin ico" "n text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black" "');port_label('input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon t" "ext');" } Block { BlockType Reference Name "Mux2" SID "11633" Ports [3, 1] Position [575, 126, 615, 214] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "40,88,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 12.5714 75.4286 88 0 ]" ",[0.77 0.82 0.91 ]);\nplot([0 40 40 0 0 ],[0 12.5714 75.4286 88 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13." "875 8.875 ],[49.55 49.55 54.55 49.55 54.55 54.55 54.55 49.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 " "],[44.55 44.55 49.55 49.55 44.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[39.55 39.55 44" ".55 44.55 39.55 ],[1 1 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[34.55 34.55 39.55 34.55 39.55 39" ".55 34.55 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon t" "ext');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');" "port_label('input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text" "');" } Block { BlockType Reference Name "Reinterpret" SID "11634" Ports [1, 1] Position [160, 252, 195, 268] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can change the signal betwe" "en signed and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothi" "ng.

Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced " "to unsigned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output " "of 56 (111000 in binary)." force_arith_type on arith_type "Signed (2's comp)" force_bin_pt off bin_pt "0" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "reinterpret" sg_icon_stat "35,16,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 16 16 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');dis" "p('reinterpret');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational" SID "11635" Ports [2, 1] Position [345, 79, 385, 126] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a!=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "40,47,2,1,white,blue,0,850de6e7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 47 47 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 47 47 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[28.55 28." "55 33.55 28.55 33.55 33.55 33.55 28.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[23.55 23.55 28.55 2" "8.55 23.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[18.55 18.55 23.55 23.55 18.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[13.55 13.55 18.55 13.55 18.55 18.55 13.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bfa \\neq b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational1" SID "11636" Ports [2, 1] Position [345, 159, 385, 206] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a!=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "40,47,2,1,white,blue,0,850de6e7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 47 47 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 47 47 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[28.55 28." "55 33.55 28.55 33.55 33.55 33.55 28.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[23.55 23.55 28.55 2" "8.55 23.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[18.55 18.55 23.55 23.55 18.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[13.55 13.55 18.55 13.55 18.55 18.55 13.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bfa \\neq b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[10:7]" SID "11637" Ports [1, 1] Position [90, 249, 130, 271] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "4" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "7" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,22,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 22 22 0 ]);\npatch([13.325 17.66 20.66 23.66 26.66 20.66 16.325 13.325 ],[14" ".33 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([16.325 20.66 17.66 13.325 16.325 ],[11.33 11." "33 14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([13.325 17.66 20.66 16.325 13.325 ],[8.33 8.33 11.33 11.33 " "8.33 ],[1 1 1 ]);\npatch([16.325 26.66 23.66 20.66 17.66 13.325 16.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncol" "or('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[11:10]" SID "11638" Ports [1, 1] Position [120, 79, 160, 101] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "2" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "10" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,22,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 22 22 0 ]);\npatch([13.325 17.66 20.66 23.66 26.66 20.66 16.325 13.325 ],[14" ".33 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([16.325 20.66 17.66 13.325 16.325 ],[11.33 11." "33 14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([13.325 17.66 20.66 16.325 13.325 ],[8.33 8.33 11.33 11.33 " "8.33 ],[1 1 1 ]);\npatch([16.325 26.66 23.66 20.66 17.66 13.325 16.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncol" "or('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[12]" SID "11639" Ports [1, 1] Position [120, 29, 160, 51] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "12" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,22,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 22 22 0 ]);\npatch([13.325 17.66 20.66 23.66 26.66 20.66 16.325 13.325 ],[14" ".33 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([16.325 20.66 17.66 13.325 16.325 ],[11.33 11." "33 14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([13.325 17.66 20.66 16.325 13.325 ],[8.33 8.33 11.33 11.33 " "8.33 ],[1 1 1 ]);\npatch([16.325 26.66 23.66 20.66 17.66 13.325 16.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncol" "or('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[6]1" SID "11640" Ports [1, 1] Position [135, 284, 175, 306] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "6" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,22,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 22 22 0 ]);\npatch([13.325 17.66 20.66 23.66 26.66 20.66 16.325 13.325 ],[14" ".33 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([16.325 20.66 17.66 13.325 16.325 ],[11.33 11." "33 14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([13.325 17.66 20.66 16.325 13.325 ],[8.33 8.33 11.33 11.33 " "8.33 ],[1 1 1 ]);\npatch([16.325 26.66 23.66 20.66 17.66 13.325 16.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncol" "or('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "11641" Position [770, 88, 800, 102] IconDisplay "Port number" } Line { SrcBlock "Mux1" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "Reinterpret" SrcPort 1 DstBlock "AddSub1" DstPort 1 } Line { SrcBlock "b[10:7]" SrcPort 1 DstBlock "Reinterpret" DstPort 1 } Line { SrcBlock "AddSub1" SrcPort 1 Points [365, 0; 0, -140] DstBlock "Mux1" DstPort 3 } Line { SrcBlock "b[6]1" SrcPort 1 Points [50, 0] DstBlock "AddSub1" DstPort 2 } Line { SrcBlock "Inverter1" SrcPort 1 DstBlock "Mux1" DstPort 1 } Line { SrcBlock "Mux2" SrcPort 1 Points [5, 0; 0, -75] DstBlock "Mux1" DstPort 2 } Line { SrcBlock "Constant2" SrcPort 1 DstBlock "Mux2" DstPort 3 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Mux2" DstPort 2 } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Inverter1" DstPort 1 } Line { SrcBlock "Logical2" SrcPort 1 Points [20, 0; 0, -90] DstBlock "Logical1" DstPort 2 } Line { SrcBlock "Constant4" SrcPort 1 DstBlock "Relational1" DstPort 2 } Line { SrcBlock "Relational1" SrcPort 1 Points [15, 0; 0, -15] DstBlock "Logical2" DstPort 2 } Line { SrcBlock "Logical" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Relational" SrcPort 1 Points [15, 0; 0, -45] DstBlock "Logical" DstPort 2 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical" DstPort 1 } Line { SrcBlock "b[11:10]" SrcPort 1 Points [80, 0] Branch { Points [0, 80] DstBlock "Relational1" DstPort 1 } Branch { DstBlock "Relational" DstPort 1 } } Line { SrcBlock "Constant" SrcPort 1 DstBlock "Relational" DstPort 2 } Line { SrcBlock "b[12]" SrcPort 1 Points [55, 0] Branch { Points [0, 110] Branch { Points [0, 70; 285, 0; 0, -80] DstBlock "Mux2" DstPort 1 } Branch { DstBlock "Logical2" DstPort 1 } } Branch { DstBlock "Inverter" DstPort 1 } } Line { SrcBlock "D" SrcPort 1 Points [15, 0] Branch { Points [0, 20] Branch { DstBlock "b[11:10]" DstPort 1 } Branch { Points [0, 170] Branch { DstBlock "b[10:7]" DstPort 1 } Branch { Points [0, 35] DstBlock "b[6]1" DstPort 1 } } } Branch { Points [0, -30] DstBlock "b[12]" DstPort 1 } } Annotation { Position [50, 166] } } } Block { BlockType SubSystem Name "Quantize4" SID "11642" Ports [1, 1] Position [1140, 605, 1190, 625] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Quantize4" Location [104, 160, 2085, 1232] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "11643" Position [25, 63, 55, 77] IconDisplay "Port number" } Block { BlockType Reference Name "AddSub1" SID "11644" Ports [2, 1] Position [245, 250, 280, 290] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Signed (2's comp)" n_bits "4" bin_pt "0" quantization "Truncate" overflow "Saturate" dbl_ovrd off use_behavioral_HDL off hw_selection "Fabric" pipelined off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" sg_icon_stat "35,40,2,1,white,blue,0,e139daf6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 40 40 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bf{a + b}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant" SID "11645" Ports [0, 1] Position [275, 105, 300, 125] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,20,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 20 20 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 20 20 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[12.22 12" ".22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[10.22 10.22 12.22 12." "22 10.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\n" "patch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('out" "put',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant1" SID "11646" Ports [0, 1] Position [515, 160, 540, 180] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "7" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "4" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,20,0,1,white,blue,0,2a6960a5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 20 20 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 20 20 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[12.22 12" ".22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[10.22 10.22 12.22 12." "22 10.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\n" "patch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('out" "put',1,'7');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant2" SID "11647" Ports [0, 1] Position [515, 190, 540, 210] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "-8" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "4" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,20,0,1,white,blue,0,4407d5c1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 20 20 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 20 20 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[12.22 12" ".22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[10.22 10.22 12.22 12." "22 10.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\n" "patch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('out" "put',1,'-8');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant4" SID "11648" Ports [0, 1] Position [275, 185, 300, 205] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "3" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,20,0,1,white,blue,0,279a71c8,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 20 20 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 20 20 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[12.22 12" ".22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[10.22 10.22 12.22 12." "22 10.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\n" "patch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('out" "put',1,'3');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "11649" Ports [1, 1] Position [270, 30, 305, 50] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "35,20,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 20 20 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 20 20 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[12.22" " 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[10.22 10.22 12." "22 12.22 10.22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1" " 1 1 ]);\npatch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black'" ");disp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter1" SID "11650" Ports [1, 1] Position [610, 50, 645, 70] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "35,20,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 20 20 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 20 20 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[12.22" " 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[10.22 10.22 12." "22 12.22 10.22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1" " 1 1 ]);\npatch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black'" ");disp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical" SID "11651" Ports [2, 1] Position [435, 30, 470, 70] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,40,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 40 40 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('b" "lack');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "11652" Ports [2, 1] Position [520, 40, 555, 80] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,40,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 40 40 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('b" "lack');disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "11653" Ports [2, 1] Position [435, 140, 470, 180] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,40,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 40 40 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('b" "lack');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux1" SID "11654" Ports [3, 1] Position [685, 42, 730, 148] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "45,106,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 15.1429 90.8571 106 0 " "],[0.77 0.82 0.91 ]);\nplot([0 45 45 0 0 ],[0 15.1429 90.8571 106 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23." "32 14.65 8.65 ],[59.66 59.66 65.66 59.66 65.66 65.66 65.66 59.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14." "65 ],[53.66 53.66 59.66 59.66 53.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[47.66 47.66 " "53.66 53.66 47.66 ],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[41.66 41.66 47.66 41.66 47.66" " 47.66 41.66 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin ico" "n text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black" "');port_label('input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon t" "ext');" } Block { BlockType Reference Name "Mux2" SID "11655" Ports [3, 1] Position [575, 126, 615, 214] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "40,88,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 12.5714 75.4286 88 0 ]" ",[0.77 0.82 0.91 ]);\nplot([0 40 40 0 0 ],[0 12.5714 75.4286 88 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13." "875 8.875 ],[49.55 49.55 54.55 49.55 54.55 54.55 54.55 49.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 " "],[44.55 44.55 49.55 49.55 44.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[39.55 39.55 44" ".55 44.55 39.55 ],[1 1 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[34.55 34.55 39.55 34.55 39.55 39" ".55 34.55 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon t" "ext');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');" "port_label('input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text" "');" } Block { BlockType Reference Name "Reinterpret" SID "11656" Ports [1, 1] Position [160, 252, 195, 268] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can change the signal betwe" "en signed and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothi" "ng.

Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced " "to unsigned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output " "of 56 (111000 in binary)." force_arith_type on arith_type "Signed (2's comp)" force_bin_pt off bin_pt "0" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "reinterpret" sg_icon_stat "35,16,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 16 16 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');dis" "p('reinterpret');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational" SID "11657" Ports [2, 1] Position [345, 79, 385, 126] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a!=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "40,47,2,1,white,blue,0,850de6e7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 47 47 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 47 47 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[28.55 28." "55 33.55 28.55 33.55 33.55 33.55 28.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[23.55 23.55 28.55 2" "8.55 23.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[18.55 18.55 23.55 23.55 18.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[13.55 13.55 18.55 13.55 18.55 18.55 13.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bfa \\neq b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational1" SID "11658" Ports [2, 1] Position [345, 159, 385, 206] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a!=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "40,47,2,1,white,blue,0,850de6e7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 47 47 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 47 47 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[28.55 28." "55 33.55 28.55 33.55 33.55 33.55 28.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[23.55 23.55 28.55 2" "8.55 23.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[18.55 18.55 23.55 23.55 18.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[13.55 13.55 18.55 13.55 18.55 18.55 13.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bfa \\neq b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[10:7]" SID "11659" Ports [1, 1] Position [90, 249, 130, 271] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "4" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "7" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,22,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 22 22 0 ]);\npatch([13.325 17.66 20.66 23.66 26.66 20.66 16.325 13.325 ],[14" ".33 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([16.325 20.66 17.66 13.325 16.325 ],[11.33 11." "33 14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([13.325 17.66 20.66 16.325 13.325 ],[8.33 8.33 11.33 11.33 " "8.33 ],[1 1 1 ]);\npatch([16.325 26.66 23.66 20.66 17.66 13.325 16.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncol" "or('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[11:10]" SID "11660" Ports [1, 1] Position [120, 79, 160, 101] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "2" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "10" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,22,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 22 22 0 ]);\npatch([13.325 17.66 20.66 23.66 26.66 20.66 16.325 13.325 ],[14" ".33 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([16.325 20.66 17.66 13.325 16.325 ],[11.33 11." "33 14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([13.325 17.66 20.66 16.325 13.325 ],[8.33 8.33 11.33 11.33 " "8.33 ],[1 1 1 ]);\npatch([16.325 26.66 23.66 20.66 17.66 13.325 16.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncol" "or('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[12]" SID "11661" Ports [1, 1] Position [120, 29, 160, 51] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "12" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,22,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 22 22 0 ]);\npatch([13.325 17.66 20.66 23.66 26.66 20.66 16.325 13.325 ],[14" ".33 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([16.325 20.66 17.66 13.325 16.325 ],[11.33 11." "33 14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([13.325 17.66 20.66 16.325 13.325 ],[8.33 8.33 11.33 11.33 " "8.33 ],[1 1 1 ]);\npatch([16.325 26.66 23.66 20.66 17.66 13.325 16.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncol" "or('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[6]1" SID "11662" Ports [1, 1] Position [135, 284, 175, 306] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "6" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,22,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 22 22 0 ]);\npatch([13.325 17.66 20.66 23.66 26.66 20.66 16.325 13.325 ],[14" ".33 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([16.325 20.66 17.66 13.325 16.325 ],[11.33 11." "33 14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([13.325 17.66 20.66 16.325 13.325 ],[8.33 8.33 11.33 11.33 " "8.33 ],[1 1 1 ]);\npatch([16.325 26.66 23.66 20.66 17.66 13.325 16.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncol" "or('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "11663" Position [770, 88, 800, 102] IconDisplay "Port number" } Line { SrcBlock "D" SrcPort 1 Points [15, 0] Branch { Points [0, -30] DstBlock "b[12]" DstPort 1 } Branch { Points [0, 20] Branch { Points [0, 170] Branch { Points [0, 35] DstBlock "b[6]1" DstPort 1 } Branch { DstBlock "b[10:7]" DstPort 1 } } Branch { DstBlock "b[11:10]" DstPort 1 } } } Line { SrcBlock "b[12]" SrcPort 1 Points [55, 0] Branch { DstBlock "Inverter" DstPort 1 } Branch { Points [0, 110] Branch { DstBlock "Logical2" DstPort 1 } Branch { Points [0, 70; 285, 0; 0, -80] DstBlock "Mux2" DstPort 1 } } } Line { SrcBlock "Constant" SrcPort 1 DstBlock "Relational" DstPort 2 } Line { SrcBlock "b[11:10]" SrcPort 1 Points [80, 0] Branch { DstBlock "Relational" DstPort 1 } Branch { Points [0, 80] DstBlock "Relational1" DstPort 1 } } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical" DstPort 1 } Line { SrcBlock "Relational" SrcPort 1 Points [15, 0; 0, -45] DstBlock "Logical" DstPort 2 } Line { SrcBlock "Logical" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Relational1" SrcPort 1 Points [15, 0; 0, -15] DstBlock "Logical2" DstPort 2 } Line { SrcBlock "Constant4" SrcPort 1 DstBlock "Relational1" DstPort 2 } Line { SrcBlock "Logical2" SrcPort 1 Points [20, 0; 0, -90] DstBlock "Logical1" DstPort 2 } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Inverter1" DstPort 1 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Mux2" DstPort 2 } Line { SrcBlock "Constant2" SrcPort 1 DstBlock "Mux2" DstPort 3 } Line { SrcBlock "Mux2" SrcPort 1 Points [5, 0; 0, -75] DstBlock "Mux1" DstPort 2 } Line { SrcBlock "Inverter1" SrcPort 1 DstBlock "Mux1" DstPort 1 } Line { SrcBlock "b[6]1" SrcPort 1 Points [50, 0] DstBlock "AddSub1" DstPort 2 } Line { SrcBlock "AddSub1" SrcPort 1 Points [365, 0; 0, -140] DstBlock "Mux1" DstPort 3 } Line { SrcBlock "b[10:7]" SrcPort 1 DstBlock "Reinterpret" DstPort 1 } Line { SrcBlock "Reinterpret" SrcPort 1 DstBlock "AddSub1" DstPort 1 } Line { SrcBlock "Mux1" SrcPort 1 DstBlock "Q" DstPort 1 } Annotation { Position [50, 166] } } } Block { BlockType SubSystem Name "Quantize5" SID "11664" Ports [1, 1] Position [1140, 685, 1190, 705] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Quantize5" Location [104, 160, 2085, 1232] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "11665" Position [25, 63, 55, 77] IconDisplay "Port number" } Block { BlockType Reference Name "AddSub1" SID "11666" Ports [2, 1] Position [245, 250, 280, 290] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Signed (2's comp)" n_bits "4" bin_pt "0" quantization "Truncate" overflow "Saturate" dbl_ovrd off use_behavioral_HDL off hw_selection "Fabric" pipelined off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" sg_icon_stat "35,40,2,1,white,blue,0,e139daf6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 40 40 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bf{a + b}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant" SID "11667" Ports [0, 1] Position [275, 105, 300, 125] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,20,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 20 20 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 20 20 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[12.22 12" ".22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[10.22 10.22 12.22 12." "22 10.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\n" "patch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('out" "put',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant1" SID "11668" Ports [0, 1] Position [515, 160, 540, 180] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "7" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "4" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,20,0,1,white,blue,0,2a6960a5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 20 20 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 20 20 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[12.22 12" ".22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[10.22 10.22 12.22 12." "22 10.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\n" "patch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('out" "put',1,'7');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant2" SID "11669" Ports [0, 1] Position [515, 190, 540, 210] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "-8" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "4" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,20,0,1,white,blue,0,4407d5c1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 20 20 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 20 20 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[12.22 12" ".22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[10.22 10.22 12.22 12." "22 10.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\n" "patch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('out" "put',1,'-8');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant4" SID "11670" Ports [0, 1] Position [275, 185, 300, 205] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "3" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,20,0,1,white,blue,0,279a71c8,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 20 20 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 20 20 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[12.22 12" ".22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[10.22 10.22 12.22 12." "22 10.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\n" "patch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('out" "put',1,'3');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "11671" Ports [1, 1] Position [270, 30, 305, 50] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "35,20,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 20 20 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 20 20 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[12.22" " 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[10.22 10.22 12." "22 12.22 10.22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1" " 1 1 ]);\npatch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black'" ");disp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter1" SID "11672" Ports [1, 1] Position [610, 50, 645, 70] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "35,20,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 20 20 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 20 20 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[12.22" " 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[10.22 10.22 12." "22 12.22 10.22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1" " 1 1 ]);\npatch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black'" ");disp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical" SID "11673" Ports [2, 1] Position [435, 30, 470, 70] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,40,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 40 40 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('b" "lack');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "11674" Ports [2, 1] Position [520, 40, 555, 80] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,40,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 40 40 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('b" "lack');disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "11675" Ports [2, 1] Position [435, 140, 470, 180] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,40,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 40 40 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('b" "lack');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux1" SID "11676" Ports [3, 1] Position [685, 42, 730, 148] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "45,106,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 15.1429 90.8571 106 0 " "],[0.77 0.82 0.91 ]);\nplot([0 45 45 0 0 ],[0 15.1429 90.8571 106 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23." "32 14.65 8.65 ],[59.66 59.66 65.66 59.66 65.66 65.66 65.66 59.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14." "65 ],[53.66 53.66 59.66 59.66 53.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[47.66 47.66 " "53.66 53.66 47.66 ],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[41.66 41.66 47.66 41.66 47.66" " 47.66 41.66 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin ico" "n text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black" "');port_label('input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon t" "ext');" } Block { BlockType Reference Name "Mux2" SID "11677" Ports [3, 1] Position [575, 126, 615, 214] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "40,88,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 12.5714 75.4286 88 0 ]" ",[0.77 0.82 0.91 ]);\nplot([0 40 40 0 0 ],[0 12.5714 75.4286 88 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13." "875 8.875 ],[49.55 49.55 54.55 49.55 54.55 54.55 54.55 49.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 " "],[44.55 44.55 49.55 49.55 44.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[39.55 39.55 44" ".55 44.55 39.55 ],[1 1 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[34.55 34.55 39.55 34.55 39.55 39" ".55 34.55 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon t" "ext');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');" "port_label('input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text" "');" } Block { BlockType Reference Name "Reinterpret" SID "11678" Ports [1, 1] Position [160, 252, 195, 268] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can change the signal betwe" "en signed and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothi" "ng.

Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced " "to unsigned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output " "of 56 (111000 in binary)." force_arith_type on arith_type "Signed (2's comp)" force_bin_pt off bin_pt "0" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "reinterpret" sg_icon_stat "35,16,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 16 16 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');dis" "p('reinterpret');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational" SID "11679" Ports [2, 1] Position [345, 79, 385, 126] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a!=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "40,47,2,1,white,blue,0,850de6e7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 47 47 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 47 47 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[28.55 28." "55 33.55 28.55 33.55 33.55 33.55 28.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[23.55 23.55 28.55 2" "8.55 23.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[18.55 18.55 23.55 23.55 18.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[13.55 13.55 18.55 13.55 18.55 18.55 13.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bfa \\neq b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational1" SID "11680" Ports [2, 1] Position [345, 159, 385, 206] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a!=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "40,47,2,1,white,blue,0,850de6e7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 47 47 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 47 47 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[28.55 28." "55 33.55 28.55 33.55 33.55 33.55 28.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[23.55 23.55 28.55 2" "8.55 23.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[18.55 18.55 23.55 23.55 18.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[13.55 13.55 18.55 13.55 18.55 18.55 13.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bfa \\neq b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[10:7]" SID "11681" Ports [1, 1] Position [90, 249, 130, 271] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "4" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "7" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,22,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 22 22 0 ]);\npatch([13.325 17.66 20.66 23.66 26.66 20.66 16.325 13.325 ],[14" ".33 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([16.325 20.66 17.66 13.325 16.325 ],[11.33 11." "33 14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([13.325 17.66 20.66 16.325 13.325 ],[8.33 8.33 11.33 11.33 " "8.33 ],[1 1 1 ]);\npatch([16.325 26.66 23.66 20.66 17.66 13.325 16.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncol" "or('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[11:10]" SID "11682" Ports [1, 1] Position [120, 79, 160, 101] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "2" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "10" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,22,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 22 22 0 ]);\npatch([13.325 17.66 20.66 23.66 26.66 20.66 16.325 13.325 ],[14" ".33 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([16.325 20.66 17.66 13.325 16.325 ],[11.33 11." "33 14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([13.325 17.66 20.66 16.325 13.325 ],[8.33 8.33 11.33 11.33 " "8.33 ],[1 1 1 ]);\npatch([16.325 26.66 23.66 20.66 17.66 13.325 16.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncol" "or('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[12]" SID "11683" Ports [1, 1] Position [120, 29, 160, 51] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "12" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,22,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 22 22 0 ]);\npatch([13.325 17.66 20.66 23.66 26.66 20.66 16.325 13.325 ],[14" ".33 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([16.325 20.66 17.66 13.325 16.325 ],[11.33 11." "33 14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([13.325 17.66 20.66 16.325 13.325 ],[8.33 8.33 11.33 11.33 " "8.33 ],[1 1 1 ]);\npatch([16.325 26.66 23.66 20.66 17.66 13.325 16.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncol" "or('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[6]1" SID "11684" Ports [1, 1] Position [135, 284, 175, 306] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "6" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,22,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 22 22 0 ]);\npatch([13.325 17.66 20.66 23.66 26.66 20.66 16.325 13.325 ],[14" ".33 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([16.325 20.66 17.66 13.325 16.325 ],[11.33 11." "33 14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([13.325 17.66 20.66 16.325 13.325 ],[8.33 8.33 11.33 11.33 " "8.33 ],[1 1 1 ]);\npatch([16.325 26.66 23.66 20.66 17.66 13.325 16.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncol" "or('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "11685" Position [770, 88, 800, 102] IconDisplay "Port number" } Line { SrcBlock "Mux1" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "Reinterpret" SrcPort 1 DstBlock "AddSub1" DstPort 1 } Line { SrcBlock "b[10:7]" SrcPort 1 DstBlock "Reinterpret" DstPort 1 } Line { SrcBlock "AddSub1" SrcPort 1 Points [365, 0; 0, -140] DstBlock "Mux1" DstPort 3 } Line { SrcBlock "b[6]1" SrcPort 1 Points [50, 0] DstBlock "AddSub1" DstPort 2 } Line { SrcBlock "Inverter1" SrcPort 1 DstBlock "Mux1" DstPort 1 } Line { SrcBlock "Mux2" SrcPort 1 Points [5, 0; 0, -75] DstBlock "Mux1" DstPort 2 } Line { SrcBlock "Constant2" SrcPort 1 DstBlock "Mux2" DstPort 3 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Mux2" DstPort 2 } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Inverter1" DstPort 1 } Line { SrcBlock "Logical2" SrcPort 1 Points [20, 0; 0, -90] DstBlock "Logical1" DstPort 2 } Line { SrcBlock "Constant4" SrcPort 1 DstBlock "Relational1" DstPort 2 } Line { SrcBlock "Relational1" SrcPort 1 Points [15, 0; 0, -15] DstBlock "Logical2" DstPort 2 } Line { SrcBlock "Logical" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Relational" SrcPort 1 Points [15, 0; 0, -45] DstBlock "Logical" DstPort 2 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical" DstPort 1 } Line { SrcBlock "b[11:10]" SrcPort 1 Points [80, 0] Branch { Points [0, 80] DstBlock "Relational1" DstPort 1 } Branch { DstBlock "Relational" DstPort 1 } } Line { SrcBlock "Constant" SrcPort 1 DstBlock "Relational" DstPort 2 } Line { SrcBlock "b[12]" SrcPort 1 Points [55, 0] Branch { Points [0, 110] Branch { Points [0, 70; 285, 0; 0, -80] DstBlock "Mux2" DstPort 1 } Branch { DstBlock "Logical2" DstPort 1 } } Branch { DstBlock "Inverter" DstPort 1 } } Line { SrcBlock "D" SrcPort 1 Points [15, 0] Branch { Points [0, 20] Branch { DstBlock "b[11:10]" DstPort 1 } Branch { Points [0, 170] Branch { DstBlock "b[10:7]" DstPort 1 } Branch { Points [0, 35] DstBlock "b[6]1" DstPort 1 } } } Branch { Points [0, -30] DstBlock "b[12]" DstPort 1 } } Annotation { Position [50, 166] } } } Block { BlockType Reference Name "Register1" SID "11686" Ports [1, 1] Position [765, 452, 790, 478] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 " "19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 1" "3.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\n" "patch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('inp" "ut',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Register10" SID "11687" Ports [1, 1] Position [615, 882, 640, 908] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 " "19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 1" "3.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\n" "patch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('inp" "ut',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Register11" SID "11688" Ports [1, 1] Position [615, 862, 640, 888] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 " "19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 1" "3.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\n" "patch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('inp" "ut',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Register12" SID "11689" Ports [1, 1] Position [615, 842, 640, 868] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 " "19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 1" "3.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\n" "patch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('inp" "ut',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Register13" SID "11690" Ports [1, 1] Position [615, 822, 640, 848] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 " "19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 1" "3.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\n" "patch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('inp" "ut',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Register14" SID "11691" Ports [1, 1] Position [615, 172, 640, 198] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 " "19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 1" "3.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\n" "patch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('inp" "ut',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Register15" SID "11692" Ports [1, 1] Position [595, 487, 620, 513] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 " "19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 1" "3.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\n" "patch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('inp" "ut',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Register16" SID "11693" Ports [1, 1] Position [595, 522, 620, 548] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 " "19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 1" "3.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\n" "patch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('inp" "ut',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Register17" SID "11694" Ports [1, 1] Position [740, 772, 765, 798] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 " "19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 1" "3.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\n" "patch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('inp" "ut',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Register18" SID "11695" Ports [1, 1] Position [960, 612, 985, 638] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 " "19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 1" "3.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\n" "patch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('inp" "ut',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Register19" SID "11696" Ports [1, 1] Position [960, 692, 985, 718] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 " "19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 1" "3.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\n" "patch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('inp" "ut',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "11697" Ports [1, 1] Position [740, 802, 765, 828] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 " "19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 1" "3.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\n" "patch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('inp" "ut',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Register20" SID "11698" Ports [1, 1] Position [960, 407, 985, 433] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 " "19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 1" "3.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\n" "patch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('inp" "ut',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Register21" SID "11699" Ports [1, 1] Position [960, 327, 985, 353] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 " "19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 1" "3.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\n" "patch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('inp" "ut',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Register22" SID "11700" Ports [1, 1] Position [960, 252, 985, 278] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 " "19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 1" "3.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\n" "patch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('inp" "ut',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Register23" SID "11701" Ports [1, 1] Position [960, 172, 985, 198] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 " "19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 1" "3.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\n" "patch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('inp" "ut',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Register3" SID "11702" Ports [1, 1] Position [550, 822, 575, 848] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 " "19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 1" "3.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\n" "patch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('inp" "ut',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Register4" SID "11703" Ports [1, 1] Position [550, 842, 575, 868] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 " "19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 1" "3.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\n" "patch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('inp" "ut',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Register5" SID "11704" Ports [1, 1] Position [550, 862, 575, 888] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 " "19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 1" "3.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\n" "patch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('inp" "ut',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Register6" SID "11705" Ports [1, 1] Position [550, 882, 575, 908] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 " "19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 1" "3.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\n" "patch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('inp" "ut',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Register7" SID "11706" Ports [1, 1] Position [550, 487, 575, 513] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 " "19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 1" "3.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\n" "patch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('inp" "ut',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Register8" SID "11707" Ports [1, 1] Position [550, 522, 575, 548] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 " "19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 1" "3.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\n" "patch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('inp" "ut',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Register9" SID "11708" Ports [1, 1] Position [550, 172, 575, 198] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 " "19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 1" "3.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\n" "patch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('inp" "ut',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Reinterpret" SID "11709" Ports [1, 1] Position [825, 152, 860, 168] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can change the signal between s" "igned and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.
Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsig" "ned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111" "000 in binary)." force_arith_type off arith_type "Signed (2's comp)" force_bin_pt on bin_pt "9" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "reinterpret" sg_icon_stat "35,16,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 16 16 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 16 16 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[10.22 10.22" " 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[8.22 8.22 10.22 10.22 8" ".22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatch" "([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('reinterpret" "');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Reinterpret1" SID "14900" Ports [1, 1] Position [825, 232, 860, 248] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can change the signal between s" "igned and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.
Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsig" "ned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111" "000 in binary)." force_arith_type off arith_type "Signed (2's comp)" force_bin_pt on bin_pt "9" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "reinterpret" sg_icon_stat "35,16,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 16 16 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 16 16 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[10.22 10.22" " 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[8.22 8.22 10.22 10.22 8" ".22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatch" "([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('reinterpret" "');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Reinterpret10" SID "11711" Ports [1, 1] Position [1450, 603, 1495, 627] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can change the signal between s" "igned and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.
Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsig" "ned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111" "000 in binary)." force_arith_type on arith_type "Unsigned" force_bin_pt on bin_pt "0" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "reinterpret" sg_icon_stat "45,24,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 24 24 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 24 24 0 ]);\npatch([15.325 19.66 22.66 25.66 28.66 22.66 18.325 15.325 ],[15.33 15" ".33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([18.325 22.66 19.66 15.325 18.325 ],[12.33 12.33 15.33" " 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([15.325 19.66 22.66 18.325 15.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 " "1 1 ]);\npatch([18.325 28.66 25.66 22.66 19.66 15.325 18.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');" "disp('reinterpret');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Reinterpret11" SID "11712" Ports [1, 1] Position [1450, 683, 1495, 707] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can change the signal between s" "igned and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.
Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsig" "ned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111" "000 in binary)." force_arith_type on arith_type "Unsigned" force_bin_pt on bin_pt "0" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "reinterpret" sg_icon_stat "45,24,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 24 24 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 24 24 0 ]);\npatch([15.325 19.66 22.66 25.66 28.66 22.66 18.325 15.325 ],[15.33 15" ".33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([18.325 22.66 19.66 15.325 18.325 ],[12.33 12.33 15.33" " 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([15.325 19.66 22.66 18.325 15.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 " "1 1 ]);\npatch([18.325 28.66 25.66 22.66 19.66 15.325 18.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');" "disp('reinterpret');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Reinterpret2" SID "14901" Ports [1, 1] Position [825, 307, 860, 323] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can change the signal between s" "igned and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.
Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsig" "ned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111" "000 in binary)." force_arith_type off arith_type "Signed (2's comp)" force_bin_pt on bin_pt "9" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "reinterpret" sg_icon_stat "35,16,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 16 16 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 16 16 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[10.22 10.22" " 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[8.22 8.22 10.22 10.22 8" ".22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatch" "([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('reinterpret" "');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Reinterpret3" SID "14902" Ports [1, 1] Position [825, 387, 860, 403] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can change the signal between s" "igned and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.
Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsig" "ned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111" "000 in binary)." force_arith_type off arith_type "Signed (2's comp)" force_bin_pt on bin_pt "9" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "reinterpret" sg_icon_stat "35,16,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 16 16 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 16 16 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[10.22 10.22" " 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[8.22 8.22 10.22 10.22 8" ".22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatch" "([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('reinterpret" "');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Reinterpret4" SID "14903" Ports [1, 1] Position [825, 592, 860, 608] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can change the signal between s" "igned and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.
Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsig" "ned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111" "000 in binary)." force_arith_type off arith_type "Signed (2's comp)" force_bin_pt on bin_pt "9" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "reinterpret" sg_icon_stat "35,16,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 16 16 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 16 16 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[10.22 10.22" " 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[8.22 8.22 10.22 10.22 8" ".22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatch" "([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('reinterpret" "');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Reinterpret5" SID "14904" Ports [1, 1] Position [825, 672, 860, 688] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can change the signal between s" "igned and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.
Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsig" "ned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111" "000 in binary)." force_arith_type off arith_type "Signed (2's comp)" force_bin_pt on bin_pt "9" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "reinterpret" sg_icon_stat "35,16,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 16 16 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 16 16 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[10.22 10.22" " 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[8.22 8.22 10.22 10.22 8" ".22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatch" "([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('reinterpret" "');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Reinterpret6" SID "11717" Ports [1, 1] Position [1450, 163, 1495, 187] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can change the signal between s" "igned and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.
Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsig" "ned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111" "000 in binary)." force_arith_type on arith_type "Unsigned" force_bin_pt on bin_pt "0" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "reinterpret" sg_icon_stat "45,24,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 24 24 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 24 24 0 ]);\npatch([15.325 19.66 22.66 25.66 28.66 22.66 18.325 15.325 ],[15.33 15" ".33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([18.325 22.66 19.66 15.325 18.325 ],[12.33 12.33 15.33" " 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([15.325 19.66 22.66 18.325 15.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 " "1 1 ]);\npatch([18.325 28.66 25.66 22.66 19.66 15.325 18.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');" "disp('reinterpret');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Reinterpret7" SID "11718" Ports [1, 1] Position [1450, 243, 1495, 267] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can change the signal between s" "igned and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.
Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsig" "ned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111" "000 in binary)." force_arith_type on arith_type "Unsigned" force_bin_pt on bin_pt "0" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "reinterpret" sg_icon_stat "45,24,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 24 24 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 24 24 0 ]);\npatch([15.325 19.66 22.66 25.66 28.66 22.66 18.325 15.325 ],[15.33 15" ".33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([18.325 22.66 19.66 15.325 18.325 ],[12.33 12.33 15.33" " 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([15.325 19.66 22.66 18.325 15.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 " "1 1 ]);\npatch([18.325 28.66 25.66 22.66 19.66 15.325 18.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');" "disp('reinterpret');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Reinterpret8" SID "11719" Ports [1, 1] Position [1450, 318, 1495, 342] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can change the signal between s" "igned and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.
Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsig" "ned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111" "000 in binary)." force_arith_type on arith_type "Unsigned" force_bin_pt on bin_pt "0" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "reinterpret" sg_icon_stat "45,24,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 24 24 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 24 24 0 ]);\npatch([15.325 19.66 22.66 25.66 28.66 22.66 18.325 15.325 ],[15.33 15" ".33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([18.325 22.66 19.66 15.325 18.325 ],[12.33 12.33 15.33" " 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([15.325 19.66 22.66 18.325 15.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 " "1 1 ]);\npatch([18.325 28.66 25.66 22.66 19.66 15.325 18.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');" "disp('reinterpret');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Reinterpret9" SID "11720" Ports [1, 1] Position [1450, 398, 1495, 422] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can change the signal between s" "igned and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.
Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsig" "ned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111" "000 in binary)." force_arith_type on arith_type "Unsigned" force_bin_pt on bin_pt "0" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "reinterpret" sg_icon_stat "45,24,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 24 24 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 24 24 0 ]);\npatch([15.325 19.66 22.66 25.66 28.66 22.66 18.325 15.325 ],[15.33 15" ".33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([18.325 22.66 19.66 15.325 18.325 ],[12.33 12.33 15.33" " 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([15.325 19.66 22.66 18.325 15.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 " "1 1 ]);\npatch([18.325 28.66 25.66 22.66 19.66 15.325 18.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');" "disp('reinterpret');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Scope Name "Scale & Quantize" SID "11721" Ports [8] Position [1780, 818, 1815, 1027] ZOrder -3 Floating off Location [1, 45, 1836, 1199] Open off NumInputPorts "8" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" } List { ListType ScopeGraphics FigureColor "[0.5 0.5 0.5]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "9000" YMin "0~0~0~0~-1~0~41.76470588235293~-0.1" YMax "2~1~1~1000~1~1~60.58823529411768~1.1" SaveName "ScopeData51" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType Outport Name "LLRs Valid" SID "11722" Position [1335, 1083, 1365, 1097] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Outport Name "LLR Vec" SID "11723" Position [1690, 233, 1720, 247] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Outport Name " Demog Cfg" SID "11724" Position [1335, 1133, 1365, 1147] NamePlacement "alternate" Port "3" IconDisplay "Port number" } Block { BlockType Outport Name " mod_sel" SID "11725" Position [1345, 778, 1375, 792] NamePlacement "alternate" Port "4" IconDisplay "Port number" } Line { SrcBlock "From1" SrcPort 1 DstBlock "Register4" DstPort 1 } Line { SrcBlock "From2" SrcPort 1 Points [35, 0] Branch { DstBlock "Register5" DstPort 1 } Branch { Points [0, -375] DstBlock "Register7" DstPort 1 } } Line { SrcBlock "From3" SrcPort 1 Points [40, 0] Branch { DstBlock "Register6" DstPort 1 } Branch { Points [0, -360] Branch { DstBlock "Register8" DstPort 1 } Branch { Points [0, -350] DstBlock "Register9" DstPort 1 } } } Line { SrcBlock "b5" SrcPort 1 DstBlock "Reinterpret" DstPort 1 } Line { SrcBlock "Mult0" SrcPort 1 DstBlock "Quantize" DstPort 1 } Line { SrcBlock "Quantize" SrcPort 1 DstBlock "Negate" DstPort 1 } Line { SrcBlock "Bits Valid" SrcPort 1 DstBlock "Delay" DstPort 1 } Line { SrcBlock "Delay" SrcPort 1 Points [205, 0] Branch { DstBlock "LLRs Valid" DstPort 1 } Branch { Points [0, -60; 255, 0; 0, -195] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "Reinterpret" SrcPort 1 DstBlock "Mult0" DstPort 1 } Line { SrcBlock "Negate" SrcPort 1 DstBlock "Reinterpret6" DstPort 1 } Line { SrcBlock "Gateway Out8" SrcPort 1 DstBlock "Display2" DstPort 1 } Line { SrcBlock "Gateway Out7" SrcPort 1 DstBlock "Display1" DstPort 1 } Line { SrcBlock "Gateway Out6" SrcPort 1 DstBlock "Display" DstPort 1 } Line { SrcBlock "b4" SrcPort 1 DstBlock "Reinterpret1" DstPort 1 } Line { SrcBlock "Mult1" SrcPort 1 DstBlock "Quantize1" DstPort 1 } Line { SrcBlock "Quantize1" SrcPort 1 DstBlock "Negate1" DstPort 1 } Line { SrcBlock "Reinterpret1" SrcPort 1 DstBlock "Mult1" DstPort 1 } Line { SrcBlock "Negate1" SrcPort 1 DstBlock "Reinterpret7" DstPort 1 } Line { SrcBlock "b3" SrcPort 1 DstBlock "Reinterpret2" DstPort 1 } Line { SrcBlock "Mult2" SrcPort 1 DstBlock "Quantize2" DstPort 1 } Line { SrcBlock "Quantize2" SrcPort 1 DstBlock "Negate2" DstPort 1 } Line { SrcBlock "Reinterpret2" SrcPort 1 DstBlock "Mult2" DstPort 1 } Line { SrcBlock "Negate2" SrcPort 1 DstBlock "Reinterpret8" DstPort 1 } Line { SrcBlock "b2" SrcPort 1 DstBlock "Reinterpret3" DstPort 1 } Line { SrcBlock "Mult3" SrcPort 1 DstBlock "Quantize3" DstPort 1 } Line { SrcBlock "Quantize3" SrcPort 1 DstBlock "Negate3" DstPort 1 } Line { SrcBlock "Reinterpret3" SrcPort 1 DstBlock "Mult3" DstPort 1 } Line { SrcBlock "Negate3" SrcPort 1 DstBlock "Reinterpret9" DstPort 1 } Line { SrcBlock "b1" SrcPort 1 DstBlock "Reinterpret4" DstPort 1 } Line { SrcBlock "Mult4" SrcPort 1 DstBlock "Quantize4" DstPort 1 } Line { SrcBlock "Quantize4" SrcPort 1 DstBlock "Negate4" DstPort 1 } Line { SrcBlock "Reinterpret4" SrcPort 1 DstBlock "Mult4" DstPort 1 } Line { SrcBlock "Negate4" SrcPort 1 DstBlock "Reinterpret10" DstPort 1 } Line { SrcBlock "b0" SrcPort 1 Points [45, 0] Branch { Points [0, 65; 400, 0; 0, 115] DstBlock "Gateway Out2" DstPort 1 } Branch { DstBlock "Reinterpret5" DstPort 1 } } Line { SrcBlock "Mult5" SrcPort 1 Points [25, 0] Branch { DstBlock "Quantize5" DstPort 1 } Branch { Points [0, 190] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "Quantize5" SrcPort 1 Points [15, 0] Branch { DstBlock "Negate5" DstPort 1 } Branch { Points [0, 215] DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "Reinterpret5" SrcPort 1 DstBlock "Mult5" DstPort 1 } Line { SrcBlock "Negate5" SrcPort 1 DstBlock "Reinterpret11" DstPort 1 } Line { SrcBlock "Demog Cfg" SrcPort 1 DstBlock "Delay2" DstPort 1 } Line { SrcBlock "Delay2" SrcPort 1 DstBlock " Demog Cfg" DstPort 1 } Line { SrcBlock "Concat" SrcPort 1 DstBlock "LLR Vec" DstPort 1 } Line { SrcBlock "Reinterpret6" SrcPort 1 DstBlock "Concat" DstPort 1 } Line { SrcBlock "Reinterpret7" SrcPort 1 Points [20, 0; 0, -55] DstBlock "Concat" DstPort 2 } Line { SrcBlock "Reinterpret8" SrcPort 1 Points [25, 0; 0, -105] DstBlock "Concat" DstPort 3 } Line { SrcBlock "Reinterpret9" SrcPort 1 Points [30, 0; 0, -160] DstBlock "Concat" DstPort 4 } Line { SrcBlock "Reinterpret10" SrcPort 1 Points [35, 0; 0, -340] DstBlock "Concat" DstPort 5 } Line { SrcBlock "Reinterpret11" SrcPort 1 Points [40, 0; 0, -395] DstBlock "Concat" DstPort 6 } Line { SrcBlock "From4" SrcPort 1 DstBlock "Register3" DstPort 1 } Line { SrcBlock "Gateway Out9" SrcPort 1 DstBlock "Display3" DstPort 1 } Line { SrcBlock "Mux" SrcPort 1 Points [45, 0; 0, -150] Branch { Points [0, -80] DstBlock "Register18" DstPort 1 } Branch { DstBlock "Register19" DstPort 1 } } Line { SrcBlock "mod_sel" SrcPort 1 Points [90, 0] Branch { Points [0, -350] DstBlock "LSB" DstPort 1 } Branch { Points [70, 0] Branch { DstBlock "Register2" DstPort 1 } Branch { Points [0, -30] DstBlock "Register17" DstPort 1 } } } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Mux" DstPort 1 } Line { SrcBlock "Mux1" SrcPort 1 Points [35, 0; 0, -80] Branch { DstBlock "Register20" DstPort 1 } Branch { Points [0, -80] DstBlock "Register21" DstPort 1 } } Line { SrcBlock "Register1" SrcPort 1 DstBlock "Mux1" DstPort 1 } Line { SrcBlock "LSB" SrcPort 1 DstBlock "Register1" DstPort 1 } Line { SrcBlock "Register3" SrcPort 1 DstBlock "Register13" DstPort 1 } Line { SrcBlock "Register4" SrcPort 1 DstBlock "Register12" DstPort 1 } Line { SrcBlock "Register5" SrcPort 1 DstBlock "Register11" DstPort 1 } Line { SrcBlock "Register6" SrcPort 1 DstBlock "Register10" DstPort 1 } Line { SrcBlock "Register7" SrcPort 1 DstBlock "Register15" DstPort 1 } Line { SrcBlock "Register8" SrcPort 1 DstBlock "Register16" DstPort 1 } Line { SrcBlock "Register9" SrcPort 1 DstBlock "Register14" DstPort 1 } Line { Name "Valid" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 DstBlock "Scale & Quantize" DstPort 1 } Line { Name "b0" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 DstBlock "Scale & Quantize" DstPort 2 } Line { Name "b0 Mult" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 DstBlock "Scale & Quantize" DstPort 3 } Line { Name "b0 Quant" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 DstBlock "Scale & Quantize" DstPort 4 } Line { SrcBlock "Register10" SrcPort 1 Points [165, 0] Branch { Points [0, 150] DstBlock "Gateway Out8" DstPort 1 } Branch { DstBlock "Mux" DstPort 5 } } Line { SrcBlock "Register11" SrcPort 1 Points [170, 0] Branch { Points [0, 135] DstBlock "Gateway Out7" DstPort 1 } Branch { DstBlock "Mux" DstPort 4 } } Line { SrcBlock "Register12" SrcPort 1 Points [175, 0] Branch { Points [0, 120] DstBlock "Gateway Out6" DstPort 1 } Branch { DstBlock "Mux" DstPort 3 } } Line { SrcBlock "Register13" SrcPort 1 Points [180, 0] Branch { Points [0, 105] DstBlock "Gateway Out9" DstPort 1 } Branch { DstBlock "Mux" DstPort 2 } } Line { SrcBlock "Register14" SrcPort 1 Points [250, 0] Branch { Points [0, 80] DstBlock "Register22" DstPort 1 } Branch { DstBlock "Register23" DstPort 1 } } Line { SrcBlock "Register15" SrcPort 1 DstBlock "Mux1" DstPort 2 } Line { SrcBlock "Register16" SrcPort 1 DstBlock "Mux1" DstPort 3 } Line { SrcBlock "Register17" SrcPort 1 DstBlock "Delay1" DstPort 1 } Line { SrcBlock "Register18" SrcPort 1 DstBlock "Mult4" DstPort 2 } Line { SrcBlock "Register19" SrcPort 1 DstBlock "Mult5" DstPort 2 } Line { SrcBlock "Register20" SrcPort 1 DstBlock "Mult3" DstPort 2 } Line { SrcBlock "Register21" SrcPort 1 DstBlock "Mult2" DstPort 2 } Line { SrcBlock "Register22" SrcPort 1 DstBlock "Mult1" DstPort 2 } Line { SrcBlock "Register23" SrcPort 1 DstBlock "Mult0" DstPort 2 } Line { SrcBlock "Delay1" SrcPort 1 Points [25, 0] Branch { DstBlock " mod_sel" DstPort 1 } Branch { Points [0, 150] DstBlock "Gateway Out5" DstPort 1 } } Line { SrcBlock "Gateway Out5" SrcPort 1 DstBlock "Scale & Quantize" DstPort 5 } Annotation { Position [770, 811] } Annotation { Name "Explicit fanout for better timing closure\nMux-to-mults was criticla path when one 4:1 mux\ndrove all 6 " "multiliers." Position [554, 982] HorizontalAlignment "left" } Annotation { Name "mod_sel" Position [1720, 939] } } } Block { BlockType ToWorkspace Name "To Workspace" SID "11726" Ports [1] Position [630, 850, 690, 880] ZOrder -7 VariableName "demod_out" MaxDataPoints "inf" SampleTime "-1" SaveFormat "Array" } Block { BlockType ToWorkspace Name "To Workspace1" SID "11727" Ports [1] Position [630, 770, 690, 800] ZOrder -7 VariableName "demod_out_valid" MaxDataPoints "inf" SampleTime "-1" SaveFormat "Array" } Block { BlockType Reference Name "b0" SID "11728" Ports [1, 1] Position [460, 304, 495, 326] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "35,22,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 22 22 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 22 22 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ]" ",[14.33 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[11.3" "3 11.33 14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[8.33 8.33 11.33 " "11.33 8.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\n\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b1" SID "11729" Ports [1, 1] Position [460, 329, 495, 351] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "1" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "35,22,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 22 22 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 22 22 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ]" ",[14.33 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[11.3" "3 11.33 14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[8.33 8.33 11.33 " "11.33 8.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\n\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "LLRs Valid" SID "11730" Position [1605, 328, 1635, 342] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Outport Name "LLR Vec" SID "11731" Position [1605, 383, 1635, 397] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Outport Name " Demog Cfg" SID "11732" Position [1605, 438, 1635, 452] NamePlacement "alternate" Port "3" IconDisplay "Port number" } Block { BlockType Outport Name " mod_sel" SID "11733" Position [1605, 493, 1635, 507] NamePlacement "alternate" Port "4" IconDisplay "Port number" } Line { SrcBlock "64QAM Soft De-Map" SrcPort 1 DstBlock "Goto7" DstPort 1 } Line { SrcBlock "64QAM Soft De-Map" SrcPort 2 DstBlock "Goto8" DstPort 1 } Line { SrcBlock "64QAM Soft De-Map" SrcPort 3 DstBlock "Goto9" DstPort 1 } Line { SrcBlock "64QAM Soft De-Map" SrcPort 4 DstBlock "Goto10" DstPort 1 } Line { SrcBlock "64QAM Soft De-Map" SrcPort 5 DstBlock "Goto11" DstPort 1 } Line { SrcBlock "64QAM Soft De-Map" SrcPort 6 DstBlock "Goto12" DstPort 1 } Line { SrcBlock "16QAM Soft De-Map" SrcPort 1 DstBlock "Goto3" DstPort 1 } Line { SrcBlock "16QAM Soft De-Map" SrcPort 2 DstBlock "Goto4" DstPort 1 } Line { SrcBlock "16QAM Soft De-Map" SrcPort 3 DstBlock "Goto5" DstPort 1 } Line { SrcBlock "16QAM Soft De-Map" SrcPort 4 DstBlock "Goto6" DstPort 1 } Line { SrcBlock "QPSK Soft De-Map" SrcPort 1 DstBlock "Goto1" DstPort 1 } Line { SrcBlock "QPSK Soft De-Map" SrcPort 2 DstBlock "Goto2" DstPort 1 } Line { SrcBlock "BPSK Soft De-Map" SrcPort 1 DstBlock "Goto" DstPort 1 } Line { SrcBlock "Mux7" SrcPort 1 Points [200, 0] Branch { Points [0, 20] Branch { DstBlock "Mux1" DstPort 1 } Branch { Points [0, 75] Branch { DstBlock "Mux2" DstPort 1 } Branch { Points [0, 80] Branch { DstBlock "Mux3" DstPort 1 } Branch { Points [0, 80] Branch { DstBlock "Mux4" DstPort 1 } Branch { Points [0, 80] Branch { DstBlock "Mux5" DstPort 1 } Branch { Points [0, 80] DstBlock "Mux6" DstPort 1 } } } } } } Branch { Points [185, 0] Branch { Points [0, 25] DstBlock "Scale &\nQuantize" DstPort 3 } Branch { Points [0, -145] DstBlock "Gateway Out7" DstPort 1 } } } Line { SrcBlock "Constant" SrcPort 1 Points [20, 0] Branch { DstBlock "Mux2" DstPort 2 } Branch { Points [0, 80] Branch { DstBlock "Mux3" DstPort 2 } Branch { Points [0, 15] Branch { DstBlock "Mux3" DstPort 3 } Branch { Points [0, 65] Branch { DstBlock "Mux4" DstPort 2 } Branch { Points [0, 15] Branch { DstBlock "Mux4" DstPort 3 } Branch { Points [0, 65] Branch { DstBlock "Mux5" DstPort 2 } Branch { Points [0, 15] Branch { DstBlock "Mux5" DstPort 3 } Branch { Points [0, 15] Branch { DstBlock "Mux5" DstPort 4 } Branch { Points [0, 50] Branch { DstBlock "Mux6" DstPort 2 } Branch { Points [0, 15] Branch { DstBlock "Mux6" DstPort 3 } Branch { Points [0, 15] DstBlock "Mux6" DstPort 4 } } } } } } } } } } } Line { SrcBlock "From4" SrcPort 1 DstBlock "Mux1" DstPort 2 } Line { SrcBlock "From1" SrcPort 1 DstBlock "Mux1" DstPort 3 } Line { SrcBlock "From2" SrcPort 1 DstBlock "Mux1" DstPort 4 } Line { SrcBlock "From3" SrcPort 1 DstBlock "Mux1" DstPort 5 } Line { SrcBlock "From5" SrcPort 1 DstBlock "Mux2" DstPort 3 } Line { SrcBlock "From6" SrcPort 1 DstBlock "Mux2" DstPort 4 } Line { SrcBlock "From7" SrcPort 1 DstBlock "Mux2" DstPort 5 } Line { SrcBlock "From9" SrcPort 1 DstBlock "Mux3" DstPort 4 } Line { SrcBlock "From10" SrcPort 1 DstBlock "Mux3" DstPort 5 } Line { SrcBlock "From11" SrcPort 1 DstBlock "Mux4" DstPort 4 } Line { SrcBlock "From8" SrcPort 1 DstBlock "Mux4" DstPort 5 } Line { SrcBlock "From12" SrcPort 1 DstBlock "Mux5" DstPort 5 } Line { SrcBlock "From13" SrcPort 1 DstBlock "Mux6" DstPort 5 } Line { SrcBlock "Mux1" SrcPort 1 DstBlock "Register4" DstPort 1 } Line { SrcBlock "Mux2" SrcPort 1 DstBlock "Register1" DstPort 1 } Line { SrcBlock "Mux3" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "Mux4" SrcPort 1 DstBlock "Register3" DstPort 1 } Line { SrcBlock "Mux5" SrcPort 1 DstBlock "Register5" DstPort 1 } Line { SrcBlock "Mux6" SrcPort 1 DstBlock "Register6" DstPort 1 } Line { SrcBlock "I" SrcPort 1 Points [95, 0] Branch { DstBlock "Convert" DstPort 1 } Branch { Labels [2, 0] Points [0, -275] DstBlock "Gateway Out2" DstPort 1 } Branch { Points [0, 435] DstBlock "Gateway Out12" DstPort 1 } } Line { SrcBlock "Q" SrcPort 1 Points [100, 0] Branch { DstBlock "Convert1" DstPort 1 } Branch { Points [0, -265] DstBlock "Gateway Out3" DstPort 1 } Branch { Points [0, 435] DstBlock "Gateway Out13" DstPort 1 } } Line { SrcBlock "b0" SrcPort 1 DstBlock "Register17" DstPort 1 } Line { SrcBlock "Demod cfg" SrcPort 1 Points [25, 0] Branch { DstBlock "Register11" DstPort 1 } Branch { Points [0, -195] DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "b1" SrcPort 1 Points [45, 0] DstBlock "BPSK Soft De-Map" DstPort 1 } Line { SrcBlock "From16" SrcPort 1 DstBlock "Mux7" DstPort 3 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Mux7" DstPort 2 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Mux7" DstPort 1 } Line { SrcBlock "IQ valid" SrcPort 1 Points [20, 0] Branch { DstBlock "Register10" DstPort 1 } Branch { Points [0, -160] DstBlock "Gateway Out1" DstPort 1 } Branch { Points [0, 530] DstBlock "Gateway Out8" DstPort 1 } } Line { SrcBlock "Register8" SrcPort 1 Points [65, 0; 0, 60] DstBlock "Scale &\nQuantize" DstPort 1 } Line { SrcBlock "Register4" SrcPort 1 DstBlock "Scale &\nQuantize" DstPort 4 } Line { SrcBlock "Register1" SrcPort 1 Points [50, 0; 0, -50] DstBlock "Scale &\nQuantize" DstPort 5 } Line { SrcBlock "Register2" SrcPort 1 Points [55, 0; 0, -105] DstBlock "Scale &\nQuantize" DstPort 6 } Line { SrcBlock "Register3" SrcPort 1 Points [60, 0; 0, -160] DstBlock "Scale &\nQuantize" DstPort 7 } Line { SrcBlock "Register5" SrcPort 1 Points [65, 0; 0, -215] DstBlock "Scale &\nQuantize" DstPort 8 } Line { SrcBlock "Register6" SrcPort 1 Points [70, 0; 0, -270] DstBlock "Scale &\nQuantize" DstPort 9 } Line { SrcBlock "Register9" SrcPort 1 Points [60, 0; 0, 60] DstBlock "Scale &\nQuantize" DstPort 2 } Line { SrcBlock "Scale &\nQuantize" SrcPort 1 Points [30, 0] Branch { Points [0, -115] DstBlock "Gateway Out6" DstPort 1 } Branch { DstBlock "Register7" DstPort 1 } } Line { SrcBlock "Scale &\nQuantize" SrcPort 2 Points [35, 0] Branch { DstBlock "Register12" DstPort 1 } Branch { Points [0, -120] DstBlock "Gateway Out9" DstPort 1 } } Line { SrcBlock "Scale &\nQuantize" SrcPort 3 DstBlock "Register13" DstPort 1 } Line { SrcBlock "Scale &\nQuantize" SrcPort 4 Points [45, 0] Branch { Points [0, -255] DstBlock "Gateway Out5" DstPort 1 } Branch { DstBlock "Register14" DstPort 1 } } Line { SrcBlock "Convert" SrcPort 1 Points [105, 0] Branch { DstBlock "BPSK Soft De-Map" DstPort 2 } Branch { Points [0, 55] Branch { DstBlock "QPSK Soft De-Map" DstPort 1 } Branch { Points [0, 70] Branch { DstBlock "16QAM Soft De-Map" DstPort 1 } Branch { Points [0, 105] DstBlock "64QAM Soft De-Map" DstPort 1 } } } } Line { SrcBlock "Convert1" SrcPort 1 Points [100, 0] Branch { DstBlock "BPSK Soft De-Map" DstPort 3 } Branch { Points [0, 60] Branch { DstBlock "QPSK Soft De-Map" DstPort 2 } Branch { Points [0, 85] Branch { DstBlock "16QAM Soft De-Map" DstPort 2 } Branch { Points [0, 120] DstBlock "64QAM Soft De-Map" DstPort 2 } } } } Line { SrcBlock "Register10" SrcPort 1 DstBlock "Register15" DstPort 1 } Line { SrcBlock "Register11" SrcPort 1 Points [30, 0] Branch { Points [0, 25] DstBlock "b1" DstPort 1 } Branch { DstBlock "b0" DstPort 1 } Branch { Points [0, -35] DstBlock "Register16" DstPort 1 } } Line { Name "Demog Cfg" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 DstBlock "Demod" DstPort 2 } Line { Name "IQ Valid" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 DstBlock "Demod" DstPort 1 } Line { Name "I" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 DstBlock "Demod" DstPort 3 } Line { Name "Q" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 DstBlock "Demod" DstPort 4 } Line { Name "Mod Sel Out" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 DstBlock "Demod" DstPort 7 } Line { Name "LLRs Valid" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 DstBlock "Demod" DstPort 6 } Line { SrcBlock "Gateway Out12" SrcPort 1 DstBlock "Real-Imag to\nComplex" DstPort 1 } Line { SrcBlock "Gateway Out13" SrcPort 1 DstBlock "Real-Imag to\nComplex" DstPort 2 } Line { SrcBlock "Real-Imag to\nComplex" SrcPort 1 DstBlock "To Workspace" DstPort 1 } Line { SrcBlock "Gateway Out8" SrcPort 1 DstBlock "To Workspace1" DstPort 1 } Line { SrcBlock "Register7" SrcPort 1 DstBlock "LLRs Valid" DstPort 1 } Line { SrcBlock "Register12" SrcPort 1 DstBlock "LLR Vec" DstPort 1 } Line { SrcBlock "Register13" SrcPort 1 DstBlock " Demog Cfg" DstPort 1 } Line { SrcBlock "Register14" SrcPort 1 DstBlock " mod_sel" DstPort 1 } Line { Name "Mod Sel" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 DstBlock "Demod" DstPort 5 } Line { SrcBlock "Register15" SrcPort 1 DstBlock "Register8" DstPort 1 } Line { SrcBlock "Register16" SrcPort 1 DstBlock "Register9" DstPort 1 } Line { SrcBlock "Register17" SrcPort 1 DstBlock "Inverter" DstPort 1 } Line { Name "LLR Vec" Labels [0, 0] SrcBlock "Gateway Out9" SrcPort 1 DstBlock "Demod" DstPort 8 } } } Block { BlockType SubSystem Name "Subcarrier Map &\nDemod Control" SID "2864" Ports [6, 6] Position [390, 60, 490, 165] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Subcarrier Map &\nDemod Control" Location [98, 303, 2319, 1506] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Eq I" SID "2865" Position [465, 118, 495, 132] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "Eq Q" SID "2866" Position [465, 133, 495, 147] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "iq_valid" SID "2867" Position [155, 563, 185, 577] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "sc_ind" SID "2868" Position [145, 458, 175, 472] Port "4" IconDisplay "Port number" } Block { BlockType Inport Name "Sym ind" SID "2869" Position [470, 253, 500, 267] NamePlacement "alternate" Port "5" IconDisplay "Port number" } Block { BlockType Inport Name "Reset" SID "2870" Position [370, 778, 400, 792] NamePlacement "alternate" Port "6" IconDisplay "Port number" } Block { BlockType Reference Name "Concat" SID "2871" Ports [2, 1] Position [820, 644, 865, 686] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary poi" "nt at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "45,42,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 42 42 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 42 42 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[27." "66 27.66 33.66 27.66 33.66 33.66 33.66 27.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[21.66 21.66 2" "7.66 27.66 21.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[15.66 15.66 21.66 21.66 15.66 " "],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[9.66 9.66 15.66 9.66 15.66 15.66 9.66 ],[0.931" " 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fontsiz" "e{20}\\}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant1" SID "2872" Ports [0, 1] Position [170, 397, 200, 413] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,16,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 16 16 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 16 16 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[1" "0.22 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[8.22 8.22 " "10.22 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[6.22 6.22 8.22 8.22 6.22 ],[" "1 1 1 ]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('output',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant2" SID "2873" Ports [0, 1] Position [460, 807, 490, 823] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,16,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 16 16 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 16 16 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[1" "0.22 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[8.22 8.22 " "10.22 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[6.22 6.22 8.22 8.22 6.22 ],[" "1 1 1 ]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('output',1,'1');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant3" SID "2874" Ports [0, 1] Position [645, 237, 675, 253] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "5" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,16,0,1,white,blue,0,98872051,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 16 16 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 16 16 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[1" "0.22 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[8.22 8.22 " "10.22 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[6.22 6.22 8.22 8.22 6.22 ],[" "1 1 1 ]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('output',1,'5');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant4" SID "2875" Ports [0, 1] Position [645, 282, 675, 298] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "6" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,16,0,1,white,blue,0,f0403ad7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 16 16 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 16 16 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[1" "0.22 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[8.22 8.22 " "10.22 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[6.22 6.22 8.22 8.22 6.22 ],[" "1 1 1 ]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('output',1,'6');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant5" SID "2876" Ports [0, 1] Position [460, 862, 490, 878] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "2" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,16,0,1,white,blue,0,fca86624,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 16 16 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 16 16 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[1" "0.22 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[8.22 8.22 " "10.22 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[6.22 6.22 8.22 8.22 6.22 ],[" "1 1 1 ]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('output',1,'2');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert" SID "2877" Ports [1, 1] Position [260, 561, 285, 579] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do" " not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "16" bin_pt "14" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.2" "2 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 " "11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);" "\npatch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label" "('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Demod Config" SID "2878" Ports [2, 3] Position [600, 627, 720, 683] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Demod Config" Location [98, 303, 2319, 1506] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "sc_ind" SID "2879" Position [85, 563, 115, 577] IconDisplay "Port number" } Block { BlockType Inport Name "sym_ind" SID "2880" Position [65, 758, 95, 772] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "2881" Ports [0, 1] Position [325, 542, 355, 558] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,16,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 16 16 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 16 16 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[10.22 10.22" " 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[8.22 8.22 10.22 10.22 8" ".22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatch" "([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1" ",'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant10" SID "2882" Ports [0, 1] Position [130, 857, 160, 873] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "3" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,16,0,1,white,blue,0,279a71c8,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 16 16 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 16 16 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[10.22 10.22" " 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[8.22 8.22 10.22 10.22 8" ".22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatch" "([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1" ",'3');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant3" SID "2883" Ports [0, 1] Position [130, 892, 160, 908] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "4" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,16,0,1,white,blue,0,85f36853,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 16 16 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 16 16 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[10.22 10.22" " 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[8.22 8.22 10.22 10.22 8" ".22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatch" "([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1" ",'4');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant8" SID "2884" Ports [0, 1] Position [130, 772, 160, 788] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "7" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,16,0,1,white,blue,0,2a6960a5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 16 16 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 16 16 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[10.22 10.22" " 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[8.22 8.22 10.22 10.22 8" ".22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatch" "([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1" ",'7');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant9" SID "2885" Ports [0, 1] Position [130, 822, 160, 838] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "2" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,16,0,1,white,blue,0,fca86624,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 16 16 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 16 16 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[10.22 10.22" " 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[8.22 8.22 10.22 10.22 8" ".22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatch" "([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1" ",'2');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Scope Name "Demod Config" SID "2886" Ports [8] Position [1325, 158, 1360, 367] ZOrder -3 Floating off Location [828, 376, 2077, 1353] Open off NumInputPorts "8" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" } List { ListType ScopeGraphics FigureColor "[0.5 0.5 0.5]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "953.8248648097133" YMin "0~0~0~0~-0.1~-0.1~-0.1~-0.1" YMax "100~30~1~1~1.1~1.1~1.1~1.1" SaveName "ScopeData47" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType From Name "From" SID "2887" Position [265, 508, 430, 532] ZOrder -9 ShowName off GotoTag "RX_PHY_MODE_11N_AC" TagVisibility "global" } Block { BlockType From Name "From1" SID "2888" Position [450, 213, 615, 237] ZOrder -9 ShowName off GotoTag "RX_PHY_MODE_11N" TagVisibility "global" } Block { BlockType From Name "From2" SID "2889" Position [450, 238, 615, 262] ZOrder -9 ShowName off GotoTag "RX_PHY_MODE_11N_AC" TagVisibility "global" } Block { BlockType From Name "From3" SID "2890" Position [260, 598, 425, 622] ZOrder -9 ShowName off GotoTag "RX_PHY_MODE_11N" TagVisibility "global" } Block { BlockType From Name "From4" SID "2891" Position [655, 740, 755, 760] ZOrder -9 ShowName off GotoTag "PHY_11N_AC" } Block { BlockType From Name "From5" SID "2892" Position [645, 930, 745, 950] ZOrder -9 ShowName off GotoTag "PHY_11N" } Block { BlockType Reference Name "Gateway Out1" SID "2893" Ports [1, 1] Position [1140, 169, 1175, 181] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Sc Ind" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "2894" Ports [1, 1] Position [1140, 219, 1175, 231] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "PHY Mode 11N" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "2895" Ports [1, 1] Position [1140, 194, 1175, 206] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Sym Ind" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "2896" Ports [1, 1] Position [1140, 244, 1175, 256] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "PHY Mode 11N_AC" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "2897" Ports [1, 1] Position [1140, 269, 1175, 281] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "PHY Mode 11N capt" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "2898" Ports [1, 1] Position [1140, 294, 1175, 306] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "PHY Mode 11N_AC capt" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "2899" Ports [1, 1] Position [1140, 319, 1175, 331] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "SIGNAL Sym" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "2900" Ports [1, 1] Position [1140, 344, 1175, 356] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "QBPSK Sym" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Goto Name "Goto3" SID "2901" Position [610, 530, 695, 550] ZOrder -10 ShowName off GotoTag "PHY_11N_AC" TagVisibility "local" } Block { BlockType Goto Name "Goto4" SID "2902" Position [610, 620, 695, 640] ZOrder -10 ShowName off GotoTag "PHY_11N" TagVisibility "local" } Block { BlockType Reference Name "Inverter" SID "2903" Ports [1, 1] Position [825, 737, 860, 763] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "35,26,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 26 26 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[16.33 16" ".33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[13.33 13.33 16.33" " 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[10.33 10.33 13.33 13.33 10.33 ]," "[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('bl" "ack');disp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "2904" Ports [2, 1] Position [920, 735, 955, 790] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,55,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 55 55 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 55 55 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[32.55 32.55 37." "55 32.55 37.55 37.55 37.55 32.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[27.55 27.55 32.55 32.55 27." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[22.55 22.55 27.55 27.55 22.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[17.55 17.55 22.55 17.55 22.55 22.55 17.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('o" "r');\nfprintf('','COMMENT: end icon text');" Port { PortNumber 1 Name "48_Subcarrier_Sym" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Logical2" SID "2905" Ports [2, 1] Position [655, 840, 690, 915] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,75,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 75 75 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 75 75 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[42.55 42.55 47." "55 42.55 47.55 47.55 47.55 42.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[37.55 37.55 42.55 42.55 37." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[32.55 32.55 37.55 37.55 32.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[27.55 27.55 32.55 27.55 32.55 32.55 27.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('o" "r');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical3" SID "2906" Ports [2, 1] Position [835, 841, 875, 894] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,53,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 53 53 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 53 53 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[31.55 31.55 36." "55 31.55 36.55 36.55 36.55 31.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[26.55 26.55 31.55 31.55 26." "55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[21.55 21.55 26.55 26.55 21.55 ],[1 1 1 ]);\npa" "tch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[16.55 16.55 21.55 16.55 21.55 21.55 16.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('a" "nd');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical4" SID "2907" Ports [2, 1] Position [920, 800, 955, 895] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,95,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 95 95 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 95 95 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[52.55 52.55 57." "55 52.55 57.55 57.55 57.55 52.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[47.55 47.55 52.55 52.55 47." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[42.55 42.55 47.55 47.55 42.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[37.55 37.55 42.55 37.55 42.55 42.55 37.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('o" "r');\nfprintf('','COMMENT: end icon text');" Port { PortNumber 1 Name "SIGNAL_Sym" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Logical5" SID "2908" Ports [2, 1] Position [840, 981, 880, 1034] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,53,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 53 53 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 53 53 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[31.55 31.55 36." "55 31.55 36.55 36.55 36.55 31.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[26.55 26.55 31.55 31.55 26." "55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[21.55 21.55 26.55 26.55 21.55 ],[1 1 1 ]);\npa" "tch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[16.55 16.55 21.55 16.55 21.55 21.55 16.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('a" "nd');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical6" SID "2909" Ports [2, 1] Position [920, 927, 955, 1038] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,111,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 111 111 0 ],[0.77 0.82 0" ".91 ]);\nplot([0 35 35 0 0 ],[0 0 111 111 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[60.55 60.55" " 65.55 60.55 65.55 65.55 65.55 60.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[55.55 55.55 60.55 60.55" " 55.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[50.55 50.55 55.55 55.55 50.55 ],[1 1 1 ]);" "\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[45.55 45.55 50.55 45.55 50.55 50.55 45.55 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');dis" "p('or');\nfprintf('','COMMENT: end icon text');" Port { PortNumber 1 Name "QBPSK_Sym" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Logical7" SID "2910" Ports [2, 1] Position [840, 926, 880, 979] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,53,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 53 53 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 53 53 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[31.55 31.55 36." "55 31.55 36.55 36.55 36.55 31.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[26.55 26.55 31.55 31.55 26." "55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[21.55 21.55 26.55 26.55 21.55 ],[1 1 1 ]);\npa" "tch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[16.55 16.55 21.55 16.55 21.55 21.55 16.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('a" "nd');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register" SID "2911" Ports [2, 1] Position [490, 500, 540, 580] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "50,80,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 80 80 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 50 50 0 0 ],[0 0 80 80 0 ]);\npatch([9.425 19.54 26.54 33.54 40.54 26.54 16.425 9.425 ],[47.77 47.7" "7 54.77 47.77 54.77 54.77 54.77 47.77 ],[1 1 1 ]);\npatch([16.425 26.54 19.54 9.425 16.425 ],[40.77 40.77 47.77 47" ".77 40.77 ],[0.931 0.946 0.973 ]);\npatch([9.425 19.54 26.54 16.425 9.425 ],[33.77 33.77 40.77 40.77 33.77 ],[1 1 " "1 ]);\npatch([16.425 40.54 33.54 26.54 19.54 9.425 16.425 ],[26.77 26.77 33.77 26.77 33.77 33.77 26.77 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');" "\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "2912" Ports [2, 1] Position [490, 590, 540, 670] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "50,80,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 80 80 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 50 50 0 0 ],[0 0 80 80 0 ]);\npatch([9.425 19.54 26.54 33.54 40.54 26.54 16.425 9.425 ],[47.77 47.7" "7 54.77 47.77 54.77 54.77 54.77 47.77 ],[1 1 1 ]);\npatch([16.425 26.54 19.54 9.425 16.425 ],[40.77 40.77 47.77 47" ".77 40.77 ],[0.931 0.946 0.973 ]);\npatch([9.425 19.54 26.54 16.425 9.425 ],[33.77 33.77 40.77 40.77 33.77 ],[1 1 " "1 ]);\npatch([16.425 40.54 33.54 26.54 19.54 9.425 16.425 ],[26.77 26.77 33.77 26.77 33.77 33.77 26.77 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');" "\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational10" SID "2913" Ports [2, 1] Position [240, 840, 275, 875] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,35,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 35 35 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 35 35 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[22.55 22.55 27." "55 22.55 27.55 27.55 27.55 22.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[17.55 17.55 22.55 22.55 17." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[12.55 12.55 17.55 17.55 12.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[7.55 7.55 12.55 7.55 12.55 12.55 7.55 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input" "',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa = b','texmode','" "on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational2" SID "2914" Ports [2, 1] Position [405, 541, 440, 579] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,38,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 38 38 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 38 38 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[24.55 24.55 29." "55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[19.55 19.55 24.55 24.55 19." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input" "',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa = b','texmode','" "on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational3" SID "2915" Ports [2, 1] Position [240, 875, 275, 910] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,35,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 35 35 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 35 35 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[22.55 22.55 27." "55 22.55 27.55 27.55 27.55 22.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[17.55 17.55 22.55 22.55 17." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[12.55 12.55 17.55 17.55 12.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[7.55 7.55 12.55 7.55 12.55 12.55 7.55 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input" "',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa = b','texmode','" "on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational7" SID "2916" Ports [2, 1] Position [240, 755, 275, 790] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "ab" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,35,2,1,white,blue,0,b5131c97,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 35 35 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 35 35 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[22.55" " 22.55 27.55 22.55 27.55 27.55 27.55 22.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[17.55 17.55 22" ".55 22.55 17.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[12.55 12.55 17.55 17.55 12.55 " "],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[7.55 7.55 12.55 7.55 12.55 12.55 7.55 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bla" "ck');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output'," "1,'\\bfa > b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational2" SID "2942" Ports [2, 1] Position [250, 396, 285, 434] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,38,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 38 38 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 38 38 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[24.55" " 24.55 29.55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[19.55 19.55 24" ".55 24.55 19.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[14.55 14.55 19.55 19.55 14.55 " "],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bla" "ck');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output'," "1,'\\bfa = b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational3" SID "2943" Ports [2, 1] Position [720, 235, 755, 270] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,35,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 35 35 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 35 35 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[22.55" " 22.55 27.55 22.55 27.55 27.55 27.55 22.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[17.55 17.55 22" ".55 22.55 17.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[12.55 12.55 17.55 17.55 12.55 " "],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[7.55 7.55 12.55 7.55 12.55 12.55 7.55 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bla" "ck');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output'," "1,'\\bfa = b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational4" SID "2944" Ports [2, 1] Position [720, 280, 755, 315] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,35,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 35 35 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 35 35 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[22.55" " 22.55 27.55 22.55 27.55 27.55 27.55 22.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[17.55 17.55 22" ".55 22.55 17.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[12.55 12.55 17.55 17.55 12.55 " "],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[7.55 7.55 12.55 7.55 12.55 12.55 7.55 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bla" "ck');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output'," "1,'\\bfa = b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational5" SID "2945" Ports [2, 1] Position [575, 845, 610, 880] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a>b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,35,2,1,white,blue,0,b5131c97,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 35 35 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 35 35 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[22.55" " 22.55 27.55 22.55 27.55 27.55 27.55 22.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[17.55 17.55 22" ".55 22.55 17.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[12.55 12.55 17.55 17.55 12.55 " "],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[7.55 7.55 12.55 7.55 12.55 12.55 7.55 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bla" "ck');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output'," "1,'\\bfa > b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational6" SID "2946" Ports [2, 1] Position [575, 790, 610, 825] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a>b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,35,2,1,white,blue,0,b5131c97,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 35 35 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 35 35 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[22.55" " 22.55 27.55 22.55 27.55 27.55 27.55 22.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[17.55 17.55 22" ".55 22.55 17.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[12.55 12.55 17.55 17.55 12.55 " "],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[7.55 7.55 12.55 7.55 12.55 12.55 7.55 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bla" "ck');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output'," "1,'\\bfa > b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "SC Sym Map 11a" SID "2947" Ports [1, 1] Position [560, 445, 615, 485] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/ROM" SourceType "Xilinx Single Port Read-Only Memory Block" depth "MAX_NUM_SC" initVector "sc_data_sym_map_11a_bool" distributed_mem "Distributed memory" rst off init_reg "0" en off latency "0" gui_display_data_type "Boolean" arith_type "Boolean" n_bits "ceil(log2(MAX_NUM_SC))+1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" dbl_ovrd off optimize "Area" use_rpm on xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "sprom" sg_icon_stat "55,40,1,1,white,blue,0,eff69a7e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 40 40 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 40 40 0 ]);\npatch([15.875 23.1 28.1 33.1 38.1 28.1 20.875 15.875 ],[25." "55 25.55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([20.875 28.1 23.1 15.875 20.875 ],[20.55 20.55" " 25.55 25.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([15.875 23.1 28.1 20.875 15.875 ],[15.55 15.55 20.55 20.55 1" "5.55 ],[1 1 1 ]);\npatch([20.875 38.1 33.1 28.1 23.1 15.875 20.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55" " ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n" "color('black');port_label('input',1,'addr');\n\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "SC Sym Map 11n/ac" SID "2948" Ports [1, 1] Position [560, 500, 615, 540] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/ROM" SourceType "Xilinx Single Port Read-Only Memory Block" depth "MAX_NUM_SC" initVector "sc_data_sym_map_11n_bool" distributed_mem "Distributed memory" rst off init_reg "0" en off latency "0" gui_display_data_type "Boolean" arith_type "Boolean" n_bits "ceil(log2(MAX_NUM_SC))+1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" dbl_ovrd off optimize "Area" use_rpm on xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "sprom" sg_icon_stat "55,40,1,1,white,blue,0,eff69a7e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 40 40 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 40 40 0 ]);\npatch([15.875 23.1 28.1 33.1 38.1 28.1 20.875 15.875 ],[25." "55 25.55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([20.875 28.1 23.1 15.875 20.875 ],[20.55 20.55" " 25.55 25.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([15.875 23.1 28.1 20.875 15.875 ],[15.55 15.55 20.55 20.55 1" "5.55 ],[1 1 1 ]);\npatch([20.875 38.1 33.1 28.1 23.1 15.875 20.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55" " ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n" "color('black');port_label('input',1,'addr');\n\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Data I" SID "2949" Position [1095, 118, 1125, 132] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Outport Name "Data Q" SID "2950" Position [1095, 133, 1125, 147] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "data_sc" SID "2951" Position [1135, 458, 1165, 472] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "Demod cfg" SID "2952" Position [1135, 658, 1165, 672] Port "4" IconDisplay "Port number" } Block { BlockType Outport Name "Reset Demod" SID "2953" Position [890, 793, 920, 807] Port "5" IconDisplay "Port number" } Block { BlockType Outport Name "Start Decoder" SID "2954" Position [890, 858, 920, 872] Port "6" IconDisplay "Port number" } Line { SrcBlock "sc_ind" SrcPort 1 Points [50, 0] Branch { Points [300, 0] Branch { DstBlock "SC Sym Map 11a" DstPort 1 } Branch { Points [0, 55] Branch { DstBlock "SC Sym Map 11n/ac" DstPort 1 } Branch { Points [0, 120] DstBlock "Demod Config" DstPort 1 } } } Branch { Points [0, -40] DstBlock "Relational2" DstPort 2 } } Line { SrcBlock "SC Sym Map 11a" SrcPort 1 DstBlock "Mux" DstPort 2 } Line { SrcBlock "iq_valid" SrcPort 1 DstBlock "Convert" DstPort 1 } Line { SrcBlock "Convert" SrcPort 1 Points [670, 0; 0, -95] DstBlock "Logical" DstPort 3 } Line { SrcBlock "Mux" SrcPort 1 DstBlock "Logical" DstPort 2 } Line { SrcBlock "SC Sym Map 11n/ac" SrcPort 1 DstBlock "Mux" DstPort 3 } Line { SrcBlock "Register" SrcPort 1 Points [165, 0] Branch { Points [0, -70] DstBlock "Logical2" DstPort 2 } Branch { DstBlock "Logical3" DstPort 1 } } Line { SrcBlock "Logical" SrcPort 1 DstBlock "data_sc" DstPort 1 } Line { SrcBlock "Constant3" SrcPort 1 DstBlock "Relational3" DstPort 1 } Line { SrcBlock "Constant4" SrcPort 1 Points [5, 0] Branch { DstBlock "Relational4" DstPort 1 } Branch { Points [0, 140] DstBlock "Relational1" DstPort 2 } } Line { SrcBlock "Sym ind" SrcPort 1 Points [20, 0] Branch { Points [165, 0] Branch { DstBlock "Relational3" DstPort 2 } Branch { Points [0, 45] Branch { DstBlock "Relational4" DstPort 2 } Branch { Points [0, 110] DstBlock "Relational1" DstPort 1 } } } Branch { Points [0, 410] Branch { Points [0, 130] Branch { Points [0, 55] DstBlock "Relational5" DstPort 1 } Branch { DstBlock "Relational6" DstPort 1 } } Branch { DstBlock "Demod Config" DstPort 2 } } } Line { SrcBlock "Relational3" SrcPort 1 Points [45, 0] DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Relational4" SrcPort 1 DstBlock "Logical1" DstPort 2 } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Logical2" DstPort 1 } Line { SrcBlock "Logical2" SrcPort 1 Points [15, 0; 0, 145] DstBlock "Logical" DstPort 1 } Line { SrcBlock "Logical3" SrcPort 1 DstBlock "Mux" DstPort 1 } Line { SrcBlock "Relational1" SrcPort 1 DstBlock "Logical3" DstPort 2 } Line { SrcBlock "Eq I" SrcPort 1 DstBlock "Data I" DstPort 1 } Line { SrcBlock "Eq Q" SrcPort 1 DstBlock "Data Q" DstPort 1 } Line { SrcBlock "From" SrcPort 1 DstBlock "Register" DstPort 1 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Relational2" DstPort 1 } Line { SrcBlock "Relational2" SrcPort 1 DstBlock "Register" DstPort 2 } Line { SrcBlock "Constant2" SrcPort 1 DstBlock "Relational6" DstPort 2 } Line { SrcBlock "Relational6" SrcPort 1 DstBlock "Posedge1" DstPort 1 } Line { SrcBlock "Constant5" SrcPort 1 DstBlock "Relational5" DstPort 2 } Line { SrcBlock "Relational5" SrcPort 1 DstBlock "Posedge" DstPort 1 } Line { SrcBlock "Posedge1" SrcPort 1 DstBlock "Logical4" DstPort 2 } Line { SrcBlock "Posedge" SrcPort 1 DstBlock "Start Decoder" DstPort 1 } Line { SrcBlock "Logical4" SrcPort 1 DstBlock "Reset Demod" DstPort 1 } Line { SrcBlock "Reset" SrcPort 1 DstBlock "Logical4" DstPort 1 } Line { SrcBlock "Concat" SrcPort 1 DstBlock "Demod cfg" DstPort 1 } Line { SrcBlock "Demod Config" SrcPort 2 DstBlock "Concat" DstPort 1 } Line { SrcBlock "Demod Config" SrcPort 3 DstBlock "Concat" DstPort 2 } Annotation { Name "Syms 5 and 6 have no data in 11n/ac\n(HT STF, HTLTF)" Position [706, 201] } Annotation { Name "OFDM Symbols in 11a/g:\n0: LTF (BPSK)\n1: LTF (BPSK)\n2: SIG (BPSK) 48sc\n3-N: Data 48sc" Position [514, 983] HorizontalAlignment "left" } Annotation { Name "OFDM Symbols in 11n SISO:\n0: L-LTF (BPSK)\n1: L-LTF (BPSK) \n2: L-SIG (BPSK) 48sc\n3: HT-SIG1 (QB" "PSK) 48sc\n4: HT-SIG2 (QBPSK) 48sc\n5: HT-STF\n6: HT-LFT1\n7-N: Data 52sc" Position [664, 1008] HorizontalAlignment "left" } Annotation { Name "OFDM Symbols in 11ac SISO:\n0: L-LTF (BPSK)\n1: L-LTF (BPSK)\n2: L-SIG (BPSK) 48sc\n3: VHT-SIGA1 (" "BPSK) 48sc\n4: VHT-SIGA2 (QBPSK) 48sc\n5: VHT-STF\n6: VHT-LFT1\n7: VHT-SIGB 52sc\n8-N: Data 52sc" Position [839, 1023] HorizontalAlignment "left" } Annotation { Name "Lookup tables below are 0 latency - add delays to I/Q here\nif that changes in a future rev" Position [786, 105] } Annotation { Name "Capture current PHY mode decision\nat start of each OFDM sym (subcarrier 0)\nEvery PHY mode sets s" "ubcarrier 0 to 0,\nso one cycle ambiguity about PHY mode\nat subcarrier 0 is no problem" Position [98, 311] HorizontalAlignment "left" } } } Block { BlockType Outport Name "OFDM Data" SID "3005" Position [1360, 113, 1390, 127] IconDisplay "Port number" } Block { BlockType Outport Name " Reset" SID "3006" Position [1360, 188, 1390, 202] Port "2" IconDisplay "Port number" } Line { SrcBlock "Decode" SrcPort 2 DstBlock "Descramble" DstPort 2 } Line { SrcBlock "sym_ind" SrcPort 1 DstBlock "Subcarrier Map &\nDemod Control" DstPort 5 } Line { SrcBlock "Decode" SrcPort 3 DstBlock "Descramble" DstPort 3 } Line { SrcBlock "Decode" SrcPort 4 DstBlock "Descramble" DstPort 4 } Line { SrcBlock "Decode" SrcPort 1 DstBlock "Descramble" DstPort 1 } Line { SrcBlock "Bus\nCreator" SrcPort 1 DstBlock "OFDM Data" DstPort 1 } Line { Name "byte" Labels [0, 0] SrcBlock "Descramble" SrcPort 1 DstBlock "Bus\nCreator" DstPort 1 } Line { Name "byte_valid" Labels [0, 0] SrcBlock "Descramble" SrcPort 2 DstBlock "Bus\nCreator" DstPort 2 } Line { Name "byte_index" Labels [0, 0] SrcBlock "Descramble" SrcPort 3 DstBlock "Bus\nCreator" DstPort 3 } Line { Name "last_byte" Labels [0, 0] SrcBlock "Descramble" SrcPort 4 DstBlock "Bus\nCreator" DstPort 4 } Line { SrcBlock "Decode" SrcPort 5 Points [10, 0] Branch { DstBlock " Reset" DstPort 1 } Branch { Points [0, 35; -800, 0; 0, -30] DstBlock "Logical5" DstPort 2 } } Line { SrcBlock "Logical5" SrcPort 1 Points [25, 0] Branch { Points [0, -45] DstBlock "Subcarrier Map &\nDemod Control" DstPort 6 } Branch { DstBlock "Decode" DstPort 5 } } Line { SrcBlock "From1" SrcPort 1 DstBlock "Logical5" DstPort 1 } Line { SrcBlock "iq_valid" SrcPort 1 DstBlock "Subcarrier Map &\nDemod Control" DstPort 3 } Line { SrcBlock "sc_ind" SrcPort 1 DstBlock "Subcarrier Map &\nDemod Control" DstPort 4 } Line { SrcBlock "Eq I" SrcPort 1 DstBlock "Subcarrier Map &\nDemod Control" DstPort 1 } Line { SrcBlock "Eq Q" SrcPort 1 DstBlock "Subcarrier Map &\nDemod Control" DstPort 2 } Line { SrcBlock "Subcarrier Map &\nDemod Control" SrcPort 6 Points [5, 0; 0, 15] DstBlock "Decode" DstPort 4 } Line { SrcBlock "Subcarrier Map &\nDemod Control" SrcPort 1 DstBlock "Soft Demod" DstPort 1 } Line { SrcBlock "Subcarrier Map &\nDemod Control" SrcPort 2 DstBlock "Soft Demod" DstPort 2 } Line { SrcBlock "Subcarrier Map &\nDemod Control" SrcPort 3 DstBlock "Soft Demod" DstPort 3 } Line { SrcBlock "Subcarrier Map &\nDemod Control" SrcPort 4 DstBlock "Soft Demod" DstPort 4 } Line { SrcBlock "De-Interleave" SrcPort 1 DstBlock "Decode" DstPort 1 } Line { SrcBlock "De-Interleave" SrcPort 2 DstBlock "Decode" DstPort 2 } Line { SrcBlock "De-Interleave" SrcPort 3 DstBlock "Decode" DstPort 3 } Line { SrcBlock "Subcarrier Map &\nDemod Control" SrcPort 5 DstBlock "De-Interleave" DstPort 5 } Line { SrcBlock "Soft Demod" SrcPort 1 DstBlock "De-Interleave" DstPort 1 } Line { SrcBlock "Soft Demod" SrcPort 2 DstBlock "De-Interleave" DstPort 2 } Line { SrcBlock "Soft Demod" SrcPort 3 DstBlock "De-Interleave" DstPort 3 } Line { SrcBlock "Soft Demod" SrcPort 4 DstBlock "De-Interleave" DstPort 4 } } } Block { BlockType SubSystem Name "EDK Processor" SID "14899" Ports [] Position [697, 288, 740, 336] CopyFcn "xlProcBlockCopyCallback(gcbh);xlBlockMoveCallback(gcbh);" DeleteFcn "xlDestroyGui(gcbh);" LoadFcn "xlBlockLoadCallback(gcbh);" ModelCloseFcn "xlDestroyGui(gcbh);" PreSaveFcn "xlBlockPreSaveCallback(gcbh);" PostSaveFcn "xlBlockPostSaveCallback(gcbh);" DestroyFcn "xlDestroyGui(gcbh);" OpenFcn "bh=gcbh;xlProcBlockCallbacks('populatesharedmemorylistbox',bh);xlOpenGui(bh, 'edkprocessor_gui.x" "ml', @xlProcBlockEnablement, @xlProcBlockAction);" CloseFcn "xlDestroyGui(gcbh);" MoveFcn "xlBlockMoveCallback(gcbh);" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskType "Xilinx EDK Processor Block" MaskDescription "Xilinx EDK Processor" MaskHelp "eval('');xlDoc('-book','sysgen','-topic','EDK_Processor');" MaskPromptString "Configure Processor for|XPS Project| |Available Memories| | |Bus Type|Base Address| |Loc" "k| |Dual Clocks| |Register Read-Back|Constraint File| |Inherit Device Type|Initial Program| |Enable Co-Debug wit" "h Xilinx SDK (Beta)| | | | | | | | | | | | | | | | " MaskStyleString "popup(EDK pcore generation|HDL netlisting),edit,edit,edit,edit,edit,popup(AXI|PLB),edit,e" "dit,checkbox,edit,checkbox,edit,checkbox,edit,edit,checkbox,edit,edit,checkbox,edit,edit,edit,edit,edit,edit,edi" "t,edit,edit,edit,edit,edit,edit,edit,edit,edit" MaskVariables "mode=&1;xmp=&2;MemVisToProc=&3;AvailableMemories=&4;portInterfaceTable=&5;bus_type_sgadvanc" "ed=&6;bus_type=&7;baseaddr=&8;baseaddr_lock_sgadvanced=&9;baseaddr_lock=@10;dual_clock_sgadvanced=&11;dual_clock" "=@12;reg_readback_sgadvanced=&13;reg_readback=@14;ucf_file=&15;inheritDeviceType_sgadvanced=&16;inheritDeviceTyp" "e=@17;elf_file=&18;codebug_sgadvanced=&19;codebug=@20;clock_name=&21;internalPortList=&22;resetPolarity=&23;memx" "table=&24;procinfo=&25;memmapdirty=&26;blockname=&27;xpsintstyle=&28;has_advanced_control=@29;sggui_pos=&30;bloc" "k_type=&31;block_version=&32;sg_icon_stat=&33;sg_mask_display=&34;sg_list_contents=&35;sg_blockgui_xml=&36;" MaskTunableValueString "on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on," "on,on,on,on,on,on,on" MaskCallbackString "|||||||||||||||||||||||||||||||||||" MaskEnableString "on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,o" "n,on,on,on,on,on,on" MaskVisibilityString "on,on,off,on,on,off,on,on,off,on,off,on,off,on,on,off,on,on,off,on,off,off,off,off,off," "off,off,off,off,off,off,off,off,off,off,off" MaskToolTipString "on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on," "on,on,on,on,on,on,on" MaskInitialization "try\n tmp_gcb = gcb;\n tmp_gcbh = gcbh;\n if (strcmp('SysGenIndex',get_param(bdroot(" "tmp_gcbh),'tag')) && ~isempty(regexp(bdroot(tmp_gcb), '^xbs', 'once')))\n return;\n end;\n xlMungeMaskParam" "s;\n\n block_type='edkprocessor';\n\n serialized_declarations = '{''block_type''=>''String''}';\n xledkproces" "sor_init();\n ptable_ = xlblockprep(get_param(tmp_gcb, 'MaskWSVariables'));\n try\n xlBlockMoveCallback(tmp" "_gcbh);\n catch \n clear global xl_updateicon_recursion_guard;\n end;\ncatch\n global dbgsysgen;\n if(~i" "sempty(dbgsysgen) && dbgsysgen)\n e = regexprep(lasterr, '\\n', '\\nError: ');\n disp(['Error: While runni" "ng MaskInit code on block ' tmp_gcb ': ' e]);\n error(e);\n end\nend\n" MaskSelfModifiable on MaskDisplay "fprintf('','COMMENT: begin icon graphics');\npatch([0 43 43 0 0 ],[0 0 48 48 0 ],[0.77 0.82 0" ".91 ]);\nplot([0 43 43 0 0 ],[0 0 48 48 0 ]);\npatch([7.65 16.32 22.32 28.32 34.32 22.32 13.65 7.65 ],[30.66 30." "66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([13.65 22.32 16.32 7.65 13.65 ],[24.66 24.66 30.66 30" ".66 24.66 ],[0.931 0.946 0.973 ]);\npatch([7.65 16.32 22.32 13.65 7.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1 1" " ]);\npatch([13.65 34.32 28.32 22.32 16.32 7.65 13.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ndisp('');\n\nfp" "rintf('','COMMENT: end icon text');" MaskIconFrame off MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "EDK pcore generation||

<<RSSI_THRESH>>
<<CONFIG>>
<<DSSS_RX_CONFIG>>
<<PKT_BUF_SEL>>
<<PKTDET_AUTOCORR_CONFIG>>
<<FEC_CONFIG>>
<<Control>>
<<LTS_Corr_PeakType_Th" "resh>>
<<C" "HAN_EST_SMOOTHING>>
<<LTS_Corr_Thresh>>
<<PKTDET_DSSS_CONFIG>>
<<LTS_Corr_Config>>
<<PHY_CCA_CONFIG>>
<<PKTBUF_MAX_WRITE_ADDR>>
<<FFT_Config>>
<<PKTDET_RSSI_CONFIG>>
<" "div> <<RX_PKT_RSSI_CD>>
<<RX_PKT_AGC_GAIN" "S>>
<<RX_P" "KT_RSSI_AB>>
<" ";<CFO_EST_TIME_DOMAIN>>
<<Status>>
<<RAMS_ADDR_WREN>>
<<MASK_1_RAM_WR_DATA>>
<<TARGET_RAM_WR_DATA>>
<<PKT_DET_COUNT_DSSS>>
<<PKT_DET_COUNT_OFDM>>
<<RXIQ_MAG_SUM_RFA>>
||{'exposed'=>[],'portdir'=>[],'portname'=>[],'shortname'=>[]}||AXI|0x80000000||off||on||on|||off" "|||on|plb|{}|0|{'mladdr'=>[0.00000000000000000,1.00000000000000000,2.00000000000000000,3.00000000000000000,4.000" "00000000000000,5.00000000000000000,6.00000000000000000,7.00000000000000000,8.00000000000000000,9.000000000000000" "00,10.00000000000000000,11.00000000000000000,12.00000000000000000,13.00000000000000000,14.00000000000000000,15.0" "0000000000000000,0.00000000000000000,1.00000000000000000,2.00000000000000000,3.00000000000000000,4.0000000000000" "0000,16.00000000000000000,17.00000000000000000,18.00000000000000000,5.00000000000000000,6.00000000000000000,7.00" "000000000000000],'mlist'=>['wlan_phy_rx_pmd/Registers/From Register8','wlan_phy_rx_pmd/Registers/From Register7'" ",'wlan_phy_rx_pmd/Registers/From Register6','wlan_phy_rx_pmd/Registers/From Register5','wlan_phy_rx_pmd/Register" "s/From Register4','wlan_phy_rx_pmd/Registers/From Register3','wlan_phy_rx_pmd/Registers/From Register2','wlan_ph" "y_rx_pmd/Registers/From Register16','wlan_phy_rx_pmd/Registers/From Register15','wlan_phy_rx_pmd/Registers/From " "Register14','wlan_phy_rx_pmd/Registers/From Register13','wlan_phy_rx_pmd/Registers/From Register12','wlan_phy_rx" "_pmd/Registers/From Register11','wlan_phy_rx_pmd/Registers/From Register10','wlan_phy_rx_pmd/Registers/From Regi" "ster1','wlan_phy_rx_pmd/Registers/From Register','wlan_phy_rx_pmd/Registers/To Register4','wlan_phy_rx_pmd/Regis" "ters/To Register3','wlan_phy_rx_pmd/Registers/To Register2','wlan_phy_rx_pmd/Registers/To Register1','wlan_phy_r" "x_pmd/Registers/To Register','wlan_phy_rx_pmd/Registers/From Register9','wlan_phy_rx_pmd/Registers/From Register" "18','wlan_phy_rx_pmd/Registers/From Register17','wlan_phy_rx_pmd/Registers/To Register6','wlan_phy_rx_pmd/Regist" "ers/To Register5','wlan_phy_rx_pmd/Registers/To Register7'],'mlname'=>['\\\\'RSSI_THRESH\\\\'','\\\\'CONFIG\\\\'" "','\\\\'DSSS_RX_CONFIG\\\\'','\\\\'PKT_BUF_SEL\\\\'','\\\\'PKTDET_AUTOCORR_CONFIG\\\\'','\\\\'FEC_CONFIG\\\\'','" "\\\\'Control\\\\'','\\\\'LTS_Corr_PeakType_Thresh\\\\'','\\\\'CHAN_EST_SMOOTHING\\\\'','\\\\'LTS_Corr_Thresh\\\\" "'','\\\\'PKTDET_DSSS_CONFIG\\\\'','\\\\'LTS_Corr_Config\\\\'','\\\\'PHY_CCA_CONFIG\\\\'','\\\\'PKTBUF_MAX_WRITE_" "ADDR\\\\'','\\\\'FFT_Config\\\\'','\\\\'PKTDET_RSSI_CONFIG\\\\'','\\\\'RX_PKT_RSSI_CD\\\\'','\\\\'RX_PKT_AGC_GAI" "NS\\\\'','\\\\'RX_PKT_RSSI_AB\\\\'','\\\\'CFO_EST_TIME_DOMAIN\\\\'','\\\\'Status\\\\'','\\\\'RAMS_ADDR_WREN\\\\'" "','\\\\'MASK_1_RAM_WR_DATA\\\\'','\\\\'TARGET_RAM_WR_DATA\\\\'','\\\\'PKT_DET_COUNT_DSSS\\\\'','\\\\'PKT_DET_COU" "NT_OFDM\\\\'','\\\\'RXIQ_MAG_SUM_RFA\\\\''],'mlstate'=>[0.00000000000000000,0.00000000000000000,0.00000000000000" "000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.000000" "00000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000," "0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.0000000000" "0000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00" "000000000000000,0.00000000000000000]}|{}|off||default|0|-1,-1,-1,-1|edkprocessor|2.7|43,48,-1,-1,white,blue,0,07" "734,right,,[ ],[ ]|fprintf('','COMMENT: begin icon graphics');\npatch([0 43 43 0 0 ],[0 0 48 48 0 ],[0.77 0.82 0" ".91 ]);\nplot([0 43 43 0 0 ],[0 0 48 48 0 ]);\npatch([7.65 16.32 22.32 28.32 34.32 22.32 13.65 7.65 ],[30.66 30." "66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([13.65 22.32 16.32 7.65 13.65 ],[24.66 24.66 30.66 30" ".66 24.66 ],[0.931 0.946 0.973 ]);\npatch([7.65 16.32 22.32 13.65 7.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1 1" " ]);\npatch([13.65 34.32 28.32 22.32 16.32 7.65 13.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nfprintf('','COM" "MENT: end icon text');|{'table'=>{'AvailableMemories'=>'popup()'}}|" System { Name "EDK Processor" Location [514, 91, 900, 269] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" SIDHighWatermark "584" Block { BlockType Reference Name "AXI_ARESETN" SID "14899:514" Ports [1, 1] Position [75, 30, 140, 50] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to Xilinx" " fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top level input p" "orts." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "16" bin_pt "14" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "xlGetNormalizedPeriod()" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end ic" "on text');" } Block { BlockType Constant Name "Constant" SID "14899:513" Position [20, 30, 40, 50] ShowName off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Constant Name "Constant1" SID "14899:515" Position [20, 80, 40, 100] ShowName off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Constant Name "Constant10" SID "14899:533" Position [20, 525, 40, 545] ShowName off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Constant Name "Constant11" SID "14899:535" Position [20, 570, 40, 590] ShowName off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Constant Name "Constant12" SID "14899:537" Position [20, 620, 40, 640] ShowName off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Constant Name "Constant13" SID "14899:539" Position [20, 670, 40, 690] ShowName off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Constant Name "Constant14" SID "14899:541" Position [20, 720, 40, 740] ShowName off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Constant Name "Constant15" SID "14899:543" Position [20, 770, 40, 790] ShowName off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Constant Name "Constant16" SID "14899:545" Position [20, 820, 40, 840] ShowName off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Constant Name "Constant17" SID "14899:547" Position [20, 870, 40, 890] ShowName off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Constant Name "Constant18" SID "14899:549" Position [20, 920, 40, 940] ShowName off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Constant Name "Constant19" SID "14899:551" Position [20, 965, 40, 985] ShowName off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Constant Name "Constant2" SID "14899:517" Position [20, 130, 40, 150] ShowName off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Constant Name "Constant20" SID "14899:553" Position [20, 1015, 40, 1035] ShowName off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Constant Name "Constant21" SID "14899:555" Position [20, 1065, 40, 1085] ShowName off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Constant Name "Constant22" SID "14899:557" Position [20, 1115, 40, 1135] ShowName off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Constant Name "Constant23" SID "14899:559" Position [20, 1165, 40, 1185] ShowName off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Constant Name "Constant24" SID "14899:561" Position [20, 1215, 40, 1235] ShowName off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Constant Name "Constant3" SID "14899:519" Position [20, 180, 40, 200] ShowName off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Constant Name "Constant4" SID "14899:521" Position [20, 225, 40, 245] ShowName off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Constant Name "Constant5" SID "14899:523" Position [20, 275, 40, 295] ShowName off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Constant Name "Constant6" SID "14899:525" Position [20, 325, 40, 345] ShowName off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Constant Name "Constant7" SID "14899:527" Position [20, 375, 40, 395] ShowName off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Constant Name "Constant8" SID "14899:529" Position [20, 425, 40, 445] ShowName off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Constant Name "Constant9" SID "14899:531" Position [20, 475, 40, 495] ShowName off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "From Register" SID "14899:486" Ports [0, 1] Position [75, 1262, 135, 1318] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'RX_PKT_RSSI_CD'" init "0" period "xlGetNormalizedPeriod()" ownership "Owned and initialized elsewhere" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "fromreg" sg_icon_stat "60,56,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8" "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ]," "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20." "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf(" "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'d" "out');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "From Register1" SID "14899:487" Ports [0, 1] Position [75, 1352, 135, 1408] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'RX_PKT_AGC_GAINS'" init "0" period "xlGetNormalizedPeriod()" ownership "Owned and initialized elsewhere" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "fromreg" sg_icon_stat "60,56,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8" "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ]," "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20." "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf(" "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'d" "out');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "From Register2" SID "14899:488" Ports [0, 1] Position [75, 1437, 135, 1493] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'RX_PKT_RSSI_AB'" init "0" period "xlGetNormalizedPeriod()" ownership "Owned and initialized elsewhere" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "fromreg" sg_icon_stat "60,56,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8" "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ]," "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20." "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf(" "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'d" "out');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "From Register3" SID "14899:489" Ports [0, 1] Position [75, 1522, 135, 1578] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'CFO_EST_TIME_DOMAIN'" init "0" period "xlGetNormalizedPeriod()" ownership "Owned and initialized elsewhere" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "fromreg" sg_icon_stat "60,56,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8" "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ]," "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20." "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf(" "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'d" "out');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "From Register4" SID "14899:490" Ports [0, 1] Position [75, 1612, 135, 1668] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'Status'" init "0" period "xlGetNormalizedPeriod()" ownership "Owned and initialized elsewhere" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "fromreg" sg_icon_stat "60,56,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8" "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ]," "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20." "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf(" "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'d" "out');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "From Register5" SID "14899:491" Ports [0, 1] Position [75, 1697, 135, 1753] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'PKT_DET_COUNT_DSSS'" init "0" period "xlGetNormalizedPeriod()" ownership "Owned and initialized elsewhere" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "fromreg" sg_icon_stat "60,56,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8" "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ]," "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20." "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf(" "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'d" "out');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "From Register6" SID "14899:492" Ports [0, 1] Position [75, 1782, 135, 1838] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'PKT_DET_COUNT_OFDM'" init "0" period "xlGetNormalizedPeriod()" ownership "Owned and initialized elsewhere" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "fromreg" sg_icon_stat "60,56,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8" "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ]," "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20." "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf(" "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'d" "out');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "From Register7" SID "14899:493" Ports [0, 1] Position [75, 1872, 135, 1928] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'RXIQ_MAG_SUM_RFA'" init "0" period "xlGetNormalizedPeriod()" ownership "Owned and initialized elsewhere" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "fromreg" sg_icon_stat "60,56,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8" "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ]," "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20." "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf(" "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'d" "out');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "S_AXI_ARADDR" SID "14899:516" Ports [1, 1] Position [75, 80, 140, 100] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to Xilinx" " fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top level input p" "orts." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "xlGetNormalizedPeriod()" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end ic" "on text');" } Block { BlockType Reference Name "S_AXI_ARBURST" SID "14899:518" Ports [1, 1] Position [75, 130, 140, 150] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to Xilinx" " fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top level input p" "orts." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "xlGetNormalizedPeriod()" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end ic" "on text');" } Block { BlockType Reference Name "S_AXI_ARCACHE" SID "14899:520" Ports [1, 1] Position [75, 180, 140, 200] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to Xilinx" " fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top level input p" "orts." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "4" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "xlGetNormalizedPeriod()" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end ic" "on text');" } Block { BlockType Reference Name "S_AXI_ARID" SID "14899:522" Ports [1, 1] Position [75, 225, 140, 245] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to Xilinx" " fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top level input p" "orts." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "8" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "xlGetNormalizedPeriod()" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end ic" "on text');" } Block { BlockType Reference Name "S_AXI_ARLEN" SID "14899:524" Ports [1, 1] Position [75, 275, 140, 295] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to Xilinx" " fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top level input p" "orts." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "8" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "xlGetNormalizedPeriod()" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end ic" "on text');" } Block { BlockType Reference Name "S_AXI_ARLOCK" SID "14899:526" Ports [1, 1] Position [75, 325, 140, 345] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to Xilinx" " fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top level input p" "orts." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "xlGetNormalizedPeriod()" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end ic" "on text');" } Block { BlockType Reference Name "S_AXI_ARPROT" SID "14899:528" Ports [1, 1] Position [75, 375, 140, 395] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to Xilinx" " fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top level input p" "orts." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "xlGetNormalizedPeriod()" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end ic" "on text');" } Block { BlockType Reference Name "S_AXI_ARREADY" SID "14899:564" Ports [1, 1] Position [450, 40, 510, 60] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" " ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "S_AXI_ARSIZE" SID "14899:530" Ports [1, 1] Position [75, 425, 140, 445] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to Xilinx" " fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top level input p" "orts." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "xlGetNormalizedPeriod()" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end ic" "on text');" } Block { BlockType Reference Name "S_AXI_ARVALID" SID "14899:532" Ports [1, 1] Position [75, 475, 140, 495] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to Xilinx" " fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top level input p" "orts." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "16" bin_pt "14" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "xlGetNormalizedPeriod()" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end ic" "on text');" } Block { BlockType Reference Name "S_AXI_AWADDR" SID "14899:534" Ports [1, 1] Position [75, 525, 140, 545] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to Xilinx" " fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top level input p" "orts." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "xlGetNormalizedPeriod()" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end ic" "on text');" } Block { BlockType Reference Name "S_AXI_AWBURST" SID "14899:536" Ports [1, 1] Position [75, 570, 140, 590] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to Xilinx" " fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top level input p" "orts." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "xlGetNormalizedPeriod()" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end ic" "on text');" } Block { BlockType Reference Name "S_AXI_AWCACHE" SID "14899:538" Ports [1, 1] Position [75, 620, 140, 640] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to Xilinx" " fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top level input p" "orts." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "4" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "xlGetNormalizedPeriod()" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end ic" "on text');" } Block { BlockType Reference Name "S_AXI_AWID" SID "14899:540" Ports [1, 1] Position [75, 670, 140, 690] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to Xilinx" " fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top level input p" "orts." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "8" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "xlGetNormalizedPeriod()" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end ic" "on text');" } Block { BlockType Reference Name "S_AXI_AWLEN" SID "14899:542" Ports [1, 1] Position [75, 720, 140, 740] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to Xilinx" " fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top level input p" "orts." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "8" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "xlGetNormalizedPeriod()" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end ic" "on text');" } Block { BlockType Reference Name "S_AXI_AWLOCK" SID "14899:544" Ports [1, 1] Position [75, 770, 140, 790] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to Xilinx" " fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top level input p" "orts." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "xlGetNormalizedPeriod()" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end ic" "on text');" } Block { BlockType Reference Name "S_AXI_AWPROT" SID "14899:546" Ports [1, 1] Position [75, 820, 140, 840] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to Xilinx" " fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top level input p" "orts." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "xlGetNormalizedPeriod()" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end ic" "on text');" } Block { BlockType Reference Name "S_AXI_AWREADY" SID "14899:566" Ports [1, 1] Position [450, 90, 510, 110] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" " ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "S_AXI_AWSIZE" SID "14899:548" Ports [1, 1] Position [75, 870, 140, 890] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to Xilinx" " fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top level input p" "orts." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "xlGetNormalizedPeriod()" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end ic" "on text');" } Block { BlockType Reference Name "S_AXI_AWVALID" SID "14899:550" Ports [1, 1] Position [75, 920, 140, 940] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to Xilinx" " fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top level input p" "orts." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "16" bin_pt "14" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "xlGetNormalizedPeriod()" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end ic" "on text');" } Block { BlockType Reference Name "S_AXI_BID" SID "14899:568" Ports [1, 1] Position [450, 140, 510, 160] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" " ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "S_AXI_BREADY" SID "14899:552" Ports [1, 1] Position [75, 965, 140, 985] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to Xilinx" " fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top level input p" "orts." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "16" bin_pt "14" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "xlGetNormalizedPeriod()" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end ic" "on text');" } Block { BlockType Reference Name "S_AXI_BRESP" SID "14899:570" Ports [1, 1] Position [450, 190, 510, 210] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" " ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "S_AXI_BVALID" SID "14899:572" Ports [1, 1] Position [450, 240, 510, 260] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" " ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "S_AXI_RDATA" SID "14899:574" Ports [1, 1] Position [450, 290, 510, 310] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" " ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "S_AXI_RID" SID "14899:576" Ports [1, 1] Position [450, 340, 510, 360] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" " ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "S_AXI_RLAST" SID "14899:578" Ports [1, 1] Position [450, 385, 510, 405] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" " ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "S_AXI_RREADY" SID "14899:554" Ports [1, 1] Position [75, 1015, 140, 1035] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to Xilinx" " fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top level input p" "orts." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "16" bin_pt "14" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "xlGetNormalizedPeriod()" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end ic" "on text');" } Block { BlockType Reference Name "S_AXI_RRESP" SID "14899:580" Ports [1, 1] Position [450, 435, 510, 455] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" " ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "S_AXI_RVALID" SID "14899:582" Ports [1, 1] Position [450, 485, 510, 505] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" " ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "S_AXI_WDATA" SID "14899:556" Ports [1, 1] Position [75, 1065, 140, 1085] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to Xilinx" " fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top level input p" "orts." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "xlGetNormalizedPeriod()" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end ic" "on text');" } Block { BlockType Reference Name "S_AXI_WLAST" SID "14899:558" Ports [1, 1] Position [75, 1115, 140, 1135] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to Xilinx" " fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top level input p" "orts." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "16" bin_pt "14" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "xlGetNormalizedPeriod()" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end ic" "on text');" } Block { BlockType Reference Name "S_AXI_WREADY" SID "14899:584" Ports [1, 1] Position [450, 535, 510, 555] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" " ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "S_AXI_WSTRB" SID "14899:560" Ports [1, 1] Position [75, 1165, 140, 1185] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to Xilinx" " fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top level input p" "orts." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "4" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "xlGetNormalizedPeriod()" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end ic" "on text');" } Block { BlockType Reference Name "S_AXI_WVALID" SID "14899:562" Ports [1, 1] Position [75, 1215, 140, 1235] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to Xilinx" " fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top level input p" "orts." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "16" bin_pt "14" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "xlGetNormalizedPeriod()" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end ic" "on text');" } Block { BlockType Terminator Name "Terminator" SID "14899:563" Position [545, 40, 565, 60] ShowName off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Terminator Name "Terminator1" SID "14899:565" Position [545, 90, 565, 110] ShowName off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Terminator Name "Terminator10" SID "14899:583" Position [545, 535, 565, 555] ShowName off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Terminator Name "Terminator2" SID "14899:567" Position [545, 140, 565, 160] ShowName off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Terminator Name "Terminator3" SID "14899:569" Position [545, 190, 565, 210] ShowName off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Terminator Name "Terminator4" SID "14899:571" Position [545, 240, 565, 260] ShowName off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Terminator Name "Terminator5" SID "14899:573" Position [545, 290, 565, 310] ShowName off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Terminator Name "Terminator6" SID "14899:575" Position [545, 340, 565, 360] ShowName off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Terminator Name "Terminator7" SID "14899:577" Position [545, 385, 565, 405] ShowName off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Terminator Name "Terminator8" SID "14899:579" Position [545, 435, 565, 455] ShowName off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Terminator Name "Terminator9" SID "14899:581" Position [545, 485, 565, 505] ShowName off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "To Register" SID "14899:494" Ports [2, 1] Position [450, 587, 510, 643] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'RSSI_THRESH'" init "0" ownership "Owned and initialized elsewhere" explicit_data_type on gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "toreg" sg_icon_stat "60,56,2,1,white,blue,0,10ab453e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8" "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ]," "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20." "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf(" "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'di" "n');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMEN" "T: end icon text');" } Block { BlockType Reference Name "To Register1" SID "14899:495" Ports [2, 1] Position [450, 672, 510, 728] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'CONFIG'" init "0" ownership "Owned and initialized elsewhere" explicit_data_type on gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "toreg" sg_icon_stat "60,56,2,1,white,blue,0,10ab453e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8" "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ]," "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20." "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf(" "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'di" "n');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMEN" "T: end icon text');" } Block { BlockType Reference Name "To Register10" SID "14899:504" Ports [2, 1] Position [450, 1452, 510, 1508] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'PKTDET_DSSS_CONFIG'" init "0" ownership "Owned and initialized elsewhere" explicit_data_type on gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "toreg" sg_icon_stat "60,56,2,1,white,blue,0,10ab453e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8" "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ]," "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20." "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf(" "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'di" "n');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMEN" "T: end icon text');" } Block { BlockType Reference Name "To Register11" SID "14899:505" Ports [2, 1] Position [450, 1537, 510, 1593] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'LTS_Corr_Config'" init "0" ownership "Owned and initialized elsewhere" explicit_data_type on gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "toreg" sg_icon_stat "60,56,2,1,white,blue,0,10ab453e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8" "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ]," "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20." "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf(" "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'di" "n');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMEN" "T: end icon text');" } Block { BlockType Reference Name "To Register12" SID "14899:506" Ports [2, 1] Position [450, 1627, 510, 1683] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'PHY_CCA_CONFIG'" init "0" ownership "Owned and initialized elsewhere" explicit_data_type on gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "toreg" sg_icon_stat "60,56,2,1,white,blue,0,10ab453e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8" "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ]," "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20." "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf(" "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'di" "n');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMEN" "T: end icon text');" } Block { BlockType Reference Name "To Register13" SID "14899:507" Ports [2, 1] Position [450, 1712, 510, 1768] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'PKTBUF_MAX_WRITE_ADDR'" init "0" ownership "Owned and initialized elsewhere" explicit_data_type on gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "toreg" sg_icon_stat "60,56,2,1,white,blue,0,10ab453e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8" "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ]," "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20." "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf(" "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'di" "n');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMEN" "T: end icon text');" } Block { BlockType Reference Name "To Register14" SID "14899:508" Ports [2, 1] Position [450, 1797, 510, 1853] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'FFT_Config'" init "0" ownership "Owned and initialized elsewhere" explicit_data_type on gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "toreg" sg_icon_stat "60,56,2,1,white,blue,0,10ab453e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8" "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ]," "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20." "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf(" "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'di" "n');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMEN" "T: end icon text');" } Block { BlockType Reference Name "To Register15" SID "14899:509" Ports [2, 1] Position [450, 1887, 510, 1943] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'PKTDET_RSSI_CONFIG'" init "0" ownership "Owned and initialized elsewhere" explicit_data_type on gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "toreg" sg_icon_stat "60,56,2,1,white,blue,0,10ab453e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8" "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ]," "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20." "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf(" "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'di" "n');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMEN" "T: end icon text');" } Block { BlockType Reference Name "To Register16" SID "14899:510" Ports [2, 1] Position [450, 1972, 510, 2028] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'RAMS_ADDR_WREN'" init "0" ownership "Owned and initialized elsewhere" explicit_data_type on gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "toreg" sg_icon_stat "60,56,2,1,white,blue,0,10ab453e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8" "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ]," "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20." "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf(" "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'di" "n');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMEN" "T: end icon text');" } Block { BlockType Reference Name "To Register17" SID "14899:511" Ports [2, 1] Position [450, 2057, 510, 2113] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'MASK_1_RAM_WR_DATA'" init "0" ownership "Owned and initialized elsewhere" explicit_data_type on gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "toreg" sg_icon_stat "60,56,2,1,white,blue,0,10ab453e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8" "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ]," "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20." "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf(" "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'di" "n');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMEN" "T: end icon text');" } Block { BlockType Reference Name "To Register18" SID "14899:512" Ports [2, 1] Position [450, 2147, 510, 2203] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'TARGET_RAM_WR_DATA'" init "0" ownership "Owned and initialized elsewhere" explicit_data_type on gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "toreg" sg_icon_stat "60,56,2,1,white,blue,0,10ab453e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8" "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ]," "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20." "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf(" "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'di" "n');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMEN" "T: end icon text');" } Block { BlockType Reference Name "To Register2" SID "14899:496" Ports [2, 1] Position [450, 757, 510, 813] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'DSSS_RX_CONFIG'" init "0" ownership "Owned and initialized elsewhere" explicit_data_type on gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "toreg" sg_icon_stat "60,56,2,1,white,blue,0,10ab453e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8" "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ]," "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20." "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf(" "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'di" "n');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMEN" "T: end icon text');" } Block { BlockType Reference Name "To Register3" SID "14899:497" Ports [2, 1] Position [450, 847, 510, 903] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'PKT_BUF_SEL'" init "0" ownership "Owned and initialized elsewhere" explicit_data_type on gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "toreg" sg_icon_stat "60,56,2,1,white,blue,0,10ab453e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8" "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ]," "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20." "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf(" "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'di" "n');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMEN" "T: end icon text');" } Block { BlockType Reference Name "To Register4" SID "14899:498" Ports [2, 1] Position [450, 932, 510, 988] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'PKTDET_AUTOCORR_CONFIG'" init "0" ownership "Owned and initialized elsewhere" explicit_data_type on gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "toreg" sg_icon_stat "60,56,2,1,white,blue,0,10ab453e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8" "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ]," "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20." "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf(" "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'di" "n');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMEN" "T: end icon text');" } Block { BlockType Reference Name "To Register5" SID "14899:499" Ports [2, 1] Position [450, 1017, 510, 1073] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'FEC_CONFIG'" init "0" ownership "Owned and initialized elsewhere" explicit_data_type on gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "toreg" sg_icon_stat "60,56,2,1,white,blue,0,10ab453e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8" "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ]," "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20." "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf(" "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'di" "n');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMEN" "T: end icon text');" } Block { BlockType Reference Name "To Register6" SID "14899:500" Ports [2, 1] Position [450, 1107, 510, 1163] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'Control'" init "0" ownership "Owned and initialized elsewhere" explicit_data_type on gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "toreg" sg_icon_stat "60,56,2,1,white,blue,0,10ab453e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8" "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ]," "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20." "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf(" "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'di" "n');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMEN" "T: end icon text');" } Block { BlockType Reference Name "To Register7" SID "14899:501" Ports [2, 1] Position [450, 1192, 510, 1248] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'LTS_Corr_PeakType_Thresh'" init "0" ownership "Owned and initialized elsewhere" explicit_data_type on gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "toreg" sg_icon_stat "60,56,2,1,white,blue,0,10ab453e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8" "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ]," "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20." "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf(" "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'di" "n');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMEN" "T: end icon text');" } Block { BlockType Reference Name "To Register8" SID "14899:502" Ports [2, 1] Position [450, 1277, 510, 1333] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'CHAN_EST_SMOOTHING'" init "0" ownership "Owned and initialized elsewhere" explicit_data_type on gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "toreg" sg_icon_stat "60,56,2,1,white,blue,0,10ab453e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8" "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ]," "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20." "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf(" "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'di" "n');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMEN" "T: end icon text');" } Block { BlockType Reference Name "To Register9" SID "14899:503" Ports [2, 1] Position [450, 1367, 510, 1423] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'LTS_Corr_Thresh'" init "0" ownership "Owned and initialized elsewhere" explicit_data_type on gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "toreg" sg_icon_stat "60,56,2,1,white,blue,0,10ab453e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8" "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ]," "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20." "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf(" "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'di" "n');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMEN" "T: end icon text');" } Block { BlockType Reference Name "memmap" SID "14899:485" Ports [52, 49] Position [170, 332, 420, 1898] LibraryVersion "1.2" SourceBlock "xbsEDKLib_r4/EDK Core" SourceType "Xilinx EDK Core Block" infoedit "For use with EDK Processor block." sim_method "Inactive" xl_use_area off xl_area "[0,0,0,0,0,0,0]" xmp "xmp" blockname "blockname" dual_clock "dual_clock" procinfo "procinfo" bus_type "bus_type" memxtable "memxtable" memmap_hdlcontent "library IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity axi_sgiface i" "s\n generic (\n -- AXI specific.\n -- TODO: need to figure out a way to pass these generics from o" "utside\n C_S_AXI_SUPPORT_BURST : integer := 0;\n -- TODO: fix the internal ID width to 8\n C" "_S_AXI_ID_WIDTH : integer := 8;\n C_S_AXI_DATA_WIDTH : integer := 32;\n C_S_AXI_ADDR_WIDT" "H : integer := 32;\n C_S_AXI_TOTAL_ADDR_LEN : integer := 12;\n C_S_AXI_LINEAR_ADDR_LEN : intege" "r := 8;\n C_S_AXI_BANK_ADDR_LEN : integer := 2;\n C_S_AXI_AWLEN_WIDTH : integer := 8;\n " "C_S_AXI_ARLEN_WIDTH : integer := 8\n );\n port (\n -- General.\n AXI_AClk : in std_lo" "gic;\n AXI_AResetN : in std_logic;\n -- not used\n AXI_Ce : in std_logic;\n \n " " -- AXI Port.\n S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);\n S_AXI_AWID" " : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);\n S_AXI_AWLEN : in std_logic_vector(C_S_AXI_AWLE" "N_WIDTH-1 downto 0);\n S_AXI_AWSIZE : in std_logic_vector(2 downto 0);\n S_AXI_AWBURST : in std_lo" "gic_vector(1 downto 0);\n S_AXI_AWLOCK : in std_logic_vector(1 downto 0);\n S_AXI_AWCACHE : in std" "_logic_vector(3 downto 0);\n S_AXI_AWPROT : in std_logic_vector(2 downto 0);\n S_AXI_AWVALID : in " "std_logic;\n S_AXI_AWREADY : out std_logic;\n \n S_AXI_WLAST : in std_logic;\n S_AXI" "_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);\n S_AXI_WSTRB : in std_logic_vector((C_S_" "AXI_DATA_WIDTH/8)-1 downto 0);\n S_AXI_WVALID : in std_logic;\n S_AXI_WREADY : out std_logic;\n " " \n S_AXI_BRESP : out std_logic_vector(1 downto 0);\n S_AXI_BID : out std_logic_vector(C_S_" "AXI_ID_WIDTH-1 downto 0);\n S_AXI_BVALID : out std_logic;\n S_AXI_BREADY : in std_logic;\n " "\n S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);\n S_AXI_ARID : in std_log" "ic_vector(C_S_AXI_ID_WIDTH-1 downto 0);\n S_AXI_ARLEN : in std_logic_vector(C_S_AXI_ARLEN_WIDTH-1 downto " "0);\n S_AXI_ARSIZE : in std_logic_vector(2 downto 0);\n S_AXI_ARBURST : in std_logic_vector(1 down" "to 0);\n S_AXI_ARLOCK : in std_logic_vector(1 downto 0);\n S_AXI_ARCACHE : in std_logic_vector(3 d" "ownto 0);\n S_AXI_ARPROT : in std_logic_vector(2 downto 0);\n S_AXI_ARVALID : in std_logic;\n " " S_AXI_ARREADY : out std_logic;\n \n -- 'From Register'\n -- 'RX_PKT_RSSI_CD'\n sm_RX" "_PKT_RSSI_CD_dout : in std_logic_vector(32-1 downto 0);\n -- 'RX_PKT_AGC_GAINS'\n sm_RX_PKT_AGC_GAINS" "_dout : in std_logic_vector(32-1 downto 0);\n -- 'RX_PKT_RSSI_AB'\n sm_RX_PKT_RSSI_AB_dout : in std_l" "ogic_vector(32-1 downto 0);\n -- 'CFO_EST_TIME_DOMAIN'\n sm_CFO_EST_TIME_DOMAIN_dout : in std_logic_v" "ector(32-1 downto 0);\n -- 'Status'\n sm_Status_dout : in std_logic_vector(32-1 downto 0);\n -" "- 'PKT_DET_COUNT_DSSS'\n sm_PKT_DET_COUNT_DSSS_dout : in std_logic_vector(32-1 downto 0);\n -- 'PKT_D" "ET_COUNT_OFDM'\n sm_PKT_DET_COUNT_OFDM_dout : in std_logic_vector(32-1 downto 0);\n -- 'RXIQ_MAG_SUM_" "RFA'\n sm_RXIQ_MAG_SUM_RFA_dout : in std_logic_vector(32-1 downto 0);\n -- 'To Register'\n -- " "'RSSI_THRESH'\n sm_RSSI_THRESH_dout : in std_logic_vector(32-1 downto 0);\n sm_RSSI_THRESH_din : out" " std_logic_vector(32-1 downto 0);\n sm_RSSI_THRESH_en : out std_logic;\n -- 'CONFIG'\n sm_CO" "NFIG_dout : in std_logic_vector(32-1 downto 0);\n sm_CONFIG_din : out std_logic_vector(32-1 downto 0);\n " " sm_CONFIG_en : out std_logic;\n -- 'DSSS_RX_CONFIG'\n sm_DSSS_RX_CONFIG_dout : in std_logic_ve" "ctor(32-1 downto 0);\n sm_DSSS_RX_CONFIG_din : out std_logic_vector(32-1 downto 0);\n sm_DSSS_RX_CON" "FIG_en : out std_logic;\n -- 'PKT_BUF_SEL'\n sm_PKT_BUF_SEL_dout : in std_logic_vector(32-1 downto " "0);\n sm_PKT_BUF_SEL_din : out std_logic_vector(32-1 downto 0);\n sm_PKT_BUF_SEL_en : out std_logi" "c;\n -- 'PKTDET_AUTOCORR_CONFIG'\n sm_PKTDET_AUTOCORR_CONFIG_dout : in std_logic_vector(32-1 downto 0" ");\n sm_PKTDET_AUTOCORR_CONFIG_din : out std_logic_vector(32-1 downto 0);\n sm_PKTDET_AUTOCORR_CONFI" "G_en : out std_logic;\n -- 'FEC_CONFIG'\n sm_FEC_CONFIG_dout : in std_logic_vector(32-1 downto 0);\n" " sm_FEC_CONFIG_din : out std_logic_vector(32-1 downto 0);\n sm_FEC_CONFIG_en : out std_logic;\n " " -- 'Control'\n sm_Control_dout : in std_logic_vector(32-1 downto 0);\n sm_Control_din : out std" "_logic_vector(32-1 downto 0);\n sm_Control_en : out std_logic;\n -- 'LTS_Corr_PeakType_Thresh'\n " " sm_LTS_Corr_PeakType_Thresh_dout : in std_logic_vector(32-1 downto 0);\n sm_LTS_Corr_PeakType_Thresh_di" "n : out std_logic_vector(32-1 downto 0);\n sm_LTS_Corr_PeakType_Thresh_en : out std_logic;\n -- 'C" "HAN_EST_SMOOTHING'\n sm_CHAN_EST_SMOOTHING_dout : in std_logic_vector(32-1 downto 0);\n sm_CHAN_EST_S" "MOOTHING_din : out std_logic_vector(32-1 downto 0);\n sm_CHAN_EST_SMOOTHING_en : out std_logic;\n " "-- 'LTS_Corr_Thresh'\n sm_LTS_Corr_Thresh_dout : in std_logic_vector(32-1 downto 0);\n sm_LTS_Corr_Th" "resh_din : out std_logic_vector(32-1 downto 0);\n sm_LTS_Corr_Thresh_en : out std_logic;\n -- 'PKT" "DET_DSSS_CONFIG'\n sm_PKTDET_DSSS_CONFIG_dout : in std_logic_vector(32-1 downto 0);\n sm_PKTDET_DSSS_" "CONFIG_din : out std_logic_vector(32-1 downto 0);\n sm_PKTDET_DSSS_CONFIG_en : out std_logic;\n --" " 'LTS_Corr_Config'\n sm_LTS_Corr_Config_dout : in std_logic_vector(32-1 downto 0);\n sm_LTS_Corr_Conf" "ig_din : out std_logic_vector(32-1 downto 0);\n sm_LTS_Corr_Config_en : out std_logic;\n -- 'PHY_C" "CA_CONFIG'\n sm_PHY_CCA_CONFIG_dout : in std_logic_vector(32-1 downto 0);\n sm_PHY_CCA_CONFIG_din : " "out std_logic_vector(32-1 downto 0);\n sm_PHY_CCA_CONFIG_en : out std_logic;\n -- 'PKTBUF_MAX_WRITE" "_ADDR'\n sm_PKTBUF_MAX_WRITE_ADDR_dout : in std_logic_vector(32-1 downto 0);\n sm_PKTBUF_MAX_WRITE_AD" "DR_din : out std_logic_vector(32-1 downto 0);\n sm_PKTBUF_MAX_WRITE_ADDR_en : out std_logic;\n -- " "'FFT_Config'\n sm_FFT_Config_dout : in std_logic_vector(32-1 downto 0);\n sm_FFT_Config_din : out st" "d_logic_vector(32-1 downto 0);\n sm_FFT_Config_en : out std_logic;\n -- 'PKTDET_RSSI_CONFIG'\n " " sm_PKTDET_RSSI_CONFIG_dout : in std_logic_vector(32-1 downto 0);\n sm_PKTDET_RSSI_CONFIG_din : out std_l" "ogic_vector(32-1 downto 0);\n sm_PKTDET_RSSI_CONFIG_en : out std_logic;\n -- 'RAMS_ADDR_WREN'\n " " sm_RAMS_ADDR_WREN_dout : in std_logic_vector(32-1 downto 0);\n sm_RAMS_ADDR_WREN_din : out std_logic_ve" "ctor(32-1 downto 0);\n sm_RAMS_ADDR_WREN_en : out std_logic;\n -- 'MASK_1_RAM_WR_DATA'\n sm_" "MASK_1_RAM_WR_DATA_dout : in std_logic_vector(32-1 downto 0);\n sm_MASK_1_RAM_WR_DATA_din : out std_logic_v" "ector(32-1 downto 0);\n sm_MASK_1_RAM_WR_DATA_en : out std_logic;\n -- 'TARGET_RAM_WR_DATA'\n " " sm_TARGET_RAM_WR_DATA_dout : in std_logic_vector(32-1 downto 0);\n sm_TARGET_RAM_WR_DATA_din : out std_lo" "gic_vector(32-1 downto 0);\n sm_TARGET_RAM_WR_DATA_en : out std_logic;\n -- 'From FIFO'\n --" " 'To FIFO'\n -- 'Shared Memory'\n\n S_AXI_RLAST : out std_logic;\n S_AXI_RID : out std_l" "ogic_vector(C_S_AXI_ID_WIDTH-1 downto 0);\n S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto" " 0);\n S_AXI_RRESP : out std_logic_vector(1 downto 0);\n S_AXI_RVALID : out std_logic;\n S_" "AXI_RREADY : in std_logic\n );\nend entity axi_sgiface;\n\narchitecture IMP of axi_sgiface is\n\n-- Internal s" "ignals for write channel.\nsignal S_AXI_BVALID_i : std_logic;\nsignal S_AXI_BID_i : std_logic_vector" "(C_S_AXI_ID_WIDTH-1 downto 0);\nsignal S_AXI_WREADY_i : std_logic;\n \n-- Internal signals for read channels" ".\nsignal S_AXI_ARLEN_i : std_logic_vector(C_S_AXI_ARLEN_WIDTH-1 downto 0);\nsignal S_AXI_RLAST_i : s" "td_logic;\nsignal S_AXI_RREADY_i : std_logic;\nsignal S_AXI_RVALID_i : std_logic;\nsignal S_AXI_RDATA_i" " : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);\nsignal S_AXI_RID_i : std_logic_vector(C_S_AXI_" "ID_WIDTH-1 downto 0);\n\n-- for read channel\nsignal read_bank_addr_i : std_logic_vector(C_S_AXI_BANK_ADDR_LEN-" "1 downto 0);\nsignal read_linear_addr_i : std_logic_vector(C_S_AXI_LINEAR_ADDR_LEN-1 downto 0);\n-- for write cha" "nnel\nsignal write_bank_addr_i : std_logic_vector(C_S_AXI_BANK_ADDR_LEN-1 downto 0);\nsignal write_linear_addr_i" " : std_logic_vector(C_S_AXI_LINEAR_ADDR_LEN-1 downto 0);\n\nsignal reg_bank_out_i : std_logic_vector(C_S_AXI" "_DATA_WIDTH-1 downto 0);\nsignal fifo_bank_out_i : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);\nsignal sh" "mem_bank_out_i : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);\n \n-- 'From Register'\n-- 'RX_PKT_RSSI_CD" "'\nsignal sm_RX_PKT_RSSI_CD_dout_i : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);\n-- 'RX_PKT_AGC_GAINS'\nsign" "al sm_RX_PKT_AGC_GAINS_dout_i : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);\n-- 'RX_PKT_RSSI_AB'\nsignal sm_R" "X_PKT_RSSI_AB_dout_i : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);\n-- 'CFO_EST_TIME_DOMAIN'\nsignal sm_CFO_E" "ST_TIME_DOMAIN_dout_i : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);\n-- 'Status'\nsignal sm_Status_dout_i : " "std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);\n-- 'PKT_DET_COUNT_DSSS'\nsignal sm_PKT_DET_COUNT_DSSS_dout_i : s" "td_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);\n-- 'PKT_DET_COUNT_OFDM'\nsignal sm_PKT_DET_COUNT_OFDM_dout_i : st" "d_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);\n-- 'RXIQ_MAG_SUM_RFA'\nsignal sm_RXIQ_MAG_SUM_RFA_dout_i : std_log" "ic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);\n-- 'To Register'\n-- 'RSSI_THRESH'\nsignal sm_RSSI_THRESH_din_i : std_" "logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);\nsignal sm_RSSI_THRESH_en_i : std_logic;\nsignal sm_RSSI_THRESH_dou" "t_i : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);\n-- 'CONFIG'\nsignal sm_CONFIG_din_i : std_logic_vector(C" "_S_AXI_DATA_WIDTH-1 downto 0);\nsignal sm_CONFIG_en_i : std_logic;\nsignal sm_CONFIG_dout_i : std_logic_vector(" "C_S_AXI_DATA_WIDTH-1 downto 0);\n-- 'DSSS_RX_CONFIG'\nsignal sm_DSSS_RX_CONFIG_din_i : std_logic_vector(C_S_AXI_D" "ATA_WIDTH-1 downto 0);\nsignal sm_DSSS_RX_CONFIG_en_i : std_logic;\nsignal sm_DSSS_RX_CONFIG_dout_i : std_logic" "_vector(C_S_AXI_DATA_WIDTH-1 downto 0);\n-- 'PKT_BUF_SEL'\nsignal sm_PKT_BUF_SEL_din_i : std_logic_vector(C_S_AXI" "_DATA_WIDTH-1 downto 0);\nsignal sm_PKT_BUF_SEL_en_i : std_logic;\nsignal sm_PKT_BUF_SEL_dout_i : std_logic_vec" "tor(C_S_AXI_DATA_WIDTH-1 downto 0);\n-- 'PKTDET_AUTOCORR_CONFIG'\nsignal sm_PKTDET_AUTOCORR_CONFIG_din_i : std_lo" "gic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);\nsignal sm_PKTDET_AUTOCORR_CONFIG_en_i : std_logic;\nsignal sm_PKTDET" "_AUTOCORR_CONFIG_dout_i : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);\n-- 'FEC_CONFIG'\nsignal sm_FEC_CONFIG_" "din_i : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);\nsignal sm_FEC_CONFIG_en_i : std_logic;\nsignal sm_FE" "C_CONFIG_dout_i : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);\n-- 'Control'\nsignal sm_Control_din_i : std_" "logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);\nsignal sm_Control_en_i : std_logic;\nsignal sm_Control_dout_i : s" "td_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);\n-- 'LTS_Corr_PeakType_Thresh'\nsignal sm_LTS_Corr_PeakType_Thresh_" "din_i : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);\nsignal sm_LTS_Corr_PeakType_Thresh_en_i : std_logic;" "\nsignal sm_LTS_Corr_PeakType_Thresh_dout_i : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);\n-- 'CHAN_EST_SMOOT" "HING'\nsignal sm_CHAN_EST_SMOOTHING_din_i : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);\nsignal sm_CHAN_EST_" "SMOOTHING_en_i : std_logic;\nsignal sm_CHAN_EST_SMOOTHING_dout_i : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto" " 0);\n-- 'LTS_Corr_Thresh'\nsignal sm_LTS_Corr_Thresh_din_i : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);\ns" "ignal sm_LTS_Corr_Thresh_en_i : std_logic;\nsignal sm_LTS_Corr_Thresh_dout_i : std_logic_vector(C_S_AXI_DATA_WI" "DTH-1 downto 0);\n-- 'PKTDET_DSSS_CONFIG'\nsignal sm_PKTDET_DSSS_CONFIG_din_i : std_logic_vector(C_S_AXI_DATA_WID" "TH-1 downto 0);\nsignal sm_PKTDET_DSSS_CONFIG_en_i : std_logic;\nsignal sm_PKTDET_DSSS_CONFIG_dout_i : std_logi" "c_vector(C_S_AXI_DATA_WIDTH-1 downto 0);\n-- 'LTS_Corr_Config'\nsignal sm_LTS_Corr_Config_din_i : std_logic_vecto" "r(C_S_AXI_DATA_WIDTH-1 downto 0);\nsignal sm_LTS_Corr_Config_en_i : std_logic;\nsignal sm_LTS_Corr_Config_dout_i" " : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);\n-- 'PHY_CCA_CONFIG'\nsignal sm_PHY_CCA_CONFIG_din_i : std_l" "ogic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);\nsignal sm_PHY_CCA_CONFIG_en_i : std_logic;\nsignal sm_PHY_CCA_CONFI" "G_dout_i : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);\n-- 'PKTBUF_MAX_WRITE_ADDR'\nsignal sm_PKTBUF_MAX_WRIT" "E_ADDR_din_i : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);\nsignal sm_PKTBUF_MAX_WRITE_ADDR_en_i : std_lo" "gic;\nsignal sm_PKTBUF_MAX_WRITE_ADDR_dout_i : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);\n-- 'FFT_Config'\n" "signal sm_FFT_Config_din_i : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);\nsignal sm_FFT_Config_en_i : std" "_logic;\nsignal sm_FFT_Config_dout_i : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);\n-- 'PKTDET_RSSI_CONFIG'\n" "signal sm_PKTDET_RSSI_CONFIG_din_i : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);\nsignal sm_PKTDET_RSSI_CONF" "IG_en_i : std_logic;\nsignal sm_PKTDET_RSSI_CONFIG_dout_i : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);\n-" "- 'RAMS_ADDR_WREN'\nsignal sm_RAMS_ADDR_WREN_din_i : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);\nsignal sm_" "RAMS_ADDR_WREN_en_i : std_logic;\nsignal sm_RAMS_ADDR_WREN_dout_i : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downt" "o 0);\n-- 'MASK_1_RAM_WR_DATA'\nsignal sm_MASK_1_RAM_WR_DATA_din_i : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto" " 0);\nsignal sm_MASK_1_RAM_WR_DATA_en_i : std_logic;\nsignal sm_MASK_1_RAM_WR_DATA_dout_i : std_logic_vector(C_" "S_AXI_DATA_WIDTH-1 downto 0);\n-- 'TARGET_RAM_WR_DATA'\nsignal sm_TARGET_RAM_WR_DATA_din_i : std_logic_vector(C_S" "_AXI_DATA_WIDTH-1 downto 0);\nsignal sm_TARGET_RAM_WR_DATA_en_i : std_logic;\nsignal sm_TARGET_RAM_WR_DATA_dout_" "i : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);\n-- 'From FIFO'\n-- 'To FIFO'\n-- 'Shared Memory'\n\ntype t_r" "ead_state is (IDLE, READ_PREP, READ_DATA);\nsignal read_state : t_read_state;\n\ntype t_write_state is (IDLE, WRITE" "_DATA, WRITE_RESPONSE);\nsignal write_state : t_write_state;\n\ntype t_memmap_state is (READ, WRITE);\nsignal memma" "p_state : t_memmap_state;\n\nconstant C_READ_PREP_DELAY : std_logic_vector(1 downto 0) := \"11\";\n\nsignal read_pr" "ep_counter : std_logic_vector(1 downto 0);\nsignal read_addr_counter : std_logic_vector(C_S_AXI_ARLEN_WIDTH-1 downt" "o 0);\nsignal read_data_counter : std_logic_vector(C_S_AXI_ARLEN_WIDTH-1 downto 0);\n\n-- enable of shared BRAMs\ns" "ignal s_shram_en : std_logic;\n\nsignal write_addr_valid : std_logic;\nsignal write_ready : std_logic;\n\n-- 're' o" "f From/To FIFOs\nsignal s_fifo_re : std_logic;\n-- 'we' of To FIFOs\nsignal s_fifo_we : std_logic;\n\nbegin\n\n-- e" "nable for 'Shared Memory' blocks\n\n-- conversion to match with the data bus width\n-- 'From Register'\n-- 'RX_PKT_" "RSSI_CD'\ngen_sm_RX_PKT_RSSI_CD_dout_i: if (32 < C_S_AXI_DATA_WIDTH) generate\n sm_RX_PKT_RSSI_CD_dout_i(C_S_AXI" "_DATA_WIDTH-1 downto 32) <= (others => '0');\nend generate gen_sm_RX_PKT_RSSI_CD_dout_i;\nsm_RX_PKT_RSSI_CD_dout_i(" "32-1 downto 0) <= sm_RX_PKT_RSSI_CD_dout;\n-- 'RX_PKT_AGC_GAINS'\ngen_sm_RX_PKT_AGC_GAINS_dout_i: if (32 < C_S_AXI_" "DATA_WIDTH) generate\n sm_RX_PKT_AGC_GAINS_dout_i(C_S_AXI_DATA_WIDTH-1 downto 32) <= (others => '0');\nend gener" "ate gen_sm_RX_PKT_AGC_GAINS_dout_i;\nsm_RX_PKT_AGC_GAINS_dout_i(32-1 downto 0) <= sm_RX_PKT_AGC_GAINS_dout;\n-- 'RX" "_PKT_RSSI_AB'\ngen_sm_RX_PKT_RSSI_AB_dout_i: if (32 < C_S_AXI_DATA_WIDTH) generate\n sm_RX_PKT_RSSI_AB_dout_i(C_" "S_AXI_DATA_WIDTH-1 downto 32) <= (others => '0');\nend generate gen_sm_RX_PKT_RSSI_AB_dout_i;\nsm_RX_PKT_RSSI_AB_do" "ut_i(32-1 downto 0) <= sm_RX_PKT_RSSI_AB_dout;\n-- 'CFO_EST_TIME_DOMAIN'\ngen_sm_CFO_EST_TIME_DOMAIN_dout_i: if (32" " < C_S_AXI_DATA_WIDTH) generate\n sm_CFO_EST_TIME_DOMAIN_dout_i(C_S_AXI_DATA_WIDTH-1 downto 32) <= (others => '0" "');\nend generate gen_sm_CFO_EST_TIME_DOMAIN_dout_i;\nsm_CFO_EST_TIME_DOMAIN_dout_i(32-1 downto 0) <= sm_CFO_EST_TI" "ME_DOMAIN_dout;\n-- 'Status'\ngen_sm_Status_dout_i: if (32 < C_S_AXI_DATA_WIDTH) generate\n sm_Status_dout_i(C_S" "_AXI_DATA_WIDTH-1 downto 32) <= (others => '0');\nend generate gen_sm_Status_dout_i;\nsm_Status_dout_i(32-1 downto " "0) <= sm_Status_dout;\n-- 'PKT_DET_COUNT_DSSS'\ngen_sm_PKT_DET_COUNT_DSSS_dout_i: if (32 < C_S_AXI_DATA_WIDTH) gene" "rate\n sm_PKT_DET_COUNT_DSSS_dout_i(C_S_AXI_DATA_WIDTH-1 downto 32) <= (others => '0');\nend generate gen_sm_PKT" "_DET_COUNT_DSSS_dout_i;\nsm_PKT_DET_COUNT_DSSS_dout_i(32-1 downto 0) <= sm_PKT_DET_COUNT_DSSS_dout;\n-- 'PKT_DET_CO" "UNT_OFDM'\ngen_sm_PKT_DET_COUNT_OFDM_dout_i: if (32 < C_S_AXI_DATA_WIDTH) generate\n sm_PKT_DET_COUNT_OFDM_dout_" "i(C_S_AXI_DATA_WIDTH-1 downto 32) <= (others => '0');\nend generate gen_sm_PKT_DET_COUNT_OFDM_dout_i;\nsm_PKT_DET_C" "OUNT_OFDM_dout_i(32-1 downto 0) <= sm_PKT_DET_COUNT_OFDM_dout;\n-- 'RXIQ_MAG_SUM_RFA'\ngen_sm_RXIQ_MAG_SUM_RFA_dout" "_i: if (32 < C_S_AXI_DATA_WIDTH) generate\n sm_RXIQ_MAG_SUM_RFA_dout_i(C_S_AXI_DATA_WIDTH-1 downto 32) <= (other" "s => '0');\nend generate gen_sm_RXIQ_MAG_SUM_RFA_dout_i;\nsm_RXIQ_MAG_SUM_RFA_dout_i(32-1 downto 0) <= sm_RXIQ_MAG_" "SUM_RFA_dout;\n-- 'To Register'\n-- 'RSSI_THRESH'\nsm_RSSI_THRESH_din <= sm_RSSI_THRESH_din_i(32-1 downto 0);\n" "sm_RSSI_THRESH_en <= sm_RSSI_THRESH_en_i;\ngen_sm_RSSI_THRESH_dout_i: if (32 < C_S_AXI_DATA_WIDTH) generate\n " " sm_RSSI_THRESH_dout_i(C_S_AXI_DATA_WIDTH-1 downto 32) <= (others => '0');\nend generate gen_sm_RSSI_THRESH_dout_" "i;\nsm_RSSI_THRESH_dout_i(32-1 downto 0) <= sm_RSSI_THRESH_dout;\n-- 'CONFIG'\nsm_CONFIG_din <= sm_CONFIG_din_i" "(32-1 downto 0);\nsm_CONFIG_en <= sm_CONFIG_en_i;\ngen_sm_CONFIG_dout_i: if (32 < C_S_AXI_DATA_WIDTH) generate" "\n sm_CONFIG_dout_i(C_S_AXI_DATA_WIDTH-1 downto 32) <= (others => '0');\nend generate gen_sm_CONFIG_dout_i;\nsm_" "CONFIG_dout_i(32-1 downto 0) <= sm_CONFIG_dout;\n-- 'DSSS_RX_CONFIG'\nsm_DSSS_RX_CONFIG_din <= sm_DSSS_RX_CONFI" "G_din_i(32-1 downto 0);\nsm_DSSS_RX_CONFIG_en <= sm_DSSS_RX_CONFIG_en_i;\ngen_sm_DSSS_RX_CONFIG_dout_i: if (32" " < C_S_AXI_DATA_WIDTH) generate\n sm_DSSS_RX_CONFIG_dout_i(C_S_AXI_DATA_WIDTH-1 downto 32) <= (others => '0');\n" "end generate gen_sm_DSSS_RX_CONFIG_dout_i;\nsm_DSSS_RX_CONFIG_dout_i(32-1 downto 0) <= sm_DSSS_RX_CONFIG_dout;\n-- " "'PKT_BUF_SEL'\nsm_PKT_BUF_SEL_din <= sm_PKT_BUF_SEL_din_i(32-1 downto 0);\nsm_PKT_BUF_SEL_en <= sm_PKT_BUF" "_SEL_en_i;\ngen_sm_PKT_BUF_SEL_dout_i: if (32 < C_S_AXI_DATA_WIDTH) generate\n sm_PKT_BUF_SEL_dout_i(C_S_AXI_DAT" "A_WIDTH-1 downto 32) <= (others => '0');\nend generate gen_sm_PKT_BUF_SEL_dout_i;\nsm_PKT_BUF_SEL_dout_i(32-1 downt" "o 0) <= sm_PKT_BUF_SEL_dout;\n-- 'PKTDET_AUTOCORR_CONFIG'\nsm_PKTDET_AUTOCORR_CONFIG_din <= sm_PKTDET_AUTOCORR_" "CONFIG_din_i(32-1 downto 0);\nsm_PKTDET_AUTOCORR_CONFIG_en <= sm_PKTDET_AUTOCORR_CONFIG_en_i;\ngen_sm_PKTDET_A" "UTOCORR_CONFIG_dout_i: if (32 < C_S_AXI_DATA_WIDTH) generate\n sm_PKTDET_AUTOCORR_CONFIG_dout_i(C_S_AXI_DATA_WID" "TH-1 downto 32) <= (others => '0');\nend generate gen_sm_PKTDET_AUTOCORR_CONFIG_dout_i;\nsm_PKTDET_AUTOCORR_CONFIG_" "dout_i(32-1 downto 0) <= sm_PKTDET_AUTOCORR_CONFIG_dout;\n-- 'FEC_CONFIG'\nsm_FEC_CONFIG_din <= sm_FEC_CONFIG_d" "in_i(32-1 downto 0);\nsm_FEC_CONFIG_en <= sm_FEC_CONFIG_en_i;\ngen_sm_FEC_CONFIG_dout_i: if (32 < C_S_AXI_DATA" "_WIDTH) generate\n sm_FEC_CONFIG_dout_i(C_S_AXI_DATA_WIDTH-1 downto 32) <= (others => '0');\nend generate gen_sm" "_FEC_CONFIG_dout_i;\nsm_FEC_CONFIG_dout_i(32-1 downto 0) <= sm_FEC_CONFIG_dout;\n-- 'Control'\nsm_Control_din <" "= sm_Control_din_i(32-1 downto 0);\nsm_Control_en <= sm_Control_en_i;\ngen_sm_Control_dout_i: if (32 < C_S_AXI" "_DATA_WIDTH) generate\n sm_Control_dout_i(C_S_AXI_DATA_WIDTH-1 downto 32) <= (others => '0');\nend generate gen_" "sm_Control_dout_i;\nsm_Control_dout_i(32-1 downto 0) <= sm_Control_dout;\n-- 'LTS_Corr_PeakType_Thresh'\nsm_LTS_Cor" "r_PeakType_Thresh_din <= sm_LTS_Corr_PeakType_Thresh_din_i(32-1 downto 0);\nsm_LTS_Corr_PeakType_Thresh_en " " <= sm_LTS_Corr_PeakType_Thresh_en_i;\ngen_sm_LTS_Corr_PeakType_Thresh_dout_i: if (32 < C_S_AXI_DATA_WIDTH) generat" "e\n sm_LTS_Corr_PeakType_Thresh_dout_i(C_S_AXI_DATA_WIDTH-1 downto 32) <= (others => '0');\nend generate gen_sm_" "LTS_Corr_PeakType_Thresh_dout_i;\nsm_LTS_Corr_PeakType_Thresh_dout_i(32-1 downto 0) <= sm_LTS_Corr_PeakType_Thresh_" "dout;\n-- 'CHAN_EST_SMOOTHING'\nsm_CHAN_EST_SMOOTHING_din <= sm_CHAN_EST_SMOOTHING_din_i(32-1 downto 0);\nsm_CH" "AN_EST_SMOOTHING_en <= sm_CHAN_EST_SMOOTHING_en_i;\ngen_sm_CHAN_EST_SMOOTHING_dout_i: if (32 < C_S_AXI_DATA_WI" "DTH) generate\n sm_CHAN_EST_SMOOTHING_dout_i(C_S_AXI_DATA_WIDTH-1 downto 32) <= (others => '0');\nend generate g" "en_sm_CHAN_EST_SMOOTHING_dout_i;\nsm_CHAN_EST_SMOOTHING_dout_i(32-1 downto 0) <= sm_CHAN_EST_SMOOTHING_dout;\n-- 'L" "TS_Corr_Thresh'\nsm_LTS_Corr_Thresh_din <= sm_LTS_Corr_Thresh_din_i(32-1 downto 0);\nsm_LTS_Corr_Thresh_en " " <= sm_LTS_Corr_Thresh_en_i;\ngen_sm_LTS_Corr_Thresh_dout_i: if (32 < C_S_AXI_DATA_WIDTH) generate\n sm_LTS_Corr" "_Thresh_dout_i(C_S_AXI_DATA_WIDTH-1 downto 32) <= (others => '0');\nend generate gen_sm_LTS_Corr_Thresh_dout_i;\nsm" "_LTS_Corr_Thresh_dout_i(32-1 downto 0) <= sm_LTS_Corr_Thresh_dout;\n-- 'PKTDET_DSSS_CONFIG'\nsm_PKTDET_DSSS_CONFIG_" "din <= sm_PKTDET_DSSS_CONFIG_din_i(32-1 downto 0);\nsm_PKTDET_DSSS_CONFIG_en <= sm_PKTDET_DSSS_CONFIG_en_i" ";\ngen_sm_PKTDET_DSSS_CONFIG_dout_i: if (32 < C_S_AXI_DATA_WIDTH) generate\n sm_PKTDET_DSSS_CONFIG_dout_i(C_S_AX" "I_DATA_WIDTH-1 downto 32) <= (others => '0');\nend generate gen_sm_PKTDET_DSSS_CONFIG_dout_i;\nsm_PKTDET_DSSS_CONFI" "G_dout_i(32-1 downto 0) <= sm_PKTDET_DSSS_CONFIG_dout;\n-- 'LTS_Corr_Config'\nsm_LTS_Corr_Config_din <= sm_LTS_" "Corr_Config_din_i(32-1 downto 0);\nsm_LTS_Corr_Config_en <= sm_LTS_Corr_Config_en_i;\ngen_sm_LTS_Corr_Config_d" "out_i: if (32 < C_S_AXI_DATA_WIDTH) generate\n sm_LTS_Corr_Config_dout_i(C_S_AXI_DATA_WIDTH-1 downto 32) <= (oth" "ers => '0');\nend generate gen_sm_LTS_Corr_Config_dout_i;\nsm_LTS_Corr_Config_dout_i(32-1 downto 0) <= sm_LTS_Corr_" "Config_dout;\n-- 'PHY_CCA_CONFIG'\nsm_PHY_CCA_CONFIG_din <= sm_PHY_CCA_CONFIG_din_i(32-1 downto 0);\nsm_PHY_CCA" "_CONFIG_en <= sm_PHY_CCA_CONFIG_en_i;\ngen_sm_PHY_CCA_CONFIG_dout_i: if (32 < C_S_AXI_DATA_WIDTH) generate\n " " sm_PHY_CCA_CONFIG_dout_i(C_S_AXI_DATA_WIDTH-1 downto 32) <= (others => '0');\nend generate gen_sm_PHY_CCA_CONFIG_" "dout_i;\nsm_PHY_CCA_CONFIG_dout_i(32-1 downto 0) <= sm_PHY_CCA_CONFIG_dout;\n-- 'PKTBUF_MAX_WRITE_ADDR'\nsm_PKTBUF_" "MAX_WRITE_ADDR_din <= sm_PKTBUF_MAX_WRITE_ADDR_din_i(32-1 downto 0);\nsm_PKTBUF_MAX_WRITE_ADDR_en <= sm_PK" "TBUF_MAX_WRITE_ADDR_en_i;\ngen_sm_PKTBUF_MAX_WRITE_ADDR_dout_i: if (32 < C_S_AXI_DATA_WIDTH) generate\n sm_PKTBU" "F_MAX_WRITE_ADDR_dout_i(C_S_AXI_DATA_WIDTH-1 downto 32) <= (others => '0');\nend generate gen_sm_PKTBUF_MAX_WRITE_A" "DDR_dout_i;\nsm_PKTBUF_MAX_WRITE_ADDR_dout_i(32-1 downto 0) <= sm_PKTBUF_MAX_WRITE_ADDR_dout;\n-- 'FFT_Config'\nsm_" "FFT_Config_din <= sm_FFT_Config_din_i(32-1 downto 0);\nsm_FFT_Config_en <= sm_FFT_Config_en_i;\ngen_sm_FFT" "_Config_dout_i: if (32 < C_S_AXI_DATA_WIDTH) generate\n sm_FFT_Config_dout_i(C_S_AXI_DATA_WIDTH-1 downto 32) <= " "(others => '0');\nend generate gen_sm_FFT_Config_dout_i;\nsm_FFT_Config_dout_i(32-1 downto 0) <= sm_FFT_Config_dout" ";\n-- 'PKTDET_RSSI_CONFIG'\nsm_PKTDET_RSSI_CONFIG_din <= sm_PKTDET_RSSI_CONFIG_din_i(32-1 downto 0);\nsm_PKTDET" "_RSSI_CONFIG_en <= sm_PKTDET_RSSI_CONFIG_en_i;\ngen_sm_PKTDET_RSSI_CONFIG_dout_i: if (32 < C_S_AXI_DATA_WIDTH)" " generate\n sm_PKTDET_RSSI_CONFIG_dout_i(C_S_AXI_DATA_WIDTH-1 downto 32) <= (others => '0');\nend generate gen_s" "m_PKTDET_RSSI_CONFIG_dout_i;\nsm_PKTDET_RSSI_CONFIG_dout_i(32-1 downto 0) <= sm_PKTDET_RSSI_CONFIG_dout;\n-- 'RAMS_" "ADDR_WREN'\nsm_RAMS_ADDR_WREN_din <= sm_RAMS_ADDR_WREN_din_i(32-1 downto 0);\nsm_RAMS_ADDR_WREN_en <= sm_R" "AMS_ADDR_WREN_en_i;\ngen_sm_RAMS_ADDR_WREN_dout_i: if (32 < C_S_AXI_DATA_WIDTH) generate\n sm_RAMS_ADDR_WREN_dou" "t_i(C_S_AXI_DATA_WIDTH-1 downto 32) <= (others => '0');\nend generate gen_sm_RAMS_ADDR_WREN_dout_i;\nsm_RAMS_ADDR_W" "REN_dout_i(32-1 downto 0) <= sm_RAMS_ADDR_WREN_dout;\n-- 'MASK_1_RAM_WR_DATA'\nsm_MASK_1_RAM_WR_DATA_din <= sm_" "MASK_1_RAM_WR_DATA_din_i(32-1 downto 0);\nsm_MASK_1_RAM_WR_DATA_en <= sm_MASK_1_RAM_WR_DATA_en_i;\ngen_sm_MASK" "_1_RAM_WR_DATA_dout_i: if (32 < C_S_AXI_DATA_WIDTH) generate\n sm_MASK_1_RAM_WR_DATA_dout_i(C_S_AXI_DATA_WIDTH-1" " downto 32) <= (others => '0');\nend generate gen_sm_MASK_1_RAM_WR_DATA_dout_i;\nsm_MASK_1_RAM_WR_DATA_dout_i(32-1 " "downto 0) <= sm_MASK_1_RAM_WR_DATA_dout;\n-- 'TARGET_RAM_WR_DATA'\nsm_TARGET_RAM_WR_DATA_din <= sm_TARGET_RAM_W" "R_DATA_din_i(32-1 downto 0);\nsm_TARGET_RAM_WR_DATA_en <= sm_TARGET_RAM_WR_DATA_en_i;\ngen_sm_TARGET_RAM_WR_DA" "TA_dout_i: if (32 < C_S_AXI_DATA_WIDTH) generate\n sm_TARGET_RAM_WR_DATA_dout_i(C_S_AXI_DATA_WIDTH-1 downto 32) " "<= (others => '0');\nend generate gen_sm_TARGET_RAM_WR_DATA_dout_i;\nsm_TARGET_RAM_WR_DATA_dout_i(32-1 downto 0) <=" " sm_TARGET_RAM_WR_DATA_dout;\n-- 'From FIFO'\n-- 'To FIFO'\n-- 'Shared Memory'\n\nReadWriteSelect: process(memmap_s" "tate) is begin\n if (memmap_state = READ) then\n else\n end if;\nend process ReadWriteSelect;\n\n---------" "--------------------------------------------------------------------\n-- address for 'Shared Memory'\n-------------" "----------------------------------------------------------------\nSharedMemory_Addr_ResetN : process(AXI_AClk) is b" "egin\n if (AXI_AClk'event and AXI_AClk = '1') then\n if (AXI_AResetN = '0') then\n memmap_stat" "e <= READ;\n else\n if (S_AXI_AWVALID = '1') then\n -- write operation\n " " memmap_state <= WRITE;\n elsif (S_AXI_ARVALID = '1') then\n -- read operation\n " " memmap_state <= READ;\n end if;\n end if;\n end if;\nend process SharedMemory_Addr" "_ResetN;\n\n-----------------------------------------------------------------------------\n-- WRITE Command Control" "\n-----------------------------------------------------------------------------\nS_AXI_BID <= S_AXI_BID_i;\nS_A" "XI_BVALID <= S_AXI_BVALID_i;\nS_AXI_WREADY <= S_AXI_WREADY_i;\n-- No error checking\nS_AXI_BRESP <= (others=>'0'" ");\n\nPROC_AWREADY_ACK: process(read_state, write_state, S_AXI_ARVALID, S_AXI_AWVALID) is begin\n if (write_stat" "e = IDLE and S_AXI_AWVALID = '1' and read_state = IDLE) then\n S_AXI_AWREADY <= S_AXI_AWVALID;\n else\n " " S_AXI_AWREADY <= '0';\n end if;\nend process PROC_AWREADY_ACK;\n\nCmd_Decode_Write: process(AXI_AClk) is b" "egin\n if (AXI_AClk'event and AXI_AClk = '1') then\n if (AXI_AResetN = '0') then\n write_addr_" "valid <= '0';\n write_ready <= '0';\n s_fifo_we <= '0';\n S_A" "XI_BVALID_i <= '0';\n S_AXI_BID_i <= (others => '0');\n write_bank_addr_i <= (" "others => '0');\n write_linear_addr_i <= (others => '0');\n else\n if (write_state = I" "DLE) then\n if (S_AXI_AWVALID = '1' and read_state = IDLE) then\n -- reflect awid" "\n S_AXI_BID_i <= S_AXI_AWID;\n\n -- latch bank and linear addresses\n " " write_bank_addr_i <= S_AXI_AWADDR(C_S_AXI_TOTAL_ADDR_LEN-1 downto C_S_AXI_LINEAR_ADDR_LEN+2);\n " " write_linear_addr_i <= S_AXI_AWADDR(C_S_AXI_LINEAR_ADDR_LEN+1 downto 2);\n write_" "addr_valid <= '1';\n s_fifo_we <= '1';\n\n -- write state transition\n " " write_state <= WRITE_DATA;\n end if;\n elsif (write_state = WRITE_DATA) then" "\n write_ready <= '1';\n s_fifo_we <= '0';\n write_addr_valid <= S_AXI" "_WVALID;\n \n if (S_AXI_WVALID = '1' and write_ready = '1') then\n " " write_linear_addr_i <= Std_Logic_Vector(unsigned(write_linear_addr_i) + 1);\n end if;\n\n " " if (S_AXI_WLAST = '1' and write_ready = '1') then\n -- start responding through B channel " "upon the last write data sample\n S_AXI_BVALID_i <= '1';\n -- write data is o" "ver\n write_addr_valid <= '0';\n write_ready <= '0';\n -- " "write state transition\n write_state <= WRITE_RESPONSE;\n end if;\n el" "sif (write_state = WRITE_RESPONSE) then\n\n if (S_AXI_BREADY = '1') then\n -- wri" "te respond is over\n S_AXI_BVALID_i <= '0';\n S_AXI_BID_i <= (others => '0');" "\n\n -- write state transition\n write_state <= IDLE;\n end if" ";\n end if;\n end if;\n end if;\nend process Cmd_Decode_Write;\n\nWrite_Linear_Addr_Decode : p" "rocess(AXI_AClk) is \n\nbegin\n if (AXI_AClk'event and AXI_AClk = '1') then\n if (AXI_AResetN = '0') then" "\n -- 'To Register'\n -- RSSI_THRESH din/en\n sm_RSSI_THRESH_din_i <= (others => '" "0');\n sm_RSSI_THRESH_en_i <= '0';\n -- CONFIG din/en\n sm_CONFIG_din_i <= (others" " => '0');\n sm_CONFIG_en_i <= '0';\n -- DSSS_RX_CONFIG din/en\n sm_DSSS_RX_CONFIG_" "din_i <= (others => '0');\n sm_DSSS_RX_CONFIG_en_i <= '0';\n -- PKT_BUF_SEL din/en\n " " sm_PKT_BUF_SEL_din_i <= (others => '0');\n sm_PKT_BUF_SEL_en_i <= '0';\n -- PKTDET_AUTOCOR" "R_CONFIG din/en\n sm_PKTDET_AUTOCORR_CONFIG_din_i <= (others => '0');\n sm_PKTDET_AUTOCORR_CO" "NFIG_en_i <= '0';\n -- FEC_CONFIG din/en\n sm_FEC_CONFIG_din_i <= (others => '0');\n " " sm_FEC_CONFIG_en_i <= '0';\n -- Control din/en\n sm_Control_din_i <= (others => '0');\n " " sm_Control_en_i <= '0';\n -- LTS_Corr_PeakType_Thresh din/en\n sm_LTS_Corr_PeakType_" "Thresh_din_i <= (others => '0');\n sm_LTS_Corr_PeakType_Thresh_en_i <= '0';\n -- CHAN_EST_SMO" "OTHING din/en\n sm_CHAN_EST_SMOOTHING_din_i <= (others => '0');\n sm_CHAN_EST_SMOOTHING_en_i " "<= '0';\n -- LTS_Corr_Thresh din/en\n sm_LTS_Corr_Thresh_din_i <= (others => '0');\n " " sm_LTS_Corr_Thresh_en_i <= '0';\n -- PKTDET_DSSS_CONFIG din/en\n sm_PKTDET_DSSS_CONFIG_din" "_i <= (others => '0');\n sm_PKTDET_DSSS_CONFIG_en_i <= '0';\n -- LTS_Corr_Config din/en\n " " sm_LTS_Corr_Config_din_i <= (others => '0');\n sm_LTS_Corr_Config_en_i <= '0';\n -- P" "HY_CCA_CONFIG din/en\n sm_PHY_CCA_CONFIG_din_i <= (others => '0');\n sm_PHY_CCA_CONFIG_en_i <" "= '0';\n -- PKTBUF_MAX_WRITE_ADDR din/en\n sm_PKTBUF_MAX_WRITE_ADDR_din_i <= (others => '0');" "\n sm_PKTBUF_MAX_WRITE_ADDR_en_i <= '0';\n -- FFT_Config din/en\n sm_FFT_Config_di" "n_i <= (others => '0');\n sm_FFT_Config_en_i <= '0';\n -- PKTDET_RSSI_CONFIG din/en\n " " sm_PKTDET_RSSI_CONFIG_din_i <= (others => '0');\n sm_PKTDET_RSSI_CONFIG_en_i <= '0';\n --" " RAMS_ADDR_WREN din/en\n sm_RAMS_ADDR_WREN_din_i <= (others => '0');\n sm_RAMS_ADDR_WREN_en_i" " <= '0';\n -- MASK_1_RAM_WR_DATA din/en\n sm_MASK_1_RAM_WR_DATA_din_i <= (others => '0');\n " " sm_MASK_1_RAM_WR_DATA_en_i <= '0';\n -- TARGET_RAM_WR_DATA din/en\n sm_TARGET_RAM_W" "R_DATA_din_i <= (others => '0');\n sm_TARGET_RAM_WR_DATA_en_i <= '0';\n -- 'To FIFO'\n " " -- 'Shared Memory'\n else\n -- default assignments\n\n -- 'To Register'\n " " if (unsigned(write_bank_addr_i) = 2) then\n if (unsigned(write_linear_addr_i) = 0) then\n " " -- RSSI_THRESH din/en\n sm_RSSI_THRESH_din_i <= S_AXI_WDATA;\n s" "m_RSSI_THRESH_en_i <= write_addr_valid;\n elsif (unsigned(write_linear_addr_i) = 1) then\n " " -- CONFIG din/en\n sm_CONFIG_din_i <= S_AXI_WDATA;\n sm_CONFIG_en_" "i <= write_addr_valid;\n elsif (unsigned(write_linear_addr_i) = 2) then\n -- DSS" "S_RX_CONFIG din/en\n sm_DSSS_RX_CONFIG_din_i <= S_AXI_WDATA;\n sm_DSSS_RX_CON" "FIG_en_i <= write_addr_valid;\n elsif (unsigned(write_linear_addr_i) = 3) then\n " " -- PKT_BUF_SEL din/en\n sm_PKT_BUF_SEL_din_i <= S_AXI_WDATA;\n sm_PKT_BUF_SE" "L_en_i <= write_addr_valid;\n elsif (unsigned(write_linear_addr_i) = 4) then\n -" "- PKTDET_AUTOCORR_CONFIG din/en\n sm_PKTDET_AUTOCORR_CONFIG_din_i <= S_AXI_WDATA;\n " " sm_PKTDET_AUTOCORR_CONFIG_en_i <= write_addr_valid;\n elsif (unsigned(write_linear_addr_i) =" " 5) then\n -- FEC_CONFIG din/en\n sm_FEC_CONFIG_din_i <= S_AXI_WDATA;\n " " sm_FEC_CONFIG_en_i <= write_addr_valid;\n elsif (unsigned(write_linear_addr_i) = 6) t" "hen\n -- Control din/en\n sm_Control_din_i <= S_AXI_WDATA;\n " " sm_Control_en_i <= write_addr_valid;\n elsif (unsigned(write_linear_addr_i) = 7) then\n " " -- LTS_Corr_PeakType_Thresh din/en\n sm_LTS_Corr_PeakType_Thresh_din_i <= S_AXI_WDATA" ";\n sm_LTS_Corr_PeakType_Thresh_en_i <= write_addr_valid;\n elsif (unsigned(writ" "e_linear_addr_i) = 8) then\n -- CHAN_EST_SMOOTHING din/en\n sm_CHAN_EST_SMOOT" "HING_din_i <= S_AXI_WDATA;\n sm_CHAN_EST_SMOOTHING_en_i <= write_addr_valid;\n e" "lsif (unsigned(write_linear_addr_i) = 9) then\n -- LTS_Corr_Thresh din/en\n s" "m_LTS_Corr_Thresh_din_i <= S_AXI_WDATA;\n sm_LTS_Corr_Thresh_en_i <= write_addr_valid;\n " " elsif (unsigned(write_linear_addr_i) = 10) then\n -- PKTDET_DSSS_CONFIG din/en\n " " sm_PKTDET_DSSS_CONFIG_din_i <= S_AXI_WDATA;\n sm_PKTDET_DSSS_CONFIG_en_i <= write_" "addr_valid;\n elsif (unsigned(write_linear_addr_i) = 11) then\n -- LTS_Corr_Confi" "g din/en\n sm_LTS_Corr_Config_din_i <= S_AXI_WDATA;\n sm_LTS_Corr_Config_en_i" " <= write_addr_valid;\n elsif (unsigned(write_linear_addr_i) = 12) then\n -- PHY" "_CCA_CONFIG din/en\n sm_PHY_CCA_CONFIG_din_i <= S_AXI_WDATA;\n sm_PHY_CCA_CON" "FIG_en_i <= write_addr_valid;\n elsif (unsigned(write_linear_addr_i) = 13) then\n " " -- PKTBUF_MAX_WRITE_ADDR din/en\n sm_PKTBUF_MAX_WRITE_ADDR_din_i <= S_AXI_WDATA;\n " " sm_PKTBUF_MAX_WRITE_ADDR_en_i <= write_addr_valid;\n elsif (unsigned(write_linear_addr_i) =" " 14) then\n -- FFT_Config din/en\n sm_FFT_Config_din_i <= S_AXI_WDATA;\n " " sm_FFT_Config_en_i <= write_addr_valid;\n elsif (unsigned(write_linear_addr_i) = 15)" " then\n -- PKTDET_RSSI_CONFIG din/en\n sm_PKTDET_RSSI_CONFIG_din_i <= S_AXI_W" "DATA;\n sm_PKTDET_RSSI_CONFIG_en_i <= write_addr_valid;\n elsif (unsigned(write_" "linear_addr_i) = 16) then\n -- RAMS_ADDR_WREN din/en\n sm_RAMS_ADDR_WREN_din_" "i <= S_AXI_WDATA;\n sm_RAMS_ADDR_WREN_en_i <= write_addr_valid;\n elsif (unsigne" "d(write_linear_addr_i) = 17) then\n -- MASK_1_RAM_WR_DATA din/en\n sm_MASK_1_" "RAM_WR_DATA_din_i <= S_AXI_WDATA;\n sm_MASK_1_RAM_WR_DATA_en_i <= write_addr_valid;\n " " elsif (unsigned(write_linear_addr_i) = 18) then\n -- TARGET_RAM_WR_DATA din/en\n " " sm_TARGET_RAM_WR_DATA_din_i <= S_AXI_WDATA;\n sm_TARGET_RAM_WR_DATA_en_i <= write_add" "r_valid;\n end if;\n end if; \n \n \n end if;\n end if;\ne" "nd process Write_Linear_Addr_Decode;\n \n--------------------------------------------------------------------------" "---\n-- READ Control\n-----------------------------------------------------------------------------\n\nS_AXI_RDATA " " <= S_AXI_RDATA_i;\nS_AXI_RVALID <= S_AXI_RVALID_i;\nS_AXI_RLAST <= S_AXI_RLAST_i;\nS_AXI_RID <= S_AXI_RID_i" ";\n-- TODO: no error checking\nS_AXI_RRESP <= (others=>'0');\n\nPROC_ARREADY_ACK: process(read_state, S_AXI_ARVALID" ", write_state, S_AXI_AWVALID) is begin\n -- Note: WRITE has higher priority than READ\n if (read_state = IDLE" " and S_AXI_ARVALID = '1' and write_state = IDLE and S_AXI_AWVALID /= '1') then\n S_AXI_ARREADY <= S_AXI_ARVA" "LID;\n else\n S_AXI_ARREADY <= '0';\n end if;\nend process PROC_ARREADY_ACK;\n\nS_AXI_WREADY_i <= writ" "e_ready;\n\nProcess_Sideband: process(write_state, read_state) is begin\n if (read_state = READ_PREP) then\n " " s_shram_en <= '1';\n elsif (read_state = READ_DATA) then\n s_shram_en <= S_AXI_RREADY;\n elsif (wr" "ite_state = WRITE_DATA) then\n s_shram_en <= S_AXI_WVALID;\n else\n s_shram_en <= '0';\n end if" ";\nend process Process_Sideband;\n\nCmd_Decode_Read: process(AXI_AClk) is begin\n if (AXI_AClk'event and AXI_ACl" "k = '1') then\n if (AXI_AResetN = '0') then\n S_AXI_RVALID_i <= '0';\n read_bank_addr_" "i <= (others => '0');\n read_linear_addr_i <= (others => '0');\n S_AXI_ARLEN_i <= (" "others => '0');\n S_AXI_RLAST_i <= '0';\n S_AXI_RID_i <= (others => '0');\n " " read_state <= IDLE;\n read_prep_counter <= (others => '0');\n read_addr_co" "unter <= (others => '0');\n read_data_counter <= (others => '0');\n else\n -- defa" "ult assignments\n s_fifo_re <= '0';\n\n if (read_state = IDLE) then\n -- Note " "WRITE has higher priority than READ\n if (S_AXI_ARVALID = '1' and write_state = IDLE and S_AXI_AWVAL" "ID /= '1') then\n -- extract bank and linear addresses\n read_bank_addr_i " "<= S_AXI_ARADDR(C_S_AXI_TOTAL_ADDR_LEN-1 downto C_S_AXI_LINEAR_ADDR_LEN+2);\n read_linear_addr_i" " <= S_AXI_ARADDR(C_S_AXI_LINEAR_ADDR_LEN+1 downto 2);\n s_fifo_re <= '1';\n\n " " -- reflect arid\n S_AXI_RID_i <= S_AXI_ARID;\n\n -- load read liner address" " and data counter\n read_addr_counter <= S_AXI_ARLEN;\n read_data_counter <= " "S_AXI_ARLEN;\n\n -- load read preparation counter\n read_prep_counter <= C_RE" "AD_PREP_DELAY;\n -- read state transition\n read_state <= READ_PREP;\n " " end if;\n elsif (read_state = READ_PREP) then\n if (unsigned(read_prep_counter) " "= 0) then\n if (unsigned(read_data_counter) = 0) then\n -- tag the last d" "ata generated by the slave\n S_AXI_RLAST_i <= '1';\n end if;\n " " -- valid data appears\n S_AXI_RVALID_i <= '1';\n -- read state trans" "ition\n read_state <= READ_DATA;\n else\n -- decrease read pre" "paration counter\n read_prep_counter <= Std_Logic_Vector(unsigned(read_prep_counter) - 1);\n " " end if;\n\n if (unsigned(read_prep_counter) /= 3 and unsigned(read_addr_counter) /= 0) t" "hen\n -- decrease address counter\n read_addr_counter <= Std_Logic_Vector(uns" "igned(read_addr_counter) - 1);\n -- increase linear address (no band crossing)\n " " read_linear_addr_i <= Std_Logic_Vector(unsigned(read_linear_addr_i) + 1);\n end if;\n " " elsif (read_state = READ_DATA) then\n if (S_AXI_RREADY = '1') then\n if (unsigne" "d(read_data_counter) = 1) then\n -- tag the last data generated by the slave\n " " S_AXI_RLAST_i <= '1';\n end if;\n\n if (unsigned(read_data_counter)" " = 0) then\n -- arid\n S_AXI_RID_i <= (others => '0');\n " " -- rlast\n S_AXI_RLAST_i <= '0';\n -- no more valid data\n" " S_AXI_RVALID_i <= '0';\n -- read state transition\n " " read_state <= IDLE;\n else\n -- decrease read preparation counter\n" " read_data_counter <= Std_Logic_Vector(unsigned(read_data_counter) - 1);\n\n " " if (unsigned(read_addr_counter) /= 0) then\n -- decrease address counter\n " " read_addr_counter <= Std_Logic_Vector(unsigned(read_addr_counter) - 1);\n " " -- increase linear address (no band crossing)\n read_linear_addr_i <= Std_Logic_" "Vector(unsigned(read_linear_addr_i) + 1);\n end if;\n end if;\n " " end if;\n end if;\n\n end if;\n end if;\nend process Cmd_Decode_Read;\n\nRead_Linear_Add" "r_Decode : process(AXI_AClk) is begin\n if (AXI_AClk'event and AXI_AClk = '1') then\n if (AXI_AResetN = '" "0') then\n reg_bank_out_i <= (others => '0');\n fifo_bank_out_i <= (others => '0');\n " " shmem_bank_out_i <= (others => '0');\n S_AXI_RDATA_i <= (others => '0');\n else\n " " if (unsigned(read_bank_addr_i) = 2) then\n -- 'From Register'\n if (unsigned(re" "ad_linear_addr_i) = 19) then\n -- 'RX_PKT_RSSI_CD' dout\n reg_bank_out_i <= s" "m_RX_PKT_RSSI_CD_dout_i;\n elsif (unsigned(read_linear_addr_i) = 20) then\n -- 'R" "X_PKT_AGC_GAINS' dout\n reg_bank_out_i <= sm_RX_PKT_AGC_GAINS_dout_i;\n elsif (un" "signed(read_linear_addr_i) = 21) then\n -- 'RX_PKT_RSSI_AB' dout\n reg_bank_o" "ut_i <= sm_RX_PKT_RSSI_AB_dout_i;\n elsif (unsigned(read_linear_addr_i) = 22) then\n " " -- 'CFO_EST_TIME_DOMAIN' dout\n reg_bank_out_i <= sm_CFO_EST_TIME_DOMAIN_dout_i;\n " " elsif (unsigned(read_linear_addr_i) = 23) then\n -- 'Status' dout\n reg" "_bank_out_i <= sm_Status_dout_i;\n elsif (unsigned(read_linear_addr_i) = 24) then\n " " -- 'PKT_DET_COUNT_DSSS' dout\n reg_bank_out_i <= sm_PKT_DET_COUNT_DSSS_dout_i;\n " " elsif (unsigned(read_linear_addr_i) = 25) then\n -- 'PKT_DET_COUNT_OFDM' dout\n " " reg_bank_out_i <= sm_PKT_DET_COUNT_OFDM_dout_i;\n elsif (unsigned(read_linear_addr_i) = 26) th" "en\n -- 'RXIQ_MAG_SUM_RFA' dout\n reg_bank_out_i <= sm_RXIQ_MAG_SUM_RFA_dout_" "i;\n end if;\n -- 'To Register' (with register readback)\n if (unsigne" "d(read_linear_addr_i) = 0) then\n -- 'RSSI_THRESH' dout\n reg_bank_out_i <= s" "m_RSSI_THRESH_dout_i;\n elsif (unsigned(read_linear_addr_i) = 1) then\n -- 'CONFI" "G' dout\n reg_bank_out_i <= sm_CONFIG_dout_i;\n elsif (unsigned(read_linear_addr_" "i) = 2) then\n -- 'DSSS_RX_CONFIG' dout\n reg_bank_out_i <= sm_DSSS_RX_CONFIG" "_dout_i;\n elsif (unsigned(read_linear_addr_i) = 3) then\n -- 'PKT_BUF_SEL' dout\n" " reg_bank_out_i <= sm_PKT_BUF_SEL_dout_i;\n elsif (unsigned(read_linear_addr_i) =" " 4) then\n -- 'PKTDET_AUTOCORR_CONFIG' dout\n reg_bank_out_i <= sm_PKTDET_AUT" "OCORR_CONFIG_dout_i;\n elsif (unsigned(read_linear_addr_i) = 5) then\n -- 'FEC_CO" "NFIG' dout\n reg_bank_out_i <= sm_FEC_CONFIG_dout_i;\n elsif (unsigned(read_linea" "r_addr_i) = 6) then\n -- 'Control' dout\n reg_bank_out_i <= sm_Control_dout_i" ";\n elsif (unsigned(read_linear_addr_i) = 7) then\n -- 'LTS_Corr_PeakType_Thresh'" " dout\n reg_bank_out_i <= sm_LTS_Corr_PeakType_Thresh_dout_i;\n elsif (unsigned(r" "ead_linear_addr_i) = 8) then\n -- 'CHAN_EST_SMOOTHING' dout\n reg_bank_out_i " "<= sm_CHAN_EST_SMOOTHING_dout_i;\n elsif (unsigned(read_linear_addr_i) = 9) then\n " " -- 'LTS_Corr_Thresh' dout\n reg_bank_out_i <= sm_LTS_Corr_Thresh_dout_i;\n elsi" "f (unsigned(read_linear_addr_i) = 10) then\n -- 'PKTDET_DSSS_CONFIG' dout\n r" "eg_bank_out_i <= sm_PKTDET_DSSS_CONFIG_dout_i;\n elsif (unsigned(read_linear_addr_i) = 11) then\n " " -- 'LTS_Corr_Config' dout\n reg_bank_out_i <= sm_LTS_Corr_Config_dout_i;\n " " elsif (unsigned(read_linear_addr_i) = 12) then\n -- 'PHY_CCA_CONFIG' dout\n " " reg_bank_out_i <= sm_PHY_CCA_CONFIG_dout_i;\n elsif (unsigned(read_linear_addr_i) = 13) th" "en\n -- 'PKTBUF_MAX_WRITE_ADDR' dout\n reg_bank_out_i <= sm_PKTBUF_MAX_WRITE_" "ADDR_dout_i;\n elsif (unsigned(read_linear_addr_i) = 14) then\n -- 'FFT_Config' d" "out\n reg_bank_out_i <= sm_FFT_Config_dout_i;\n elsif (unsigned(read_linear_addr_" "i) = 15) then\n -- 'PKTDET_RSSI_CONFIG' dout\n reg_bank_out_i <= sm_PKTDET_RS" "SI_CONFIG_dout_i;\n elsif (unsigned(read_linear_addr_i) = 16) then\n -- 'RAMS_ADD" "R_WREN' dout\n reg_bank_out_i <= sm_RAMS_ADDR_WREN_dout_i;\n elsif (unsigned(read" "_linear_addr_i) = 17) then\n -- 'MASK_1_RAM_WR_DATA' dout\n reg_bank_out_i <=" " sm_MASK_1_RAM_WR_DATA_dout_i;\n elsif (unsigned(read_linear_addr_i) = 18) then\n " " -- 'TARGET_RAM_WR_DATA' dout\n reg_bank_out_i <= sm_TARGET_RAM_WR_DATA_dout_i;\n " " end if;\n\n S_AXI_RDATA_i <= reg_bank_out_i;\n elsif (unsigned(read_bank_addr_i) = 1) th" "en\n -- 'From FIFO'\n -- 'To FIFO'\n\n S_AXI_RDATA_i <= fifo_bank_out_" "i;\n elsif (unsigned(read_bank_addr_i) = 0 and s_shram_en = '1') then\n -- 'Shared Memory" "'\n\n S_AXI_RDATA_i <= shmem_bank_out_i;\n end if;\n end if;\n end if;\nend pro" "cess Read_Linear_Addr_Decode;\n\nend architecture IMP;\n" config "{'inports'=>[{'arith_type'=>2.00000000000000000,'bin_pt'=>0.00000000000000000,'name'=>'AXI_ARESETN','wid" "th'=>0},{'arith_type'=>2.00000000000000000,'bin_pt'=>0.00000000000000000,'name'=>'S_AXI_ARADDR','width'=>32},{'arit" "h_type'=>2.00000000000000000,'bin_pt'=>0.00000000000000000,'name'=>'S_AXI_ARBURST','width'=>2},{'arith_type'=>2.000" "00000000000000,'bin_pt'=>0.00000000000000000,'name'=>'S_AXI_ARCACHE','width'=>4},{'arith_type'=>2.00000000000000000" ",'bin_pt'=>0.00000000000000000,'name'=>'S_AXI_ARID','width'=>8},{'arith_type'=>2.00000000000000000,'bin_pt'=>0.0000" "0000000000000,'name'=>'S_AXI_ARLEN','width'=>8},{'arith_type'=>2.00000000000000000,'bin_pt'=>0.00000000000000000,'n" "ame'=>'S_AXI_ARLOCK','width'=>2},{'arith_type'=>2.00000000000000000,'bin_pt'=>0.00000000000000000,'name'=>'S_AXI_AR" "PROT','width'=>3},{'arith_type'=>2.00000000000000000,'bin_pt'=>0.00000000000000000,'name'=>'S_AXI_ARSIZE','width'=>" "3},{'arith_type'=>2.00000000000000000,'bin_pt'=>0.00000000000000000,'name'=>'S_AXI_ARVALID','width'=>0},{'arith_typ" "e'=>2.00000000000000000,'bin_pt'=>0.00000000000000000,'name'=>'S_AXI_AWADDR','width'=>32},{'arith_type'=>2.00000000" "000000000,'bin_pt'=>0.00000000000000000,'name'=>'S_AXI_AWBURST','width'=>2},{'arith_type'=>2.00000000000000000,'bin" "_pt'=>0.00000000000000000,'name'=>'S_AXI_AWCACHE','width'=>4},{'arith_type'=>2.00000000000000000,'bin_pt'=>0.000000" "00000000000,'name'=>'S_AXI_AWID','width'=>8},{'arith_type'=>2.00000000000000000,'bin_pt'=>0.00000000000000000,'name" "'=>'S_AXI_AWLEN','width'=>8},{'arith_type'=>2.00000000000000000,'bin_pt'=>0.00000000000000000,'name'=>'S_AXI_AWLOCK" "','width'=>2},{'arith_type'=>2.00000000000000000,'bin_pt'=>0.00000000000000000,'name'=>'S_AXI_AWPROT','width'=>3},{" "'arith_type'=>2.00000000000000000,'bin_pt'=>0.00000000000000000,'name'=>'S_AXI_AWSIZE','width'=>3},{'arith_type'=>2" ".00000000000000000,'bin_pt'=>0.00000000000000000,'name'=>'S_AXI_AWVALID','width'=>0},{'arith_type'=>2.0000000000000" "0000,'bin_pt'=>0.00000000000000000,'name'=>'S_AXI_BREADY','width'=>0},{'arith_type'=>2.00000000000000000,'bin_pt'=>" "0.00000000000000000,'name'=>'S_AXI_RREADY','width'=>0},{'arith_type'=>2.00000000000000000,'bin_pt'=>0.0000000000000" "0000,'name'=>'S_AXI_WDATA','width'=>32},{'arith_type'=>2.00000000000000000,'bin_pt'=>0.00000000000000000,'name'=>'S" "_AXI_WLAST','width'=>0},{'arith_type'=>2.00000000000000000,'bin_pt'=>0.00000000000000000,'name'=>'S_AXI_WSTRB','wid" "th'=>4},{'arith_type'=>2.00000000000000000,'bin_pt'=>0.00000000000000000,'name'=>'S_AXI_WVALID','width'=>0},{'arith" "_type'=>2,'bin_pt'=>0,'name'=>'sm_RX_PKT_RSSI_CD_dout','width'=>32},{'arith_type'=>2,'bin_pt'=>0,'name'=>'sm_RX_PKT" "_AGC_GAINS_dout','width'=>32},{'arith_type'=>2,'bin_pt'=>0,'name'=>'sm_RX_PKT_RSSI_AB_dout','width'=>32},{'arith_ty" "pe'=>2,'bin_pt'=>0,'name'=>'sm_CFO_EST_TIME_DOMAIN_dout','width'=>32},{'arith_type'=>2,'bin_pt'=>0,'name'=>'sm_Stat" "us_dout','width'=>32},{'arith_type'=>2,'bin_pt'=>0,'name'=>'sm_PKT_DET_COUNT_DSSS_dout','width'=>32},{'arith_type'=" ">2,'bin_pt'=>0,'name'=>'sm_PKT_DET_COUNT_OFDM_dout','width'=>32},{'arith_type'=>2,'bin_pt'=>0,'name'=>'sm_RXIQ_MAG_" "SUM_RFA_dout','width'=>32},{'arith_type'=>2,'bin_pt'=>0,'name'=>'sm_RSSI_THRESH_dout','width'=>32},{'arith_type'=>2" ",'bin_pt'=>0,'name'=>'sm_CONFIG_dout','width'=>32},{'arith_type'=>2,'bin_pt'=>0,'name'=>'sm_DSSS_RX_CONFIG_dout','w" "idth'=>32},{'arith_type'=>2,'bin_pt'=>0,'name'=>'sm_PKT_BUF_SEL_dout','width'=>32},{'arith_type'=>2,'bin_pt'=>0,'na" "me'=>'sm_PKTDET_AUTOCORR_CONFIG_dout','width'=>32},{'arith_type'=>2,'bin_pt'=>0,'name'=>'sm_FEC_CONFIG_dout','width" "'=>32},{'arith_type'=>2,'bin_pt'=>0,'name'=>'sm_Control_dout','width'=>32},{'arith_type'=>2,'bin_pt'=>0,'name'=>'sm" "_LTS_Corr_PeakType_Thresh_dout','width'=>32},{'arith_type'=>2,'bin_pt'=>0,'name'=>'sm_CHAN_EST_SMOOTHING_dout','wid" "th'=>32},{'arith_type'=>2,'bin_pt'=>0,'name'=>'sm_LTS_Corr_Thresh_dout','width'=>32},{'arith_type'=>2,'bin_pt'=>0,'" "name'=>'sm_PKTDET_DSSS_CONFIG_dout','width'=>32},{'arith_type'=>2,'bin_pt'=>0,'name'=>'sm_LTS_Corr_Config_dout','wi" "dth'=>32},{'arith_type'=>2,'bin_pt'=>0,'name'=>'sm_PHY_CCA_CONFIG_dout','width'=>32},{'arith_type'=>2,'bin_pt'=>0,'" "name'=>'sm_PKTBUF_MAX_WRITE_ADDR_dout','width'=>32},{'arith_type'=>2,'bin_pt'=>0,'name'=>'sm_FFT_Config_dout','widt" "h'=>32},{'arith_type'=>2,'bin_pt'=>0,'name'=>'sm_PKTDET_RSSI_CONFIG_dout','width'=>32},{'arith_type'=>2,'bin_pt'=>0" ",'name'=>'sm_RAMS_ADDR_WREN_dout','width'=>32},{'arith_type'=>2,'bin_pt'=>0,'name'=>'sm_MASK_1_RAM_WR_DATA_dout','w" "idth'=>32},{'arith_type'=>2,'bin_pt'=>0,'name'=>'sm_TARGET_RAM_WR_DATA_dout','width'=>32}],'outports'=>[{'arith_typ" "e'=>2.00000000000000000,'bin_pt'=>0.00000000000000000,'name'=>'S_AXI_ARREADY','width'=>0},{'arith_type'=>2.00000000" "000000000,'bin_pt'=>0.00000000000000000,'name'=>'S_AXI_AWREADY','width'=>0},{'arith_type'=>2.00000000000000000,'bin" "_pt'=>0.00000000000000000,'name'=>'S_AXI_BID','width'=>8},{'arith_type'=>2.00000000000000000,'bin_pt'=>0.0000000000" "0000000,'name'=>'S_AXI_BRESP','width'=>2},{'arith_type'=>2.00000000000000000,'bin_pt'=>0.00000000000000000,'name'=>" "'S_AXI_BVALID','width'=>0},{'arith_type'=>2.00000000000000000,'bin_pt'=>0.00000000000000000,'name'=>'S_AXI_RDATA','" "width'=>32},{'arith_type'=>2.00000000000000000,'bin_pt'=>0.00000000000000000,'name'=>'S_AXI_RID','width'=>8},{'arit" "h_type'=>2.00000000000000000,'bin_pt'=>0.00000000000000000,'name'=>'S_AXI_RLAST','width'=>0},{'arith_type'=>2.00000" "000000000000,'bin_pt'=>0.00000000000000000,'name'=>'S_AXI_RRESP','width'=>2},{'arith_type'=>2.00000000000000000,'bi" "n_pt'=>0.00000000000000000,'name'=>'S_AXI_RVALID','width'=>0},{'arith_type'=>2.00000000000000000,'bin_pt'=>0.000000" "00000000000,'name'=>'S_AXI_WREADY','width'=>0},{'arith_type'=>2,'bin_pt'=>0,'name'=>'sm_RSSI_THRESH_din','width'=>3" "2},{'arith_type'=>2.00000000000000000,'bin_pt'=>0.00000000000000000,'name'=>'sm_RSSI_THRESH_en','width'=>0.00000000" "000000000},{'arith_type'=>2,'bin_pt'=>0,'name'=>'sm_CONFIG_din','width'=>32},{'arith_type'=>2.00000000000000000,'bi" "n_pt'=>0.00000000000000000,'name'=>'sm_CONFIG_en','width'=>0.00000000000000000},{'arith_type'=>2,'bin_pt'=>0,'name'" "=>'sm_DSSS_RX_CONFIG_din','width'=>32},{'arith_type'=>2.00000000000000000,'bin_pt'=>0.00000000000000000,'name'=>'sm" "_DSSS_RX_CONFIG_en','width'=>0.00000000000000000},{'arith_type'=>2,'bin_pt'=>0,'name'=>'sm_PKT_BUF_SEL_din','width'" "=>32},{'arith_type'=>2.00000000000000000,'bin_pt'=>0.00000000000000000,'name'=>'sm_PKT_BUF_SEL_en','width'=>0.00000" "000000000000},{'arith_type'=>2,'bin_pt'=>0,'name'=>'sm_PKTDET_AUTOCORR_CONFIG_din','width'=>32},{'arith_type'=>2.00" "000000000000000,'bin_pt'=>0.00000000000000000,'name'=>'sm_PKTDET_AUTOCORR_CONFIG_en','width'=>0.00000000000000000}," "{'arith_type'=>2,'bin_pt'=>0,'name'=>'sm_FEC_CONFIG_din','width'=>32},{'arith_type'=>2.00000000000000000,'bin_pt'=>" "0.00000000000000000,'name'=>'sm_FEC_CONFIG_en','width'=>0.00000000000000000},{'arith_type'=>2,'bin_pt'=>0,'name'=>'" "sm_Control_din','width'=>32},{'arith_type'=>2.00000000000000000,'bin_pt'=>0.00000000000000000,'name'=>'sm_Control_e" "n','width'=>0.00000000000000000},{'arith_type'=>2,'bin_pt'=>0,'name'=>'sm_LTS_Corr_PeakType_Thresh_din','width'=>32" "},{'arith_type'=>2.00000000000000000,'bin_pt'=>0.00000000000000000,'name'=>'sm_LTS_Corr_PeakType_Thresh_en','width'" "=>0.00000000000000000},{'arith_type'=>2,'bin_pt'=>0,'name'=>'sm_CHAN_EST_SMOOTHING_din','width'=>32},{'arith_type'=" ">2.00000000000000000,'bin_pt'=>0.00000000000000000,'name'=>'sm_CHAN_EST_SMOOTHING_en','width'=>0.00000000000000000}" ",{'arith_type'=>2,'bin_pt'=>0,'name'=>'sm_LTS_Corr_Thresh_din','width'=>32},{'arith_type'=>2.00000000000000000,'bin" "_pt'=>0.00000000000000000,'name'=>'sm_LTS_Corr_Thresh_en','width'=>0.00000000000000000},{'arith_type'=>2,'bin_pt'=>" "0,'name'=>'sm_PKTDET_DSSS_CONFIG_din','width'=>32},{'arith_type'=>2.00000000000000000,'bin_pt'=>0.00000000000000000" ",'name'=>'sm_PKTDET_DSSS_CONFIG_en','width'=>0.00000000000000000},{'arith_type'=>2,'bin_pt'=>0,'name'=>'sm_LTS_Corr" "_Config_din','width'=>32},{'arith_type'=>2.00000000000000000,'bin_pt'=>0.00000000000000000,'name'=>'sm_LTS_Corr_Con" "fig_en','width'=>0.00000000000000000},{'arith_type'=>2,'bin_pt'=>0,'name'=>'sm_PHY_CCA_CONFIG_din','width'=>32},{'a" "rith_type'=>2.00000000000000000,'bin_pt'=>0.00000000000000000,'name'=>'sm_PHY_CCA_CONFIG_en','width'=>0.00000000000" "000000},{'arith_type'=>2,'bin_pt'=>0,'name'=>'sm_PKTBUF_MAX_WRITE_ADDR_din','width'=>32},{'arith_type'=>2.000000000" "00000000,'bin_pt'=>0.00000000000000000,'name'=>'sm_PKTBUF_MAX_WRITE_ADDR_en','width'=>0.00000000000000000},{'arith_" "type'=>2,'bin_pt'=>0,'name'=>'sm_FFT_Config_din','width'=>32},{'arith_type'=>2.00000000000000000,'bin_pt'=>0.000000" "00000000000,'name'=>'sm_FFT_Config_en','width'=>0.00000000000000000},{'arith_type'=>2,'bin_pt'=>0,'name'=>'sm_PKTDE" "T_RSSI_CONFIG_din','width'=>32},{'arith_type'=>2.00000000000000000,'bin_pt'=>0.00000000000000000,'name'=>'sm_PKTDET" "_RSSI_CONFIG_en','width'=>0.00000000000000000},{'arith_type'=>2,'bin_pt'=>0,'name'=>'sm_RAMS_ADDR_WREN_din','width'" "=>32},{'arith_type'=>2.00000000000000000,'bin_pt'=>0.00000000000000000,'name'=>'sm_RAMS_ADDR_WREN_en','width'=>0.00" "000000000000000},{'arith_type'=>2,'bin_pt'=>0,'name'=>'sm_MASK_1_RAM_WR_DATA_din','width'=>32},{'arith_type'=>2.000" "00000000000000,'bin_pt'=>0.00000000000000000,'name'=>'sm_MASK_1_RAM_WR_DATA_en','width'=>0.00000000000000000},{'ari" "th_type'=>2,'bin_pt'=>0,'name'=>'sm_TARGET_RAM_WR_DATA_din','width'=>32},{'arith_type'=>2.00000000000000000,'bin_pt" "'=>0.00000000000000000,'name'=>'sm_TARGET_RAM_WR_DATA_en','width'=>0.00000000000000000}]}" inheritDeviceType "inheritDeviceType" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "edkcore" sg_icon_stat "250,1566,52,49,white,blue,0,01ff78c9,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 250 250 0 0 ],[0 0 1566 1566 0 ],[0.77 0.8" "2 0.91 ]);\nplot([0 250 250 0 0 ],[0 0 1566 1566 0 ]);\npatch([47.125 97.7 132.7 167.7 202.7 132.7 82.125 47.125 ]," "[821.85 821.85 856.85 821.85 856.85 856.85 856.85 821.85 ],[1 1 1 ]);\npatch([82.125 132.7 97.7 47.125 82.125 ],[78" "6.85 786.85 821.85 821.85 786.85 ],[0.931 0.946 0.973 ]);\npatch([47.125 97.7 132.7 82.125 47.125 ],[751.85 751.85 " "786.85 786.85 751.85 ],[1 1 1 ]);\npatch([82.125 202.7 167.7 132.7 97.7 47.125 82.125 ],[716.85 716.85 751.85 716.8" "5 751.85 751.85 716.85 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: be" "gin icon text');\ncolor('black');port_label('input',1,'AXI_ARESETN');\ncolor('black');port_label('input',2,'S_AXI_A" "RADDR');\ncolor('black');port_label('input',3,'S_AXI_ARBURST');\ncolor('black');port_label('input',4,'S_AXI_ARCACHE" "');\ncolor('black');port_label('input',5,'S_AXI_ARID');\ncolor('black');port_label('input',6,'S_AXI_ARLEN');\ncolor" "('black');port_label('input',7,'S_AXI_ARLOCK');\ncolor('black');port_label('input',8,'S_AXI_ARPROT');\ncolor('black" "');port_label('input',9,'S_AXI_ARSIZE');\ncolor('black');port_label('input',10,'S_AXI_ARVALID');\ncolor('black');po" "rt_label('input',11,'S_AXI_AWADDR');\ncolor('black');port_label('input',12,'S_AXI_AWBURST');\ncolor('black');port_l" "abel('input',13,'S_AXI_AWCACHE');\ncolor('black');port_label('input',14,'S_AXI_AWID');\ncolor('black');port_label('" "input',15,'S_AXI_AWLEN');\ncolor('black');port_label('input',16,'S_AXI_AWLOCK');\ncolor('black');port_label('input'" ",17,'S_AXI_AWPROT');\ncolor('black');port_label('input',18,'S_AXI_AWSIZE');\ncolor('black');port_label('input',19,'" "S_AXI_AWVALID');\ncolor('black');port_label('input',20,'S_AXI_BREADY');\ncolor('black');port_label('input',21,'S_AX" "I_RREADY');\ncolor('black');port_label('input',22,'S_AXI_WDATA');\ncolor('black');port_label('input',23,'S_AXI_WLAS" "T');\ncolor('black');port_label('input',24,'S_AXI_WSTRB');\ncolor('black');port_label('input',25,'S_AXI_WVALID');\n" "color('black');port_label('input',26,'sm_RX_PKT_RSSI_CD_dout');\ncolor('black');port_label('input',27,'sm_RX_PKT_AG" "C_GAINS_dout');\ncolor('black');port_label('input',28,'sm_RX_PKT_RSSI_AB_dout');\ncolor('black');port_label('input'" ",29,'sm_CFO_EST_TIME_DOMAIN_dout');\ncolor('black');port_label('input',30,'sm_Status_dout');\ncolor('black');port_l" "abel('input',31,'sm_PKT_DET_COUNT_DSSS_dout');\ncolor('black');port_label('input',32,'sm_PKT_DET_COUNT_OFDM_dout');" "\ncolor('black');port_label('input',33,'sm_RXIQ_MAG_SUM_RFA_dout');\ncolor('black');port_label('input',34,'sm_RSSI_" "THRESH_dout');\ncolor('black');port_label('input',35,'sm_CONFIG_dout');\ncolor('black');port_label('input',36,'sm_D" "SSS_RX_CONFIG_dout');\ncolor('black');port_label('input',37,'sm_PKT_BUF_SEL_dout');\ncolor('black');port_label('inp" "ut',38,'sm_PKTDET_AUTOCORR_CONFIG_dout');\ncolor('black');port_label('input',39,'sm_FEC_CONFIG_dout');\ncolor('blac" "k');port_label('input',40,'sm_Control_dout');\ncolor('black');port_label('input',41,'sm_LTS_Corr_PeakType_Thresh_do" "ut');\ncolor('black');port_label('input',42,'sm_CHAN_EST_SMOOTHING_dout');\ncolor('black');port_label('input',43,'s" "m_LTS_Corr_Thresh_dout');\ncolor('black');port_label('input',44,'sm_PKTDET_DSSS_CONFIG_dout');\ncolor('black');port" "_label('input',45,'sm_LTS_Corr_Config_dout');\ncolor('black');port_label('input',46,'sm_PHY_CCA_CONFIG_dout');\ncol" "or('black');port_label('input',47,'sm_PKTBUF_MAX_WRITE_ADDR_dout');\ncolor('black');port_label('input',48,'sm_FFT_C" "onfig_dout');\ncolor('black');port_label('input',49,'sm_PKTDET_RSSI_CONFIG_dout');\ncolor('black');port_label('inpu" "t',50,'sm_RAMS_ADDR_WREN_dout');\ncolor('black');port_label('input',51,'sm_MASK_1_RAM_WR_DATA_dout');\ncolor('black" "');port_label('input',52,'sm_TARGET_RAM_WR_DATA_dout');\ncolor('black');port_label('output',1,'S_AXI_ARREADY');\nco" "lor('black');port_label('output',2,'S_AXI_AWREADY');\ncolor('black');port_label('output',3,'S_AXI_BID');\ncolor('bl" "ack');port_label('output',4,'S_AXI_BRESP');\ncolor('black');port_label('output',5,'S_AXI_BVALID');\ncolor('black');" "port_label('output',6,'S_AXI_RDATA');\ncolor('black');port_label('output',7,'S_AXI_RID');\ncolor('black');port_labe" "l('output',8,'S_AXI_RLAST');\ncolor('black');port_label('output',9,'S_AXI_RRESP');\ncolor('black');port_label('outp" "ut',10,'S_AXI_RVALID');\ncolor('black');port_label('output',11,'S_AXI_WREADY');\ncolor('black');port_label('output'" ",12,'sm_RSSI_THRESH_din');\ncolor('black');port_label('output',13,'sm_RSSI_THRESH_en');\ncolor('black');port_label(" "'output',14,'sm_CONFIG_din');\ncolor('black');port_label('output',15,'sm_CONFIG_en');\ncolor('black');port_label('o" "utput',16,'sm_DSSS_RX_CONFIG_din');\ncolor('black');port_label('output',17,'sm_DSSS_RX_CONFIG_en');\ncolor('black')" ";port_label('output',18,'sm_PKT_BUF_SEL_din');\ncolor('black');port_label('output',19,'sm_PKT_BUF_SEL_en');\ncolor(" "'black');port_label('output',20,'sm_PKTDET_AUTOCORR_CONFIG_din');\ncolor('black');port_label('output',21,'sm_PKTDET" "_AUTOCORR_CONFIG_en');\ncolor('black');port_label('output',22,'sm_FEC_CONFIG_din');\ncolor('black');port_label('out" "put',23,'sm_FEC_CONFIG_en');\ncolor('black');port_label('output',24,'sm_Control_din');\ncolor('black');port_label('" "output',25,'sm_Control_en');\ncolor('black');port_label('output',26,'sm_LTS_Corr_PeakType_Thresh_din');\ncolor('bla" "ck');port_label('output',27,'sm_LTS_Corr_PeakType_Thresh_en');\ncolor('black');port_label('output',28,'sm_CHAN_EST_" "SMOOTHING_din');\ncolor('black');port_label('output',29,'sm_CHAN_EST_SMOOTHING_en');\ncolor('black');port_label('ou" "tput',30,'sm_LTS_Corr_Thresh_din');\ncolor('black');port_label('output',31,'sm_LTS_Corr_Thresh_en');\ncolor('black'" ");port_label('output',32,'sm_PKTDET_DSSS_CONFIG_din');\ncolor('black');port_label('output',33,'sm_PKTDET_DSSS_CONFI" "G_en');\ncolor('black');port_label('output',34,'sm_LTS_Corr_Config_din');\ncolor('black');port_label('output',35,'s" "m_LTS_Corr_Config_en');\ncolor('black');port_label('output',36,'sm_PHY_CCA_CONFIG_din');\ncolor('black');port_label" "('output',37,'sm_PHY_CCA_CONFIG_en');\ncolor('black');port_label('output',38,'sm_PKTBUF_MAX_WRITE_ADDR_din');\ncolo" "r('black');port_label('output',39,'sm_PKTBUF_MAX_WRITE_ADDR_en');\ncolor('black');port_label('output',40,'sm_FFT_Co" "nfig_din');\ncolor('black');port_label('output',41,'sm_FFT_Config_en');\ncolor('black');port_label('output',42,'sm_" "PKTDET_RSSI_CONFIG_din');\ncolor('black');port_label('output',43,'sm_PKTDET_RSSI_CONFIG_en');\ncolor('black');port_" "label('output',44,'sm_RAMS_ADDR_WREN_din');\ncolor('black');port_label('output',45,'sm_RAMS_ADDR_WREN_en');\ncolor(" "'black');port_label('output',46,'sm_MASK_1_RAM_WR_DATA_din');\ncolor('black');port_label('output',47,'sm_MASK_1_RAM" "_WR_DATA_en');\ncolor('black');port_label('output',48,'sm_TARGET_RAM_WR_DATA_din');\ncolor('black');port_label('out" "put',49,'sm_TARGET_RAM_WR_DATA_en');\nfprintf('','COMMENT: end icon text');" } Line { SrcBlock "memmap" SrcPort 49 Points [5, 0; 0, 355] DstBlock "To Register18" DstPort 2 } Line { SrcBlock "memmap" SrcPort 48 Points [5, 0; 0, 355] DstBlock "To Register18" DstPort 1 } Line { SrcBlock "memmap" SrcPort 13 Points [5, 0; 0, -125] DstBlock "To Register" DstPort 2 } Line { SrcBlock "memmap" SrcPort 12 Points [5, 0; 0, -125] DstBlock "To Register" DstPort 1 } Line { SrcBlock "memmap" SrcPort 45 Points [5, 0; 0, 300] DstBlock "To Register16" DstPort 2 } Line { SrcBlock "memmap" SrcPort 44 Points [5, 0; 0, 300] DstBlock "To Register16" DstPort 1 } Line { SrcBlock "memmap" SrcPort 19 Points [10, 0] DstBlock "To Register3" DstPort 2 } Line { SrcBlock "memmap" SrcPort 18 Points [5, 0; 0, -45] DstBlock "To Register3" DstPort 1 } Line { SrcBlock "memmap" SrcPort 43 Points [5, 0; 0, 275] DstBlock "To Register15" DstPort 2 } Line { SrcBlock "memmap" SrcPort 42 Points [5, 0; 0, 275] DstBlock "To Register15" DstPort 1 } Line { SrcBlock "memmap" SrcPort 33 Points [5, 0; 0, 140] DstBlock "To Register10" DstPort 2 } Line { SrcBlock "memmap" SrcPort 32 Points [5, 0; 0, 140] DstBlock "To Register10" DstPort 1 } Line { SrcBlock "memmap" SrcPort 21 Points [10, 0] DstBlock "To Register4" DstPort 2 } Line { SrcBlock "memmap" SrcPort 20 Points [10, 0] DstBlock "To Register4" DstPort 1 } Line { SrcBlock "memmap" SrcPort 39 Points [5, 0; 0, 220] DstBlock "To Register13" DstPort 2 } Line { SrcBlock "memmap" SrcPort 38 Points [5, 0; 0, 220] DstBlock "To Register13" DstPort 1 } Line { SrcBlock "memmap" SrcPort 37 Points [5, 0; 0, 195] DstBlock "To Register12" DstPort 2 } Line { SrcBlock "memmap" SrcPort 36 Points [5, 0; 0, 195] DstBlock "To Register12" DstPort 1 } Line { SrcBlock "memmap" SrcPort 47 Points [5, 0; 0, 325] DstBlock "To Register17" DstPort 2 } Line { SrcBlock "memmap" SrcPort 46 Points [5, 0; 0, 325] DstBlock "To Register17" DstPort 1 } Line { SrcBlock "memmap" SrcPort 31 Points [5, 0; 0, 115] DstBlock "To Register9" DstPort 2 } Line { SrcBlock "memmap" SrcPort 30 Points [5, 0; 0, 115] DstBlock "To Register9" DstPort 1 } Line { SrcBlock "memmap" SrcPort 27 Points [5, 0; 0, 60] DstBlock "To Register7" DstPort 2 } Line { SrcBlock "memmap" SrcPort 26 Points [5, 0; 0, 60] DstBlock "To Register7" DstPort 1 } Line { SrcBlock "memmap" SrcPort 35 Points [5, 0; 0, 165] DstBlock "To Register11" DstPort 2 } Line { SrcBlock "memmap" SrcPort 34 Points [5, 0; 0, 165] DstBlock "To Register11" DstPort 1 } Line { SrcBlock "memmap" SrcPort 41 Points [5, 0; 0, 245] DstBlock "To Register14" DstPort 2 } Line { SrcBlock "memmap" SrcPort 40 Points [5, 0; 0, 245] DstBlock "To Register14" DstPort 1 } Line { SrcBlock "memmap" SrcPort 23 Points [10, 0] DstBlock "To Register5" DstPort 2 } Line { SrcBlock "memmap" SrcPort 22 Points [10, 0] DstBlock "To Register5" DstPort 1 } Line { SrcBlock "memmap" SrcPort 17 Points [5, 0; 0, -75] DstBlock "To Register2" DstPort 2 } Line { SrcBlock "memmap" SrcPort 16 Points [5, 0; 0, -75] DstBlock "To Register2" DstPort 1 } Line { SrcBlock "memmap" SrcPort 25 Points [5, 0; 0, 35] DstBlock "To Register6" DstPort 2 } Line { SrcBlock "memmap" SrcPort 24 Points [10, 0] DstBlock "To Register6" DstPort 1 } Line { SrcBlock "memmap" SrcPort 15 Points [5, 0; 0, -100] DstBlock "To Register1" DstPort 2 } Line { SrcBlock "memmap" SrcPort 14 Points [5, 0; 0, -100] DstBlock "To Register1" DstPort 1 } Line { SrcBlock "memmap" SrcPort 29 Points [5, 0; 0, 85] DstBlock "To Register8" DstPort 2 } Line { SrcBlock "memmap" SrcPort 28 Points [5, 0; 0, 85] DstBlock "To Register8" DstPort 1 } Line { SrcBlock "memmap" SrcPort 11 Points [5, 0; 0, -150] DstBlock "S_AXI_WREADY" DstPort 1 } Line { SrcBlock "memmap" SrcPort 10 Points [5, 0; 0, -170] DstBlock "S_AXI_RVALID" DstPort 1 } Line { SrcBlock "memmap" SrcPort 9 Points [5, 0; 0, -190] DstBlock "S_AXI_RRESP" DstPort 1 } Line { SrcBlock "memmap" SrcPort 8 Points [5, 0; 0, -210] DstBlock "S_AXI_RLAST" DstPort 1 } Line { SrcBlock "memmap" SrcPort 7 Points [5, 0; 0, -225] DstBlock "S_AXI_RID" DstPort 1 } Line { SrcBlock "memmap" SrcPort 6 Points [5, 0; 0, -245] DstBlock "S_AXI_RDATA" DstPort 1 } Line { SrcBlock "memmap" SrcPort 5 Points [5, 0; 0, -265] DstBlock "S_AXI_BVALID" DstPort 1 } Line { SrcBlock "memmap" SrcPort 4 Points [5, 0; 0, -285] DstBlock "S_AXI_BRESP" DstPort 1 } Line { SrcBlock "memmap" SrcPort 3 Points [5, 0; 0, -305] DstBlock "S_AXI_BID" DstPort 1 } Line { SrcBlock "memmap" SrcPort 2 Points [5, 0; 0, -325] DstBlock "S_AXI_AWREADY" DstPort 1 } Line { SrcBlock "memmap" SrcPort 1 Points [5, 0; 0, -345] DstBlock "S_AXI_ARREADY" DstPort 1 } Line { SrcBlock "S_AXI_WVALID" SrcPort 1 Points [5, 0; 0, -155] DstBlock "memmap" DstPort 25 } Line { SrcBlock "S_AXI_WSTRB" SrcPort 1 Points [5, 0; 0, -135] DstBlock "memmap" DstPort 24 } Line { SrcBlock "S_AXI_WLAST" SrcPort 1 Points [5, 0; 0, -115] DstBlock "memmap" DstPort 23 } Line { SrcBlock "S_AXI_WDATA" SrcPort 1 Points [5, 0; 0, -95] DstBlock "memmap" DstPort 22 } Line { SrcBlock "S_AXI_RREADY" SrcPort 1 Points [5, 0; 0, -75] DstBlock "memmap" DstPort 21 } Line { SrcBlock "S_AXI_BREADY" SrcPort 1 Points [5, 0; 0, -55] DstBlock "memmap" DstPort 20 } Line { SrcBlock "S_AXI_AWVALID" SrcPort 1 Points [5, 0; 0, -40] DstBlock "memmap" DstPort 19 } Line { SrcBlock "S_AXI_AWSIZE" SrcPort 1 Points [10, 0] DstBlock "memmap" DstPort 18 } Line { SrcBlock "S_AXI_AWPROT" SrcPort 1 DstBlock "memmap" DstPort 17 } Line { SrcBlock "S_AXI_AWLOCK" SrcPort 1 Points [10, 0] DstBlock "memmap" DstPort 16 } Line { SrcBlock "S_AXI_AWLEN" SrcPort 1 Points [5, 0; 0, 40] DstBlock "memmap" DstPort 15 } Line { SrcBlock "S_AXI_AWID" SrcPort 1 Points [5, 0; 0, 60] DstBlock "memmap" DstPort 14 } Line { SrcBlock "S_AXI_AWCACHE" SrcPort 1 Points [5, 0; 0, 80] DstBlock "memmap" DstPort 13 } Line { SrcBlock "S_AXI_AWBURST" SrcPort 1 Points [5, 0; 0, 100] DstBlock "memmap" DstPort 12 } Line { SrcBlock "S_AXI_AWADDR" SrcPort 1 Points [5, 0; 0, 115] DstBlock "memmap" DstPort 11 } Line { SrcBlock "S_AXI_ARVALID" SrcPort 1 Points [5, 0; 0, 135] DstBlock "memmap" DstPort 10 } Line { SrcBlock "S_AXI_ARSIZE" SrcPort 1 Points [5, 0; 0, 155] DstBlock "memmap" DstPort 9 } Line { SrcBlock "S_AXI_ARPROT" SrcPort 1 Points [5, 0; 0, 175] DstBlock "memmap" DstPort 8 } Line { SrcBlock "S_AXI_ARLOCK" SrcPort 1 Points [5, 0; 0, 195] DstBlock "memmap" DstPort 7 } Line { SrcBlock "S_AXI_ARLEN" SrcPort 1 Points [5, 0; 0, 215] DstBlock "memmap" DstPort 6 } Line { SrcBlock "S_AXI_ARID" SrcPort 1 Points [5, 0; 0, 235] DstBlock "memmap" DstPort 5 } Line { SrcBlock "S_AXI_ARCACHE" SrcPort 1 Points [5, 0; 0, 250] DstBlock "memmap" DstPort 4 } Line { SrcBlock "S_AXI_ARBURST" SrcPort 1 Points [5, 0; 0, 270] DstBlock "memmap" DstPort 3 } Line { SrcBlock "S_AXI_ARADDR" SrcPort 1 Points [5, 0; 0, 290] DstBlock "memmap" DstPort 2 } Line { SrcBlock "AXI_ARESETN" SrcPort 1 Points [10, 0] DstBlock "memmap" DstPort 1 } Line { SrcBlock "To Register18" SrcPort 1 Points [0, -55; -360, 0] DstBlock "memmap" DstPort 52 } Line { SrcBlock "From Register4" SrcPort 1 Points [10, 0; 0, -420] DstBlock "memmap" DstPort 30 } Line { SrcBlock "From Register" SrcPort 1 Points [10, 0; 0, -190] DstBlock "memmap" DstPort 26 } Line { SrcBlock "From Register2" SrcPort 1 Points [10, 0; 0, -305] DstBlock "memmap" DstPort 28 } Line { SrcBlock "From Register1" SrcPort 1 Points [10, 0; 0, -250] DstBlock "memmap" DstPort 27 } Line { SrcBlock "From Register7" SrcPort 1 Points [10, 0; 0, -590] DstBlock "memmap" DstPort 33 } Line { SrcBlock "To Register" SrcPort 1 Points [0, -55; -85, 0; 0, -235; -280, 0; 0, 1015] DstBlock "memmap" DstPort 34 } Line { SrcBlock "To Register16" SrcPort 1 Points [0, -50; -365, 0; 0, -130] DstBlock "memmap" DstPort 50 } Line { SrcBlock "From Register6" SrcPort 1 Points [10, 0; 0, -530] DstBlock "memmap" DstPort 32 } Line { SrcBlock "From Register5" SrcPort 1 Points [10, 0; 0, -475] DstBlock "memmap" DstPort 31 } Line { SrcBlock "To Register3" SrcPort 1 Points [0, 50; -85, 0; 0, 980; -280, 0; 0, -475] DstBlock "memmap" DstPort 37 } Line { SrcBlock "To Register15" SrcPort 1 Points [0, -35; -90, 0; 0, 25; -275, 0; 0, -115] DstBlock "memmap" DstPort 49 } Line { SrcBlock "To Register10" SrcPort 1 Points [0, 50; -85, 0; 0, 375; -280, 0; 0, -265] DstBlock "memmap" DstPort 44 } Line { SrcBlock "To Register4" SrcPort 1 Points [0, 50; -85, 0; 0, 895; -280, 0; 0, -445] DstBlock "memmap" DstPort 38 } Line { SrcBlock "To Register13" SrcPort 1 Points [0, 50; -85, 0; 0, 115; -280, 0; 0, -175] DstBlock "memmap" DstPort 47 } Line { SrcBlock "To Register12" SrcPort 1 Points [0, 50; -85, 0; 0, 200; -280, 0; 0, -205] DstBlock "memmap" DstPort 46 } Line { SrcBlock "To Register17" SrcPort 1 Points [0, -50; -365, 0; 0, -185] DstBlock "memmap" DstPort 51 } Line { SrcBlock "To Register9" SrcPort 1 Points [0, 50; -85, 0; 0, 460; -280, 0; 0, -295] DstBlock "memmap" DstPort 43 } Line { SrcBlock "To Register7" SrcPort 1 Points [0, 50; -85, 0; 0, 635; -280, 0; 0, -355] DstBlock "memmap" DstPort 41 } Line { SrcBlock "To Register11" SrcPort 1 Points [0, 55; -85, 0; 0, 285; -280, 0; 0, -235] DstBlock "memmap" DstPort 45 } Line { SrcBlock "To Register14" SrcPort 1 Points [0, 55; -90, 0; 0, 25; -275, 0; 0, -145] DstBlock "memmap" DstPort 48 } Line { SrcBlock "To Register5" SrcPort 1 Points [0, 55; -85, 0; 0, 805; -280, 0; 0, -415] DstBlock "memmap" DstPort 39 } Line { SrcBlock "To Register2" SrcPort 1 Points [0, -50; -85, 0; 0, -410; -280, 0; 0, 1075] DstBlock "memmap" DstPort 36 } Line { SrcBlock "To Register6" SrcPort 1 Points [0, 50; -85, 0; 0, 720; -280, 0; 0, -385] DstBlock "memmap" DstPort 40 } Line { SrcBlock "To Register1" SrcPort 1 Points [0, -50; -85, 0; 0, -325; -280, 0; 0, 1045] DstBlock "memmap" DstPort 35 } Line { SrcBlock "To Register8" SrcPort 1 Points [0, 55; -85, 0; 0, 545; -280, 0; 0, -325] DstBlock "memmap" DstPort 42 } Line { SrcBlock "From Register3" SrcPort 1 Points [10, 0; 0, -360] DstBlock "memmap" DstPort 29 } Line { SrcBlock "S_AXI_WREADY" SrcPort 1 DstBlock "Terminator10" DstPort 1 } Line { SrcBlock "S_AXI_RVALID" SrcPort 1 DstBlock "Terminator9" DstPort 1 } Line { SrcBlock "S_AXI_RRESP" SrcPort 1 DstBlock "Terminator8" DstPort 1 } Line { SrcBlock "S_AXI_RLAST" SrcPort 1 DstBlock "Terminator7" DstPort 1 } Line { SrcBlock "S_AXI_RID" SrcPort 1 DstBlock "Terminator6" DstPort 1 } Line { SrcBlock "S_AXI_RDATA" SrcPort 1 DstBlock "Terminator5" DstPort 1 } Line { SrcBlock "S_AXI_BVALID" SrcPort 1 DstBlock "Terminator4" DstPort 1 } Line { SrcBlock "S_AXI_BRESP" SrcPort 1 DstBlock "Terminator3" DstPort 1 } Line { SrcBlock "S_AXI_BID" SrcPort 1 DstBlock "Terminator2" DstPort 1 } Line { SrcBlock "S_AXI_AWREADY" SrcPort 1 DstBlock "Terminator1" DstPort 1 } Line { SrcBlock "S_AXI_ARREADY" SrcPort 1 DstBlock "Terminator" DstPort 1 } Line { SrcBlock "Constant24" SrcPort 1 DstBlock "S_AXI_WVALID" DstPort 1 } Line { SrcBlock "Constant23" SrcPort 1 DstBlock "S_AXI_WSTRB" DstPort 1 } Line { SrcBlock "Constant22" SrcPort 1 DstBlock "S_AXI_WLAST" DstPort 1 } Line { SrcBlock "Constant21" SrcPort 1 DstBlock "S_AXI_WDATA" DstPort 1 } Line { SrcBlock "Constant20" SrcPort 1 DstBlock "S_AXI_RREADY" DstPort 1 } Line { SrcBlock "Constant19" SrcPort 1 DstBlock "S_AXI_BREADY" DstPort 1 } Line { SrcBlock "Constant18" SrcPort 1 DstBlock "S_AXI_AWVALID" DstPort 1 } Line { SrcBlock "Constant17" SrcPort 1 DstBlock "S_AXI_AWSIZE" DstPort 1 } Line { SrcBlock "Constant16" SrcPort 1 DstBlock "S_AXI_AWPROT" DstPort 1 } Line { SrcBlock "Constant15" SrcPort 1 DstBlock "S_AXI_AWLOCK" DstPort 1 } Line { SrcBlock "Constant14" SrcPort 1 DstBlock "S_AXI_AWLEN" DstPort 1 } Line { SrcBlock "Constant13" SrcPort 1 DstBlock "S_AXI_AWID" DstPort 1 } Line { SrcBlock "Constant12" SrcPort 1 DstBlock "S_AXI_AWCACHE" DstPort 1 } Line { SrcBlock "Constant11" SrcPort 1 DstBlock "S_AXI_AWBURST" DstPort 1 } Line { SrcBlock "Constant10" SrcPort 1 DstBlock "S_AXI_AWADDR" DstPort 1 } Line { SrcBlock "Constant9" SrcPort 1 DstBlock "S_AXI_ARVALID" DstPort 1 } Line { SrcBlock "Constant8" SrcPort 1 DstBlock "S_AXI_ARSIZE" DstPort 1 } Line { SrcBlock "Constant7" SrcPort 1 DstBlock "S_AXI_ARPROT" DstPort 1 } Line { SrcBlock "Constant6" SrcPort 1 DstBlock "S_AXI_ARLOCK" DstPort 1 } Line { SrcBlock "Constant5" SrcPort 1 DstBlock "S_AXI_ARLEN" DstPort 1 } Line { SrcBlock "Constant4" SrcPort 1 DstBlock "S_AXI_ARID" DstPort 1 } Line { SrcBlock "Constant3" SrcPort 1 DstBlock "S_AXI_ARCACHE" DstPort 1 } Line { SrcBlock "Constant2" SrcPort 1 DstBlock "S_AXI_ARBURST" DstPort 1 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "S_AXI_ARADDR" DstPort 1 } Line { SrcBlock "Constant" SrcPort 1 DstBlock "AXI_ARESETN" DstPort 1 } } } Block { BlockType SubSystem Name "FCS & Pkt Buf" SID "3008" Ports [2] Position [1085, 74, 1140, 216] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "FCS & Pkt Buf" Location [1550, 284, 2016, 624] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "138" Block { BlockType Inport Name "DSSS data" SID "3009" Position [490, 253, 520, 267] IconDisplay "Port number" } Block { BlockType Inport Name "OFDM data" SID "3010" Position [490, 333, 520, 347] Port "2" IconDisplay "Port number" } Block { BlockType BusSelector Name "Bus\nSelector" SID "3011" Ports [1, 4] Position [580, 302, 590, 378] ZOrder -3 ShowName off OutputSignals "byte_valid,byte_index,byte,last_byte" Port { PortNumber 1 Name "" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 2 Name "" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 3 Name "" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 4 Name "" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType BusSelector Name "Bus\nSelector1" SID "3012" Ports [1, 4] Position [580, 222, 590, 298] ZOrder -3 ShowName off OutputSignals "byte_valid,byte_index,byte,last_byte" Port { PortNumber 1 Name "" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 2 Name "" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 3 Name "" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 4 Name "" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Scope Name "Bytes In" SID "3013" Ports [8] Position [855, 215, 890, 385] ZOrder -3 Floating off Location [1, 45, 1833, 1199] Open off NumInputPorts "8" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" } List { ListType ScopeGraphics FigureColor "[0.5 0.5 0.5]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "10000" YMin "0~0~0~-1~-1~-1~-1~-1" YMax "1~90~225~1~1~1~1~1" SaveName "ScopeData36" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType SubSystem Name "FCS Calc" SID "3014" Ports [2] Position [605, 498, 680, 542] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "FCS Calc" Location [168, 748, 1956, 1452] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "DSSS data" SID "3015" Position [280, 133, 310, 147] IconDisplay "Port number" } Block { BlockType Inport Name "OFDM data" SID "3016" Position [280, 223, 310, 237] Port "2" IconDisplay "Port number" } Block { BlockType BusSelector Name "Bus\nSelector" SID "3017" Ports [1, 4] Position [380, 192, 390, 268] ZOrder -3 ShowName off OutputSignals "byte_valid,byte_index,byte,last_byte" Port { PortNumber 1 Name "" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 2 Name "" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 3 Name "" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 4 Name "" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType BusSelector Name "Bus\nSelector1" SID "3018" Ports [1, 4] Position [380, 102, 390, 178] ZOrder -3 ShowName off OutputSignals "byte_valid,byte_index,byte,last_byte" Port { PortNumber 1 Name "" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 2 Name "" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 3 Name "" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 4 Name "" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType SubSystem Name "CRC32 Calc" SID "3019" Ports [3, 1] Position [920, 520, 1035, 590] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "CRC32 Calc" Location [442, 320, 2118, 1280] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "byte_valid" SID "3020" Position [605, 593, 635, 607] IconDisplay "Port number" } Block { BlockType Inport Name "byte" SID "3021" Position [135, 478, 165, 492] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "rst" SID "3022" Position [485, 578, 515, 592] Port "3" IconDisplay "Port number" } Block { BlockType Reference Name "24LSB" SID "3023" Ports [1, 1] Position [530, 276, 575, 304] BlockMirror on LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type" " is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardwar" "e notes: In hardware this block costs nothing." nbits "24" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,28,1,1,white,blue,0,1fd851a7,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 28 28 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 28 28 0 ]);\npatch([13.1 18.88 22.88 26.88 30.88 22.88 17.1 13.1 ],[18.44 18.44 22" ".44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([17.1 22.88 18.88 13.1 17.1 ],[14.44 14.44 18.44 18.44 14.44" " ],[0.931 0.946 0.973 ]);\npatch([13.1 18.88 22.88 17.1 13.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\npatch(" "[17.1 30.88 26.88 22.88 18.88 13.1 17.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nfprintf" "('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output'," "1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "8MSB" SID "3024" Ports [1, 1] Position [530, 221, 575, 249] BlockMirror on LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type" " is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardwar" "e notes: In hardware this block costs nothing." nbits "8" boolean_output off mode "Upper Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,28,1,1,white,blue,0,1fd851a7,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 28 28 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 28 28 0 ]);\npatch([13.1 18.88 22.88 26.88 30.88 22.88 17.1 13.1 ],[18.44 18.44 22" ".44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([17.1 22.88 18.88 13.1 17.1 ],[14.44 14.44 18.44 18.44 14.44" " ],[0.931 0.946 0.973 ]);\npatch([13.1 18.88 22.88 17.1 13.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\npatch(" "[17.1 30.88 26.88 22.88 18.88 13.1 17.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nfprintf" "('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output'," "1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Assert1" SID "3025" Ports [1, 1] Position [880, 468, 915, 482] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Assert" SourceType "Xilinx Assert Block" infoedit "Asserts a user-defined sample rate and/or type on a signal.

Hardware notes: In hardware this b" "lock costs nothing." assert_type off type_source "Explicitly" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "16" bin_pt "14" preci_type "Single" exp_width "8" frac_width "24" assert_rate on rate_source "Explicitly" period "1" output_port on has_advanced_control "0" sggui_pos "20,20,356,423" block_type "assert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,14,1,1,white,blue,0,9657e937,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 14 14 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[9.22 9.22 1" "1.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[7.22 7.22 9.22 9.22 7.22 ]," "[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([14.5" "5 21.44 19.44 17.44 15.44 12.55 14.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('Assert');\nfprint" "f('','COMMENT: end icon text');" } Block { BlockType Reference Name "CRC Remainders1" SID "3026" Ports [1, 1] Position [510, 439, 560, 491] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/ROM" SourceType "Xilinx Single Port Read-Only Memory Block" depth "256" initVector "CRC_Table32" distributed_mem "Distributed memory" rst off init_reg "0" en off latency "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" dbl_ovrd off optimize "Area" use_rpm off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "20,20,348,308" block_type "sprom" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,52,1,1,white,blue,0,eff69a7e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 52 52 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 50 50 0 0 ],[0 0 52 52 0 ]);\npatch([9.425 19.54 26.54 33.54 40.54 26.54 16.425 9.425 ],[33.77 33.7" "7 40.77 33.77 40.77 40.77 40.77 33.77 ],[1 1 1 ]);\npatch([16.425 26.54 19.54 9.425 16.425 ],[26.77 26.77 33.77 33" ".77 26.77 ],[0.931 0.946 0.973 ]);\npatch([9.425 19.54 26.54 16.425 9.425 ],[19.77 19.77 26.77 26.77 19.77 ],[1 1 " "1 ]);\npatch([16.425 40.54 33.54 26.54 19.54 9.425 16.425 ],[12.77 12.77 19.77 12.77 19.77 19.77 12.77 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('input',1,'addr');\n\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Concat1" SID "3027" Ports [2, 1] Position [525, 320, 575, 375] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point at z" "ero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,55,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 55 55 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 50 50 0 0 ],[0 0 55 55 0 ]);\npatch([9.425 19.54 26.54 33.54 40.54 26.54 16.425 9.425 ],[34.77 34.7" "7 41.77 34.77 41.77 41.77 41.77 34.77 ],[1 1 1 ]);\npatch([16.425 26.54 19.54 9.425 16.425 ],[27.77 27.77 34.77 34" ".77 27.77 ],[0.931 0.946 0.973 ]);\npatch([9.425 19.54 26.54 16.425 9.425 ],[20.77 20.77 27.77 27.77 20.77 ],[1 1 " "1 ]);\npatch([16.425 40.54 33.54 26.54 19.54 9.425 16.425 ],[13.77 13.77 20.77 13.77 20.77 20.77 13.77 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fontsize{20}\\}'" ",'texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant1" SID "3028" Ports [0, 1] Position [460, 347, 485, 373] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "8" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,26,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 " "19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 1" "3.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\n" "patch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('out" "put',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant3" SID "3029" Ports [0, 1] Position [900, 495, 975, 515] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "hex2dec('C704DD7B')" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "75,20,0,1,white,blue,0,8e9231cf,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 75 75 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 75 75 0 0 ],[0 0 20 20 0 ]);\npatch([32.55 35.44 37.44 39.44 41.44 37.44 34.55 32.55 ],[12.22 12.22" " 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([34.55 37.44 35.44 32.55 34.55 ],[10.22 10.22 12.22 12.22" " 10.22 ],[0.931 0.946 0.973 ]);\npatch([32.55 35.44 37.44 34.55 32.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\n" "patch([34.55 41.44 39.44 37.44 35.44 32.55 34.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('outp" "ut',1,'3338984827');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Endian Swap" SID "3030" Ports [1, 1] Position [225, 468, 285, 502] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Endian Swap" Location [36, 222, 2218, 1427] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "B" SID "3031" Position [270, 313, 300, 327] IconDisplay "Port number" } Block { BlockType Reference Name "Concat" SID "3032" Ports [8, 1] Position [530, 296, 565, 589] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point " "at zero." num_inputs "8" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "35,293,8,1,white,blue,0,6fe74153,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 293 293 0 ],[0.77 0." "82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 293 293 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[151.5" "5 151.55 156.55 151.55 156.55 156.55 156.55 151.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[146.55 " "146.55 151.55 151.55 146.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[141.55 141.55 146.5" "5 146.55 141.55 ],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[136.55 136.55 141.55 136.55 141." "55 141.55 136.55 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin" " icon text');\ncolor('black');port_label('input',1,'hi');\n\n\n\n\n\n\ncolor('black');port_label('input',8,'lo')" ";\n\ncolor('black');disp('\\fontsize{20}\\}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b0" SID "3033" Ports [1, 1] Position [435, 311, 475, 329] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b1" SID "3034" Ports [1, 1] Position [435, 346, 475, 364] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "1" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b2" SID "3035" Ports [1, 1] Position [435, 381, 475, 399] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "2" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b3" SID "3036" Ports [1, 1] Position [435, 416, 475, 434] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "3" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b4" SID "3037" Ports [1, 1] Position [435, 451, 475, 469] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "4" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b5" SID "3038" Ports [1, 1] Position [435, 486, 475, 504] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "5" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b6" SID "3039" Ports [1, 1] Position [435, 521, 475, 539] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "6" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b7" SID "3040" Ports [1, 1] Position [435, 556, 475, 574] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "7" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "I" SID "3041" Position [650, 438, 680, 452] IconDisplay "Port number" } Line { SrcBlock "B" SrcPort 1 Points [100, 0] Branch { DstBlock "b0" DstPort 1 } Branch { Points [0, 35] Branch { DstBlock "b1" DstPort 1 } Branch { Points [0, 35] Branch { DstBlock "b2" DstPort 1 } Branch { Points [0, 35] Branch { DstBlock "b3" DstPort 1 } Branch { Points [0, 35] Branch { DstBlock "b4" DstPort 1 } Branch { Points [0, 35] Branch { DstBlock "b5" DstPort 1 } Branch { Points [0, 35] Branch { DstBlock "b6" DstPort 1 } Branch { Points [0, 35] DstBlock "b7" DstPort 1 } } } } } } } } Line { SrcBlock "b0" SrcPort 1 DstBlock "Concat" DstPort 1 } Line { SrcBlock "b1" SrcPort 1 DstBlock "Concat" DstPort 2 } Line { SrcBlock "b2" SrcPort 1 DstBlock "Concat" DstPort 3 } Line { SrcBlock "b3" SrcPort 1 DstBlock "Concat" DstPort 4 } Line { SrcBlock "b4" SrcPort 1 DstBlock "Concat" DstPort 5 } Line { SrcBlock "b5" SrcPort 1 DstBlock "Concat" DstPort 6 } Line { SrcBlock "b6" SrcPort 1 DstBlock "Concat" DstPort 7 } Line { SrcBlock "Concat" SrcPort 1 DstBlock "I" DstPort 1 } Line { SrcBlock "b7" SrcPort 1 DstBlock "Concat" DstPort 8 } } } Block { BlockType Scope Name "FCS Calc" SID "3042" Ports [8] Position [1325, 913, 1360, 1122] ZOrder -3 Floating off Location [167, 49, 1573, 1207] Open off NumInputPorts "8" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" } List { ListType ScopeGraphics FigureColor "[0.5 0.5 0.5]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "10000" YMin "0~0~10~-1~-1~-1~-1~-1" YMax "1~1~120~1~1~1~1~1" SaveName "ScopeData15" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType Reference Name "Gateway Out1" SID "3043" Ports [1, 1] Position [1175, 949, 1210, 961] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Reset" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out10" SID "3044" Ports [1, 1] Position [1175, 924, 1210, 936] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Vin" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "3045" Ports [1, 1] Position [1175, 974, 1210, 986] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Byte" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "3046" Ports [1, 1] Position [1175, 999, 1210, 1011] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Good" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Logical3" SID "3047" Ports [2, 1] Position [380, 425, 425, 505] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "XOR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,80,2,1,white,blue,0,dc21e094,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 80 80 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 80 80 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[46.66 46.66 5" "2.66 46.66 52.66 52.66 52.66 46.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[40.66 40.66 46.66 46.66 40" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[34.66 34.66 40.66 40.66 34.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[28.66 28.66 34.66 28.66 34.66 34.66 28.66 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('" "xor');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical4" SID "3048" Ports [2, 1] Position [640, 427, 685, 478] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "XOR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,51,2,1,white,blue,0,dc21e094,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 51 51 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 51 51 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[31.66 31.66 3" "7.66 31.66 37.66 37.66 37.66 31.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[25.66 25.66 31.66 31.66 25" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[19.66 19.66 25.66 25.66 19.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[13.66 13.66 19.66 13.66 19.66 19.66 13.66 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('" "xor');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational1" SID "3049" Ports [2, 1] Position [1060, 462, 1115, 518] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "55,56,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 55 55 0 0 ],[0 0 56 56 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ],[35.77 35" ".77 42.77 35.77 42.77 42.77 42.77 35.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[28.77 28.77 35.77" " 35.77 28.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[21.77 21.77 28.77 28.77 21.77 ]," "[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[14.77 14.77 21.77 14.77 21.77 21.77 14.77 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1," "'\\bfa = b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "crc_accum" SID "3050" Ports [3, 1] Position [775, 448, 820, 502] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "hex2dec('FFFFFFFF')" rst on en on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,54,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 54 54 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 54 54 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[33.66 33.66 3" "9.66 33.66 39.66 39.66 39.66 33.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[27.66 27.66 33.66 33.66 27" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[21.66 21.66 27.66 27.66 21.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[15.66 15.66 21.66 15.66 21.66 21.66 15.66 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('" "input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'en');\ncolor('bl" "ack');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon te" "xt');" } Block { BlockType Outport Name "FCS Good" SID "3051" Position [1185, 483, 1215, 497] IconDisplay "Port number" } Line { SrcBlock "Endian Swap" SrcPort 1 DstBlock "Logical3" DstPort 2 } Line { SrcBlock "Logical3" SrcPort 1 DstBlock "CRC Remainders1" DstPort 1 } Line { SrcBlock "CRC Remainders1" SrcPort 1 DstBlock "Logical4" DstPort 2 } Line { SrcBlock "Concat1" SrcPort 1 Points [35, 0; 0, 90] DstBlock "Logical4" DstPort 1 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Concat1" DstPort 2 } Line { SrcBlock "Logical4" SrcPort 1 DstBlock "crc_accum" DstPort 1 } Line { SrcBlock "crc_accum" SrcPort 1 DstBlock "Assert1" DstPort 1 } Line { SrcBlock "Assert1" SrcPort 1 Points [25, 0] Branch { Points [0, -185; -330, 0] Branch { DstBlock "24LSB" DstPort 1 } Branch { Points [0, -55] DstBlock "8MSB" DstPort 1 } } Branch { DstBlock "Relational1" DstPort 1 } } Line { SrcBlock "byte_valid" SrcPort 1 Points [95, 0] Branch { Points [0, -105] DstBlock "crc_accum" DstPort 3 } Branch { Points [0, 330] DstBlock "Gateway Out10" DstPort 1 } } Line { SrcBlock "rst" SrcPort 1 Points [200, 0] Branch { Points [0, -110] DstBlock "crc_accum" DstPort 2 } Branch { Points [0, 370] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "24LSB" SrcPort 1 Points [-45, 0; 0, 45] DstBlock "Concat1" DstPort 1 } Line { SrcBlock "8MSB" SrcPort 1 Points [-260, 0; 0, 210] DstBlock "Logical3" DstPort 1 } Line { SrcBlock "byte" SrcPort 1 Points [20, 0] Branch { DstBlock "Endian Swap" DstPort 1 } Branch { Points [0, 495] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "Constant3" SrcPort 1 DstBlock "Relational1" DstPort 2 } Line { SrcBlock "Relational1" SrcPort 1 Points [10, 0] Branch { DstBlock "FCS Good" DstPort 1 } Branch { Points [0, 515] DstBlock "Gateway Out3" DstPort 1 } } Line { Name "Vin" Labels [0, 0] SrcBlock "Gateway Out10" SrcPort 1 DstBlock "FCS Calc" DstPort 1 } Line { Name "Reset" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 DstBlock "FCS Calc" DstPort 2 } Line { Name "Byte" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 DstBlock "FCS Calc" DstPort 3 } Line { Name "Good" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 DstBlock "FCS Calc" DstPort 4 } } } Block { BlockType Reference Name "Constant" SID "3052" Ports [0, 1] Position [205, 685, 235, 705] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "4" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,20,0,1,white,blue,0,85f36853,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 20 20 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 20 20 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[1" "2.22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[10.22 10.2" "2 12.22 12.22 10.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[8.22 8.22 10.22 10.22 8.2" "2 ],[1 1 1 ]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931" " 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('output',1,'4');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant1" SID "3053" Ports [0, 1] Position [500, 765, 530, 785] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "5" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,20,0,1,white,blue,0,98872051,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 20 20 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 20 20 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[1" "2.22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[10.22 10.2" "2 12.22 12.22 10.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[8.22 8.22 10.22 10.22 8.2" "2 ],[1 1 1 ]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931" " 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('output',1,'5');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant4" SID "3054" Ports [0, 1] Position [205, 725, 235, 745] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "10" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "4" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,20,0,1,white,blue,0,46ffeebb,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 20 20 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 20 20 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[1" "2.22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[10.22 10.2" "2 12.22 12.22 10.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[8.22 8.22 10.22 10.22 8.2" "2 ],[1 1 1 ]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931" " 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('output',1,'10');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay1" SID "3055" Ports [1, 1] Position [965, 810, 995, 840] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "30,30,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 30 30 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 30 30 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 " "19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 1" "9.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');di" "sp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay2" SID "3056" Ports [1, 1] Position [965, 875, 995, 905] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "30,30,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 30 30 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 30 30 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 " "19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 1" "9.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');di" "sp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay3" SID "3057" Ports [1, 1] Position [1185, 810, 1215, 840] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "30,30,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 30 30 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 30 30 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 " "19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 1" "9.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');di" "sp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay4" SID "3058" Ports [1, 1] Position [1185, 875, 1215, 905] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "30,30,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 30 30 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 30 30 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 " "19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 1" "9.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');di" "sp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Scope Name "FCS Calc" SID "3059" Ports [8] Position [1745, 413, 1780, 622] ZOrder -3 Floating off Location [1921, 45, 3841, 1199] Open off NumInputPorts "8" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" } List { ListType ScopeGraphics FigureColor "[0.5 0.5 0.5]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "16000" YMin "-1~-1~-1~1~-1~-1~-1~1" YMax "1~1~1~1~1~1~1~1" SaveName "ScopeData22" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType From Name "From" SID "3060" Position [220, 337, 335, 353] ZOrder -9 ShowName off GotoTag "DSSS_Byte_Valid" } Block { BlockType From Name "From1" SID "3061" Position [80, 643, 245, 667] ZOrder -9 ShowName off GotoTag "RX_PHY_MODE_11N_AC" TagVisibility "global" } Block { BlockType From Name "From10" SID "3062" Position [695, 548, 840, 562] ZOrder -9 ShowName off GotoTag "CUR_RX_BYTE" } Block { BlockType From Name "From11" SID "3063" Position [465, 612, 580, 628] ZOrder -9 ShowName off GotoTag "DSSS_Byte_Valid" } Block { BlockType From Name "From12" SID "3064" Position [370, 647, 485, 663] ZOrder -9 ShowName off GotoTag "OFDM_Byte_Valid" } Block { BlockType From Name "From13" SID "3065" Position [370, 752, 485, 768] ZOrder -9 ShowName off GotoTag "DSSS_Byte_Index" } Block { BlockType From Name "From14" SID "3066" Position [370, 727, 485, 743] ZOrder -9 ShowName off GotoTag "DSSS_Byte_Valid" } Block { BlockType From Name "From15" SID "3067" Position [695, 523, 840, 537] ZOrder -9 ShowName off GotoTag "CUR_RX_BYTE_VALID" } Block { BlockType From Name "From17" SID "3068" Position [705, 872, 820, 888] ZOrder -9 ShowName off GotoTag "DSSS_Last_Byte" } Block { BlockType From Name "From19" SID "3069" Position [705, 827, 820, 843] ZOrder -9 ShowName off GotoTag "OFDM_Byte_Valid" } Block { BlockType From Name "From20" SID "3070" Position [220, 457, 335, 473] ZOrder -9 ShowName off GotoTag "OFDM_Byte_Valid" } Block { BlockType From Name "From3" SID "3071" Position [220, 442, 335, 458] ZOrder -9 ShowName off GotoTag "DSSS_Byte_Valid" } Block { BlockType From Name "From4" SID "3072" Position [220, 387, 335, 403] ZOrder -9 ShowName off GotoTag "DSSS_Byte" } Block { BlockType From Name "From5" SID "3073" Position [220, 362, 335, 378] ZOrder -9 ShowName off GotoTag "OFDM_Byte" } Block { BlockType From Name "From6" SID "3074" Position [705, 807, 820, 823] ZOrder -9 ShowName off GotoTag "OFDM_Last_Byte" } Block { BlockType From Name "From7" SID "3075" Position [370, 672, 485, 688] ZOrder -9 ShowName off GotoTag "OFDM_Byte_Index" } Block { BlockType From Name "From8" SID "3076" Position [705, 892, 820, 908] ZOrder -9 ShowName off GotoTag "DSSS_Byte_Valid" } Block { BlockType Reference Name "Gateway Out1" SID "3077" Ports [1, 1] Position [1595, 449, 1630, 461] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Reset" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out10" SID "3078" Ports [1, 1] Position [1595, 424, 1630, 436] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Vin" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "3079" Ports [1, 1] Position [1595, 474, 1630, 486] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Byte" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "3080" Ports [1, 1] Position [1595, 499, 1630, 511] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Good" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "3081" Ports [1, 1] Position [1595, 524, 1630, 536] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "OFDM Last" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "3082" Ports [1, 1] Position [1595, 549, 1630, 561] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "DSSS Last" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "3083" Ports [1, 1] Position [1595, 574, 1630, 586] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "OFDM Good" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "3084" Ports [1, 1] Position [1595, 599, 1630, 611] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "DSSS Good" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Goto Name "Goto" SID "3085" Position [615, 103, 760, 117] ZOrder -10 ShowName off GotoTag "DSSS_Byte_Valid" TagVisibility "local" } Block { BlockType Goto Name "Goto1" SID "3086" Position [615, 123, 760, 137] ZOrder -10 ShowName off GotoTag "DSSS_Byte_Index" TagVisibility "local" } Block { BlockType Goto Name "Goto10" SID "3087" Position [1295, 745, 1495, 765] ShowName off GotoTag "DSSS_FCS_GOOD" TagVisibility "global" } Block { BlockType Goto Name "Goto12" SID "3088" Position [530, 361, 685, 379] ShowName off GotoTag "CUR_RX_BYTE" TagVisibility "local" } Block { BlockType Goto Name "Goto13" SID "3089" Position [1295, 815, 1495, 835] ShowName off GotoTag "OFDM_RX_DATA_DONE" TagVisibility "global" } Block { BlockType Goto Name "Goto14" SID "3090" Position [1295, 880, 1495, 900] ShowName off GotoTag "DSSS_RX_DATA_DONE" TagVisibility "global" } Block { BlockType Goto Name "Goto15" SID "3091" Position [530, 451, 685, 469] ShowName off GotoTag "CUR_RX_BYTE_VALID" TagVisibility "local" } Block { BlockType Goto Name "Goto2" SID "3092" Position [615, 143, 760, 157] ZOrder -10 ShowName off GotoTag "DSSS_Byte" TagVisibility "local" } Block { BlockType Goto Name "Goto3" SID "3093" Position [615, 163, 760, 177] ZOrder -10 ShowName off GotoTag "DSSS_Last_Byte" TagVisibility "local" } Block { BlockType Goto Name "Goto4" SID "3094" Position [450, 193, 595, 207] ZOrder -10 ShowName off GotoTag "OFDM_Byte_Valid" TagVisibility "local" } Block { BlockType Goto Name "Goto5" SID "3095" Position [450, 213, 595, 227] ZOrder -10 ShowName off GotoTag "OFDM_Byte_Index" TagVisibility "local" } Block { BlockType Goto Name "Goto6" SID "3096" Position [450, 233, 595, 247] ZOrder -10 ShowName off GotoTag "OFDM_Byte" TagVisibility "local" } Block { BlockType Goto Name "Goto7" SID "3097" Position [450, 253, 595, 267] ZOrder -10 ShowName off GotoTag "OFDM_Last_Byte" TagVisibility "local" } Block { BlockType Goto Name "Goto9" SID "3098" Position [1290, 690, 1490, 710] ShowName off GotoTag "OFDM_FCS_GOOD" TagVisibility "global" } Block { BlockType Reference Name "Logical1" SID "3099" Ports [2, 1] Position [655, 639, 690, 706] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,67,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 67 67 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 67 67 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[38.55" " 38.55 43.55 38.55 43.55 43.55 43.55 38.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[33.55 33.55 38" ".55 38.55 33.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[28.55 28.55 33.55 33.55 28.55 " "],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[23.55 23.55 28.55 23.55 28.55 28.55 23.55 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n" "color('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "3100" Ports [2, 1] Position [655, 719, 690, 786] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,67,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 67 67 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 67 67 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[38.55" " 38.55 43.55 38.55 43.55 43.55 43.55 38.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[33.55 33.55 38" ".55 38.55 33.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[28.55 28.55 33.55 33.55 28.55 " "],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[23.55 23.55 28.55 23.55 28.55 28.55 23.55 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n" "color('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical5" SID "3101" Ports [2, 1] Position [875, 806, 910, 844] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,38,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 38 38 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 38 38 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[24.55" " 24.55 29.55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[19.55 19.55 24" ".55 24.55 19.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[14.55 14.55 19.55 19.55 14.55 " "],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolo" "r('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical6" SID "3102" Ports [2, 1] Position [875, 871, 910, 909] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,38,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 38 38 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 38 38 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[24.55" " 24.55 29.55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[19.55 19.55 24" ".55 24.55 19.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[14.55 14.55 19.55 19.55 14.55 " "],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolo" "r('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical7" SID "3103" Ports [2, 1] Position [410, 444, 445, 471] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,27,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 27 27 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 27 27 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ]" ",[16.33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[13.3" "3 13.33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[10.33 10.33 13.3" "3 13.33 10.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[7.33 7.33 10.33 7.33 10.33 1" "0.33 7.33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon " "text');\n\n\n\ncolor('black');disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux" SID "3104" Ports [3, 1] Position [290, 637, 325, 753] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "35,116,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 16.5714 99.4286 116" " 0 ],[0.77 0.82 0.91 ]);\nplot([0 35 35 0 0 ],[0 16.5714 99.4286 116 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18" ".1 10.875 5.875 ],[63.55 63.55 68.55 63.55 68.55 68.55 68.55 63.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 " "10.875 ],[58.55 58.55 63.55 63.55 58.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[53.55 " "53.55 58.55 58.55 53.55 ],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[48.55 48.55 53.55 48.55" " 53.55 53.55 48.55 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: be" "gin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolo" "r('black');port_label('input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: e" "nd icon text');" } Block { BlockType Reference Name "Mux2" SID "3105" Ports [3, 1] Position [415, 329, 440, 411] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "25,82,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 11.7143 70.2857 82 " "0 ],[0.77 0.82 0.91 ]);\nplot([0 25 25 0 0 ],[0 11.7143 70.2857 82 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 1" "2.66 8.325 5.325 ],[44.33 44.33 47.33 44.33 47.33 47.33 47.33 44.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325" " 8.325 ],[41.33 41.33 44.33 44.33 41.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[38.33 " "38.33 41.33 41.33 38.33 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[35.33 35.33 38.33 35.3" "3 38.33 38.33 35.33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: b" "egin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncol" "or('black');port_label('input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: " "end icon text');" } Block { BlockType Reference Name "Mux4" SID "3106" Ports [3, 1] Position [795, 604, 820, 686] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "25,82,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 11.7143 70.2857 82 " "0 ],[0.77 0.82 0.91 ]);\nplot([0 25 25 0 0 ],[0 11.7143 70.2857 82 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 1" "2.66 8.325 5.325 ],[44.33 44.33 47.33 44.33 47.33 47.33 47.33 44.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325" " 8.325 ],[41.33 41.33 44.33 44.33 41.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[38.33 " "38.33 41.33 41.33 38.33 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[35.33 35.33 38.33 35.3" "3 38.33 38.33 35.33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: b" "egin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncol" "or('black');port_label('input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: " "end icon text');" } Block { BlockType Reference Name "Register" SID "3113" Ports [3, 1] Position [1180, 683, 1220, 717] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "40,34,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 34 34 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 34 34 0 ]);\npatch([11.1 16.88 20.88 24.88 28.88 20.88 15.1 11.1 ],[21.4" "4 21.44 25.44 21.44 25.44 25.44 25.44 21.44 ],[1 1 1 ]);\npatch([15.1 20.88 16.88 11.1 15.1 ],[17.44 17.44 21.4" "4 21.44 17.44 ],[0.931 0.946 0.973 ]);\npatch([11.1 16.88 20.88 15.1 11.1 ],[13.44 13.44 17.44 17.44 13.44 ],[1" " 1 1 ]);\npatch([15.1 28.88 24.88 20.88 16.88 11.1 15.1 ],[9.44 9.44 13.44 9.44 13.44 13.44 9.44 ],[0.931 0.946" " 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'e" "n');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "3114" Ports [3, 1] Position [1180, 738, 1220, 772] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "40,34,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 34 34 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 34 34 0 ]);\npatch([11.1 16.88 20.88 24.88 28.88 20.88 15.1 11.1 ],[21.4" "4 21.44 25.44 21.44 25.44 25.44 25.44 21.44 ],[1 1 1 ]);\npatch([15.1 20.88 16.88 11.1 15.1 ],[17.44 17.44 21.4" "4 21.44 17.44 ],[0.931 0.946 0.973 ]);\npatch([11.1 16.88 20.88 15.1 11.1 ],[13.44 13.44 17.44 17.44 13.44 ],[1" " 1 1 ]);\npatch([15.1 28.88 24.88 20.88 16.88 11.1 15.1 ],[9.44 9.44 13.44 9.44 13.44 13.44 9.44 ],[0.931 0.946" " 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'e" "n');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Reference Name "Relational" SID "3115" Ports [2, 1] Position [585, 672, 620, 703] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a<=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,31,2,1,white,blue,0,52e4b236,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 31 31 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 31 31 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[19.44 " "19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[15.44 15.44 19.44 1" "9.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 " "]);\npatch([12.1 25.88 21.88 17.88 13.88 8.1 12.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa \\" "leq b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational1" SID "3116" Ports [2, 1] Position [585, 752, 620, 783] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a<=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,31,2,1,white,blue,0,52e4b236,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 31 31 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 31 31 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[19.44 " "19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[15.44 15.44 19.44 1" "9.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 " "]);\npatch([12.1 25.88 21.88 17.88 13.88 8.1 12.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa \\" "leq b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Line { SrcBlock "From" SrcPort 1 DstBlock "Mux2" DstPort 1 } Line { SrcBlock "From5" SrcPort 1 DstBlock "Mux2" DstPort 2 } Line { SrcBlock "From4" SrcPort 1 DstBlock "Mux2" DstPort 3 } Line { SrcBlock "Mux2" SrcPort 1 DstBlock "Goto12" DstPort 1 } Line { SrcBlock "From3" SrcPort 1 DstBlock "Logical7" DstPort 1 } Line { SrcBlock "From20" SrcPort 1 DstBlock "Logical7" DstPort 2 } Line { SrcBlock "Logical7" SrcPort 1 DstBlock "Goto15" DstPort 1 } Line { SrcBlock "Mux4" SrcPort 1 Points [25, 0; 0, -65; 15, 0] Branch { DstBlock "CRC32 Calc" DstPort 3 } Branch { Points [0, -125] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "From11" SrcPort 1 DstBlock "Mux4" DstPort 1 } Line { SrcBlock "Register1" SrcPort 1 Points [40, 0] Branch { DstBlock "Goto10" DstPort 1 } Branch { Points [0, -150] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "Register" SrcPort 1 Points [35, 0] Branch { DstBlock "Goto9" DstPort 1 } Branch { Points [0, -120] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "CRC32 Calc" SrcPort 1 Points [45, 0] Branch { Points [0, 135] Branch { DstBlock "Register" DstPort 1 } Branch { Points [0, 55] DstBlock "Register1" DstPort 1 } } Branch { Points [0, -50] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "Delay2" SrcPort 1 Points [130, 0] Branch { DstBlock "Delay4" DstPort 1 } Branch { Points [0, -125] Branch { DstBlock "Register1" DstPort 3 } Branch { Points [0, -210] DstBlock "Gateway Out5" DstPort 1 } } } Line { SrcBlock "Delay1" SrcPort 1 Points [120, 0] Branch { DstBlock "Delay3" DstPort 1 } Branch { Points [0, -115] Branch { DstBlock "Register" DstPort 3 } Branch { Points [0, -180] DstBlock "Gateway Out4" DstPort 1 } } } Line { SrcBlock "Logical6" SrcPort 1 DstBlock "Delay2" DstPort 1 } Line { SrcBlock "Logical5" SrcPort 1 DstBlock "Delay1" DstPort 1 } Line { SrcBlock "From8" SrcPort 1 DstBlock "Logical6" DstPort 2 } Line { SrcBlock "From17" SrcPort 1 DstBlock "Logical6" DstPort 1 } Line { SrcBlock "From19" SrcPort 1 DstBlock "Logical5" DstPort 2 } Line { SrcBlock "From6" SrcPort 1 DstBlock "Logical5" DstPort 1 } Line { SrcBlock "From15" SrcPort 1 Points [10, 0] Branch { DstBlock "CRC32 Calc" DstPort 1 } Branch { Points [0, -100] DstBlock "Gateway Out10" DstPort 1 } } Line { SrcBlock "Logical2" SrcPort 1 Points [75, 0] Branch { Points [0, -85] DstBlock "Mux4" DstPort 3 } Branch { DstBlock "Register1" DstPort 2 } } Line { SrcBlock "From14" SrcPort 1 DstBlock "Logical2" DstPort 1 } Line { SrcBlock "Relational1" SrcPort 1 DstBlock "Logical2" DstPort 2 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Relational1" DstPort 2 } Line { SrcBlock "From13" SrcPort 1 DstBlock "Relational1" DstPort 1 } Line { SrcBlock "Logical1" SrcPort 1 Points [50, 0] Branch { Points [0, -30] DstBlock "Mux4" DstPort 2 } Branch { Points [0, 25] DstBlock "Register" DstPort 2 } } Line { SrcBlock "From12" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Relational" SrcPort 1 DstBlock "Logical1" DstPort 2 } Line { SrcBlock "Mux" SrcPort 1 DstBlock "Relational" DstPort 2 } Line { SrcBlock "From7" SrcPort 1 DstBlock "Relational" DstPort 1 } Line { SrcBlock "From10" SrcPort 1 Points [35, 0] Branch { DstBlock "CRC32 Calc" DstPort 2 } Branch { Points [0, -75] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "Delay3" SrcPort 1 DstBlock "Goto13" DstPort 1 } Line { SrcBlock "Delay4" SrcPort 1 DstBlock "Goto14" DstPort 1 } Line { Name "Vin" Labels [0, 0] SrcBlock "Gateway Out10" SrcPort 1 DstBlock "FCS Calc" DstPort 1 } Line { Name "Reset" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 DstBlock "FCS Calc" DstPort 2 } Line { Name "Byte" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 DstBlock "FCS Calc" DstPort 3 } Line { Name "Good" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 DstBlock "FCS Calc" DstPort 4 } Line { Name "OFDM Last" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 DstBlock "FCS Calc" DstPort 5 } Line { Name "DSSS Last" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 DstBlock "FCS Calc" DstPort 6 } Line { Name "OFDM Good" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 DstBlock "FCS Calc" DstPort 7 } Line { Name "DSSS Good" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 DstBlock "FCS Calc" DstPort 8 } Line { Name "" Labels [0, 0] SrcBlock "Bus\nSelector1" SrcPort 1 DstBlock "Goto" DstPort 1 } Line { Name "" Labels [0, 0] SrcBlock "Bus\nSelector1" SrcPort 2 DstBlock "Goto1" DstPort 1 } Line { Name "" Labels [0, 0] SrcBlock "Bus\nSelector1" SrcPort 3 DstBlock "Goto2" DstPort 1 } Line { Name "" Labels [0, 0] SrcBlock "Bus\nSelector1" SrcPort 4 DstBlock "Goto3" DstPort 1 } Line { Name "" Labels [0, 0] SrcBlock "Bus\nSelector" SrcPort 1 DstBlock "Goto4" DstPort 1 } Line { Name "" Labels [0, 0] SrcBlock "Bus\nSelector" SrcPort 2 DstBlock "Goto5" DstPort 1 } Line { Name "" Labels [0, 0] SrcBlock "Bus\nSelector" SrcPort 3 DstBlock "Goto6" DstPort 1 } Line { Name "" Labels [0, 0] SrcBlock "Bus\nSelector" SrcPort 4 DstBlock "Goto7" DstPort 1 } Line { SrcBlock "DSSS data" SrcPort 1 DstBlock "Bus\nSelector1" DstPort 1 } Line { SrcBlock "OFDM data" SrcPort 1 DstBlock "Bus\nSelector" DstPort 1 } Line { SrcBlock "From1" SrcPort 1 DstBlock "Mux" DstPort 1 } Line { SrcBlock "Constant" SrcPort 1 DstBlock "Mux" DstPort 2 } Line { SrcBlock "Constant4" SrcPort 1 DstBlock "Mux" DstPort 3 } Annotation { Name "These signals are routed to the MAC Outputs\nblock for use by the MAC core. The PHY doesn't\nreall" "y care if FCS was good or bad; once the\nlast byte is written to the pkt buffer, the PHY is done.\nFCS calculat" "ion is in the PHY to support MAC-free\nusage of the design." Position [1288, 947] HorizontalAlignment "left" } Annotation { Name "Checksum starts at MAC payload\nSIGNAL, HT-SIG and SERVICE\nbytes not covered by FCS\n\n11ac actua" "lly has more non-CRC bytes\nin the VHTSIGB field. This is safe to \nignore here, at least until we add 11ac\nsu" "pport in the SIG decoder blocks." Position [35, 802] HorizontalAlignment "left" } } } Block { BlockType Reference Name "Gateway Out1" SID "3117" Ports [1, 1] Position [705, 304, 740, 316] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.88" " ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.11 " "8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 ],[" "0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([15." "775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" Port { PortNumber 1 Name "OFDM Valid" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out11" SID "3118" Ports [1, 1] Position [705, 264, 740, 276] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.88" " ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.11 " "8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 ],[" "0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([15." "775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" Port { PortNumber 1 Name "DSSS Byte" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out12" SID "3119" Ports [1, 1] Position [705, 284, 740, 296] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.88" " ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.11 " "8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 ],[" "0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([15." "775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" Port { PortNumber 1 Name "DSSS Last Byte" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "3120" Ports [1, 1] Position [705, 324, 740, 336] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.88" " ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.11 " "8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 ],[" "0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([15." "775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" Port { PortNumber 1 Name "OFDM Byte Index" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "3121" Ports [1, 1] Position [705, 344, 740, 356] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.88" " ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.11 " "8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 ],[" "0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([15." "775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" Port { PortNumber 1 Name "OFDM Byte" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "3122" Ports [1, 1] Position [705, 364, 740, 376] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.88" " ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.11 " "8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 ],[" "0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([15." "775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" Port { PortNumber 1 Name "OFDM Last Byte" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "3123" Ports [1, 1] Position [705, 244, 740, 256] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.88" " ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.11 " "8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 ],[" "0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([15." "775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" Port { PortNumber 1 Name "DSSS Byte Index" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out9" SID "3124" Ports [1, 1] Position [705, 224, 740, 236] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.88" " ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.11 " "8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 ],[" "0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([15." "775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" Port { PortNumber 1 Name "DSSS Valid" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType SubSystem Name "Pkt Buf Interface" SID "3125" Ports [2] Position [605, 443, 680, 487] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Pkt Buf Interface" Location [613, 132, 1889, 619] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "DSSS data" SID "3126" Position [130, 78, 160, 92] IconDisplay "Port number" } Block { BlockType Inport Name "OFDM data" SID "3127" Position [130, 168, 160, 182] Port "2" IconDisplay "Port number" } Block { BlockType SubSystem Name "Addr Check" SID "3128" Ports [2, 2] Position [755, 363, 825, 427] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Addr Check" Location [381, 439, 1016, 736] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "WrEn" SID "3129" Position [200, 188, 230, 202] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "Addr" SID "3130" Position [200, 223, 230, 237] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType From Name "From1" SID "3131" Position [25, 253, 260, 267] ZOrder -9 ShowName off GotoTag "regRx_PktBuf_Max_WriteAddr" TagVisibility "global" } Block { BlockType Reference Name "Logical1" SID "3132" Ports [2, 1] Position [505, 215, 540, 255] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,40,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 40 40 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 40 40 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[25.55 25.55 30." "55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[20.55 20.55 25.55 25.55 20." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('a" "nd');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational" SID "3133" Ports [2, 1] Position [320, 217, 375, 273] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a
Hardw" "are notes: In hardware this block costs nothing." nbits "9" boolean_output off mode "Lower Bit Location + Width" bit1 "2" base1 "MSB of Input" bit0 "3" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,442,407" block_type "slice" block_version "8.2.02" sg_icon_stat "45,20,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 20 20 0 ]);\npatch([17.55 20.44 22.44 24.44 26.44 22.44 19.55 17.55 ],[12.22 12.22" " 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([19.55 22.44 20.44 17.55 19.55 ],[10.22 10.22 12.22 12.22" " 10.22 ],[0.931 0.946 0.973 ]);\npatch([17.55 20.44 22.44 19.55 17.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\n" "patch([19.55 26.44 24.44 22.44 20.44 17.55 19.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('ou" "tput',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub1" SID "3142" Ports [2, 1] Position [475, 685, 520, 725] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "0" precision "Full" arith_type "Unsigned" n_bits "15" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL off hw_selection "Fabric" pipelined off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" sg_icon_stat "45,40,2,1,white,blue,0,e139daf6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 40 40 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 40 40 0 ]);\npatch([10.875 18.1 23.1 28.1 33.1 23.1 15.875 10.875 ],[25.55 25.55 3" "0.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([15.875 23.1 18.1 10.875 15.875 ],[20.55 20.55 25.55 25.55 " "20.55 ],[0.931 0.946 0.973 ]);\npatch([10.875 18.1 23.1 15.875 10.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1 1 ])" ";\npatch([15.875 33.1 28.1 23.1 18.1 10.875 15.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.946 0.9" "73 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_la" "bel('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bf{a + b}'" ",'texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub2" SID "3143" Ports [2, 1] Position [460, 555, 505, 595] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "0" precision "Full" arith_type "Unsigned" n_bits "15" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL off hw_selection "Fabric" pipelined off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" sg_icon_stat "45,40,2,1,white,blue,0,e139daf6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 40 40 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 40 40 0 ]);\npatch([10.875 18.1 23.1 28.1 33.1 23.1 15.875 10.875 ],[25.55 25.55 3" "0.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([15.875 23.1 18.1 10.875 15.875 ],[20.55 20.55 25.55 25.55 " "20.55 ],[0.931 0.946 0.973 ]);\npatch([10.875 18.1 23.1 15.875 10.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1 1 ])" ";\npatch([15.875 33.1 28.1 23.1 18.1 10.875 15.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.946 0.9" "73 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_la" "bel('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bf{a + b}'" ",'texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "BRAM I/O" SID "3144" Ports [3] Position [1450, 282, 1540, 338] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "BRAM I/O" Location [1504, 362, 1782, 821] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Dout[63:0]" SID "3145" Position [255, 308, 285, 322] IconDisplay "Port number" } Block { BlockType Inport Name "Addr[31:0]" SID "3146" Position [255, 378, 285, 392] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "WEn[7:0]" SID "3147" Position [255, 458, 285, 472] Port "3" IconDisplay "Port number" } Block { BlockType Reference Name "BRAM_Addr" SID "3148" Ports [1, 1] Position [465, 375, 520, 395] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "20,20,356,332" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "55,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 20 20 0 ],[0.95 0.93" " 0.65 ]);\nplot([0 55 55 0 0 ],[0 0 20 20 0 ]);\npatch([22.55 25.44 27.44 29.44 31.44 27.44 24.55 22.55 ],[12.22" " 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([24.55 27.44 25.44 22.55 24.55 ],[10.22 10.22 12." "22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([22.55 25.44 27.44 24.55 22.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1" " 1 1 ]);\npatch([24.55 31.44 29.44 27.44 25.44 22.55 24.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 " "0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');po" "rt_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfpr" "intf('','COMMENT: end icon text');" } Block { BlockType Reference Name "BRAM_Din" SID "3149" Ports [1, 1] Position [470, 539, 525, 561] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to X" "ilinx fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top level" " input ports." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "64" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "20,20,356,432" block_type "gatewayin" block_version "VER_STRING_GOES_HERE" sg_icon_stat "55,22,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 22 22 0 ],[0.95 0.93" " 0.65 ]);\nplot([0 55 55 0 0 ],[0 0 22 22 0 ]);\npatch([20.325 24.66 27.66 30.66 33.66 27.66 23.325 20.325 ],[14" ".33 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([23.325 27.66 24.66 20.325 23.325 ],[11.33 11." "33 14.33 14.33 11.33 ],[0.985 0.979 0.895 ]);\npatch([20.325 24.66 27.66 23.325 20.325 ],[8.33 8.33 11.33 11.33 " "8.33 ],[1 1 1 ]);\npatch([23.325 33.66 30.66 27.66 24.66 20.325 23.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[" "0.985 0.979 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor" "('black');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1" ",' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "BRAM_Dout" SID "3150" Ports [1, 1] Position [465, 305, 520, 325] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "20,20,356,332" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "55,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 20 20 0 ],[0.95 0.93" " 0.65 ]);\nplot([0 55 55 0 0 ],[0 0 20 20 0 ]);\npatch([22.55 25.44 27.44 29.44 31.44 27.44 24.55 22.55 ],[12.22" " 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([24.55 27.44 25.44 22.55 24.55 ],[10.22 10.22 12." "22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([22.55 25.44 27.44 24.55 22.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1" " 1 1 ]);\npatch([24.55 31.44 29.44 27.44 25.44 22.55 24.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 " "0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');po" "rt_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfpr" "intf('','COMMENT: end icon text');" } Block { BlockType Reference Name "BRAM_En" SID "3151" Ports [1, 1] Position [465, 610, 525, 630] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "8.2.02" sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0.93" " 0.65 ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12.22" " 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 12." "22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1" " 1 1 ]);\npatch([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 " "0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');po" "rt_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfpr" "intf('','COMMENT: end icon text');" } Block { BlockType Reference Name "BRAM_Reset" SID "3152" Ports [1, 1] Position [465, 665, 525, 685] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "8.2.02" sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0.93" " 0.65 ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12.22" " 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 12." "22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1" " 1 1 ]);\npatch([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 " "0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');po" "rt_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfpr" "intf('','COMMENT: end icon text');" } Block { BlockType Reference Name "BRAM_WEn" SID "3153" Ports [1, 1] Position [465, 455, 520, 475] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "20,20,356,332" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "55,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 20 20 0 ],[0.95 0.93" " 0.65 ]);\nplot([0 55 55 0 0 ],[0 0 20 20 0 ]);\npatch([22.55 25.44 27.44 29.44 31.44 27.44 24.55 22.55 ],[12.22" " 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([24.55 27.44 25.44 22.55 24.55 ],[10.22 10.22 12." "22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([22.55 25.44 27.44 24.55 22.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1" " 1 1 ]);\npatch([24.55 31.44 29.44 27.44 25.44 22.55 24.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 " "0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');po" "rt_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfpr" "intf('','COMMENT: end icon text');" } Block { BlockType Constant Name "Constant" SID "3154" Position [335, 537, 360, 563] ZOrder -5 ShowName off Value "0" } Block { BlockType Reference Name "Constant1" SID "3155" Ports [0, 1] Position [340, 609, 360, 631] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period on period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "8.2.02" sg_icon_stat "20,22,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 20 20 0 0 ],[0 0 22 22 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[13.22 13." "22 15.22 13.22 15.22 15.22 15.22 13.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[11.22 11.22 13.22 13.22" " 11.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[9.22 9.22 11.22 11.22 9.22 ],[1 1 1 ]);\npa" "tch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[7.22 7.22 9.22 7.22 9.22 9.22 7.22 ],[0.931 0.946 0.973 ]);\nfprin" "tf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output" "',1,'1');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant2" SID "3156" Ports [0, 1] Position [340, 664, 360, 686] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period on period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "8.2.02" sg_icon_stat "20,22,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 20 20 0 0 ],[0 0 22 22 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[13.22 13." "22 15.22 13.22 15.22 15.22 15.22 13.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[11.22 11.22 13.22 13.22" " 11.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[9.22 9.22 11.22 11.22 9.22 ],[1 1 1 ]);\npa" "tch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[7.22 7.22 9.22 7.22 9.22 9.22 7.22 ],[0.931 0.946 0.973 ]);\nfprin" "tf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output" "',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register" SID "3157" Ports [1, 1] Position [395, 301, 430, 329] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,28,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 28 28 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[18.44 18.4" "4 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[14.44 14.44 18.44 18.44 " "14.44 ],[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\np" "atch([12.1 25.88 21.88 17.88 13.88 8.1 12.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('in" "put',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf" "('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "3158" Ports [1, 1] Position [395, 371, 430, 399] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,28,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 28 28 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[18.44 18.4" "4 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[14.44 14.44 18.44 18.44 " "14.44 ],[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\np" "atch([12.1 25.88 21.88 17.88 13.88 8.1 12.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('in" "put',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf" "('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "3159" Ports [1, 1] Position [395, 451, 430, 479] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,28,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 28 28 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[18.44 18.4" "4 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[14.44 14.44 18.44 18.44 " "14.44 ],[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\np" "atch([12.1 25.88 21.88 17.88 13.88 8.1 12.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('in" "put',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf" "('','COMMENT: end icon text');" } Block { BlockType Terminator Name "Terminator" SID "3160" Position [540, 380, 550, 390] ShowName off } Block { BlockType Terminator Name "Terminator1" SID "3161" Position [540, 545, 550, 555] ShowName off } Block { BlockType Terminator Name "Terminator2" SID "3162" Position [540, 310, 550, 320] ShowName off } Block { BlockType Terminator Name "Terminator3" SID "3163" Position [540, 615, 550, 625] ShowName off } Block { BlockType Terminator Name "Terminator4" SID "3164" Position [540, 670, 550, 680] ShowName off } Block { BlockType Terminator Name "Terminator5" SID "3165" Position [540, 460, 550, 470] ShowName off } Line { SrcBlock "BRAM_Reset" SrcPort 1 DstBlock "Terminator4" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "BRAM_WEn" DstPort 1 } Line { SrcBlock "Register1" SrcPort 1 DstBlock "BRAM_Addr" DstPort 1 } Line { SrcBlock "Register" SrcPort 1 DstBlock "BRAM_Dout" DstPort 1 } Line { SrcBlock "BRAM_WEn" SrcPort 1 DstBlock "Terminator5" DstPort 1 } Line { SrcBlock "BRAM_En" SrcPort 1 DstBlock "Terminator3" DstPort 1 } Line { SrcBlock "BRAM_Dout" SrcPort 1 DstBlock "Terminator2" DstPort 1 } Line { SrcBlock "BRAM_Din" SrcPort 1 DstBlock "Terminator1" DstPort 1 } Line { SrcBlock "BRAM_Addr" SrcPort 1 DstBlock "Terminator" DstPort 1 } Line { SrcBlock "Constant" SrcPort 1 DstBlock "BRAM_Din" DstPort 1 } Line { SrcBlock "Constant2" SrcPort 1 DstBlock "BRAM_Reset" DstPort 1 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "BRAM_En" DstPort 1 } Line { SrcBlock "Dout[63:0]" SrcPort 1 DstBlock "Register" DstPort 1 } Line { SrcBlock "Addr[31:0]" SrcPort 1 DstBlock "Register1" DstPort 1 } Line { SrcBlock "WEn[7:0]" SrcPort 1 DstBlock "Register2" DstPort 1 } } } Block { BlockType SubSystem Name "BRAM WEn Decoding" SID "3166" Ports [2, 1] Position [760, 554, 875, 636] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "BRAM WEn Decoding" Location [232, 87, 1681, 1095] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "125" Block { BlockType Inport Name "byte_addr" SID "3167" Position [300, 333, 330, 347] IconDisplay "Port number" } Block { BlockType Inport Name "byte_valid" SID "3168" Position [705, 683, 735, 697] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "3LSB" SID "3169" Ports [1, 1] Position [400, 330, 445, 350] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "3" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,442,407" block_type "slice" block_version "8.2.02" sg_icon_stat "45,20,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 20 20 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 20 20 0 ]);\npatch([17.55 20.44 22.44 24.44 26.44 22.44 19.55 17.55 ],[12.22" " 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([19.55 22.44 20.44 17.55 19.55 ],[10.22 10.22 12." "22 12.22 10.22 ],[0.931 0.946 0.973 ]);\npatch([17.55 20.44 22.44 19.55 17.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1" " 1 1 ]);\npatch([19.55 26.44 24.44 22.44 20.44 17.55 19.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');" "port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Concat" SID "3170" Ports [8, 1] Position [1030, 369, 1070, 611] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point " "at zero." num_inputs "8" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" block_version "8.2.02" sg_icon_stat "40,242,8,1,white,blue,0,6fe74153,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 242 242 0 ],[0.77 0." "82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 242 242 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[126.5" "5 126.55 131.55 126.55 131.55 131.55 131.55 126.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[121.55 " "121.55 126.55 126.55 121.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[116.55 116.55 121.5" "5 121.55 116.55 ],[1 1 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[111.55 111.55 116.55 111.55 116." "55 116.55 111.55 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin" " icon text');\ncolor('black');port_label('input',1,'hi');\n\n\n\n\n\n\ncolor('black');port_label('input',8,'lo')" ";\n\ncolor('black');disp('\\fontsize{20}\\}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Concat1" SID "3171" Ports [3, 1] Position [365, 261, 400, 299] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point " "at zero." num_inputs "3" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" block_version "8.2.02" sg_icon_stat "35,38,3,1,white,blue,0,61ef8218,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 38 38 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 38 38 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[24.55 24." "55 29.55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[19.55 19.55 24.55 2" "4.55 19.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');por" "t_label('input',1,'hi');\n\ncolor('black');port_label('input',3,'lo');\n\ncolor('black');disp('\\fontsize{20}\\}" "','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Constant1" SID "3172" Ports [0, 1] Position [710, 369, 730, 391] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "2" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "8.2.02" sg_icon_stat "20,22,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 20 20 0 0 ],[0 0 22 22 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[13.22 13." "22 15.22 13.22 15.22 15.22 15.22 13.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[11.22 11.22 13.22 13.22" " 11.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[9.22 9.22 11.22 11.22 9.22 ],[1 1 1 ]);\npa" "tch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[7.22 7.22 9.22 7.22 9.22 9.22 7.22 ],[0.931 0.946 0.973 ]);\nfprin" "tf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output" "',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant2" SID "3173" Ports [0, 1] Position [710, 399, 730, 421] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "2" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "8.2.02" sg_icon_stat "20,22,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 20 20 0 0 ],[0 0 22 22 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[13.22 13." "22 15.22 13.22 15.22 15.22 15.22 13.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[11.22 11.22 13.22 13.22" " 11.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[9.22 9.22 11.22 11.22 9.22 ],[1 1 1 ]);\npa" "tch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[7.22 7.22 9.22 7.22 9.22 9.22 7.22 ],[0.931 0.946 0.973 ]);\nfprin" "tf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output" "',1,'1');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant3" SID "3174" Ports [0, 1] Position [710, 429, 730, 451] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "2" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "2" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "8.2.02" sg_icon_stat "20,22,0,1,white,blue,0,fca86624,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 20 20 0 0 ],[0 0 22 22 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[13.22 13." "22 15.22 13.22 15.22 15.22 15.22 13.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[11.22 11.22 13.22 13.22" " 11.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[9.22 9.22 11.22 11.22 9.22 ],[1 1 1 ]);\npa" "tch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[7.22 7.22 9.22 7.22 9.22 9.22 7.22 ],[0.931 0.946 0.973 ]);\nfprin" "tf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output" "',1,'2');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant4" SID "3175" Ports [0, 1] Position [710, 459, 730, 481] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "3" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "2" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "8.2.02" sg_icon_stat "20,22,0,1,white,blue,0,279a71c8,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 20 20 0 0 ],[0 0 22 22 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[13.22 13." "22 15.22 13.22 15.22 15.22 15.22 13.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[11.22 11.22 13.22 13.22" " 11.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[9.22 9.22 11.22 11.22 9.22 ],[1 1 1 ]);\npa" "tch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[7.22 7.22 9.22 7.22 9.22 9.22 7.22 ],[0.931 0.946 0.973 ]);\nfprin" "tf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output" "',1,'3');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant5" SID "3176" Ports [0, 1] Position [710, 489, 730, 511] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "4" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "2" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "8.2.02" sg_icon_stat "20,22,0,1,white,blue,0,85f36853,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 20 20 0 0 ],[0 0 22 22 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[13.22 13." "22 15.22 13.22 15.22 15.22 15.22 13.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[11.22 11.22 13.22 13.22" " 11.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[9.22 9.22 11.22 11.22 9.22 ],[1 1 1 ]);\npa" "tch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[7.22 7.22 9.22 7.22 9.22 9.22 7.22 ],[0.931 0.946 0.973 ]);\nfprin" "tf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output" "',1,'4');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant6" SID "3177" Ports [0, 1] Position [710, 519, 730, 541] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "5" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "2" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "8.2.02" sg_icon_stat "20,22,0,1,white,blue,0,98872051,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 20 20 0 0 ],[0 0 22 22 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[13.22 13." "22 15.22 13.22 15.22 15.22 15.22 13.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[11.22 11.22 13.22 13.22" " 11.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[9.22 9.22 11.22 11.22 9.22 ],[1 1 1 ]);\npa" "tch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[7.22 7.22 9.22 7.22 9.22 9.22 7.22 ],[0.931 0.946 0.973 ]);\nfprin" "tf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output" "',1,'5');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant7" SID "3178" Ports [0, 1] Position [710, 549, 730, 571] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "6" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "2" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "8.2.02" sg_icon_stat "20,22,0,1,white,blue,0,f0403ad7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 20 20 0 0 ],[0 0 22 22 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[13.22 13." "22 15.22 13.22 15.22 15.22 15.22 13.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[11.22 11.22 13.22 13.22" " 11.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[9.22 9.22 11.22 11.22 9.22 ],[1 1 1 ]);\npa" "tch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[7.22 7.22 9.22 7.22 9.22 9.22 7.22 ],[0.931 0.946 0.973 ]);\nfprin" "tf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output" "',1,'6');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant8" SID "3179" Ports [0, 1] Position [710, 579, 730, 601] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "7" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "2" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "8.2.02" sg_icon_stat "20,22,0,1,white,blue,0,2a6960a5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 20 20 0 0 ],[0 0 22 22 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[13.22 13." "22 15.22 13.22 15.22 15.22 15.22 13.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[11.22 11.22 13.22 13.22" " 11.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[9.22 9.22 11.22 11.22 9.22 ],[1 1 1 ]);\npa" "tch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[7.22 7.22 9.22 7.22 9.22 9.22 7.22 ],[0.931 0.946 0.973 ]);\nfprin" "tf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output" "',1,'7');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From1" SID "3180" Position [75, 259, 300, 281] ZOrder -9 ShowName off GotoTag "regRx_PKT_BUF_BYTE_ORDER_SWAP" TagVisibility "global" } Block { BlockType Reference Name "Logical" SID "3181" Ports [2, 1] Position [935, 369, 965, 396] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "8.2.02" sg_icon_stat "30,27,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 27 27 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 27 27 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[16.3" "3 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 13.33 " "16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13.33 10." "33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n" "color('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "3182" Ports [2, 1] Position [935, 399, 965, 426] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "8.2.02" sg_icon_stat "30,27,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 27 27 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 27 27 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[16.3" "3 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 13.33 " "16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13.33 10." "33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n" "color('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "3183" Ports [2, 1] Position [935, 429, 965, 456] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "8.2.02" sg_icon_stat "30,27,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 27 27 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 27 27 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[16.3" "3 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 13.33 " "16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13.33 10." "33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n" "color('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical3" SID "3184" Ports [2, 1] Position [935, 459, 965, 486] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "8.2.02" sg_icon_stat "30,27,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 27 27 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 27 27 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[16.3" "3 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 13.33 " "16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13.33 10." "33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n" "color('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical4" SID "3185" Ports [2, 1] Position [585, 309, 625, 351] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "XOR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,42,2,1,white,blue,0,dc21e094,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 42 42 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 42 42 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[26.55 26." "55 31.55 26.55 31.55 31.55 31.55 26.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[21.55 21.55 26.55 2" "6.55 21.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[16.55 16.55 21.55 21.55 16.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[11.55 11.55 16.55 11.55 16.55 16.55 11.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('b" "lack');disp('xor');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical5" SID "3186" Ports [2, 1] Position [935, 489, 965, 516] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "8.2.02" sg_icon_stat "30,27,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 27 27 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 27 27 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[16.3" "3 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 13.33 " "16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13.33 10." "33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n" "color('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical6" SID "3187" Ports [2, 1] Position [935, 519, 965, 546] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "8.2.02" sg_icon_stat "30,27,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 27 27 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 27 27 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[16.3" "3 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 13.33 " "16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13.33 10." "33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n" "color('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical7" SID "3188" Ports [2, 1] Position [935, 549, 965, 576] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "8.2.02" sg_icon_stat "30,27,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 27 27 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 27 27 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[16.3" "3 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 13.33 " "16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13.33 10." "33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n" "color('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical8" SID "3189" Ports [2, 1] Position [935, 579, 965, 606] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "8.2.02" sg_icon_stat "30,27,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 27 27 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 27 27 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[16.3" "3 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 13.33 " "16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13.33 10." "33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n" "color('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational" SID "3190" Ports [2, 1] Position [820, 357, 850, 388] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" block_version "8.2.02" sg_icon_stat "30,31,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 31 31 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 31 31 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 19.4" "4 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 19.44 " "15.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\np" "atch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('in" "put',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa = b','texmo" "de','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational1" SID "3191" Ports [2, 1] Position [820, 387, 850, 418] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" block_version "8.2.02" sg_icon_stat "30,31,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 31 31 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 31 31 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 19.4" "4 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 19.44 " "15.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\np" "atch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('in" "put',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa = b','texmo" "de','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational2" SID "3192" Ports [2, 1] Position [820, 417, 850, 448] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" block_version "8.2.02" sg_icon_stat "30,31,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 31 31 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 31 31 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 19.4" "4 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 19.44 " "15.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\np" "atch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('in" "put',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa = b','texmo" "de','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational3" SID "3193" Ports [2, 1] Position [820, 447, 850, 478] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" block_version "8.2.02" sg_icon_stat "30,31,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 31 31 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 31 31 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 19.4" "4 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 19.44 " "15.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\np" "atch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('in" "put',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa = b','texmo" "de','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational4" SID "3194" Ports [2, 1] Position [820, 477, 850, 508] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" block_version "8.2.02" sg_icon_stat "30,31,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 31 31 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 31 31 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 19.4" "4 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 19.44 " "15.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\np" "atch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('in" "put',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa = b','texmo" "de','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational5" SID "3195" Ports [2, 1] Position [820, 507, 850, 538] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" block_version "8.2.02" sg_icon_stat "30,31,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 31 31 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 31 31 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 19.4" "4 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 19.44 " "15.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\np" "atch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('in" "put',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa = b','texmo" "de','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational6" SID "3196" Ports [2, 1] Position [820, 537, 850, 568] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" block_version "8.2.02" sg_icon_stat "30,31,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 31 31 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 31 31 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 19.4" "4 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 19.44 " "15.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\np" "atch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('in" "put',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa = b','texmo" "de','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational7" SID "3197" Ports [2, 1] Position [820, 567, 850, 598] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" block_version "8.2.02" sg_icon_stat "30,31,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 31 31 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 31 31 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 19.4" "4 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 19.44 " "15.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\np" "atch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('in" "put',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa = b','texmo" "de','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "WrEn[7:0]" SID "3198" Position [1160, 483, 1190, 497] IconDisplay "Port number" } Line { SrcBlock "From1" SrcPort 1 Points [35, 0] Branch { DstBlock "Concat1" DstPort 1 } Branch { Points [0, 10] Branch { DstBlock "Concat1" DstPort 2 } Branch { Points [0, 10] DstBlock "Concat1" DstPort 3 } } } Line { SrcBlock "Concat1" SrcPort 1 Points [80, 0; 0, 40] DstBlock "Logical4" DstPort 1 } Line { SrcBlock "3LSB" SrcPort 1 DstBlock "Logical4" DstPort 2 } Line { SrcBlock "Logical3" SrcPort 1 DstBlock "Concat" DstPort 4 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Relational" DstPort 2 } Line { SrcBlock "Constant2" SrcPort 1 DstBlock "Relational1" DstPort 2 } Line { SrcBlock "Constant3" SrcPort 1 DstBlock "Relational2" DstPort 2 } Line { SrcBlock "Constant4" SrcPort 1 DstBlock "Relational3" DstPort 2 } Line { SrcBlock "byte_addr" SrcPort 1 DstBlock "3LSB" DstPort 1 } Line { SrcBlock "Relational" SrcPort 1 DstBlock "Logical" DstPort 1 } Line { SrcBlock "Relational1" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Relational2" SrcPort 1 DstBlock "Logical2" DstPort 1 } Line { SrcBlock "Relational3" SrcPort 1 DstBlock "Logical3" DstPort 1 } Line { SrcBlock "Concat" SrcPort 1 DstBlock "WrEn[7:0]" DstPort 1 } Line { SrcBlock "Logical4" SrcPort 1 Points [160, 0; 0, 35] Branch { DstBlock "Relational" DstPort 1 } Branch { Points [0, 30] Branch { DstBlock "Relational1" DstPort 1 } Branch { Points [0, 30] Branch { DstBlock "Relational2" DstPort 1 } Branch { Points [0, 30] Branch { Points [0, 0] DstBlock "Relational3" DstPort 1 } Branch { Points [0, 30] Branch { Points [0, 30] Branch { Points [0, 30] Branch { DstBlock "Relational6" DstPort 1 } Branch { Points [0, 30] DstBlock "Relational7" DstPort 1 } } Branch { DstBlock "Relational5" DstPort 1 } } Branch { DstBlock "Relational4" DstPort 1 } } } } } } Line { SrcBlock "Logical" SrcPort 1 DstBlock "Concat" DstPort 1 } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Concat" DstPort 2 } Line { SrcBlock "Logical2" SrcPort 1 DstBlock "Concat" DstPort 3 } Line { SrcBlock "byte_valid" SrcPort 1 Points [160, 0; 0, -90] Branch { DstBlock "Logical8" DstPort 2 } Branch { Points [0, -30] Branch { DstBlock "Logical7" DstPort 2 } Branch { Points [0, -30] Branch { DstBlock "Logical6" DstPort 2 } Branch { Points [0, -30] Branch { Points [0, -30] Branch { Points [0, -30] Branch { Points [0, -30] Branch { Points [0, -30] DstBlock "Logical" DstPort 2 } Branch { DstBlock "Logical1" DstPort 2 } } Branch { DstBlock "Logical2" DstPort 2 } } Branch { DstBlock "Logical3" DstPort 2 } } Branch { DstBlock "Logical5" DstPort 2 } } } } } Line { SrcBlock "Logical8" SrcPort 1 DstBlock "Concat" DstPort 8 } Line { SrcBlock "Constant5" SrcPort 1 DstBlock "Relational4" DstPort 2 } Line { SrcBlock "Constant6" SrcPort 1 DstBlock "Relational5" DstPort 2 } Line { SrcBlock "Constant7" SrcPort 1 DstBlock "Relational6" DstPort 2 } Line { SrcBlock "Constant8" SrcPort 1 DstBlock "Relational7" DstPort 2 } Line { SrcBlock "Relational4" SrcPort 1 DstBlock "Logical5" DstPort 1 } Line { SrcBlock "Relational5" SrcPort 1 DstBlock "Logical6" DstPort 1 } Line { SrcBlock "Relational6" SrcPort 1 DstBlock "Logical7" DstPort 1 } Line { SrcBlock "Relational7" SrcPort 1 DstBlock "Logical8" DstPort 1 } Line { SrcBlock "Logical5" SrcPort 1 DstBlock "Concat" DstPort 5 } Line { SrcBlock "Logical6" SrcPort 1 DstBlock "Concat" DstPort 6 } Line { SrcBlock "Logical7" SrcPort 1 DstBlock "Concat" DstPort 7 } } } Block { BlockType Reference Name "Concat" SID "3199" Ports [4, 1] Position [1010, 255, 1060, 295] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point at z" "ero." num_inputs "4" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" block_version "8.2.02" sg_icon_stat "50,40,4,1,white,blue,0,47d3d416,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 40 40 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 50 50 0 0 ],[0 0 40 40 0 ]);\npatch([13.875 21.1 26.1 31.1 36.1 26.1 18.875 13.875 ],[25.55 25.55 3" "0.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([18.875 26.1 21.1 13.875 18.875 ],[20.55 20.55 25.55 25.55 " "20.55 ],[0.931 0.946 0.973 ]);\npatch([13.875 21.1 26.1 18.875 13.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1 1 ])" ";\npatch([18.875 36.1 31.1 26.1 21.1 13.875 18.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.946 0.9" "73 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_la" "bel('input',1,'hi');\n\n\ncolor('black');port_label('input',4,'lo');\n\ncolor('black');disp('\\fontsize{20}\\}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Concat1" SID "3200" Ports [4, 1] Position [945, 361, 990, 424] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point at z" "ero." num_inputs "4" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" block_version "8.2.02" sg_icon_stat "45,63,4,1,white,blue,0,47d3d416,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 63 63 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 63 63 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[37.66 37.66 4" "3.66 37.66 43.66 43.66 43.66 37.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[31.66 31.66 37.66 37.66 31" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[25.66 25.66 31.66 31.66 25.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[19.66 19.66 25.66 19.66 25.66 25.66 19.66 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('" "input',1,'hi');\n\n\ncolor('black');port_label('input',4,'lo');\n\ncolor('black');disp('\\fontsize{20}\\}','texmod" "e','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Concat2" SID "3201" Ports [2, 1] Position [295, 563, 340, 607] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point at z" "ero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" block_version "8.2.02" sg_icon_stat "45,44,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 28.66 3" "4.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 28.66 22" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('" "input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fontsize{20}\\}','texmode','" "on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Concat3" SID "3202" Ports [2, 1] Position [1280, 262, 1325, 313] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point at z" "ero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" block_version "8.2.02" sg_icon_stat "45,51,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 51 51 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 51 51 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[31.66 31.66 3" "7.66 31.66 37.66 37.66 37.66 31.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[25.66 25.66 31.66 31.66 25" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[19.66 19.66 25.66 25.66 19.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[13.66 13.66 19.66 13.66 19.66 19.66 13.66 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('" "input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fontsize{20}\\}','texmode','" "on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Concat4" SID "3203" Ports [2, 1] Position [365, 723, 410, 767] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point at z" "ero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" block_version "8.2.02" sg_icon_stat "45,44,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 28.66 3" "4.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 28.66 22" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('" "input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fontsize{20}\\}','texmode','" "on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Concat5" SID "3204" Ports [4, 1] Position [500, 910, 550, 950] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point at z" "ero." num_inputs "4" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" block_version "8.2.02" sg_icon_stat "50,40,4,1,white,blue,0,47d3d416,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 40 40 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 50 50 0 0 ],[0 0 40 40 0 ]);\npatch([13.875 21.1 26.1 31.1 36.1 26.1 18.875 13.875 ],[25.55 25.55 3" "0.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([18.875 26.1 21.1 13.875 18.875 ],[20.55 20.55 25.55 25.55 " "20.55 ],[0.931 0.946 0.973 ]);\npatch([13.875 21.1 26.1 18.875 13.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1 1 ])" ";\npatch([18.875 36.1 31.1 26.1 21.1 13.875 18.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.946 0.9" "73 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_la" "bel('input',1,'hi');\n\n\ncolor('black');port_label('input',4,'lo');\n\ncolor('black');disp('\\fontsize{20}\\}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Concat6" SID "3205" Ports [2, 1] Position [680, 921, 715, 959] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point at z" "ero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" block_version "8.2.02" sg_icon_stat "35,38,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 38 38 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 38 38 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[24.55 24.55 29." "55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[19.55 19.55 24.55 24.55 19." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input" "',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fontsize{20}\\}','texmode','on');" "\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Concat7" SID "3206" Ports [2, 1] Position [365, 673, 410, 717] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point at z" "ero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" block_version "8.2.02" sg_icon_stat "45,44,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 28.66 3" "4.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 28.66 22" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('" "input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fontsize{20}\\}','texmode','" "on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Constant1" SID "3207" Ports [0, 1] Position [305, 746, 320, 764] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "15,18,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11.22 13.22 " "11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 9.22 ],[0.931" " 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([4.55 11.44 9.44" " 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon" " graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'0');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Constant2" SID "3208" Ports [0, 1] Position [625, 941, 640, 959] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "4" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "15,18,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11.22 13.22 " "11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 9.22 ],[0.931" " 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([4.55 11.44 9.44" " 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon" " graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'0');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Constant3" SID "3209" Ports [0, 1] Position [870, 359, 890, 381] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "16" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period on period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "8.2.02" sg_icon_stat "20,22,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 20 20 0 0 ],[0 0 22 22 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[13.22 13.22 15." "22 13.22 15.22 15.22 15.22 13.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[11.22 11.22 13.22 13.22 11.22 ]" ",[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[9.22 9.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([7.55 " "14.44 12.44 10.44 8.44 5.55 7.55 ],[7.22 7.22 9.22 7.22 9.22 9.22 7.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'0');\nfpr" "intf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant4" SID "3210" Ports [0, 1] Position [295, 696, 310, 714] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "15,18,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11.22 13.22 " "11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 9.22 ],[0.931" " 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([4.55 11.44 9.44" " 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon" " graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'0');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Constant5" SID "3211" Ports [0, 1] Position [870, 404, 890, 426] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period on period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "8.2.02" sg_icon_stat "20,22,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 20 20 0 0 ],[0 0 22 22 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[13.22 13.22 15." "22 13.22 15.22 15.22 15.22 13.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[11.22 11.22 13.22 13.22 11.22 ]" ",[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[9.22 9.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([7.55 " "14.44 12.44 10.44 8.44 5.55 7.55 ],[7.22 7.22 9.22 7.22 9.22 9.22 7.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'0');\nfpr" "intf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant7" SID "3212" Ports [0, 1] Position [235, 586, 250, 604] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "15,18,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11.22 13.22 " "11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 9.22 ],[0.931" " 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([4.55 11.44 9.44" " 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon" " graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'0');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Convert" SID "3213" Ports [1, 1] Position [680, 872, 710, 888] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "8" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "30,16,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 16 16 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 16 16 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[10.22 10.22" " 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[8.22 8.22 10.22 10.22 8" ".22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatch" "([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output'" ",1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Display Name "Display" SID "3214" Ports [1] Position [435, 629, 525, 651] ZOrder -1 ShowName off Decimation "1" Lockdown off } Block { BlockType From Name "From1" SID "3215" Position [60, 211, 220, 229] ZOrder -9 ShowName off GotoTag "regRx_Record_Chan_Est_Pkt_Buf" TagVisibility "global" } Block { BlockType From Name "From2" SID "3216" Position [540, 306, 700, 324] ZOrder -9 ShowName off GotoTag "CHAN_EST_IQ_32b" TagVisibility "global" } Block { BlockType From Name "From3" SID "3217" Position [30, 676, 190, 694] ZOrder -9 ShowName off GotoTag "regRx_PktBuf_Rx_H_Est_Offset" TagVisibility "global" } Block { BlockType From Name "From4" SID "3218" Position [145, 726, 305, 744] ZOrder -9 ShowName off GotoTag "CHAN_EST_IND" TagVisibility "global" } Block { BlockType From Name "From5" SID "3219" Position [160, 906, 320, 924] ZOrder -9 ShowName off GotoTag "CHAN_EST_VALID" TagVisibility "global" } Block { BlockType From Name "From6" SID "3220" Position [60, 236, 220, 254] ZOrder -9 ShowName off GotoTag "CHAN_EST_VALID" TagVisibility "global" } Block { BlockType From Name "From7" SID "3221" Position [405, 799, 630, 821] ZOrder -9 ShowName off GotoTag "regRx_PKT_BUF_H_EST_ORDER_SWAP" TagVisibility "global" } Block { BlockType From Name "From9" SID "3222" Position [30, 566, 190, 584] ZOrder -9 ShowName off GotoTag "regRx_PktBuf_Rx_Addr_Offset" TagVisibility "global" } Block { BlockType Reference Name "Gateway Out1" SID "3223" Ports [1, 1] Position [1505, 454, 1540, 466] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "BRAM WEN" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out10" SID "3224" Ports [1, 1] Position [1505, 429, 1540, 441] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "BRAM Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out11" SID "3225" Ports [1, 1] Position [1645, 174, 1680, 186] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "Gateway Out12" SID "3226" Ports [1, 1] Position [1645, 229, 1680, 241] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "Gateway Out2" SID "3227" Ports [1, 1] Position [1505, 479, 1540, 491] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Rx Byte Index" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "3228" Ports [1, 1] Position [1505, 604, 1540, 616] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "H Est Valid" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "3229" Ports [1, 1] Position [1505, 504, 1540, 516] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Rx Byte Valid" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "3230" Ports [1, 1] Position [1505, 579, 1540, 591] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "H Est Ind" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "3231" Ports [1, 1] Position [1505, 554, 1540, 566] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "H Est WrEn" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "3232" Ports [1, 1] Position [1505, 529, 1540, 541] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Dout 32" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "3233" Ports [1, 1] Position [365, 634, 400, 646] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "Gateway Out9" SID "3234" Ports [1, 1] Position [1645, 124, 1680, 136] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "LSB" SID "3235" Ports [1, 1] Position [485, 820, 530, 840] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type" " is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardw" "are notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,442,407" block_type "slice" block_version "8.2.02" sg_icon_stat "45,20,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 20 20 0 ]);\npatch([17.55 20.44 22.44 24.44 26.44 22.44 19.55 17.55 ],[12.22 12.22" " 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([19.55 22.44 20.44 17.55 19.55 ],[10.22 10.22 12.22 12.22" " 10.22 ],[0.931 0.946 0.973 ]);\npatch([17.55 20.44 22.44 19.55 17.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\n" "patch([19.55 26.44 24.44 22.44 20.44 17.55 19.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('ou" "tput',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical" SID "3236" Ports [2, 1] Position [300, 209, 330, 256] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "8.2.02" sg_icon_stat "30,47,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 47 47 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 47 47 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[27.44 27.44 31.4" "4 27.44 31.44 31.44 31.44 27.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[23.44 23.44 27.44 27.44 23.44 ]," "[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[19.44 19.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1" " 23.88 19.88 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 15.44 19.44 19.44 15.44 ],[0.931 0.946 0.973 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('and');\nfpri" "ntf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical4" SID "3237" Ports [2, 1] Position [675, 799, 715, 841] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "XOR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,42,2,1,white,blue,0,dc21e094,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 42 42 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 42 42 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[26.55 26.55 31." "55 26.55 31.55 31.55 31.55 26.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[21.55 21.55 26.55 26.55 21." "55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[16.55 16.55 21.55 21.55 16.55 ],[1 1 1 ]);\npa" "tch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[11.55 11.55 16.55 11.55 16.55 16.55 11.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('x" "or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux" SID "3238" Ports [3, 1] Position [1180, 546, 1210, 644] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "30,98,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 14 84 98 0 ],[0.77 0.82 0." "91 ]);\nplot([0 30 30 0 0 ],[0 14 84 98 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[53.44 53.44 57" ".44 53.44 57.44 57.44 57.44 53.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[49.44 49.44 53.44 53.44 49.44 " "],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[45.44 45.44 49.44 49.44 45.44 ],[1 1 1 ]);\npatch([10" ".1 23.88 19.88 15.88 11.88 6.1 10.1 ],[41.44 41.44 45.44 41.44 45.44 45.44 41.44 ],[0.931 0.946 0.973 ]);\nfprintf" "('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3,'d1');\n\ncolor('black');d" "isp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux1" SID "3239" Ports [3, 1] Position [680, 391, 710, 489] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "30,98,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 14 84 98 0 ],[0.77 0.82 0." "91 ]);\nplot([0 30 30 0 0 ],[0 14 84 98 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[53.44 53.44 57" ".44 53.44 57.44 57.44 57.44 53.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[49.44 49.44 53.44 53.44 49.44 " "],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[45.44 45.44 49.44 49.44 45.44 ],[1 1 1 ]);\npatch([10" ".1 23.88 19.88 15.88 11.88 6.1 10.1 ],[41.44 41.44 45.44 41.44 45.44 45.44 41.44 ],[0.931 0.946 0.973 ]);\nfprintf" "('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3,'d1');\n\ncolor('black');d" "isp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux2" SID "3240" Ports [3, 1] Position [1180, 218, 1210, 332] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "30,114,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 16.2857 97.7143 114 0 ],[0" ".77 0.82 0.91 ]);\nplot([0 30 30 0 0 ],[0 16.2857 97.7143 114 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1" " 6.1 ],[61.44 61.44 65.44 61.44 65.44 65.44 65.44 61.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[57.44 57" ".44 61.44 61.44 57.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[53.44 53.44 57.44 57.44 53.44 ]" ",[1 1 1 ]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[49.44 49.44 53.44 49.44 53.44 53.44 49.44 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3,'d1'" ");\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux3" SID "3241" Ports [3, 1] Position [790, 788, 810, 972] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "20,184,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 26.2857 157.714 184 0 ],[0" ".77 0.82 0.91 ]);\nplot([0 20 20 0 0 ],[0 26.2857 157.714 184 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55" " 5.55 ],[94.22 94.22 96.22 94.22 96.22 96.22 96.22 94.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[92.22 9" "2.22 94.22 94.22 92.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[90.22 90.22 92.22 92.22 90.22" " ],[1 1 1 ]);\npatch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[88.22 88.22 90.22 88.22 90.22 90.22 88.22 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3,'d" "1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Scope Name "Pkt Buf Addr" SID "3242" Ports [8] Position [1660, 418, 1695, 627] ZOrder -3 Floating off Location [1158, 119, 2461, 1463] Open off NumInputPorts "8" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" } List { ListType ScopeGraphics FigureColor "[0.5 0.5 0.5]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "10000" YMin "0~0~0~0~0~-1~-1~-1" YMax "17.5~150~17.5~1~4.5e+009~1~1~1" SaveName "ScopeData27" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType ToWorkspace Name "To Workspace" SID "3243" Ports [1] Position [1720, 115, 1780, 145] ZOrder -7 VariableName "pkt_buf_bram_data" MaxDataPoints "inf" SampleTime "-1" SaveFormat "Array" } Block { BlockType ToWorkspace Name "To Workspace1" SID "3244" Ports [1] Position [1720, 165, 1780, 195] ZOrder -7 VariableName "pkt_buf_bram_addr" MaxDataPoints "inf" SampleTime "-1" SaveFormat "Array" } Block { BlockType ToWorkspace Name "To Workspace2" SID "3245" Ports [1] Position [1720, 220, 1780, 250] ZOrder -7 VariableName "pkt_buf_bram_wen" MaxDataPoints "inf" SampleTime "-1" SaveFormat "Array" } Line { Name "Rx Byte Valid" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 DstBlock "Pkt Buf Addr" DstPort 4 } Line { SrcBlock "9LSB + 3" SrcPort 1 DstBlock "Concat1" DstPort 3 } Line { SrcBlock "byte_valid" SrcPort 1 Points [150, 0] Branch { DstBlock "BRAM WEn Decoding" DstPort 2 } Branch { Points [0, -105] DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "AddSub2" SrcPort 1 Points [105, 0] Branch { Points [0, -135] DstBlock "Mux1" DstPort 2 } Branch { Points [105, 0] Branch { DstBlock "BRAM WEn Decoding" DstPort 1 } Branch { Points [0, -90] DstBlock "Gateway Out2" DstPort 1 } } } Line { SrcBlock "Pkt Buf Sel" SrcPort 1 DstBlock "Concat1" DstPort 2 } Line { SrcBlock "byte " SrcPort 1 Points [55, 0] Branch { DstBlock "Concat" DstPort 1 } Branch { Points [0, 10] Branch { DstBlock "Concat" DstPort 2 } Branch { Points [0, 10] Branch { DstBlock "Concat" DstPort 3 } Branch { Points [0, 10] DstBlock "Concat" DstPort 4 } } } } Line { Name "Rx Byte Index" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 DstBlock "Pkt Buf Addr" DstPort 3 } Line { Name "BRAM WEN" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 DstBlock "Pkt Buf Addr" DstPort 2 } Line { Name "BRAM Addr" Labels [0, 0] SrcBlock "Gateway Out10" SrcPort 1 DstBlock "Pkt Buf Addr" DstPort 1 } Line { SrcBlock "Constant3" SrcPort 1 DstBlock "Concat1" DstPort 1 } Line { SrcBlock "Constant5" SrcPort 1 DstBlock "Concat1" DstPort 4 } Line { SrcBlock "Concat1" SrcPort 1 Points [350, 0; 0, -85; 40, 0] Branch { Points [35, 0] Branch { DstBlock "BRAM I/O" DstPort 2 } Branch { Points [0, 125] DstBlock "Gateway Out10" DstPort 1 } } Branch { Points [0, -130] DstBlock "Gateway Out11" DstPort 1 } } Line { SrcBlock "BRAM WEn Decoding" SrcPort 1 DstBlock "Mux" DstPort 2 } Line { SrcBlock "byte_ind" SrcPort 1 DstBlock "AddSub2" DstPort 1 } Line { SrcBlock "Concat2" SrcPort 1 DstBlock "AddSub2" DstPort 2 } Line { SrcBlock "From9" SrcPort 1 DstBlock "Concat2" DstPort 1 } Line { SrcBlock "Constant7" SrcPort 1 DstBlock "Concat2" DstPort 2 } Line { Name "H Est Valid" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 DstBlock "Pkt Buf Addr" DstPort 8 } Line { SrcBlock "Mux2" SrcPort 1 Points [35, 0] Branch { DstBlock "Concat3" DstPort 1 } Branch { Points [0, 25] Branch { DstBlock "Concat3" DstPort 2 } Branch { Points [0, 235] DstBlock "Gateway Out7" DstPort 1 } } Branch { Points [0, -145] DstBlock "Gateway Out9" DstPort 1 } } Line { SrcBlock "Concat" SrcPort 1 DstBlock "Mux2" DstPort 2 } Line { SrcBlock "From4" SrcPort 1 Points [25, 0] Branch { DstBlock "Concat4" DstPort 1 } Branch { Points [0, 95] Branch { DstBlock "LSB" DstPort 1 } Branch { Points [0, 190; 1125, 0; 0, -435] DstBlock "Gateway Out5" DstPort 1 } } } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Concat4" DstPort 2 } Line { SrcBlock "Mux1" SrcPort 1 Points [55, 0] DstBlock "9LSB + 3" DstPort 1 } Line { SrcBlock "Logical" SrcPort 1 Points [115, 0] Branch { DstBlock "Mux2" DstPort 1 } Branch { Points [0, 175] Branch { DstBlock "Mux1" DstPort 1 } Branch { Points [0, 110; 665, 0; 0, 45] DstBlock "Mux" DstPort 1 } } } Line { SrcBlock "Mux3" SrcPort 1 Points [300, 0; 0, -195] Branch { Points [0, -60] DstBlock "Mux" DstPort 3 } Branch { Points [315, 0; 0, -125] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "From5" SrcPort 1 Points [145, 0] Branch { DstBlock "Concat5" DstPort 1 } Branch { Points [0, 10] Branch { DstBlock "Concat5" DstPort 2 } Branch { Points [0, 10] Branch { DstBlock "Concat5" DstPort 3 } Branch { Points [0, 10] Branch { DstBlock "Concat5" DstPort 4 } Branch { Points [0, 40; 1000, 0; 0, -375] DstBlock "Gateway Out3" DstPort 1 } } } } } Line { SrcBlock "Concat5" SrcPort 1 Points [65, 0] Branch { DstBlock "Concat6" DstPort 1 } Branch { Points [0, -50] DstBlock "Convert" DstPort 1 } } Line { SrcBlock "Constant2" SrcPort 1 DstBlock "Concat6" DstPort 2 } Line { SrcBlock "From1" SrcPort 1 DstBlock "Logical" DstPort 1 } Line { SrcBlock "From6" SrcPort 1 DstBlock "Logical" DstPort 2 } Line { SrcBlock "Concat4" SrcPort 1 Points [20, 0; 0, -30] DstBlock "AddSub1" DstPort 2 } Line { SrcBlock "Concat7" SrcPort 1 DstBlock "AddSub1" DstPort 1 } Line { SrcBlock "From3" SrcPort 1 Points [95, 0] Branch { DstBlock "Concat7" DstPort 1 } Branch { Points [0, -45] DstBlock "Gateway Out8" DstPort 1 } } Line { SrcBlock "Constant4" SrcPort 1 DstBlock "Concat7" DstPort 2 } Line { SrcBlock "AddSub1" SrcPort 1 Points [95, 0; 0, -235] DstBlock "Mux1" DstPort 3 } Line { SrcBlock "Concat3" SrcPort 1 DstBlock "BRAM I/O" DstPort 1 } Line { SrcBlock "Mux" SrcPort 1 Points [145, 0; 0, -265; 30, 0] Branch { Points [25, 0] Branch { DstBlock "BRAM I/O" DstPort 3 } Branch { Points [0, 130] DstBlock "Gateway Out1" DstPort 1 } } Branch { Points [0, -95] DstBlock "Gateway Out12" DstPort 1 } } Line { SrcBlock "Concat6" SrcPort 1 DstBlock "Mux3" DstPort 3 } Line { SrcBlock "Convert" SrcPort 1 DstBlock "Mux3" DstPort 2 } Line { SrcBlock "From7" SrcPort 1 DstBlock "Logical4" DstPort 1 } Line { SrcBlock "LSB" SrcPort 1 DstBlock "Logical4" DstPort 2 } Line { SrcBlock "Logical4" SrcPort 1 DstBlock "Mux3" DstPort 1 } Line { Name "H Est Ind" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 DstBlock "Pkt Buf Addr" DstPort 7 } Line { Name "H Est WrEn" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 DstBlock "Pkt Buf Addr" DstPort 6 } Line { SrcBlock "From2" SrcPort 1 DstBlock "Mux2" DstPort 3 } Line { Name "Dout 32" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 DstBlock "Pkt Buf Addr" DstPort 5 } Line { SrcBlock "Gateway Out8" SrcPort 1 DstBlock "Display" DstPort 1 } Line { SrcBlock "Gateway Out11" SrcPort 1 DstBlock "To Workspace1" DstPort 1 } Line { SrcBlock "Gateway Out9" SrcPort 1 DstBlock "To Workspace" DstPort 1 } Line { SrcBlock "Gateway Out12" SrcPort 1 DstBlock "To Workspace2" DstPort 1 } Annotation { Name "Word Addr\n(1K words max)" Position [809, 438] } } } Block { BlockType BusSelector Name "Bus\nSelector" SID "3246" Ports [1, 4] Position [230, 137, 240, 213] ZOrder -3 ShowName off OutputSignals "byte_valid,byte_index,byte,last_byte" Port { PortNumber 1 Name "" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 2 Name "" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 3 Name "" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 4 Name "" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType BusSelector Name "Bus\nSelector1" SID "3247" Ports [1, 4] Position [230, 47, 240, 123] ZOrder -3 ShowName off OutputSignals "byte_valid,byte_index,byte,last_byte" Port { PortNumber 1 Name "" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 2 Name "" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 3 Name "" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 4 Name "" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType SubSystem Name "DSSS Addr Calc" SID "3248" Ports [1, 1] Position [320, 424, 380, 446] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "DSSS Addr Calc" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "R" SID "3249" Position [560, 413, 590, 427] IconDisplay "Port number" } Block { BlockType Reference Name "AddSub1" SID "3250" Ports [2, 1] Position [685, 455, 730, 495] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "0" precision "Full" arith_type "Unsigned" n_bits "3" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL off hw_selection "Fabric" pipelined off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" sg_icon_stat "45,40,2,1,white,blue,0,e139daf6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 40 40 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 40 40 0 ]);\npatch([10.875 18.1 23.1 28.1 33.1 23.1 15.875 10.875 ],[25.55 25.55 3" "0.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([15.875 23.1 18.1 10.875 15.875 ],[20.55 20.55 25.55 25.55 " "20.55 ],[0.931 0.946 0.973 ]);\npatch([10.875 18.1 23.1 15.875 10.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1 1 ])" ";\npatch([15.875 33.1 28.1 23.1 18.1 10.875 15.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.946 0.9" "73 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_la" "bel('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bf{a + b}'" ",'texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant1" SID "3251" Ports [0, 1] Position [605, 426, 620, 444] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "5" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "15,18,0,1,white,blue,0,98872051,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11.22 13.22 " "11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 9.22 ],[0.931" " 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([4.55 11.44 9.44" " 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon" " graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'5');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Constant3" SID "3252" Ports [0, 1] Position [590, 475, 620, 495] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "10" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "4" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,20,0,1,white,blue,0,46ffeebb,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 20 20 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[12.22 12.22" " 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[10.22 10.22 12.22 12.22" " 10.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\n" "patch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('outp" "ut',1,'10');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux5" SID "3253" Ports [3, 1] Position [800, 408, 825, 542] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "25,134,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 19.1429 114.857 134 0 ],[0" ".77 0.82 0.91 ]);\nplot([0 25 25 0 0 ],[0 19.1429 114.857 134 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.3" "25 5.325 ],[70.33 70.33 73.33 70.33 73.33 73.33 73.33 70.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[6" "7.33 67.33 70.33 70.33 67.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[64.33 64.33 67.33 67" ".33 64.33 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[61.33 61.33 64.33 61.33 64.33 64.33 61." "33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nc" "olor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label(" "'input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational" SID "3254" Ports [2, 1] Position [690, 412, 725, 443] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a<=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,31,2,1,white,blue,0,52e4b236,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 31 31 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 31 31 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[19.44 19.44 23.4" "4 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[15.44 15.44 19.44 19.44 15.44 ]," "[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([12.1" " 25.88 21.88 17.88 13.88 8.1 12.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'a');\n" "color('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa \\leq b','texmode','on');\n" "color('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "M" SID "3255" Position [885, 468, 915, 482] IconDisplay "Port number" } Line { SrcBlock "Mux5" SrcPort 1 DstBlock "M" DstPort 1 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Relational" DstPort 2 } Line { SrcBlock "Relational" SrcPort 1 DstBlock "Mux5" DstPort 1 } Line { SrcBlock "R" SrcPort 1 Points [65, 0] Branch { DstBlock "Relational" DstPort 1 } Branch { Points [0, 45] Branch { DstBlock "AddSub1" DstPort 1 } Branch { Points [0, 55] DstBlock "Mux5" DstPort 3 } } } Line { SrcBlock "Constant3" SrcPort 1 DstBlock "AddSub1" DstPort 2 } Line { SrcBlock "AddSub1" SrcPort 1 DstBlock "Mux5" DstPort 2 } Annotation { Name "DSSS Byte Index Rx -> Memory mapping\n\nR=Rx byte index\nM=Memory byte index\n\nR M\n0 0 SIGNAL[0]\n" "1 1 SERVICE[0]\n2 2 LENGTH[0]\n3 3 LENGTH[1]\n4 4 CRC16[0]\n5 5 CRC16[1]\n 6 no write\n ...\n " " 15 no write\n6 16 MPDU[0]\n7 17 MPDU[1]\n8 18 MPDU[2]\n..." Position [674, 244] HorizontalAlignment "left" FontName "Consolas" FontSize 12 } } } Block { BlockType From Name "From" SID "3256" Position [670, 87, 785, 103] ZOrder -9 ShowName off GotoTag "DSSS_Byte_Valid" } Block { BlockType From Name "From18" SID "3257" Position [130, 402, 245, 418] ZOrder -9 ShowName off GotoTag "OFDM_Byte_Index" } Block { BlockType From Name "From20" SID "3258" Position [670, 207, 785, 223] ZOrder -9 ShowName off GotoTag "OFDM_Byte_Valid" } Block { BlockType From Name "From23" SID "3259" Position [265, 477, 380, 493] ZOrder -9 ShowName off GotoTag "DSSS_Byte_Valid" } Block { BlockType From Name "From27" SID "3260" Position [220, 501, 380, 519] ZOrder -9 ShowName off GotoTag "regRx_OFDM_PKT_BUF_SEL" TagVisibility "global" } Block { BlockType From Name "From29" SID "3261" Position [130, 367, 245, 383] ZOrder -9 ShowName off GotoTag "DSSS_Byte_Valid" } Block { BlockType From Name "From3" SID "3262" Position [670, 192, 785, 208] ZOrder -9 ShowName off GotoTag "DSSS_Byte_Valid" } Block { BlockType From Name "From30" SID "3263" Position [560, 343, 705, 357] ZOrder -9 ShowName off GotoTag "CUR_RX_BYTE" } Block { BlockType From Name "From31" SID "3264" Position [560, 373, 705, 387] ZOrder -9 ShowName off GotoTag "CUR_RX_BYTE_VALID" } Block { BlockType From Name "From32" SID "3265" Position [130, 427, 245, 443] ZOrder -9 ShowName off GotoTag "DSSS_Byte_Index" } Block { BlockType From Name "From4" SID "3266" Position [670, 137, 785, 153] ZOrder -9 ShowName off GotoTag "DSSS_Byte" } Block { BlockType From Name "From5" SID "3267" Position [670, 112, 785, 128] ZOrder -9 ShowName off GotoTag "OFDM_Byte" } Block { BlockType From Name "From9" SID "3268" Position [220, 526, 380, 544] ZOrder -9 ShowName off GotoTag "regRx_DSSS_PKT_BUF_SEL" TagVisibility "global" } Block { BlockType Goto Name "Goto" SID "3269" Position [305, 48, 450, 62] ZOrder -10 ShowName off GotoTag "DSSS_Byte_Valid" TagVisibility "local" } Block { BlockType Goto Name "Goto1" SID "3270" Position [305, 68, 450, 82] ZOrder -10 ShowName off GotoTag "DSSS_Byte_Index" TagVisibility "local" } Block { BlockType Goto Name "Goto12" SID "3271" Position [980, 111, 1135, 129] ShowName off GotoTag "CUR_RX_BYTE" TagVisibility "local" } Block { BlockType Goto Name "Goto15" SID "3272" Position [980, 201, 1135, 219] ShowName off GotoTag "CUR_RX_BYTE_VALID" TagVisibility "local" } Block { BlockType Goto Name "Goto2" SID "3273" Position [305, 88, 450, 102] ZOrder -10 ShowName off GotoTag "DSSS_Byte" TagVisibility "local" } Block { BlockType Goto Name "Goto3" SID "3274" Position [305, 108, 450, 122] ZOrder -10 ShowName off GotoTag "DSSS_Last_Byte" TagVisibility "local" } Block { BlockType Goto Name "Goto4" SID "3275" Position [300, 138, 445, 152] ZOrder -10 ShowName off GotoTag "OFDM_Byte_Valid" TagVisibility "local" } Block { BlockType Goto Name "Goto5" SID "3276" Position [300, 158, 445, 172] ZOrder -10 ShowName off GotoTag "OFDM_Byte_Index" TagVisibility "local" } Block { BlockType Goto Name "Goto6" SID "3277" Position [300, 178, 445, 192] ZOrder -10 ShowName off GotoTag "OFDM_Byte" TagVisibility "local" } Block { BlockType Goto Name "Goto7" SID "3278" Position [300, 198, 445, 212] ZOrder -10 ShowName off GotoTag "OFDM_Last_Byte" TagVisibility "local" } Block { BlockType Reference Name "Logical7" SID "3279" Ports [2, 1] Position [860, 194, 895, 221] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,27,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 27 27 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 27 27 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ]" ",[16.33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[13.3" "3 13.33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[10.33 10.33 13.3" "3 13.33 10.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[7.33 7.33 10.33 7.33 10.33 1" "0.33 7.33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon " "text');\n\n\n\ncolor('black');disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux2" SID "3280" Ports [3, 1] Position [865, 79, 890, 161] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "25,82,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 11.7143 70.2857 82 " "0 ],[0.77 0.82 0.91 ]);\nplot([0 25 25 0 0 ],[0 11.7143 70.2857 82 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 1" "2.66 8.325 5.325 ],[44.33 44.33 47.33 44.33 47.33 47.33 47.33 44.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325" " 8.325 ],[41.33 41.33 44.33 44.33 41.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[38.33 " "38.33 41.33 41.33 38.33 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[35.33 35.33 38.33 35.3" "3 38.33 38.33 35.33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: b" "egin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncol" "or('black');port_label('input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: " "end icon text');" } Block { BlockType Reference Name "Mux3" SID "3281" Ports [3, 1] Position [460, 469, 485, 551] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "25,82,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 11.7143 70.2857 82 " "0 ],[0.77 0.82 0.91 ]);\nplot([0 25 25 0 0 ],[0 11.7143 70.2857 82 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 1" "2.66 8.325 5.325 ],[44.33 44.33 47.33 44.33 47.33 47.33 47.33 44.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325" " 8.325 ],[41.33 41.33 44.33 44.33 41.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[38.33 " "38.33 41.33 41.33 38.33 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[35.33 35.33 38.33 35.3" "3 38.33 38.33 35.33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: b" "egin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncol" "or('black');port_label('input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: " "end icon text');" } Block { BlockType Reference Name "Mux5" SID "3282" Ports [3, 1] Position [460, 369, 485, 451] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "25,82,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 11.7143 70.2857 82 " "0 ],[0.77 0.82 0.91 ]);\nplot([0 25 25 0 0 ],[0 11.7143 70.2857 82 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 1" "2.66 8.325 5.325 ],[44.33 44.33 47.33 44.33 47.33 47.33 47.33 44.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325" " 8.325 ],[41.33 41.33 44.33 44.33 41.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[38.33 " "38.33 41.33 41.33 38.33 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[35.33 35.33 38.33 35.3" "3 38.33 38.33 35.33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: b" "egin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncol" "or('black');port_label('input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: " "end icon text');" } Block { BlockType SubSystem Name "OFDM Addr Calc" SID "3283" Ports [1, 1] Position [320, 399, 380, 421] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "OFDM Addr Calc" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "R" SID "3284" Position [550, 303, 580, 317] IconDisplay "Port number" } Block { BlockType Reference Name "AddSub1" SID "3285" Ports [2, 1] Position [685, 455, 730, 495] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "0" precision "Full" arith_type "Unsigned" n_bits "3" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL off hw_selection "Fabric" pipelined off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" sg_icon_stat "45,40,2,1,white,blue,0,e139daf6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 40 40 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 40 40 0 ]);\npatch([10.875 18.1 23.1 28.1 33.1 23.1 15.875 10.875 ],[25.55 25.55 3" "0.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([15.875 23.1 18.1 10.875 15.875 ],[20.55 20.55 25.55 25.55 " "20.55 ],[0.931 0.946 0.973 ]);\npatch([10.875 18.1 23.1 15.875 10.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1 1 ])" ";\npatch([15.875 33.1 28.1 23.1 18.1 10.875 15.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.946 0.9" "73 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_la" "bel('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bf{a + b}'" ",'texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant1" SID "3286" Ports [0, 1] Position [385, 421, 410, 449] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "4" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,28,0,1,white,blue,0,85f36853,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 17.33 " "20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33 17.33 1" "4.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1 1 1 ]);\n" "patch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('out" "put',1,'4');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant2" SID "3287" Ports [0, 1] Position [385, 556, 410, 584] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "11" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "4" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,28,0,1,white,blue,0,997df0ab,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 17.33 " "20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33 17.33 1" "4.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1 1 1 ]);\n" "patch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('out" "put',1,'11');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant3" SID "3288" Ports [0, 1] Position [385, 466, 410, 494] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "10" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "4" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,28,0,1,white,blue,0,46ffeebb,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 17.33 " "20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33 17.33 1" "4.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1 1 1 ]);\n" "patch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('out" "put',1,'10');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant4" SID "3289" Ports [0, 1] Position [385, 601, 410, 629] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "5" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,28,0,1,white,blue,0,98872051,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 17.33 " "20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33 17.33 1" "4.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1 1 1 ]);\n" "patch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('out" "put',1,'5');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "3290" Position [225, 378, 390, 402] ZOrder -9 ShowName off GotoTag "RX_PHY_MODE_11N_AC" TagVisibility "global" } Block { BlockType Reference Name "Mux1" SID "3291" Ports [3, 1] Position [460, 368, 485, 502] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "25,134,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 19.1429 114.857 134 0 ],[0" ".77 0.82 0.91 ]);\nplot([0 25 25 0 0 ],[0 19.1429 114.857 134 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.3" "25 5.325 ],[70.33 70.33 73.33 70.33 73.33 73.33 73.33 70.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[6" "7.33 67.33 70.33 70.33 67.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[64.33 64.33 67.33 67" ".33 64.33 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[61.33 61.33 64.33 61.33 64.33 64.33 61." "33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nc" "olor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label(" "'input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux2" SID "3292" Ports [3, 1] Position [460, 503, 485, 637] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "25,134,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 19.1429 114.857 134 0 ],[0" ".77 0.82 0.91 ]);\nplot([0 25 25 0 0 ],[0 19.1429 114.857 134 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.3" "25 5.325 ],[70.33 70.33 73.33 70.33 73.33 73.33 73.33 70.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[6" "7.33 67.33 70.33 70.33 67.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[64.33 64.33 67.33 67" ".33 64.33 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[61.33 61.33 64.33 61.33 64.33 64.33 61." "33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nc" "olor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label(" "'input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux5" SID "3293" Ports [3, 1] Position [800, 408, 825, 542] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "25,134,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 19.1429 114.857 134 0 ],[0" ".77 0.82 0.91 ]);\nplot([0 25 25 0 0 ],[0 19.1429 114.857 134 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.3" "25 5.325 ],[70.33 70.33 73.33 70.33 73.33 73.33 73.33 70.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[6" "7.33 67.33 70.33 70.33 67.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[64.33 64.33 67.33 67" ".33 64.33 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[61.33 61.33 64.33 61.33 64.33 64.33 61." "33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nc" "olor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label(" "'input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational" SID "3294" Ports [2, 1] Position [690, 412, 725, 443] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a<=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,31,2,1,white,blue,0,52e4b236,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 31 31 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 31 31 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[19.44 19.44 23.4" "4 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[15.44 15.44 19.44 19.44 15.44 ]," "[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([12.1" " 25.88 21.88 17.88 13.88 8.1 12.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'a');\n" "color('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa \\leq b','texmode','on');\n" "color('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "M" SID "3295" Position [885, 468, 915, 482] IconDisplay "Port number" } Line { SrcBlock "Mux2" SrcPort 1 Points [140, 0; 0, -85] DstBlock "AddSub1" DstPort 2 } Line { SrcBlock "R" SrcPort 1 Points [75, 0; 0, 110] Branch { DstBlock "Relational" DstPort 1 } Branch { Points [0, 45] Branch { DstBlock "AddSub1" DstPort 1 } Branch { Points [0, 55] DstBlock "Mux5" DstPort 3 } } } Line { SrcBlock "Relational" SrcPort 1 DstBlock "Mux5" DstPort 1 } Line { SrcBlock "Mux5" SrcPort 1 DstBlock "M" DstPort 1 } Line { SrcBlock "AddSub1" SrcPort 1 DstBlock "Mux5" DstPort 2 } Line { SrcBlock "From" SrcPort 1 Points [35, 0] Branch { DstBlock "Mux1" DstPort 1 } Branch { Points [0, 135] DstBlock "Mux2" DstPort 1 } } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Mux1" DstPort 2 } Line { SrcBlock "Mux1" SrcPort 1 DstBlock "Relational" DstPort 2 } Line { SrcBlock "Constant2" SrcPort 1 DstBlock "Mux2" DstPort 2 } Line { SrcBlock "Constant3" SrcPort 1 DstBlock "Mux1" DstPort 3 } Line { SrcBlock "Constant4" SrcPort 1 DstBlock "Mux2" DstPort 3 } Annotation { Name "OFDM Byte Index Rx -> Memory mapping\n11a/g Rx\n\nR=Rx byte index\nM=Memory byte index\n\nR M\n0 0 S" "IGNAL[0]\n1 1 SIGNAL[1]\n2 2 SIGNAL[2]\n3 3 SERVICE[0]\n4 4 SERVICE[1]\n 5 no write\n ...\n 15" " no write\n5 16 MPDU[0]\n6 17 MPDU[1]\n..." Position [964, 239] HorizontalAlignment "left" FontName "Consolas" FontSize 12 } Annotation { Name "OFDM Byte Index Rx -> Memory mapping\n11n/ac Rx\n\nR=Rx byte index\nM=Memory byte index\n\nR M\n0 0 " "SIGNAL[0]\n1 1 SIGNAL[1]\n2 2 SIGNAL[2]\n3 3 HT-SIG[0]\n4 4 HT-SIG[1]\n5 5 HT-SIG[2]\n6 6 HT-SIG" "[3]\n7 7 HT-SIG[4]\n8 8 HT-SIG[5]\n9 9 SERVICE[0]\n10 10 SERVICE[1]\n 11 no write\n...\n 15 no wri" "te\n11 16 MAC Payload[0]\n12 17 MAC Payload[1]\n..." Position [1249, 279] HorizontalAlignment "left" FontName "Consolas" FontSize 12 } } } Block { BlockType Reference Name "Register4" SID "3296" Ports [1, 1] Position [955, 425, 985, 455] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 30 30 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 30 30 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 " "19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 1" "9.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register5" SID "3297" Ports [1, 1] Position [955, 395, 985, 425] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 30 30 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 30 30 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 " "19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 1" "9.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register7" SID "3298" Ports [1, 1] Position [955, 335, 985, 365] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 30 30 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 30 30 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 " "19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 1" "9.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register8" SID "3299" Ports [1, 1] Position [955, 365, 985, 395] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 30 30 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 30 30 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 " "19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 1" "9.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Rx Data MAC\nOutputs" SID "3300" Ports [3] Position [1080, 481, 1160, 549] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Rx Data MAC\nOutputs" Location [2081, 120, 2846, 988] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Byte " SID "3301" Position [625, 658, 655, 672] IconDisplay "Port number" } Block { BlockType Inport Name "Byte Valid" SID "3302" Position [625, 598, 655, 612] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "Byte Ind" SID "3303" Position [620, 508, 650, 522] NamePlacement "alternate" Port "3" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub1" SID "3304" Ports [2, 1] Position [765, 507, 800, 538] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Subtraction" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Unsigned" n_bits "ceil(log2(MAX_NUM_BYTES))" bin_pt "0" quantization "Truncate" overflow "Saturate" dbl_ovrd off use_behavioral_HDL off hw_selection "Fabric" pipelined off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" sg_icon_stat "35,31,2,1,white,blue,0,32e1f85f,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 31 31 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 31 31 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[19.44 19.44 23.4" "4 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[15.44 15.44 19.44 19.44 15.44 ]," "[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([12.1" " 25.88 21.88 17.88 13.88 8.1 12.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'a');\n" "color('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bf{a - b}','texmode','on');\nfp" "rintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant4" SID "3305" Ports [0, 1] Position [665, 520, 695, 540] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "16" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "5" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,20,0,1,white,blue,0,eafdfd08,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 20 20 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[12.22 12.22" " 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[10.22 10.22 12.22 12.22" " 10.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\n" "patch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('outp" "ut',1,'16');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Goto Name "Goto11" SID "3306" Position [975, 516, 1130, 534] ShowName off GotoTag "CUR_MPDU_BYTE_INDEX" TagVisibility "global" } Block { BlockType Goto Name "Goto16" SID "3307" Position [975, 586, 1130, 604] ShowName off GotoTag "CUR_MPDU_BYTE_VALID" TagVisibility "global" } Block { BlockType Goto Name "Goto8" SID "3308" Position [975, 656, 1130, 674] ShowName off GotoTag "CUR_MPDU_BYTE" TagVisibility "global" } Block { BlockType Reference Name "Logical4" SID "3309" Ports [2, 1] Position [830, 574, 870, 616] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,42,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 42 42 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 42 42 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[26.55 26.55 31." "55 26.55 31.55 31.55 31.55 26.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[21.55 21.55 26.55 26.55 21." "55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[16.55 16.55 21.55 21.55 16.55 ],[1 1 1 ]);\npa" "tch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[11.55 11.55 16.55 11.55 16.55 16.55 11.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('a" "nd');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational2" SID "3310" Ports [2, 1] Position [760, 567, 795, 598] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a>=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,31,2,1,white,blue,0,6218dc92,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 31 31 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 31 31 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[19.44 19.44 23.4" "4 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[15.44 15.44 19.44 19.44 15.44 ]," "[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([12.1" " 25.88 21.88 17.88 13.88 8.1 12.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'a');\n" "color('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa \\geq b','texmode','on');\n" "color('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Line { SrcBlock "Logical4" SrcPort 1 DstBlock "Goto16" DstPort 1 } Line { SrcBlock "Relational2" SrcPort 1 DstBlock "Logical4" DstPort 1 } Line { SrcBlock "AddSub1" SrcPort 1 DstBlock "Goto11" DstPort 1 } Line { SrcBlock "Constant4" SrcPort 1 Points [20, 0] Branch { DstBlock "AddSub1" DstPort 2 } Branch { Points [0, 60] DstBlock "Relational2" DstPort 2 } } Line { SrcBlock "Byte Ind" SrcPort 1 Points [75, 0] Branch { DstBlock "AddSub1" DstPort 1 } Branch { Points [0, 60] DstBlock "Relational2" DstPort 1 } } Line { SrcBlock "Byte Valid" SrcPort 1 DstBlock "Logical4" DstPort 2 } Line { SrcBlock "Byte " SrcPort 1 DstBlock "Goto8" DstPort 1 } Annotation { Name "Byte index output to MAC is\nindexed so 0 = MPDU start\n(0x10 into pkt buffer)" Position [749, 451] } Annotation { Name "Outputs to MAC hw" Position [1203, 594] } } } Line { SrcBlock "From23" SrcPort 1 DstBlock "Mux3" DstPort 1 } Line { SrcBlock "From32" SrcPort 1 DstBlock "DSSS Addr Calc" DstPort 1 } Line { SrcBlock "DSSS Addr Calc" SrcPort 1 DstBlock "Mux5" DstPort 3 } Line { SrcBlock "From29" SrcPort 1 Points [160, 0; 0, 10] DstBlock "Mux5" DstPort 1 } Line { SrcBlock "Mux5" SrcPort 1 DstBlock "Addr Check" DstPort 2 } Line { SrcBlock "From18" SrcPort 1 DstBlock "OFDM Addr Calc" DstPort 1 } Line { SrcBlock "OFDM Addr Calc" SrcPort 1 DstBlock "Mux5" DstPort 2 } Line { SrcBlock "Mux3" SrcPort 1 Points [355, 0; 0, -70] DstBlock "Register4" DstPort 1 } Line { SrcBlock "Register4" SrcPort 1 DstBlock "BRAM IF 64b" DstPort 4 } Line { SrcBlock "From30" SrcPort 1 DstBlock "Register7" DstPort 1 } Line { SrcBlock "From31" SrcPort 1 DstBlock "Addr Check" DstPort 1 } Line { SrcBlock "Register7" SrcPort 1 Points [50, 0] Branch { DstBlock "BRAM IF 64b" DstPort 1 } Branch { Points [0, 145] DstBlock "Rx Data MAC\nOutputs" DstPort 1 } } Line { SrcBlock "Register8" SrcPort 1 Points [45, 0] Branch { DstBlock "BRAM IF 64b" DstPort 2 } Branch { Points [0, 135] DstBlock "Rx Data MAC\nOutputs" DstPort 2 } } Line { SrcBlock "Register5" SrcPort 1 Points [40, 0] Branch { DstBlock "BRAM IF 64b" DstPort 3 } Branch { Points [0, 125] DstBlock "Rx Data MAC\nOutputs" DstPort 3 } } Line { Name "" Labels [0, 0] SrcBlock "Bus\nSelector1" SrcPort 1 DstBlock "Goto" DstPort 1 } Line { Name "" Labels [0, 0] SrcBlock "Bus\nSelector1" SrcPort 2 DstBlock "Goto1" DstPort 1 } Line { Name "" Labels [0, 0] SrcBlock "Bus\nSelector1" SrcPort 3 DstBlock "Goto2" DstPort 1 } Line { Name "" Labels [0, 0] SrcBlock "Bus\nSelector1" SrcPort 4 DstBlock "Goto3" DstPort 1 } Line { Name "" Labels [0, 0] SrcBlock "Bus\nSelector" SrcPort 1 DstBlock "Goto4" DstPort 1 } Line { Name "" Labels [0, 0] SrcBlock "Bus\nSelector" SrcPort 2 DstBlock "Goto5" DstPort 1 } Line { Name "" Labels [0, 0] SrcBlock "Bus\nSelector" SrcPort 3 DstBlock "Goto6" DstPort 1 } Line { Name "" Labels [0, 0] SrcBlock "Bus\nSelector" SrcPort 4 DstBlock "Goto7" DstPort 1 } Line { SrcBlock "DSSS data" SrcPort 1 DstBlock "Bus\nSelector1" DstPort 1 } Line { SrcBlock "OFDM data" SrcPort 1 DstBlock "Bus\nSelector" DstPort 1 } Line { SrcBlock "From" SrcPort 1 DstBlock "Mux2" DstPort 1 } Line { SrcBlock "From5" SrcPort 1 DstBlock "Mux2" DstPort 2 } Line { SrcBlock "From4" SrcPort 1 DstBlock "Mux2" DstPort 3 } Line { SrcBlock "Mux2" SrcPort 1 DstBlock "Goto12" DstPort 1 } Line { SrcBlock "From3" SrcPort 1 DstBlock "Logical7" DstPort 1 } Line { SrcBlock "From20" SrcPort 1 DstBlock "Logical7" DstPort 2 } Line { SrcBlock "Logical7" SrcPort 1 DstBlock "Goto15" DstPort 1 } Line { SrcBlock "From27" SrcPort 1 DstBlock "Mux3" DstPort 2 } Line { SrcBlock "From9" SrcPort 1 DstBlock "Mux3" DstPort 3 } Line { SrcBlock "Addr Check" SrcPort 1 DstBlock "Register8" DstPort 1 } Line { SrcBlock "Addr Check" SrcPort 2 DstBlock "Register5" DstPort 1 } } } Line { SrcBlock "OFDM data" SrcPort 1 Points [10, 0] Branch { DstBlock "Bus\nSelector" DstPort 1 } Branch { Points [0, 135] Branch { Points [0, 0] DstBlock "Pkt Buf Interface" DstPort 2 } Branch { Points [0, 55] DstBlock "FCS Calc" DstPort 2 } } } Line { SrcBlock "DSSS data" SrcPort 1 Points [20, 0] Branch { DstBlock "Bus\nSelector1" DstPort 1 } Branch { Points [0, 195] Branch { DstBlock "Pkt Buf Interface" DstPort 1 } Branch { Points [0, 55] DstBlock "FCS Calc" DstPort 1 } } } Line { Name "" Labels [0, 0] SrcBlock "Bus\nSelector1" SrcPort 1 DstBlock "Gateway Out9" DstPort 1 } Line { Name "" Labels [0, 0] SrcBlock "Bus\nSelector1" SrcPort 2 DstBlock "Gateway Out8" DstPort 1 } Line { Name "" Labels [0, 0] SrcBlock "Bus\nSelector1" SrcPort 3 DstBlock "Gateway Out11" DstPort 1 } Line { Name "" Labels [0, 0] SrcBlock "Bus\nSelector1" SrcPort 4 DstBlock "Gateway Out12" DstPort 1 } Line { Name "" Labels [0, 0] SrcBlock "Bus\nSelector" SrcPort 1 DstBlock "Gateway Out1" DstPort 1 } Line { Name "" Labels [0, 0] SrcBlock "Bus\nSelector" SrcPort 2 DstBlock "Gateway Out2" DstPort 1 } Line { Name "" Labels [0, 0] SrcBlock "Bus\nSelector" SrcPort 3 DstBlock "Gateway Out3" DstPort 1 } Line { Name "" Labels [0, 0] SrcBlock "Bus\nSelector" SrcPort 4 DstBlock "Gateway Out4" DstPort 1 } Line { Name "DSSS Valid" Labels [0, 0] SrcBlock "Gateway Out9" SrcPort 1 DstBlock "Bytes In" DstPort 1 } Line { Name "DSSS Byte Index" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 DstBlock "Bytes In" DstPort 2 } Line { Name "DSSS Byte" Labels [0, 0] SrcBlock "Gateway Out11" SrcPort 1 DstBlock "Bytes In" DstPort 3 } Line { Name "DSSS Last Byte" Labels [0, 0] SrcBlock "Gateway Out12" SrcPort 1 DstBlock "Bytes In" DstPort 4 } Line { Name "OFDM Valid" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 DstBlock "Bytes In" DstPort 5 } Line { Name "OFDM Byte Index" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 DstBlock "Bytes In" DstPort 6 } Line { Name "OFDM Byte" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 DstBlock "Bytes In" DstPort 7 } Line { Name "OFDM Last Byte" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 DstBlock "Bytes In" DstPort 8 } } } Block { BlockType SubSystem Name "FFT" SID "3311" Ports [5, 6] Position [550, 142, 705, 243] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "FFT" Location [2, 74, 2464, 1576] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "104" Block { BlockType Inport Name "data_in_xn_im" SID "3312" Position [215, 518, 245, 532] IconDisplay "Port number" } Block { BlockType Inport Name "data_in_xn_re" SID "3313" Position [215, 558, 245, 572] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "data_in_tvalid" SID "3314" Position [215, 598, 245, 612] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "data_in_tlast" SID "3315" Position [215, 638, 245, 652] Port "4" IconDisplay "Port number" } Block { BlockType Inport Name "Reset" SID "3316" Position [215, 928, 245, 942] Port "5" IconDisplay "Port number" } Block { BlockType Reference Name "Constant3" SID "3317" Ports [0, 1] Position [420, 674, 435, 696] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period on period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "15,22,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.91" " ]);\nplot([0 15 15 0 0 ],[0 0 22 22 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[13.22 13.22 15.22 13" ".22 15.22 15.22 15.22 13.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[11.22 11.22 13.22 13.22 11.22 ],[0.931" " 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[9.22 9.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([4.55 11.44 9.4" "4 7.44 5.44 2.55 4.55 ],[7.22 7.22 9.22 7.22 9.22 9.22 7.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon" " graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Constant4" SID "3318" Ports [0, 1] Position [415, 474, 430, 496] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period on period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "15,22,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.91" " ]);\nplot([0 15 15 0 0 ],[0 0 22 22 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[13.22 13.22 15.22 13" ".22 15.22 15.22 15.22 13.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[11.22 11.22 13.22 13.22 11.22 ],[0.931" " 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[9.22 9.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([4.55 11.44 9.4" "4 7.44 5.44 2.55 4.55 ],[7.22 7.22 9.22 7.22 9.22 9.22 7.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon" " graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Constant5" SID "3319" Ports [0, 1] Position [415, 434, 430, 456] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period on period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "15,22,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.91" " ]);\nplot([0 15 15 0 0 ],[0 0 22 22 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[13.22 13.22 15.22 13" ".22 15.22 15.22 15.22 13.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[11.22 11.22 13.22 13.22 11.22 ],[0.931" " 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[9.22 9.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([4.55 11.44 9.4" "4 7.44 5.44 2.55 4.55 ],[7.22 7.22 9.22 7.22 9.22 9.22 7.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon" " graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Convert" SID "11312" Ports [1, 1] Position [335, 510, 380, 540] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "24" bin_pt "23" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "45,30,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\npatch([13.1 18.88 22.88 26.88 30.88 22.88 17.1 13.1 ],[19.44 19.44 23.4" "4 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([17.1 22.88 18.88 13.1 17.1 ],[15.44 15.44 19.44 19.44 15.44 ]," "[0.931 0.946 0.973 ]);\npatch([13.1 18.88 22.88 17.1 13.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([17." "1 30.88 26.88 22.88 18.88 13.1 17.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cas" "t');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "11313" Ports [1, 1] Position [335, 550, 380, 580] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "24" bin_pt "23" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "45,30,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\npatch([13.1 18.88 22.88 26.88 30.88 22.88 17.1 13.1 ],[19.44 19.44 23.4" "4 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([17.1 22.88 18.88 13.1 17.1 ],[15.44 15.44 19.44 19.44 15.44 ]," "[0.931 0.946 0.973 ]);\npatch([13.1 18.88 22.88 17.1 13.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([17." "1 30.88 26.88 22.88 18.88 13.1 17.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cas" "t');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Scope Name "FFT In" SID "3320" Ports [10] Position [1095, 91, 1135, 334] ZOrder -3 Floating off Location [6, 40, 1838, 1194] Open off NumInputPorts "10" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" axes9 "%" axes10 "%" } List { ListType ScopeGraphics FigureColor "[0.501960784313725 0.501960784313725 0.501960784313725]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[2 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "30000" YMin "-0.1~0~-0.5~-0.5~0~-1~-1~0~0~-1" YMax "1.1~1~0.5~0.5~1~1~1~1~1~1" SaveName "ScopeData1" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType Scope Name "FFT Out" SID "3321" Ports [10] Position [1580, 641, 1620, 884] ZOrder -3 Floating off Location [6, 40, 1838, 1194] Open off NumInputPorts "10" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" axes9 "%" axes10 "%" } List { ListType ScopeGraphics FigureColor "[0.5 0.5 0.5]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "40000" YMin "0~-1~-1~0~0~0~0~0~-1~-1" YMax "1~1~1~80~1~1~40~1~1~1" SaveName "ScopeData29" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType Reference Name "Fast Fourier Transform 8.0 " SID "3322" Ports [10, 17] Position [485, 374, 680, 796] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Fast Fourier Transform 8.0 " SourceType "Xilinx Fast Fourier Transform 8.0 Block" transform_length "64" target_clock_frequency "160" target_data_throughput "50" implementation_options "radix_4_burst_io" run_time_configurable_transform_length off phase_factor_width "24" scaling_options "scaled" rounding_modes "convergent_rounding" aclken off aresetn on cyclic_prefix_insertion off output_ordering "natural_order" throttle_scheme "nonrealtime" xk_index on ovflo on trim_axipin_name on memory_options_data "block_ram" memory_options_phase_factors "block_ram" number_of_stages_using_block_ram_for_data_and_phase_factors "0" memory_options_reorder "block_ram" memory_options_hybrid off complex_mult_type "use_mults_performance" butterfly_type "use_luts" xl_use_area off xl_area "[0,0,0,0,0,0,0]" channels "1" input_ordering "natural_order" input_width "16" ip_name "Fast Fourier Transform" ip_version "8.0" dsptool_ready "true" ipcore_usecache "true" ipcore_useipmodelcache "true" wrapper_available "true" port_translation_map "{ 'aclken' => 'en', 'aresetn' => 'rst'}" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "xfft_v8_0" sg_icon_stat "195,422,10,17,white,blue,0,d636f25c,right,,[2 2 2 3 3 3 3 4 5 1 ],[2 3 4 4 5 5 5 5 5 5 1 1 1 1 1 1" " 1 ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 0 3 3 ],[405 297 297 405 ],[6.360000e-001 " "6.760000e-001 7.480000e-001 ]);\npatch([0 0 3 3 ],[285 137 137 285 ],[5.020000e-001 5.320000e-001 5.860000e-001 ]);" "\npatch([0 0 3 3 ],[125 97 97 125 ],[3.680000e-001 3.880000e-001 4.240000e-001 ]);\npatch([0 0 3 3 ],[85 57 57 85 ]" ",[2.340000e-001 2.440000e-001 2.620000e-001 ]);\npatch([0 0 3 3 ],[45 17 17 45 ],[7.700000e-001 8.200000e-001 9.100" "000e-001 ]);\npatch([192 192 195 195 ],[420 402 402 420 ],[6.360000e-001 6.760000e-001 7.480000e-001 ]);\npatch([19" "2 192 195 195 ],[395 377 377 395 ],[5.020000e-001 5.320000e-001 5.860000e-001 ]);\npatch([192 192 195 195 ],[370 32" "7 327 370 ],[3.680000e-001 3.880000e-001 4.240000e-001 ]);\npatch([192 192 195 195 ],[320 177 177 320 ],[2.340000e-" "001 2.440000e-001 2.620000e-001 ]);\npatch([192 192 195 195 ],[170 2 2 170 ],[7.700000e-001 8.200000e-001 9.100000e" "-001 ]);\npatch([3 191 191 3 3 ],[0 0 422 422 0 ],[7.700000e-001 8.200000e-001 9.100000e-001 ]);\nplot([3 191 191 3" " 3 ],[0 0 422 422 0 ]);\n\n\npatch([36.925 75.94 102.94 129.94 156.94 102.94 63.925 36.925 ],[240.97 240.97 267.97 " "240.97 267.97 267.97 267.97 240.97 ],[1 1 1 ]);\npatch([63.925 102.94 75.94 36.925 63.925 ],[213.97 213.97 240.97 2" "40.97 213.97 ],[0.931 0.946 0.973 ]);\npatch([36.925 75.94 102.94 63.925 36.925 ],[186.97 186.97 213.97 213.97 186." "97 ],[1 1 1 ]);\npatch([63.925 156.94 129.94 102.94 75.94 36.925 63.925 ],[159.97 159.97 186.97 159.97 186.97 186.9" "7 159.97 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text'" ");\ncolor('black');port_label('input',1,' config_tdata_scale_sch ');\ncolor('black');port_label('input',2,' conf" "ig_tdata_fwd_inv ');\ncolor('black');port_label('input',3,' config_tvalid ');\ncolor('black');port_label('input'" ",4,' data_tdata_xn_im ');\ncolor('black');port_label('input',5,' data_tdata_xn_re ');\ncolor('black');port_labe" "l('input',6,' data_tvalid ');\ncolor('black');port_label('input',7,' data_tlast ');\ncolor('black');port_label(" "'input',8,' status_tready ');\ncolor('black');port_label('input',9,' data_tready ');\ncolor('black');port_label" "('input',10,' aresetn ');\ncolor('black');port_label('output',1,' config_tready ');\ncolor('black');port_label(" "'output',2,' data_tready ');\ncolor('black');port_label('output',3,' status_tvalid ');\ncolor('black');port_lab" "el('output',4,' status_tdata_ovflo ');\ncolor('black');port_label('output',5,' data_tdata_xk_im ');\ncolor('bla" "ck');port_label('output',6,' data_tdata_xk_re ');\ncolor('black');port_label('output',7,' data_tuser_ovflo ');\n" "color('black');port_label('output',8,' data_tuser_xk_index ');\ncolor('black');port_label('output',9,' data_tval" "id ');\ncolor('black');port_label('output',10,' data_tlast ');\ncolor('black');port_label('output',11,' event_f" "rame_started ');\ncolor('black');port_label('output',12,' event_tlast_unexpected ');\ncolor('black');port_label(" "'output',13,' event_tlast_missing ');\ncolor('black');port_label('output',14,' event_fft_overflow ');\ncolor('b" "lack');port_label('output',15,' event_data_in_channel_halt ');\ncolor('black');port_label('output',16,' event_st" "atus_channel_halt ');\ncolor('black');port_label('output',17,' event_data_out_channel_halt ');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType From Name "From1" SID "3323" Position [1155, 421, 1345, 439] ShowName off CloseFcn "tagdialog Close" GotoTag "FFT_data_tready" } Block { BlockType From Name "From10" SID "3324" Position [680, 116, 870, 134] ShowName off CloseFcn "tagdialog Close" GotoTag "FFT_data_tready" } Block { BlockType From Name "From11" SID "3325" Position [675, 191, 865, 209] ShowName off CloseFcn "tagdialog Close" GotoTag "FFT_frame_started" } Block { BlockType From Name "From12" SID "3326" Position [675, 216, 865, 234] ShowName off CloseFcn "tagdialog Close" GotoTag "FFT_tlast_expected" } Block { BlockType From Name "From13" SID "3327" Position [675, 241, 865, 259] ShowName off CloseFcn "tagdialog Close" GotoTag "FFT_tlast_missing" } Block { BlockType From Name "From14" SID "3328" Position [1045, 741, 1235, 759] ShowName off CloseFcn "tagdialog Close" GotoTag "FFT_xk_tlast" } Block { BlockType From Name "From15" SID "3329" Position [1045, 716, 1235, 734] ShowName off CloseFcn "tagdialog Close" GotoTag "FFT_xk_index" } Block { BlockType From Name "From16" SID "3330" Position [1045, 691, 1235, 709] ShowName off CloseFcn "tagdialog Close" GotoTag "FFT_xk_im" } Block { BlockType From Name "From17" SID "3331" Position [1045, 666, 1235, 684] ShowName off CloseFcn "tagdialog Close" GotoTag "FFT_xk_re" } Block { BlockType From Name "From18" SID "3332" Position [1045, 641, 1235, 659] ShowName off CloseFcn "tagdialog Close" GotoTag "FFT_xk_valid" } Block { BlockType From Name "From19" SID "3333" Position [1130, 816, 1320, 834] ShowName off CloseFcn "tagdialog Close" GotoTag "FFT_status_tdata_ovflo" } Block { BlockType From Name "From2" SID "3334" Position [1155, 466, 1345, 484] ShowName off CloseFcn "tagdialog Close" GotoTag "FFT_xk_im" } Block { BlockType From Name "From20" SID "3335" Position [1130, 841, 1320, 859] ShowName off CloseFcn "tagdialog Close" GotoTag "FFT_event_overflow" } Block { BlockType From Name "From3" SID "3336" Position [305, 395, 445, 415] ShowName off CloseFcn "tagdialog Close" GotoTag "regRx_FFT_SCALING" TagVisibility "global" } Block { BlockType From Name "From4" SID "3337" Position [1155, 481, 1345, 499] ShowName off CloseFcn "tagdialog Close" GotoTag "FFT_xk_re" } Block { BlockType From Name "From5" SID "3338" Position [1155, 531, 1345, 549] ShowName off CloseFcn "tagdialog Close" GotoTag "FFT_xk_index" } Block { BlockType From Name "From6" SID "3339" Position [1155, 546, 1345, 564] ShowName off CloseFcn "tagdialog Close" GotoTag "FFT_xk_valid" } Block { BlockType From Name "From7" SID "3340" Position [645, 971, 835, 989] ShowName off CloseFcn "tagdialog Close" GotoTag "FFT_xk_tlast" } Block { BlockType From Name "From8" SID "3341" Position [785, 1096, 975, 1114] ShowName off CloseFcn "tagdialog Close" GotoTag "FFT_xk_index" } Block { BlockType From Name "From9" SID "3342" Position [785, 1071, 975, 1089] ShowName off CloseFcn "tagdialog Close" GotoTag "FFT_xk_valid" } Block { BlockType Reference Name "Gateway Out" SID "3343" Ports [1, 1] Position [930, 94, 965, 106] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.88" " ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.11 " "8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 ],[" "0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([15." "775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" Port { PortNumber 1 Name "data in tvalid" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out1" SID "3344" Ports [1, 1] Position [930, 119, 965, 131] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.88" " ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.11 " "8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 ],[" "0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([15." "775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" Port { PortNumber 1 Name "data in tready" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out10" SID "3345" Ports [1, 1] Position [1415, 794, 1450, 806] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.88" " ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.11 " "8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 ],[" "0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([15." "775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" Port { PortNumber 1 Name "OFDM Sym Ind" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out11" SID "3346" Ports [1, 1] Position [1415, 644, 1450, 656] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.88" " ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.11 " "8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 ],[" "0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([15." "775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" Port { PortNumber 1 Name "data out tvalid" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out12" SID "3347" Ports [1, 1] Position [1415, 669, 1450, 681] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.88" " ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.11 " "8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 ],[" "0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([15." "775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" Port { PortNumber 1 Name "out re" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out13" SID "3348" Ports [1, 1] Position [1415, 769, 1450, 781] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.88" " ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.11 " "8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 ],[" "0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([15." "775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" Port { PortNumber 1 Name "reset" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out14" SID "3349" Ports [1, 1] Position [1415, 694, 1450, 706] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.88" " ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.11 " "8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 ],[" "0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([15." "775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" Port { PortNumber 1 Name "out im" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out15" SID "3350" Ports [1, 1] Position [1415, 719, 1450, 731] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.88" " ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.11 " "8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 ],[" "0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([15." "775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" Port { PortNumber 1 Name "xk_ind" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out16" SID "3351" Ports [1, 1] Position [1415, 744, 1450, 756] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.88" " ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.11 " "8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 ],[" "0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([15." "775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" Port { PortNumber 1 Name "out tlast" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out17" SID "3352" Ports [1, 1] Position [930, 294, 965, 306] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.88" " ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.11 " "8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 ],[" "0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([15." "775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" Port { PortNumber 1 Name "fft aresetn" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "3353" Ports [1, 1] Position [930, 144, 965, 156] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.88" " ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.11 " "8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 ],[" "0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([15." "775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" Port { PortNumber 1 Name "data_in_re" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "3354" Ports [1, 1] Position [930, 169, 965, 181] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.88" " ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.11 " "8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 ],[" "0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([15." "775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" Port { PortNumber 1 Name "data_in_im" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "3355" Ports [1, 1] Position [930, 194, 965, 206] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.88" " ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.11 " "8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 ],[" "0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([15." "775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" Port { PortNumber 1 Name "frame started" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "3356" Ports [1, 1] Position [930, 219, 965, 231] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.88" " ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.11 " "8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 ],[" "0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([15." "775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" Port { PortNumber 1 Name "tlast_unexpected" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "3357" Ports [1, 1] Position [930, 244, 965, 256] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.88" " ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.11 " "8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 ],[" "0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([15." "775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" Port { PortNumber 1 Name "tlast_missing" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "3358" Ports [1, 1] Position [930, 269, 965, 281] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.88" " ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.11 " "8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 ],[" "0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([15." "775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" Port { PortNumber 1 Name "data in tlast" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "3359" Ports [1, 1] Position [1415, 844, 1450, 856] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.88" " ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.11 " "8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 ],[" "0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([15." "775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" Port { PortNumber 1 Name "Event Overflow" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out9" SID "3360" Ports [1, 1] Position [1415, 819, 1450, 831] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.88" " ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.11 " "8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 ],[" "0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([15." "775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" Port { PortNumber 1 Name "tdata Overflow" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Goto Name "Goto1" SID "3361" Position [1080, 1021, 1245, 1039] ShowName off GotoTag "CS_OFDM_SYM_IND" TagVisibility "global" } Block { BlockType Goto Name "Goto10" SID "3362" Position [760, 526, 955, 544] ShowName off GotoTag "FFT_tuser_ovflo" TagVisibility "local" } Block { BlockType Goto Name "Goto11" SID "3363" Position [760, 551, 955, 569] ShowName off GotoTag "FFT_xk_index" TagVisibility "local" } Block { BlockType Goto Name "Goto12" SID "3364" Position [760, 576, 955, 594] ShowName off GotoTag "FFT_xk_valid" TagVisibility "local" } Block { BlockType Goto Name "Goto13" SID "3365" Position [760, 601, 955, 619] ShowName off GotoTag "FFT_xk_tlast" TagVisibility "local" } Block { BlockType Goto Name "Goto14" SID "3366" Position [760, 626, 955, 644] ShowName off GotoTag "FFT_frame_started" TagVisibility "local" } Block { BlockType Goto Name "Goto15" SID "3367" Position [760, 651, 955, 669] ShowName off GotoTag "FFT_tlast_expected" TagVisibility "local" } Block { BlockType Goto Name "Goto16" SID "3368" Position [760, 676, 955, 694] ShowName off GotoTag "FFT_tlast_missing" TagVisibility "local" } Block { BlockType Goto Name "Goto17" SID "3369" Position [760, 701, 955, 719] ShowName off GotoTag "FFT_event_overflow" TagVisibility "local" } Block { BlockType Goto Name "Goto2" SID "3370" Position [1080, 1071, 1240, 1089] ShowName off GotoTag "CS_FFT_VALID_OUT" TagVisibility "global" } Block { BlockType Goto Name "Goto3" SID "3371" Position [1080, 1096, 1240, 1114] ShowName off GotoTag "CS_FFT_XKIND_OUT" TagVisibility "global" } Block { BlockType Goto Name "Goto4" SID "3372" Position [1080, 1046, 1240, 1064] ShowName off GotoTag "CS_FFT_VALID_IN" TagVisibility "global" } Block { BlockType Goto Name "Goto5" SID "3373" Position [760, 376, 955, 394] ShowName off GotoTag "FFT_config_tready" TagVisibility "local" } Block { BlockType Goto Name "Goto6" SID "3374" Position [760, 401, 955, 419] ShowName off GotoTag "FFT_data_tready" TagVisibility "local" } Block { BlockType Goto Name "Goto7" SID "3375" Position [760, 451, 955, 469] ShowName off GotoTag "FFT_status_tdata_ovflo" TagVisibility "local" } Block { BlockType Goto Name "Goto8" SID "3376" Position [760, 476, 955, 494] ShowName off GotoTag "FFT_xk_im" TagVisibility "local" } Block { BlockType Goto Name "Goto9" SID "3377" Position [760, 501, 955, 519] ShowName off GotoTag "FFT_xk_re" TagVisibility "local" } Block { BlockType SubSystem Name "Reset\nGen" SID "3378" Ports [2, 2] Position [325, 903, 440, 947] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Reset\nGen" Location [214, 564, 734, 915] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "FFT Valid In" SID "3379" Position [380, 588, 410, 602] IconDisplay "Port number" } Block { BlockType Inport Name "Reset" SID "3380" Position [380, 628, 410, 642] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Inverter" SID "3381" Ports [1, 1] Position [915, 463, 945, 477] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "30,14,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 14 14 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 14 14 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[9" ".22 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[7.22 7.22 9.22" " 9.22 7.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 " "]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');d" "isp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter1" SID "3382" Ports [1, 1] Position [565, 652, 595, 688] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "4" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "30,36,1,1,white,blue,0,183dcab3,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 36 36 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 36 36 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[22.44 " "22.44 26.44 22.44 26.44 26.44 26.44 22.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[18.44 18.44 22.44 2" "2.44 18.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[14.44 14.44 18.44 18.44 14.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[10.44 10.44 14.44 10.44 14.44 14.44 10.44 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black'" ");disp('z^{-4}\\newline ','texmode','on');\ncolor('black');disp(' \\nnot');\nfprintf('','COMMENT: end icon text" "');" } Block { BlockType Reference Name "Logical" SID "3383" Ports [2, 1] Position [565, 612, 595, 643] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "30,31,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 31 31 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 31 31 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 " "19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 1" "9.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');" "disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "3384" Ports [2, 1] Position [775, 527, 805, 558] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "30,31,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 31 31 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 31 31 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 " "19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 1" "9.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');" "disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "3385" Ports [1, 1] Position [1000, 454, 1025, 486] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "1" rst off en off dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,32,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 32 32 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 32 32 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[19" ".33 19.33 22.33 19.33 22.33 22.33 22.33 19.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[16.33 16.33 " "19.33 19.33 16.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[10.33 10.33 13.33 10.33 13.33 13.33 10.33 ]," "[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncol" "or('black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}" "','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "S-R Latch1" SID "3386" Ports [2, 1] Position [635, 610, 675, 690] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "S-R Latch1" Location [351, 366, 2001, 1172] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "3387" Position [140, 103, 170, 117] IconDisplay "Port number" } Block { BlockType Inport Name "R" SID "3388" Position [140, 88, 170, 102] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "3389" Ports [0, 1] Position [195, 71, 210, 89] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "15,18,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11.22 13.22 " "11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 9.22 ],[0.931" " 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([4.55 11.44 9.44" " 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon" " graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "3390" Ports [1, 1] Position [210, 86, 235, 104] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cast');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "3391" Ports [1, 1] Position [210, 101, 235, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cast');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "3392" Ports [3, 1] Position [255, 71, 300, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 30.66 3" "6.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 30.66 24" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('" "input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'en');\ncolor('bl" "ack');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon te" "xt');" } Block { BlockType Outport Name "Q" SID "3393" Position [325, 88, 355, 102] IconDisplay "Port number" } Line { SrcBlock "S" SrcPort 1 DstBlock "Convert2" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "Convert2" SrcPort 1 DstBlock "Register2" DstPort 3 } } } Block { BlockType Outport Name "FFT Reset" SID "3394" Position [1065, 463, 1095, 477] IconDisplay "Port number" } Block { BlockType Outport Name " Reset" SID "3395" Position [1065, 538, 1095, 552] Port "2" IconDisplay "Port number" } Line { SrcBlock "Inverter1" SrcPort 1 DstBlock "S-R Latch1" DstPort 2 } Line { SrcBlock "Reset" SrcPort 1 Points [80, 0] Branch { Points [0, -100] DstBlock "Logical1" DstPort 1 } Branch { DstBlock "Logical" DstPort 2 } } Line { SrcBlock "Logical" SrcPort 1 DstBlock "S-R Latch1" DstPort 1 } Line { SrcBlock "S-R Latch1" SrcPort 1 Points [25, 0; 0, -100] DstBlock "Logical1" DstPort 2 } Line { SrcBlock "Logical1" SrcPort 1 Points [45, 0] Branch { DstBlock " Reset" DstPort 1 } Branch { Points [0, -75] DstBlock "Inverter" DstPort 1 } } Line { SrcBlock "FFT Valid In" SrcPort 1 Points [115, 0; 0, 25] Branch { Points [0, 50] DstBlock "Inverter1" DstPort 1 } Branch { Points [0, 0] DstBlock "Logical" DstPort 1 } } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "FFT Reset" DstPort 1 } Annotation { Name "Extend FFT reset for duration of TVALID + 4 to handle\ncase of pkt ending while new FFT frame is b" "eing loaded.\nTurns out reset inputs for FIFO and FFT do not actually\nflush internal state - both cores keep r" "espnding to inputs\nwhile reset is asserted (very frustrating...)" Position [542, 840] } } } Block { BlockType SubSystem Name "Sym Count" SID "3396" Ports [3, 1] Position [870, 870, 955, 1000] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Sym Count" Location [88, 301, 2101, 1216] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "data_in_tvalid" SID "3397" Position [135, 433, 165, 447] IconDisplay "Port number" } Block { BlockType Inport Name "pkt_done" SID "3398" Position [135, 313, 165, 327] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "data_out_tlast" SID "3399" Position [135, 343, 165, 357] Port "3" IconDisplay "Port number" } Block { BlockType Reference Name "Logical" SID "3400" Ports [2, 1] Position [320, 427, 350, 458] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "30,31,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 31 31 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 31 31 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 " "19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 1" "9.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');" "disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "S-R Latch1" SID "3401" Ports [2, 1] Position [230, 433, 265, 462] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "S-R Latch1" Location [351, 366, 2001, 1172] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "3402" Position [140, 103, 170, 117] IconDisplay "Port number" } Block { BlockType Inport Name "R" SID "3403" Position [140, 88, 170, 102] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "3404" Ports [0, 1] Position [195, 71, 210, 89] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "15,18,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11.22 13.22 " "11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 9.22 ],[0.931" " 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([4.55 11.44 9.44" " 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon" " graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "3405" Ports [1, 1] Position [210, 86, 235, 104] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cast');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "3406" Ports [1, 1] Position [210, 101, 235, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cast');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "3407" Ports [3, 1] Position [255, 71, 300, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 30.66 3" "6.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 30.66 24" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('" "input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'en');\ncolor('bl" "ack');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon te" "xt');" } Block { BlockType Outport Name "Q" SID "3408" Position [325, 88, 355, 102] IconDisplay "Port number" } Line { SrcBlock "S" SrcPort 1 DstBlock "Convert2" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "Convert2" SrcPort 1 DstBlock "Register2" DstPort 3 } } } Block { BlockType Reference Name "Symbol\nCounter" SID "3409" Ports [2, 1] Position [430, 305, 490, 365] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited co" "unter is implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "Inf" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "ceil(log2(MAX_NUM_SYMS))" bin_pt "0" load_pin off rst on en on explicit_period "off" period "1" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "counter" sg_icon_stat "60,60,2,1,white,blue,0,ae3608d6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 60 60 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[38.8" "8 38.88 46.88 38.88 46.88 46.88 46.88 38.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[30.88 30.88 38.8" "8 38.88 30.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[22.88 22.88 30.88 30.88 22.88 ],[1" " 1 1 ]);\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[14.88 14.88 22.88 14.88 22.88 22.88 14.88 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('blac" "k');port_label('input',1,'rst');\ncolor('black');port_label('input',2,'en');\n\ncolor('black');disp('{\\fontsiz" "e{14}\\bf++}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Sym Ind" SID "3410" Position [575, 328, 605, 342] IconDisplay "Port number" } Line { SrcBlock "data_out_tlast" SrcPort 1 Points [120, 0; 0, 85] DstBlock "Logical" DstPort 1 } Line { SrcBlock "Logical" SrcPort 1 Points [60, 0] DstBlock "Symbol\nCounter" DstPort 2 } Line { SrcBlock "S-R Latch1" SrcPort 1 Points [15, 0] } Line { SrcBlock "data_in_tvalid" SrcPort 1 Points [20, 0] Branch { DstBlock "S-R Latch1" DstPort 1 } Branch { Points [0, 40; 115, 0] DstBlock "Logical" DstPort 2 } } Line { SrcBlock "Symbol\nCounter" SrcPort 1 DstBlock "Sym Ind" DstPort 1 } Line { SrcBlock "pkt_done" SrcPort 1 Points [30, 0] Branch { Points [0, 135] DstBlock "S-R Latch1" DstPort 2 } Branch { DstBlock "Symbol\nCounter" DstPort 1 } } Annotation { Name "\"Symbol index\" counts OFDM symbols and increments with each FFT.\nContent of each OFDM sybmol de" "pends on PHY mode (ag, n, or ac)" Position [186, 509] HorizontalAlignment "left" } } } Block { BlockType Outport Name "data_in_tready" SID "3411" Position [1425, 423, 1455, 437] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Outport Name "data_out_xk_re" SID "3412" Position [1425, 483, 1455, 497] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "data_out_xk_im" SID "3413" Position [1425, 468, 1455, 482] NamePlacement "alternate" Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "data_out_tvalid" SID "3415" Position [1425, 548, 1455, 562] Port "4" IconDisplay "Port number" } Block { BlockType Outport Name "data_out_xk_index" SID "3414" Position [1425, 533, 1455, 547] NamePlacement "alternate" Port "5" IconDisplay "Port number" } Block { BlockType Outport Name "sym_ind" SID "3416" Position [1145, 928, 1175, 942] Port "6" IconDisplay "Port number" } Line { Name "reset" Labels [0, 0] SrcBlock "Gateway Out13" SrcPort 1 DstBlock "FFT Out" DstPort 6 } Line { Name "out tlast" Labels [0, 0] SrcBlock "Gateway Out16" SrcPort 1 DstBlock "FFT Out" DstPort 5 } Line { Name "xk_ind" Labels [0, 0] SrcBlock "Gateway Out15" SrcPort 1 DstBlock "FFT Out" DstPort 4 } Line { Name "out im" Labels [0, 0] SrcBlock "Gateway Out14" SrcPort 1 DstBlock "FFT Out" DstPort 3 } Line { Name "out re" Labels [0, 0] SrcBlock "Gateway Out12" SrcPort 1 DstBlock "FFT Out" DstPort 2 } Line { Name "data out tvalid" Labels [0, 0] SrcBlock "Gateway Out11" SrcPort 1 DstBlock "FFT Out" DstPort 1 } Line { SrcBlock "From5" SrcPort 1 DstBlock "data_out_xk_index" DstPort 1 } Line { SrcBlock "From4" SrcPort 1 DstBlock "data_out_xk_re" DstPort 1 } Line { SrcBlock "From7" SrcPort 1 DstBlock "Sym Count" DstPort 3 } Line { SrcBlock "From6" SrcPort 1 DstBlock "data_out_tvalid" DstPort 1 } Line { SrcBlock "From2" SrcPort 1 DstBlock "data_out_xk_im" DstPort 1 } Line { SrcBlock "From1" SrcPort 1 DstBlock "data_in_tready" DstPort 1 } Line { Name "data in tlast" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 DstBlock "FFT In" DstPort 8 } Line { Name "tlast_missing" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 DstBlock "FFT In" DstPort 7 } Line { Name "tlast_unexpected" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 DstBlock "FFT In" DstPort 6 } Line { Name "frame started" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 DstBlock "FFT In" DstPort 5 } Line { Name "data_in_im" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 DstBlock "FFT In" DstPort 4 } Line { Name "data_in_re" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 DstBlock "FFT In" DstPort 3 } Line { Name "data in tready" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 DstBlock "FFT In" DstPort 2 } Line { Name "data in tvalid" Labels [0, 0] SrcBlock "Gateway Out" SrcPort 1 DstBlock "FFT In" DstPort 1 } Line { SrcBlock "Fast Fourier Transform 8.0 " SrcPort 1 DstBlock "Goto5" DstPort 1 } Line { SrcBlock "Fast Fourier Transform 8.0 " SrcPort 2 DstBlock "Goto6" DstPort 1 } Line { SrcBlock "Fast Fourier Transform 8.0 " SrcPort 4 DstBlock "Goto7" DstPort 1 } Line { SrcBlock "Fast Fourier Transform 8.0 " SrcPort 5 DstBlock "Goto8" DstPort 1 } Line { SrcBlock "Fast Fourier Transform 8.0 " SrcPort 6 DstBlock "Goto9" DstPort 1 } Line { SrcBlock "Fast Fourier Transform 8.0 " SrcPort 7 DstBlock "Goto10" DstPort 1 } Line { SrcBlock "Fast Fourier Transform 8.0 " SrcPort 8 DstBlock "Goto11" DstPort 1 } Line { SrcBlock "Fast Fourier Transform 8.0 " SrcPort 9 Points [40, 0] Branch { DstBlock "Goto12" DstPort 1 } Branch { Points [0, 305] DstBlock "Sym Count" DstPort 1 } } Line { SrcBlock "Fast Fourier Transform 8.0 " SrcPort 10 DstBlock "Goto13" DstPort 1 } Line { SrcBlock "Fast Fourier Transform 8.0 " SrcPort 11 DstBlock "Goto14" DstPort 1 } Line { SrcBlock "Fast Fourier Transform 8.0 " SrcPort 12 DstBlock "Goto15" DstPort 1 } Line { SrcBlock "Fast Fourier Transform 8.0 " SrcPort 13 DstBlock "Goto16" DstPort 1 } Line { SrcBlock "Fast Fourier Transform 8.0 " SrcPort 14 DstBlock "Goto17" DstPort 1 } Line { SrcBlock "Constant3" SrcPort 1 Points [20, 0] Branch { DstBlock "Fast Fourier Transform 8.0 " DstPort 8 } Branch { Points [0, 40] DstBlock "Fast Fourier Transform 8.0 " DstPort 9 } } Line { SrcBlock "Constant4" SrcPort 1 DstBlock "Fast Fourier Transform 8.0 " DstPort 3 } Line { SrcBlock "Constant5" SrcPort 1 DstBlock "Fast Fourier Transform 8.0 " DstPort 2 } Line { SrcBlock "From3" SrcPort 1 DstBlock "Fast Fourier Transform 8.0 " DstPort 1 } Line { SrcBlock "From8" SrcPort 1 DstBlock "Goto3" DstPort 1 } Line { SrcBlock "From9" SrcPort 1 DstBlock "Goto2" DstPort 1 } Line { SrcBlock "Reset\nGen" SrcPort 2 Points [385, 0] Branch { DstBlock "Sym Count" DstPort 2 } Branch { Points [0, -160] DstBlock "Gateway Out13" DstPort 1 } } Line { SrcBlock "Reset" SrcPort 1 DstBlock "Reset\nGen" DstPort 2 } Line { SrcBlock "data_in_tvalid" SrcPort 1 Points [35, 0] Branch { Points [0, 0] Branch { DstBlock "Fast Fourier Transform 8.0 " DstPort 6 } Branch { Points [0, 285] Branch { Points [0, 25] DstBlock "Reset\nGen" DstPort 1 } Branch { Points [305, 0] Branch { Points [0, 165] DstBlock "Goto4" DstPort 1 } Branch { Points [50, 0] } } } } Branch { Points [0, -505] DstBlock "Gateway Out" DstPort 1 } } Line { SrcBlock "Sym Count" SrcPort 1 Points [70, 0] Branch { DstBlock "sym_ind" DstPort 1 } Branch { Points [0, -135] DstBlock "Gateway Out10" DstPort 1 } Branch { Points [0, 95] DstBlock "Goto1" DstPort 1 } } Line { SrcBlock "data_in_tlast" SrcPort 1 Points [50, 0] Branch { DstBlock "Fast Fourier Transform 8.0 " DstPort 7 } Branch { Points [0, -370] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "data_in_xn_im" SrcPort 1 Points [15, 0] Branch { Points [0, -350] DstBlock "Gateway Out3" DstPort 1 } Branch { DstBlock "Convert" DstPort 1 } } Line { SrcBlock "data_in_xn_re" SrcPort 1 Points [10, 0] Branch { Points [0, -415] DstBlock "Gateway Out2" DstPort 1 } Branch { DstBlock "Convert1" DstPort 1 } } Line { Name "OFDM Sym Ind" Labels [0, 0] SrcBlock "Gateway Out10" SrcPort 1 DstBlock "FFT Out" DstPort 7 } Line { Name "tdata Overflow" Labels [0, 0] SrcBlock "Gateway Out9" SrcPort 1 DstBlock "FFT Out" DstPort 8 } Line { SrcBlock "From10" SrcPort 1 DstBlock "Gateway Out1" DstPort 1 } Line { SrcBlock "From11" SrcPort 1 DstBlock "Gateway Out4" DstPort 1 } Line { SrcBlock "From12" SrcPort 1 DstBlock "Gateway Out5" DstPort 1 } Line { SrcBlock "From13" SrcPort 1 DstBlock "Gateway Out6" DstPort 1 } Line { SrcBlock "From14" SrcPort 1 DstBlock "Gateway Out16" DstPort 1 } Line { SrcBlock "From15" SrcPort 1 DstBlock "Gateway Out15" DstPort 1 } Line { SrcBlock "From16" SrcPort 1 DstBlock "Gateway Out14" DstPort 1 } Line { SrcBlock "From17" SrcPort 1 DstBlock "Gateway Out12" DstPort 1 } Line { SrcBlock "From18" SrcPort 1 DstBlock "Gateway Out11" DstPort 1 } Line { SrcBlock "From19" SrcPort 1 DstBlock "Gateway Out9" DstPort 1 } Line { SrcBlock "From20" SrcPort 1 DstBlock "Gateway Out8" DstPort 1 } Line { Name "Event Overflow" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 DstBlock "FFT Out" DstPort 9 } Line { SrcBlock "Reset\nGen" SrcPort 1 Points [20, 0; 0, -150] Branch { DstBlock "Fast Fourier Transform 8.0 " DstPort 10 } Branch { Points [0, -465] DstBlock "Gateway Out17" DstPort 1 } } Line { Name "fft aresetn" Labels [0, 0] SrcBlock "Gateway Out17" SrcPort 1 DstBlock "FFT In" DstPort 9 } Line { SrcBlock "Convert" SrcPort 1 DstBlock "Fast Fourier Transform 8.0 " DstPort 4 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Fast Fourier Transform 8.0 " DstPort 5 } Annotation { Name "Lots of From/Goto here to avoid routing\nmess with all the FFT signals. I usually hate\nFrom/Goto intra-s" "ubsystem, but it's the best\nalternative to a routing spagetti with all of the \nFFT data and status outputs, espec" "ially given\nthat Xilinx is likely to change ports & port orders\nin future releases of the FFT core." Position [362, 1085] FontName "Arial" FontSize 14 } } } Block { BlockType SubSystem Name "Inputs" SID "3417" Ports [0, 4] Position [60, 153, 135, 197] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Inputs" Location [73, 74, 1749, 1018] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "110" Block { BlockType Reference Name "AGC_DONE" SID "3418" Ports [1, 1] Position [240, 543, 280, 557] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to Xilinx" " fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top level input p" "orts." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "5" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "40,14,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.95 0.93 0.65" " ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9.22 9.22 11." "22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0." "985 0.979 0.895 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([17.55 24" ".44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.985 0.979 0.895 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'\\fontsize{" "11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType BusCreator Name "Bus\nCreator" SID "3419" Ports [4, 1] Position [1415, 214, 1420, 296] ZOrder -2 ShowName off DisplayOption "bar" } Block { BlockType BusCreator Name "Bus\nCreator1" SID "3420" Ports [4, 1] Position [1415, 319, 1420, 401] ZOrder -2 ShowName off DisplayOption "bar" } Block { BlockType BusCreator Name "Bus\nCreator2" SID "3421" Ports [4, 1] Position [1415, 424, 1420, 506] ZOrder -2 ShowName off DisplayOption "bar" } Block { BlockType BusCreator Name "Bus\nCreator3" SID "3422" Ports [4, 1] Position [1415, 109, 1420, 191] ZOrder -2 ShowName off DisplayOption "bar" } Block { BlockType Constant Name "Constant" SID "3423" Position [225, 75, 255, 105] ZOrder -5 Value "0" } Block { BlockType Constant Name "Constant1" SID "3424" Position [180, 535, 210, 565] ZOrder -5 } Block { BlockType Reference Name "Convert2" SID "3425" Ports [1, 1] Position [405, 196, 430, 214] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13.2" "2 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ],[0." "931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16.44 " "14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: en" "d icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cast');\nfprin" "tf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay3" SID "3426" Ports [1, 1] Position [350, 535, 380, 565] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "30,30,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 30 30 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 19.44 23.44 " "19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 19.44 15.44 ],[0." "931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([10.1 23." "88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-1}','texmode','on');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From1" SID "3427" Position [255, 50, 450, 70] ShowName off CloseFcn "tagdialog Close" GotoTag "REG_USE_RX_SIGS_INVALID_INPUT" TagVisibility "global" } Block { BlockType From Name "From10" SID "3428" Position [1225, 362, 1320, 378] ShowName off CloseFcn "tagdialog Close" GotoTag "RFC_ADC_Q" Port { PortNumber 1 Name "RFC_Q" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType From Name "From11" SID "3429" Position [1225, 382, 1320, 398] ShowName off CloseFcn "tagdialog Close" GotoTag "RFD_ADC_Q" Port { PortNumber 1 Name "RFD_Q" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType From Name "From12" SID "3430" Position [1225, 467, 1320, 483] ShowName off CloseFcn "tagdialog Close" GotoTag "RFC_RSSI" Port { PortNumber 1 Name "RFC_RSSI" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType From Name "From13" SID "3431" Position [1225, 487, 1320, 503] ShowName off CloseFcn "tagdialog Close" GotoTag "RFD_RSSI" Port { PortNumber 1 Name "RFD_RSSI" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType From Name "From2" SID "3432" Position [1225, 217, 1320, 233] ShowName off CloseFcn "tagdialog Close" GotoTag "RFA_ADC_I" Port { PortNumber 1 Name "RFA_I" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType From Name "From3" SID "3433" Position [1225, 322, 1320, 338] ShowName off CloseFcn "tagdialog Close" GotoTag "RFA_ADC_Q" Port { PortNumber 1 Name "RFA_Q" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType From Name "From4" SID "3434" Position [1225, 237, 1320, 253] ShowName off CloseFcn "tagdialog Close" GotoTag "RFB_ADC_I" Port { PortNumber 1 Name "RFB_I" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType From Name "From5" SID "3435" Position [1225, 342, 1320, 358] ShowName off CloseFcn "tagdialog Close" GotoTag "RFB_ADC_Q" Port { PortNumber 1 Name "RFB_Q" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType From Name "From6" SID "3436" Position [1225, 427, 1320, 443] ShowName off CloseFcn "tagdialog Close" GotoTag "RFA_RSSI" Port { PortNumber 1 Name "RFA_RSSI" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType From Name "From7" SID "3437" Position [1225, 447, 1320, 463] ShowName off CloseFcn "tagdialog Close" GotoTag "RFB_RSSI" Port { PortNumber 1 Name "RFB_RSSI" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType From Name "From8" SID "3438" Position [1225, 277, 1320, 293] ShowName off CloseFcn "tagdialog Close" GotoTag "RFD_ADC_I" Port { PortNumber 1 Name "RFD_I" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType From Name "From9" SID "3439" Position [1225, 257, 1320, 273] ShowName off CloseFcn "tagdialog Close" GotoTag "RFC_ADC_I" Port { PortNumber 1 Name "RFC_I" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Goto Name "Goto1" SID "3440" Position [870, 166, 965, 184] ZOrder -10 ShowName off GotoTag "RFA_ADC_I" TagVisibility "local" } Block { BlockType Goto Name "Goto10" SID "3441" Position [870, 196, 965, 214] ZOrder -10 ShowName off GotoTag "RFA_RSSI" TagVisibility "local" } Block { BlockType Goto Name "Goto11" SID "3442" Position [870, 251, 965, 269] ZOrder -10 ShowName off GotoTag "RFB_ADC_I" TagVisibility "local" } Block { BlockType Goto Name "Goto12" SID "3443" Position [870, 451, 965, 469] ZOrder -10 ShowName off GotoTag "RFD_ADC_Q" TagVisibility "local" } Block { BlockType Goto Name "Goto13" SID "3444" Position [870, 366, 965, 384] ZOrder -10 ShowName off GotoTag "RFC_ADC_Q" TagVisibility "local" } Block { BlockType Goto Name "Goto14" SID "3445" Position [870, 281, 965, 299] ZOrder -10 ShowName off GotoTag "RFB_RSSI" TagVisibility "local" } Block { BlockType Goto Name "Goto15" SID "3446" Position [870, 266, 965, 284] ZOrder -10 ShowName off GotoTag "RFB_ADC_Q" TagVisibility "local" } Block { BlockType Goto Name "Goto16" SID "11745" Position [335, 280, 430, 300] ZOrder -10 ShowName off GotoTag "SAMP_CE_Input" TagVisibility "global" } Block { BlockType Goto Name "Goto2" SID "3447" Position [490, 145, 585, 165] ZOrder -10 ShowName off GotoTag "CS_ADC_IQ_Valid" TagVisibility "global" } Block { BlockType Goto Name "Goto3" SID "3448" Position [870, 351, 965, 369] ZOrder -10 ShowName off GotoTag "RFC_ADC_I" TagVisibility "local" } Block { BlockType Goto Name "Goto4" SID "3449" Position [870, 381, 965, 399] ZOrder -10 ShowName off GotoTag "RFC_RSSI" TagVisibility "local" } Block { BlockType Goto Name "Goto5" SID "3450" Position [870, 181, 965, 199] ZOrder -10 ShowName off GotoTag "RFA_ADC_Q" TagVisibility "local" } Block { BlockType Goto Name "Goto6" SID "3451" Position [685, 66, 880, 84] ZOrder -10 ShowName off GotoTag "CS_RX_SIGS_INVALID" TagVisibility "global" } Block { BlockType Goto Name "Goto7" SID "3452" Position [870, 436, 965, 454] ZOrder -10 ShowName off GotoTag "RFD_ADC_I" TagVisibility "local" } Block { BlockType Goto Name "Goto8" SID "3453" Position [870, 466, 965, 484] ZOrder -10 ShowName off GotoTag "RFD_RSSI" TagVisibility "local" } Block { BlockType Goto Name "Goto9" SID "3454" Position [535, 540, 630, 560] ZOrder -10 ShowName off GotoTag "AGC_DONE" TagVisibility "global" } Block { BlockType Reference Name "Logical" SID "3455" Ports [2, 1] Position [520, 44, 555, 106] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,62,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 62 62 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 62 62 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[36.55 36.55 41.55" " 36.55 41.55 41.55 41.55 36.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[31.55 31.55 36.55 36.55 31.55 " "],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[26.55 26.55 31.55 31.55 26.55 ],[1 1 1 ]);\npatch(" "[10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[21.55 21.55 26.55 21.55 26.55 26.55 21.55 ],[0.931 0.946 0.973 ]);\nfpr" "intf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('and');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType DiscretePulseGenerator Name "Pulse\nGenerator3" SID "3456" Ports [0, 1] Position [70, 189, 100, 221] ZOrder -13 ShowName off Period "160 / rx_sim.samp_rate" PhaseDelay "5" } Block { BlockType SubSystem Name "RF A Inputs" SID "3457" Ports [2, 3] Position [695, 166, 800, 214] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "RF A Inputs" Location [2, 70, 2469, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Rst" SID "3458" Position [795, 418, 825, 432] IconDisplay "Port number" } Block { BlockType Inport Name "IQ Valid" SID "3459" Position [795, 478, 825, 492] Port "2" IconDisplay "Port number" } Block { BlockType Abs Name "Abs" SID "18128" Position [1335, 310, 1365, 340] ZOrder -1 SaturateOnIntegerOverflow off } Block { BlockType ComplexToRealImag Name "Complex to\nReal-Imag" SID "8505" Ports [1, 2] Position [445, 390, 480, 490] ZOrder -7 ShowName off Output "Real and imag" } Block { BlockType Constant Name "Constant1" SID "3460" Position [555, 515, 585, 545] ZOrder -5 ShowName off Value "0" } Block { BlockType Constant Name "Constant2" SID "3461" Position [555, 715, 585, 745] ZOrder -5 ShowName off Value "2" } Block { BlockType Constant Name "Constant4" SID "3462" Position [555, 770, 585, 800] ZOrder -5 ShowName off Value "5" } Block { BlockType Reference Name "Delay1" SID "3463" Ports [1, 1] Position [835, 715, 865, 745] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "30,30,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 30 30 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 30 30 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 " "19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 1" "9.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');di" "sp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay2" SID "3464" Ports [1, 1] Position [835, 770, 865, 800] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "30,30,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 30 30 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 30 30 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 " "19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 1" "9.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');di" "sp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Down Sample" SID "3465" Ports [1, 1] Position [1050, 525, 1075, 555] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Down Sample" SourceType "Xilinx Down Sampler Block" infoedit "Hardware notes: Sample and Latency controls determine the hardware implementation. The cost i" "n hardware of different implementations varies considerably; press Help for details." sample_ratio "16" sample_phase "Last Value of Frame (most efficient)" en off latency "1" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "dsamp" sg_icon_stat "25,30,1,1,white,blue,0,40e65a2b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 30 30 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 30 30 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[18" ".33 18.33 21.33 18.33 21.33 21.33 21.33 18.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[15.33 15.33 " "18.33 18.33 15.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[12.33 12.33 15.33 15.33 12.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[9.33 9.33 12.33 9.33 12.33 12.33 9.33 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncol" "or('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\newline{\\fontsize{14pt}\\bf\\dow" "narrow}16','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType FromWorkspace Name "From\nWorkspace" SID "3466" Position [250, 426, 400, 454] ZOrder -10 ShowName off VariableName "rx_sim.waveform_RFA" SampleTime "160 / rx_sim.samp_rate" Interpolate off ZeroCross on OutputAfterFinalValue "Setting to zero" } Block { BlockType Reference Name "Gateway Out" SID "18123" Ports [1, 1] Position [1180, 320, 1215, 330] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[6.11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6." "11 6.11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Goto Name "Goto" SID "3468" Position [1005, 316, 1075, 334] ZOrder -10 ShowName off GotoTag "CS_ADC_I" TagVisibility "global" } Block { BlockType Goto Name "Goto1" SID "3469" Position [1005, 341, 1075, 359] ZOrder -10 ShowName off GotoTag "CS_ADC_Q" TagVisibility "global" } Block { BlockType Goto Name "Goto3" SID "3470" Position [1030, 750, 1125, 770] ZOrder -10 ShowName off GotoTag "CS_G_RF" TagVisibility "global" } Block { BlockType Goto Name "Goto4" SID "3471" Position [1030, 805, 1125, 825] ZOrder -10 ShowName off GotoTag "CS_G_BB" TagVisibility "global" } Block { BlockType Goto Name "Goto5" SID "3472" Position [1335, 588, 1475, 612] ZOrder -10 ShowName off GotoTag "CS_RFA_RSSI" TagVisibility "global" } Block { BlockType Goto Name "Goto7" SID "3473" Position [1030, 720, 1125, 740] ZOrder -10 ShowName off GotoTag "RFA_AGC_G_RF" TagVisibility "global" } Block { BlockType Goto Name "Goto8" SID "3474" Position [1030, 775, 1125, 795] ZOrder -10 ShowName off GotoTag "RFA_AGC_G_BB" TagVisibility "global" } Block { BlockType SubSystem Name "RF A RSSI Sum" SID "3475" Ports [1, 1] Position [1145, 526, 1215, 554] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "RF A RSSI Sum" Location [168, 292, 964, 583] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "RSSI" SID "3476" Position [120, 48, 150, 62] IconDisplay "Port number" } Block { BlockType Reference Name "Down Sample6" SID "3477" Ports [1, 1] Position [225, 98, 250, 122] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Down Sample" SourceType "Xilinx Down Sampler Block" infoedit "Hardware notes: Sample and Latency controls determine the hardware implementation. The cost in hardw" "are of different implementations varies considerably; press Help for details." sample_ratio "16" sample_phase "Last Value of Frame (most efficient)" en off latency "1" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,356,300" block_type "dsamp" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,24,1,1,white,blue,0,40e65a2b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 24 24 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 24 24 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[15.33 15.33 " "18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[12.33 12.33 15.33 15.33 1" "2.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 1 1 ]);\npat" "ch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 0.973 ]);\nfprin" "tf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-1}\\ne" "wline ','texmode','on');\ncolor('black');disp(' \\newline{\\fontsize{14pt}\\bf\\downarrow}16','texmode','on');\nfp" "rintf('','COMMENT: end icon text');" } Block { BlockType From Name "From12" SID "3478" Position [25, 101, 180, 119] ShowName off CloseFcn "tagdialog Close" GotoTag "RX_GLOBAL_RESET" TagVisibility "global" } Block { BlockType SubSystem Name "RSSI DET\nDebug Out" SID "3479" Ports [2] Position [470, 285, 530, 325] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "RSSI DET\nDebug Out" Location [203, 179, 2137, 1473] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "125" Block { BlockType Inport Name "Avg RSSI" SID "3480" Position [170, 243, 200, 257] IconDisplay "Port number" } Block { BlockType Inport Name "Raw RSSI" SID "3481" Position [170, 328, 200, 342] Port "2" IconDisplay "Port number" } Block { BlockType From Name "From1" SID "3482" Position [205, 170, 375, 190] ShowName off CloseFcn "tagdialog Close" GotoTag "regRx_Debug_RSSI_Sel" TagVisibility "global" } Block { BlockType From Name "From2" SID "3483" Position [180, 420, 350, 440] ShowName off CloseFcn "tagdialog Close" GotoTag "regRx_Debug_RSSI_THRESH" TagVisibility "global" } Block { BlockType Goto Name "Goto1" SID "3484" Position [790, 443, 930, 467] ZOrder -10 ShowName off GotoTag "CS_RFA_RSSI_DET" TagVisibility "global" } Block { BlockType Reference Name "Mux" SID "3485" Ports [3, 1] Position [575, 189, 620, 381] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "45,192,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 27.4286 164.571 192 0 " "],[0.77 0.82 0.91 ]);\nplot([0 45 45 0 0 ],[0 27.4286 164.571 192 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23." "32 14.65 8.65 ],[102.66 102.66 108.66 102.66 108.66 108.66 108.66 102.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 " "8.65 14.65 ],[96.66 96.66 102.66 102.66 96.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[90" ".66 90.66 96.66 96.66 90.66 ],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[84.66 84.66 90.66 8" "4.66 90.66 90.66 84.66 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT:" " begin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\nco" "lor('black');port_label('input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: " "end icon text');" } Block { BlockType Reference Name "Register1" SID "3486" Ports [1, 1] Position [270, 315, 305, 355] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,40,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 40 40 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode'," "'on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "3487" Ports [1, 1] Position [690, 265, 725, 305] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,40,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 40 40 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode'," "'on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register3" SID "3488" Ports [1, 1] Position [780, 265, 815, 305] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,40,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 40 40 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode'," "'on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register4" SID "3489" Ports [1, 1] Position [270, 230, 305, 270] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,40,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 40 40 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode'," "'on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational" SID "3490" Ports [2, 1] Position [455, 322, 510, 378] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a>b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "55,56,2,1,white,blue,0,b5131c97,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 56 56 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 56 56 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ],[35" ".77 35.77 42.77 35.77 42.77 42.77 42.77 35.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[28.77 28." "77 35.77 35.77 28.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[21.77 21.77 28.77 28.7" "7 21.77 ],[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[14.77 14.77 21.77 14.77 21.77 21.77" " 14.77 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text" "');\ncolor('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_l" "abel('output',1,'\\bfa > b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational1" SID "3491" Ports [2, 1] Position [455, 237, 510, 293] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a>b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "55,56,2,1,white,blue,0,b5131c97,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 56 56 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 56 56 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ],[35" ".77 35.77 42.77 35.77 42.77 42.77 42.77 35.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[28.77 28." "77 35.77 35.77 28.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[21.77 21.77 28.77 28.7" "7 21.77 ],[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[14.77 14.77 21.77 14.77 21.77 21.77" " 14.77 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text" "');\ncolor('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_l" "abel('output',1,'\\bfa > b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "dbg_RSSI_DET" SID "3492" Ports [1, 1] Position [885, 278, 925, 292] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "8.2" sg_icon_stat "40,14,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.95 0.93" " 0.65 ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9.22 " "9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22 9.22" " 7.22 ],[0.985 0.979 0.895 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\np" "atch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.985 0.979 0.895 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i" "nput',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Register3" DstPort 1 } Line { SrcBlock "Register3" SrcPort 1 DstBlock "dbg_RSSI_DET" DstPort 1 } Line { SrcBlock "From2" SrcPort 1 Points [70, 0; 0, -65] Branch { DstBlock "Relational" DstPort 2 } Branch { Points [0, -85] DstBlock "Relational1" DstPort 2 } } Line { SrcBlock "Raw RSSI" SrcPort 1 DstBlock "Register1" DstPort 1 } Line { SrcBlock "Register1" SrcPort 1 DstBlock "Relational" DstPort 1 } Line { SrcBlock "Avg RSSI" SrcPort 1 DstBlock "Register4" DstPort 1 } Line { SrcBlock "Register4" SrcPort 1 DstBlock "Relational1" DstPort 1 } Line { SrcBlock "Relational" SrcPort 1 DstBlock "Mux" DstPort 3 } Line { SrcBlock "Relational1" SrcPort 1 Points [20, 0; 0, 20] DstBlock "Mux" DstPort 2 } Line { SrcBlock "Mux" SrcPort 1 Points [40, 0] Branch { DstBlock "Register2" DstPort 1 } Branch { Points [0, 170] DstBlock "Goto1" DstPort 1 } } Line { SrcBlock "From1" SrcPort 1 Points [75, 0; 0, 40] DstBlock "Mux" DstPort 1 } } } Block { BlockType SubSystem Name "Running Sum" SID "3493" Ports [2, 1] Position [300, 27, 365, 138] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Running Sum" Location [203, 179, 2137, 1473] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "RSSI" SID "3494" Position [500, 143, 530, 157] IconDisplay "Port number" } Block { BlockType Inport Name "reset" SID "3495" Position [240, 269, 270, 281] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "ASR" SID "3496" Ports [2, 1] Position [720, 165, 760, 200] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Addressable Shift Register" SourceType "Xilinx Addressable Shift Register Block" infoedit "Delay of configurable length. Any element in the delay line can be addressed and " " driven onto the output port.

Hardware notes: Implemented using SRL16s. If Virtex-4, Virt" "ex-II or Spartan-3 devices are used, multiple SRLC16s are cascaded together." infer_latency on depth "2" initVector "[0]" en off dbl_ovrd off use_behavioral_HDL off Optimization "Resource" xl_use_area off xl_area "[0,0,0,0,0,0,0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,356,359" block_type "addrsr" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,35,2,1,white,blue,0,a352fb33,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 35 35 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 35 35 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[22.55 22." "55 27.55 22.55 27.55 27.55 27.55 22.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[17.55 17.55 22.55 2" "2.55 17.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[12.55 12.55 17.55 17.55 12.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[7.55 7.55 12.55 7.55 12.55 12.55 7.55 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');por" "t_label('input',1,'d');\ncolor('black');port_label('input',2,'addr');\ncolor('black');port_label('output',1,'q')" ";\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Accumulator" SID "3497" Ports [2, 1] Position [895, 164, 930, 206] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Accumulator" SourceType "Xilinx Accumulator Block" infoedit "Adder or subtractor-based accumulator. Output type and binary point position match the input.

Hardware notes: When \"Reinitialize with input 'b' on reset\" is selected, the accumulator is forced to run " "at the system rate even if the input 'b' is running at a slower rate." operation "Add" n_bits "17" overflow "Flag as error" scale "1" rst on infoeditControl "reset for floating point data type must be asserted for a minimum of 2 cycles" hasbypass off en off latency "0" dbl_ovrd off msb_inp "100" msb "100" lsb "-100" use_behavioral_HDL on implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,356,457" block_type "accum" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,42,2,1,white,blue,0,6949434e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 42 42 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 42 42 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[26.55 26." "55 31.55 26.55 31.55 31.55 31.55 26.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[21.55 21.55 26.55 2" "6.55 21.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[16.55 16.55 21.55 21.55 16.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[11.55 11.55 16.55 11.55 16.55 16.55 11.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'b');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'" "\\bf+=b','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub" SID "3498" Ports [2, 1] Position [805, 146, 840, 199] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Subtraction" use_carryin off use_carryout off en off latency "0" precision "Full" arith_type "Unsigned" n_bits "10" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL off hw_selection "Fabric" pipelined off xl_use_area off xl_area "[0,0,0,0,0,0,0]" use_rpm "on" has_advanced_control "0" sggui_pos "283,438,356,344" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,53,2,1,white,blue,0,32e1f85f,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 53 53 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 53 53 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[31.55 31." "55 36.55 31.55 36.55 36.55 36.55 31.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[26.55 26.55 31.55 3" "1.55 26.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[21.55 21.55 26.55 26.55 21.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[16.55 16.55 21.55 16.55 21.55 21.55 16.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bf{a - b}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert7" SID "3499" Ports [1, 1] Position [980, 177, 1005, 193] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "17" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Saturate" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,461,334" block_type "convert" block_version "10.1.3" sg_icon_stat "25,16,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 16 16 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[10.22 10" ".22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[8.22 8.22 10.22 10.22" " 8.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('outpu" "t',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From1" SID "3500" Position [75, 215, 270, 235] ShowName off CloseFcn "tagdialog Close" GotoTag "regRx_RSSI_SUM_LEN_A" TagVisibility "global" } Block { BlockType Reference Name "Logical" SID "3501" Ports [2, 1] Position [510, 255, 535, 315] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,261" block_type "logical" block_version "10.1.3" sg_icon_stat "25,60,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 60 60 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 60 60 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[33.33 " "33.33 36.33 33.33 36.33 36.33 36.33 33.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[30.33 30.33 33.33" " 33.33 30.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[27.33 27.33 30.33 30.33 27.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[24.33 24.33 27.33 24.33 27.33 27.33 24.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor" "('black');disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Long Reset Gen" SID "3502" Ports [2, 1] Position [375, 250, 470, 285] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Long Reset Gen" Location [203, 179, 2137, 1473] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "duration" SID "3503" Position [60, 258, 90, 272] IconDisplay "Port number" } Block { BlockType Inport Name "reset_in" SID "3504" Position [60, 188, 90, 202] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Counter" SID "3505" Ports [2, 1] Position [405, 172, 455, 223] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited count" "er is implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "0" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "8" bin_pt "0" load_pin off rst on en on explicit_period "off" period "4" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,356,619" block_type "counter" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,51,2,1,white,blue,0,ae3608d6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 51 51 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 51 51 0 ]);\npatch([9.425 19.54 26.54 33.54 40.54 26.54 16.425 9.425 ],[32.7" "7 32.77 39.77 32.77 39.77 39.77 39.77 32.77 ],[1 1 1 ]);\npatch([16.425 26.54 19.54 9.425 16.425 ],[25.77 25.77 " "32.77 32.77 25.77 ],[0.931 0.946 0.973 ]);\npatch([9.425 19.54 26.54 16.425 9.425 ],[18.77 18.77 25.77 25.77 18." "77 ],[1 1 1 ]);\npatch([16.425 40.54 33.54 26.54 19.54 9.425 16.425 ],[11.77 11.77 18.77 11.77 18.77 18.77 11.77" " ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nc" "olor('black');port_label('input',1,'rst');\ncolor('black');port_label('input',2,'en');\n\ncolor('black');disp('{" "\\fontsize{14}\\bf++}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Relational" SID "3506" Ports [2, 1] Position [530, 188, 575, 232] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bfa = b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "S-R Latch" SID "3507" Ports [2, 1] Position [225, 182, 255, 233] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "S-R Latch" Location [160, 70, 1918, 1152] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "3508" Position [140, 103, 170, 117] IconDisplay "Port number" } Block { BlockType Inport Name "R" SID "3509" Position [140, 88, 170, 102] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "3510" Ports [0, 1] Position [195, 71, 210, 89] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,400,346" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "15,18,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11.22 " "13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 9.22 " "],[0.931 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([4.55 " "11.44 9.44 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "3511" Ports [3, 1] Position [255, 71, 300, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "3512" Position [325, 88, 355, 102] IconDisplay "Port number" } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "S" SrcPort 1 DstBlock "Register2" DstPort 3 } } } Block { BlockType Outport Name "reset_out" SID "3513" Position [465, 93, 495, 107] IconDisplay "Port number" } Line { SrcBlock "Relational" SrcPort 1 Points [0, -50; -210, 0] Branch { Points [0, 25] DstBlock "Counter" DstPort 1 } Branch { Points [-175, 0; 0, 60] DstBlock "S-R Latch" DstPort 2 } } Line { SrcBlock "Counter" SrcPort 1 Points [0, 0] DstBlock "Relational" DstPort 1 } Line { SrcBlock "reset_in" SrcPort 1 DstBlock "S-R Latch" DstPort 1 } Line { SrcBlock "duration" SrcPort 1 Points [420, 0] DstBlock "Relational" DstPort 2 } Line { SrcBlock "S-R Latch" SrcPort 1 Points [55, 0] Branch { DstBlock "Counter" DstPort 2 } Branch { Points [0, -110] DstBlock "reset_out" DstPort 1 } } } } Block { BlockType Reference Name "Register" SID "3514" Ports [2, 1] Position [615, 141, 655, 179] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,38,2,1,white,blue,0,140cc11c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 38 38 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 38 38 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[24.55 24." "55 29.55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[19.55 19.55 24.55 2" "4.55 19.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');por" "t_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'q');" "\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "avg" SID "3515" Position [1060, 178, 1090, 192] IconDisplay "Port number" } Line { SrcBlock "ASR" SrcPort 1 DstBlock "AddSub" DstPort 2 } Line { SrcBlock "AddSub" SrcPort 1 DstBlock "Accumulator" DstPort 1 } Line { SrcBlock "Register" SrcPort 1 Points [35, 0] Branch { Points [0, 15] DstBlock "ASR" DstPort 1 } Branch { DstBlock "AddSub" DstPort 1 } } Line { SrcBlock "From1" SrcPort 1 Points [60, 0] Branch { Points [370, 0] DstBlock "ASR" DstPort 2 } Branch { Points [0, 35] DstBlock "Long Reset Gen" DstPort 1 } } Line { SrcBlock "RSSI" SrcPort 1 DstBlock "Register" DstPort 1 } Line { SrcBlock "Accumulator" SrcPort 1 DstBlock "Convert7" DstPort 1 } Line { SrcBlock "Logical" SrcPort 1 Points [40, 0] Branch { Points [0, -115] DstBlock "Register" DstPort 2 } Branch { Points [265, 0; 0, -90] DstBlock "Accumulator" DstPort 2 } } Line { SrcBlock "reset" SrcPort 1 Points [60, 0] Branch { DstBlock "Long Reset Gen" DstPort 2 } Branch { Points [0, 25] DstBlock "Logical" DstPort 2 } } Line { SrcBlock "Long Reset Gen" SrcPort 1 DstBlock "Logical" DstPort 1 } Line { SrcBlock "Convert7" SrcPort 1 DstBlock "avg" DstPort 1 } Annotation { Name "This block impelemnts a variable-length running sum.\nFor a sum y(n) of the previous N samples of seq" "uence x(n), it implements\ny(n) = y(n-1) + x(n) - x(n-N)\nThis requires a careful reset procedure, where the ful" "l shift register\nis zerored out. Otherwise the feedback-based sum stops working." Position [289, 149] } } } Block { BlockType Outport Name "Sum" SID "3516" Position [470, 78, 500, 92] IconDisplay "Port number" } Line { SrcBlock "From12" SrcPort 1 DstBlock "Down Sample6" DstPort 1 } Line { SrcBlock "RSSI" SrcPort 1 Points [30, 0] Branch { DstBlock "Running Sum" DstPort 1 } Branch { Points [0, 260] DstBlock "RSSI DET\nDebug Out" DstPort 2 } } Line { SrcBlock "Down Sample6" SrcPort 1 DstBlock "Running Sum" DstPort 2 } Line { SrcBlock "Running Sum" SrcPort 1 Points [20, 0] Branch { DstBlock "Sum" DstPort 1 } Branch { Points [0, 210] DstBlock "RSSI DET\nDebug Out" DstPort 1 } } } } Block { BlockType Reference Name "RFA_G_BB" SID "3517" Ports [1, 1] Position [640, 778, 680, 792] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to" " Xilinx fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top l" "evel input ports." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "5" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "40,14,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9" ".22 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22" " 9.22 7.22 ],[0.985 0.979 0.895 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.985 0.979 0.89" "5 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprint" "f('','COMMENT: end icon text');" } Block { BlockType Reference Name "RFA_G_RF" SID "3518" Ports [1, 1] Position [640, 723, 680, 737] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to" " Xilinx fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top l" "evel input ports." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "40,14,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9" ".22 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22" " 9.22 7.22 ],[0.985 0.979 0.895 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.985 0.979 0.89" "5 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprint" "f('','COMMENT: end icon text');" } Block { BlockType Reference Name "RFA_RSSI" SID "3519" Ports [1, 1] Position [640, 523, 680, 537] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to" " Xilinx fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top l" "evel input ports." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "10" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "40,14,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9" ".22 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22" " 9.22 7.22 ],[0.985 0.979 0.895 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.985 0.979 0.89" "5 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprint" "f('','COMMENT: end icon text');" } Block { BlockType Reference Name "RFA_RX_I" SID "3520" Ports [1, 1] Position [640, 408, 680, 422] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to" " Xilinx fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top l" "evel input ports." gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "16" bin_pt "15" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "40,14,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9" ".22 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22" " 9.22 7.22 ],[0.985 0.979 0.895 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.985 0.979 0.89" "5 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprint" "f('','COMMENT: end icon text');" } Block { BlockType Reference Name "RFA_RX_Q" SID "3521" Ports [1, 1] Position [640, 458, 680, 472] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to" " Xilinx fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top l" "evel input ports." gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "16" bin_pt "15" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "40,14,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9" ".22 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22" " 9.22 7.22 ],[0.985 0.979 0.895 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.985 0.979 0.89" "5 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprint" "f('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register" SID "3522" Ports [3, 1] Position [980, 407, 1020, 443] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "40,36,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 36 36 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 36 36 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[23.55" " 23.55 28.55 23.55 28.55 28.55 28.55 23.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[18.55 18.55 23" ".55 23.55 18.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[13.55 13.55 18.55 18.55 13.55 " "],[1 1 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[8.55 8.55 13.55 8.55 13.55 13.55 8.55 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bla" "ck');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input'" ",3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('" "','COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "3523" Ports [3, 1] Position [980, 457, 1020, 493] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "40,36,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 36 36 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 36 36 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[23.55" " 23.55 28.55 23.55 28.55 28.55 28.55 23.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[18.55 18.55 23" ".55 23.55 18.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[13.55 13.55 18.55 18.55 13.55 " "],[1 1 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[8.55 8.55 13.55 8.55 13.55 13.55 8.55 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bla" "ck');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input'" ",3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('" "','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "3524" Ports [1, 1] Position [750, 400, 775, 430] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 30 30 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 30 30 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[18" ".33 18.33 21.33 18.33 21.33 21.33 21.33 18.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[15.33 15.33 " "18.33 18.33 15.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[12.33 12.33 15.33 15.33 12.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[9.33 9.33 12.33 9.33 12.33 12.33 9.33 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register3" SID "3525" Ports [2, 1] Position [980, 520, 1015, 555] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,35,2,1,white,blue,0,140cc11c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 35 35 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 35 35 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[22.55" " 22.55 27.55 22.55 27.55 27.55 27.55 22.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[17.55 17.55 22" ".55 22.55 17.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[12.55 12.55 17.55 17.55 12.55 " "],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[7.55 7.55 12.55 7.55 12.55 12.55 7.55 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bla" "ck');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output" "',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register4" SID "3526" Ports [1, 1] Position [750, 450, 775, 480] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 30 30 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 30 30 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[18" ".33 18.33 21.33 18.33 21.33 21.33 21.33 18.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[15.33 15.33 " "18.33 18.33 15.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[12.33 12.33 15.33 15.33 12.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[9.33 9.33 12.33 9.33 12.33 12.33 9.33 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register5" SID "3527" Ports [1, 1] Position [750, 515, 775, 545] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 30 30 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 30 30 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[18" ".33 18.33 21.33 18.33 21.33 21.33 21.33 18.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[15.33 15.33 " "18.33 18.33 15.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[12.33 12.33 15.33 15.33 12.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[9.33 9.33 12.33 9.33 12.33 12.33 9.33 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Signum Name "Sign" SID "18127" Position [1255, 310, 1285, 340] ZOrder -25 } Block { BlockType ToWorkspace Name "To Workspace" SID "18122" Ports [1] Position [1430, 312, 1585, 338] ZOrder -7 ShowName off VariableName "rx_sim_nonzero_iq_input" MaxDataPoints "inf" SampleTime "-1" SaveFormat "Array" } Block { BlockType ZeroOrderHold Name "Zero-Order\nHold" SID "8484" Position [520, 402, 545, 428] ZOrder -19 ShowName off } Block { BlockType ZeroOrderHold Name "Zero-Order\nHold1" SID "8485" Position [520, 452, 545, 478] ZOrder -19 ShowName off } Block { BlockType Outport Name "ADC I" SID "3528" Position [1290, 418, 1320, 432] IconDisplay "Port number" } Block { BlockType Outport Name "ADC Q" SID "3529" Position [1290, 468, 1320, 482] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "Avg RSSI" SID "3530" Position [1290, 533, 1320, 547] Port "3" IconDisplay "Port number" } Line { SrcBlock "Complex to\nReal-Imag" SrcPort 1 DstBlock "Zero-Order\nHold" DstPort 1 } Line { SrcBlock "Complex to\nReal-Imag" SrcPort 2 DstBlock "Zero-Order\nHold1" DstPort 1 } Line { SrcBlock "RFA_RX_I" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "RFA_RX_Q" SrcPort 1 DstBlock "Register4" DstPort 1 } Line { SrcBlock "Register" SrcPort 1 Points [80, 0] Branch { DstBlock "ADC I" DstPort 1 } Branch { Points [0, -100] DstBlock "Gateway Out" DstPort 1 } } Line { SrcBlock "Register1" SrcPort 1 DstBlock "ADC Q" DstPort 1 } Line { SrcBlock "Register3" SrcPort 1 DstBlock "Down Sample" DstPort 1 } Line { SrcBlock "Down Sample" SrcPort 1 DstBlock "RF A RSSI Sum" DstPort 1 } Line { SrcBlock "RF A RSSI Sum" SrcPort 1 Points [10, 0] Branch { Points [0, 60] DstBlock "Goto5" DstPort 1 } Branch { DstBlock "Avg RSSI" DstPort 1 } } Line { SrcBlock "RFA_RSSI" SrcPort 1 DstBlock "Register5" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 Points [100, 0] Branch { DstBlock "Register" DstPort 1 } Branch { Points [0, -90] DstBlock "Goto" DstPort 1 } } Line { SrcBlock "Register4" SrcPort 1 Points [105, 0] Branch { DstBlock "Register1" DstPort 1 } Branch { Points [0, -115] DstBlock "Goto1" DstPort 1 } } Line { SrcBlock "Register5" SrcPort 1 DstBlock "Register3" DstPort 1 } Line { SrcBlock "Rst" SrcPort 1 Points [105, 0] Branch { DstBlock "Register" DstPort 2 } Branch { Points [0, 50] Branch { DstBlock "Register1" DstPort 2 } Branch { Points [0, 70] DstBlock "Register3" DstPort 2 } } } Line { SrcBlock "IQ Valid" SrcPort 1 Points [35, 0] Branch { DstBlock "Register1" DstPort 3 } Branch { Points [0, -50] DstBlock "Register" DstPort 3 } } Line { SrcBlock "RFA_G_RF" SrcPort 1 DstBlock "Delay1" DstPort 1 } Line { SrcBlock "RFA_G_BB" SrcPort 1 DstBlock "Delay2" DstPort 1 } Line { SrcBlock "Delay1" SrcPort 1 Points [125, 0] Branch { Points [0, 30] DstBlock "Goto3" DstPort 1 } Branch { DstBlock "Goto7" DstPort 1 } } Line { SrcBlock "Delay2" SrcPort 1 Points [125, 0] Branch { Points [0, 30] DstBlock "Goto4" DstPort 1 } Branch { DstBlock "Goto8" DstPort 1 } } Line { SrcBlock "Constant2" SrcPort 1 DstBlock "RFA_G_RF" DstPort 1 } Line { SrcBlock "Constant4" SrcPort 1 DstBlock "RFA_G_BB" DstPort 1 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "RFA_RSSI" DstPort 1 } Line { SrcBlock "From\nWorkspace" SrcPort 1 DstBlock "Complex to\nReal-Imag" DstPort 1 } Line { SrcBlock "Zero-Order\nHold" SrcPort 1 DstBlock "RFA_RX_I" DstPort 1 } Line { SrcBlock "Zero-Order\nHold1" SrcPort 1 DstBlock "RFA_RX_Q" DstPort 1 } Line { SrcBlock "Gateway Out" SrcPort 1 DstBlock "Sign" DstPort 1 } Line { SrcBlock "Sign" SrcPort 1 DstBlock "Abs" DstPort 1 } Line { SrcBlock "Abs" SrcPort 1 DstBlock "To Workspace" DstPort 1 } } } Block { BlockType SubSystem Name "RF B Inputs" SID "3531" Ports [2, 3] Position [695, 251, 800, 299] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "RF B Inputs" Location [138, 279, 2317, 1561] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Rst" SID "3532" Position [795, 418, 825, 432] IconDisplay "Port number" } Block { BlockType Inport Name "IQ Valid" SID "3533" Position [795, 478, 825, 492] Port "2" IconDisplay "Port number" } Block { BlockType Constant Name "Constant1" SID "3534" Position [560, 400, 590, 430] ZOrder -5 ShowName off Value "0" } Block { BlockType Constant Name "Constant2" SID "3535" Position [560, 450, 590, 480] ZOrder -5 ShowName off Value "0" } Block { BlockType Constant Name "Constant3" SID "3536" Position [560, 515, 590, 545] ZOrder -5 ShowName off Value "0" } Block { BlockType Constant Name "Constant6" SID "3537" Position [560, 655, 590, 685] ZOrder -5 ShowName off Value "2" } Block { BlockType Constant Name "Constant7" SID "3538" Position [560, 710, 590, 740] ZOrder -5 ShowName off Value "5" } Block { BlockType Reference Name "Delay4" SID "3539" Ports [1, 1] Position [840, 655, 870, 685] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "30,30,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 30 30 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 30 30 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 " "19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 1" "9.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');di" "sp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay5" SID "3540" Ports [1, 1] Position [840, 710, 870, 740] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "30,30,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 30 30 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 30 30 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 " "19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 1" "9.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');di" "sp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Down Sample" SID "3541" Ports [1, 1] Position [1050, 525, 1075, 555] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Down Sample" SourceType "Xilinx Down Sampler Block" infoedit "Hardware notes: Sample and Latency controls determine the hardware implementation. The cost i" "n hardware of different implementations varies considerably; press Help for details." sample_ratio "16" sample_phase "Last Value of Frame (most efficient)" en off latency "1" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "dsamp" sg_icon_stat "25,30,1,1,white,blue,0,40e65a2b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 30 30 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 30 30 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[18" ".33 18.33 21.33 18.33 21.33 21.33 21.33 18.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[15.33 15.33 " "18.33 18.33 15.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[12.33 12.33 15.33 15.33 12.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[9.33 9.33 12.33 9.33 12.33 12.33 9.33 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncol" "or('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\newline{\\fontsize{14pt}\\bf\\dow" "narrow}16','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Goto Name "Goto12" SID "3542" Position [1035, 660, 1130, 680] ZOrder -10 ShowName off GotoTag "RFB_AGC_G_RF" TagVisibility "global" } Block { BlockType Goto Name "Goto13" SID "3543" Position [1035, 715, 1130, 735] ZOrder -10 ShowName off GotoTag "RFB_AGC_G_BB" TagVisibility "global" } Block { BlockType SubSystem Name "RF B RSSI Sum" SID "3544" Ports [1, 1] Position [1145, 526, 1215, 554] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "RF B RSSI Sum" Location [138, 279, 2317, 1561] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "RSSI" SID "3545" Position [120, 48, 150, 62] IconDisplay "Port number" } Block { BlockType Reference Name "Down Sample6" SID "3546" Ports [1, 1] Position [225, 98, 250, 122] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Down Sample" SourceType "Xilinx Down Sampler Block" infoedit "Hardware notes: Sample and Latency controls determine the hardware implementation. The cost in hardw" "are of different implementations varies considerably; press Help for details." sample_ratio "16" sample_phase "Last Value of Frame (most efficient)" en off latency "1" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,356,300" block_type "dsamp" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,24,1,1,white,blue,0,40e65a2b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 24 24 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 24 24 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[15.33 15.33 " "18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[12.33 12.33 15.33 15.33 1" "2.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 1 1 ]);\npat" "ch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 0.973 ]);\nfprin" "tf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-1}\\ne" "wline ','texmode','on');\ncolor('black');disp(' \\newline{\\fontsize{14pt}\\bf\\downarrow}16','texmode','on');\nfp" "rintf('','COMMENT: end icon text');" } Block { BlockType From Name "From12" SID "3547" Position [25, 101, 180, 119] ShowName off CloseFcn "tagdialog Close" GotoTag "RX_GLOBAL_RESET" TagVisibility "global" } Block { BlockType SubSystem Name "Running Sum" SID "3548" Ports [2, 1] Position [300, 27, 365, 138] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Running Sum" Location [203, 179, 2137, 1473] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "RSSI" SID "3549" Position [500, 143, 530, 157] IconDisplay "Port number" } Block { BlockType Inport Name "reset" SID "3550" Position [240, 269, 270, 281] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "ASR" SID "3551" Ports [2, 1] Position [720, 165, 760, 200] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Addressable Shift Register" SourceType "Xilinx Addressable Shift Register Block" infoedit "Delay of configurable length. Any element in the delay line can be addressed and " " driven onto the output port.

Hardware notes: Implemented using SRL16s. If Virtex-4, Virt" "ex-II or Spartan-3 devices are used, multiple SRLC16s are cascaded together." infer_latency on depth "2" initVector "[0]" en off dbl_ovrd off use_behavioral_HDL off Optimization "Resource" xl_use_area off xl_area "[0,0,0,0,0,0,0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,356,359" block_type "addrsr" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,35,2,1,white,blue,0,a352fb33,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 35 35 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 35 35 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[22.55 22." "55 27.55 22.55 27.55 27.55 27.55 22.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[17.55 17.55 22.55 2" "2.55 17.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[12.55 12.55 17.55 17.55 12.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[7.55 7.55 12.55 7.55 12.55 12.55 7.55 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');por" "t_label('input',1,'d');\ncolor('black');port_label('input',2,'addr');\ncolor('black');port_label('output',1,'q')" ";\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Accumulator" SID "3552" Ports [2, 1] Position [895, 164, 930, 206] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Accumulator" SourceType "Xilinx Accumulator Block" infoedit "Adder or subtractor-based accumulator. Output type and binary point position match the input.

Hardware notes: When \"Reinitialize with input 'b' on reset\" is selected, the accumulator is forced to run " "at the system rate even if the input 'b' is running at a slower rate." operation "Add" n_bits "17" overflow "Flag as error" scale "1" rst on infoeditControl "reset for floating point data type must be asserted for a minimum of 2 cycles" hasbypass off en off latency "0" dbl_ovrd off msb_inp "100" msb "100" lsb "-100" use_behavioral_HDL on implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,356,457" block_type "accum" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,42,2,1,white,blue,0,6949434e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 42 42 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 42 42 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[26.55 26." "55 31.55 26.55 31.55 31.55 31.55 26.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[21.55 21.55 26.55 2" "6.55 21.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[16.55 16.55 21.55 21.55 16.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[11.55 11.55 16.55 11.55 16.55 16.55 11.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'b');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'" "\\bf+=b','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub" SID "3553" Ports [2, 1] Position [805, 146, 840, 199] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Subtraction" use_carryin off use_carryout off en off latency "0" precision "Full" arith_type "Unsigned" n_bits "10" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL off hw_selection "Fabric" pipelined off xl_use_area off xl_area "[0,0,0,0,0,0,0]" use_rpm "on" has_advanced_control "0" sggui_pos "283,438,356,344" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,53,2,1,white,blue,0,32e1f85f,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 53 53 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 53 53 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[31.55 31." "55 36.55 31.55 36.55 36.55 36.55 31.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[26.55 26.55 31.55 3" "1.55 26.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[21.55 21.55 26.55 26.55 21.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[16.55 16.55 21.55 16.55 21.55 21.55 16.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bf{a - b}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert7" SID "3554" Ports [1, 1] Position [980, 177, 1005, 193] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "17" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Saturate" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,461,334" block_type "convert" block_version "10.1.3" sg_icon_stat "25,16,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 16 16 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[10.22 10" ".22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[8.22 8.22 10.22 10.22" " 8.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('outpu" "t',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From1" SID "3555" Position [75, 215, 270, 235] ShowName off CloseFcn "tagdialog Close" GotoTag "regRx_RSSI_SUM_LEN_B" TagVisibility "global" } Block { BlockType Reference Name "Logical" SID "3556" Ports [2, 1] Position [510, 255, 535, 315] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,261" block_type "logical" block_version "10.1.3" sg_icon_stat "25,60,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 60 60 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 60 60 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[33.33 " "33.33 36.33 33.33 36.33 36.33 36.33 33.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[30.33 30.33 33.33" " 33.33 30.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[27.33 27.33 30.33 30.33 27.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[24.33 24.33 27.33 24.33 27.33 27.33 24.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor" "('black');disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Long Reset Gen" SID "3557" Ports [2, 1] Position [375, 250, 470, 285] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Long Reset Gen" Location [203, 179, 2137, 1473] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "duration" SID "3558" Position [60, 258, 90, 272] IconDisplay "Port number" } Block { BlockType Inport Name "reset_in" SID "3559" Position [60, 188, 90, 202] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Counter" SID "3560" Ports [2, 1] Position [405, 172, 455, 223] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited count" "er is implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "0" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "8" bin_pt "0" load_pin off rst on en on explicit_period "off" period "4" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,356,619" block_type "counter" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,51,2,1,white,blue,0,ae3608d6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 51 51 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 51 51 0 ]);\npatch([9.425 19.54 26.54 33.54 40.54 26.54 16.425 9.425 ],[32.7" "7 32.77 39.77 32.77 39.77 39.77 39.77 32.77 ],[1 1 1 ]);\npatch([16.425 26.54 19.54 9.425 16.425 ],[25.77 25.77 " "32.77 32.77 25.77 ],[0.931 0.946 0.973 ]);\npatch([9.425 19.54 26.54 16.425 9.425 ],[18.77 18.77 25.77 25.77 18." "77 ],[1 1 1 ]);\npatch([16.425 40.54 33.54 26.54 19.54 9.425 16.425 ],[11.77 11.77 18.77 11.77 18.77 18.77 11.77" " ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nc" "olor('black');port_label('input',1,'rst');\ncolor('black');port_label('input',2,'en');\n\ncolor('black');disp('{" "\\fontsize{14}\\bf++}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Relational" SID "3561" Ports [2, 1] Position [530, 188, 575, 232] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bfa = b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "S-R Latch" SID "3562" Ports [2, 1] Position [225, 182, 255, 233] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "S-R Latch" Location [160, 70, 1918, 1152] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "3563" Position [140, 103, 170, 117] IconDisplay "Port number" } Block { BlockType Inport Name "R" SID "3564" Position [140, 88, 170, 102] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "3565" Ports [0, 1] Position [195, 71, 210, 89] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,400,346" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "15,18,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11.22 " "13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 9.22 " "],[0.931 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([4.55 " "11.44 9.44 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "3566" Ports [3, 1] Position [255, 71, 300, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "3567" Position [325, 88, 355, 102] IconDisplay "Port number" } Line { SrcBlock "S" SrcPort 1 DstBlock "Register2" DstPort 3 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Register2" DstPort 1 } } } Block { BlockType Outport Name "reset_out" SID "3568" Position [465, 93, 495, 107] IconDisplay "Port number" } Line { SrcBlock "S-R Latch" SrcPort 1 Points [55, 0] Branch { Points [0, -110] DstBlock "reset_out" DstPort 1 } Branch { DstBlock "Counter" DstPort 2 } } Line { SrcBlock "duration" SrcPort 1 Points [420, 0] DstBlock "Relational" DstPort 2 } Line { SrcBlock "reset_in" SrcPort 1 DstBlock "S-R Latch" DstPort 1 } Line { SrcBlock "Counter" SrcPort 1 Points [0, 0] DstBlock "Relational" DstPort 1 } Line { SrcBlock "Relational" SrcPort 1 Points [0, -50; -210, 0] Branch { Points [-175, 0; 0, 60] DstBlock "S-R Latch" DstPort 2 } Branch { Points [0, 25] DstBlock "Counter" DstPort 1 } } } } Block { BlockType Reference Name "Register" SID "3569" Ports [2, 1] Position [615, 141, 655, 179] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,38,2,1,white,blue,0,140cc11c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 38 38 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 38 38 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[24.55 24." "55 29.55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[19.55 19.55 24.55 2" "4.55 19.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');por" "t_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'q');" "\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "avg" SID "3570" Position [1060, 178, 1090, 192] IconDisplay "Port number" } Line { SrcBlock "Convert7" SrcPort 1 DstBlock "avg" DstPort 1 } Line { SrcBlock "Long Reset Gen" SrcPort 1 DstBlock "Logical" DstPort 1 } Line { SrcBlock "reset" SrcPort 1 Points [60, 0] Branch { Points [0, 25] DstBlock "Logical" DstPort 2 } Branch { DstBlock "Long Reset Gen" DstPort 2 } } Line { SrcBlock "Logical" SrcPort 1 Points [40, 0] Branch { Points [265, 0; 0, -90] DstBlock "Accumulator" DstPort 2 } Branch { Points [0, -115] DstBlock "Register" DstPort 2 } } Line { SrcBlock "Accumulator" SrcPort 1 DstBlock "Convert7" DstPort 1 } Line { SrcBlock "RSSI" SrcPort 1 DstBlock "Register" DstPort 1 } Line { SrcBlock "From1" SrcPort 1 Points [60, 0] Branch { Points [0, 35] DstBlock "Long Reset Gen" DstPort 1 } Branch { Points [370, 0] DstBlock "ASR" DstPort 2 } } Line { SrcBlock "Register" SrcPort 1 Points [35, 0] Branch { DstBlock "AddSub" DstPort 1 } Branch { Points [0, 15] DstBlock "ASR" DstPort 1 } } Line { SrcBlock "AddSub" SrcPort 1 DstBlock "Accumulator" DstPort 1 } Line { SrcBlock "ASR" SrcPort 1 DstBlock "AddSub" DstPort 2 } Annotation { Name "This block impelemnts a variable-length running sum.\nFor a sum y(n) of the previous N samples of seq" "uence x(n), it implements\ny(n) = y(n-1) + x(n) - x(n-N)\nThis requires a careful reset procedure, where the ful" "l shift register\nis zerored out. Otherwise the feedback-based sum stops working." Position [289, 149] } } } Block { BlockType Outport Name "Sum" SID "3571" Position [470, 78, 500, 92] IconDisplay "Port number" } Line { SrcBlock "Running Sum" SrcPort 1 DstBlock "Sum" DstPort 1 } Line { SrcBlock "Down Sample6" SrcPort 1 DstBlock "Running Sum" DstPort 2 } Line { SrcBlock "RSSI" SrcPort 1 DstBlock "Running Sum" DstPort 1 } Line { SrcBlock "From12" SrcPort 1 DstBlock "Down Sample6" DstPort 1 } } } Block { BlockType Reference Name "RFB_G_BB" SID "3572" Ports [1, 1] Position [645, 718, 685, 732] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to" " Xilinx fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top l" "evel input ports." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "5" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "40,14,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9" ".22 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22" " 9.22 7.22 ],[0.985 0.979 0.895 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.985 0.979 0.89" "5 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprint" "f('','COMMENT: end icon text');" } Block { BlockType Reference Name "RFB_G_RF" SID "3573" Ports [1, 1] Position [645, 663, 685, 677] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to" " Xilinx fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top l" "evel input ports." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "40,14,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9" ".22 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22" " 9.22 7.22 ],[0.985 0.979 0.895 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.985 0.979 0.89" "5 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprint" "f('','COMMENT: end icon text');" } Block { BlockType Reference Name "RFB_RSSI" SID "3574" Ports [1, 1] Position [645, 523, 685, 537] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to" " Xilinx fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top l" "evel input ports." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "10" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "40,14,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9" ".22 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22" " 9.22 7.22 ],[0.985 0.979 0.895 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.985 0.979 0.89" "5 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprint" "f('','COMMENT: end icon text');" } Block { BlockType Reference Name "RFB_RX_I" SID "3575" Ports [1, 1] Position [645, 408, 685, 422] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to" " Xilinx fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top l" "evel input ports." gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "16" bin_pt "15" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "40,14,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9" ".22 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22" " 9.22 7.22 ],[0.985 0.979 0.895 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.985 0.979 0.89" "5 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprint" "f('','COMMENT: end icon text');" } Block { BlockType Reference Name "RFB_RX_Q" SID "3576" Ports [1, 1] Position [645, 458, 685, 472] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to" " Xilinx fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top l" "evel input ports." gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "16" bin_pt "15" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "40,14,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9" ".22 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22" " 9.22 7.22 ],[0.985 0.979 0.895 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.985 0.979 0.89" "5 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprint" "f('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register" SID "3577" Ports [3, 1] Position [980, 407, 1020, 443] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "40,36,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 36 36 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 36 36 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[23.55" " 23.55 28.55 23.55 28.55 28.55 28.55 23.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[18.55 18.55 23" ".55 23.55 18.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[13.55 13.55 18.55 18.55 13.55 " "],[1 1 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[8.55 8.55 13.55 8.55 13.55 13.55 8.55 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bla" "ck');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input'" ",3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('" "','COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "3578" Ports [3, 1] Position [980, 457, 1020, 493] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "40,36,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 36 36 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 36 36 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[23.55" " 23.55 28.55 23.55 28.55 28.55 28.55 23.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[18.55 18.55 23" ".55 23.55 18.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[13.55 13.55 18.55 18.55 13.55 " "],[1 1 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[8.55 8.55 13.55 8.55 13.55 13.55 8.55 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bla" "ck');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input'" ",3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('" "','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "3579" Ports [1, 1] Position [750, 400, 775, 430] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 30 30 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 30 30 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[18" ".33 18.33 21.33 18.33 21.33 21.33 21.33 18.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[15.33 15.33 " "18.33 18.33 15.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[12.33 12.33 15.33 15.33 12.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[9.33 9.33 12.33 9.33 12.33 12.33 9.33 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register3" SID "3580" Ports [2, 1] Position [980, 520, 1015, 555] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,35,2,1,white,blue,0,140cc11c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 35 35 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 35 35 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[22.55" " 22.55 27.55 22.55 27.55 27.55 27.55 22.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[17.55 17.55 22" ".55 22.55 17.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[12.55 12.55 17.55 17.55 12.55 " "],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[7.55 7.55 12.55 7.55 12.55 12.55 7.55 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bla" "ck');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output" "',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register4" SID "3581" Ports [1, 1] Position [750, 450, 775, 480] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 30 30 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 30 30 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[18" ".33 18.33 21.33 18.33 21.33 21.33 21.33 18.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[15.33 15.33 " "18.33 18.33 15.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[12.33 12.33 15.33 15.33 12.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[9.33 9.33 12.33 9.33 12.33 12.33 9.33 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register5" SID "3582" Ports [1, 1] Position [750, 515, 775, 545] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 30 30 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 30 30 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[18" ".33 18.33 21.33 18.33 21.33 21.33 21.33 18.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[15.33 15.33 " "18.33 18.33 15.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[12.33 12.33 15.33 15.33 12.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[9.33 9.33 12.33 9.33 12.33 12.33 9.33 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "ADC I" SID "3583" Position [1290, 418, 1320, 432] IconDisplay "Port number" } Block { BlockType Outport Name "ADC Q" SID "3584" Position [1290, 468, 1320, 482] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "Avg RSSI" SID "3585" Position [1290, 533, 1320, 547] Port "3" IconDisplay "Port number" } Line { SrcBlock "IQ Valid" SrcPort 1 Points [35, 0] Branch { Points [0, -50] DstBlock "Register" DstPort 3 } Branch { DstBlock "Register1" DstPort 3 } } Line { SrcBlock "Rst" SrcPort 1 Points [105, 0] Branch { Points [0, 50] Branch { Points [0, 70] DstBlock "Register3" DstPort 2 } Branch { DstBlock "Register1" DstPort 2 } } Branch { DstBlock "Register" DstPort 2 } } Line { SrcBlock "Register5" SrcPort 1 DstBlock "Register3" DstPort 1 } Line { SrcBlock "Register4" SrcPort 1 DstBlock "Register1" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Register" DstPort 1 } Line { SrcBlock "RFB_RSSI" SrcPort 1 DstBlock "Register5" DstPort 1 } Line { SrcBlock "RF B RSSI Sum" SrcPort 1 DstBlock "Avg RSSI" DstPort 1 } Line { SrcBlock "Down Sample" SrcPort 1 DstBlock "RF B RSSI Sum" DstPort 1 } Line { SrcBlock "Register3" SrcPort 1 DstBlock "Down Sample" DstPort 1 } Line { SrcBlock "Register1" SrcPort 1 DstBlock "ADC Q" DstPort 1 } Line { SrcBlock "Register" SrcPort 1 DstBlock "ADC I" DstPort 1 } Line { SrcBlock "RFB_RX_Q" SrcPort 1 DstBlock "Register4" DstPort 1 } Line { SrcBlock "RFB_RX_I" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "RFB_G_RF" SrcPort 1 DstBlock "Delay4" DstPort 1 } Line { SrcBlock "RFB_G_BB" SrcPort 1 DstBlock "Delay5" DstPort 1 } Line { SrcBlock "Delay4" SrcPort 1 DstBlock "Goto12" DstPort 1 } Line { SrcBlock "Delay5" SrcPort 1 DstBlock "Goto13" DstPort 1 } Line { SrcBlock "Constant6" SrcPort 1 DstBlock "RFB_G_RF" DstPort 1 } Line { SrcBlock "Constant7" SrcPort 1 DstBlock "RFB_G_BB" DstPort 1 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "RFB_RX_I" DstPort 1 } Line { SrcBlock "Constant3" SrcPort 1 DstBlock "RFB_RSSI" DstPort 1 } Line { SrcBlock "Constant2" SrcPort 1 DstBlock "RFB_RX_Q" DstPort 1 } } } Block { BlockType SubSystem Name "RF C Inputs" SID "3586" Ports [2, 3] Position [695, 351, 800, 399] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "RF C Inputs" Location [138, 279, 2317, 1561] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Rst" SID "3587" Position [795, 418, 825, 432] IconDisplay "Port number" } Block { BlockType Inport Name "IQ Valid" SID "3588" Position [795, 478, 825, 492] Port "2" IconDisplay "Port number" } Block { BlockType Constant Name "Constant1" SID "3589" Position [570, 400, 600, 430] ZOrder -5 ShowName off Value "0" } Block { BlockType Constant Name "Constant2" SID "3590" Position [555, 715, 585, 745] ZOrder -5 ShowName off Value "2" } Block { BlockType Constant Name "Constant3" SID "3591" Position [570, 450, 600, 480] ZOrder -5 ShowName off Value "0" } Block { BlockType Constant Name "Constant4" SID "3592" Position [555, 770, 585, 800] ZOrder -5 ShowName off Value "5" } Block { BlockType Constant Name "Constant5" SID "3593" Position [570, 515, 600, 545] ZOrder -5 ShowName off Value "0" } Block { BlockType Reference Name "Delay1" SID "3594" Ports [1, 1] Position [835, 715, 865, 745] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "30,30,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 30 30 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 30 30 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 " "19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 1" "9.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');di" "sp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay2" SID "3595" Ports [1, 1] Position [835, 770, 865, 800] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "30,30,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 30 30 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 30 30 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 " "19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 1" "9.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');di" "sp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Down Sample" SID "3596" Ports [1, 1] Position [1050, 525, 1075, 555] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Down Sample" SourceType "Xilinx Down Sampler Block" infoedit "Hardware notes: Sample and Latency controls determine the hardware implementation. The cost i" "n hardware of different implementations varies considerably; press Help for details." sample_ratio "16" sample_phase "Last Value of Frame (most efficient)" en off latency "1" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "dsamp" sg_icon_stat "25,30,1,1,white,blue,0,40e65a2b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 30 30 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 30 30 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[18" ".33 18.33 21.33 18.33 21.33 21.33 21.33 18.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[15.33 15.33 " "18.33 18.33 15.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[12.33 12.33 15.33 15.33 12.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[9.33 9.33 12.33 9.33 12.33 12.33 9.33 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncol" "or('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\newline{\\fontsize{14pt}\\bf\\dow" "narrow}16','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Goto Name "Goto" SID "3597" Position [1005, 316, 1105, 334] ZOrder -10 ShowName off GotoTag "CS_ADC_I_RFC" TagVisibility "global" } Block { BlockType Goto Name "Goto1" SID "3598" Position [1005, 341, 1110, 359] ZOrder -10 ShowName off GotoTag "CS_ADC_Q_RFC" TagVisibility "global" } Block { BlockType Goto Name "Goto7" SID "3599" Position [1030, 720, 1125, 740] ZOrder -10 ShowName off GotoTag "RFC_AGC_G_RF" TagVisibility "global" } Block { BlockType Goto Name "Goto8" SID "3600" Position [1030, 775, 1125, 795] ZOrder -10 ShowName off GotoTag "RFC_AGC_G_BB" TagVisibility "global" } Block { BlockType SubSystem Name "RF C RSSI Sum" SID "3601" Ports [1, 1] Position [1145, 526, 1215, 554] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "RF C RSSI Sum" Location [138, 279, 2317, 1561] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "RSSI" SID "3602" Position [120, 48, 150, 62] IconDisplay "Port number" } Block { BlockType Reference Name "Down Sample6" SID "3603" Ports [1, 1] Position [225, 98, 250, 122] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Down Sample" SourceType "Xilinx Down Sampler Block" infoedit "Hardware notes: Sample and Latency controls determine the hardware implementation. The cost in hardw" "are of different implementations varies considerably; press Help for details." sample_ratio "16" sample_phase "Last Value of Frame (most efficient)" en off latency "1" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,356,300" block_type "dsamp" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,24,1,1,white,blue,0,40e65a2b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 24 24 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 24 24 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[15.33 15.33 " "18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[12.33 12.33 15.33 15.33 1" "2.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 1 1 ]);\npat" "ch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 0.973 ]);\nfprin" "tf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-1}\\ne" "wline ','texmode','on');\ncolor('black');disp(' \\newline{\\fontsize{14pt}\\bf\\downarrow}16','texmode','on');\nfp" "rintf('','COMMENT: end icon text');" } Block { BlockType From Name "From12" SID "3604" Position [25, 101, 180, 119] ShowName off CloseFcn "tagdialog Close" GotoTag "RX_GLOBAL_RESET" TagVisibility "global" } Block { BlockType SubSystem Name "Running Sum" SID "3605" Ports [2, 1] Position [300, 27, 365, 138] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Running Sum" Location [203, 179, 2137, 1473] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "RSSI" SID "3606" Position [500, 143, 530, 157] IconDisplay "Port number" } Block { BlockType Inport Name "reset" SID "3607" Position [240, 269, 270, 281] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "ASR" SID "3608" Ports [2, 1] Position [720, 165, 760, 200] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Addressable Shift Register" SourceType "Xilinx Addressable Shift Register Block" infoedit "Delay of configurable length. Any element in the delay line can be addressed and " " driven onto the output port.

Hardware notes: Implemented using SRL16s. If Virtex-4, Virt" "ex-II or Spartan-3 devices are used, multiple SRLC16s are cascaded together." infer_latency on depth "2" initVector "[0]" en off dbl_ovrd off use_behavioral_HDL off Optimization "Resource" xl_use_area off xl_area "[0,0,0,0,0,0,0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,356,359" block_type "addrsr" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,35,2,1,white,blue,0,a352fb33,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 35 35 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 35 35 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[22.55 22." "55 27.55 22.55 27.55 27.55 27.55 22.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[17.55 17.55 22.55 2" "2.55 17.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[12.55 12.55 17.55 17.55 12.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[7.55 7.55 12.55 7.55 12.55 12.55 7.55 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');por" "t_label('input',1,'d');\ncolor('black');port_label('input',2,'addr');\ncolor('black');port_label('output',1,'q')" ";\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Accumulator" SID "3609" Ports [2, 1] Position [895, 164, 930, 206] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Accumulator" SourceType "Xilinx Accumulator Block" infoedit "Adder or subtractor-based accumulator. Output type and binary point position match the input.

Hardware notes: When \"Reinitialize with input 'b' on reset\" is selected, the accumulator is forced to run " "at the system rate even if the input 'b' is running at a slower rate." operation "Add" n_bits "17" overflow "Flag as error" scale "1" rst on infoeditControl "reset for floating point data type must be asserted for a minimum of 2 cycles" hasbypass off en off latency "0" dbl_ovrd off msb_inp "100" msb "100" lsb "-100" use_behavioral_HDL on implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,356,457" block_type "accum" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,42,2,1,white,blue,0,6949434e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 42 42 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 42 42 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[26.55 26." "55 31.55 26.55 31.55 31.55 31.55 26.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[21.55 21.55 26.55 2" "6.55 21.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[16.55 16.55 21.55 21.55 16.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[11.55 11.55 16.55 11.55 16.55 16.55 11.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'b');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'" "\\bf+=b','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub" SID "3610" Ports [2, 1] Position [805, 146, 840, 199] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Subtraction" use_carryin off use_carryout off en off latency "0" precision "Full" arith_type "Unsigned" n_bits "10" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL off hw_selection "Fabric" pipelined off xl_use_area off xl_area "[0,0,0,0,0,0,0]" use_rpm "on" has_advanced_control "0" sggui_pos "283,438,356,344" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,53,2,1,white,blue,0,32e1f85f,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 53 53 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 53 53 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[31.55 31." "55 36.55 31.55 36.55 36.55 36.55 31.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[26.55 26.55 31.55 3" "1.55 26.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[21.55 21.55 26.55 26.55 21.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[16.55 16.55 21.55 16.55 21.55 21.55 16.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bf{a - b}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert7" SID "3611" Ports [1, 1] Position [980, 177, 1005, 193] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "17" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Saturate" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,461,334" block_type "convert" block_version "10.1.3" sg_icon_stat "25,16,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 16 16 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[10.22 10" ".22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[8.22 8.22 10.22 10.22" " 8.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('outpu" "t',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From1" SID "3612" Position [75, 215, 270, 235] ShowName off CloseFcn "tagdialog Close" GotoTag "regRx_RSSI_SUM_LEN_C" TagVisibility "global" } Block { BlockType Reference Name "Logical" SID "3613" Ports [2, 1] Position [510, 255, 535, 315] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,261" block_type "logical" block_version "10.1.3" sg_icon_stat "25,60,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 60 60 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 60 60 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[33.33 " "33.33 36.33 33.33 36.33 36.33 36.33 33.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[30.33 30.33 33.33" " 33.33 30.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[27.33 27.33 30.33 30.33 27.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[24.33 24.33 27.33 24.33 27.33 27.33 24.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor" "('black');disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Long Reset Gen" SID "3614" Ports [2, 1] Position [375, 250, 470, 285] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Long Reset Gen" Location [203, 179, 2137, 1473] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "duration" SID "3615" Position [60, 258, 90, 272] IconDisplay "Port number" } Block { BlockType Inport Name "reset_in" SID "3616" Position [60, 188, 90, 202] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Counter" SID "3617" Ports [2, 1] Position [405, 172, 455, 223] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited count" "er is implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "0" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "8" bin_pt "0" load_pin off rst on en on explicit_period "off" period "4" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,356,619" block_type "counter" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,51,2,1,white,blue,0,ae3608d6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 51 51 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 51 51 0 ]);\npatch([9.425 19.54 26.54 33.54 40.54 26.54 16.425 9.425 ],[32.7" "7 32.77 39.77 32.77 39.77 39.77 39.77 32.77 ],[1 1 1 ]);\npatch([16.425 26.54 19.54 9.425 16.425 ],[25.77 25.77 " "32.77 32.77 25.77 ],[0.931 0.946 0.973 ]);\npatch([9.425 19.54 26.54 16.425 9.425 ],[18.77 18.77 25.77 25.77 18." "77 ],[1 1 1 ]);\npatch([16.425 40.54 33.54 26.54 19.54 9.425 16.425 ],[11.77 11.77 18.77 11.77 18.77 18.77 11.77" " ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nc" "olor('black');port_label('input',1,'rst');\ncolor('black');port_label('input',2,'en');\n\ncolor('black');disp('{" "\\fontsize{14}\\bf++}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Relational" SID "3618" Ports [2, 1] Position [530, 188, 575, 232] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bfa = b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "S-R Latch" SID "3619" Ports [2, 1] Position [225, 182, 255, 233] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "S-R Latch" Location [160, 70, 1918, 1152] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "3620" Position [140, 103, 170, 117] IconDisplay "Port number" } Block { BlockType Inport Name "R" SID "3621" Position [140, 88, 170, 102] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "3622" Ports [0, 1] Position [195, 71, 210, 89] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,400,346" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "15,18,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11.22 " "13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 9.22 " "],[0.931 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([4.55 " "11.44 9.44 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "3623" Ports [3, 1] Position [255, 71, 300, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "3624" Position [325, 88, 355, 102] IconDisplay "Port number" } Line { SrcBlock "S" SrcPort 1 DstBlock "Register2" DstPort 3 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Register2" DstPort 1 } } } Block { BlockType Outport Name "reset_out" SID "3625" Position [465, 93, 495, 107] IconDisplay "Port number" } Line { SrcBlock "S-R Latch" SrcPort 1 Points [55, 0] Branch { Points [0, -110] DstBlock "reset_out" DstPort 1 } Branch { DstBlock "Counter" DstPort 2 } } Line { SrcBlock "duration" SrcPort 1 Points [420, 0] DstBlock "Relational" DstPort 2 } Line { SrcBlock "reset_in" SrcPort 1 DstBlock "S-R Latch" DstPort 1 } Line { SrcBlock "Counter" SrcPort 1 Points [0, 0] DstBlock "Relational" DstPort 1 } Line { SrcBlock "Relational" SrcPort 1 Points [0, -50; -210, 0] Branch { Points [-175, 0; 0, 60] DstBlock "S-R Latch" DstPort 2 } Branch { Points [0, 25] DstBlock "Counter" DstPort 1 } } } } Block { BlockType Reference Name "Register" SID "3626" Ports [2, 1] Position [615, 141, 655, 179] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,38,2,1,white,blue,0,140cc11c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 38 38 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 38 38 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[24.55 24." "55 29.55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[19.55 19.55 24.55 2" "4.55 19.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');por" "t_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'q');" "\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "avg" SID "3627" Position [1060, 178, 1090, 192] IconDisplay "Port number" } Line { SrcBlock "Convert7" SrcPort 1 DstBlock "avg" DstPort 1 } Line { SrcBlock "Long Reset Gen" SrcPort 1 DstBlock "Logical" DstPort 1 } Line { SrcBlock "reset" SrcPort 1 Points [60, 0] Branch { Points [0, 25] DstBlock "Logical" DstPort 2 } Branch { DstBlock "Long Reset Gen" DstPort 2 } } Line { SrcBlock "Logical" SrcPort 1 Points [40, 0] Branch { Points [265, 0; 0, -90] DstBlock "Accumulator" DstPort 2 } Branch { Points [0, -115] DstBlock "Register" DstPort 2 } } Line { SrcBlock "Accumulator" SrcPort 1 DstBlock "Convert7" DstPort 1 } Line { SrcBlock "RSSI" SrcPort 1 DstBlock "Register" DstPort 1 } Line { SrcBlock "From1" SrcPort 1 Points [60, 0] Branch { Points [0, 35] DstBlock "Long Reset Gen" DstPort 1 } Branch { Points [370, 0] DstBlock "ASR" DstPort 2 } } Line { SrcBlock "Register" SrcPort 1 Points [35, 0] Branch { DstBlock "AddSub" DstPort 1 } Branch { Points [0, 15] DstBlock "ASR" DstPort 1 } } Line { SrcBlock "AddSub" SrcPort 1 DstBlock "Accumulator" DstPort 1 } Line { SrcBlock "ASR" SrcPort 1 DstBlock "AddSub" DstPort 2 } Annotation { Name "This block impelemnts a variable-length running sum.\nFor a sum y(n) of the previous N samples of seq" "uence x(n), it implements\ny(n) = y(n-1) + x(n) - x(n-N)\nThis requires a careful reset procedure, where the ful" "l shift register\nis zerored out. Otherwise the feedback-based sum stops working." Position [289, 149] } } } Block { BlockType Outport Name "Sum" SID "3628" Position [470, 78, 500, 92] IconDisplay "Port number" } Line { SrcBlock "Running Sum" SrcPort 1 DstBlock "Sum" DstPort 1 } Line { SrcBlock "Down Sample6" SrcPort 1 DstBlock "Running Sum" DstPort 2 } Line { SrcBlock "RSSI" SrcPort 1 DstBlock "Running Sum" DstPort 1 } Line { SrcBlock "From12" SrcPort 1 DstBlock "Down Sample6" DstPort 1 } } } Block { BlockType Reference Name "RFC_G_BB" SID "3629" Ports [1, 1] Position [640, 778, 680, 792] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to" " Xilinx fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top l" "evel input ports." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "5" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "40,14,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9" ".22 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22" " 9.22 7.22 ],[0.985 0.979 0.895 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.985 0.979 0.89" "5 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprint" "f('','COMMENT: end icon text');" } Block { BlockType Reference Name "RFC_G_RF" SID "3630" Ports [1, 1] Position [640, 723, 680, 737] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to" " Xilinx fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top l" "evel input ports." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "40,14,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9" ".22 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22" " 9.22 7.22 ],[0.985 0.979 0.895 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.985 0.979 0.89" "5 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprint" "f('','COMMENT: end icon text');" } Block { BlockType Reference Name "RFC_RSSI" SID "3631" Ports [1, 1] Position [640, 523, 680, 537] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to" " Xilinx fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top l" "evel input ports." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "10" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "40,14,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9" ".22 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22" " 9.22 7.22 ],[0.985 0.979 0.895 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.985 0.979 0.89" "5 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprint" "f('','COMMENT: end icon text');" } Block { BlockType Reference Name "RFC_RX_I" SID "3632" Ports [1, 1] Position [640, 408, 680, 422] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to" " Xilinx fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top l" "evel input ports." gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "16" bin_pt "15" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "40,14,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9" ".22 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22" " 9.22 7.22 ],[0.985 0.979 0.895 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.985 0.979 0.89" "5 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprint" "f('','COMMENT: end icon text');" } Block { BlockType Reference Name "RFC_RX_Q" SID "3633" Ports [1, 1] Position [640, 458, 680, 472] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to" " Xilinx fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top l" "evel input ports." gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "16" bin_pt "15" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "40,14,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9" ".22 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22" " 9.22 7.22 ],[0.985 0.979 0.895 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.985 0.979 0.89" "5 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprint" "f('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register" SID "3634" Ports [3, 1] Position [980, 407, 1020, 443] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "40,36,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 36 36 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 36 36 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[23.55" " 23.55 28.55 23.55 28.55 28.55 28.55 23.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[18.55 18.55 23" ".55 23.55 18.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[13.55 13.55 18.55 18.55 13.55 " "],[1 1 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[8.55 8.55 13.55 8.55 13.55 13.55 8.55 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bla" "ck');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input'" ",3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('" "','COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "3635" Ports [3, 1] Position [980, 457, 1020, 493] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "40,36,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 36 36 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 36 36 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[23.55" " 23.55 28.55 23.55 28.55 28.55 28.55 23.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[18.55 18.55 23" ".55 23.55 18.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[13.55 13.55 18.55 18.55 13.55 " "],[1 1 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[8.55 8.55 13.55 8.55 13.55 13.55 8.55 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bla" "ck');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input'" ",3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('" "','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "3636" Ports [1, 1] Position [750, 400, 775, 430] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 30 30 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 30 30 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[18" ".33 18.33 21.33 18.33 21.33 21.33 21.33 18.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[15.33 15.33 " "18.33 18.33 15.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[12.33 12.33 15.33 15.33 12.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[9.33 9.33 12.33 9.33 12.33 12.33 9.33 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register3" SID "3637" Ports [2, 1] Position [980, 520, 1015, 555] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,35,2,1,white,blue,0,140cc11c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 35 35 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 35 35 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[22.55" " 22.55 27.55 22.55 27.55 27.55 27.55 22.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[17.55 17.55 22" ".55 22.55 17.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[12.55 12.55 17.55 17.55 12.55 " "],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[7.55 7.55 12.55 7.55 12.55 12.55 7.55 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bla" "ck');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output" "',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register4" SID "3638" Ports [1, 1] Position [750, 450, 775, 480] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 30 30 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 30 30 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[18" ".33 18.33 21.33 18.33 21.33 21.33 21.33 18.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[15.33 15.33 " "18.33 18.33 15.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[12.33 12.33 15.33 15.33 12.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[9.33 9.33 12.33 9.33 12.33 12.33 9.33 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register5" SID "3639" Ports [1, 1] Position [750, 515, 775, 545] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 30 30 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 30 30 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[18" ".33 18.33 21.33 18.33 21.33 21.33 21.33 18.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[15.33 15.33 " "18.33 18.33 15.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[12.33 12.33 15.33 15.33 12.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[9.33 9.33 12.33 9.33 12.33 12.33 9.33 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "ADC I" SID "3640" Position [1290, 418, 1320, 432] IconDisplay "Port number" } Block { BlockType Outport Name "ADC Q" SID "3641" Position [1290, 468, 1320, 482] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "Avg RSSI" SID "3642" Position [1290, 533, 1320, 547] Port "3" IconDisplay "Port number" } Line { SrcBlock "Constant4" SrcPort 1 DstBlock "RFC_G_BB" DstPort 1 } Line { SrcBlock "Constant2" SrcPort 1 DstBlock "RFC_G_RF" DstPort 1 } Line { SrcBlock "Delay2" SrcPort 1 DstBlock "Goto8" DstPort 1 } Line { SrcBlock "Delay1" SrcPort 1 DstBlock "Goto7" DstPort 1 } Line { SrcBlock "RFC_G_BB" SrcPort 1 DstBlock "Delay2" DstPort 1 } Line { SrcBlock "RFC_G_RF" SrcPort 1 DstBlock "Delay1" DstPort 1 } Line { SrcBlock "IQ Valid" SrcPort 1 Points [35, 0] Branch { Points [0, -50] DstBlock "Register" DstPort 3 } Branch { DstBlock "Register1" DstPort 3 } } Line { SrcBlock "Rst" SrcPort 1 Points [105, 0] Branch { Points [0, 50] Branch { Points [0, 70] DstBlock "Register3" DstPort 2 } Branch { DstBlock "Register1" DstPort 2 } } Branch { DstBlock "Register" DstPort 2 } } Line { SrcBlock "Register5" SrcPort 1 DstBlock "Register3" DstPort 1 } Line { SrcBlock "Register4" SrcPort 1 Points [120, 0] Branch { DstBlock "Register1" DstPort 1 } Branch { Points [0, -115] DstBlock "Goto1" DstPort 1 } } Line { SrcBlock "Register2" SrcPort 1 Points [110, 0] Branch { DstBlock "Register" DstPort 1 } Branch { Points [0, -90] DstBlock "Goto" DstPort 1 } } Line { SrcBlock "RFC_RSSI" SrcPort 1 DstBlock "Register5" DstPort 1 } Line { SrcBlock "RF C RSSI Sum" SrcPort 1 DstBlock "Avg RSSI" DstPort 1 } Line { SrcBlock "Down Sample" SrcPort 1 DstBlock "RF C RSSI Sum" DstPort 1 } Line { SrcBlock "Register3" SrcPort 1 DstBlock "Down Sample" DstPort 1 } Line { SrcBlock "Register1" SrcPort 1 DstBlock "ADC Q" DstPort 1 } Line { SrcBlock "Register" SrcPort 1 DstBlock "ADC I" DstPort 1 } Line { SrcBlock "RFC_RX_Q" SrcPort 1 DstBlock "Register4" DstPort 1 } Line { SrcBlock "RFC_RX_I" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "Constant3" SrcPort 1 DstBlock "RFC_RX_Q" DstPort 1 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "RFC_RX_I" DstPort 1 } Line { SrcBlock "Constant5" SrcPort 1 DstBlock "RFC_RSSI" DstPort 1 } } } Block { BlockType SubSystem Name "RF D Inputs" SID "3643" Ports [2, 3] Position [695, 436, 800, 484] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "RF D Inputs" Location [138, 279, 2317, 1561] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Rst" SID "3644" Position [795, 418, 825, 432] IconDisplay "Port number" } Block { BlockType Inport Name "IQ Valid" SID "3645" Position [795, 478, 825, 492] Port "2" IconDisplay "Port number" } Block { BlockType Constant Name "Constant1" SID "3646" Position [560, 400, 590, 430] ZOrder -5 ShowName off Value "0" } Block { BlockType Constant Name "Constant2" SID "3647" Position [560, 450, 590, 480] ZOrder -5 ShowName off Value "0" } Block { BlockType Constant Name "Constant3" SID "3648" Position [560, 515, 590, 545] ZOrder -5 ShowName off Value "0" } Block { BlockType Constant Name "Constant6" SID "3649" Position [560, 655, 590, 685] ZOrder -5 ShowName off Value "2" } Block { BlockType Constant Name "Constant7" SID "3650" Position [560, 710, 590, 740] ZOrder -5 ShowName off Value "5" } Block { BlockType Reference Name "Delay4" SID "3651" Ports [1, 1] Position [840, 655, 870, 685] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "30,30,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 30 30 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 30 30 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 " "19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 1" "9.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');di" "sp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay5" SID "3652" Ports [1, 1] Position [840, 710, 870, 740] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "30,30,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 30 30 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 30 30 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 " "19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 1" "9.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');di" "sp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Down Sample" SID "3653" Ports [1, 1] Position [1050, 525, 1075, 555] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Down Sample" SourceType "Xilinx Down Sampler Block" infoedit "Hardware notes: Sample and Latency controls determine the hardware implementation. The cost i" "n hardware of different implementations varies considerably; press Help for details." sample_ratio "16" sample_phase "Last Value of Frame (most efficient)" en off latency "1" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "dsamp" sg_icon_stat "25,30,1,1,white,blue,0,40e65a2b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 30 30 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 30 30 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[18" ".33 18.33 21.33 18.33 21.33 21.33 21.33 18.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[15.33 15.33 " "18.33 18.33 15.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[12.33 12.33 15.33 15.33 12.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[9.33 9.33 12.33 9.33 12.33 12.33 9.33 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncol" "or('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\newline{\\fontsize{14pt}\\bf\\dow" "narrow}16','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Goto Name "Goto12" SID "3654" Position [1035, 660, 1130, 680] ZOrder -10 ShowName off GotoTag "RFD_AGC_G_RF" TagVisibility "global" } Block { BlockType Goto Name "Goto13" SID "3655" Position [1035, 715, 1130, 735] ZOrder -10 ShowName off GotoTag "RFD_AGC_G_BB" TagVisibility "global" } Block { BlockType SubSystem Name "RF D RSSI Sum" SID "3656" Ports [1, 1] Position [1145, 526, 1215, 554] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "RF D RSSI Sum" Location [138, 279, 2317, 1561] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "RSSI" SID "3657" Position [120, 48, 150, 62] IconDisplay "Port number" } Block { BlockType Reference Name "Down Sample6" SID "3658" Ports [1, 1] Position [225, 98, 250, 122] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Down Sample" SourceType "Xilinx Down Sampler Block" infoedit "Hardware notes: Sample and Latency controls determine the hardware implementation. The cost in hardw" "are of different implementations varies considerably; press Help for details." sample_ratio "16" sample_phase "Last Value of Frame (most efficient)" en off latency "1" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,356,300" block_type "dsamp" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,24,1,1,white,blue,0,40e65a2b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 24 24 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 24 24 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[15.33 15.33 " "18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[12.33 12.33 15.33 15.33 1" "2.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 1 1 ]);\npat" "ch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 0.973 ]);\nfprin" "tf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-1}\\ne" "wline ','texmode','on');\ncolor('black');disp(' \\newline{\\fontsize{14pt}\\bf\\downarrow}16','texmode','on');\nfp" "rintf('','COMMENT: end icon text');" } Block { BlockType From Name "From12" SID "3659" Position [25, 101, 180, 119] ShowName off CloseFcn "tagdialog Close" GotoTag "RX_GLOBAL_RESET" TagVisibility "global" } Block { BlockType SubSystem Name "Running Sum" SID "3660" Ports [2, 1] Position [300, 27, 365, 138] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Running Sum" Location [203, 179, 2137, 1473] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "RSSI" SID "3661" Position [500, 143, 530, 157] IconDisplay "Port number" } Block { BlockType Inport Name "reset" SID "3662" Position [240, 269, 270, 281] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "ASR" SID "3663" Ports [2, 1] Position [720, 165, 760, 200] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Addressable Shift Register" SourceType "Xilinx Addressable Shift Register Block" infoedit "Delay of configurable length. Any element in the delay line can be addressed and " " driven onto the output port.

Hardware notes: Implemented using SRL16s. If Virtex-4, Virt" "ex-II or Spartan-3 devices are used, multiple SRLC16s are cascaded together." infer_latency on depth "2" initVector "[0]" en off dbl_ovrd off use_behavioral_HDL off Optimization "Resource" xl_use_area off xl_area "[0,0,0,0,0,0,0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,356,359" block_type "addrsr" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,35,2,1,white,blue,0,a352fb33,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 35 35 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 35 35 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[22.55 22." "55 27.55 22.55 27.55 27.55 27.55 22.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[17.55 17.55 22.55 2" "2.55 17.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[12.55 12.55 17.55 17.55 12.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[7.55 7.55 12.55 7.55 12.55 12.55 7.55 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');por" "t_label('input',1,'d');\ncolor('black');port_label('input',2,'addr');\ncolor('black');port_label('output',1,'q')" ";\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Accumulator" SID "3664" Ports [2, 1] Position [895, 164, 930, 206] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Accumulator" SourceType "Xilinx Accumulator Block" infoedit "Adder or subtractor-based accumulator. Output type and binary point position match the input.

Hardware notes: When \"Reinitialize with input 'b' on reset\" is selected, the accumulator is forced to run " "at the system rate even if the input 'b' is running at a slower rate." operation "Add" n_bits "17" overflow "Flag as error" scale "1" rst on infoeditControl "reset for floating point data type must be asserted for a minimum of 2 cycles" hasbypass off en off latency "0" dbl_ovrd off msb_inp "100" msb "100" lsb "-100" use_behavioral_HDL on implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,356,457" block_type "accum" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,42,2,1,white,blue,0,6949434e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 42 42 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 42 42 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[26.55 26." "55 31.55 26.55 31.55 31.55 31.55 26.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[21.55 21.55 26.55 2" "6.55 21.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[16.55 16.55 21.55 21.55 16.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[11.55 11.55 16.55 11.55 16.55 16.55 11.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'b');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'" "\\bf+=b','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub" SID "3665" Ports [2, 1] Position [805, 146, 840, 199] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Subtraction" use_carryin off use_carryout off en off latency "0" precision "Full" arith_type "Unsigned" n_bits "10" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL off hw_selection "Fabric" pipelined off xl_use_area off xl_area "[0,0,0,0,0,0,0]" use_rpm "on" has_advanced_control "0" sggui_pos "283,438,356,344" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,53,2,1,white,blue,0,32e1f85f,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 53 53 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 53 53 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[31.55 31." "55 36.55 31.55 36.55 36.55 36.55 31.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[26.55 26.55 31.55 3" "1.55 26.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[21.55 21.55 26.55 26.55 21.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[16.55 16.55 21.55 16.55 21.55 21.55 16.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bf{a - b}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert7" SID "3666" Ports [1, 1] Position [980, 177, 1005, 193] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "17" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Saturate" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,461,334" block_type "convert" block_version "10.1.3" sg_icon_stat "25,16,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 16 16 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[10.22 10" ".22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[8.22 8.22 10.22 10.22" " 8.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('outpu" "t',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From1" SID "3667" Position [75, 215, 270, 235] ShowName off CloseFcn "tagdialog Close" GotoTag "regRx_RSSI_SUM_LEN_D" TagVisibility "global" } Block { BlockType Reference Name "Logical" SID "3668" Ports [2, 1] Position [510, 255, 535, 315] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,261" block_type "logical" block_version "10.1.3" sg_icon_stat "25,60,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 60 60 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 60 60 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[33.33 " "33.33 36.33 33.33 36.33 36.33 36.33 33.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[30.33 30.33 33.33" " 33.33 30.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[27.33 27.33 30.33 30.33 27.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[24.33 24.33 27.33 24.33 27.33 27.33 24.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor" "('black');disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Long Reset Gen" SID "3669" Ports [2, 1] Position [375, 250, 470, 285] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Long Reset Gen" Location [203, 179, 2137, 1473] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "duration" SID "3670" Position [60, 258, 90, 272] IconDisplay "Port number" } Block { BlockType Inport Name "reset_in" SID "3671" Position [60, 188, 90, 202] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Counter" SID "3672" Ports [2, 1] Position [405, 172, 455, 223] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited count" "er is implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "0" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "8" bin_pt "0" load_pin off rst on en on explicit_period "off" period "4" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,356,619" block_type "counter" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,51,2,1,white,blue,0,ae3608d6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 51 51 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 51 51 0 ]);\npatch([9.425 19.54 26.54 33.54 40.54 26.54 16.425 9.425 ],[32.7" "7 32.77 39.77 32.77 39.77 39.77 39.77 32.77 ],[1 1 1 ]);\npatch([16.425 26.54 19.54 9.425 16.425 ],[25.77 25.77 " "32.77 32.77 25.77 ],[0.931 0.946 0.973 ]);\npatch([9.425 19.54 26.54 16.425 9.425 ],[18.77 18.77 25.77 25.77 18." "77 ],[1 1 1 ]);\npatch([16.425 40.54 33.54 26.54 19.54 9.425 16.425 ],[11.77 11.77 18.77 11.77 18.77 18.77 11.77" " ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nc" "olor('black');port_label('input',1,'rst');\ncolor('black');port_label('input',2,'en');\n\ncolor('black');disp('{" "\\fontsize{14}\\bf++}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Relational" SID "3673" Ports [2, 1] Position [530, 188, 575, 232] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bfa = b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "S-R Latch" SID "3674" Ports [2, 1] Position [225, 182, 255, 233] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "S-R Latch" Location [160, 70, 1918, 1152] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "3675" Position [140, 103, 170, 117] IconDisplay "Port number" } Block { BlockType Inport Name "R" SID "3676" Position [140, 88, 170, 102] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "3677" Ports [0, 1] Position [195, 71, 210, 89] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,400,346" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "15,18,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11.22 " "13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 9.22 " "],[0.931 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([4.55 " "11.44 9.44 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "3678" Ports [3, 1] Position [255, 71, 300, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "3679" Position [325, 88, 355, 102] IconDisplay "Port number" } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "S" SrcPort 1 DstBlock "Register2" DstPort 3 } } } Block { BlockType Outport Name "reset_out" SID "3680" Position [465, 93, 495, 107] IconDisplay "Port number" } Line { SrcBlock "Relational" SrcPort 1 Points [0, -50; -210, 0] Branch { Points [0, 25] DstBlock "Counter" DstPort 1 } Branch { Points [-175, 0; 0, 60] DstBlock "S-R Latch" DstPort 2 } } Line { SrcBlock "Counter" SrcPort 1 Points [0, 0] DstBlock "Relational" DstPort 1 } Line { SrcBlock "reset_in" SrcPort 1 DstBlock "S-R Latch" DstPort 1 } Line { SrcBlock "duration" SrcPort 1 Points [420, 0] DstBlock "Relational" DstPort 2 } Line { SrcBlock "S-R Latch" SrcPort 1 Points [55, 0] Branch { DstBlock "Counter" DstPort 2 } Branch { Points [0, -110] DstBlock "reset_out" DstPort 1 } } } } Block { BlockType Reference Name "Register" SID "3681" Ports [2, 1] Position [615, 141, 655, 179] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,38,2,1,white,blue,0,140cc11c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 38 38 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 38 38 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[24.55 24." "55 29.55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[19.55 19.55 24.55 2" "4.55 19.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');por" "t_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'q');" "\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "avg" SID "3682" Position [1060, 178, 1090, 192] IconDisplay "Port number" } Line { SrcBlock "ASR" SrcPort 1 DstBlock "AddSub" DstPort 2 } Line { SrcBlock "AddSub" SrcPort 1 DstBlock "Accumulator" DstPort 1 } Line { SrcBlock "Register" SrcPort 1 Points [35, 0] Branch { Points [0, 15] DstBlock "ASR" DstPort 1 } Branch { DstBlock "AddSub" DstPort 1 } } Line { SrcBlock "From1" SrcPort 1 Points [60, 0] Branch { Points [370, 0] DstBlock "ASR" DstPort 2 } Branch { Points [0, 35] DstBlock "Long Reset Gen" DstPort 1 } } Line { SrcBlock "RSSI" SrcPort 1 DstBlock "Register" DstPort 1 } Line { SrcBlock "Accumulator" SrcPort 1 DstBlock "Convert7" DstPort 1 } Line { SrcBlock "Logical" SrcPort 1 Points [40, 0] Branch { Points [0, -115] DstBlock "Register" DstPort 2 } Branch { Points [265, 0; 0, -90] DstBlock "Accumulator" DstPort 2 } } Line { SrcBlock "reset" SrcPort 1 Points [60, 0] Branch { DstBlock "Long Reset Gen" DstPort 2 } Branch { Points [0, 25] DstBlock "Logical" DstPort 2 } } Line { SrcBlock "Long Reset Gen" SrcPort 1 DstBlock "Logical" DstPort 1 } Line { SrcBlock "Convert7" SrcPort 1 DstBlock "avg" DstPort 1 } Annotation { Name "This block impelemnts a variable-length running sum.\nFor a sum y(n) of the previous N samples of seq" "uence x(n), it implements\ny(n) = y(n-1) + x(n) - x(n-N)\nThis requires a careful reset procedure, where the ful" "l shift register\nis zerored out. Otherwise the feedback-based sum stops working." Position [289, 149] } } } Block { BlockType Outport Name "Sum" SID "3683" Position [470, 78, 500, 92] IconDisplay "Port number" } Line { SrcBlock "From12" SrcPort 1 DstBlock "Down Sample6" DstPort 1 } Line { SrcBlock "RSSI" SrcPort 1 DstBlock "Running Sum" DstPort 1 } Line { SrcBlock "Down Sample6" SrcPort 1 DstBlock "Running Sum" DstPort 2 } Line { SrcBlock "Running Sum" SrcPort 1 DstBlock "Sum" DstPort 1 } } } Block { BlockType Reference Name "RFD_G_BB" SID "3684" Ports [1, 1] Position [645, 718, 685, 732] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to" " Xilinx fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top l" "evel input ports." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "5" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "40,14,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9" ".22 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22" " 9.22 7.22 ],[0.985 0.979 0.895 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.985 0.979 0.89" "5 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprint" "f('','COMMENT: end icon text');" } Block { BlockType Reference Name "RFD_G_RF" SID "3685" Ports [1, 1] Position [645, 663, 685, 677] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to" " Xilinx fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top l" "evel input ports." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "40,14,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9" ".22 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22" " 9.22 7.22 ],[0.985 0.979 0.895 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.985 0.979 0.89" "5 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprint" "f('','COMMENT: end icon text');" } Block { BlockType Reference Name "RFD_RSSI" SID "3686" Ports [1, 1] Position [645, 523, 685, 537] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to" " Xilinx fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top l" "evel input ports." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "10" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "40,14,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9" ".22 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22" " 9.22 7.22 ],[0.985 0.979 0.895 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.985 0.979 0.89" "5 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprint" "f('','COMMENT: end icon text');" } Block { BlockType Reference Name "RFD_RX_I" SID "3687" Ports [1, 1] Position [645, 408, 685, 422] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to" " Xilinx fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top l" "evel input ports." gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "16" bin_pt "15" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "40,14,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9" ".22 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22" " 9.22 7.22 ],[0.985 0.979 0.895 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.985 0.979 0.89" "5 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprint" "f('','COMMENT: end icon text');" } Block { BlockType Reference Name "RFD_RX_Q" SID "3688" Ports [1, 1] Position [645, 458, 685, 472] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to" " Xilinx fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top l" "evel input ports." gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "16" bin_pt "15" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "40,14,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9" ".22 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22" " 9.22 7.22 ],[0.985 0.979 0.895 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.985 0.979 0.89" "5 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprint" "f('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register" SID "3689" Ports [3, 1] Position [980, 407, 1020, 443] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "40,36,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 36 36 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 36 36 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[23.55" " 23.55 28.55 23.55 28.55 28.55 28.55 23.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[18.55 18.55 23" ".55 23.55 18.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[13.55 13.55 18.55 18.55 13.55 " "],[1 1 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[8.55 8.55 13.55 8.55 13.55 13.55 8.55 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bla" "ck');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input'" ",3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('" "','COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "3690" Ports [3, 1] Position [980, 457, 1020, 493] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "40,36,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 36 36 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 36 36 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[23.55" " 23.55 28.55 23.55 28.55 28.55 28.55 23.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[18.55 18.55 23" ".55 23.55 18.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[13.55 13.55 18.55 18.55 13.55 " "],[1 1 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[8.55 8.55 13.55 8.55 13.55 13.55 8.55 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bla" "ck');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input'" ",3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('" "','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "3691" Ports [1, 1] Position [750, 400, 775, 430] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 30 30 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 30 30 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[18" ".33 18.33 21.33 18.33 21.33 21.33 21.33 18.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[15.33 15.33 " "18.33 18.33 15.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[12.33 12.33 15.33 15.33 12.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[9.33 9.33 12.33 9.33 12.33 12.33 9.33 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register3" SID "3692" Ports [2, 1] Position [980, 520, 1015, 555] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,35,2,1,white,blue,0,140cc11c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 35 35 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 35 35 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[22.55" " 22.55 27.55 22.55 27.55 27.55 27.55 22.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[17.55 17.55 22" ".55 22.55 17.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[12.55 12.55 17.55 17.55 12.55 " "],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[7.55 7.55 12.55 7.55 12.55 12.55 7.55 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bla" "ck');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output" "',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register4" SID "3693" Ports [1, 1] Position [750, 450, 775, 480] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 30 30 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 30 30 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[18" ".33 18.33 21.33 18.33 21.33 21.33 21.33 18.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[15.33 15.33 " "18.33 18.33 15.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[12.33 12.33 15.33 15.33 12.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[9.33 9.33 12.33 9.33 12.33 12.33 9.33 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register5" SID "3694" Ports [1, 1] Position [750, 515, 775, 545] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 30 30 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 30 30 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[18" ".33 18.33 21.33 18.33 21.33 21.33 21.33 18.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[15.33 15.33 " "18.33 18.33 15.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[12.33 12.33 15.33 15.33 12.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[9.33 9.33 12.33 9.33 12.33 12.33 9.33 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "ADC I" SID "3695" Position [1290, 418, 1320, 432] IconDisplay "Port number" } Block { BlockType Outport Name "ADC Q" SID "3696" Position [1290, 468, 1320, 482] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "Avg RSSI" SID "3697" Position [1290, 533, 1320, 547] Port "3" IconDisplay "Port number" } Line { SrcBlock "Constant7" SrcPort 1 DstBlock "RFD_G_BB" DstPort 1 } Line { SrcBlock "Constant6" SrcPort 1 DstBlock "RFD_G_RF" DstPort 1 } Line { SrcBlock "Delay5" SrcPort 1 DstBlock "Goto13" DstPort 1 } Line { SrcBlock "Delay4" SrcPort 1 DstBlock "Goto12" DstPort 1 } Line { SrcBlock "RFD_G_BB" SrcPort 1 DstBlock "Delay5" DstPort 1 } Line { SrcBlock "RFD_G_RF" SrcPort 1 DstBlock "Delay4" DstPort 1 } Line { SrcBlock "RFD_RX_I" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "RFD_RX_Q" SrcPort 1 DstBlock "Register4" DstPort 1 } Line { SrcBlock "Register" SrcPort 1 DstBlock "ADC I" DstPort 1 } Line { SrcBlock "Register1" SrcPort 1 DstBlock "ADC Q" DstPort 1 } Line { SrcBlock "Register3" SrcPort 1 DstBlock "Down Sample" DstPort 1 } Line { SrcBlock "Down Sample" SrcPort 1 DstBlock "RF D RSSI Sum" DstPort 1 } Line { SrcBlock "RF D RSSI Sum" SrcPort 1 DstBlock "Avg RSSI" DstPort 1 } Line { SrcBlock "RFD_RSSI" SrcPort 1 DstBlock "Register5" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Register" DstPort 1 } Line { SrcBlock "Register4" SrcPort 1 DstBlock "Register1" DstPort 1 } Line { SrcBlock "Register5" SrcPort 1 DstBlock "Register3" DstPort 1 } Line { SrcBlock "Rst" SrcPort 1 Points [105, 0] Branch { DstBlock "Register" DstPort 2 } Branch { Points [0, 50] Branch { DstBlock "Register1" DstPort 2 } Branch { Points [0, 70] DstBlock "Register3" DstPort 2 } } } Line { SrcBlock "IQ Valid" SrcPort 1 Points [35, 0] Branch { DstBlock "Register1" DstPort 3 } Branch { Points [0, -50] DstBlock "Register" DstPort 3 } } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "RFD_RX_I" DstPort 1 } Line { SrcBlock "Constant2" SrcPort 1 DstBlock "RFD_RX_Q" DstPort 1 } Line { SrcBlock "Constant3" SrcPort 1 DstBlock "RFD_RSSI" DstPort 1 } } } Block { BlockType SubSystem Name "RSSI Clock Gen" SID "3698" Ports [0, 1] Position [315, 628, 365, 672] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "RSSI Clock Gen" Location [18, 1100, 370, 1311] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Reference Name "1LSB+3" SID "3699" Ports [1, 1] Position [440, 316, 475, 334] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "3" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "35,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 18 18 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[1" "1.22 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[9.22 9.22 " "11.22 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[7.22 7.22 9.22 9.22 7.22 ],[" "1 1 1 ]);\npatch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black" "');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "RSSI Clock\nGenerator" SID "3700" Ports [0, 1] Position [340, 312, 385, 338] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited co" "unter is implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "Inf" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "4" bin_pt "0" load_pin off rst off en off explicit_period "on" period "1" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,356,630" block_type "counter" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,26,0,1,white,blue,0,7ac47ef5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 26 26 0 ]);\npatch([15.325 19.66 22.66 25.66 28.66 22.66 18.325 15.325 ]" ",[16.33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([18.325 22.66 19.66 15.325 18.325 ],[13.3" "3 13.33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([15.325 19.66 22.66 18.325 15.325 ],[10.33 10.33 13.3" "3 13.33 10.33 ],[1 1 1 ]);\npatch([18.325 28.66 25.66 22.66 19.66 15.325 18.325 ],[7.33 7.33 10.33 7.33 10.33 1" "0.33 7.33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon " "text');\n\ncolor('black');disp('{\\fontsize{14}\\bf++}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Clk" SID "3701" Position [540, 318, 570, 332] IconDisplay "Port number" } Line { SrcBlock "RSSI Clock\nGenerator" SrcPort 1 DstBlock "1LSB+3" DstPort 1 } Line { SrcBlock "1LSB+3" SrcPort 1 DstBlock "Clk" DstPort 1 } } } Block { BlockType Reference Name "RSSI_ADC_CLK" SID "3702" Ports [1, 1] Position [490, 643, 530, 657] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, o" "r fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarded, depen" "ding on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "8.2" sg_icon_stat "40,14,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.95 0.93 0.65" " ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9.22 9.22 11." "22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0." "985 0.979 0.895 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([17.55 24" ".44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.985 0.979 0.895 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ');\ncolor" "('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "RX_IQ_SAMP_CE" SID "3703" Ports [1, 1] Position [145, 198, 185, 212] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to Xilinx" " fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top level input p" "orts." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "40,14,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.95 0.93 0.65" " ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9.22 9.22 11." "22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0." "985 0.979 0.895 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([17.55 24" ".44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.985 0.979 0.895 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'\\fontsize{" "11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "RX_SIGS_INVALID" SID "3704" Ports [1, 1] Position [330, 83, 370, 97] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to Xilinx" " fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top level input p" "orts." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "40,14,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.95 0.93 0.65" " ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9.22 9.22 11." "22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0." "985 0.979 0.895 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([17.55 24" ".44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.985 0.979 0.895 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'\\fontsize{" "11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register3" SID "3705" Ports [1, 1] Position [245, 192, 275, 218] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[16.33 16.33 " "19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 13.33 16.33 16.33" " 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ])" ";\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label" "('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprint" "f('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register6" SID "3706" Ports [1, 1] Position [435, 75, 460, 105] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 30 30 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[18.33 18.33 21" ".33 18.33 21.33 21.33 21.33 18.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[15.33 15.33 18.33 18.33 15.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[12.33 12.33 15.33 15.33 12.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[9.33 9.33 12.33 9.33 12.33 12.33 9.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Terminator Name "Terminator" SID "3707" Position [585, 640, 605, 660] ShowName off } Block { BlockType SubSystem Name "negedge1" SID "3708" Ports [1, 1] Position [315, 198, 360, 212] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "negedge1" Location [384, 656, 940, 879] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "3709" Position [265, 183, 295, 197] IconDisplay "Port number" } Block { BlockType Reference Name "Delay" SID "3710" Ports [1, 1] Position [425, 153, 460, 177] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p. If register retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ]" ",[15.33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.3" "3 12.33 15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 " "12.33 9.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\n\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "3711" Ports [1, 1] Position [485, 181, 510, 199] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.2" "2 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 " "11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);" "\npatch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('no" "t');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "3712" Ports [2, 1] Position [540, 151, 585, 204] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,53,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 53 53 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 53 53 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[32." "66 32.66 38.66 32.66 38.66 38.66 38.66 32.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[26.66 26.66 3" "2.66 32.66 26.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[20.66 20.66 26.66 26.66 20.66 " "],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[14.66 14.66 20.66 14.66 20.66 20.66 14.66 ],[0" ".931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n" "color('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "3713" Position [610, 173, 640, 187] IconDisplay "Port number" } Line { SrcBlock "D" SrcPort 1 Points [85, 0] Branch { Points [0, -25] DstBlock "Delay" DstPort 1 } Branch { DstBlock "Inverter" DstPort 1 } } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "Delay" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical1" DstPort 2 } } } Block { BlockType Outport Name "ADC I" SID "3714" Position [1490, 248, 1520, 262] IconDisplay "Port number" } Block { BlockType Outport Name "ADC Q" SID "3715" Position [1490, 353, 1520, 367] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "IQ Valid" SID "3716" Position [1490, 143, 1520, 157] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "RSSI" SID "3717" Position [1490, 458, 1520, 472] Port "4" IconDisplay "Port number" } Line { SrcBlock "RSSI_ADC_CLK" SrcPort 1 DstBlock "Terminator" DstPort 1 } Line { SrcBlock "RSSI Clock Gen" SrcPort 1 DstBlock "RSSI_ADC_CLK" DstPort 1 } Line { SrcBlock "Constant" SrcPort 1 DstBlock "RX_SIGS_INVALID" DstPort 1 } Line { SrcBlock "RX_SIGS_INVALID" SrcPort 1 DstBlock "Register6" DstPort 1 } Line { SrcBlock "Logical" SrcPort 1 Points [80, 0] Branch { DstBlock "Goto6" DstPort 1 } Branch { Points [0, 105] Branch { DstBlock "RF A Inputs" DstPort 1 } Branch { Points [0, 85] Branch { DstBlock "RF B Inputs" DstPort 1 } Branch { Points [0, 100] Branch { DstBlock "RF C Inputs" DstPort 1 } Branch { Points [0, 85] DstBlock "RF D Inputs" DstPort 1 } } } } } Line { SrcBlock "Register6" SrcPort 1 DstBlock "Logical" DstPort 2 } Line { SrcBlock "From1" SrcPort 1 DstBlock "Logical" DstPort 1 } Line { SrcBlock "Bus\nCreator" SrcPort 1 DstBlock "ADC I" DstPort 1 } Line { SrcBlock "Bus\nCreator1" SrcPort 1 DstBlock "ADC Q" DstPort 1 } Line { SrcBlock "Bus\nCreator2" SrcPort 1 DstBlock "RSSI" DstPort 1 } Line { Name "RFA_I" Labels [0, 0] SrcBlock "From2" SrcPort 1 DstBlock "Bus\nCreator" DstPort 1 } Line { Name "RFB_I" Labels [0, 0] SrcBlock "From4" SrcPort 1 DstBlock "Bus\nCreator" DstPort 2 } Line { Name "RFA_Q" Labels [0, 0] SrcBlock "From3" SrcPort 1 DstBlock "Bus\nCreator1" DstPort 1 } Line { Name "RFB_Q" Labels [0, 0] SrcBlock "From5" SrcPort 1 DstBlock "Bus\nCreator1" DstPort 2 } Line { Name "RFA_RSSI" Labels [0, 0] SrcBlock "From6" SrcPort 1 DstBlock "Bus\nCreator2" DstPort 1 } Line { Name "RFB_RSSI" Labels [0, 0] SrcBlock "From7" SrcPort 1 DstBlock "Bus\nCreator2" DstPort 2 } Line { SrcBlock "AGC_DONE" SrcPort 1 DstBlock "Delay3" DstPort 1 } Line { SrcBlock "Delay3" SrcPort 1 DstBlock "Goto9" DstPort 1 } Line { SrcBlock "Bus\nCreator3" SrcPort 1 DstBlock "IQ Valid" DstPort 1 } Line { SrcBlock "Convert2" SrcPort 1 Points [10, 0] Branch { Points [0, -50] DstBlock "Goto2" DstPort 1 } Branch { Points [190, 0] Branch { DstBlock "RF A Inputs" DstPort 2 } Branch { Points [0, -85; 750, 0] Branch { DstBlock "Bus\nCreator3" DstPort 1 } Branch { Points [0, 20] Branch { DstBlock "Bus\nCreator3" DstPort 2 } Branch { Points [0, 20] Branch { DstBlock "Bus\nCreator3" DstPort 3 } Branch { Points [0, 20] DstBlock "Bus\nCreator3" DstPort 4 } } } } Branch { Points [0, 85] Branch { DstBlock "RF B Inputs" DstPort 2 } Branch { Points [0, 100] Branch { DstBlock "RF C Inputs" DstPort 2 } Branch { Points [0, 85] DstBlock "RF D Inputs" DstPort 2 } } } } } Line { Labels [0, 0] SrcBlock "negedge1" SrcPort 1 DstBlock "Convert2" DstPort 1 } Line { SrcBlock "Register3" SrcPort 1 DstBlock "negedge1" DstPort 1 } Line { SrcBlock "RX_IQ_SAMP_CE" SrcPort 1 Points [20, 0] Branch { DstBlock "Register3" DstPort 1 } Branch { Points [0, 85] DstBlock "Goto16" DstPort 1 } } Line { SrcBlock "Pulse\nGenerator3" SrcPort 1 DstBlock "RX_IQ_SAMP_CE" DstPort 1 } Line { SrcBlock "RF A Inputs" SrcPort 1 DstBlock "Goto1" DstPort 1 } Line { SrcBlock "RF A Inputs" SrcPort 2 DstBlock "Goto5" DstPort 1 } Line { SrcBlock "RF A Inputs" SrcPort 3 DstBlock "Goto10" DstPort 1 } Line { SrcBlock "RF B Inputs" SrcPort 1 DstBlock "Goto11" DstPort 1 } Line { SrcBlock "RF B Inputs" SrcPort 2 DstBlock "Goto15" DstPort 1 } Line { SrcBlock "RF B Inputs" SrcPort 3 DstBlock "Goto14" DstPort 1 } Line { Name "RFD_I" Labels [0, 0] SrcBlock "From8" SrcPort 1 DstBlock "Bus\nCreator" DstPort 4 } Line { Name "RFC_I" Labels [0, 0] SrcBlock "From9" SrcPort 1 DstBlock "Bus\nCreator" DstPort 3 } Line { Name "RFC_Q" Labels [0, 0] SrcBlock "From10" SrcPort 1 DstBlock "Bus\nCreator1" DstPort 3 } Line { Name "RFD_Q" Labels [0, 0] SrcBlock "From11" SrcPort 1 DstBlock "Bus\nCreator1" DstPort 4 } Line { Name "RFC_RSSI" Labels [0, 0] SrcBlock "From12" SrcPort 1 DstBlock "Bus\nCreator2" DstPort 3 } Line { Name "RFD_RSSI" Labels [0, 0] SrcBlock "From13" SrcPort 1 DstBlock "Bus\nCreator2" DstPort 4 } Line { SrcBlock "RF C Inputs" SrcPort 1 DstBlock "Goto3" DstPort 1 } Line { SrcBlock "RF C Inputs" SrcPort 2 DstBlock "Goto13" DstPort 1 } Line { SrcBlock "RF C Inputs" SrcPort 3 DstBlock "Goto4" DstPort 1 } Line { SrcBlock "RF D Inputs" SrcPort 1 DstBlock "Goto7" DstPort 1 } Line { SrcBlock "RF D Inputs" SrcPort 2 DstBlock "Goto12" DstPort 1 } Line { SrcBlock "RF D Inputs" SrcPort 3 DstBlock "Goto8" DstPort 1 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "AGC_DONE" DstPort 1 } } } Block { BlockType SubSystem Name "MAC I/O" SID "10187" Ports [] Position [770, 287, 810, 333] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "MAC I/O" Location [-1678, 227, -18, 1187] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "80" Block { BlockType Reference Name "Concat1" SID "10188" Ports [2, 1] Position [370, 621, 420, 674] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point at ze" "ro." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "50,53,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 53 53 0 ],[0.77 0.82 0.91" " ]);\nplot([0 50 50 0 0 ],[0 0 53 53 0 ]);\npatch([9.425 19.54 26.54 33.54 40.54 26.54 16.425 9.425 ],[33.77 33.77 " "40.77 33.77 40.77 40.77 40.77 33.77 ],[1 1 1 ]);\npatch([16.425 26.54 19.54 9.425 16.425 ],[26.77 26.77 33.77 33.77" " 26.77 ],[0.931 0.946 0.973 ]);\npatch([9.425 19.54 26.54 16.425 9.425 ],[19.77 19.77 26.77 26.77 19.77 ],[1 1 1 ])" ";\npatch([16.425 40.54 33.54 26.54 19.54 9.425 16.425 ],[12.77 12.77 19.77 12.77 19.77 19.77 12.77 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fontsize{20}\\}','texmo" "de','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Constant Name "Constant" SID "10934" Position [935, 47, 960, 73] ZOrder -4 ShowName off Value "0" } Block { BlockType Reference Name "Convert1" SID "10189" Ports [1, 1] Position [775, 751, 800, 769] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "ceil(log2(MAX_NUM_BYTES))" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13.2" "2 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ],[0." "931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16.44 " "14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: en" "d icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cast');\nfprin" "tf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "10190" Ports [1, 1] Position [815, 286, 840, 304] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "ceil(log2(MAX_NUM_BYTES))" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13.2" "2 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ],[0." "931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16.44 " "14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: en" "d icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cast');\nfprin" "tf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert3" SID "17416" Ports [1, 1] Position [630, 1056, 655, 1074] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "7" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13.2" "2 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ],[0." "931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16.44 " "14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: en" "d icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cast');\nfprin" "tf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert4" SID "10778" Ports [1, 1] Position [495, 666, 520, 684] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13.2" "2 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ],[0." "931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16.44 " "14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: en" "d icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cast');\nfprin" "tf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay" SID "10192" Ports [1, 1] Position [440, 495, 470, 525] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "8" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "30,30,1,1,white,blue,0,e47f993a,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 30 30 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 19.44 23.44 " "19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 19.44 15.44 ],[0." "931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([10.1 23." "88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-8}','texmode','on');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay1" SID "18029" Ports [1, 1] Position [440, 475, 470, 505] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "8" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "30,30,1,1,white,blue,0,e47f993a,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 30 30 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 19.44 23.44 " "19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 19.44 15.44 ],[0." "931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([10.1 23." "88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-8}','texmode','on');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay2" SID "18030" Ports [1, 1] Position [800, 485, 825, 515] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "8" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "25,30,1,1,white,blue,0,e47f993a,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 30 30 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[18.33 18.33 21" ".33 18.33 21.33 21.33 21.33 18.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[15.33 15.33 18.33 18.33 15.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[12.33 12.33 15.33 15.33 12.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[9.33 9.33 12.33 9.33 12.33 12.33 9.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-8}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From1" SID "10193" Position [35, 625, 300, 645] ShowName off CloseFcn "tagdialog Close" GotoTag "OFDM_RX_ERROR_NO_PAYLOAD_REASON" TagVisibility "global" } Block { BlockType From Name "From10" SID "11737" Position [430, 935, 630, 955] ShowName off CloseFcn "tagdialog Close" GotoTag "OFDM_FCS_GOOD" TagVisibility "global" } Block { BlockType From Name "From11" SID "11738" Position [430, 830, 630, 850] ShowName off CloseFcn "tagdialog Close" GotoTag "DSSS_RX_DATA_DONE" TagVisibility "global" } Block { BlockType From Name "From12" SID "11739" Position [430, 850, 630, 870] ShowName off CloseFcn "tagdialog Close" GotoTag "OFDM_RX_DATA_DONE" TagVisibility "global" } Block { BlockType From Name "From13" SID "10197" Position [555, 285, 755, 305] ShowName off CloseFcn "tagdialog Close" GotoTag "CUR_MPDU_BYTE_INDEX" TagVisibility "global" } Block { BlockType From Name "From14" SID "10198" Position [555, 235, 755, 255] ShowName off CloseFcn "tagdialog Close" GotoTag "CUR_MPDU_BYTE" TagVisibility "global" } Block { BlockType From Name "From15" SID "10199" Position [555, 185, 755, 205] ShowName off CloseFcn "tagdialog Close" GotoTag "CUR_MPDU_BYTE_VALID" TagVisibility "global" } Block { BlockType From Name "From16" SID "10200" Position [395, 1030, 595, 1050] ShowName off CloseFcn "tagdialog Close" GotoTag "OFDM_RX_DATA_MCS" TagVisibility "global" } Block { BlockType From Name "From17" SID "10201" Position [385, 565, 525, 585] ShowName off CloseFcn "tagdialog Close" GotoTag "DSSS_RX_END" TagVisibility "global" } Block { BlockType From Name "From18" SID "10202" Position [40, 515, 240, 535] ShowName off CloseFcn "tagdialog Close" GotoTag "RX_END_OFDM_LAST_SAMP" TagVisibility "global" } Block { BlockType From Name "From19" SID "10203" Position [195, 480, 390, 500] ShowName off CloseFcn "tagdialog Close" GotoTag "RX_GLOBAL_RESET" TagVisibility "global" } Block { BlockType From Name "From2" SID "10204" Position [675, 492, 780, 508] ShowName off CloseFcn "tagdialog Close" GotoTag "RX_GLOBAL_RESET" TagVisibility "global" } Block { BlockType From Name "From20" SID "10205" Position [425, 1135, 625, 1155] ShowName off CloseFcn "tagdialog Close" GotoTag "OFDM_RX_PARAMS_READY" TagVisibility "global" } Block { BlockType From Name "From21" SID "10206" Position [425, 1305, 625, 1325] ShowName off CloseFcn "tagdialog Close" GotoTag "OFDM_RX_UNSUPPORTED" TagVisibility "global" } Block { BlockType From Name "From22" SID "10207" Position [425, 1260, 625, 1280] ShowName off CloseFcn "tagdialog Close" GotoTag "OFDM_RX_PHY_MODE" TagVisibility "global" } Block { BlockType From Name "From23" SID "10208" Position [40, 540, 240, 560] ShowName off CloseFcn "tagdialog Close" GotoTag "OFDM_RX_ERROR_NO_PAYLOAD" TagVisibility "global" } Block { BlockType From Name "From25" SID "10209" Position [40, 565, 240, 585] ShowName off CloseFcn "tagdialog Close" GotoTag "RX_RESET_WHILE_ACTIVE" TagVisibility "global" } Block { BlockType From Name "From26" SID "17413" Position [395, 1055, 595, 1075] ShowName off CloseFcn "tagdialog Close" GotoTag "RX_START_DSSS_PHY_HDR_MCS" TagVisibility "global" } Block { BlockType From Name "From27" SID "10211" Position [35, 650, 235, 670] ShowName off CloseFcn "tagdialog Close" GotoTag "RX_RESET_WHILE_ACTIVE" TagVisibility "global" } Block { BlockType From Name "From3" SID "11297" Position [535, 53, 735, 67] ShowName off CloseFcn "tagdialog Close" GotoTag "RX_STARTED_TO_MAC" TagVisibility "global" } Block { BlockType From Name "From4" SID "10212" Position [190, 435, 390, 455] ShowName off CloseFcn "tagdialog Close" GotoTag "OFDM_RX_SIGNAL_VALID" TagVisibility "global" } Block { BlockType From Name "From5" SID "10213" Position [560, 115, 760, 135] ShowName off CloseFcn "tagdialog Close" GotoTag "RX_CCA_BUSY" TagVisibility "global" } Block { BlockType From Name "From6" SID "10214" Position [430, 750, 630, 770] ShowName off CloseFcn "tagdialog Close" GotoTag "OFDM_RX_DATA_LENGTH" TagVisibility "global" } Block { BlockType From Name "From7" SID "10215" Position [190, 415, 390, 435] ShowName off CloseFcn "tagdialog Close" GotoTag "RX_START_DSSS_SIGNAL_VALID" TagVisibility "global" } Block { BlockType From Name "From8" SID "10216" Position [430, 775, 630, 795] ShowName off CloseFcn "tagdialog Close" GotoTag "DSSS_SIGNAL_LENGTH" TagVisibility "global" } Block { BlockType From Name "From9" SID "11740" Position [430, 895, 630, 915] ShowName off CloseFcn "tagdialog Close" GotoTag "DSSS_FCS_GOOD" TagVisibility "global" } Block { BlockType Goto Name "Goto1" SID "10764" Position [1070, 581, 1305, 599] ZOrder -10 ShowName off GotoTag "CS_MAC_OUT_RX_END" TagVisibility "global" } Block { BlockType Goto Name "Goto2" SID "10935" Position [1260, 51, 1495, 69] ZOrder -10 ShowName off GotoTag "MAC_PHY_BLOCK_PKT_DET" TagVisibility "global" } Block { BlockType Goto Name "Goto3" SID "10765" Position [1070, 466, 1305, 484] ZOrder -10 ShowName off GotoTag "CS_MAC_OUT_RX_START" TagVisibility "global" } Block { BlockType Goto Name "Goto4" SID "10766" Position [1070, 971, 1305, 989] ZOrder -10 ShowName off GotoTag "CS_MAC_OUT_FCS_GOOD" TagVisibility "global" } Block { BlockType Goto Name "Goto5" SID "10219" Position [1070, 486, 1305, 504] ZOrder -10 ShowName off GotoTag "RX_STARTED_TO_MAC" TagVisibility "global" } Block { BlockType Goto Name "Goto6" SID "10767" Position [1070, 1076, 1305, 1094] ZOrder -10 ShowName off GotoTag "CS_MAC_OUT_MCS" TagVisibility "global" } Block { BlockType Goto Name "Goto7" SID "10768" Position [1060, 791, 1295, 809] ZOrder -10 ShowName off GotoTag "CS_MAC_OUT_LENGTH" TagVisibility "global" } Block { BlockType Reference Name "Inverter" SID "11776" Ports [1, 1] Position [815, 696, 840, 714] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13.2" "2 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ],[0." "931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16.44 " "14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: en" "d icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfprintf('','COMMENT: " "end icon text');" } Block { BlockType Reference Name "Logical1" SID "10220" Ports [2, 1] Position [545, 414, 580, 456] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,42,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 42 42 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 42 42 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[26.55 26.55 31.55" " 26.55 31.55 31.55 31.55 26.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[21.55 21.55 26.55 26.55 21.55 " "],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[16.55 16.55 21.55 21.55 16.55 ],[1 1 1 ]);\npatch(" "[10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[11.55 11.55 16.55 11.55 16.55 16.55 11.55 ],[0.931 0.946 0.973 ]);\nfpr" "intf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('or');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "10221" Ports [2, 1] Position [495, 479, 520, 521] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "25,42,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 42 42 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 42 42 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[24.33 24.33 27" ".33 24.33 27.33 27.33 27.33 24.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[21.33 21.33 24.33 24.33 21.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[18.33 18.33 21.33 21.33 18.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[15.33 15.33 18.33 15.33 18.33 18.33 15.33 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('or')" ";\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical3" SID "10222" Ports [2, 1] Position [1000, 525, 1025, 560] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "25,35,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 35 35 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 35 35 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[20.33 20.33 23" ".33 20.33 23.33 23.33 23.33 20.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[17.33 17.33 20.33 20.33 17.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[14.33 14.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[11.33 11.33 14.33 11.33 14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('and'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical4" SID "10223" Ports [3, 1] Position [290, 514, 320, 586] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "30,72,3,1,white,blue,0,a2abe52d,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 72 72 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 72 72 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[40.44 40.44 44.44 " "40.44 44.44 44.44 44.44 40.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[36.44 36.44 40.44 40.44 36.44 ],[0." "931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[32.44 32.44 36.44 36.44 32.44 ],[1 1 1 ]);\npatch([10.1 23." "88 19.88 15.88 11.88 6.1 10.1 ],[28.44 28.44 32.44 28.44 32.44 32.44 28.44 ],[0.931 0.946 0.973 ]);\nfprintf('','CO" "MMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\ncolor('black');disp('or');\nfprintf('" "','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical5" SID "10224" Ports [2, 1] Position [845, 490, 870, 525] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "25,35,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 35 35 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 35 35 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[20.33 20.33 23" ".33 20.33 23.33 23.33 23.33 20.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[17.33 17.33 20.33 20.33 17.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[14.33 14.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[11.33 11.33 14.33 11.33 14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('or')" ";\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical6" SID "11741" Ports [3, 1] Position [715, 811, 740, 869] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "25,58,3,1,white,blue,0,a2abe52d,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 58 58 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 58 58 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[32.33 32.33 35" ".33 32.33 35.33 35.33 35.33 32.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[29.33 29.33 32.33 32.33 29.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[26.33 26.33 29.33 29.33 26.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[23.33 23.33 26.33 23.33 26.33 26.33 23.33 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\ncolor('black');disp('or" "');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical7" SID "11742" Ports [2, 1] Position [765, 915, 790, 950] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "25,35,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 35 35 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 35 35 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[20.33 20.33 23" ".33 20.33 23.33 23.33 23.33 20.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[17.33 17.33 20.33 20.33 17.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[14.33 14.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[11.33 11.33 14.33 11.33 14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('or')" ";\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical8" SID "11743" Ports [2, 1] Position [705, 920, 730, 955] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "25,35,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 35 35 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 35 35 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[20.33 20.33 23" ".33 20.33 23.33 23.33 23.33 20.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[17.33 17.33 20.33 20.33 17.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[14.33 14.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[11.33 11.33 14.33 11.33 14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('and'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical9" SID "11744" Ports [2, 1] Position [705, 880, 730, 915] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "25,35,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 35 35 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 35 35 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[20.33 20.33 23" ".33 20.33 23.33 23.33 23.33 20.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[17.33 17.33 20.33 20.33 17.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[14.33 14.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[11.33 11.33 14.33 11.33 14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('and'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Scope Name "MAC Outputs" SID "10225" Ports [12] Position [1680, 430, 1725, 715] ZOrder -3 Floating off Location [1, 45, 1843, 1199] Open off NumInputPorts "12" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" axes9 "%" axes10 "%" axes11 "%" axes12 "%" } List { ListType ScopeGraphics FigureColor "[0.501960784313725 0.501960784313725 0.501960784313725]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[2 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "12900 " YMin "-1~-1~-1~1~59~-1~-1~-1~-1~1~1.9~-1" YMax "1~1~1~1~59~1~1~1~1~1~2.1~1" SaveName "ScopeData37" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType Scope Name "MAC Rx Data Outputs" SID "10226" Ports [4] Position [1370, 173, 1415, 367] ZOrder -3 Floating off Location [16, 155, 1696, 1159] Open off NumInputPorts "4" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" } List { ListType ScopeGraphics FigureColor "[0.5 0.5 0.5]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "32908 " YMin "-1~-1~-1~1" YMax "1~1~1~1" SaveName "ScopeData32" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType Reference Name "Mux1" SID "10227" Ports [3, 1] Position [685, 609, 710, 691] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "25,82,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 11.7143 70.2857 82 0 ],[0.7" "7 0.82 0.91 ]);\nplot([0 25 25 0 0 ],[0 11.7143 70.2857 82 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5" ".325 ],[44.33 44.33 47.33 44.33 47.33 47.33 47.33 44.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[41.33 " "41.33 44.33 44.33 41.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[38.33 38.33 41.33 41.33 38" ".33 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[35.33 35.33 38.33 35.33 38.33 38.33 35.33 ],[0" ".931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3" ",'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux2" SID "10228" Ports [3, 1] Position [685, 509, 710, 591] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "25,82,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 11.7143 70.2857 82 0 ],[0.7" "7 0.82 0.91 ]);\nplot([0 25 25 0 0 ],[0 11.7143 70.2857 82 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5" ".325 ],[44.33 44.33 47.33 44.33 47.33 47.33 47.33 44.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[41.33 " "41.33 44.33 44.33 41.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[38.33 38.33 41.33 41.33 38" ".33 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[35.33 35.33 38.33 35.33 38.33 38.33 35.33 ],[0" ".931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3" ",'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux3" SID "10229" Ports [3, 1] Position [685, 719, 710, 801] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "25,82,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 11.7143 70.2857 82 0 ],[0.7" "7 0.82 0.91 ]);\nplot([0 25 25 0 0 ],[0 11.7143 70.2857 82 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5" ".325 ],[44.33 44.33 47.33 44.33 47.33 47.33 47.33 44.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[41.33 " "41.33 44.33 44.33 41.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[38.33 38.33 41.33 41.33 38" ".33 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[35.33 35.33 38.33 35.33 38.33 38.33 35.33 ],[0" ".931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3" ",'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux4" SID "17414" Ports [3, 1] Position [705, 999, 730, 1081] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "25,82,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 11.7143 70.2857 82 0 ],[0.7" "7 0.82 0.91 ]);\nplot([0 25 25 0 0 ],[0 11.7143 70.2857 82 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5" ".325 ],[44.33 44.33 47.33 44.33 47.33 47.33 47.33 44.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[41.33 " "41.33 44.33 44.33 41.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[38.33 38.33 41.33 41.33 38" ".33 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[35.33 35.33 38.33 35.33 38.33 38.33 35.33 ],[0" ".931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3" ",'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "PHY_CCA.IND_BUSY" SID "10232" Ports [1, 1] Position [1025, 115, 1085, 135] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" " ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "PHY_RX_BLOCK_PKTDET" SID "10933" Ports [1, 1] Position [1020, 50, 1085, 70] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to Xilinx" " fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top level input p" "orts." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "16" bin_pt "14" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end ic" "on text');" } Block { BlockType Reference Name "PHY_RX_DATA.BYTE" SID "10233" Ports [1, 1] Position [1030, 235, 1085, 255] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "55,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 55 55 0 0 ],[0 0 20 20 0 ]);\npatch([22.55 25.44 27.44 29.44 31.44 27.44 24.55 22.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([24.55 27.44 25.44 22.55 24.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([22.55 25.44 27.44 24.55 22.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([24.55 31.44 29.44 27.44 25.44 22.55 24.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" " ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Data Byte" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "PHY_RX_DATA.BYTENUM" SID "10234" Ports [1, 1] Position [1030, 285, 1085, 305] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "55,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 55 55 0 0 ],[0 0 20 20 0 ]);\npatch([22.55 25.44 27.44 29.44 31.44 27.44 24.55 22.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([24.55 27.44 25.44 22.55 24.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([22.55 25.44 27.44 24.55 22.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([24.55 31.44 29.44 27.44 25.44 22.55 24.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" " ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Data Index" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "PHY_RX_DATA.BYTENUM1" SID "10235" Ports [1, 1] Position [1190, 339, 1225, 351] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.88" " ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.11 " "8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 ],[" "0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([15." "775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" Port { PortNumber 1 Name "Validated Rx Data" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "PHY_RX_DATA.BYTENUM2" SID "11298" Ports [1, 1] Position [825, 54, 860, 66] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.88" " ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.11 " "8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 ],[" "0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([15." "775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" } Block { BlockType Reference Name "PHY_RX_DATA.IND" SID "10236" Ports [1, 1] Position [1030, 185, 1085, 205] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "55,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 55 55 0 0 ],[0 0 20 20 0 ]);\npatch([22.55 25.44 27.44 29.44 31.44 27.44 24.55 22.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([24.55 27.44 25.44 22.55 24.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([22.55 25.44 27.44 24.55 22.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([24.55 31.44 29.44 27.44 25.44 22.55 24.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" " ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Data Valid" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "PHY_RX_DATA_DONE.IND" SID "10237" Ports [1, 1] Position [1200, 830, 1255, 850] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "55,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 55 55 0 0 ],[0 0 20 20 0 ]);\npatch([22.55 25.44 27.44 29.44 31.44 27.44 24.55 22.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([24.55 27.44 25.44 22.55 24.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([22.55 25.44 27.44 24.55 22.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([24.55 31.44 29.44 27.44 25.44 22.55 24.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" " ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Data Done" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "PHY_RX_END.IND" SID "10238" Ports [1, 1] Position [1190, 535, 1250, 555] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" " ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Rx End" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "PHY_RX_END.RXERROR" SID "10239" Ports [1, 1] Position [1195, 640, 1255, 660] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" " ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Rx End Error" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "PHY_RX_FCS_GOOD.IND" SID "10240" Ports [1, 1] Position [1200, 925, 1255, 945] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "55,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 55 55 0 0 ],[0 0 20 20 0 ]);\npatch([22.55 25.44 27.44 29.44 31.44 27.44 24.55 22.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([24.55 27.44 25.44 22.55 24.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([22.55 25.44 27.44 24.55 22.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([24.55 31.44 29.44 27.44 25.44 22.55 24.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" " ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "FCS Good" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "PHY_RX_PHY_HDR.IND" SID "10241" Ports [1, 1] Position [1195, 1135, 1255, 1155] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" " ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Rx PHY Hdr Ready" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "PHY_RX_PHY_HDR.LENGTH" SID "10242" Ports [1, 1] Position [1195, 750, 1255, 770] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" " ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Rx Length" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "PHY_RX_PHY_HDR.MCS" SID "10243" Ports [1, 1] Position [1200, 1030, 1260, 1050] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" " ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "PHY Hdr MCS" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "PHY_RX_PHY_HDR.PHY_MODE" SID "10244" Ports [1, 1] Position [1195, 1260, 1255, 1280] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" " ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "PHY Mode" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "PHY_RX_PHY_HDR.UNSUPPORTED" SID "10245" Ports [1, 1] Position [1195, 1305, 1255, 1325] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" " ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "PHY Hdr Unsupported" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "PHY_RX_START.IND" SID "10246" Ports [1, 1] Position [1190, 425, 1250, 445] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" " ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Rx Start" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "PHY_RX_START.PHY_SEL" SID "10247" Ports [1, 1] Position [1195, 695, 1255, 715] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" " ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Rx PHY Sel" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType SubSystem Name "Pulse Stretch1" SID "10248" Ports [1, 1] Position [915, 877, 970, 913] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Pulse Stretch1" Location [61, 101, 2263, 1443] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "P" SID "10249" Position [350, 258, 380, 272] IconDisplay "Port number" } Block { BlockType Reference Name "Delay" SID "10250" Ports [1, 1] Position [410, 329, 445, 361] BlockMirror on NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "16" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,32,1,1,white,blue,0,f89f7887,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 32 32 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 32 32 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[20.44 " "20.44 24.44 20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[16.44 16.44 20.44 2" "0.44 16.44 ],[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1 1 1 " "]);\npatch([12.1 25.88 21.88 17.88 13.88 8.1 12.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');di" "sp('z^{-16}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register15" SID "10251" Ports [1, 1] Position [535, 265, 565, 295] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 30 30 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 30 30 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 " "19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 1" "9.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "S-R Latch" SID "10252" Ports [2, 1] Position [405, 253, 450, 302] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "S-R Latch" Location [13, 209, 2156, 1324] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "10253" Position [140, 103, 170, 117] IconDisplay "Port number" } Block { BlockType Inport Name "R" SID "10254" Position [140, 88, 170, 102] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "10255" Ports [0, 1] Position [195, 71, 210, 89] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "15,18,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11.22 13.22 " "11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 9.22 ],[0.931" " 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([4.55 11.44 9.44" " 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon" " graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "10256" Ports [1, 1] Position [210, 86, 235, 104] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cast');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "10257" Ports [1, 1] Position [210, 101, 235, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cast');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "10258" Ports [3, 1] Position [255, 71, 300, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 30.66 3" "6.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 30.66 24" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('" "input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'en');\ncolor('bl" "ack');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon te" "xt');" } Block { BlockType Outport Name "Q" SID "10259" Position [325, 88, 355, 102] IconDisplay "Port number" } Line { SrcBlock "Convert2" SrcPort 1 DstBlock "Register2" DstPort 3 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "S" SrcPort 1 DstBlock "Convert2" DstPort 1 } } } Block { BlockType Outport Name "P16" SID "10260" Position [605, 273, 635, 287] IconDisplay "Port number" } Line { SrcBlock "S-R Latch" SrcPort 1 Points [40, 0] Branch { Points [0, 65] DstBlock "Delay" DstPort 1 } Branch { DstBlock "Register15" DstPort 1 } } Line { SrcBlock "Delay" SrcPort 1 Points [-25, 0; 0, -55] DstBlock "S-R Latch" DstPort 2 } Line { SrcBlock "P" SrcPort 1 DstBlock "S-R Latch" DstPort 1 } Line { SrcBlock "Register15" SrcPort 1 DstBlock "P16" DstPort 1 } } } Block { BlockType Reference Name "Register1" SID "10261" Ports [1, 1] Position [1070, 635, 1100, 665] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 30 30 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 19.44 23.44 " "19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 19.44 15.44 ],[0." "931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([10.1 23." "88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor(" "'black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon " "text');" } Block { BlockType Reference Name "Register10" SID "10262" Ports [1, 1] Position [615, 420, 645, 450] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 30 30 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 19.44 23.44 " "19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 19.44 15.44 ],[0." "931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([10.1 23." "88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor(" "'black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon " "text');" } Block { BlockType Reference Name "Register11" SID "10263" Ports [1, 1] Position [1075, 1025, 1105, 1055] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 30 30 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 19.44 23.44 " "19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 19.44 15.44 ],[0." "931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([10.1 23." "88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor(" "'black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon " "text');" } Block { BlockType Reference Name "Register12" SID "10264" Ports [1, 1] Position [1070, 690, 1100, 720] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 30 30 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 19.44 23.44 " "19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 19.44 15.44 ],[0." "931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([10.1 23." "88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor(" "'black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon " "text');" } Block { BlockType Reference Name "Register13" SID "10265" Ports [1, 1] Position [1070, 1300, 1100, 1330] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 30 30 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 19.44 23.44 " "19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 19.44 15.44 ],[0." "931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([10.1 23." "88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor(" "'black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon " "text');" } Block { BlockType Reference Name "Register14" SID "10266" Ports [1, 1] Position [840, 880, 870, 910] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 30 30 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 19.44 23.44 " "19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 19.44 15.44 ],[0." "931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([10.1 23." "88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor(" "'black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon " "text');" } Block { BlockType Reference Name "Register15" SID "10267" Ports [1, 1] Position [1000, 880, 1030, 910] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 30 30 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 19.44 23.44 " "19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 19.44 15.44 ],[0." "931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([10.1 23." "88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor(" "'black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon " "text');" } Block { BlockType Reference Name "Register16" SID "10268" Ports [1, 1] Position [1070, 880, 1100, 910] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 30 30 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 19.44 23.44 " "19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 19.44 15.44 ],[0." "931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([10.1 23." "88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor(" "'black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon " "text');" } Block { BlockType Reference Name "Register17" SID "10269" Ports [1, 1] Position [1070, 1130, 1100, 1160] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 30 30 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 19.44 23.44 " "19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 19.44 15.44 ],[0." "931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([10.1 23." "88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor(" "'black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon " "text');" } Block { BlockType Reference Name "Register18" SID "10270" Ports [1, 1] Position [1070, 1255, 1100, 1285] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 30 30 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 19.44 23.44 " "19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 19.44 15.44 ],[0." "931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([10.1 23." "88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor(" "'black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon " "text');" } Block { BlockType Reference Name "Register19" SID "10271" Ports [1, 1] Position [1070, 530, 1100, 560] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 30 30 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 19.44 23.44 " "19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 19.44 15.44 ],[0." "931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([10.1 23." "88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor(" "'black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon " "text');" } Block { BlockType Reference Name "Register2" SID "10272" Ports [1, 1] Position [1070, 920, 1100, 950] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 30 30 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 19.44 23.44 " "19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 19.44 15.44 ],[0." "931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([10.1 23." "88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor(" "'black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon " "text');" } Block { BlockType Reference Name "Register20" SID "10273" Ports [2, 1] Position [1100, 325, 1135, 365] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,40,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 40 40 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 40 40 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[25.55 25.55 30.55" " 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[20.55 20.55 25.55 25.55 20.55 " "],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1 1 ]);\npatch(" "[10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.946 0.973 ]);\nfpr" "intf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');dis" "p('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register21" SID "10936" Ports [1, 1] Position [1145, 45, 1175, 75] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 30 30 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 19.44 23.44 " "19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 19.44 15.44 ],[0." "931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([10.1 23." "88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor(" "'black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon " "text');" } Block { BlockType Reference Name "Register3" SID "10274" Ports [1, 1] Position [1070, 825, 1100, 855] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 30 30 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 19.44 23.44 " "19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 19.44 15.44 ],[0." "931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([10.1 23." "88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor(" "'black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon " "text');" } Block { BlockType Reference Name "Register4" SID "10275" Ports [1, 1] Position [935, 280, 965, 310] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 30 30 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 19.44 23.44 " "19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 19.44 15.44 ],[0." "931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([10.1 23." "88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor(" "'black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon " "text');" } Block { BlockType Reference Name "Register5" SID "10276" Ports [1, 1] Position [935, 230, 965, 260] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 30 30 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 19.44 23.44 " "19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 19.44 15.44 ],[0." "931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([10.1 23." "88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor(" "'black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon " "text');" } Block { BlockType Reference Name "Register6" SID "10277" Ports [1, 1] Position [935, 180, 965, 210] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 30 30 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 19.44 23.44 " "19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 19.44 15.44 ],[0." "931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([10.1 23." "88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor(" "'black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon " "text');" } Block { BlockType Reference Name "Register7" SID "10278" Ports [1, 1] Position [1070, 420, 1100, 450] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 30 30 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 19.44 23.44 " "19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 19.44 15.44 ],[0." "931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([10.1 23." "88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor(" "'black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon " "text');" } Block { BlockType Reference Name "Register8" SID "10279" Ports [1, 1] Position [935, 110, 965, 140] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 30 30 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 19.44 23.44 " "19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 19.44 15.44 ],[0." "931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([10.1 23." "88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor(" "'black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon " "text');" } Block { BlockType Reference Name "Register9" SID "10280" Ports [1, 1] Position [1070, 745, 1100, 775] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 30 30 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 19.44 23.44 " "19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 19.44 15.44 ],[0." "931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([10.1 23." "88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor(" "'black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon " "text');" } Block { BlockType SubSystem Name "S-R Latch1" SID "10281" Ports [2, 1] Position [600, 469, 635, 511] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "S-R Latch1" Location [351, 366, 2001, 1172] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "10282" Position [140, 103, 170, 117] IconDisplay "Port number" } Block { BlockType Inport Name "R" SID "10283" Position [140, 88, 170, 102] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "10284" Ports [0, 1] Position [195, 71, 210, 89] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "15,18,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 " "9.22 ],[0.931 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch(" "[4.55 11.44 9.44 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf(''" ",'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1," "'1');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "10285" Ports [1, 1] Position [210, 86, 235, 104] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do" " not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.2" "2 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 " "11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);" "\npatch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label" "('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "10286" Ports [1, 1] Position [210, 101, 235, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do" " not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.2" "2 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 " "11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);" "\npatch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label" "('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "10287" Ports [3, 1] Position [255, 71, 300, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30." "66 30.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 3" "0.66 30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 " "],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0" ".931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor" "('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('i" "nput',3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfpri" "ntf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "10288" Position [325, 88, 355, 102] IconDisplay "Port number" } Line { SrcBlock "Convert2" SrcPort 1 DstBlock "Register2" DstPort 3 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "S" SrcPort 1 DstBlock "Convert2" DstPort 1 } } } Block { BlockType SubSystem Name "S-R Latch2" SID "10289" Ports [2, 1] Position [905, 464, 940, 526] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "S-R Latch2" Location [351, 366, 2001, 1172] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "10290" Position [140, 103, 170, 117] IconDisplay "Port number" } Block { BlockType Inport Name "R" SID "10291" Position [140, 88, 170, 102] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "10292" Ports [0, 1] Position [195, 71, 210, 89] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "15,18,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 " "9.22 ],[0.931 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch(" "[4.55 11.44 9.44 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf(''" ",'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1," "'1');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "10293" Ports [1, 1] Position [210, 86, 235, 104] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do" " not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.2" "2 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 " "11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);" "\npatch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label" "('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "10294" Ports [1, 1] Position [210, 101, 235, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do" " not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.2" "2 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 " "11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);" "\npatch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label" "('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "10295" Ports [3, 1] Position [255, 71, 300, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30." "66 30.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 3" "0.66 30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 " "],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0" ".931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor" "('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('i" "nput',3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfpri" "ntf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "10296" Position [325, 88, 355, 102] IconDisplay "Port number" } Line { SrcBlock "S" SrcPort 1 DstBlock "Convert2" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "Convert2" SrcPort 1 DstBlock "Register2" DstPort 3 } } } Block { BlockType ToWorkspace Name "To Workspace" SID "18121" Ports [1] Position [1400, 397, 1555, 423] ZOrder -7 ShowName off VariableName "rx_sim_rx_start_mac_output" MaxDataPoints "inf" SampleTime "-1" SaveFormat "Array" } Block { BlockType Reference Name "dbg_FCS_GOOD" SID "10297" Ports [1, 1] Position [1200, 885, 1255, 905] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "55,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 55 55 0 0 ],[0 0 20 20 0 ]);\npatch([22.55 25.44 27.44 29.44 31.44 27.44 24.55 22.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([24.55 27.44 25.44 22.55 24.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([22.55 25.44 27.44 24.55 22.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([24.55 31.44 29.44 27.44 25.44 22.55 24.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" " ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType SubSystem Name "posedge" SID "11300" Ports [1, 1] Position [345, 543, 390, 557] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "posedge" Location [214, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "11301" Position [215, 188, 245, 202] IconDisplay "Port number" } Block { BlockType Reference Name "Delay" SID "11302" Ports [1, 1] Position [425, 178, 460, 202] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p. If register retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ]" ",[15.33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.3" "3 12.33 15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 " "12.33 9.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\n\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "11303" Ports [1, 1] Position [490, 181, 515, 199] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.2" "2 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 " "11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);" "\npatch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('no" "t');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "11304" Ports [2, 1] Position [540, 151, 585, 204] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,53,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 53 53 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 53 53 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[32." "66 32.66 38.66 32.66 38.66 38.66 38.66 32.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[26.66 26.66 3" "2.66 32.66 26.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[20.66 20.66 26.66 26.66 20.66 " "],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[14.66 14.66 20.66 14.66 20.66 20.66 14.66 ],[0" ".931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n" "color('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "11305" Position [610, 173, 640, 187] IconDisplay "Port number" } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical1" DstPort 2 } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "D" SrcPort 1 Points [135, 0; 0, -5] Branch { DstBlock "Delay" DstPort 1 } Branch { Points [0, -25] DstBlock "Logical1" DstPort 1 } } Line { SrcBlock "Delay" SrcPort 1 DstBlock "Inverter" DstPort 1 } } } Line { SrcBlock "Register1" SrcPort 1 DstBlock "PHY_RX_END.RXERROR" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "PHY_RX_FCS_GOOD.IND" DstPort 1 } Line { SrcBlock "Register3" SrcPort 1 DstBlock "PHY_RX_DATA_DONE.IND" DstPort 1 } Line { SrcBlock "From14" SrcPort 1 DstBlock "Register5" DstPort 1 } Line { SrcBlock "From15" SrcPort 1 DstBlock "Register6" DstPort 1 } Line { SrcBlock "From13" SrcPort 1 DstBlock "Convert2" DstPort 1 } Line { SrcBlock "Register4" SrcPort 1 DstBlock "PHY_RX_DATA.BYTENUM" DstPort 1 } Line { SrcBlock "Register5" SrcPort 1 Points [20, 0] Branch { DstBlock "PHY_RX_DATA.BYTE" DstPort 1 } Branch { Points [0, 90] DstBlock "Register20" DstPort 1 } } Line { SrcBlock "Register6" SrcPort 1 Points [10, 0] Branch { DstBlock "PHY_RX_DATA.IND" DstPort 1 } Branch { Points [0, 160] DstBlock "Register20" DstPort 2 } } Line { SrcBlock "From5" SrcPort 1 DstBlock "Register8" DstPort 1 } Line { SrcBlock "Register7" SrcPort 1 DstBlock "PHY_RX_START.IND" DstPort 1 } Line { SrcBlock "Register8" SrcPort 1 DstBlock "PHY_CCA.IND_BUSY" DstPort 1 } Line { SrcBlock "Register9" SrcPort 1 DstBlock "PHY_RX_PHY_HDR.LENGTH" DstPort 1 } Line { SrcBlock "From7" SrcPort 1 Points [125, 0] Branch { DstBlock "Logical1" DstPort 1 } Branch { Points [0, 55] DstBlock "S-R Latch1" DstPort 1 } } Line { SrcBlock "From4" SrcPort 1 DstBlock "Logical1" DstPort 2 } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Register10" DstPort 1 } Line { SrcBlock "Mux3" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Mux1" SrcPort 1 DstBlock "Register1" DstPort 1 } Line { SrcBlock "Logical7" SrcPort 1 Points [5, 0] Branch { Points [0, -40] DstBlock "Register14" DstPort 1 } Branch { Points [225, 0] Branch { DstBlock "Register2" DstPort 1 } Branch { Points [0, 45] DstBlock "Goto4" DstPort 1 } } } Line { SrcBlock "Register10" SrcPort 1 Points [185, 0] Branch { Points [0, 45] DstBlock "S-R Latch2" DstPort 1 } Branch { Points [170, 0] Branch { DstBlock "Register7" DstPort 1 } Branch { Points [0, 40] DstBlock "Goto3" DstPort 1 } } } Line { SrcBlock "Register14" SrcPort 1 DstBlock "Pulse Stretch1" DstPort 1 } Line { SrcBlock "Register16" SrcPort 1 DstBlock "dbg_FCS_GOOD" DstPort 1 } Line { SrcBlock "S-R Latch2" SrcPort 1 Points [10, 0] Branch { DstBlock "Goto5" DstPort 1 } Branch { Points [0, 40] DstBlock "Logical3" DstPort 1 } } Line { SrcBlock "Convert2" SrcPort 1 DstBlock "Register4" DstPort 1 } Line { SrcBlock "Register12" SrcPort 1 DstBlock "PHY_RX_START.PHY_SEL" DstPort 1 } Line { SrcBlock "Convert1" SrcPort 1 Points [205, 0] Branch { DstBlock "Register9" DstPort 1 } Branch { Points [0, 40] DstBlock "Goto7" DstPort 1 } } Line { Name "Data Valid" Labels [0, 0] SrcBlock "PHY_RX_DATA.IND" SrcPort 1 DstBlock "MAC Rx Data Outputs" DstPort 1 } Line { Name "Data Byte" Labels [0, 0] SrcBlock "PHY_RX_DATA.BYTE" SrcPort 1 DstBlock "MAC Rx Data Outputs" DstPort 2 } Line { Name "Data Index" Labels [0, 0] SrcBlock "PHY_RX_DATA.BYTENUM" SrcPort 1 DstBlock "MAC Rx Data Outputs" DstPort 3 } Line { SrcBlock "Register20" SrcPort 1 DstBlock "PHY_RX_DATA.BYTENUM1" DstPort 1 } Line { Name "Validated Rx Data" Labels [0, 0] SrcBlock "PHY_RX_DATA.BYTENUM1" SrcPort 1 DstBlock "MAC Rx Data Outputs" DstPort 4 } Line { SrcBlock "S-R Latch1" SrcPort 1 Points [10, 0; 0, 35] Branch { DstBlock "Mux2" DstPort 1 } Branch { Points [0, 100] Branch { Points [0, 80] Branch { DstBlock "Inverter" DstPort 1 } Branch { Points [0, 30] Branch { DstBlock "Mux3" DstPort 1 } Branch { Points [0, 280] DstBlock "Mux4" DstPort 1 } } } Branch { DstBlock "Mux1" DstPort 1 } } } Line { SrcBlock "Logical5" SrcPort 1 DstBlock "S-R Latch2" DstPort 2 } Line { SrcBlock "Logical2" SrcPort 1 DstBlock "S-R Latch1" DstPort 2 } Line { SrcBlock "From19" SrcPort 1 DstBlock "Delay1" DstPort 1 } Line { SrcBlock "Mux2" SrcPort 1 Points [115, 0] Branch { DstBlock "Logical5" DstPort 2 } Branch { DstBlock "Logical3" DstPort 2 } } Line { SrcBlock "Register19" SrcPort 1 DstBlock "PHY_RX_END.IND" DstPort 1 } Line { SrcBlock "From2" SrcPort 1 DstBlock "Delay2" DstPort 1 } Line { SrcBlock "Logical3" SrcPort 1 Points [15, 0] Branch { DstBlock "Register19" DstPort 1 } Branch { Points [0, 45] DstBlock "Goto1" DstPort 1 } } Line { SrcBlock "Register15" SrcPort 1 DstBlock "Register16" DstPort 1 } Line { SrcBlock "Pulse Stretch1" SrcPort 1 DstBlock "Register15" DstPort 1 } Line { SrcBlock "Register11" SrcPort 1 DstBlock "PHY_RX_PHY_HDR.MCS" DstPort 1 } Line { SrcBlock "Mux4" SrcPort 1 Points [295, 0] Branch { DstBlock "Register11" DstPort 1 } Branch { Points [0, 45] DstBlock "Goto6" DstPort 1 } } Line { SrcBlock "Register13" SrcPort 1 DstBlock "PHY_RX_PHY_HDR.UNSUPPORTED" DstPort 1 } Line { SrcBlock "From21" SrcPort 1 DstBlock "Register13" DstPort 1 } Line { SrcBlock "From20" SrcPort 1 DstBlock "Register17" DstPort 1 } Line { SrcBlock "Register17" SrcPort 1 DstBlock "PHY_RX_PHY_HDR.IND" DstPort 1 } Line { SrcBlock "Register18" SrcPort 1 DstBlock "PHY_RX_PHY_HDR.PHY_MODE" DstPort 1 } Line { SrcBlock "From22" SrcPort 1 DstBlock "Register18" DstPort 1 } Line { SrcBlock "From18" SrcPort 1 DstBlock "Logical4" DstPort 1 } Line { SrcBlock "From23" SrcPort 1 DstBlock "Logical4" DstPort 2 } Line { SrcBlock "From25" SrcPort 1 DstBlock "Logical4" DstPort 3 } Line { SrcBlock "Logical4" SrcPort 1 DstBlock "posedge" DstPort 1 } Line { SrcBlock "From1" SrcPort 1 DstBlock "Concat1" DstPort 1 } Line { SrcBlock "From27" SrcPort 1 Points [100, 0] Branch { DstBlock "Concat1" DstPort 2 } Branch { Points [0, 15] Branch { DstBlock "Convert4" DstPort 1 } Branch { Points [0, 145] DstBlock "Logical6" DstPort 1 } } } Line { SrcBlock "Concat1" SrcPort 1 DstBlock "Mux1" DstPort 2 } Line { SrcBlock "Delay" SrcPort 1 DstBlock "Logical2" DstPort 2 } Line { SrcBlock "Convert4" SrcPort 1 DstBlock "Mux1" DstPort 3 } Line { Name "Rx Start" Labels [0, 0] SrcBlock "PHY_RX_START.IND" SrcPort 1 Points [100, 0] Branch { DstBlock "MAC Outputs" DstPort 1 } Branch { Points [0, -25] DstBlock "To Workspace" DstPort 1 } } Line { Name "Rx End" Labels [0, 0] SrcBlock "PHY_RX_END.IND" SrcPort 1 Points [130, 0; 0, -85] DstBlock "MAC Outputs" DstPort 2 } Line { Name "Rx End Error" Labels [0, 0] SrcBlock "PHY_RX_END.RXERROR" SrcPort 1 Points [155, 0; 0, -165] DstBlock "MAC Outputs" DstPort 3 } Line { Name "Rx PHY Sel" Labels [0, 0] SrcBlock "PHY_RX_START.PHY_SEL" SrcPort 1 Points [180, 0; 0, -195] DstBlock "MAC Outputs" DstPort 4 } Line { Name "Rx Length" Labels [0, 0] SrcBlock "PHY_RX_PHY_HDR.LENGTH" SrcPort 1 Points [205, 0; 0, -225] DstBlock "MAC Outputs" DstPort 5 } Line { Name "Data Done" Labels [0, 0] SrcBlock "PHY_RX_DATA_DONE.IND" SrcPort 1 Points [220, 0; 0, -280] DstBlock "MAC Outputs" DstPort 6 } Line { Name "FCS Good" Labels [0, 0] SrcBlock "PHY_RX_FCS_GOOD.IND" SrcPort 1 Points [250, 0; 0, -350] DstBlock "MAC Outputs" DstPort 7 } Line { Name "Rx PHY Hdr Ready" Labels [0, 0] SrcBlock "PHY_RX_PHY_HDR.IND" SrcPort 1 Points [290, 0; 0, -535] DstBlock "MAC Outputs" DstPort 8 } Line { Name "PHY Hdr MCS" Labels [0, 0] SrcBlock "PHY_RX_PHY_HDR.MCS" SrcPort 1 Points [310, 0; 0, -405] DstBlock "MAC Outputs" DstPort 9 } Line { Name "PHY Mode" Labels [0, 0] SrcBlock "PHY_RX_PHY_HDR.PHY_MODE" SrcPort 1 Points [340, 0; 0, -610] DstBlock "MAC Outputs" DstPort 10 } Line { Name "PHY Hdr Unsupported" Labels [0, 0] SrcBlock "PHY_RX_PHY_HDR.UNSUPPORTED" SrcPort 1 Points [360, 0; 0, -630] DstBlock "MAC Outputs" DstPort 11 } Line { SrcBlock "Constant" SrcPort 1 DstBlock "PHY_RX_BLOCK_PKTDET" DstPort 1 } Line { SrcBlock "PHY_RX_BLOCK_PKTDET" SrcPort 1 DstBlock "Register21" DstPort 1 } Line { SrcBlock "Register21" SrcPort 1 DstBlock "Goto2" DstPort 1 } Line { SrcBlock "From3" SrcPort 1 DstBlock "PHY_RX_DATA.BYTENUM2" DstPort 1 } Line { SrcBlock "posedge" SrcPort 1 DstBlock "Mux2" DstPort 2 } Line { SrcBlock "From12" SrcPort 1 Points [40, 0] Branch { Points [0, 70] DstBlock "Logical8" DstPort 1 } Branch { DstBlock "Logical6" DstPort 3 } } Line { SrcBlock "From11" SrcPort 1 Points [45, 0] Branch { Points [0, 50] DstBlock "Logical9" DstPort 1 } Branch { DstBlock "Logical6" DstPort 2 } } Line { SrcBlock "Logical8" SrcPort 1 DstBlock "Logical7" DstPort 2 } Line { SrcBlock "From10" SrcPort 1 DstBlock "Logical8" DstPort 2 } Line { SrcBlock "Logical9" SrcPort 1 Points [5, 0; 0, 25] DstBlock "Logical7" DstPort 1 } Line { SrcBlock "From9" SrcPort 1 DstBlock "Logical9" DstPort 2 } Line { SrcBlock "Logical6" SrcPort 1 DstBlock "Register3" DstPort 1 } Line { SrcBlock "From17" SrcPort 1 Points [50, 0] Branch { DstBlock "Mux2" DstPort 3 } Branch { Points [0, -40; -155, 0] DstBlock "Delay" DstPort 1 } } Line { SrcBlock "From8" SrcPort 1 DstBlock "Mux3" DstPort 3 } Line { SrcBlock "From6" SrcPort 1 DstBlock "Mux3" DstPort 2 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Register12" DstPort 1 } Line { SrcBlock "From16" SrcPort 1 DstBlock "Mux4" DstPort 2 } Line { SrcBlock "From26" SrcPort 1 DstBlock "Convert3" DstPort 1 } Line { SrcBlock "Convert3" SrcPort 1 DstBlock "Mux4" DstPort 3 } Line { SrcBlock "Delay1" SrcPort 1 DstBlock "Logical2" DstPort 1 } Line { SrcBlock "Delay2" SrcPort 1 DstBlock "Logical5" DstPort 1 } Annotation { Name "Cast byte index and LENGTH as UFix22_0, enough bits\nfor any future MAX_NUM_BYTES. This cast saves having" " to \nupdate the MAC core for changes to MAX_NUM_BYTES." Position [278, 292] HorizontalAlignment "left" } Annotation { Name "MAC interprets RX_END.RXERROR when \nRX_END.IND == 1 or RX_PARAMS.IND == 1\nThe latter case occurs when t" "he HT-SIG field is\ninvalid, either due to CRC failing or an invalid\ncombination of field values. RXERROR must ass" "ert\nwith RXD_PARAMS.IND so the MAC hardware can\nproperly terminate Rx processing without relying on\nHT-SIG.MCS/L" "ENGTH" Position [441, 1610] HorizontalAlignment "left" } Annotation { Name "Un-invert PHY_SEL to match values\nin <=v1.5.3 designs" Position [817, 678] } } } Block { BlockType SubSystem Name "Registers" SID "3824" Ports [] Position [556, 286, 603, 333] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Registers" Location [23, 89, 2067, 1522] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "80" Block { BlockType Reference Name " b[23:16] " SID "3825" Ports [1, 1] Position [375, 458, 415, 472] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardwar" "e notes: In hardware this block costs nothing." nbits "8" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "16" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "523,427,449,420" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9.22 9.22 11." "22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0." "931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([17.55 24" ".44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a:b]');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name " b[31:24]" SID "3826" Ports [1, 1] Position [375, 503, 415, 517] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardwar" "e notes: In hardware this block costs nothing." nbits "8" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "24" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "523,427,449,420" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9.22 9.22 11." "22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0." "931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([17.55 24" ".44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a:b]');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "2x " SID "3827" Ports [1, 1] Position [1590, 1029, 1630, 1051] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "2x " Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "d" SID "3828" Position [380, 398, 410, 412] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Reference Name "Concat2" SID "3829" Ports [2, 1] Position [490, 388, 530, 452] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary poi" "nt at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" block_version "8.2.02" sg_icon_stat "40,64,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 64 64 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 64 64 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[37.55" " 37.55 42.55 37.55 42.55 42.55 42.55 37.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[32.55 32.55 37" ".55 37.55 32.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[27.55 27.55 32.55 32.55 27.55 " "],[1 1 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[22.55 22.55 27.55 22.55 27.55 27.55 22.55 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor(" "'black');port_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\font" "size{20}\\}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Constant2" SID "3830" Ports [0, 1] Position [380, 425, 405, 445] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period on period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,20,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 20 20 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 20 20 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[12.2" "2 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[10.22 10.22 12.2" "2 12.22 10.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 " "1 ]);\npatch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('output',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "2d" SID "3831" Position [590, 413, 620, 427] IconDisplay "Port number" } Line { SrcBlock "Concat2" SrcPort 1 DstBlock "2d" DstPort 1 } Line { SrcBlock "d" SrcPort 1 DstBlock "Concat2" DstPort 1 } Line { SrcBlock "Constant2" SrcPort 1 DstBlock "Concat2" DstPort 2 } } } Block { BlockType Reference Name "Concat" SID "3832" Ports [5, 1] Position [1260, 180, 1295, 270] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point at ze" "ro." num_inputs "5" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" block_version "8.2.02" sg_icon_stat "35,90,5,1,white,blue,0,64797e70,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 90 90 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 90 90 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[50.55 50.55 55.55" " 50.55 55.55 55.55 55.55 50.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[45.55 45.55 50.55 50.55 45.55 " "],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[40.55 40.55 45.55 45.55 40.55 ],[1 1 1 ]);\npatch(" "[10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[35.55 35.55 40.55 35.55 40.55 40.55 35.55 ],[0.931 0.946 0.973 ]);\nfpr" "intf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,'hi');\n\n\n\ncolor('black');port_label('input',5,'lo');\n\ncolor('black');disp('\\fontsize{20}\\}','texmode','on" "');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType SubSystem Name "Config Bits" SID "3833" Ports [1] Position [520, 248, 575, 282] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Config Bits" Location [528, 324, 983, 466] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "32b" SID "3834" Position [25, 28, 55, 42] IconDisplay "Port number" } Block { BlockType Goto Name "Goto" SID "3835" Position [235, 770, 430, 790] ZOrder -10 ShowName off GotoTag "regRx_phyCCA_Mode_Sel" TagVisibility "global" } Block { BlockType Goto Name "Goto1" SID "3836" Position [230, 55, 430, 75] ShowName off GotoTag "REG_USE_RX_SIGS_INVALID_INPUT" TagVisibility "global" } Block { BlockType Goto Name "Goto10" SID "3837" Position [230, 700, 430, 720] ShowName off GotoTag "regRx_pktDetEn_Ext" TagVisibility "global" } Block { BlockType Goto Name "Goto11" SID "3838" Position [230, 575, 430, 595] ShowName off GotoTag "regRx_pktDetEn_RFC" TagVisibility "global" } Block { BlockType Goto Name "Goto12" SID "3839" Position [230, 635, 430, 655] ShowName off GotoTag "regRx_pktDetEn_RFD" TagVisibility "global" } Block { BlockType Goto Name "Goto13" SID "16610" Position [230, 405, 430, 425] ShowName off GotoTag "regRx_DISABLE_OFDM" TagVisibility "global" } Block { BlockType Goto Name "Goto14" SID "3841" Position [230, 910, 430, 930] ShowName off GotoTag "regRx_MAX_SIGNAL_LENGTH_KB" TagVisibility "global" } Block { BlockType Goto Name "Goto15" SID "3842" Position [235, 980, 430, 1000] ZOrder -10 ShowName off GotoTag "regRx_pktDet_requireBoth_OFDM" TagVisibility "global" } Block { BlockType Goto Name "Goto16" SID "3843" Position [235, 1025, 430, 1045] ZOrder -10 ShowName off GotoTag "regRx_rateLength_holds_pktDet" TagVisibility "global" } Block { BlockType Goto Name "Goto17" SID "3844" Position [230, 25, 430, 45] ShowName off GotoTag "regRx_DSSS_RX_EN" TagVisibility "global" } Block { BlockType Goto Name "Goto18" SID "3845" Position [235, 1080, 430, 1100] ZOrder -10 ShowName off GotoTag "regRx_DSSS_asserts_CCA_busy" TagVisibility "global" } Block { BlockType Goto Name "Goto19" SID "3846" Position [235, 1140, 430, 1160] ZOrder -10 ShowName off GotoTag "regRx_PHY_MODE_11N_ENABLE" TagVisibility "global" } Block { BlockType Goto Name "Goto2" SID "3847" Position [230, 180, 430, 200] ShowName off GotoTag "regRx_DSSS_RX_Req_PktDet" TagVisibility "global" } Block { BlockType Goto Name "Goto20" SID "3848" Position [230, 95, 430, 115] ShowName off GotoTag "regRx_PKT_BUF_BYTE_ORDER_SWAP" TagVisibility "global" } Block { BlockType Goto Name "Goto21" SID "4017" Position [235, 1430, 435, 1450] ShowName off GotoTag "CS_SW_TRIG" TagVisibility "global" } Block { BlockType Goto Name "Goto22" SID "14912" Position [235, 1185, 475, 1205] ZOrder -10 ShowName off GotoTag "regRx_PHY_MODE_11AC_DET_ENABLE" TagVisibility "global" } Block { BlockType Goto Name "Goto23" SID "15804" Position [235, 1225, 430, 1245] ZOrder -10 ShowName off GotoTag "regRx_pktDet_requireBoth_DSSS" TagVisibility "global" } Block { BlockType Goto Name "Goto24" SID "17474" Position [235, 1275, 430, 1295] ZOrder -10 ShowName off GotoTag "regRx_Reset_PktDetCounts" TagVisibility "global" } Block { BlockType Goto Name "Goto25" SID "18023" Position [235, 1315, 480, 1335] ZOrder -10 ShowName off GotoTag "regRx_DSSS_SYNC_Blocks_Late_PktDet" TagVisibility "global" } Block { BlockType Goto Name "Goto26" SID "18031" Position [235, 1355, 480, 1375] ZOrder -10 ShowName off GotoTag "regRx_OFDM_Rx_Req_Pkt_Det" TagVisibility "global" } Block { BlockType Goto Name "Goto3" SID "3849" Position [230, 230, 430, 250] ShowName off GotoTag "regRx_BYPASS_CFO_EST" TagVisibility "global" } Block { BlockType Goto Name "Goto4" SID "3850" Position [230, 285, 430, 305] ShowName off GotoTag "regRx_Record_Chan_Est_Pkt_Buf" TagVisibility "global" } Block { BlockType Goto Name "Goto5" SID "3851" Position [230, 140, 430, 160] ShowName off GotoTag "regRx_PKT_BUF_H_EST_ORDER_SWAP" TagVisibility "global" } Block { BlockType Goto Name "Goto6" SID "3852" Position [230, 345, 430, 365] ShowName off GotoTag "regRx_switchingDiv_En" TagVisibility "global" } Block { BlockType Goto Name "Goto7" SID "3853" Position [230, 850, 430, 870] ShowName off GotoTag "regRx_noSwitching_AntSel" TagVisibility "global" } Block { BlockType Goto Name "Goto8" SID "3854" Position [230, 465, 430, 485] ShowName off GotoTag "regRx_pktDetEn_RFA" TagVisibility "global" } Block { BlockType Goto Name "Goto9" SID "3855" Position [230, 525, 430, 545] ShowName off GotoTag "regRx_pktDetEn_RFB" TagVisibility "global" } Block { BlockType Reference Name "b[0] " SID "3856" Ports [1, 1] Position [110, 28, 150, 42] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9" ".22 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22" " 9.22 7.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');por" "t_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[10]" SID "3857" Ports [1, 1] Position [110, 528, 150, 542] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "10" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9" ".22 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22" " 9.22 7.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');por" "t_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[11]" SID "3858" Ports [1, 1] Position [110, 578, 150, 592] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "11" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9" ".22 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22" " 9.22 7.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');por" "t_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[12]" SID "3859" Ports [1, 1] Position [110, 638, 150, 652] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "12" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9" ".22 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22" " 9.22 7.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');por" "t_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[13]" SID "3860" Ports [1, 1] Position [110, 703, 150, 717] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "13" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9" ".22 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22" " 9.22 7.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');por" "t_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[14]" SID "3861" Ports [1, 1] Position [110, 773, 150, 787] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "14" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9" ".22 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22" " 9.22 7.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');por" "t_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[16:15]" SID "3862" Ports [1, 1] Position [110, 853, 150, 867] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "2" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "15" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9" ".22 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22" " 9.22 7.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');por" "t_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[1] " SID "3863" Ports [1, 1] Position [110, 58, 150, 72] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "1" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9" ".22 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22" " 9.22 7.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');por" "t_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[20:17]" SID "3864" Ports [1, 1] Position [110, 913, 150, 927] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "4" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "17" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9" ".22 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22" " 9.22 7.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');por" "t_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[21]" SID "3865" Ports [1, 1] Position [110, 983, 150, 997] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "21" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9" ".22 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22" " 9.22 7.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');por" "t_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[22]" SID "3866" Ports [1, 1] Position [110, 1028, 150, 1042] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "22" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9" ".22 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22" " 9.22 7.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');por" "t_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[23]" SID "3867" Ports [1, 1] Position [110, 1083, 150, 1097] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "23" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9" ".22 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22" " 9.22 7.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');por" "t_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[24]" SID "3868" Ports [1, 1] Position [110, 1143, 150, 1157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "24" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9" ".22 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22" " 9.22 7.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');por" "t_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[25]" SID "14913" Ports [1, 1] Position [110, 1188, 150, 1202] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "25" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9" ".22 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22" " 9.22 7.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');por" "t_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[26]" SID "15805" Ports [1, 1] Position [110, 1228, 150, 1242] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "26" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9" ".22 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22" " 9.22 7.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');por" "t_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[27]" SID "17475" Ports [1, 1] Position [110, 1278, 150, 1292] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "27" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9" ".22 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22" " 9.22 7.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');por" "t_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[28]" SID "18024" Ports [1, 1] Position [110, 1318, 150, 1332] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "28" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9" ".22 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22" " 9.22 7.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');por" "t_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[29]" SID "18032" Ports [1, 1] Position [110, 1358, 150, 1372] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "29" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9" ".22 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22" " 9.22 7.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');por" "t_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[2]" SID "3869" Ports [1, 1] Position [110, 98, 150, 112] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "2" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9" ".22 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22" " 9.22 7.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');por" "t_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[31]" SID "14869" Ports [1, 1] Position [110, 1433, 150, 1447] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "31" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9" ".22 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22" " 9.22 7.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');por" "t_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[3]" SID "3870" Ports [1, 1] Position [110, 143, 150, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "3" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9" ".22 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22" " 9.22 7.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');por" "t_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[4]" SID "3871" Ports [1, 1] Position [110, 183, 150, 197] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "4" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9" ".22 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22" " 9.22 7.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');por" "t_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[5]" SID "3872" Ports [1, 1] Position [110, 233, 150, 247] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "5" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9" ".22 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22" " 9.22 7.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');por" "t_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[6]" SID "3873" Ports [1, 1] Position [110, 288, 150, 302] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "6" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9" ".22 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22" " 9.22 7.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');por" "t_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[7]" SID "3874" Ports [1, 1] Position [110, 348, 150, 362] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "7" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9" ".22 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22" " 9.22 7.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');por" "t_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[8]" SID "3875" Ports [1, 1] Position [110, 408, 150, 422] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "8" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9" ".22 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22" " 9.22 7.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');por" "t_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[9]" SID "3876" Ports [1, 1] Position [110, 468, 150, 482] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "9" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9" ".22 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22" " 9.22 7.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');por" "t_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Line { SrcBlock "32b" SrcPort 1 Points [15, 0] Branch { Points [0, 30] Branch { DstBlock "b[1] " DstPort 1 } Branch { Points [0, 40] Branch { DstBlock "b[2]" DstPort 1 } Branch { Points [0, 45] Branch { DstBlock "b[3]" DstPort 1 } Branch { Points [0, 40] Branch { DstBlock "b[4]" DstPort 1 } Branch { Points [0, 50] Branch { DstBlock "b[5]" DstPort 1 } Branch { Points [0, 55] Branch { DstBlock "b[6]" DstPort 1 } Branch { Points [0, 60] Branch { DstBlock "b[7]" DstPort 1 } Branch { Points [0, 60] Branch { Points [0, 60] Branch { DstBlock "b[9]" DstPort 1 } Branch { Points [0, 60] Branch { DstBlock "b[10]" DstPort 1 } Branch { Points [0, 50] Branch { Points [0, 60] Branch { DstBlock "b[12]" DstPort 1 } Branch { Points [0, 65] Branch { DstBlock "b[13]" DstPort 1 } Branch { Points [0, 70] Branch { DstBlock "b[14]" DstPort 1 } Branch { Points [0, 80] Branch { DstBlock "b[16:15]" DstPort 1 } Branch { Points [0, 60] Branch { DstBlock "b[20:17]" DstPort 1 } Branch { Points [0, 70] Branch { DstBlock "b[21]" DstPort 1 } Branch { Points [0, 45] Branch { DstBlock "b[22]" DstPort 1 } Branch { Points [0, 55] Branch { DstBlock "b[23]" DstPort 1 } Branch { Points [0, 60] Branch { DstBlock "b[24]" DstPort 1 } Branch { Points [0, 45] Branch { DstBlock "b[25]" DstPort 1 } Branch { Points [0, 40] Branch { DstBlock "b[26]" DstPort 1 } Branch { Points [0, 50] Branch { DstBlock "b[27]" DstPort 1 } Branch { Points [0, 40] Branch { DstBlock "b[28]" DstPort 1 } Branch { Points [0, 40] Branch { Points [0, 75] DstBlock "b[31]" DstPort 1 } Branch { DstBlock "b[29]" DstPort 1 } } } } } } } } } } } } } } } Branch { DstBlock "b[11]" DstPort 1 } } } } Branch { DstBlock "b[8]" DstPort 1 } } } } } } } } } Branch { DstBlock "b[0] " DstPort 1 } } Line { SrcBlock "b[0] " SrcPort 1 DstBlock "Goto17" DstPort 1 } Line { SrcBlock "b[1] " SrcPort 1 DstBlock "Goto1" DstPort 1 } Line { SrcBlock "b[2]" SrcPort 1 DstBlock "Goto20" DstPort 1 } Line { SrcBlock "b[3]" SrcPort 1 DstBlock "Goto5" DstPort 1 } Line { SrcBlock "b[4]" SrcPort 1 DstBlock "Goto2" DstPort 1 } Line { SrcBlock "b[5]" SrcPort 1 DstBlock "Goto3" DstPort 1 } Line { SrcBlock "b[6]" SrcPort 1 DstBlock "Goto4" DstPort 1 } Line { SrcBlock "b[7]" SrcPort 1 DstBlock "Goto6" DstPort 1 } Line { SrcBlock "b[16:15]" SrcPort 1 DstBlock "Goto7" DstPort 1 } Line { SrcBlock "b[9]" SrcPort 1 DstBlock "Goto8" DstPort 1 } Line { SrcBlock "b[10]" SrcPort 1 DstBlock "Goto9" DstPort 1 } Line { SrcBlock "b[13]" SrcPort 1 DstBlock "Goto10" DstPort 1 } Line { SrcBlock "b[11]" SrcPort 1 DstBlock "Goto11" DstPort 1 } Line { SrcBlock "b[12]" SrcPort 1 DstBlock "Goto12" DstPort 1 } Line { SrcBlock "b[14]" SrcPort 1 DstBlock "Goto" DstPort 1 } Line { SrcBlock "b[20:17]" SrcPort 1 DstBlock "Goto14" DstPort 1 } Line { SrcBlock "b[21]" SrcPort 1 DstBlock "Goto15" DstPort 1 } Line { SrcBlock "b[22]" SrcPort 1 DstBlock "Goto16" DstPort 1 } Line { SrcBlock "b[23]" SrcPort 1 DstBlock "Goto18" DstPort 1 } Line { SrcBlock "b[24]" SrcPort 1 DstBlock "Goto19" DstPort 1 } Line { SrcBlock "b[31]" SrcPort 1 DstBlock "Goto21" DstPort 1 } Line { SrcBlock "b[25]" SrcPort 1 DstBlock "Goto22" DstPort 1 } Line { SrcBlock "b[26]" SrcPort 1 DstBlock "Goto23" DstPort 1 } Line { SrcBlock "b[8]" SrcPort 1 DstBlock "Goto13" DstPort 1 } Line { SrcBlock "b[27]" SrcPort 1 DstBlock "Goto24" DstPort 1 } Line { SrcBlock "b[28]" SrcPort 1 DstBlock "Goto25" DstPort 1 } Line { SrcBlock "b[29]" SrcPort 1 DstBlock "Goto26" DstPort 1 } } } Block { BlockType Reference Name "Constant1" SID "3877" Ports [0, 1] Position [1550, 245, 1575, 265] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Boolean" arith_type "Boolean" n_bits "30" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period on period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,20,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 20 20 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[12.22 12.22 14.2" "2 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[10.22 10.22 12.22 12.22 10.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatch([9.55 1" "6.44 14.44 12.44 10.44 7.55 9.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nfprin" "tf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant2" SID "3878" Ports [0, 1] Position [1555, 490, 1580, 510] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Boolean" arith_type "Boolean" n_bits "30" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period on period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,20,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 20 20 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[12.22 12.22 14.2" "2 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[10.22 10.22 12.22 12.22 10.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatch([9.55 1" "6.44 14.44 12.44 10.44 7.55 9.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nfprin" "tf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant3" SID "3879" Ports [0, 1] Position [1555, 360, 1580, 380] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Boolean" arith_type "Boolean" n_bits "30" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period on period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,20,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 20 20 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[12.22 12.22 14.2" "2 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[10.22 10.22 12.22 12.22 10.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatch([9.55 1" "6.44 14.44 12.44 10.44 7.55 9.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nfprin" "tf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant4" SID "3880" Ports [0, 1] Position [1555, 595, 1580, 615] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Boolean" arith_type "Boolean" n_bits "30" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period on period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,20,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 20 20 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[12.22 12.22 14.2" "2 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[10.22 10.22 12.22 12.22 10.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatch([9.55 1" "6.44 14.44 12.44 10.44 7.55 9.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nfprin" "tf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant5" SID "3881" Ports [0, 1] Position [1555, 685, 1580, 705] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Boolean" arith_type "Boolean" n_bits "30" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period on period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,20,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 20 20 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[12.22 12.22 14.2" "2 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[10.22 10.22 12.22 12.22 10.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatch([9.55 1" "6.44 14.44 12.44 10.44 7.55 9.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nfprin" "tf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant6" SID "17435" Ports [0, 1] Position [1550, 130, 1575, 150] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Boolean" arith_type "Boolean" n_bits "30" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period on period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,20,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 20 20 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[12.22 12.22 14.2" "2 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[10.22 10.22 12.22 12.22 10.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatch([9.55 1" "6.44 14.44 12.44 10.44 7.55 9.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nfprin" "tf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant7" SID "17450" Ports [0, 1] Position [1550, 45, 1575, 65] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Boolean" arith_type "Boolean" n_bits "30" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period on period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,20,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 20 20 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[12.22 12.22 14.2" "2 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[10.22 10.22 12.22 12.22 10.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatch([9.55 1" "6.44 14.44 12.44 10.44 7.55 9.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nfprin" "tf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant8" SID "18159" Ports [0, 1] Position [1555, 770, 1580, 790] ForegroundColor "red" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Boolean" arith_type "Boolean" n_bits "30" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period on period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,20,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 20 20 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[12.22 12.22 14.2" "2 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[10.22 10.22 12.22 12.22 10.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatch([9.55 1" "6.44 14.44 12.44 10.44 7.55 9.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nfprin" "tf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert" SID "3882" Ports [1, 1] Position [1485, 215, 1515, 235] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "30,20,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 20 20 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output'," "1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "3883" Ports [1, 1] Position [1350, 330, 1380, 350] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "32" bin_pt "31" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "30,20,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 20 20 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output'," "1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "3884" Ports [1, 1] Position [1485, 565, 1515, 585] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "30,20,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 20 20 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output'," "1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert3" SID "3885" Ports [1, 1] Position [1485, 460, 1515, 480] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "30,20,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 20 20 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output'," "1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert4" SID "3886" Ports [1, 1] Position [1485, 655, 1515, 675] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "30,20,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 20 20 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output'," "1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert5" SID "17436" Ports [1, 1] Position [1480, 100, 1510, 120] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "30,20,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 20 20 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output'," "1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert6" SID "17451" Ports [1, 1] Position [1480, 15, 1510, 35] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "30,20,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 20 20 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output'," "1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert7" SID "18160" Ports [1, 1] Position [1485, 740, 1515, 760] ForegroundColor "red" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "30,20,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 20 20 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output'," "1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Down Sample1" SID "3887" Ports [1, 1] Position [555, 913, 580, 937] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Down Sample" SourceType "Xilinx Down Sampler Block" infoedit "Hardware notes: Sample and Latency controls determine the hardware implementation. The cost in hardwa" "re of different implementations varies considerably; press Help for details." sample_ratio "8" sample_phase "Last Value of Frame (most efficient)" en off latency "1" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,356,300" block_type "dsamp" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,24,1,1,white,blue,0,dee880ed,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 24 24 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 24 24 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[15.33 15.33 18" ".33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[12.33 12.33 15.33 15.33 12.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 1 1 ]);\npatch([" "8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 0.973 ]);\nfprintf(''" ",'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-1}\\newline " "','texmode','on');\ncolor('black');disp(' \\newline{\\fontsize{14pt}\\bf\\downarrow}8','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Down Sample16" SID "3888" Ports [1, 1] Position [555, 868, 580, 892] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Down Sample" SourceType "Xilinx Down Sampler Block" infoedit "Hardware notes: Sample and Latency controls determine the hardware implementation. The cost in hardwa" "re of different implementations varies considerably; press Help for details." sample_ratio "8" sample_phase "Last Value of Frame (most efficient)" en off latency "1" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,356,300" block_type "dsamp" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,24,1,1,white,blue,0,dee880ed,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 24 24 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 24 24 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[15.33 15.33 18" ".33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[12.33 12.33 15.33 15.33 12.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 1 1 ]);\npatch([" "8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 0.973 ]);\nfprintf(''" ",'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-1}\\newline " "','texmode','on');\ncolor('black');disp(' \\newline{\\fontsize{14pt}\\bf\\downarrow}8','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Down Sample2" SID "3889" Ports [1, 1] Position [555, 958, 580, 982] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Down Sample" SourceType "Xilinx Down Sampler Block" infoedit "Hardware notes: Sample and Latency controls determine the hardware implementation. The cost in hardwa" "re of different implementations varies considerably; press Help for details." sample_ratio "8" sample_phase "Last Value of Frame (most efficient)" en off latency "1" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,356,300" block_type "dsamp" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,24,1,1,white,blue,0,dee880ed,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 24 24 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 24 24 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[15.33 15.33 18" ".33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[12.33 12.33 15.33 15.33 12.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 1 1 ]);\npatch([" "8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 0.973 ]);\nfprintf(''" ",'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-1}\\newline " "','texmode','on');\ncolor('black');disp(' \\newline{\\fontsize{14pt}\\bf\\downarrow}8','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Down Sample6" SID "3893" Ports [1, 1] Position [310, 1133, 335, 1157] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Down Sample" SourceType "Xilinx Down Sampler Block" infoedit "Hardware notes: Sample and Latency controls determine the hardware implementation. The cost in hardwa" "re of different implementations varies considerably; press Help for details." sample_ratio "16" sample_phase "Last Value of Frame (most efficient)" en off latency "1" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,356,300" block_type "dsamp" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,24,1,1,white,blue,0,40e65a2b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 24 24 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 24 24 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[15.33 15.33 18" ".33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[12.33 12.33 15.33 15.33 12.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 1 1 ]);\npatch([" "8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 0.973 ]);\nfprintf(''" ",'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-1}\\newline " "','texmode','on');\ncolor('black');disp(' \\newline{\\fontsize{14pt}\\bf\\downarrow}16','texmode','on');\nfprintf('" "','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Fanout" SID "3895" Ports [3] Position [705, 857, 780, 993] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Fanout" Location [708, 910, 1220, 1211] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "156" Block { BlockType Inport Name "Corr_Thresh" SID "3896" Position [220, 353, 250, 367] IconDisplay "Port number" } Block { BlockType Inport Name "E_Thresh" SID "3897" Position [220, 463, 250, 477] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "MinDur" SID "3898" Position [220, 603, 250, 617] Port "3" IconDisplay "Port number" } Block { BlockType Goto Name "Goto1" SID "3899" Position [465, 260, 665, 280] ShowName off GotoTag "regRx_PktDet_CorrThresh_A" TagVisibility "global" } Block { BlockType Goto Name "Goto10" SID "3900" Position [400, 385, 600, 405] ShowName off GotoTag "regRx_PktDet_EnergyThresh_A" TagVisibility "global" } Block { BlockType Goto Name "Goto12" SID "3901" Position [400, 550, 610, 570] ShowName off GotoTag "regPktDet_pktDetMinDuration_autoCorr_B" TagVisibility "global" } Block { BlockType Goto Name "Goto13" SID "3902" Position [400, 576, 610, 594] ShowName off GotoTag "regPktDet_pktDetMinDuration_autoCorr_C" TagVisibility "global" } Block { BlockType Goto Name "Goto14" SID "3903" Position [400, 602, 610, 618] ShowName off GotoTag "regPktDet_pktDetMinDuration_autoCorr_D" TagVisibility "global" } Block { BlockType Goto Name "Goto2" SID "3904" Position [465, 290, 665, 310] ShowName off GotoTag "regRx_PktDet_CorrThresh_B" TagVisibility "global" } Block { BlockType Goto Name "Goto3" SID "3905" Position [465, 320, 665, 340] ShowName off GotoTag "regRx_PktDet_CorrThresh_C" TagVisibility "global" } Block { BlockType Goto Name "Goto4" SID "3906" Position [465, 350, 665, 370] ShowName off GotoTag "regRx_PktDet_CorrThresh_D" TagVisibility "global" } Block { BlockType Goto Name "Goto5" SID "3907" Position [400, 460, 600, 480] ShowName off GotoTag "regRx_PktDet_EnergyThresh_D" TagVisibility "global" } Block { BlockType Goto Name "Goto6" SID "3908" Position [400, 435, 600, 455] ShowName off GotoTag "regRx_PktDet_EnergyThresh_C" TagVisibility "global" } Block { BlockType Goto Name "Goto8" SID "3909" Position [400, 526, 610, 544] ShowName off GotoTag "regPktDet_pktDetMinDuration_autoCorr_A" TagVisibility "global" } Block { BlockType Goto Name "Goto9" SID "3910" Position [400, 410, 600, 430] ShowName off GotoTag "regRx_PktDet_EnergyThresh_B" TagVisibility "global" } Block { BlockType Reference Name "Register1" SID "3911" Ports [1, 1] Position [310, 317, 335, 343] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 " "16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register10" SID "3912" Ports [1, 1] Position [310, 572, 335, 598] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 " "16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register11" SID "3913" Ports [1, 1] Position [310, 597, 335, 623] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 " "16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "3914" Ports [1, 1] Position [310, 287, 335, 313] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 " "16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register20" SID "3915" Ports [1, 1] Position [310, 347, 335, 373] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 " "16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register3" SID "3916" Ports [1, 1] Position [310, 257, 335, 283] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 " "16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register4" SID "3917" Ports [1, 1] Position [310, 382, 335, 408] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 " "16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register5" SID "3918" Ports [1, 1] Position [310, 407, 335, 433] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 " "16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register6" SID "3919" Ports [1, 1] Position [310, 432, 335, 458] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 " "16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register7" SID "3920" Ports [1, 1] Position [310, 457, 335, 483] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 " "16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register8" SID "3921" Ports [1, 1] Position [310, 522, 335, 548] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 " "16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register9" SID "3922" Ports [1, 1] Position [310, 547, 335, 573] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 " "16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Line { SrcBlock "Corr_Thresh" SrcPort 1 Points [25, 0] Branch { DstBlock "Register20" DstPort 1 } Branch { Points [0, -30] Branch { DstBlock "Register1" DstPort 1 } Branch { Points [0, -30] Branch { DstBlock "Register2" DstPort 1 } Branch { Points [0, -30] DstBlock "Register3" DstPort 1 } } } } Line { SrcBlock "E_Thresh" SrcPort 1 Points [25, 0] Branch { Points [0, -25] Branch { Points [0, -25] Branch { Points [0, -25] DstBlock "Register4" DstPort 1 } Branch { DstBlock "Register5" DstPort 1 } } Branch { DstBlock "Register6" DstPort 1 } } Branch { DstBlock "Register7" DstPort 1 } } Line { SrcBlock "MinDur" SrcPort 1 Points [25, 0] Branch { Points [0, -25] Branch { Points [0, -25] Branch { Points [0, -25] DstBlock "Register8" DstPort 1 } Branch { DstBlock "Register9" DstPort 1 } } Branch { DstBlock "Register10" DstPort 1 } } Branch { DstBlock "Register11" DstPort 1 } } Line { SrcBlock "Register20" SrcPort 1 DstBlock "Goto4" DstPort 1 } Line { SrcBlock "Register1" SrcPort 1 DstBlock "Goto3" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Goto2" DstPort 1 } Line { SrcBlock "Register3" SrcPort 1 DstBlock "Goto1" DstPort 1 } Line { SrcBlock "Register4" SrcPort 1 DstBlock "Goto10" DstPort 1 } Line { SrcBlock "Register5" SrcPort 1 DstBlock "Goto9" DstPort 1 } Line { SrcBlock "Register6" SrcPort 1 DstBlock "Goto6" DstPort 1 } Line { SrcBlock "Register7" SrcPort 1 DstBlock "Goto5" DstPort 1 } Line { SrcBlock "Register8" SrcPort 1 DstBlock "Goto8" DstPort 1 } Line { SrcBlock "Register9" SrcPort 1 DstBlock "Goto12" DstPort 1 } Line { SrcBlock "Register10" SrcPort 1 DstBlock "Goto13" DstPort 1 } Line { SrcBlock "Register11" SrcPort 1 DstBlock "Goto14" DstPort 1 } } } Block { BlockType SubSystem Name "Fanout1" SID "3923" Ports [3] Position [570, 1121, 620, 1259] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Fanout1" Location [161, 165, 1952, 1483] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "156" Block { BlockType Inport Name "In1" SID "3924" Position [220, 353, 250, 367] IconDisplay "Port number" } Block { BlockType Inport Name "In2" SID "3925" Position [220, 498, 250, 512] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "In3" SID "3926" Position [220, 643, 250, 657] Port "3" IconDisplay "Port number" } Block { BlockType Goto Name "Goto1" SID "3927" Position [375, 290, 560, 310] ShowName off GotoTag "regRx_RSSI_SUM_LEN_B" TagVisibility "global" } Block { BlockType Goto Name "Goto2" SID "3928" Position [375, 320, 560, 340] ShowName off GotoTag "regRx_RSSI_SUM_LEN_C" TagVisibility "global" } Block { BlockType Goto Name "Goto22" SID "3929" Position [375, 260, 560, 280] ShowName off GotoTag "regRx_RSSI_SUM_LEN_A" TagVisibility "global" } Block { BlockType Goto Name "Goto23" SID "3930" Position [375, 405, 560, 425] ShowName off GotoTag "regRx_PKTDET_RSSI_THRESH_A" TagVisibility "global" } Block { BlockType Goto Name "Goto24" SID "3931" Position [385, 550, 570, 570] ShowName off GotoTag "regRx_PKTDET_RSSI_MIN_DUR_A" TagVisibility "global" } Block { BlockType Goto Name "Goto3" SID "3932" Position [375, 350, 560, 370] ShowName off GotoTag "regRx_RSSI_SUM_LEN_D" TagVisibility "global" } Block { BlockType Goto Name "Goto4" SID "3933" Position [375, 435, 560, 455] ShowName off GotoTag "regRx_PKTDET_RSSI_THRESH_B" TagVisibility "global" } Block { BlockType Goto Name "Goto5" SID "3934" Position [375, 465, 560, 485] ShowName off GotoTag "regRx_PKTDET_RSSI_THRESH_C" TagVisibility "global" } Block { BlockType Goto Name "Goto6" SID "3935" Position [375, 495, 560, 515] ShowName off GotoTag "regRx_PKTDET_RSSI_THRESH_D" TagVisibility "global" } Block { BlockType Goto Name "Goto7" SID "3936" Position [385, 580, 570, 600] ShowName off GotoTag "regRx_PKTDET_RSSI_MIN_DUR_B" TagVisibility "global" } Block { BlockType Goto Name "Goto8" SID "3937" Position [385, 610, 570, 630] ShowName off GotoTag "regRx_PKTDET_RSSI_MIN_DUR_C" TagVisibility "global" } Block { BlockType Goto Name "Goto9" SID "3938" Position [385, 640, 570, 660] ShowName off GotoTag "regRx_PKTDET_RSSI_MIN_DUR_D" TagVisibility "global" } Block { BlockType Reference Name "Register1" SID "3939" Ports [1, 1] Position [310, 317, 335, 343] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 " "16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register10" SID "3940" Ports [1, 1] Position [310, 637, 335, 663] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 " "16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register11" SID "3941" Ports [1, 1] Position [310, 547, 335, 573] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 " "16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "3942" Ports [1, 1] Position [310, 287, 335, 313] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 " "16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register20" SID "3943" Ports [1, 1] Position [310, 347, 335, 373] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 " "16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register3" SID "3944" Ports [1, 1] Position [310, 257, 335, 283] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 " "16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register4" SID "3945" Ports [1, 1] Position [310, 462, 335, 488] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 " "16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register5" SID "3946" Ports [1, 1] Position [310, 432, 335, 458] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 " "16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register6" SID "3947" Ports [1, 1] Position [310, 492, 335, 518] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 " "16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register7" SID "3948" Ports [1, 1] Position [310, 402, 335, 428] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 " "16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register8" SID "3949" Ports [1, 1] Position [310, 607, 335, 633] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 " "16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register9" SID "3950" Ports [1, 1] Position [310, 577, 335, 603] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 " "16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Line { SrcBlock "Register3" SrcPort 1 DstBlock "Goto22" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Goto1" DstPort 1 } Line { SrcBlock "Register1" SrcPort 1 DstBlock "Goto2" DstPort 1 } Line { SrcBlock "Register20" SrcPort 1 DstBlock "Goto3" DstPort 1 } Line { SrcBlock "In1" SrcPort 1 Points [25, 0] Branch { Points [0, -30] Branch { Points [0, -30] Branch { Points [0, -30] DstBlock "Register3" DstPort 1 } Branch { DstBlock "Register2" DstPort 1 } } Branch { DstBlock "Register1" DstPort 1 } } Branch { DstBlock "Register20" DstPort 1 } } Line { SrcBlock "In2" SrcPort 1 Points [25, 0] Branch { DstBlock "Register6" DstPort 1 } Branch { Points [0, -30] Branch { DstBlock "Register4" DstPort 1 } Branch { Points [0, -30] Branch { DstBlock "Register5" DstPort 1 } Branch { Points [0, -30] DstBlock "Register7" DstPort 1 } } } } Line { SrcBlock "In3" SrcPort 1 Points [25, 0] Branch { Points [0, -30] Branch { Points [0, -30] Branch { Points [0, -30] DstBlock "Register11" DstPort 1 } Branch { DstBlock "Register9" DstPort 1 } } Branch { DstBlock "Register8" DstPort 1 } } Branch { DstBlock "Register10" DstPort 1 } } Line { SrcBlock "Register11" SrcPort 1 DstBlock "Goto24" DstPort 1 } Line { SrcBlock "Register9" SrcPort 1 DstBlock "Goto7" DstPort 1 } Line { SrcBlock "Register8" SrcPort 1 DstBlock "Goto8" DstPort 1 } Line { SrcBlock "Register10" SrcPort 1 DstBlock "Goto9" DstPort 1 } Line { SrcBlock "Register7" SrcPort 1 DstBlock "Goto23" DstPort 1 } Line { SrcBlock "Register5" SrcPort 1 DstBlock "Goto4" DstPort 1 } Line { SrcBlock "Register4" SrcPort 1 DstBlock "Goto5" DstPort 1 } Line { SrcBlock "Register6" SrcPort 1 DstBlock "Goto6" DstPort 1 } } } Block { BlockType SubSystem Name "Fanout2" SID "3951" Ports [2] Position [1695, 2095, 1775, 2230] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Fanout2" Location [708, 910, 1220, 1211] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "156" Block { BlockType Inport Name "Corr_Thresh" SID "3952" Position [220, 353, 250, 367] IconDisplay "Port number" } Block { BlockType Inport Name "E_Thresh" SID "3953" Position [290, 493, 320, 507] Port "2" IconDisplay "Port number" } Block { BlockType Goto Name "Goto1" SID "3954" Position [465, 260, 665, 280] ShowName off GotoTag "regRx_PktDet_CorrThresh_DSSS_A" TagVisibility "global" } Block { BlockType Goto Name "Goto10" SID "3955" Position [470, 415, 670, 435] ShowName off GotoTag "regRx_PktDet_EnergyThresh_DSSS_A" TagVisibility "global" } Block { BlockType Goto Name "Goto2" SID "3956" Position [465, 290, 665, 310] ShowName off GotoTag "regRx_PktDet_CorrThresh_DSSS_B" TagVisibility "global" } Block { BlockType Goto Name "Goto3" SID "3957" Position [465, 320, 665, 340] ShowName off GotoTag "regRx_PktDet_CorrThresh_DSSS_C" TagVisibility "global" } Block { BlockType Goto Name "Goto4" SID "3958" Position [465, 350, 665, 370] ShowName off GotoTag "regRx_PktDet_CorrThresh_DSSS_D" TagVisibility "global" } Block { BlockType Goto Name "Goto5" SID "3959" Position [470, 490, 670, 510] ShowName off GotoTag "regRx_PktDet_EnergyThresh_DSSS_D" TagVisibility "global" } Block { BlockType Goto Name "Goto6" SID "3960" Position [470, 465, 670, 485] ShowName off GotoTag "regRx_PktDet_EnergyThresh_DSSS_C" TagVisibility "global" } Block { BlockType Goto Name "Goto9" SID "3961" Position [470, 440, 670, 460] ShowName off GotoTag "regRx_PktDet_EnergyThresh_DSSS_B" TagVisibility "global" } Block { BlockType Reference Name "Register1" SID "3962" Ports [1, 1] Position [310, 317, 335, 343] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 " "16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "3963" Ports [1, 1] Position [310, 287, 335, 313] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 " "16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register20" SID "3964" Ports [1, 1] Position [310, 347, 335, 373] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 " "16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register3" SID "3965" Ports [1, 1] Position [310, 257, 335, 283] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 " "16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register4" SID "3966" Ports [1, 1] Position [380, 412, 405, 438] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 " "16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register5" SID "3967" Ports [1, 1] Position [380, 437, 405, 463] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 " "16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register6" SID "3968" Ports [1, 1] Position [380, 462, 405, 488] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 " "16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register7" SID "3969" Ports [1, 1] Position [380, 487, 405, 513] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 " "16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Line { SrcBlock "Register3" SrcPort 1 DstBlock "Goto1" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Goto2" DstPort 1 } Line { SrcBlock "Register1" SrcPort 1 DstBlock "Goto3" DstPort 1 } Line { SrcBlock "Register20" SrcPort 1 DstBlock "Goto4" DstPort 1 } Line { SrcBlock "Corr_Thresh" SrcPort 1 Points [25, 0] Branch { Points [0, -30] Branch { Points [0, -30] Branch { Points [0, -30] DstBlock "Register3" DstPort 1 } Branch { DstBlock "Register2" DstPort 1 } } Branch { DstBlock "Register1" DstPort 1 } } Branch { DstBlock "Register20" DstPort 1 } } Line { SrcBlock "E_Thresh" SrcPort 1 Points [25, 0] Branch { Points [0, -25] Branch { Points [0, -25] Branch { Points [0, -25] DstBlock "Register4" DstPort 1 } Branch { DstBlock "Register5" DstPort 1 } } Branch { DstBlock "Register6" DstPort 1 } } Branch { DstBlock "Register7" DstPort 1 } } Line { SrcBlock "Register4" SrcPort 1 DstBlock "Goto10" DstPort 1 } Line { SrcBlock "Register5" SrcPort 1 DstBlock "Goto9" DstPort 1 } Line { SrcBlock "Register6" SrcPort 1 DstBlock "Goto6" DstPort 1 } Line { SrcBlock "Register7" SrcPort 1 DstBlock "Goto5" DstPort 1 } } } Block { BlockType Reference Name "From Register" SID "3970" Ports [0, 1] Position [230, 1130, 270, 1160] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'PKTDET_RSSI_CONFIG'" init "REG_RX_PKTDET_RSSI_CONFIG" period "1" ownership "Locally owned and initialized" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "fromreg" sg_icon_stat "40,30,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 30 30 0 ]);\npatch([11.1 16.88 20.88 24.88 28.88 20.88 15.1 11.1 ],[19.44 19.44 23.4" "4 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([15.1 20.88 16.88 11.1 15.1 ],[15.44 15.44 19.44 19.44 15.44 ]," "[0.931 0.946 0.973 ]);\npatch([11.1 16.88 20.88 15.1 11.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([15." "1 28.88 24.88 20.88 16.88 11.1 15.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "From Register1" SID "3971" Ports [0, 1] Position [230, 1270, 270, 1300] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'FFT_Config'" init "REG_RX_FFT_Config" period "1" ownership "Locally owned and initialized" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "fromreg" sg_icon_stat "40,30,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 30 30 0 ]);\npatch([11.1 16.88 20.88 24.88 28.88 20.88 15.1 11.1 ],[19.44 19.44 23.4" "4 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([15.1 20.88 16.88 11.1 15.1 ],[15.44 15.44 19.44 19.44 15.44 ]," "[0.931 0.946 0.973 ]);\npatch([11.1 16.88 20.88 15.1 11.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([15." "1 28.88 24.88 20.88 16.88 11.1 15.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "From Register10" SID "3972" Ports [0, 1] Position [230, 1515, 270, 1545] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'PKTBUF_MAX_WRITE_ADDR'" init "REG_RX_PKT_BUF_Max_Write_Addr" period "1" ownership "Locally owned and initialized" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "fromreg" sg_icon_stat "40,30,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 30 30 0 ]);\npatch([11.1 16.88 20.88 24.88 28.88 20.88 15.1 11.1 ],[19.44 19.44 23.4" "4 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([15.1 20.88 16.88 11.1 15.1 ],[15.44 15.44 19.44 19.44 15.44 ]," "[0.931 0.946 0.973 ]);\npatch([11.1 16.88 20.88 15.1 11.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([15." "1 28.88 24.88 20.88 16.88 11.1 15.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "From Register11" SID "3973" Ports [0, 1] Position [240, 745, 280, 775] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'PHY_CCA_CONFIG'" init "REG_RX_CCA_CONFIG" period "1" ownership "Locally owned and initialized" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "fromreg" sg_icon_stat "40,30,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 30 30 0 ]);\npatch([11.1 16.88 20.88 24.88 28.88 20.88 15.1 11.1 ],[19.44 19.44 23.4" "4 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([15.1 20.88 16.88 11.1 15.1 ],[15.44 15.44 19.44 19.44 15.44 ]," "[0.931 0.946 0.973 ]);\npatch([11.1 16.88 20.88 15.1 11.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([15." "1 28.88 24.88 20.88 16.88 11.1 15.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "From Register12" SID "3974" Ports [0, 1] Position [1230, 1025, 1270, 1055] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'LTS_Corr_Config'" init "REG_RX_LTS_Corr_Confg" period "1" ownership "Locally owned and initialized" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "fromreg" sg_icon_stat "40,30,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 30 30 0 ]);\npatch([11.1 16.88 20.88 24.88 28.88 20.88 15.1 11.1 ],[19.44 19.44 23.4" "4 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([15.1 20.88 16.88 11.1 15.1 ],[15.44 15.44 19.44 19.44 15.44 ]," "[0.931 0.946 0.973 ]);\npatch([11.1 16.88 20.88 15.1 11.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([15." "1 28.88 24.88 20.88 16.88 11.1 15.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "From Register13" SID "3975" Ports [0, 1] Position [1230, 2115, 1270, 2145] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'PKTDET_DSSS_CONFIG'" init "REG_RX_PktDet_DSSS_Config" period "1" ownership "Locally owned and initialized" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "fromreg" sg_icon_stat "40,30,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 30 30 0 ]);\npatch([11.1 16.88 20.88 24.88 28.88 20.88 15.1 11.1 ],[19.44 19.44 23.4" "4 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([15.1 20.88 16.88 11.1 15.1 ],[15.44 15.44 19.44 19.44 15.44 ]," "[0.931 0.946 0.973 ]);\npatch([11.1 16.88 20.88 15.1 11.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([15." "1 28.88 24.88 20.88 16.88 11.1 15.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "From Register14" SID "3976" Ports [0, 1] Position [1230, 920, 1270, 950] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'LTS_Corr_Thresh'" init "REG_RX_LTS_Corr_Thresh" period "1" ownership "Locally owned and initialized" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "fromreg" sg_icon_stat "40,30,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 30 30 0 ]);\npatch([11.1 16.88 20.88 24.88 28.88 20.88 15.1 11.1 ],[19.44 19.44 23.4" "4 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([15.1 20.88 16.88 11.1 15.1 ],[15.44 15.44 19.44 19.44 15.44 ]," "[0.931 0.946 0.973 ]);\npatch([11.1 16.88 20.88 15.1 11.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([15." "1 28.88 24.88 20.88 16.88 11.1 15.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "From Register15" SID "9778" Ports [0, 1] Position [1230, 1385, 1270, 1415] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'CHAN_EST_SMOOTHING'" init "REG_RX_Chan_Est_Smoothing" period "1" ownership "Locally owned and initialized" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "fromreg" sg_icon_stat "40,30,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 30 30 0 ]);\npatch([11.1 16.88 20.88 24.88 28.88 20.88 15.1 11.1 ],[19.44 19.44 23.4" "4 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([15.1 20.88 16.88 11.1 15.1 ],[15.44 15.44 19.44 19.44 15.44 ]," "[0.931 0.946 0.973 ]);\npatch([11.1 16.88 20.88 15.1 11.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([15." "1 28.88 24.88 20.88 16.88 11.1 15.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "From Register16" SID "11777" Ports [0, 1] Position [1230, 1210, 1270, 1240] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'LTS_Corr_PeakType_Thresh'" init "REG_RX_LTS_Corr_PeakType_Thresh" period "1" ownership "Locally owned and initialized" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "fromreg" sg_icon_stat "40,30,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 30 30 0 ]);\npatch([11.1 16.88 20.88 24.88 28.88 20.88 15.1 11.1 ],[19.44 19.44 23.4" "4 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([15.1 20.88 16.88 11.1 15.1 ],[15.44 15.44 19.44 19.44 15.44 ]," "[0.931 0.946 0.973 ]);\npatch([11.1 16.88 20.88 15.1 11.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([15." "1 28.88 24.88 20.88 16.88 11.1 15.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "From Register17" SID "15731" Ports [0, 1] Position [1230, 1960, 1270, 1990] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'TARGET_RAM_WR_DATA'" init "0" period "1" ownership "Locally owned and initialized" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "fromreg" sg_icon_stat "40,30,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 30 30 0 ]);\npatch([11.1 16.88 20.88 24.88 28.88 20.88 15.1 11.1 ],[19.44 19.44 23.4" "4 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([15.1 20.88 16.88 11.1 15.1 ],[15.44 15.44 19.44 19.44 15.44 ]," "[0.931 0.946 0.973 ]);\npatch([11.1 16.88 20.88 15.1 11.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([15." "1 28.88 24.88 20.88 16.88 11.1 15.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "From Register18" SID "15732" Ports [0, 1] Position [1230, 2035, 1270, 2065] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'MASK_1_RAM_WR_DATA'" init "0" period "1" ownership "Locally owned and initialized" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "fromreg" sg_icon_stat "40,30,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 30 30 0 ]);\npatch([11.1 16.88 20.88 24.88 28.88 20.88 15.1 11.1 ],[19.44 19.44 23.4" "4 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([15.1 20.88 16.88 11.1 15.1 ],[15.44 15.44 19.44 19.44 15.44 ]," "[0.931 0.946 0.973 ]);\npatch([11.1 16.88 20.88 15.1 11.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([15." "1 28.88 24.88 20.88 16.88 11.1 15.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "From Register2" SID "3977" Ports [0, 1] Position [250, 145, 290, 175] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'Control'" init "REG_RX_Control" period "1" ownership "Locally owned and initialized" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "fromreg" sg_icon_stat "40,30,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 30 30 0 ]);\npatch([11.1 16.88 20.88 24.88 28.88 20.88 15.1 11.1 ],[19.44 19.44 23.4" "4 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([15.1 20.88 16.88 11.1 15.1 ],[15.44 15.44 19.44 19.44 15.44 ]," "[0.931 0.946 0.973 ]);\npatch([11.1 16.88 20.88 15.1 11.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([15." "1 28.88 24.88 20.88 16.88 11.1 15.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "From Register3" SID "3978" Ports [0, 1] Position [255, 570, 295, 600] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'FEC_CONFIG'" init "REG_RX_FEC_Config" period "1" ownership "Locally owned and initialized" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "fromreg" sg_icon_stat "40,30,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 30 30 0 ]);\npatch([11.1 16.88 20.88 24.88 28.88 20.88 15.1 11.1 ],[19.44 19.44 23.4" "4 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([15.1 20.88 16.88 11.1 15.1 ],[15.44 15.44 19.44 19.44 15.44 ]," "[0.931 0.946 0.973 ]);\npatch([11.1 16.88 20.88 15.1 11.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([15." "1 28.88 24.88 20.88 16.88 11.1 15.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "From Register4" SID "3979" Ports [0, 1] Position [235, 865, 275, 895] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'PKTDET_AUTOCORR_CONFIG'" init "REG_RX_PktDet_AutoCorr_Config" period "1" ownership "Locally owned and initialized" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "fromreg" sg_icon_stat "40,30,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 30 30 0 ]);\npatch([11.1 16.88 20.88 24.88 28.88 20.88 15.1 11.1 ],[19.44 19.44 23.4" "4 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([15.1 20.88 16.88 11.1 15.1 ],[15.44 15.44 19.44 19.44 15.44 ]," "[0.931 0.946 0.973 ]);\npatch([11.1 16.88 20.88 15.1 11.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([15." "1 28.88 24.88 20.88 16.88 11.1 15.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "From Register5" SID "3980" Ports [0, 1] Position [255, 340, 295, 370] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'PKT_BUF_SEL'" init "REG_RX_PktBuf_Sel" period "1" ownership "Locally owned and initialized" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "fromreg" sg_icon_stat "40,30,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 30 30 0 ]);\npatch([11.1 16.88 20.88 24.88 28.88 20.88 15.1 11.1 ],[19.44 19.44 23.4" "4 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([15.1 20.88 16.88 11.1 15.1 ],[15.44 15.44 19.44 19.44 15.44 ]," "[0.931 0.946 0.973 ]);\npatch([11.1 16.88 20.88 15.1 11.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([15." "1 28.88 24.88 20.88 16.88 11.1 15.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "From Register6" SID "3981" Ports [0, 1] Position [1230, 1605, 1270, 1635] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'DSSS_RX_CONFIG'" init "REG_RX_DSSS_RX_CONFIG" period "1" ownership "Locally owned and initialized" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "fromreg" sg_icon_stat "40,30,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 30 30 0 ]);\npatch([11.1 16.88 20.88 24.88 28.88 20.88 15.1 11.1 ],[19.44 19.44 23.4" "4 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([15.1 20.88 16.88 11.1 15.1 ],[15.44 15.44 19.44 19.44 15.44 ]," "[0.931 0.946 0.973 ]);\npatch([11.1 16.88 20.88 15.1 11.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([15." "1 28.88 24.88 20.88 16.88 11.1 15.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "From Register7" SID "3982" Ports [0, 1] Position [270, 250, 310, 280] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'CONFIG'" init "REG_RX_Config" period "1" ownership "Locally owned and initialized" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "fromreg" sg_icon_stat "40,30,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 30 30 0 ]);\npatch([11.1 16.88 20.88 24.88 28.88 20.88 15.1 11.1 ],[19.44 19.44 23.4" "4 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([15.1 20.88 16.88 11.1 15.1 ],[15.44 15.44 19.44 19.44 15.44 ]," "[0.931 0.946 0.973 ]);\npatch([11.1 16.88 20.88 15.1 11.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([15." "1 28.88 24.88 20.88 16.88 11.1 15.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "From Register8" SID "3983" Ports [0, 1] Position [225, 1595, 265, 1625] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'RSSI_THRESH'" init "600" period "1" ownership "Locally owned and initialized" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "fromreg" sg_icon_stat "40,30,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 30 30 0 ]);\npatch([11.1 16.88 20.88 24.88 28.88 20.88 15.1 11.1 ],[19.44 19.44 23.4" "4 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([15.1 20.88 16.88 11.1 15.1 ],[15.44 15.44 19.44 19.44 15.44 ]," "[0.931 0.946 0.973 ]);\npatch([11.1 16.88 20.88 15.1 11.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([15." "1 28.88 24.88 20.88 16.88 11.1 15.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "From Register9" SID "15730" Ports [0, 1] Position [1230, 1825, 1270, 1855] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'RAMS_ADDR_WREN'" init "0" period "1" ownership "Locally owned and initialized" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "fromreg" sg_icon_stat "40,30,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 30 30 0 ]);\npatch([11.1 16.88 20.88 24.88 28.88 20.88 15.1 11.1 ],[19.44 19.44 23.4" "4 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([15.1 20.88 16.88 11.1 15.1 ],[15.44 15.44 19.44 19.44 15.44 ]," "[0.931 0.946 0.973 ]);\npatch([11.1 16.88 20.88 15.1 11.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([15." "1 28.88 24.88 20.88 16.88 11.1 15.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From1" SID "3985" Position [1070, 330, 1210, 350] ShowName off CloseFcn "tagdialog Close" GotoTag "regRx_CFO_Estimate" TagVisibility "global" } Block { BlockType From Name "From10" SID "17437" Position [1105, 99, 1280, 121] ShowName off CloseFcn "tagdialog Close" GotoTag "regRx_PktDetCount_OFDM" TagVisibility "global" } Block { BlockType From Name "From11" SID "17452" Position [1105, 14, 1280, 36] ShowName off CloseFcn "tagdialog Close" GotoTag "regRx_PktDetCount_DSSS" TagVisibility "global" } Block { BlockType From Name "From12" SID "18161" Position [965, 739, 1180, 761] ForegroundColor "red" ShowName off CloseFcn "tagdialog Close" GotoTag "reg_RFA_RXIQ_MAG_SUM_40SAMP" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType From Name "From2" SID "3986" Position [1145, 565, 1285, 585] ShowName off CloseFcn "tagdialog Close" GotoTag "RSSI_POST_AGC_AB" TagVisibility "global" } Block { BlockType From Name "From3" SID "3987" Position [1145, 460, 1285, 480] ShowName off CloseFcn "tagdialog Close" GotoTag "GAINS_POST_AGC" TagVisibility "global" } Block { BlockType From Name "From4" SID "3988" Position [1070, 215, 1210, 235] ShowName off CloseFcn "tagdialog Close" GotoTag "ANTENNA_SEL" TagVisibility "global" } Block { BlockType From Name "From5" SID "3989" Position [1070, 235, 1210, 255] ShowName off CloseFcn "tagdialog Close" GotoTag "DSSS_FCS_GOOD" TagVisibility "global" } Block { BlockType From Name "From6" SID "3990" Position [1070, 255, 1210, 275] ShowName off CloseFcn "tagdialog Close" GotoTag "OFDM_FCS_GOOD" TagVisibility "global" } Block { BlockType From Name "From7" SID "3991" Position [1070, 195, 1210, 215] ShowName off CloseFcn "tagdialog Close" GotoTag "PKTDET_STATUS_OFDM" TagVisibility "global" } Block { BlockType From Name "From8" SID "3992" Position [1145, 655, 1285, 675] ShowName off CloseFcn "tagdialog Close" GotoTag "RSSI_POST_AGC_CD" TagVisibility "global" } Block { BlockType From Name "From9" SID "3993" Position [1070, 175, 1210, 195] ShowName off CloseFcn "tagdialog Close" GotoTag "PKTDET_STATUS_DSSS" TagVisibility "global" } Block { BlockType Goto Name "Goto1" SID "3994" Position [650, 1275, 850, 1295] ShowName off GotoTag "regRx_NUM_SC" TagVisibility "global" } Block { BlockType Goto Name "Goto10" SID "3995" Position [1690, 1030, 1890, 1050] ShowName off GotoTag "regRx_PktDet_Timout" TagVisibility "global" } Block { BlockType Goto Name "Goto11" SID "15771" Position [1670, 1710, 1870, 1730] ShowName off GotoTag "regRx_DSSS_SFD_Timeout" TagVisibility "global" } Block { BlockType Goto Name "Goto12" SID "3997" Position [570, 1520, 770, 1540] ShowName off GotoTag "regRx_PktBuf_Max_WriteAddr" TagVisibility "global" } Block { BlockType Goto Name "Goto13" SID "3998" Position [625, 345, 825, 365] ShowName off GotoTag "regRx_OFDM_PKT_BUF_SEL" TagVisibility "global" } Block { BlockType Goto Name "Goto14" SID "15734" Position [1590, 1830, 1790, 1850] ShowName off GotoTag "reg_RAMs_Wr_Addr" TagVisibility "global" } Block { BlockType Goto Name "Goto15" SID "4000" Position [665, 1005, 850, 1025] ShowName off GotoTag "regRx_PKT_DET_RESET_EXT_DUR" TagVisibility "global" } Block { BlockType Goto Name "Goto16" SID "4001" Position [1645, 926, 1900, 944] ShowName off GotoTag "regRx_LongCorr_Thresh_lowSNR" TagVisibility "global" } Block { BlockType Goto Name "Goto17" SID "4002" Position [610, 750, 810, 770] ShowName off GotoTag "regRx_RSSI_CS_THRESH" TagVisibility "global" } Block { BlockType Goto Name "Goto18" SID "15735" Position [1590, 1920, 1790, 1940] ShowName off GotoTag "reg_Mask_1_WrEn" TagVisibility "global" } Block { BlockType Goto Name "Goto19" SID "9442" Position [625, 575, 825, 595] ShowName off GotoTag "regRx_FEC_SCALE_BPSK" TagVisibility "global" } Block { BlockType Goto Name "Goto2" SID "4004" Position [650, 1315, 850, 1335] ShowName off GotoTag "regRx_CP_LEN" TagVisibility "global" } Block { BlockType Goto Name "Goto20" SID "4005" Position [610, 805, 810, 825] ShowName off GotoTag "regRx_CCA_PostRx_Extension" TagVisibility "global" } Block { BlockType Goto Name "Goto21" SID "4006" Position [555, 1600, 755, 1620] ShowName off GotoTag "regRx_Debug_RSSI_THRESH" TagVisibility "global" } Block { BlockType Goto Name "Goto22" SID "9803" Position [1695, 1390, 1895, 1410] ShowName off GotoTag "regRx_Chan_Est_Smoothing_A" TagVisibility "global" } Block { BlockType Goto Name "Goto23" SID "9805" Position [1695, 1430, 1895, 1450] ShowName off GotoTag "regRx_Chan_Est_Smoothing_B" TagVisibility "global" } Block { BlockType Goto Name "Goto24" SID "14852" Position [1720, 1505, 1920, 1525] ShowName off GotoTag "regRx_PHY_Det_IQ_Thresh" TagVisibility "global" } Block { BlockType Goto Name "Goto25" SID "4007" Position [625, 400, 825, 420] ShowName off GotoTag "regRx_DSSS_PKT_BUF_SEL" TagVisibility "global" } Block { BlockType Goto Name "Goto26" SID "4008" Position [625, 455, 825, 475] ShowName off GotoTag "regRx_PktBuf_Rx_Addr_Offset" TagVisibility "global" } Block { BlockType Goto Name "Goto27" SID "4009" Position [625, 615, 825, 635] ShowName off GotoTag "regRx_FEC_SCALE_QPSK" TagVisibility "global" } Block { BlockType Goto Name "Goto28" SID "4010" Position [625, 650, 825, 670] ShowName off GotoTag "regRx_FEC_SCALE_16QAM" TagVisibility "global" } Block { BlockType Goto Name "Goto29" SID "4011" Position [625, 685, 825, 705] ShowName off GotoTag "regRx_FEC_SCALE_64QAM" TagVisibility "global" } Block { BlockType Goto Name "Goto3" SID "4012" Position [650, 1365, 850, 1385] ShowName off GotoTag "regRx_FFT_OFFSET" TagVisibility "global" } Block { BlockType Goto Name "Goto30" SID "4013" Position [1645, 966, 1900, 984] ShowName off GotoTag "regRx_LongCorr_Thresh_highSNR" TagVisibility "global" } Block { BlockType Goto Name "Goto31" SID "4014" Position [625, 500, 825, 520] ShowName off GotoTag "regRx_PktBuf_Rx_H_Est_Offset" TagVisibility "global" } Block { BlockType Goto Name "Goto32" SID "4015" Position [555, 1650, 755, 1670] ShowName off GotoTag "regRx_Debug_RSSI_Sel" TagVisibility "global" } Block { BlockType Goto Name "Goto33" SID "11778" Position [1625, 1216, 1880, 1234] ShowName off GotoTag "regRx_LongCorr_PeakType_Thresh_lowSNR" TagVisibility "global" } Block { BlockType Goto Name "Goto34" SID "11779" Position [1625, 1256, 1880, 1274] ShowName off GotoTag "regRx_LongCorr_PeakType_Thresh_highSNR" TagVisibility "global" } Block { BlockType Goto Name "Goto35" SID "14839" Position [1660, 1146, 1915, 1164] ShowName off GotoTag "regRx_LongCorr_PeakDelayMasks" TagVisibility "global" } Block { BlockType Goto Name "Goto36" SID "15832" Position [1670, 1755, 1870, 1775] ShowName off GotoTag "regRx_DSSS_SYNC_Search_Time" TagVisibility "global" } Block { BlockType Goto Name "Goto37" SID "15737" Position [1590, 1965, 1790, 1985] ShowName off GotoTag "reg_Target_RAM_Wr_Data" TagVisibility "global" } Block { BlockType Goto Name "Goto38" SID "15738" Position [1590, 2040, 1790, 2060] ShowName off GotoTag "reg_Mask_1_RAM_Wr_Data" TagVisibility "global" } Block { BlockType Goto Name "Goto4" SID "4016" Position [575, 150, 775, 170] ShowName off GotoTag "regRx_Global_Reset" TagVisibility "global" } Block { BlockType Goto Name "Goto5" SID "15728" Position [1670, 1610, 1870, 1630] ShowName off GotoTag "reg_Match_Thresh_Mask_1" TagVisibility "global" } Block { BlockType Goto Name "Goto6" SID "4018" Position [570, 1425, 770, 1445] ShowName off GotoTag "regRx_FFT_SCALING" TagVisibility "global" } Block { BlockType Goto Name "Goto7" SID "15733" Position [1590, 1885, 1790, 1905] ShowName off GotoTag "reg_Target_RAM_WrEn" TagVisibility "global" } Block { BlockType Goto Name "Goto8" SID "15769" Position [1670, 1660, 1870, 1680] ShowName off GotoTag "regRx_DSSS_SYNC_Timeout" TagVisibility "global" } Block { BlockType Goto Name "Goto9" SID "4021" Position [1635, 1091, 1890, 1109] ShowName off GotoTag "regRx_LongCorr_RSSI_Thresh" TagVisibility "global" } Block { BlockType Reference Name "Register1" SID "14874" Ports [1, 1] Position [550, 1272, 575, 1298] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register10" SID "4023" Ports [1, 1] Position [485, 1222, 510, 1248] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register11" SID "4024" Ports [1, 1] Position [1450, 962, 1475, 988] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register12" SID "14877" Ports [1, 1] Position [535, 572, 560, 598] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register13" SID "4026" Ports [1, 1] Position [1450, 1087, 1475, 1113] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register14" SID "4027" Ports [1, 1] Position [1450, 922, 1475, 948] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register15" SID "4028" Ports [1, 1] Position [1450, 1027, 1475, 1053] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register16" SID "4029" Ports [1, 1] Position [1415, 457, 1440, 483] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register17" SID "4030" Ports [1, 1] Position [1415, 562, 1440, 588] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register18" SID "4031" Ports [1, 1] Position [1415, 652, 1440, 678] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register19" SID "4032" Ports [1, 1] Position [610, 867, 635, 893] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "14875" Ports [1, 1] Position [550, 1312, 575, 1338] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register20" SID "4034" Ports [1, 1] Position [1610, 2117, 1635, 2143] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register21" SID "4035" Ports [1, 1] Position [610, 912, 635, 938] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register22" SID "4036" Ports [1, 1] Position [1610, 2182, 1635, 2208] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register23" SID "4037" Ports [1, 1] Position [610, 957, 635, 983] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register24" SID "15739" Ports [1, 1] Position [1380, 1827, 1405, 1853] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register25" SID "4039" Ports [1, 1] Position [555, 1002, 580, 1028] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register26" SID "4040" Ports [1, 1] Position [610, 1002, 635, 1028] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register27" SID "15740" Ports [1, 1] Position [1310, 1827, 1335, 1853] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register28" SID "15772" Ports [1, 1] Position [1495, 1607, 1520, 1633] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register29" SID "15773" Ports [1, 1] Position [1495, 1657, 1520, 1683] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register3" SID "14876" Ports [1, 1] Position [550, 1362, 575, 1388] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register30" SID "4045" Ports [1, 1] Position [330, 1517, 355, 1543] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register31" SID "4046" Ports [1, 1] Position [395, 1517, 420, 1543] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register32" SID "4047" Ports [1, 1] Position [465, 1517, 490, 1543] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register33" SID "4048" Ports [1, 1] Position [415, 1597, 440, 1623] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register34" SID "4049" Ports [1, 1] Position [480, 1597, 505, 1623] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register35" SID "4050" Ports [1, 1] Position [480, 1647, 505, 1673] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register36" SID "4051" Ports [1, 1] Position [415, 1647, 440, 1673] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register37" SID "15741" Ports [1, 1] Position [1380, 1962, 1405, 1988] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register38" SID "4053" Ports [1, 1] Position [1270, 327, 1295, 353] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register39" SID "9533" Ports [1, 1] Position [485, 572, 510, 598] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register4" SID "4054" Ports [1, 1] Position [475, 1272, 500, 1298] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register40" SID "15742" Ports [1, 1] Position [1380, 2037, 1405, 2063] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register41" SID "15743" Ports [1, 1] Position [1310, 2037, 1335, 2063] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register42" SID "9534" Ports [1, 1] Position [485, 612, 510, 638] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register43" SID "9535" Ports [1, 1] Position [485, 647, 510, 673] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register44" SID "4057" Ports [1, 1] Position [485, 342, 510, 368] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register45" SID "4058" Ports [1, 1] Position [485, 397, 510, 423] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register46" SID "4059" Ports [1, 1] Position [485, 452, 510, 478] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register47" SID "4060" Ports [1, 1] Position [485, 497, 510, 523] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register48" SID "4061" Ports [1, 1] Position [360, 252, 385, 278] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register49" SID "4062" Ports [1, 1] Position [430, 252, 455, 278] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register5" SID "4063" Ports [1, 1] Position [475, 1312, 500, 1338] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register50" SID "4064" Ports [1, 1] Position [460, 147, 485, 173] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register51" SID "4065" Ports [1, 1] Position [1345, 212, 1370, 238] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register52" SID "4066" Ports [1, 1] Position [1415, 212, 1440, 238] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register53" SID "9536" Ports [1, 1] Position [485, 682, 510, 708] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register54" SID "9537" Ports [1, 1] Position [485, 747, 510, 773] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register55" SID "4067" Ports [1, 1] Position [1350, 457, 1375, 483] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register56" SID "4068" Ports [1, 1] Position [1350, 562, 1375, 588] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register57" SID "4069" Ports [1, 1] Position [1350, 652, 1375, 678] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register58" SID "9538" Ports [1, 1] Position [485, 802, 510, 828] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register59" SID "9780" Ports [1, 1] Position [1305, 1387, 1330, 1413] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register6" SID "4070" Ports [1, 1] Position [475, 1362, 500, 1388] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register60" SID "9804" Ports [1, 1] Position [1620, 1387, 1645, 1413] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register61" SID "14853" Ports [1, 1] Position [1620, 1502, 1645, 1528] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register62" SID "9822" Ports [1, 1] Position [1620, 1427, 1645, 1453] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register63" SID "14854" Ports [1, 1] Position [1565, 1502, 1590, 1528] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register64" SID "14878" Ports [1, 1] Position [535, 612, 560, 638] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register65" SID "14879" Ports [1, 1] Position [535, 647, 560, 673] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register66" SID "14880" Ports [1, 1] Position [535, 682, 560, 708] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register67" SID "14881" Ports [1, 1] Position [535, 747, 560, 773] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register68" SID "14882" Ports [1, 1] Position [535, 802, 560, 828] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register69" SID "14883" Ports [1, 1] Position [1565, 1387, 1590, 1413] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register7" SID "4071" Ports [1, 1] Position [475, 1422, 500, 1448] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register70" SID "14884" Ports [1, 1] Position [1565, 1427, 1590, 1453] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register71" SID "15744" Ports [1, 1] Position [1310, 1962, 1335, 1988] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register72" SID "14886" Ports [1, 1] Position [1535, 1087, 1560, 1113] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register73" SID "14887" Ports [1, 1] Position [1535, 1027, 1560, 1053] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register74" SID "14888" Ports [1, 1] Position [1535, 962, 1560, 988] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register75" SID "14889" Ports [1, 1] Position [1535, 922, 1560, 948] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register76" SID "15774" Ports [1, 1] Position [1495, 1707, 1520, 1733] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register77" SID "15775" Ports [1, 1] Position [1555, 1607, 1580, 1633] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register78" SID "15776" Ports [1, 1] Position [1555, 1657, 1580, 1683] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register79" SID "15777" Ports [1, 1] Position [1555, 1707, 1580, 1733] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register8" SID "4072" Ports [1, 1] Position [485, 1132, 510, 1158] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register80" SID "15830" Ports [1, 1] Position [1495, 1752, 1520, 1778] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register81" SID "15831" Ports [1, 1] Position [1555, 1752, 1580, 1778] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register82" SID "17438" Ports [1, 1] Position [1410, 97, 1435, 123] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register83" SID "17439" Ports [1, 1] Position [1345, 97, 1370, 123] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register84" SID "17453" Ports [1, 1] Position [1410, 12, 1435, 38] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register85" SID "11780" Ports [1, 1] Position [1450, 1252, 1475, 1278] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register86" SID "11781" Ports [1, 1] Position [1450, 1212, 1475, 1238] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register87" SID "11782" Ports [1, 1] Position [1535, 1252, 1560, 1278] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register88" SID "14840" Ports [1, 1] Position [1450, 1142, 1475, 1168] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register89" SID "14841" Ports [1, 1] Position [1535, 1142, 1560, 1168] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register9" SID "4073" Ports [1, 1] Position [485, 1177, 510, 1203] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register90" SID "11783" Ports [1, 1] Position [1535, 1212, 1560, 1238] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register91" SID "17454" Ports [1, 1] Position [1345, 12, 1370, 38] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register92" SID "18162" Ports [1, 1] Position [1305, 737, 1330, 763] ForegroundColor "red" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType Reference Name "Register93" SID "18163" Ports [1, 1] Position [1240, 737, 1265, 763] ForegroundColor "red" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMM" "ENT: end icon text');" } Block { BlockType SubSystem Name "Sim Reset" SID "4074" Ports [0, 1] Position [380, 100, 425, 130] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Sim Reset" Location [347, 173, 617, 257] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Sum Name "Add" SID "4075" Ports [2, 1] Position [90, 57, 120, 88] ZOrder -2 InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Reference Name "Disregard Subsystem" SID "4076" Tag "discardX" Ports [] Position [553, 252, 611, 310] ShowName off AttributesFormatString "Disregard Subsystem\\nFor Generation" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Disregard Subsystem" SourceType "Xilinx Disregard Subsystem For Generation Block" infoedit "Place this block into a subsystem to have System Generator ignore the subsystem during code ge" "neration. This block can be used in combination with the Simulation Multiplexer block to provide an alternative" " simulation model for another subsystem (e.g., to provide a simulation model for a black box)." has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "disregard" sg_icon_stat "58,58,-1,-1,darkgray,black,0,07734,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 58 58 0 0 ],[0 0 58 58 0 ],[0.1 0." "1 0.1 ]);\nplot([0 58 58 0 0 ],[0 0 58 58 0 ]);\npatch([11.2 22.76 30.76 38.76 46.76 30.76 19.2 11.2 ],[37.88 3" "7.88 45.88 37.88 45.88 45.88 45.88 37.88 ],[0.33 0.33 0.33 ]);\npatch([19.2 30.76 22.76 11.2 19.2 ],[29.88 29.8" "8 37.88 37.88 29.88 ],[0.261 0.261 0.261 ]);\npatch([11.2 22.76 30.76 19.2 11.2 ],[21.88 21.88 29.88 29.88 21.8" "8 ],[0.33 0.33 0.33 ]);\npatch([19.2 46.76 38.76 30.76 22.76 11.2 19.2 ],[13.88 13.88 21.88 13.88 21.88 21.88 1" "3.88 ],[0.261 0.261 0.261 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType DiscretePulseGenerator Name "Pulse\nGenerator" SID "4077" Ports [0, 1] Position [25, 29, 55, 61] ZOrder -13 Period "1e6" PulseWidth "2" PhaseDelay "0.8e4" } Block { BlockType DiscretePulseGenerator Name "Pulse\nGenerator1" SID "4078" Ports [0, 1] Position [25, 99, 55, 131] ZOrder -13 Amplitude "0" Period "1e6" PulseWidth "2" PhaseDelay "2.5e4" } Block { BlockType Reference Name "sim_only_reset" SID "4079" Ports [1, 1] Position [190, 63, 230, 77] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to" " Xilinx fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top l" "evel input ports." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "40,14,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9" ".22 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22" " 9.22 7.22 ],[0.985 0.979 0.895 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.985 0.979 0.89" "5 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprint" "f('','COMMENT: end icon text');" } Block { BlockType Outport Name "Out1" SID "4080" Position [255, 63, 285, 77] IconDisplay "Port number" } Line { SrcBlock "sim_only_reset" SrcPort 1 DstBlock "Out1" DstPort 1 } Line { SrcBlock "Pulse\nGenerator" SrcPort 1 Points [10, 0; 0, 20] DstBlock "Add" DstPort 1 } Line { SrcBlock "Pulse\nGenerator1" SrcPort 1 Points [10, 0; 0, -35] DstBlock "Add" DstPort 2 } Line { SrcBlock "Add" SrcPort 1 Points [5, 0; 0, -5] DstBlock "sim_only_reset" DstPort 1 } } } Block { BlockType Terminator Name "Terminator" SID "4081" Position [1685, 235, 1695, 245] ShowName off } Block { BlockType Terminator Name "Terminator1" SID "4082" Position [1690, 350, 1700, 360] ShowName off } Block { BlockType Terminator Name "Terminator2" SID "4083" Position [1690, 585, 1700, 595] ShowName off } Block { BlockType Terminator Name "Terminator3" SID "4084" Position [1690, 480, 1700, 490] ShowName off } Block { BlockType Terminator Name "Terminator4" SID "4085" Position [1690, 675, 1700, 685] ShowName off } Block { BlockType Terminator Name "Terminator5" SID "17440" Position [1685, 120, 1695, 130] ShowName off } Block { BlockType Terminator Name "Terminator6" SID "17456" Position [1680, 35, 1690, 45] ShowName off } Block { BlockType Terminator Name "Terminator7" SID "18164" Position [1690, 760, 1700, 770] ForegroundColor "red" ShowName off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "To Register" SID "4086" Ports [2, 1] Position [1610, 212, 1670, 268] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'Status'" init "0" ownership "Locally owned and initialized" explicit_data_type on gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "toreg" sg_icon_stat "60,56,2,1,white,blue,0,10ab453e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8" "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ]," "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20." "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf(" "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'di" "n');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMEN" "T: end icon text');" } Block { BlockType Reference Name "To Register1" SID "4087" Ports [2, 1] Position [1610, 327, 1670, 383] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'CFO_EST_TIME_DOMAIN'" init "0" ownership "Locally owned and initialized" explicit_data_type on gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "toreg" sg_icon_stat "60,56,2,1,white,blue,0,10ab453e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8" "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ]," "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20." "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf(" "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'di" "n');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMEN" "T: end icon text');" } Block { BlockType Reference Name "To Register2" SID "4088" Ports [2, 1] Position [1615, 562, 1675, 618] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'RX_PKT_RSSI_AB'" init "0" ownership "Locally owned and initialized" explicit_data_type on gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "toreg" sg_icon_stat "60,56,2,1,white,blue,0,10ab453e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8" "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ]," "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20." "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf(" "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'di" "n');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMEN" "T: end icon text');" } Block { BlockType Reference Name "To Register3" SID "4089" Ports [2, 1] Position [1615, 457, 1675, 513] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'RX_PKT_AGC_GAINS'" init "0" ownership "Locally owned and initialized" explicit_data_type on gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "toreg" sg_icon_stat "60,56,2,1,white,blue,0,10ab453e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8" "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ]," "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20." "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf(" "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'di" "n');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMEN" "T: end icon text');" } Block { BlockType Reference Name "To Register4" SID "4090" Ports [2, 1] Position [1615, 652, 1675, 708] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'RX_PKT_RSSI_CD'" init "0" ownership "Locally owned and initialized" explicit_data_type on gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "toreg" sg_icon_stat "60,56,2,1,white,blue,0,10ab453e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8" "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ]," "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20." "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf(" "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'di" "n');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMEN" "T: end icon text');" } Block { BlockType Reference Name "To Register5" SID "17441" Ports [2, 1] Position [1610, 97, 1670, 153] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'PKT_DET_COUNT_OFDM'" init "0" ownership "Locally owned and initialized" explicit_data_type on gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "toreg" sg_icon_stat "60,56,2,1,white,blue,0,10ab453e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8" "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ]," "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20." "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf(" "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'di" "n');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMEN" "T: end icon text');" } Block { BlockType Reference Name "To Register6" SID "17455" Ports [2, 1] Position [1610, 12, 1670, 68] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'PKT_DET_COUNT_DSSS'" init "0" ownership "Locally owned and initialized" explicit_data_type on gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "toreg" sg_icon_stat "60,56,2,1,white,blue,0,10ab453e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8" "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ]," "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20." "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf(" "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'di" "n');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMEN" "T: end icon text');" } Block { BlockType Reference Name "To Register7" SID "18165" Ports [2, 1] Position [1615, 737, 1675, 793] ForegroundColor "red" AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'RXIQ_MAG_SUM_RFA'" init "0" ownership "Locally owned and initialized" explicit_data_type on gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "toreg" sg_icon_stat "60,56,2,1,white,blue,0,10ab453e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8" "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ]," "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20." "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf(" "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'di" "n');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMEN" "T: end icon text');" } Block { BlockType Reference Name "To_UFix8_1" SID "4091" Ports [1, 1] Position [460, 917, 505, 933] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can change the signal between si" "gned and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.
<" "br>Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsigned" " with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111000 " "in binary)." force_arith_type on arith_type "Unsigned" force_bin_pt on bin_pt "3" has_advanced_control "0" sggui_pos "20,20,356,284" block_type "cast" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,16,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 16 16 0 ],[0.77 0.82 0.91" " ]);\nplot([0 45 45 0 0 ],[0 0 16 16 0 ]);\npatch([17.55 20.44 22.44 24.44 26.44 22.44 19.55 17.55 ],[10.22 10.22 1" "2.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([19.55 22.44 20.44 17.55 19.55 ],[8.22 8.22 10.22 10.22 8.22" " ],[0.931 0.946 0.973 ]);\npatch([17.55 20.44 22.44 19.55 17.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatch([19" ".55 26.44 24.44 22.44 20.44 17.55 19.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprintf(''," "'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('reinterpret');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "To_UFix8_2" SID "15952" Ports [1, 1] Position [1495, 2187, 1540, 2203] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can change the signal between si" "gned and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.
<" "br>Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsigned" " with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111000 " "in binary)." force_arith_type on arith_type "Unsigned" force_bin_pt on bin_pt "3" has_advanced_control "0" sggui_pos "20,20,356,284" block_type "cast" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,16,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 16 16 0 ],[0.77 0.82 0.91" " ]);\nplot([0 45 45 0 0 ],[0 0 16 16 0 ]);\npatch([17.55 20.44 22.44 24.44 26.44 22.44 19.55 17.55 ],[10.22 10.22 1" "2.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([19.55 22.44 20.44 17.55 19.55 ],[8.22 8.22 10.22 10.22 8.22" " ],[0.931 0.946 0.973 ]);\npatch([17.55 20.44 22.44 19.55 17.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatch([19" ".55 26.44 24.44 22.44 20.44 17.55 19.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprintf(''," "'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('reinterpret');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "To_UFix8_3" SID "4093" Ports [1, 1] Position [1495, 2122, 1540, 2138] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can change the signal between si" "gned and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.
<" "br>Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsigned" " with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111000 " "in binary)." force_arith_type on arith_type "Unsigned" force_bin_pt on bin_pt "8" has_advanced_control "0" sggui_pos "20,20,356,284" block_type "cast" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,16,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 16 16 0 ],[0.77 0.82 0.91" " ]);\nplot([0 45 45 0 0 ],[0 0 16 16 0 ]);\npatch([17.55 20.44 22.44 24.44 26.44 22.44 19.55 17.55 ],[10.22 10.22 1" "2.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([19.55 22.44 20.44 17.55 19.55 ],[8.22 8.22 10.22 10.22 8.22" " ],[0.931 0.946 0.973 ]);\npatch([17.55 20.44 22.44 19.55 17.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatch([19" ".55 26.44 24.44 22.44 20.44 17.55 19.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprintf(''," "'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('reinterpret');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "To_UFix8_4" SID "4094" Ports [1, 1] Position [1475, 332, 1520, 348] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can change the signal between si" "gned and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.
<" "br>Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsigned" " with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111000 " "in binary)." force_arith_type on arith_type "Unsigned" force_bin_pt on bin_pt "0" has_advanced_control "0" sggui_pos "20,20,356,284" block_type "cast" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,16,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 16 16 0 ],[0.77 0.82 0.91" " ]);\nplot([0 45 45 0 0 ],[0 0 16 16 0 ]);\npatch([17.55 20.44 22.44 24.44 26.44 22.44 19.55 17.55 ],[10.22 10.22 1" "2.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([19.55 22.44 20.44 17.55 19.55 ],[8.22 8.22 10.22 10.22 8.22" " ],[0.931 0.946 0.973 ]);\npatch([17.55 20.44 22.44 19.55 17.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatch([19" ".55 26.44 24.44 22.44 20.44 17.55 19.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprintf(''," "'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('reinterpret');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "To_UFix8_5" SID "9817" Ports [1, 1] Position [1475, 1392, 1520, 1408] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can change the signal between si" "gned and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.
<" "br>Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsigned" " with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111000 " "in binary)." force_arith_type on arith_type "Unsigned" force_bin_pt on bin_pt "12" has_advanced_control "0" sggui_pos "20,20,356,284" block_type "cast" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,16,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 16 16 0 ],[0.77 0.82 0.91" " ]);\nplot([0 45 45 0 0 ],[0 0 16 16 0 ]);\npatch([17.55 20.44 22.44 24.44 26.44 22.44 19.55 17.55 ],[10.22 10.22 1" "2.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([19.55 22.44 20.44 17.55 19.55 ],[8.22 8.22 10.22 10.22 8.22" " ],[0.931 0.946 0.973 ]);\npatch([17.55 20.44 22.44 19.55 17.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatch([19" ".55 26.44 24.44 22.44 20.44 17.55 19.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprintf(''," "'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('reinterpret');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "To_UFix8_6" SID "9818" Ports [1, 1] Position [1475, 1432, 1520, 1448] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can change the signal between si" "gned and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.
<" "br>Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsigned" " with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111000 " "in binary)." force_arith_type on arith_type "Unsigned" force_bin_pt on bin_pt "12" has_advanced_control "0" sggui_pos "20,20,356,284" block_type "cast" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,16,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 16 16 0 ],[0.77 0.82 0.91" " ]);\nplot([0 45 45 0 0 ],[0 0 16 16 0 ]);\npatch([17.55 20.44 22.44 24.44 26.44 22.44 19.55 17.55 ],[10.22 10.22 1" "2.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([19.55 22.44 20.44 17.55 19.55 ],[8.22 8.22 10.22 10.22 8.22" " ],[0.931 0.946 0.973 ]);\npatch([17.55 20.44 22.44 19.55 17.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatch([19" ".55 26.44 24.44 22.44 20.44 17.55 19.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprintf(''," "'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('reinterpret');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "To_UFix8_7" SID "4095" Ports [1, 1] Position [460, 872, 505, 888] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can change the signal between si" "gned and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.
<" "br>Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsigned" " with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111000 " "in binary)." force_arith_type on arith_type "Unsigned" force_bin_pt on bin_pt "8" has_advanced_control "0" sggui_pos "20,20,356,284" block_type "cast" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,16,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 16 16 0 ],[0.77 0.82 0.91" " ]);\nplot([0 45 45 0 0 ],[0 0 16 16 0 ]);\npatch([17.55 20.44 22.44 24.44 26.44 22.44 19.55 17.55 ],[10.22 10.22 1" "2.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([19.55 22.44 20.44 17.55 19.55 ],[8.22 8.22 10.22 10.22 8.22" " ],[0.931 0.946 0.973 ]);\npatch([17.55 20.44 22.44 19.55 17.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatch([19" ".55 26.44 24.44 22.44 20.44 17.55 19.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprintf(''," "'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('reinterpret');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "To_UFix8_8" SID "18166" Ports [1, 1] Position [1395, 742, 1440, 758] ForegroundColor "red" NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can change the signal between si" "gned and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.
<" "br>Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsigned" " with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111000 " "in binary)." force_arith_type on arith_type "Unsigned" force_bin_pt on bin_pt "0" has_advanced_control "0" sggui_pos "20,20,356,284" block_type "cast" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,16,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 16 16 0 ],[0.77 0.82 0.91" " ]);\nplot([0 45 45 0 0 ],[0 0 16 16 0 ]);\npatch([17.55 20.44 22.44 24.44 26.44 22.44 19.55 17.55 ],[10.22 10.22 1" "2.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([19.55 22.44 20.44 17.55 19.55 ],[8.22 8.22 10.22 10.22 8.22" " ],[0.931 0.946 0.973 ]);\npatch([17.55 20.44 22.44 19.55 17.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatch([19" ".55 26.44 24.44 22.44 20.44 17.55 19.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprintf(''," "'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('reinterpret');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[0]" SID "4097" Ports [1, 1] Position [380, 153, 420, 167] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardwar" "e notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9.22 9.22 11." "22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0." "931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([17.55 24" ".44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a:b]');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[11:0]" SID "9802" Ports [1, 1] Position [1390, 1393, 1430, 1407] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardwar" "e notes: In hardware this block costs nothing." nbits "12" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9.22 9.22 11." "22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0." "931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([17.55 24" ".44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a:b]');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[11:8]" SID "4099" Ports [1, 1] Position [375, 403, 415, 417] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardwar" "e notes: In hardware this block costs nothing." nbits "4" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "8" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9.22 9.22 11." "22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0." "931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([17.55 24" ".44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a:b]');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[14:10]" SID "4100" Ports [1, 1] Position [375, 653, 415, 667] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardwar" "e notes: In hardware this block costs nothing." nbits "5" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "10" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9.22 9.22 11." "22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0." "931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([17.55 24" ".44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a:b]');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[15:0]" SID "4101" Ports [1, 1] Position [1375, 928, 1415, 942] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardwar" "e notes: In hardware this block costs nothing." nbits "16" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9.22 9.22 11." "22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0." "931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([17.55 24" ".44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a:b]');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[15:0] " SID "4102" Ports [1, 1] Position [330, 1603, 370, 1617] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardwar" "e notes: In hardware this block costs nothing." nbits "16" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9.22 9.22 11." "22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0." "931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([17.55 24" ".44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a:b]');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[15:0]1" SID "11784" Ports [1, 1] Position [1375, 1218, 1415, 1232] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardwar" "e notes: In hardware this block costs nothing." nbits "16" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9.22 9.22 11." "22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0." "931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([17.55 24" ".44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a:b]');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[15:0]2" SID "15745" Ports [1, 1] Position [1470, 1833, 1510, 1847] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardwar" "e notes: In hardware this block costs nothing." nbits "16" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9.22 9.22 11." "22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0." "931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([17.55 24" ".44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a:b]');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[15:0]x" SID "4103" Ports [1, 1] Position [345, 753, 385, 767] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardwar" "e notes: In hardware this block costs nothing." nbits "16" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9.22 9.22 11." "22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0." "931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([17.55 24" ".44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a:b]');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[15:8]" SID "4104" Ports [1, 1] Position [340, 1318, 380, 1332] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardwar" "e notes: In hardware this block costs nothing." nbits "8" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "8" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9.22 9.22 11." "22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0." "931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([17.55 24" ".44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a:b]');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[15:8]1" SID "15768" Ports [1, 1] Position [1405, 1663, 1445, 1677] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardwar" "e notes: In hardware this block costs nothing." nbits "8" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "8" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9.22 9.22 11." "22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0." "931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([17.55 24" ".44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a:b]');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[19:15]" SID "9441" Ports [1, 1] Position [375, 688, 415, 702] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardwar" "e notes: In hardware this block costs nothing." nbits "5" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "15" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9.22 9.22 11." "22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0." "931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([17.55 24" ".44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a:b]');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[19:5]" SID "4107" Ports [1, 1] Position [370, 1181, 405, 1199] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardwar" "e notes: In hardware this block costs nothing." nbits "15" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "5" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 18 18 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[11.22 11.22 1" "3.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[9.22 9.22 11.22 11.22 9.22" " ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([14" ".55 21.44 19.44 17.44 15.44 12.55 14.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf(''," "'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a" ":b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[21:8]" SID "4106" Ports [1, 1] Position [1410, 2188, 1450, 2202] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardwar" "e notes: In hardware this block costs nothing." nbits "14" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "8" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9.22 9.22 11." "22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0." "931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([17.55 24" ".44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a:b]');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[21:8] " SID "4108" Ports [1, 1] Position [375, 918, 415, 932] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardwar" "e notes: In hardware this block costs nothing." nbits "14" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "8" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9.22 9.22 11." "22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0." "931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([17.55 24" ".44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a:b]');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[23:0]" SID "9807" Ports [1, 1] Position [1385, 1433, 1425, 1447] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardwar" "e notes: In hardware this block costs nothing." nbits "12" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "12" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9.22 9.22 11." "22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0." "931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([17.55 24" ".44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a:b]');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[23:16]" SID "4109" Ports [1, 1] Position [340, 1368, 380, 1382] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardwar" "e notes: In hardware this block costs nothing." nbits "8" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "16" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9.22 9.22 11." "22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0." "931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([17.55 24" ".44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a:b]');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[23:16]1" SID "4110" Ports [1, 1] Position [345, 808, 385, 822] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardwar" "e notes: In hardware this block costs nothing." nbits "8" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "16" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9.22 9.22 11." "22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0." "931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([17.55 24" ".44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a:b]');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[23:16]2" SID "15770" Ports [1, 1] Position [1405, 1713, 1445, 1727] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardwar" "e notes: In hardware this block costs nothing." nbits "8" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "16" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9.22 9.22 11." "22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0." "931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([17.55 24" ".44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a:b]');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[23:8]" SID "4111" Ports [1, 1] Position [1375, 1093, 1415, 1107] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardwar" "e notes: In hardware this block costs nothing." nbits "16" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "8" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9.22 9.22 11." "22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0." "931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([17.55 24" ".44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a:b]');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[24:20]" SID "4113" Ports [1, 1] Position [370, 1226, 405, 1244] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardwar" "e notes: In hardware this block costs nothing." nbits "5" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "20" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 18 18 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[11.22 11.22 1" "3.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[9.22 9.22 11.22 11.22 9.22" " ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([14" ".55 21.44 19.44 17.44 15.44 12.55 14.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf(''," "'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a" ":b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[24]" SID "15746" Ports [1, 1] Position [1470, 1888, 1510, 1902] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardwar" "e notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "24" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9.22 9.22 11." "22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0." "931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([17.55 24" ".44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a:b]');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[25:22] " SID "4114" Ports [1, 1] Position [375, 961, 410, 979] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardwar" "e notes: In hardware this block costs nothing." nbits "4" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "22" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 18 18 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[11.22 11.22 1" "3.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[9.22 9.22 11.22 11.22 9.22" " ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([14" ".55 21.44 19.44 17.44 15.44 12.55 14.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf(''," "'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a" ":b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[25]" SID "15747" Ports [1, 1] Position [1470, 1923, 1510, 1937] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardwar" "e notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "25" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9.22 9.22 11." "22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0." "931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([17.55 24" ".44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a:b]');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[26:24]" SID "14842" Ports [1, 1] Position [1375, 1148, 1415, 1162] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardwar" "e notes: In hardware this block costs nothing." nbits "3" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "24" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9.22 9.22 11." "22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0." "931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([17.55 24" ".44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a:b]');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[29:24]" SID "4115" Ports [1, 1] Position [340, 1428, 380, 1442] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardwar" "e notes: In hardware this block costs nothing." nbits "6" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "24" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9.22 9.22 11." "22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0." "931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([17.55 24" ".44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a:b]');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[29:24]1" SID "14855" Ports [1, 1] Position [1385, 1508, 1425, 1522] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardwar" "e notes: In hardware this block costs nothing." nbits "6" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "24" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9.22 9.22 11." "22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0." "931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([17.55 24" ".44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a:b]');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[31:16]" SID "4116" Ports [1, 1] Position [1375, 968, 1415, 982] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardwar" "e notes: In hardware this block costs nothing." nbits "16" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "16" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9.22 9.22 11." "22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0." "931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([17.55 24" ".44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a:b]');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[31:16]1" SID "11785" Ports [1, 1] Position [1375, 1258, 1415, 1272] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardwar" "e notes: In hardware this block costs nothing." nbits "16" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "16" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9.22 9.22 11." "22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0." "931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([17.55 24" ".44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a:b]');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[31:24]" SID "15829" Ports [1, 1] Position [1405, 1758, 1445, 1772] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardwar" "e notes: In hardware this block costs nothing." nbits "8" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "24" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9.22 9.22 11." "22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0." "931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([17.55 24" ".44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a:b]');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[31:26]" SID "4119" Ports [1, 1] Position [375, 1006, 410, 1024] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardwar" "e notes: In hardware this block costs nothing." nbits "6" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "26" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 18 18 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[11.22 11.22 1" "3.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[9.22 9.22 11.22 11.22 9.22" " ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([14" ".55 21.44 19.44 17.44 15.44 12.55 14.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf(''," "'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a" ":b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[31]" SID "4120" Ports [1, 1] Position [330, 1653, 370, 1667] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardwar" "e notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "31" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9.22 9.22 11." "22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0." "931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([17.55 24" ".44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a:b]');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[3:0]" SID "4121" Ports [1, 1] Position [375, 348, 415, 362] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardwar" "e notes: In hardware this block costs nothing." nbits "4" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9.22 9.22 11." "22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0." "931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([17.55 24" ".44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a:b]');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[4:0]" SID "4122" Ports [1, 1] Position [370, 1136, 405, 1154] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardwar" "e notes: In hardware this block costs nothing." nbits "5" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 18 18 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[11.22 11.22 1" "3.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[9.22 9.22 11.22 11.22 9.22" " ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([14" ".55 21.44 19.44 17.44 15.44 12.55 14.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf(''," "'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a" ":b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[4:0] " SID "4123" Ports [1, 1] Position [375, 578, 415, 592] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardwar" "e notes: In hardware this block costs nothing." nbits "5" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9.22 9.22 11." "22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0." "931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([17.55 24" ".44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a:b]');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[7:0]" SID "4124" Ports [1, 1] Position [340, 1278, 380, 1292] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardwar" "e notes: In hardware this block costs nothing." nbits "8" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9.22 9.22 11." "22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0." "931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([17.55 24" ".44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a:b]');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[7:0] " SID "4125" Ports [1, 1] Position [375, 873, 415, 887] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardwar" "e notes: In hardware this block costs nothing." nbits "8" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9.22 9.22 11." "22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0." "931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([17.55 24" ".44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a:b]');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[7:0] 1" SID "4126" Ports [1, 1] Position [1375, 1033, 1415, 1047] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardwar" "e notes: In hardware this block costs nothing." nbits "8" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9.22 9.22 11." "22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0." "931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([17.55 24" ".44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a:b]');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[7:0] 2" SID "4127" Ports [1, 1] Position [1410, 2123, 1450, 2137] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardwar" "e notes: In hardware this block costs nothing." nbits "8" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9.22 9.22 11." "22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0." "931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([17.55 24" ".44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a:b]');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[7:0]1" SID "15729" Ports [1, 1] Position [1405, 1613, 1445, 1627] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardwar" "e notes: In hardware this block costs nothing." nbits "8" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9.22 9.22 11." "22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0." "931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([17.55 24" ".44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a:b]');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[9:5]" SID "4129" Ports [1, 1] Position [375, 618, 415, 632] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardwar" "e notes: In hardware this block costs nothing." nbits "5" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "5" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9.22 9.22 11." "22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0." "931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([17.55 24" ".44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a:b]');" "\nfprintf('','COMMENT: end icon text');" } Line { SrcBlock "b[31:16]" SrcPort 1 DstBlock "Register11" DstPort 1 } Line { SrcBlock "From Register1" SrcPort 1 Points [35, 0] Branch { DstBlock "b[7:0]" DstPort 1 } Branch { Points [0, 40] Branch { DstBlock "b[15:8]" DstPort 1 } Branch { Points [0, 50] Branch { DstBlock "b[23:16]" DstPort 1 } Branch { Points [0, 60] DstBlock "b[29:24]" DstPort 1 } } } } Line { SrcBlock "b[7:0]" SrcPort 1 DstBlock "Register4" DstPort 1 } Line { SrcBlock "b[15:8]" SrcPort 1 DstBlock "Register5" DstPort 1 } Line { SrcBlock "b[23:16]" SrcPort 1 DstBlock "Register6" DstPort 1 } Line { SrcBlock "From Register2" SrcPort 1 DstBlock "b[0]" DstPort 1 } Line { SrcBlock "b[0]" SrcPort 1 DstBlock "Register50" DstPort 1 } Line { SrcBlock "From Register3" SrcPort 1 Points [45, 0] Branch { DstBlock "b[4:0] " DstPort 1 } Branch { Points [0, 40] Branch { DstBlock "b[9:5]" DstPort 1 } Branch { Points [0, 35] Branch { DstBlock "b[14:10]" DstPort 1 } Branch { Points [0, 35] DstBlock "b[19:15]" DstPort 1 } } } } Line { SrcBlock "b[29:24]" SrcPort 1 DstBlock "Register7" DstPort 1 } Line { SrcBlock "From5" SrcPort 1 DstBlock "Concat" DstPort 4 } Line { SrcBlock "From6" SrcPort 1 DstBlock "Concat" DstPort 5 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "To Register" DstPort 2 } Line { SrcBlock "To Register" SrcPort 1 DstBlock "Terminator" DstPort 1 } Line { SrcBlock "From Register4" SrcPort 1 Points [65, 0] Branch { DstBlock "b[7:0] " DstPort 1 } Branch { Points [0, 45] Branch { DstBlock "b[21:8] " DstPort 1 } Branch { Points [0, 45] Branch { DstBlock "b[25:22] " DstPort 1 } Branch { Points [0, 45] DstBlock "b[31:26]" DstPort 1 } } } } Line { SrcBlock "b[7:0] " SrcPort 1 DstBlock "To_UFix8_7" DstPort 1 } Line { SrcBlock "b[21:8] " SrcPort 1 DstBlock "To_UFix8_1" DstPort 1 } Line { SrcBlock "To_UFix8_7" SrcPort 1 DstBlock "Down Sample16" DstPort 1 } Line { SrcBlock "To_UFix8_1" SrcPort 1 DstBlock "Down Sample1" DstPort 1 } Line { SrcBlock "Down Sample16" SrcPort 1 DstBlock "Register19" DstPort 1 } Line { SrcBlock "Down Sample1" SrcPort 1 DstBlock "Register21" DstPort 1 } Line { SrcBlock "b[15:0]" SrcPort 1 DstBlock "Register14" DstPort 1 } Line { SrcBlock "b[25:22] " SrcPort 1 DstBlock "Down Sample2" DstPort 1 } Line { SrcBlock "Down Sample2" SrcPort 1 DstBlock "Register23" DstPort 1 } Line { SrcBlock "From Register5" SrcPort 1 Points [35, 0] Branch { DstBlock "b[3:0]" DstPort 1 } Branch { Points [0, 55] Branch { DstBlock "b[11:8]" DstPort 1 } Branch { Points [0, 55] Branch { DstBlock " b[23:16] " DstPort 1 } Branch { Points [0, 45] DstBlock " b[31:24]" DstPort 1 } } } } Line { SrcBlock "b[3:0]" SrcPort 1 DstBlock "Register44" DstPort 1 } Line { SrcBlock "From Register6" SrcPort 1 Points [25, 0] Branch { Points [0, 50] Branch { DstBlock "b[15:8]1" DstPort 1 } Branch { Points [0, 50] Branch { DstBlock "b[23:16]2" DstPort 1 } Branch { Points [0, 45] DstBlock "b[31:24]" DstPort 1 } } } Branch { DstBlock "b[7:0]1" DstPort 1 } } Line { SrcBlock "From Register8" SrcPort 1 Points [35, 0] Branch { DstBlock "b[15:0] " DstPort 1 } Branch { Points [0, 50] DstBlock "b[31]" DstPort 1 } } Line { SrcBlock "b[15:0] " SrcPort 1 DstBlock "Register33" DstPort 1 } Line { SrcBlock "b[4:0]" SrcPort 1 DstBlock "Register8" DstPort 1 } Line { SrcBlock "Down Sample6" SrcPort 1 Points [5, 0] Branch { DstBlock "b[4:0]" DstPort 1 } Branch { Points [0, 45] Branch { DstBlock "b[19:5]" DstPort 1 } Branch { Points [0, 45] DstBlock "b[24:20]" DstPort 1 } } } Line { SrcBlock "b[19:5]" SrcPort 1 DstBlock "Register9" DstPort 1 } Line { SrcBlock "From Register" SrcPort 1 DstBlock "Down Sample6" DstPort 1 } Line { SrcBlock "b[24:20]" SrcPort 1 DstBlock "Register10" DstPort 1 } Line { Labels [0, 0] SrcBlock "From Register7" SrcPort 1 DstBlock "Register48" DstPort 1 } Line { SrcBlock "Register4" SrcPort 1 DstBlock "Register1" DstPort 1 } Line { SrcBlock "Register5" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "Register6" SrcPort 1 DstBlock "Register3" DstPort 1 } Line { SrcBlock "Register7" SrcPort 1 DstBlock "Goto6" DstPort 1 } Line { SrcBlock "Register8" SrcPort 1 DstBlock "Fanout1" DstPort 1 } Line { SrcBlock "Register9" SrcPort 1 DstBlock "Fanout1" DstPort 2 } Line { SrcBlock "Register10" SrcPort 1 DstBlock "Fanout1" DstPort 3 } Line { SrcBlock "Register11" SrcPort 1 DstBlock "Register74" DstPort 1 } Line { SrcBlock "b[31:26]" SrcPort 1 DstBlock "Register25" DstPort 1 } Line { SrcBlock "From Register11" SrcPort 1 Points [35, 0] Branch { DstBlock "b[15:0]x" DstPort 1 } Branch { Points [0, 55] DstBlock "b[23:16]1" DstPort 1 } } Line { SrcBlock "b[15:0]x" SrcPort 1 DstBlock "Register54" DstPort 1 } Line { SrcBlock "b[23:16]1" SrcPort 1 DstBlock "Register58" DstPort 1 } Line { SrcBlock "b[11:8]" SrcPort 1 DstBlock "Register45" DstPort 1 } Line { SrcBlock "Convert" SrcPort 1 DstBlock "To Register" DstPort 1 } Line { SrcBlock " b[23:16] " SrcPort 1 DstBlock "Register46" DstPort 1 } Line { SrcBlock "b[4:0] " SrcPort 1 DstBlock "Register39" DstPort 1 } Line { SrcBlock "b[9:5]" SrcPort 1 DstBlock "Register42" DstPort 1 } Line { SrcBlock "b[14:10]" SrcPort 1 DstBlock "Register43" DstPort 1 } Line { SrcBlock "Constant4" SrcPort 1 DstBlock "To Register2" DstPort 2 } Line { SrcBlock "To Register2" SrcPort 1 DstBlock "Terminator2" DstPort 1 } Line { SrcBlock "Convert2" SrcPort 1 DstBlock "To Register2" DstPort 1 } Line { SrcBlock "Register13" SrcPort 1 DstBlock "Register72" DstPort 1 } Line { SrcBlock "b[23:8]" SrcPort 1 DstBlock "Register13" DstPort 1 } Line { SrcBlock "Register14" SrcPort 1 DstBlock "Register75" DstPort 1 } Line { SrcBlock "From Register14" SrcPort 1 Points [35, 0] Branch { DstBlock "b[15:0]" DstPort 1 } Branch { Points [0, 40] DstBlock "b[31:16]" DstPort 1 } } Line { SrcBlock "From Register12" SrcPort 1 Points [45, 0] Branch { DstBlock "b[7:0] 1" DstPort 1 } Branch { Points [0, 60] Branch { DstBlock "b[23:8]" DstPort 1 } Branch { Points [0, 55] DstBlock "b[26:24]" DstPort 1 } } } Line { SrcBlock "2x " SrcPort 1 DstBlock "Goto10" DstPort 1 } Line { SrcBlock "Register15" SrcPort 1 DstBlock "Register73" DstPort 1 } Line { SrcBlock "b[7:0] 1" SrcPort 1 DstBlock "Register15" DstPort 1 } Line { SrcBlock " b[31:24]" SrcPort 1 DstBlock "Register47" DstPort 1 } Line { SrcBlock "From2" SrcPort 1 DstBlock "Register56" DstPort 1 } Line { SrcBlock "From4" SrcPort 1 DstBlock "Concat" DstPort 3 } Line { SrcBlock "Constant2" SrcPort 1 DstBlock "To Register3" DstPort 2 } Line { SrcBlock "To Register3" SrcPort 1 DstBlock "Terminator3" DstPort 1 } Line { SrcBlock "Convert3" SrcPort 1 DstBlock "To Register3" DstPort 1 } Line { SrcBlock "From3" SrcPort 1 DstBlock "Register55" DstPort 1 } Line { SrcBlock "Register16" SrcPort 1 DstBlock "Convert3" DstPort 1 } Line { SrcBlock "Register17" SrcPort 1 DstBlock "Convert2" DstPort 1 } Line { SrcBlock "b[31]" SrcPort 1 DstBlock "Register36" DstPort 1 } Line { SrcBlock "Concat" SrcPort 1 DstBlock "Register51" DstPort 1 } Line { SrcBlock "From7" SrcPort 1 DstBlock "Concat" DstPort 2 } Line { SrcBlock "Constant5" SrcPort 1 DstBlock "To Register4" DstPort 2 } Line { SrcBlock "To Register4" SrcPort 1 DstBlock "Terminator4" DstPort 1 } Line { SrcBlock "Convert4" SrcPort 1 DstBlock "To Register4" DstPort 1 } Line { SrcBlock "Register18" SrcPort 1 DstBlock "Convert4" DstPort 1 } Line { SrcBlock "From8" SrcPort 1 DstBlock "Register57" DstPort 1 } Line { SrcBlock "Register19" SrcPort 1 DstBlock "Fanout" DstPort 1 } Line { SrcBlock "Register21" SrcPort 1 DstBlock "Fanout" DstPort 2 } Line { SrcBlock "Register23" SrcPort 1 DstBlock "Fanout" DstPort 3 } Line { SrcBlock "Register33" SrcPort 1 DstBlock "Register34" DstPort 1 } Line { SrcBlock "Register34" SrcPort 1 DstBlock "Goto21" DstPort 1 } Line { SrcBlock "Register35" SrcPort 1 DstBlock "Goto32" DstPort 1 } Line { SrcBlock "Register36" SrcPort 1 DstBlock "Register35" DstPort 1 } Line { SrcBlock "Register44" SrcPort 1 DstBlock "Goto13" DstPort 1 } Line { SrcBlock "Register45" SrcPort 1 DstBlock "Goto25" DstPort 1 } Line { SrcBlock "Register46" SrcPort 1 DstBlock "Goto26" DstPort 1 } Line { SrcBlock "Register47" SrcPort 1 DstBlock "Goto31" DstPort 1 } Line { Labels [0, 0] SrcBlock "Register48" SrcPort 1 DstBlock "Register49" DstPort 1 } Line { Labels [0, 0] SrcBlock "Register49" SrcPort 1 DstBlock "Config Bits" DstPort 1 } Line { SrcBlock "Register51" SrcPort 1 DstBlock "Register52" DstPort 1 } Line { SrcBlock "Register52" SrcPort 1 DstBlock "Convert" DstPort 1 } Line { SrcBlock "Register55" SrcPort 1 DstBlock "Register16" DstPort 1 } Line { SrcBlock "Register56" SrcPort 1 DstBlock "Register17" DstPort 1 } Line { SrcBlock "Register57" SrcPort 1 DstBlock "Register18" DstPort 1 } Line { SrcBlock "Register25" SrcPort 1 DstBlock "Register26" DstPort 1 } Line { SrcBlock "Register26" SrcPort 1 DstBlock "Goto15" DstPort 1 } Line { SrcBlock "From Register13" SrcPort 1 Points [100, 0] Branch { DstBlock "b[7:0] 2" DstPort 1 } Branch { Points [0, 65] DstBlock "b[21:8]" DstPort 1 } } Line { SrcBlock "b[7:0] 2" SrcPort 1 DstBlock "To_UFix8_3" DstPort 1 } Line { SrcBlock "To_UFix8_3" SrcPort 1 DstBlock "Register20" DstPort 1 } Line { SrcBlock "Register20" SrcPort 1 DstBlock "Fanout2" DstPort 1 } Line { SrcBlock "b[21:8]" SrcPort 1 DstBlock "To_UFix8_2" DstPort 1 } Line { SrcBlock "Register22" SrcPort 1 DstBlock "Fanout2" DstPort 2 } Line { SrcBlock "From9" SrcPort 1 DstBlock "Concat" DstPort 1 } Line { SrcBlock "From Register10" SrcPort 1 DstBlock "Register30" DstPort 1 } Line { SrcBlock "Register30" SrcPort 1 DstBlock "Register31" DstPort 1 } Line { SrcBlock "Register31" SrcPort 1 DstBlock "Register32" DstPort 1 } Line { SrcBlock "Register32" SrcPort 1 DstBlock "Goto12" DstPort 1 } Line { SrcBlock "From1" SrcPort 1 DstBlock "Register38" DstPort 1 } Line { SrcBlock "Constant3" SrcPort 1 DstBlock "To Register1" DstPort 2 } Line { SrcBlock "To Register1" SrcPort 1 DstBlock "Terminator1" DstPort 1 } Line { SrcBlock "To_UFix8_4" SrcPort 1 DstBlock "To Register1" DstPort 1 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "To_UFix8_4" DstPort 1 } Line { SrcBlock "Register38" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "b[19:15]" SrcPort 1 DstBlock "Register53" DstPort 1 } Line { SrcBlock "Register39" SrcPort 1 DstBlock "Register12" DstPort 1 } Line { SrcBlock "Register42" SrcPort 1 DstBlock "Register64" DstPort 1 } Line { SrcBlock "Register43" SrcPort 1 DstBlock "Register65" DstPort 1 } Line { SrcBlock "Register53" SrcPort 1 DstBlock "Register66" DstPort 1 } Line { SrcBlock "Register54" SrcPort 1 DstBlock "Register67" DstPort 1 } Line { SrcBlock "Register58" SrcPort 1 DstBlock "Register68" DstPort 1 } Line { SrcBlock "From Register15" SrcPort 1 DstBlock "Register59" DstPort 1 } Line { SrcBlock "Register59" SrcPort 1 Points [20, 0] Branch { DstBlock "b[11:0]" DstPort 1 } Branch { Points [0, 40] Branch { DstBlock "b[23:0]" DstPort 1 } Branch { Points [0, 75] DstBlock "b[29:24]1" DstPort 1 } } } Line { SrcBlock "b[11:0]" SrcPort 1 DstBlock "To_UFix8_5" DstPort 1 } Line { SrcBlock "b[23:0]" SrcPort 1 DstBlock "To_UFix8_6" DstPort 1 } Line { SrcBlock "To_UFix8_5" SrcPort 1 DstBlock "Register69" DstPort 1 } Line { SrcBlock "To_UFix8_6" SrcPort 1 DstBlock "Register70" DstPort 1 } Line { SrcBlock "Register60" SrcPort 1 DstBlock "Goto22" DstPort 1 } Line { SrcBlock "Register62" SrcPort 1 DstBlock "Goto23" DstPort 1 } Line { SrcBlock "b[31:16]1" SrcPort 1 DstBlock "Register85" DstPort 1 } Line { SrcBlock "b[15:0]1" SrcPort 1 DstBlock "Register86" DstPort 1 } Line { SrcBlock "Register85" SrcPort 1 DstBlock "Register87" DstPort 1 } Line { SrcBlock "Register86" SrcPort 1 DstBlock "Register90" DstPort 1 } Line { SrcBlock "From Register16" SrcPort 1 Points [35, 0] Branch { Points [0, 40] DstBlock "b[31:16]1" DstPort 1 } Branch { DstBlock "b[15:0]1" DstPort 1 } } Line { SrcBlock "Register87" SrcPort 1 DstBlock "Goto34" DstPort 1 } Line { SrcBlock "Register90" SrcPort 1 DstBlock "Goto33" DstPort 1 } Line { SrcBlock "b[26:24]" SrcPort 1 DstBlock "Register88" DstPort 1 } Line { SrcBlock "Register88" SrcPort 1 DstBlock "Register89" DstPort 1 } Line { SrcBlock "Register89" SrcPort 1 DstBlock "Goto35" DstPort 1 } Line { SrcBlock "b[29:24]1" SrcPort 1 DstBlock "Register63" DstPort 1 } Line { SrcBlock "Register61" SrcPort 1 DstBlock "Goto24" DstPort 1 } Line { SrcBlock "Register63" SrcPort 1 DstBlock "Register61" DstPort 1 } Line { SrcBlock "Register1" SrcPort 1 DstBlock "Goto1" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Goto2" DstPort 1 } Line { SrcBlock "Register3" SrcPort 1 DstBlock "Goto3" DstPort 1 } Line { SrcBlock "Register12" SrcPort 1 DstBlock "Goto19" DstPort 1 } Line { SrcBlock "Register64" SrcPort 1 DstBlock "Goto27" DstPort 1 } Line { SrcBlock "Register65" SrcPort 1 DstBlock "Goto28" DstPort 1 } Line { SrcBlock "Register66" SrcPort 1 DstBlock "Goto29" DstPort 1 } Line { SrcBlock "Register67" SrcPort 1 DstBlock "Goto17" DstPort 1 } Line { SrcBlock "Register68" SrcPort 1 DstBlock "Goto20" DstPort 1 } Line { SrcBlock "Register69" SrcPort 1 DstBlock "Register60" DstPort 1 } Line { SrcBlock "Register70" SrcPort 1 DstBlock "Register62" DstPort 1 } Line { SrcBlock "Register72" SrcPort 1 DstBlock "Goto9" DstPort 1 } Line { SrcBlock "Register73" SrcPort 1 DstBlock "2x " DstPort 1 } Line { SrcBlock "Register74" SrcPort 1 DstBlock "Goto30" DstPort 1 } Line { SrcBlock "Register75" SrcPort 1 DstBlock "Goto16" DstPort 1 } Line { SrcBlock "b[7:0]1" SrcPort 1 DstBlock "Register28" DstPort 1 } Line { SrcBlock "From Register9" SrcPort 1 DstBlock "Register27" DstPort 1 } Line { SrcBlock "b[24]" SrcPort 1 DstBlock "Goto7" DstPort 1 } Line { SrcBlock "b[25]" SrcPort 1 DstBlock "Goto18" DstPort 1 } Line { SrcBlock "Register24" SrcPort 1 Points [30, 0] Branch { Points [0, 55] Branch { DstBlock "b[24]" DstPort 1 } Branch { Points [0, 35] DstBlock "b[25]" DstPort 1 } } Branch { DstBlock "b[15:0]2" DstPort 1 } } Line { SrcBlock "Register27" SrcPort 1 DstBlock "Register24" DstPort 1 } Line { SrcBlock "From Register18" SrcPort 1 DstBlock "Register41" DstPort 1 } Line { SrcBlock "From Register17" SrcPort 1 DstBlock "Register71" DstPort 1 } Line { SrcBlock "Register37" SrcPort 1 DstBlock "Goto37" DstPort 1 } Line { SrcBlock "Register40" SrcPort 1 DstBlock "Goto38" DstPort 1 } Line { SrcBlock "Register41" SrcPort 1 DstBlock "Register40" DstPort 1 } Line { SrcBlock "Register71" SrcPort 1 DstBlock "Register37" DstPort 1 } Line { SrcBlock "b[15:0]2" SrcPort 1 DstBlock "Goto14" DstPort 1 } Line { SrcBlock "b[15:8]1" SrcPort 1 DstBlock "Register29" DstPort 1 } Line { SrcBlock "b[23:16]2" SrcPort 1 DstBlock "Register76" DstPort 1 } Line { SrcBlock "Register28" SrcPort 1 DstBlock "Register77" DstPort 1 } Line { SrcBlock "Register29" SrcPort 1 DstBlock "Register78" DstPort 1 } Line { SrcBlock "Register76" SrcPort 1 DstBlock "Register79" DstPort 1 } Line { SrcBlock "Register77" SrcPort 1 DstBlock "Goto5" DstPort 1 } Line { SrcBlock "Register78" SrcPort 1 DstBlock "Goto8" DstPort 1 } Line { SrcBlock "Register79" SrcPort 1 DstBlock "Goto11" DstPort 1 } Line { SrcBlock "Register80" SrcPort 1 DstBlock "Register81" DstPort 1 } Line { SrcBlock "b[31:24]" SrcPort 1 DstBlock "Register80" DstPort 1 } Line { SrcBlock "Register81" SrcPort 1 DstBlock "Goto36" DstPort 1 } Line { SrcBlock "To_UFix8_2" SrcPort 1 DstBlock "Register22" DstPort 1 } Line { SrcBlock "Constant6" SrcPort 1 DstBlock "To Register5" DstPort 2 } Line { SrcBlock "To Register5" SrcPort 1 DstBlock "Terminator5" DstPort 1 } Line { SrcBlock "Convert5" SrcPort 1 DstBlock "To Register5" DstPort 1 } Line { SrcBlock "From10" SrcPort 1 DstBlock "Register83" DstPort 1 } Line { SrcBlock "Register82" SrcPort 1 DstBlock "Convert5" DstPort 1 } Line { SrcBlock "Register83" SrcPort 1 DstBlock "Register82" DstPort 1 } Line { SrcBlock "Constant7" SrcPort 1 DstBlock "To Register6" DstPort 2 } Line { SrcBlock "To Register6" SrcPort 1 DstBlock "Terminator6" DstPort 1 } Line { SrcBlock "Convert6" SrcPort 1 DstBlock "To Register6" DstPort 1 } Line { SrcBlock "From11" SrcPort 1 DstBlock "Register91" DstPort 1 } Line { SrcBlock "Register84" SrcPort 1 DstBlock "Convert6" DstPort 1 } Line { SrcBlock "Register91" SrcPort 1 DstBlock "Register84" DstPort 1 } Line { SrcBlock "Register50" SrcPort 1 DstBlock "Goto4" DstPort 1 } Line { SrcBlock "Constant8" SrcPort 1 DstBlock "To Register7" DstPort 2 } Line { SrcBlock "To Register7" SrcPort 1 DstBlock "Terminator7" DstPort 1 } Line { SrcBlock "Convert7" SrcPort 1 DstBlock "To Register7" DstPort 1 } Line { SrcBlock "Register92" SrcPort 1 DstBlock "To_UFix8_8" DstPort 1 } Line { SrcBlock "From12" SrcPort 1 DstBlock "Register93" DstPort 1 } Line { SrcBlock "Register93" SrcPort 1 DstBlock "Register92" DstPort 1 } Line { SrcBlock "To_UFix8_8" SrcPort 1 DstBlock "Convert7" DstPort 1 } Annotation { Name "IMPORTANT: FFT_Scaling cannot have > 1 cycle latency from the AXI reg. Otherwise\nthe FFT core sim adopts" " the wrong scaling on the first sim run. Unclear if this issue\nwould also occur in hardware." Position [519, 1475] } } } Block { BlockType SubSystem Name "Resets" SID "4131" Ports [] Position [496, 286, 544, 334] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Resets" Location [88, 301, 2330, 1301] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Reference Name "Convert1" SID "4132" Ports [1, 1] Position [750, 466, 785, 484] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "16" bin_pt "14" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "35,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 18 18 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[11.22 11.22 1" "3.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[9.22 9.22 11.22 11.22 9.22" " ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([14" ".55 21.44 19.44 17.44 15.44 12.55 14.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf(''," "'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'ca" "st');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From2" SID "4133" Position [460, 466, 615, 484] ShowName off CloseFcn "tagdialog Close" GotoTag "regRx_Global_Reset" TagVisibility "global" } Block { BlockType Goto Name "Goto" SID "4134" Position [865, 464, 1030, 486] ZOrder -10 ShowName off GotoTag "RX_GLOBAL_RESET" TagVisibility "global" } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Goto" DstPort 1 } Line { SrcBlock "From2" SrcPort 1 DstBlock "Convert1" DstPort 1 } } } Block { BlockType SubSystem Name "Sync & Antenna Sel" SID "4136" Ports [5, 6] Position [200, 150, 310, 210] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Sync & Antenna Sel" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "125" Block { BlockType Inport Name "Rx I" SID "4137" Position [365, 283, 395, 297] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "Rx Q" SID "4138" Position [365, 313, 395, 327] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "IQ Valid" SID "4139" Position [365, 343, 395, 357] NamePlacement "alternate" Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "RSSI" SID "4140" Position [365, 373, 395, 387] NamePlacement "alternate" Port "4" IconDisplay "Port number" } Block { BlockType Inport Name "Reset " SID "4141" Position [140, 218, 170, 232] NamePlacement "alternate" Port "5" IconDisplay "Port number" } Block { BlockType Scope Name "ADC/Corr" SID "4142" Ports [10] Position [1210, 12, 1245, 183] ZOrder -3 Floating off Location [135, 36, 1477, 1194] Open off NumInputPorts "10" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" axes9 "%" axes10 "%" } List { ListType ScopeGraphics FigureColor "[0.501960784313725 0.501960784313725 0.501960784313725]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[2 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "13944" YMin "0.95~-1~-1~0.95~-1~-1~-1~-1~-1~-1" YMax "1.05~1~1~1.05~1~1~1~1~1~1" SaveName "ScopeData34" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType SubSystem Name "Antenna Selection" SID "4143" Ports [6, 4] Position [675, 400, 765, 505] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off Port { PortNumber 4 Name "Avg RSSI" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } System { Name "Antenna Selection" Location [432, 441, 567, 604] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Pkt Det" SID "4144" Position [305, 678, 335, 692] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "Rx I Vec" SID "4145" Position [1180, 673, 1210, 687] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "Rx Q Vec" SID "4146" Position [1180, 788, 1210, 802] NamePlacement "alternate" Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "IQ Valid" SID "4147" Position [1180, 558, 1210, 572] NamePlacement "alternate" Port "4" IconDisplay "Port number" } Block { BlockType Inport Name "RSSI Vec" SID "4148" Position [1180, 908, 1210, 922] NamePlacement "alternate" Port "5" IconDisplay "Port number" } Block { BlockType Inport Name "Reset" SID "4149" Position [495, 793, 525, 807] NamePlacement "alternate" Port "6" IconDisplay "Port number" } Block { BlockType SubSystem Name "Ant Sel Logic" SID "4150" Ports [4, 1] Position [795, 701, 855, 764] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Ant Sel Logic" Location [138, 279, 2317, 1561] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "110" Block { BlockType Inport Name "G A" SID "4151" Position [250, 353, 280, 367] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "G B" SID "4152" Position [250, 383, 280, 397] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "G C" SID "4153" Position [250, 613, 280, 627] NamePlacement "alternate" Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "G D" SID "4154" Position [250, 643, 280, 657] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "Concat" SID "4155" Ports [2, 1] Position [1025, 408, 1075, 517] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point at z" "ero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "50,109,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 109 109 0 ],[0.77 0.82 0" ".91 ]);\nplot([0 50 50 0 0 ],[0 0 109 109 0 ]);\npatch([9.425 19.54 26.54 33.54 40.54 26.54 16.425 9.425 ],[61.77 " "61.77 68.77 61.77 68.77 68.77 68.77 61.77 ],[1 1 1 ]);\npatch([16.425 26.54 19.54 9.425 16.425 ],[54.77 54.77 61.7" "7 61.77 54.77 ],[0.931 0.946 0.973 ]);\npatch([9.425 19.54 26.54 16.425 9.425 ],[47.77 47.77 54.77 54.77 47.77 ],[" "1 1 1 ]);\npatch([16.425 40.54 33.54 26.54 19.54 9.425 16.425 ],[40.77 40.77 47.77 40.77 47.77 47.77 40.77 ],[0.93" "1 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('blac" "k');port_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fontsize{20}" "\\}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From4" SID "4156" Position [1085, 350, 1285, 370] ShowName off CloseFcn "tagdialog Close" GotoTag "regRx_noSwitching_AntSel" TagVisibility "global" } Block { BlockType From Name "From6" SID "4157" Position [1085, 310, 1285, 330] ShowName off CloseFcn "tagdialog Close" GotoTag "regRx_switchingDiv_En" TagVisibility "global" } Block { BlockType Reference Name "Inverter2" SID "4158" Ports [1, 1] Position [1200, 457, 1225, 473] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "25,16,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 16 16 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 16 16 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[10.22 10.22 12" ".22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[8.22 8.22 10.22 10.22 8.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Mux" SID "4159" Ports [3, 1] Position [650, 352, 685, 488] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "35,136,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 19.4286 116.571 136 0 ],[0" ".77 0.82 0.91 ]);\nplot([0 35 35 0 0 ],[0 19.4286 116.571 136 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 " "5.875 ],[73.55 73.55 78.55 73.55 78.55 78.55 78.55 73.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[68." "55 68.55 73.55 73.55 68.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[63.55 63.55 68.55 68.5" "5 63.55 ],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[58.55 58.55 63.55 58.55 63.55 63.55 58.55 " "],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolo" "r('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('in" "put',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux1" SID "4160" Ports [3, 1] Position [645, 612, 680, 748] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "35,136,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 19.4286 116.571 136 0 ],[0" ".77 0.82 0.91 ]);\nplot([0 35 35 0 0 ],[0 19.4286 116.571 136 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 " "5.875 ],[73.55 73.55 78.55 73.55 78.55 78.55 78.55 73.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[68." "55 68.55 73.55 73.55 68.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[63.55 63.55 68.55 68.5" "5 63.55 ],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[58.55 58.55 63.55 58.55 63.55 63.55 58.55 " "],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolo" "r('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('in" "put',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux2" SID "4161" Ports [3, 1] Position [935, 463, 965, 587] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "30,124,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 17.7143 106.286 124 0 ],[0" ".77 0.82 0.91 ]);\nplot([0 30 30 0 0 ],[0 17.7143 106.286 124 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1" " 6.1 ],[66.44 66.44 70.44 66.44 70.44 70.44 70.44 66.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[62.44 62" ".44 66.44 66.44 62.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[58.44 58.44 62.44 62.44 58.44 ]" ",[1 1 1 ]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[54.44 54.44 58.44 54.44 58.44 58.44 54.44 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3,'d1'" ");\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux3" SID "4162" Ports [3, 1] Position [1395, 298, 1425, 422] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "30,124,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 17.7143 106.286 124 0 ],[0" ".77 0.82 0.91 ]);\nplot([0 30 30 0 0 ],[0 17.7143 106.286 124 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1" " 6.1 ],[66.44 66.44 70.44 66.44 70.44 70.44 70.44 66.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[62.44 62" ".44 66.44 66.44 62.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[58.44 58.44 62.44 62.44 58.44 ]" ",[1 1 1 ]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[54.44 54.44 58.44 54.44 58.44 58.44 54.44 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3,'d1'" ");\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "RF A En Mask" SID "4163" Ports [1, 1] Position [340, 348, 395, 372] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "RF A En Mask" Location [198, 510, 881, 659] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "GA" SID "4164" Position [255, 73, 285, 87] IconDisplay "Port number" } Block { BlockType Reference Name "Concat1" SID "4165" Ports [7, 1] Position [360, 31, 400, 69] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point " "at zero." num_inputs "7" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "40,38,7,1,white,blue,0,5db75f69,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 38 38 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 38 38 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[24.55 24." "55 29.55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[19.55 19.55 24.55 2" "4.55 19.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');por" "t_label('input',1,'hi');\n\n\n\n\n\ncolor('black');port_label('input',7,'lo');\n\ncolor('black');disp('\\fontsiz" "e{20}\\}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From5" SID "4166" Position [25, 25, 225, 45] ShowName off CloseFcn "tagdialog Close" GotoTag "regRx_pktDetEn_RFA" TagVisibility "global" } Block { BlockType Reference Name "Inverter1" SID "4167" Ports [1, 1] Position [280, 27, 305, 43] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "25,16,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 16 16 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[10.22 10" ".22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[8.22 8.22 10.22 10.22" " 8.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical3" SID "4168" Ports [2, 1] Position [440, 37, 470, 93] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "30,56,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 56 56 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 56 56 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[32.44 32.4" "4 36.44 32.44 36.44 36.44 36.44 32.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[28.44 28.44 32.44 32.44 " "28.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[24.44 24.44 28.44 28.44 24.44 ],[1 1 1 ]);\np" "atch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[20.44 20.44 24.44 20.44 24.44 24.44 20.44 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp" "('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name " GA" SID "4169" Position [495, 58, 525, 72] IconDisplay "Port number" } Line { SrcBlock "From5" SrcPort 1 DstBlock "Inverter1" DstPort 1 } Line { SrcBlock "Inverter1" SrcPort 1 Points [35, 0] Branch { DstBlock "Concat1" DstPort 1 } Branch { Points [0, 5] Branch { DstBlock "Concat1" DstPort 2 } Branch { Points [0, 5] Branch { DstBlock "Concat1" DstPort 3 } Branch { Points [0, 5] Branch { DstBlock "Concat1" DstPort 4 } Branch { Points [0, 5] Branch { DstBlock "Concat1" DstPort 5 } Branch { Points [0, 5] Branch { DstBlock "Concat1" DstPort 6 } Branch { DstBlock "Concat1" DstPort 7 } } } } } } } Line { SrcBlock "Concat1" SrcPort 1 DstBlock "Logical3" DstPort 1 } Line { SrcBlock "Logical3" SrcPort 1 DstBlock " GA" DstPort 1 } Line { SrcBlock "GA" SrcPort 1 DstBlock "Logical3" DstPort 2 } Annotation { Name "If this antenna isn't enabled for pkt det override the actual\ngain values with the max value, so the" " selection diversity\nlogic never selects this antenna." Position [263, 154] } } } Block { BlockType SubSystem Name "RF B En Mask" SID "4170" Ports [1, 1] Position [340, 378, 395, 402] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "RF B En Mask" Location [138, 279, 2317, 1561] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "GB" SID "4171" Position [255, 73, 285, 87] IconDisplay "Port number" } Block { BlockType Reference Name "Concat1" SID "4172" Ports [7, 1] Position [360, 31, 400, 69] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point " "at zero." num_inputs "7" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "40,38,7,1,white,blue,0,5db75f69,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 38 38 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 38 38 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[24.55 24." "55 29.55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[19.55 19.55 24.55 2" "4.55 19.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');por" "t_label('input',1,'hi');\n\n\n\n\n\ncolor('black');port_label('input',7,'lo');\n\ncolor('black');disp('\\fontsiz" "e{20}\\}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From5" SID "4173" Position [25, 25, 225, 45] ShowName off CloseFcn "tagdialog Close" GotoTag "regRx_pktDetEn_RFB" TagVisibility "global" } Block { BlockType Reference Name "Inverter1" SID "4174" Ports [1, 1] Position [280, 27, 305, 43] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "25,16,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 16 16 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[10.22 10" ".22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[8.22 8.22 10.22 10.22" " 8.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical3" SID "4175" Ports [2, 1] Position [440, 37, 470, 93] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "30,56,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 56 56 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 56 56 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[32.44 32.4" "4 36.44 32.44 36.44 36.44 36.44 32.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[28.44 28.44 32.44 32.44 " "28.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[24.44 24.44 28.44 28.44 24.44 ],[1 1 1 ]);\np" "atch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[20.44 20.44 24.44 20.44 24.44 24.44 20.44 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp" "('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name " GB" SID "4176" Position [495, 58, 525, 72] IconDisplay "Port number" } Line { SrcBlock "GB" SrcPort 1 DstBlock "Logical3" DstPort 2 } Line { SrcBlock "Logical3" SrcPort 1 DstBlock " GB" DstPort 1 } Line { SrcBlock "Concat1" SrcPort 1 DstBlock "Logical3" DstPort 1 } Line { SrcBlock "Inverter1" SrcPort 1 Points [35, 0] Branch { Points [0, 5] Branch { Points [0, 5] Branch { Points [0, 5] Branch { Points [0, 5] Branch { Points [0, 5] Branch { DstBlock "Concat1" DstPort 7 } Branch { DstBlock "Concat1" DstPort 6 } } Branch { DstBlock "Concat1" DstPort 5 } } Branch { DstBlock "Concat1" DstPort 4 } } Branch { DstBlock "Concat1" DstPort 3 } } Branch { DstBlock "Concat1" DstPort 2 } } Branch { DstBlock "Concat1" DstPort 1 } } Line { SrcBlock "From5" SrcPort 1 DstBlock "Inverter1" DstPort 1 } Annotation { Name "If this antenna isn't enabled for pkt det override the actual\ngain values with the max value, so the" " selection diversity\nlogic never selects this antenna." Position [253, 174] } } } Block { BlockType SubSystem Name "RF C En Mask" SID "4177" Ports [1, 1] Position [340, 608, 395, 632] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "RF C En Mask" Location [138, 279, 2317, 1561] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "GC" SID "4178" Position [255, 73, 285, 87] IconDisplay "Port number" } Block { BlockType Reference Name "Concat1" SID "4179" Ports [7, 1] Position [360, 31, 400, 69] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point " "at zero." num_inputs "7" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "40,38,7,1,white,blue,0,5db75f69,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 38 38 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 38 38 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[24.55 24." "55 29.55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[19.55 19.55 24.55 2" "4.55 19.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');por" "t_label('input',1,'hi');\n\n\n\n\n\ncolor('black');port_label('input',7,'lo');\n\ncolor('black');disp('\\fontsiz" "e{20}\\}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From5" SID "4180" Position [25, 25, 225, 45] ShowName off CloseFcn "tagdialog Close" GotoTag "regRx_pktDetEn_RFC" TagVisibility "global" } Block { BlockType Reference Name "Inverter1" SID "4181" Ports [1, 1] Position [280, 27, 305, 43] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "25,16,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 16 16 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[10.22 10" ".22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[8.22 8.22 10.22 10.22" " 8.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical3" SID "4182" Ports [2, 1] Position [440, 37, 470, 93] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "30,56,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 56 56 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 56 56 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[32.44 32.4" "4 36.44 32.44 36.44 36.44 36.44 32.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[28.44 28.44 32.44 32.44 " "28.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[24.44 24.44 28.44 28.44 24.44 ],[1 1 1 ]);\np" "atch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[20.44 20.44 24.44 20.44 24.44 24.44 20.44 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp" "('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name " GC" SID "4183" Position [495, 58, 525, 72] IconDisplay "Port number" } Line { SrcBlock "GC" SrcPort 1 DstBlock "Logical3" DstPort 2 } Line { SrcBlock "Logical3" SrcPort 1 DstBlock " GC" DstPort 1 } Line { SrcBlock "Concat1" SrcPort 1 DstBlock "Logical3" DstPort 1 } Line { SrcBlock "Inverter1" SrcPort 1 Points [35, 0] Branch { Points [0, 5] Branch { Points [0, 5] Branch { Points [0, 5] Branch { Points [0, 5] Branch { Points [0, 5] Branch { DstBlock "Concat1" DstPort 7 } Branch { DstBlock "Concat1" DstPort 6 } } Branch { DstBlock "Concat1" DstPort 5 } } Branch { DstBlock "Concat1" DstPort 4 } } Branch { DstBlock "Concat1" DstPort 3 } } Branch { DstBlock "Concat1" DstPort 2 } } Branch { DstBlock "Concat1" DstPort 1 } } Line { SrcBlock "From5" SrcPort 1 DstBlock "Inverter1" DstPort 1 } Annotation { Name "If this antenna isn't enabled for pkt det override the actual\ngain values with the max value, so the" " selection diversity\nlogic never selects this antenna." Position [243, 164] } } } Block { BlockType SubSystem Name "RF D En Mask" SID "4184" Ports [1, 1] Position [340, 638, 395, 662] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "RF D En Mask" Location [138, 279, 2317, 1561] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "GD" SID "4185" Position [255, 73, 285, 87] IconDisplay "Port number" } Block { BlockType Reference Name "Concat1" SID "4186" Ports [7, 1] Position [360, 31, 400, 69] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point " "at zero." num_inputs "7" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "40,38,7,1,white,blue,0,5db75f69,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 38 38 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 38 38 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[24.55 24." "55 29.55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[19.55 19.55 24.55 2" "4.55 19.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');por" "t_label('input',1,'hi');\n\n\n\n\n\ncolor('black');port_label('input',7,'lo');\n\ncolor('black');disp('\\fontsiz" "e{20}\\}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From5" SID "4187" Position [25, 25, 225, 45] ShowName off CloseFcn "tagdialog Close" GotoTag "regRx_pktDetEn_RFD" TagVisibility "global" } Block { BlockType Reference Name "Inverter1" SID "4188" Ports [1, 1] Position [280, 27, 305, 43] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "25,16,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 16 16 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[10.22 10" ".22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[8.22 8.22 10.22 10.22" " 8.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical3" SID "4189" Ports [2, 1] Position [440, 37, 470, 93] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "30,56,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 56 56 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 56 56 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[32.44 32.4" "4 36.44 32.44 36.44 36.44 36.44 32.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[28.44 28.44 32.44 32.44 " "28.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[24.44 24.44 28.44 28.44 24.44 ],[1 1 1 ]);\np" "atch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[20.44 20.44 24.44 20.44 24.44 24.44 20.44 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp" "('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name " GD" SID "4190" Position [495, 58, 525, 72] IconDisplay "Port number" } Line { SrcBlock "From5" SrcPort 1 DstBlock "Inverter1" DstPort 1 } Line { SrcBlock "Inverter1" SrcPort 1 Points [35, 0] Branch { DstBlock "Concat1" DstPort 1 } Branch { Points [0, 5] Branch { DstBlock "Concat1" DstPort 2 } Branch { Points [0, 5] Branch { DstBlock "Concat1" DstPort 3 } Branch { Points [0, 5] Branch { DstBlock "Concat1" DstPort 4 } Branch { Points [0, 5] Branch { DstBlock "Concat1" DstPort 5 } Branch { Points [0, 5] Branch { DstBlock "Concat1" DstPort 6 } Branch { DstBlock "Concat1" DstPort 7 } } } } } } } Line { SrcBlock "Concat1" SrcPort 1 DstBlock "Logical3" DstPort 1 } Line { SrcBlock "Logical3" SrcPort 1 DstBlock " GD" DstPort 1 } Line { SrcBlock "GD" SrcPort 1 DstBlock "Logical3" DstPort 2 } Annotation { Name "If this antenna isn't enabled for pkt det override the actual\ngain values with the max value, so the" " selection diversity\nlogic never selects this antenna." Position [288, 169] } } } Block { BlockType Reference Name "Relational" SID "4191" Ports [2, 1] Position [495, 347, 550, 403] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a<=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "55,56,2,1,white,blue,0,52e4b236,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 55 55 0 0 ],[0 0 56 56 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ],[35.77 35" ".77 42.77 35.77 42.77 42.77 42.77 35.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[28.77 28.77 35.77" " 35.77 28.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[21.77 21.77 28.77 28.77 21.77 ]," "[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[14.77 14.77 21.77 14.77 21.77 21.77 14.77 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1," "'\\bfa \\leq b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational1" SID "4192" Ports [2, 1] Position [495, 607, 550, 663] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a<=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "55,56,2,1,white,blue,0,52e4b236,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 55 55 0 0 ],[0 0 56 56 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ],[35.77 35" ".77 42.77 35.77 42.77 42.77 42.77 35.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[28.77 28.77 35.77" " 35.77 28.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[21.77 21.77 28.77 28.77 21.77 ]," "[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[14.77 14.77 21.77 14.77 21.77 21.77 14.77 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1," "'\\bfa \\leq b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational2" SID "4193" Ports [2, 1] Position [820, 407, 875, 463] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a<=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "55,56,2,1,white,blue,0,52e4b236,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 55 55 0 0 ],[0 0 56 56 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ],[35.77 35" ".77 42.77 35.77 42.77 42.77 42.77 35.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[28.77 28.77 35.77" " 35.77 28.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[21.77 21.77 28.77 28.77 21.77 ]," "[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[14.77 14.77 21.77 14.77 21.77 21.77 14.77 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1," "'\\bfa \\leq b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Ant Sel" SID "4194" Position [1495, 352, 1525, 368] NamePlacement "alternate" IconDisplay "Port number" } Line { SrcBlock "RF D En Mask" SrcPort 1 Points [65, 0] Branch { DstBlock "Relational1" DstPort 2 } Branch { Points [0, 30] DstBlock "Mux1" DstPort 2 } } Line { SrcBlock "RF C En Mask" SrcPort 1 Points [60, 0] Branch { DstBlock "Relational1" DstPort 1 } Branch { Points [0, 105] DstBlock "Mux1" DstPort 3 } } Line { SrcBlock "RF B En Mask" SrcPort 1 Points [65, 0] Branch { DstBlock "Relational" DstPort 2 } Branch { Points [0, 30] DstBlock "Mux" DstPort 2 } } Line { SrcBlock "RF A En Mask" SrcPort 1 Points [60, 0] Branch { DstBlock "Relational" DstPort 1 } Branch { Points [0, 105] DstBlock "Mux" DstPort 3 } } Line { SrcBlock "Relational" SrcPort 1 Points [65, 0] Branch { DstBlock "Mux" DstPort 1 } Branch { Points [0, 190] DstBlock "Mux2" DstPort 3 } } Line { SrcBlock "Mux" SrcPort 1 DstBlock "Relational2" DstPort 1 } Line { SrcBlock "Relational1" SrcPort 1 Points [45, 0] Branch { DstBlock "Mux1" DstPort 1 } Branch { Points [0, -110] DstBlock "Mux2" DstPort 2 } } Line { SrcBlock "Mux1" SrcPort 1 Points [25, 0; 0, -230] DstBlock "Relational2" DstPort 2 } Line { SrcBlock "Relational2" SrcPort 1 Points [20, 0] Branch { DstBlock "Concat" DstPort 1 } Branch { Points [0, 50] DstBlock "Mux2" DstPort 1 } } Line { SrcBlock "Mux2" SrcPort 1 Points [20, 0; 0, -35] DstBlock "Concat" DstPort 2 } Line { SrcBlock "Concat" SrcPort 1 DstBlock "Inverter2" DstPort 1 } Line { SrcBlock "Inverter2" SrcPort 1 Points [110, 0; 0, -65] DstBlock "Mux3" DstPort 3 } Line { SrcBlock "From6" SrcPort 1 DstBlock "Mux3" DstPort 1 } Line { SrcBlock "G A" SrcPort 1 DstBlock "RF A En Mask" DstPort 1 } Line { SrcBlock "G B" SrcPort 1 DstBlock "RF B En Mask" DstPort 1 } Line { SrcBlock "G C" SrcPort 1 DstBlock "RF C En Mask" DstPort 1 } Line { SrcBlock "G D" SrcPort 1 DstBlock "RF D En Mask" DstPort 1 } Line { SrcBlock "From4" SrcPort 1 DstBlock "Mux3" DstPort 2 } Line { SrcBlock "Mux3" SrcPort 1 DstBlock "Ant Sel" DstPort 1 } Annotation { Name "[0 0] = RF A\n[0 1] = RF B\n[1 0] = RF C\n[1 1] = RF D" Position [1275, 504] } Annotation { Name "[1 1] = RF A\n[1 0] = RF B\n[0 1] = RF C\n[0 0] = RF D" Position [1145, 499] } } } Block { BlockType BusSelector Name "Bus\nSelector1" SID "4195" Ports [1, 4] Position [1285, 753, 1290, 837] ZOrder -3 ShowName off OutputSignals "RFA_Q,RFB_Q,RFC_Q,RFD_Q" Port { PortNumber 1 Name "" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 2 Name "" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 3 Name "" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 4 Name "" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType BusSelector Name "Bus\nSelector2" SID "4196" Ports [1, 4] Position [1285, 874, 1290, 956] ZOrder -3 ShowName off OutputSignals "RFA_RSSI,RFB_RSSI,RFC_RSSI,RFD_RSSI" Port { PortNumber 1 Name "" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 2 Name "" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 3 Name "" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 4 Name "" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType BusSelector Name "Bus\nSelector3" SID "4197" Ports [1, 4] Position [1285, 638, 1290, 722] ZOrder -3 ShowName off OutputSignals "RFA_I,RFB_I,RFC_I,RFD_I" Port { PortNumber 1 Name "" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 2 Name "" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 3 Name "" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 4 Name "" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType BusSelector Name "Bus\nSelector4" SID "4198" Ports [1, 4] Position [1280, 525, 1285, 605] ZOrder -3 ShowName off OutputSignals "signal1,signal2,signal3,signal4" Port { PortNumber 1 Name "" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 2 Name "" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 3 Name "" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 4 Name "" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Delay" SID "4199" Ports [1, 1] Position [640, 1001, 670, 1029] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "30,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 " "18.44 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 1" "8.44 14.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');di" "sp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From5" SID "4200" Position [225, 706, 355, 724] ShowName off CloseFcn "tagdialog Close" GotoTag "AGC_DONE" TagVisibility "global" } Block { BlockType Reference Name "Gateway Out" SID "4201" Ports [1, 1] Position [845, 490, 870, 500] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "25,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 10 10 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 25 25 0 0 ],[0 0 10 10 0 ]);\npatch([9.775 11.22 12.22 13.22 14.22 12.22 10.775 9.775 ],[" "6.11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([10.775 12.22 11.22 9.775 10.775 ],[5.11 5.11 6.11 " "6.11 5.11 ],[0.964 0.964 0.964 ]);\npatch([9.775 11.22 12.22 10.775 9.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 " "]);\npatch([10.775 14.22 13.22 12.22 11.22 9.775 10.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0." "964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');por" "t_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf" "('','COMMENT: end icon text');" Port { PortNumber 1 Name "Pkt Det" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out1" SID "4202" Ports [1, 1] Position [845, 505, 870, 515] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "25,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 10 10 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 25 25 0 0 ],[0 0 10 10 0 ]);\npatch([9.775 11.22 12.22 13.22 14.22 12.22 10.775 9.775 ],[" "6.11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([10.775 12.22 11.22 9.775 10.775 ],[5.11 5.11 6.11 " "6.11 5.11 ],[0.964 0.964 0.964 ]);\npatch([9.775 11.22 12.22 10.775 9.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 " "]);\npatch([10.775 14.22 13.22 12.22 11.22 9.775 10.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0." "964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');por" "t_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf" "('','COMMENT: end icon text');" Port { PortNumber 1 Name "AGC Done" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "4203" Ports [1, 1] Position [845, 520, 870, 530] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "25,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 10 10 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 25 25 0 0 ],[0 0 10 10 0 ]);\npatch([9.775 11.22 12.22 13.22 14.22 12.22 10.775 9.775 ],[" "6.11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([10.775 12.22 11.22 9.775 10.775 ],[5.11 5.11 6.11 " "6.11 5.11 ],[0.964 0.964 0.964 ]);\npatch([9.775 11.22 12.22 10.775 9.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 " "]);\npatch([10.775 14.22 13.22 12.22 11.22 9.775 10.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0." "964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');por" "t_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf" "('','COMMENT: end icon text');" Port { PortNumber 1 Name "G A" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "4204" Ports [1, 1] Position [845, 535, 870, 545] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "25,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 10 10 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 25 25 0 0 ],[0 0 10 10 0 ]);\npatch([9.775 11.22 12.22 13.22 14.22 12.22 10.775 9.775 ],[" "6.11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([10.775 12.22 11.22 9.775 10.775 ],[5.11 5.11 6.11 " "6.11 5.11 ],[0.964 0.964 0.964 ]);\npatch([9.775 11.22 12.22 10.775 9.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 " "]);\npatch([10.775 14.22 13.22 12.22 11.22 9.775 10.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0." "964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');por" "t_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf" "('','COMMENT: end icon text');" Port { PortNumber 1 Name "G B" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "4205" Ports [1, 1] Position [845, 550, 870, 560] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "25,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 10 10 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 25 25 0 0 ],[0 0 10 10 0 ]);\npatch([9.775 11.22 12.22 13.22 14.22 12.22 10.775 9.775 ],[" "6.11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([10.775 12.22 11.22 9.775 10.775 ],[5.11 5.11 6.11 " "6.11 5.11 ],[0.964 0.964 0.964 ]);\npatch([9.775 11.22 12.22 10.775 9.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 " "]);\npatch([10.775 14.22 13.22 12.22 11.22 9.775 10.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0." "964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');por" "t_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf" "('','COMMENT: end icon text');" Port { PortNumber 1 Name "G C" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "4206" Ports [1, 1] Position [845, 565, 870, 575] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "25,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 10 10 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 25 25 0 0 ],[0 0 10 10 0 ]);\npatch([9.775 11.22 12.22 13.22 14.22 12.22 10.775 9.775 ],[" "6.11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([10.775 12.22 11.22 9.775 10.775 ],[5.11 5.11 6.11 " "6.11 5.11 ],[0.964 0.964 0.964 ]);\npatch([9.775 11.22 12.22 10.775 9.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 " "]);\npatch([10.775 14.22 13.22 12.22 11.22 9.775 10.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0." "964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');por" "t_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf" "('','COMMENT: end icon text');" Port { PortNumber 1 Name "G D" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Goto Name "Goto1" SID "4207" Position [1035, 993, 1175, 1017] ZOrder -10 ShowName off GotoTag "ANTENNA_SEL" TagVisibility "global" } Block { BlockType Reference Name "Logical" SID "4208" Ports [2, 1] Position [400, 671, 435, 729] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,58,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 58 58 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 58 58 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[34.55" " 34.55 39.55 34.55 39.55 39.55 39.55 34.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[29.55 29.55 34" ".55 34.55 29.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[24.55 24.55 29.55 29.55 24.55 " "],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[19.55 19.55 24.55 19.55 24.55 24.55 19.55 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n" "color('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux1" SID "4209" Ports [5, 1] Position [1370, 616, 1390, 724] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "4" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "20,108,5,1,white,blue,3,d6c79293,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 15.4286 92.5714 108" " 0 ],[0.77 0.82 0.91 ]);\nplot([0 20 20 0 0 ],[0 15.4286 92.5714 108 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 " "10.44 7.55 5.55 ],[56.22 56.22 58.22 56.22 58.22 58.22 58.22 56.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7." "55 ],[54.22 54.22 56.22 56.22 54.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[52.22 52.22 5" "4.22 54.22 52.22 ],[1 1 1 ]);\npatch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[50.22 50.22 52.22 50.22 52.22 52" ".22 50.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon " "text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black'" ");port_label('input',3,'d1');\ncolor('black');port_label('input',4,'d2');\ncolor('black');port_label('input',5," "'d3');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux2" SID "4210" Ports [5, 1] Position [1370, 731, 1390, 839] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "4" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "20,108,5,1,white,blue,3,d6c79293,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 15.4286 92.5714 108" " 0 ],[0.77 0.82 0.91 ]);\nplot([0 20 20 0 0 ],[0 15.4286 92.5714 108 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 " "10.44 7.55 5.55 ],[56.22 56.22 58.22 56.22 58.22 58.22 58.22 56.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7." "55 ],[54.22 54.22 56.22 56.22 54.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[52.22 52.22 5" "4.22 54.22 52.22 ],[1 1 1 ]);\npatch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[50.22 50.22 52.22 50.22 52.22 52" ".22 50.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon " "text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black'" ");port_label('input',3,'d1');\ncolor('black');port_label('input',4,'d2');\ncolor('black');port_label('input',5," "'d3');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux3" SID "4211" Ports [5, 1] Position [1370, 501, 1390, 609] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "4" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "20,108,5,1,white,blue,3,d6c79293,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 15.4286 92.5714 108" " 0 ],[0.77 0.82 0.91 ]);\nplot([0 20 20 0 0 ],[0 15.4286 92.5714 108 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 " "10.44 7.55 5.55 ],[56.22 56.22 58.22 56.22 58.22 58.22 58.22 56.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7." "55 ],[54.22 54.22 56.22 56.22 54.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[52.22 52.22 5" "4.22 54.22 52.22 ],[1 1 1 ]);\npatch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[50.22 50.22 52.22 50.22 52.22 52" ".22 50.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon " "text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black'" ");port_label('input',3,'d1');\ncolor('black');port_label('input',4,'d2');\ncolor('black');port_label('input',5," "'d3');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux4" SID "4212" Ports [5, 1] Position [1370, 851, 1390, 959] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "4" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "20,108,5,1,white,blue,3,d6c79293,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 15.4286 92.5714 108" " 0 ],[0.77 0.82 0.91 ]);\nplot([0 20 20 0 0 ],[0 15.4286 92.5714 108 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 " "10.44 7.55 5.55 ],[56.22 56.22 58.22 56.22 58.22 58.22 58.22 56.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7." "55 ],[54.22 54.22 56.22 56.22 54.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[52.22 52.22 5" "4.22 54.22 52.22 ],[1 1 1 ]);\npatch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[50.22 50.22 52.22 50.22 52.22 52" ".22 50.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon " "text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black'" ");port_label('input',3,'d1');\ncolor('black');port_label('input',4,'d2');\ncolor('black');port_label('input',5," "'d3');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Posedge" SID "4213" Ports [1, 1] Position [490, 693, 525, 707] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Posedge" Location [88, 301, 2330, 1301] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "4214" Position [200, 253, 230, 267] IconDisplay "Port number" } Block { BlockType Reference Name "Delay" SID "4215" Ports [1, 1] Position [425, 153, 460, 177] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. If r" "egister retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[15.33 15" ".33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.33 12.33 15.33" " 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 " "1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');" "disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "4216" Ports [1, 1] Position [490, 156, 515, 174] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "4217" Ports [2, 1] Position [540, 151, 585, 204] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,53,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 53 53 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 53 53 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[32.66 32.66 3" "8.66 32.66 38.66 38.66 38.66 32.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[26.66 26.66 32.66 32.66 26" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[20.66 20.66 26.66 26.66 20.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[14.66 14.66 20.66 14.66 20.66 20.66 14.66 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('" "and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "4218" Position [610, 173, 640, 187] IconDisplay "Port number" } Line { SrcBlock "D" SrcPort 1 Points [150, 0; 0, -70] Branch { DstBlock "Logical1" DstPort 2 } Branch { Points [0, -25] DstBlock "Delay" DstPort 1 } } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Delay" SrcPort 1 DstBlock "Inverter" DstPort 1 } Annotation { Name "Rising Edge Detection" Position [500, 112] } } } Block { BlockType SubSystem Name "RF A Gains" SID "4219" Ports [2, 1] Position [615, 691, 695, 729] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "RF A Gains" Location [237, 698, 722, 914] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Capt" SID "4220" Position [165, 258, 195, 272] IconDisplay "Port number" } Block { BlockType Inport Name "Rst" SID "4221" Position [165, 238, 195, 252] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Concat" SID "4222" Ports [2, 1] Position [315, 171, 365, 209] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point at z" "ero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "50,38,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 38 38 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 50 50 0 0 ],[0 0 38 38 0 ]);\npatch([13.875 21.1 26.1 31.1 36.1 26.1 18.875 13.875 ],[24.55 24.55 2" "9.55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([18.875 26.1 21.1 13.875 18.875 ],[19.55 19.55 24.55 24.55 " "19.55 ],[0.931 0.946 0.973 ]);\npatch([13.875 21.1 26.1 18.875 13.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1 1 ])" ";\npatch([18.875 36.1 31.1 26.1 21.1 13.875 18.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0.973 ]" ");\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label(" "'input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fontsize{20}\\}','texmode'," "'on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "4223" Position [165, 170, 280, 190] ZOrder -9 ShowName off GotoTag "RFA_AGC_G_RF" TagVisibility "global" } Block { BlockType From Name "From1" SID "4224" Position [165, 190, 280, 210] ZOrder -9 ShowName off GotoTag "RFA_AGC_G_BB" TagVisibility "global" } Block { BlockType Reference Name "Register2" SID "4225" Ports [3, 1] Position [450, 181, 495, 229] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 30.66 3" "6.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 30.66 24" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('" "input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'en');\ncolor('bl" "ack');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon te" "xt');" } Block { BlockType Outport Name "G_vec" SID "4226" Position [570, 198, 600, 212] IconDisplay "Port number" } Line { SrcBlock "From" SrcPort 1 DstBlock "Concat" DstPort 1 } Line { SrcBlock "From1" SrcPort 1 DstBlock "Concat" DstPort 2 } Line { SrcBlock "Concat" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "Rst" SrcPort 1 Points [215, 0; 0, -40] DstBlock "Register2" DstPort 2 } Line { SrcBlock "Capt" SrcPort 1 Points [220, 0; 0, -45] DstBlock "Register2" DstPort 3 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "G_vec" DstPort 1 } } } Block { BlockType SubSystem Name "RF B Gains" SID "4227" Ports [2, 1] Position [615, 771, 695, 809] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "RF B Gains" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Capt" SID "4228" Position [165, 258, 195, 272] IconDisplay "Port number" } Block { BlockType Inport Name "Rst" SID "4229" Position [165, 238, 195, 252] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Concat" SID "4230" Ports [2, 1] Position [315, 171, 365, 209] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point at z" "ero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "50,38,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 38 38 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 50 50 0 0 ],[0 0 38 38 0 ]);\npatch([13.875 21.1 26.1 31.1 36.1 26.1 18.875 13.875 ],[24.55 24.55 2" "9.55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([18.875 26.1 21.1 13.875 18.875 ],[19.55 19.55 24.55 24.55 " "19.55 ],[0.931 0.946 0.973 ]);\npatch([13.875 21.1 26.1 18.875 13.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1 1 ])" ";\npatch([18.875 36.1 31.1 26.1 21.1 13.875 18.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0.973 ]" ");\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label(" "'input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fontsize{20}\\}','texmode'," "'on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "4231" Position [165, 170, 280, 190] ZOrder -9 ShowName off GotoTag "RFB_AGC_G_RF" TagVisibility "global" } Block { BlockType From Name "From1" SID "4232" Position [165, 190, 280, 210] ZOrder -9 ShowName off GotoTag "RFB_AGC_G_BB" TagVisibility "global" } Block { BlockType Reference Name "Register2" SID "4233" Ports [3, 1] Position [450, 181, 495, 229] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 30.66 3" "6.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 30.66 24" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('" "input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'en');\ncolor('bl" "ack');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon te" "xt');" } Block { BlockType Outport Name "G_vec" SID "4234" Position [570, 198, 600, 212] IconDisplay "Port number" } Line { SrcBlock "Register2" SrcPort 1 DstBlock "G_vec" DstPort 1 } Line { SrcBlock "Capt" SrcPort 1 Points [220, 0; 0, -45] DstBlock "Register2" DstPort 3 } Line { SrcBlock "Rst" SrcPort 1 Points [215, 0; 0, -40] DstBlock "Register2" DstPort 2 } Line { SrcBlock "Concat" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "From1" SrcPort 1 DstBlock "Concat" DstPort 2 } Line { SrcBlock "From" SrcPort 1 DstBlock "Concat" DstPort 1 } } } Block { BlockType SubSystem Name "RF C Gains" SID "4235" Ports [2, 1] Position [615, 846, 695, 884] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "RF C Gains" Location [237, 698, 722, 914] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Capt" SID "4236" Position [165, 258, 195, 272] IconDisplay "Port number" } Block { BlockType Inport Name "Rst" SID "4237" Position [165, 238, 195, 252] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Concat" SID "4238" Ports [2, 1] Position [315, 171, 365, 209] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point at z" "ero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "50,38,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 38 38 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 50 50 0 0 ],[0 0 38 38 0 ]);\npatch([13.875 21.1 26.1 31.1 36.1 26.1 18.875 13.875 ],[24.55 24.55 2" "9.55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([18.875 26.1 21.1 13.875 18.875 ],[19.55 19.55 24.55 24.55 " "19.55 ],[0.931 0.946 0.973 ]);\npatch([13.875 21.1 26.1 18.875 13.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1 1 ])" ";\npatch([18.875 36.1 31.1 26.1 21.1 13.875 18.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0.973 ]" ");\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label(" "'input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fontsize{20}\\}','texmode'," "'on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "4239" Position [165, 170, 280, 190] ZOrder -9 ShowName off GotoTag "RFC_AGC_G_RF" TagVisibility "global" } Block { BlockType From Name "From1" SID "4240" Position [165, 190, 280, 210] ZOrder -9 ShowName off GotoTag "RFC_AGC_G_BB" TagVisibility "global" } Block { BlockType Reference Name "Register2" SID "4241" Ports [3, 1] Position [450, 181, 495, 229] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 30.66 3" "6.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 30.66 24" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('" "input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'en');\ncolor('bl" "ack');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon te" "xt');" } Block { BlockType Outport Name "G_vec" SID "4242" Position [570, 198, 600, 212] IconDisplay "Port number" } Line { SrcBlock "Register2" SrcPort 1 DstBlock "G_vec" DstPort 1 } Line { SrcBlock "Capt" SrcPort 1 Points [220, 0; 0, -45] DstBlock "Register2" DstPort 3 } Line { SrcBlock "Rst" SrcPort 1 Points [215, 0; 0, -40] DstBlock "Register2" DstPort 2 } Line { SrcBlock "Concat" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "From1" SrcPort 1 DstBlock "Concat" DstPort 2 } Line { SrcBlock "From" SrcPort 1 DstBlock "Concat" DstPort 1 } } } Block { BlockType SubSystem Name "RF D Gains" SID "4243" Ports [2, 1] Position [615, 916, 695, 954] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "RF D Gains" Location [138, 279, 2317, 1561] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Capt" SID "4244" Position [165, 258, 195, 272] IconDisplay "Port number" } Block { BlockType Inport Name "Rst" SID "4245" Position [165, 238, 195, 252] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Concat" SID "4246" Ports [2, 1] Position [315, 171, 365, 209] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point at z" "ero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "50,38,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 38 38 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 50 50 0 0 ],[0 0 38 38 0 ]);\npatch([13.875 21.1 26.1 31.1 36.1 26.1 18.875 13.875 ],[24.55 24.55 2" "9.55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([18.875 26.1 21.1 13.875 18.875 ],[19.55 19.55 24.55 24.55 " "19.55 ],[0.931 0.946 0.973 ]);\npatch([13.875 21.1 26.1 18.875 13.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1 1 ])" ";\npatch([18.875 36.1 31.1 26.1 21.1 13.875 18.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0.973 ]" ");\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label(" "'input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fontsize{20}\\}','texmode'," "'on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "4247" Position [165, 170, 280, 190] ZOrder -9 ShowName off GotoTag "RFD_AGC_G_RF" TagVisibility "global" } Block { BlockType From Name "From1" SID "4248" Position [165, 190, 280, 210] ZOrder -9 ShowName off GotoTag "RFD_AGC_G_BB" TagVisibility "global" } Block { BlockType Reference Name "Register2" SID "4249" Ports [3, 1] Position [450, 181, 495, 229] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 30.66 3" "6.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 30.66 24" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('" "input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'en');\ncolor('bl" "ack');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon te" "xt');" } Block { BlockType Outport Name "G_vec" SID "4250" Position [570, 198, 600, 212] IconDisplay "Port number" } Line { SrcBlock "From" SrcPort 1 DstBlock "Concat" DstPort 1 } Line { SrcBlock "From1" SrcPort 1 DstBlock "Concat" DstPort 2 } Line { SrcBlock "Concat" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "Rst" SrcPort 1 Points [215, 0; 0, -40] DstBlock "Register2" DstPort 2 } Line { SrcBlock "Capt" SrcPort 1 Points [220, 0; 0, -45] DstBlock "Register2" DstPort 3 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "G_vec" DstPort 1 } } } Block { BlockType Reference Name "Register3" SID "4296" Ports [2, 1] Position [940, 978, 985, 1027] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,49,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 49 49 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 49 49 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30." "66 30.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 3" "0.66 30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 " "],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0" ".931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor" "('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('ou" "tput',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Scope Name "Sel Div" SID "4297" Ports [10] Position [980, 477, 1015, 648] ZOrder -3 Floating off Location [106, 316, 2442, 1368] Open off NumInputPorts "10" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" axes9 "%" axes10 "%" } TimeRange "16708 " YMin "0~-1~-1~0~-1~-1~-1~-1~-1~-1" YMax "1~1~1~1~1~1~1~1~1~1" SaveName "ScopeData42" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType Outport Name "Rx I" SID "4298" Position [1460, 662, 1490, 678] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Outport Name " Rx Q" SID "4299" Position [1460, 777, 1490, 793] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Outport Name " IQ Valid" SID "4300" Position [1460, 547, 1490, 563] NamePlacement "alternate" Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "RSSI" SID "4301" Position [1460, 897, 1490, 913] NamePlacement "alternate" Port "4" IconDisplay "Port number" } Line { SrcBlock "RF A Gains" SrcPort 1 Points [10, 0] Branch { Points [0, -185] DstBlock "Gateway Out2" DstPort 1 } Branch { DstBlock "Ant Sel Logic" DstPort 1 } } Line { SrcBlock "RF B Gains" SrcPort 1 Points [20, 0; 0, -65] Branch { Points [0, -185] DstBlock "Gateway Out4" DstPort 1 } Branch { DstBlock "Ant Sel Logic" DstPort 2 } } Line { SrcBlock "Rx Q Vec" SrcPort 1 DstBlock "Bus\nSelector1" DstPort 1 } Line { SrcBlock "Reset" SrcPort 1 Points [40, 0] Branch { DstBlock "RF B Gains" DstPort 2 } Branch { Points [0, -80] DstBlock "RF A Gains" DstPort 2 } Branch { Points [0, 75] Branch { DstBlock "RF C Gains" DstPort 2 } Branch { Points [0, 70] DstBlock "RF D Gains" DstPort 2 } } } Line { SrcBlock "Logical" SrcPort 1 DstBlock "Posedge" DstPort 1 } Line { SrcBlock "Pkt Det" SrcPort 1 Points [25, 0] Branch { DstBlock "Logical" DstPort 1 } Branch { Points [0, -190] DstBlock "Gateway Out" DstPort 1 } } Line { SrcBlock "From5" SrcPort 1 Points [10, 0] Branch { DstBlock "Logical" DstPort 2 } Branch { Points [0, -205] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "Posedge" SrcPort 1 Points [55, 0] Branch { DstBlock "RF A Gains" DstPort 1 } Branch { Points [0, 80] Branch { DstBlock "RF B Gains" DstPort 1 } Branch { Points [0, 75] Branch { DstBlock "RF C Gains" DstPort 1 } Branch { Points [0, 70] Branch { Points [0, 90] DstBlock "Delay" DstPort 1 } Branch { DstBlock "RF D Gains" DstPort 1 } } } } } Line { SrcBlock "Delay" SrcPort 1 DstBlock "Register3" DstPort 2 } Line { SrcBlock "Register3" SrcPort 1 DstBlock "Goto1" DstPort 1 } Line { SrcBlock "IQ Valid" SrcPort 1 DstBlock "Bus\nSelector4" DstPort 1 } Line { Name "" Labels [0, 0] SrcBlock "Bus\nSelector4" SrcPort 1 DstBlock "Mux3" DstPort 2 } Line { Name "" Labels [0, 0] SrcBlock "Bus\nSelector4" SrcPort 2 DstBlock "Mux3" DstPort 3 } Line { SrcBlock "Mux3" SrcPort 1 DstBlock " IQ Valid" DstPort 1 } Line { Name "G A" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 DstBlock "Sel Div" DstPort 3 } Line { Name "AGC Done" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 DstBlock "Sel Div" DstPort 2 } Line { Name "Pkt Det" Labels [0, 0] SrcBlock "Gateway Out" SrcPort 1 DstBlock "Sel Div" DstPort 1 } Line { Name "G B" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 DstBlock "Sel Div" DstPort 4 } Line { SrcBlock "RF C Gains" SrcPort 1 Points [30, 0; 0, -125] Branch { DstBlock "Ant Sel Logic" DstPort 3 } Branch { Points [0, -185] DstBlock "Gateway Out5" DstPort 1 } } Line { SrcBlock "RF D Gains" SrcPort 1 Points [40, 0; 0, -180] Branch { DstBlock "Ant Sel Logic" DstPort 4 } Branch { Points [0, -185] DstBlock "Gateway Out6" DstPort 1 } } Line { Name "G C" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 DstBlock "Sel Div" DstPort 5 } Line { Name "G D" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 DstBlock "Sel Div" DstPort 6 } Line { Name "" Labels [0, 0] SrcBlock "Bus\nSelector4" SrcPort 3 DstBlock "Mux3" DstPort 4 } Line { Name "" Labels [0, 0] SrcBlock "Bus\nSelector4" SrcPort 4 DstBlock "Mux3" DstPort 5 } Line { SrcBlock "Rx I Vec" SrcPort 1 DstBlock "Bus\nSelector3" DstPort 1 } Line { Name "" Labels [0, 0] SrcBlock "Bus\nSelector3" SrcPort 1 DstBlock "Mux1" DstPort 2 } Line { Name "" Labels [0, 0] SrcBlock "Bus\nSelector3" SrcPort 2 DstBlock "Mux1" DstPort 3 } Line { Name "" Labels [0, 0] SrcBlock "Bus\nSelector3" SrcPort 3 DstBlock "Mux1" DstPort 4 } Line { Name "" Labels [0, 0] SrcBlock "Bus\nSelector3" SrcPort 4 DstBlock "Mux1" DstPort 5 } Line { Name "" Labels [0, 0] SrcBlock "Bus\nSelector1" SrcPort 1 DstBlock "Mux2" DstPort 2 } Line { Name "" Labels [0, 0] SrcBlock "Bus\nSelector1" SrcPort 2 DstBlock "Mux2" DstPort 3 } Line { Name "" Labels [0, 0] SrcBlock "Bus\nSelector1" SrcPort 3 DstBlock "Mux2" DstPort 4 } Line { Name "" Labels [0, 0] SrcBlock "Bus\nSelector1" SrcPort 4 DstBlock "Mux2" DstPort 5 } Line { SrcBlock "RSSI Vec" SrcPort 1 DstBlock "Bus\nSelector2" DstPort 1 } Line { Name "" Labels [0, 0] SrcBlock "Bus\nSelector2" SrcPort 1 DstBlock "Mux4" DstPort 2 } Line { Name "" Labels [0, 0] SrcBlock "Bus\nSelector2" SrcPort 2 DstBlock "Mux4" DstPort 3 } Line { Name "" Labels [0, 0] SrcBlock "Bus\nSelector2" SrcPort 3 DstBlock "Mux4" DstPort 4 } Line { Name "" Labels [0, 0] SrcBlock "Bus\nSelector2" SrcPort 4 DstBlock "Mux4" DstPort 5 } Line { SrcBlock "Mux4" SrcPort 1 DstBlock "RSSI" DstPort 1 } Line { SrcBlock "Ant Sel Logic" SrcPort 1 Points [15, 0] Branch { Points [475, 0] Branch { Points [0, -105] Branch { Points [0, -115] DstBlock "Mux3" DstPort 1 } Branch { DstBlock "Mux1" DstPort 1 } } Branch { Points [0, 10] Branch { DstBlock "Mux2" DstPort 1 } Branch { Points [0, 120] DstBlock "Mux4" DstPort 1 } } } Branch { Points [0, 255] DstBlock "Register3" DstPort 1 } } Line { SrcBlock "Mux2" SrcPort 1 DstBlock " Rx Q" DstPort 1 } Line { SrcBlock "Mux1" SrcPort 1 DstBlock "Rx I" DstPort 1 } } } Block { BlockType SubSystem Name "Debug \nOutputs" SID "4302" Ports [4] Position [1050, 811, 1135, 874] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Debug \nOutputs" Location [280, 193, 2120, 1196] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "LTS" SID "4303" Position [265, 448, 295, 462] IconDisplay "Port number" } Block { BlockType Inport Name "LTS Timeout" SID "4304" Position [340, 663, 370, 677] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "Det OFDM" SID "4305" Position [235, 938, 265, 952] NamePlacement "alternate" Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "Det DSSS" SID "4306" Position [235, 993, 265, 1007] Port "4" IconDisplay "Port number" } Block { BlockType Goto Name "Goto" SID "4307" Position [595, 872, 710, 888] ZOrder -10 ShowName off GotoTag "CS_Pktdet_OFDM" TagVisibility "global" } Block { BlockType Goto Name "Goto1" SID "4308" Position [605, 621, 700, 639] ZOrder -10 ShowName off GotoTag "CS_LTS_Timeout" TagVisibility "global" } Block { BlockType Goto Name "Goto2" SID "4309" Position [595, 900, 710, 920] ZOrder -10 ShowName off GotoTag "CS_Pktdet_DSSS" TagVisibility "global" } Block { BlockType Reference Name "LTS_SYNC" SID "4310" Ports [1, 1] Position [775, 448, 815, 462] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "40,14,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9" ".22 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22" " 9.22 7.22 ],[0.985 0.979 0.895 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.985 0.979 0.89" "5 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprin" "tf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Pulse Stretch" SID "4311" Ports [1, 1] Position [505, 437, 560, 473] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Pulse Stretch" Location [461, 514, 706, 672] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "P" SID "4312" Position [350, 258, 380, 272] IconDisplay "Port number" } Block { BlockType Reference Name "Delay" SID "4313" Ports [1, 1] Position [410, 329, 445, 361] BlockMirror on NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "16" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,32,1,1,white,blue,0,f89f7887,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 32 32 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 32 32 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[20.44 20.44 24.4" "4 20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[16.44 16.44 20.44 20.44 16.44 ]," "[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1 1 1 ]);\npatch([12.1" " 25.88 21.88 17.88 13.88 8.1 12.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-16}','texmode'" ",'on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "S-R Latch" SID "4314" Ports [2, 1] Position [405, 253, 450, 302] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "S-R Latch" Location [13, 209, 2156, 1324] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "4315" Position [140, 103, 170, 117] IconDisplay "Port number" } Block { BlockType Inport Name "R" SID "4316" Position [140, 88, 170, 102] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "4317" Ports [0, 1] Position [195, 71, 210, 89] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "15,18,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11.22 " "13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 9.22 " "],[0.931 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([4.55 " "11.44 9.44 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "4318" Ports [1, 1] Position [210, 86, 235, 104] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('outpu" "t',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "4319" Ports [1, 1] Position [210, 101, 235, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('outpu" "t',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "4320" Ports [3, 1] Position [255, 71, 300, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "4321" Position [325, 88, 355, 102] IconDisplay "Port number" } Line { SrcBlock "Convert2" SrcPort 1 DstBlock "Register2" DstPort 3 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "S" SrcPort 1 DstBlock "Convert2" DstPort 1 } } } Block { BlockType Outport Name "P16" SID "4322" Position [515, 273, 545, 287] IconDisplay "Port number" } Line { SrcBlock "S-R Latch" SrcPort 1 Points [40, 0] Branch { Points [0, 65] DstBlock "Delay" DstPort 1 } Branch { DstBlock "P16" DstPort 1 } } Line { SrcBlock "Delay" SrcPort 1 Points [-25, 0; 0, -55] DstBlock "S-R Latch" DstPort 2 } Line { SrcBlock "P" SrcPort 1 DstBlock "S-R Latch" DstPort 1 } } } Block { BlockType SubSystem Name "Pulse Stretch1" SID "4323" Ports [1, 1] Position [420, 652, 475, 688] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Pulse Stretch1" Location [61, 101, 2263, 1443] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "P" SID "4324" Position [350, 258, 380, 272] IconDisplay "Port number" } Block { BlockType Reference Name "Delay" SID "4325" Ports [1, 1] Position [410, 329, 445, 361] BlockMirror on NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "16" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,32,1,1,white,blue,0,f89f7887,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 32 32 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 32 32 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[20.44 20.44 24.4" "4 20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[16.44 16.44 20.44 20.44 16.44 ]," "[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1 1 1 ]);\npatch([12.1" " 25.88 21.88 17.88 13.88 8.1 12.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-16}','texmode'" ",'on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "S-R Latch" SID "4326" Ports [2, 1] Position [405, 253, 450, 302] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "S-R Latch" Location [13, 209, 2156, 1324] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "4327" Position [140, 103, 170, 117] IconDisplay "Port number" } Block { BlockType Inport Name "R" SID "4328" Position [140, 88, 170, 102] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "4329" Ports [0, 1] Position [195, 71, 210, 89] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "15,18,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11.22 " "13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 9.22 " "],[0.931 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([4.55 " "11.44 9.44 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "4330" Ports [1, 1] Position [210, 86, 235, 104] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('outpu" "t',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "4331" Ports [1, 1] Position [210, 101, 235, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('outpu" "t',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "4332" Ports [3, 1] Position [255, 71, 300, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "4333" Position [325, 88, 355, 102] IconDisplay "Port number" } Line { SrcBlock "Convert2" SrcPort 1 DstBlock "Register2" DstPort 3 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "S" SrcPort 1 DstBlock "Convert2" DstPort 1 } } } Block { BlockType Outport Name "P16" SID "4334" Position [515, 273, 545, 287] IconDisplay "Port number" } Line { SrcBlock "S-R Latch" SrcPort 1 Points [40, 0] Branch { Points [0, 65] DstBlock "Delay" DstPort 1 } Branch { DstBlock "P16" DstPort 1 } } Line { SrcBlock "Delay" SrcPort 1 Points [-25, 0; 0, -55] DstBlock "S-R Latch" DstPort 2 } Line { SrcBlock "P" SrcPort 1 DstBlock "S-R Latch" DstPort 1 } } } Block { BlockType Reference Name "Register10" SID "4335" Ports [1, 1] Position [340, 983, 375, 1017] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,34,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 34 34 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 34 34 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[21.44 " "21.44 25.44 21.44 25.44 25.44 25.44 21.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[17.44 17.44 21.44 2" "1.44 17.44 ],[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[13.44 13.44 17.44 17.44 13.44 ],[1 1 1 " "]);\npatch([12.1 25.88 21.88 17.88 13.88 8.1 12.1 ],[9.44 9.44 13.44 9.44 13.44 13.44 9.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register11" SID "4336" Ports [1, 1] Position [475, 983, 510, 1017] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,34,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 34 34 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 34 34 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[21.44 " "21.44 25.44 21.44 25.44 25.44 25.44 21.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[17.44 17.44 21.44 2" "1.44 17.44 ],[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[13.44 13.44 17.44 17.44 13.44 ],[1 1 1 " "]);\npatch([12.1 25.88 21.88 17.88 13.88 8.1 12.1 ],[9.44 9.44 13.44 9.44 13.44 13.44 9.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "4337" Ports [1, 1] Position [565, 657, 600, 683] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 26 26 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ]" ",[16.33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[13.3" "3 13.33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[10.33 10.33 13.3" "3 13.33 10.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[7.33 7.33 10.33 7.33 10.33 1" "0.33 7.33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon " "text');\ncolor('black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');" "disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register3" SID "4338" Ports [1, 1] Position [635, 657, 670, 683] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 26 26 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ]" ",[16.33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[13.3" "3 13.33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[10.33 10.33 13.3" "3 13.33 10.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[7.33 7.33 10.33 7.33 10.33 1" "0.33 7.33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon " "text');\ncolor('black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');" "disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register4" SID "4339" Ports [1, 1] Position [405, 928, 440, 962] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,34,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 34 34 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 34 34 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[21.44 " "21.44 25.44 21.44 25.44 25.44 25.44 21.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[17.44 17.44 21.44 2" "1.44 17.44 ],[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[13.44 13.44 17.44 17.44 13.44 ],[1 1 1 " "]);\npatch([12.1 25.88 21.88 17.88 13.88 8.1 12.1 ],[9.44 9.44 13.44 9.44 13.44 13.44 9.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register5" SID "4340" Ports [1, 1] Position [405, 983, 440, 1017] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,34,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 34 34 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 34 34 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[21.44 " "21.44 25.44 21.44 25.44 25.44 25.44 21.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[17.44 17.44 21.44 2" "1.44 17.44 ],[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[13.44 13.44 17.44 17.44 13.44 ],[1 1 1 " "]);\npatch([12.1 25.88 21.88 17.88 13.88 8.1 12.1 ],[9.44 9.44 13.44 9.44 13.44 13.44 9.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register6" SID "4341" Ports [1, 1] Position [340, 928, 375, 962] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,34,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 34 34 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 34 34 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[21.44 " "21.44 25.44 21.44 25.44 25.44 25.44 21.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[17.44 17.44 21.44 2" "1.44 17.44 ],[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[13.44 13.44 17.44 17.44 13.44 ],[1 1 1 " "]);\npatch([12.1 25.88 21.88 17.88 13.88 8.1 12.1 ],[9.44 9.44 13.44 9.44 13.44 13.44 9.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register7" SID "4342" Ports [1, 1] Position [475, 928, 510, 962] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,34,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 34 34 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 34 34 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[21.44 " "21.44 25.44 21.44 25.44 25.44 25.44 21.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[17.44 17.44 21.44 2" "1.44 17.44 ],[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[13.44 13.44 17.44 17.44 13.44 ],[1 1 1 " "]);\npatch([12.1 25.88 21.88 17.88 13.88 8.1 12.1 ],[9.44 9.44 13.44 9.44 13.44 13.44 9.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register8" SID "4343" Ports [1, 1] Position [615, 442, 650, 468] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 26 26 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ]" ",[16.33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[13.3" "3 13.33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[10.33 10.33 13.3" "3 13.33 10.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[7.33 7.33 10.33 7.33 10.33 1" "0.33 7.33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon " "text');\ncolor('black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');" "disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register9" SID "4344" Ports [1, 1] Position [685, 442, 720, 468] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 26 26 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ]" ",[16.33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[13.3" "3 13.33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[10.33 10.33 13.3" "3 13.33 10.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[7.33 7.33 10.33 7.33 10.33 1" "0.33 7.33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon " "text');\ncolor('black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');" "disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Slice2" SID "4345" Ports [1, 1] Position [335, 448, 370, 462] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Upper Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "35,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 14 14 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 14 14 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[9" ".22 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[7.22 7.22 9.22" " 9.22 7.22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 " "]);\npatch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');por" "t_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "dbg_PKT_DET_DSSS" SID "4346" Ports [1, 1] Position [575, 990, 635, 1010] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[1" "2.22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.2" "2 12.22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.2" "2 ],[1 1 1 ]);\npatch([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985" " 0.979 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','o" "n');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "dbg_PKT_DET_OFDM" SID "4347" Ports [1, 1] Position [575, 935, 635, 955] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[1" "2.22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.2" "2 12.22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.2" "2 ],[1 1 1 ]);\npatch([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985" " 0.979 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','o" "n');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "dbg_lts_timeout" SID "4348" Ports [1, 1] Position [725, 663, 765, 677] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "40,14,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9" ".22 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22" " 9.22 7.22 ],[0.985 0.979 0.895 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.985 0.979 0.89" "5 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprin" "tf('','COMMENT: end icon text');" } Line { SrcBlock "Register8" SrcPort 1 DstBlock "Register9" DstPort 1 } Line { SrcBlock "Register9" SrcPort 1 DstBlock "LTS_SYNC" DstPort 1 } Line { SrcBlock "Slice2" SrcPort 1 DstBlock "Pulse Stretch" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Register3" DstPort 1 } Line { SrcBlock "Register3" SrcPort 1 DstBlock "dbg_lts_timeout" DstPort 1 } Line { SrcBlock "LTS" SrcPort 1 DstBlock "Slice2" DstPort 1 } Line { SrcBlock "Register6" SrcPort 1 Points [0, 0] Branch { DstBlock "Register4" DstPort 1 } Branch { Points [0, -65] DstBlock "Goto" DstPort 1 } } Line { SrcBlock "Register7" SrcPort 1 DstBlock "dbg_PKT_DET_OFDM" DstPort 1 } Line { SrcBlock "Register4" SrcPort 1 DstBlock "Register7" DstPort 1 } Line { SrcBlock "Register10" SrcPort 1 Points [5, 0] Branch { DstBlock "Register5" DstPort 1 } Branch { Points [0, -90] DstBlock "Goto2" DstPort 1 } } Line { SrcBlock "Register11" SrcPort 1 DstBlock "dbg_PKT_DET_DSSS" DstPort 1 } Line { SrcBlock "Register5" SrcPort 1 DstBlock "Register11" DstPort 1 } Line { SrcBlock "Det OFDM" SrcPort 1 DstBlock "Register6" DstPort 1 } Line { SrcBlock "Det DSSS" SrcPort 1 DstBlock "Register10" DstPort 1 } Line { SrcBlock "Pulse Stretch" SrcPort 1 DstBlock "Register8" DstPort 1 } Line { SrcBlock "LTS Timeout" SrcPort 1 DstBlock "Pulse Stretch1" DstPort 1 } Line { SrcBlock "Pulse Stretch1" SrcPort 1 Points [45, 0] Branch { DstBlock "Register2" DstPort 1 } Branch { Points [0, -40] DstBlock "Goto1" DstPort 1 } } Annotation { Name "Pulse stretch the timeout signal\nso it's visible on debug outputs\nand in down-sampled CS ILA" Position [459, 740] } } } Block { BlockType Reference Name "Delay" SID "18079" Ports [1, 1] Position [1005, 568, 1030, 592] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "25,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 24 24 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 24 24 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[15.33 15.33 18" ".33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[12.33 12.33 15.33 15.33 12.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 1 1 ]);\npatch([" "8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 0.973 ]);\nfprintf(''" ",'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-1}','texmode" "','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From11" SID "4349" Position [15, 235, 155, 255] ShowName off CloseFcn "tagdialog Close" GotoTag "DSSS_RX_RESET" TagVisibility "global" } Block { BlockType Reference Name "Gateway Out" SID "4350" Ports [1, 1] Position [1075, 25, 1100, 35] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "25,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 10 10 0 ],[0.88 0.88 0.88" " ]);\nplot([0 25 25 0 0 ],[0 0 10 10 0 ]);\npatch([9.775 11.22 12.22 13.22 14.22 12.22 10.775 9.775 ],[6.11 6.11 7." "11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([10.775 12.22 11.22 9.775 10.775 ],[5.11 5.11 6.11 6.11 5.11 ],[0.9" "64 0.964 0.964 ]);\npatch([9.775 11.22 12.22 10.775 9.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]);\npatch([10.775 1" "4.22 13.22 12.22 11.22 9.775 10.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.964 ]);\nfprintf('','COM" "MENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ');\ncol" "or('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Pkt Det OFDM" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out1" SID "4351" Ports [1, 1] Position [1075, 40, 1100, 50] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "25,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 10 10 0 ],[0.88 0.88 0.88" " ]);\nplot([0 25 25 0 0 ],[0 0 10 10 0 ]);\npatch([9.775 11.22 12.22 13.22 14.22 12.22 10.775 9.775 ],[6.11 6.11 7." "11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([10.775 12.22 11.22 9.775 10.775 ],[5.11 5.11 6.11 6.11 5.11 ],[0.9" "64 0.964 0.964 ]);\npatch([9.775 11.22 12.22 10.775 9.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]);\npatch([10.775 1" "4.22 13.22 12.22 11.22 9.775 10.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.964 ]);\nfprintf('','COM" "MENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ');\ncol" "or('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Pkt Done" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "4352" Ports [1, 1] Position [1075, 55, 1100, 65] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "25,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 10 10 0 ],[0.88 0.88 0.88" " ]);\nplot([0 25 25 0 0 ],[0 0 10 10 0 ]);\npatch([9.775 11.22 12.22 13.22 14.22 12.22 10.775 9.775 ],[6.11 6.11 7." "11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([10.775 12.22 11.22 9.775 10.775 ],[5.11 5.11 6.11 6.11 5.11 ],[0.9" "64 0.964 0.964 ]);\npatch([9.775 11.22 12.22 10.775 9.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]);\npatch([10.775 1" "4.22 13.22 12.22 11.22 9.775 10.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.964 ]);\nfprintf('','COM" "MENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ');\ncol" "or('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon text');" Port { PortNumber 1 Name "LTS TO" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "4353" Ports [1, 1] Position [1075, 145, 1100, 155] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "25,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 10 10 0 ],[0.88 0.88 0.88" " ]);\nplot([0 25 25 0 0 ],[0 0 10 10 0 ]);\npatch([9.775 11.22 12.22 13.22 14.22 12.22 10.775 9.775 ],[6.11 6.11 7." "11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([10.775 12.22 11.22 9.775 10.775 ],[5.11 5.11 6.11 6.11 5.11 ],[0.9" "64 0.964 0.964 ]);\npatch([9.775 11.22 12.22 10.775 9.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]);\npatch([10.775 1" "4.22 13.22 12.22 11.22 9.775 10.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.964 ]);\nfprintf('','COM" "MENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ');\ncol" "or('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out4" SID "4354" Ports [1, 1] Position [1075, 70, 1100, 80] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "25,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 10 10 0 ],[0.88 0.88 0.88" " ]);\nplot([0 25 25 0 0 ],[0 0 10 10 0 ]);\npatch([9.775 11.22 12.22 13.22 14.22 12.22 10.775 9.775 ],[6.11 6.11 7." "11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([10.775 12.22 11.22 9.775 10.775 ],[5.11 5.11 6.11 6.11 5.11 ],[0.9" "64 0.964 0.964 ]);\npatch([9.775 11.22 12.22 10.775 9.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]);\npatch([10.775 1" "4.22 13.22 12.22 11.22 9.775 10.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.964 ]);\nfprintf('','COM" "MENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ');\ncol" "or('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Pkt Det DSSS" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType SubSystem Name "LTS Correlation" SID "11786" Ports [5, 2] Position [845, 556, 935, 644] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "LTS Correlation" Location [-1478, 227, -2, 1187] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "rx_I" SID "11787" Position [170, 288, 200, 302] IconDisplay "Port number" } Block { BlockType Inport Name "rx_Q" SID "11788" Position [170, 323, 200, 337] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "rx_IQ_valid" SID "11789" Position [170, 358, 200, 372] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "RSSI" SID "11790" Position [170, 508, 200, 522] Port "4" IconDisplay "Port number" } Block { BlockType Inport Name "OFDM Pkt Det" SID "11791" Position [170, 238, 200, 252] Port "5" IconDisplay "Port number" } Block { BlockType SubSystem Name "Corr Event Logic" SID "11792" Ports [5, 1] Position [770, 305, 885, 385] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Corr Event Logic" Location [202, 70, 2473, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "125" Block { BlockType Inport Name "En" SID "11793" Position [170, 133, 200, 147] IconDisplay "Port number" } Block { BlockType Inport Name "Corr" SID "11794" Position [170, 168, 200, 182] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "IQ Valid" SID "11795" Position [170, 397, 200, 413] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "Corr Thresh" SID "11796" Position [170, 262, 200, 278] Port "4" IconDisplay "Port number" } Block { BlockType Inport Name "Peak Type Thresh" SID "11797" Position [170, 357, 200, 373] Port "5" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub" SID "11798" Ports [2, 1] Position [290, 238, 345, 282] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Subtraction" use_carryin off use_carryout off en off latency "1" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL off hw_selection "Fabric" pipelined off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" sg_icon_stat "55,44,2,1,white,blue,0,8a00a986,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 44 44 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 55 55 0 0 ],[0 0 44 44 0 ]);\npatch([13.65 22.32 28.32 34.32 40.32 28.32 19.65 13.65 ],[28.66 28.66" " 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([19.65 28.32 22.32 13.65 19.65 ],[22.66 22.66 28.66 28.66" " 22.66 ],[0.931 0.946 0.973 ]);\npatch([13.65 22.32 28.32 19.65 13.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1 1 ])" ";\npatch([19.65 40.32 34.32 28.32 22.32 13.65 19.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0.946 0." "973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bf{a - b}" "','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\newline\\bf{}" "','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Dual Peak Det" SID "11799" Ports [2, 1] Position [780, 245, 820, 305] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Dual Peak Det" Location [649, 125, 1510, 500] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "123" Block { BlockType Inport Name "Peak" SID "11800" Position [320, 258, 350, 272] IconDisplay "Port number" } Block { BlockType Inport Name "IQ Valid" SID "11801" Position [320, 293, 345, 307] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Delay" SID "11802" Ports [2, 1] Position [425, 255, 465, 290] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en on latency "63" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "40,35,2,1,white,blue,0,cab2ee4e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 35 35 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 35 35 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[22.55 22." "55 27.55 22.55 27.55 27.55 27.55 22.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[17.55 17.55 22.55 2" "2.55 17.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[12.55 12.55 17.55 17.55 12.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[7.55 7.55 12.55 7.55 12.55 12.55 7.55 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');p" "ort_label('input',2,'en');\n\ncolor('black');disp('z^{-63}','texmode','on');\nfprintf('','COMMENT: end icon text" "');" } Block { BlockType Reference Name "Delay2" SID "11803" Ports [2, 1] Position [545, 255, 585, 290] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en on latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "40,35,2,1,white,blue,0,7c0ac154,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 35 35 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 35 35 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[22.55 22." "55 27.55 22.55 27.55 27.55 27.55 22.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[17.55 17.55 22.55 2" "2.55 17.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[12.55 12.55 17.55 17.55 12.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[7.55 7.55 12.55 7.55 12.55 12.55 7.55 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');p" "ort_label('input',2,'en');\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text'" ");" } Block { BlockType Reference Name "Delay3" SID "11804" Ports [2, 1] Position [640, 255, 680, 290] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en on latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "40,35,2,1,white,blue,0,7c0ac154,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 35 35 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 35 35 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[22.55 22." "55 27.55 22.55 27.55 27.55 27.55 22.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[17.55 17.55 22.55 2" "2.55 17.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[12.55 12.55 17.55 17.55 12.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[7.55 7.55 12.55 7.55 12.55 12.55 7.55 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');p" "ort_label('input',2,'en');\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text'" ");" } Block { BlockType From Name "From6" SID "11805" Position [40, 25, 295, 45] ShowName off CloseFcn "tagdialog Close" GotoTag "regRx_LongCorr_PeakDelayMasks" TagVisibility "global" } Block { BlockType Reference Name "Logical1" SID "11806" Ports [3, 1] Position [705, 69, 745, 101] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,32,3,1,white,blue,0,98d76266,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 32 32 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 32 32 0 ]);\npatch([11.1 16.88 20.88 24.88 28.88 20.88 15.1 11.1 ],[20.44 20" ".44 24.44 20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([15.1 20.88 16.88 11.1 15.1 ],[16.44 16.44 20.44 20." "44 16.44 ],[0.931 0.946 0.973 ]);\npatch([11.1 16.88 20.88 15.1 11.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1 1 1 ]" ");\npatch([15.1 28.88 24.88 20.88 16.88 11.1 15.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946 0.973 " "]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\ncolor('black');" "disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "11807" Ports [3, 1] Position [800, 28, 830, 142] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "30,114,3,1,white,blue,0,a2abe52d,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 114 114 0 ],[0.77 0." "82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 114 114 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[61.44 " "61.44 65.44 61.44 65.44 65.44 65.44 61.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[57.44 57.44 61.44 61" ".44 57.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[53.44 53.44 57.44 57.44 53.44 ],[1 1 1 ])" ";\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[49.44 49.44 53.44 49.44 53.44 53.44 49.44 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\ncolor('black'" ");disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical3" SID "11808" Ports [3, 1] Position [705, 109, 745, 141] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,32,3,1,white,blue,0,98d76266,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 32 32 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 32 32 0 ]);\npatch([11.1 16.88 20.88 24.88 28.88 20.88 15.1 11.1 ],[20.44 20" ".44 24.44 20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([15.1 20.88 16.88 11.1 15.1 ],[16.44 16.44 20.44 20." "44 16.44 ],[0.931 0.946 0.973 ]);\npatch([11.1 16.88 20.88 15.1 11.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1 1 1 ]" ");\npatch([15.1 28.88 24.88 20.88 16.88 11.1 15.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946 0.973 " "]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\ncolor('black');" "disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical7" SID "11809" Ports [3, 1] Position [705, 29, 745, 61] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,32,3,1,white,blue,0,98d76266,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 32 32 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 32 32 0 ]);\npatch([11.1 16.88 20.88 24.88 28.88 20.88 15.1 11.1 ],[20.44 20" ".44 24.44 20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([15.1 20.88 16.88 11.1 15.1 ],[16.44 16.44 20.44 20." "44 16.44 ],[0.931 0.946 0.973 ]);\npatch([11.1 16.88 20.88 15.1 11.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1 1 1 ]" ");\npatch([15.1 28.88 24.88 20.88 16.88 11.1 15.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946 0.973 " "]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\ncolor('black');" "disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register" SID "11810" Ports [1, 1] Position [340, 22, 370, 48] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[16.3" "3 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 13.33 " "16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13.33 10." "33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor" "('black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','" "texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b0" SID "11811" Ports [1, 1] Position [425, 25, 460, 45] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "35,20,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 20 20 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 20 20 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[12.22" " 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[10.22 10.22 12." "22 12.22 10.22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1" " 1 1 ]);\npatch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');" "port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b1" SID "11812" Ports [1, 1] Position [425, 65, 460, 85] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "1" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "35,20,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 20 20 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 20 20 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[12.22" " 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[10.22 10.22 12." "22 12.22 10.22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1" " 1 1 ]);\npatch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');" "port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b2" SID "11813" Ports [1, 1] Position [425, 105, 460, 125] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "2" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "35,20,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 20 20 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 20 20 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[12.22" " 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[10.22 10.22 12." "22 12.22 10.22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1" " 1 1 ]);\npatch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');" "port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Det" SID "11814" Position [890, 78, 920, 92] IconDisplay "Port number" } Line { SrcBlock "Delay" SrcPort 1 Points [30, 0; 0, -10] Branch { Points [0, -210] DstBlock "Logical7" DstPort 3 } Branch { DstBlock "Delay2" DstPort 1 } } Line { SrcBlock "From6" SrcPort 1 DstBlock "Register" DstPort 1 } Line { SrcBlock "b0" SrcPort 1 DstBlock "Logical7" DstPort 1 } Line { SrcBlock "IQ Valid" SrcPort 1 Points [45, 0] Branch { Points [0, -20] DstBlock "Delay" DstPort 2 } Branch { Points [125, 0] Branch { Points [105, 0] DstBlock "Delay3" DstPort 2 } Branch { Points [0, -20] DstBlock "Delay2" DstPort 2 } } } Line { SrcBlock "Peak" SrcPort 1 Points [40, 0] Branch { DstBlock "Delay" DstPort 1 } Branch { Points [0, -50; 100, 0; 0, -170; 185, 0] Branch { DstBlock "Logical7" DstPort 2 } Branch { Points [0, 40] Branch { DstBlock "Logical1" DstPort 2 } Branch { Points [0, 40] DstBlock "Logical3" DstPort 2 } } } } Line { SrcBlock "Logical2" SrcPort 1 DstBlock "Det" DstPort 1 } Line { SrcBlock "b1" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Delay2" SrcPort 1 Points [20, 0; 0, -10] Branch { Points [0, -170] DstBlock "Logical1" DstPort 3 } Branch { DstBlock "Delay3" DstPort 1 } } Line { SrcBlock "b2" SrcPort 1 DstBlock "Logical3" DstPort 1 } Line { SrcBlock "Delay3" SrcPort 1 Points [0, -140] DstBlock "Logical3" DstPort 3 } Line { SrcBlock "Logical7" SrcPort 1 DstBlock "Logical2" DstPort 1 } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Logical2" DstPort 2 } Line { SrcBlock "Logical3" SrcPort 1 DstBlock "Logical2" DstPort 3 } Line { SrcBlock "Register" SrcPort 1 Points [15, 0] Branch { DstBlock "b0" DstPort 1 } Branch { Points [0, 40] Branch { DstBlock "b1" DstPort 1 } Branch { Points [0, 40] DstBlock "b2" DstPort 1 } } } } } Block { BlockType SubSystem Name "Dual Peak Det1" SID "11815" Ports [2, 1] Position [780, 325, 820, 385] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Dual Peak Det1" Location [202, 70, 1830, 1180] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "155" Block { BlockType Inport Name "Peak" SID "11816" Position [325, 258, 355, 272] IconDisplay "Port number" } Block { BlockType Inport Name "IQ Valid" SID "11817" Position [325, 293, 350, 307] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Delay" SID "11818" Ports [2, 1] Position [430, 255, 470, 290] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en on latency "63" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "40,35,2,1,white,blue,0,cab2ee4e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 35 35 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 35 35 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[22.55 22." "55 27.55 22.55 27.55 27.55 27.55 22.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[17.55 17.55 22.55 2" "2.55 17.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[12.55 12.55 17.55 17.55 12.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[7.55 7.55 12.55 7.55 12.55 12.55 7.55 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');p" "ort_label('input',2,'en');\n\ncolor('black');disp('z^{-63}','texmode','on');\nfprintf('','COMMENT: end icon text" "');" } Block { BlockType Reference Name "Delay2" SID "11819" Ports [2, 1] Position [550, 255, 590, 290] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en on latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "40,35,2,1,white,blue,0,7c0ac154,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 35 35 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 35 35 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[22.55 22." "55 27.55 22.55 27.55 27.55 27.55 22.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[17.55 17.55 22.55 2" "2.55 17.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[12.55 12.55 17.55 17.55 12.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[7.55 7.55 12.55 7.55 12.55 12.55 7.55 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');p" "ort_label('input',2,'en');\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text'" ");" } Block { BlockType Reference Name "Delay3" SID "11820" Ports [2, 1] Position [645, 255, 685, 290] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en on latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "40,35,2,1,white,blue,0,7c0ac154,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 35 35 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 35 35 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[22.55 22." "55 27.55 22.55 27.55 27.55 27.55 22.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[17.55 17.55 22.55 2" "2.55 17.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[12.55 12.55 17.55 17.55 12.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[7.55 7.55 12.55 7.55 12.55 12.55 7.55 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');p" "ort_label('input',2,'en');\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text'" ");" } Block { BlockType From Name "From6" SID "11821" Position [30, 25, 285, 45] ShowName off CloseFcn "tagdialog Close" GotoTag "regRx_LongCorr_PeakDelayMasks" TagVisibility "global" } Block { BlockType Reference Name "Logical1" SID "11822" Ports [3, 1] Position [710, 69, 750, 101] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,32,3,1,white,blue,0,98d76266,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 32 32 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 32 32 0 ]);\npatch([11.1 16.88 20.88 24.88 28.88 20.88 15.1 11.1 ],[20.44 20" ".44 24.44 20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([15.1 20.88 16.88 11.1 15.1 ],[16.44 16.44 20.44 20." "44 16.44 ],[0.931 0.946 0.973 ]);\npatch([11.1 16.88 20.88 15.1 11.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1 1 1 ]" ");\npatch([15.1 28.88 24.88 20.88 16.88 11.1 15.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946 0.973 " "]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\ncolor('black');" "disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "11823" Ports [3, 1] Position [805, 28, 835, 142] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "30,114,3,1,white,blue,0,a2abe52d,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 114 114 0 ],[0.77 0." "82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 114 114 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[61.44 " "61.44 65.44 61.44 65.44 65.44 65.44 61.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[57.44 57.44 61.44 61" ".44 57.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[53.44 53.44 57.44 57.44 53.44 ],[1 1 1 ])" ";\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[49.44 49.44 53.44 49.44 53.44 53.44 49.44 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\ncolor('black'" ");disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical3" SID "11824" Ports [3, 1] Position [710, 104, 750, 136] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,32,3,1,white,blue,0,98d76266,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 32 32 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 32 32 0 ]);\npatch([11.1 16.88 20.88 24.88 28.88 20.88 15.1 11.1 ],[20.44 20" ".44 24.44 20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([15.1 20.88 16.88 11.1 15.1 ],[16.44 16.44 20.44 20." "44 16.44 ],[0.931 0.946 0.973 ]);\npatch([11.1 16.88 20.88 15.1 11.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1 1 1 ]" ");\npatch([15.1 28.88 24.88 20.88 16.88 11.1 15.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946 0.973 " "]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\ncolor('black');" "disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical7" SID "11825" Ports [3, 1] Position [710, 29, 750, 61] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,32,3,1,white,blue,0,98d76266,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 32 32 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 32 32 0 ]);\npatch([11.1 16.88 20.88 24.88 28.88 20.88 15.1 11.1 ],[20.44 20" ".44 24.44 20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([15.1 20.88 16.88 11.1 15.1 ],[16.44 16.44 20.44 20." "44 16.44 ],[0.931 0.946 0.973 ]);\npatch([11.1 16.88 20.88 15.1 11.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1 1 1 ]" ");\npatch([15.1 28.88 24.88 20.88 16.88 11.1 15.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946 0.973 " "]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\ncolor('black');" "disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register" SID "11826" Ports [1, 1] Position [335, 22, 365, 48] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[16.3" "3 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 13.33 " "16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13.33 10." "33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor" "('black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','" "texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b0" SID "11827" Ports [1, 1] Position [430, 25, 465, 45] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "35,20,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 20 20 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 20 20 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[12.22" " 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[10.22 10.22 12." "22 12.22 10.22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1" " 1 1 ]);\npatch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');" "port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b1" SID "11828" Ports [1, 1] Position [430, 65, 465, 85] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "1" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "35,20,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 20 20 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 20 20 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[12.22" " 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[10.22 10.22 12." "22 12.22 10.22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1" " 1 1 ]);\npatch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');" "port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b2" SID "11829" Ports [1, 1] Position [430, 100, 465, 120] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "2" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "35,20,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 20 20 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 20 20 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[12.22" " 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[10.22 10.22 12." "22 12.22 10.22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1" " 1 1 ]);\npatch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');" "port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Det" SID "11830" Position [895, 78, 925, 92] IconDisplay "Port number" } Line { SrcBlock "Logical3" SrcPort 1 Points [35, 0] DstBlock "Logical2" DstPort 3 } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Logical2" DstPort 2 } Line { SrcBlock "Logical7" SrcPort 1 Points [0, 5] DstBlock "Logical2" DstPort 1 } Line { SrcBlock "Delay3" SrcPort 1 Points [0, -145] DstBlock "Logical3" DstPort 3 } Line { SrcBlock "b2" SrcPort 1 DstBlock "Logical3" DstPort 1 } Line { SrcBlock "Delay2" SrcPort 1 Points [20, 0; 0, -10] Branch { DstBlock "Delay3" DstPort 1 } Branch { Points [0, -170] DstBlock "Logical1" DstPort 3 } } Line { SrcBlock "b1" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Logical2" SrcPort 1 DstBlock "Det" DstPort 1 } Line { SrcBlock "Peak" SrcPort 1 Points [40, 0] Branch { Points [0, -50; 100, 0; 0, -170; 185, 0] Branch { Points [0, 40] Branch { Points [0, 35] DstBlock "Logical3" DstPort 2 } Branch { DstBlock "Logical1" DstPort 2 } } Branch { DstBlock "Logical7" DstPort 2 } } Branch { DstBlock "Delay" DstPort 1 } } Line { SrcBlock "IQ Valid" SrcPort 1 Points [45, 0] Branch { Points [125, 0] Branch { Points [0, -20] DstBlock "Delay2" DstPort 2 } Branch { Points [105, 0] DstBlock "Delay3" DstPort 2 } } Branch { Points [0, -20] DstBlock "Delay" DstPort 2 } } Line { SrcBlock "b0" SrcPort 1 DstBlock "Logical7" DstPort 1 } Line { SrcBlock "From6" SrcPort 1 DstBlock "Register" DstPort 1 } Line { SrcBlock "Delay" SrcPort 1 Points [30, 0; 0, -10] Branch { DstBlock "Delay2" DstPort 1 } Branch { Points [0, -210] DstBlock "Logical7" DstPort 3 } } Line { SrcBlock "Register" SrcPort 1 Points [25, 0] Branch { Points [0, 40] Branch { Points [0, 35] DstBlock "b2" DstPort 1 } Branch { DstBlock "b1" DstPort 1 } } Branch { DstBlock "b0" DstPort 1 } } } } Block { BlockType Reference Name "Gateway Out1" SID "11831" Ports [1, 1] Position [1090, 79, 1125, 91] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "En" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "11832" Ports [1, 1] Position [1090, 99, 1125, 111] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Corr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "11833" Ports [1, 1] Position [1090, 119, 1125, 131] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Big Peak" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "11834" Ports [1, 1] Position [1090, 139, 1125, 151] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Small Peak" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "11835" Ports [1, 1] Position [1090, 159, 1125, 171] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Corr Event" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Goto Name "Goto" SID "11836" Position [1090, 14, 1225, 36] ZOrder -10 ShowName off GotoTag "CS_LTS_BigPeak" TagVisibility "global" } Block { BlockType Goto Name "Goto1" SID "11837" Position [1090, 34, 1225, 56] ZOrder -10 ShowName off GotoTag "CS_LTS_SmallPeak" TagVisibility "global" } Block { BlockType Goto Name "Goto2" SID "11838" Position [1090, 54, 1225, 76] ZOrder -10 ShowName off GotoTag "CS_LTS_Det" TagVisibility "global" } Block { BlockType Goto Name "Goto3" SID "14872" Position [955, 449, 1090, 471] ZOrder -10 ShowName off GotoTag "CS_LTS_Peak" TagVisibility "global" } Block { BlockType Reference Name "Inverter" SID "11839" Ports [1, 1] Position [560, 345, 585, 365] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "25,20,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 20 20 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[12.22 12.22 14" ".22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[10.22 10.22 12.22 12.22 10.22" " ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatch([9." "55 16.44 14.44 12.44 10.44 7.55 9.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter1" SID "11840" Ports [1, 1] Position [450, 246, 485, 274] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "1" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "35,28,1,1,white,blue,0,e69ac283,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 28 28 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 28 28 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[18.44 18.44 22.4" "4 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[14.44 14.44 18.44 18.44 14.44 ]," "[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\npatch([12.1" " 25.88 21.88 17.88 13.88 8.1 12.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-1}\\newline '," "'texmode','on');\ncolor('black');disp(' \\nnot');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Scope Name "LTS Corr Decision" SID "11841" Ports [8] Position [1265, 74, 1310, 236] ZOrder -3 Floating off Location [1921, 45, 3841, 1199] Open off NumInputPorts "8" ZoomMode "yonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" } List { ListType ScopeGraphics FigureColor "[0.5 0.5 0.5]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "20000" YMin "0~0~-1~0~0~-1~-1~-1" YMax "1~25000~1~1~1~1~1~1" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType Reference Name "Logical" SID "11842" Ports [3, 1] Position [625, 238, 665, 282] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "3" en off latency "1" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,44,3,1,white,blue,0,e36395a3,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 44 44 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 44 44 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[27.55 27.55 32." "55 27.55 32.55 32.55 32.55 27.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[22.55 22.55 27.55 27.55 22." "55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[17.55 17.55 22.55 22.55 17.55 ],[1 1 1 ]);\npa" "tch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[12.55 12.55 17.55 12.55 17.55 17.55 12.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\ncolor('black');disp(" "'z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\nand');\nfprintf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Big Peak" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Logical1" SID "14871" Ports [2, 1] Position [780, 438, 820, 482] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "1" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,44,2,1,white,blue,0,bc838b24,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 44 44 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 44 44 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[27.55 27.55 32." "55 27.55 32.55 32.55 32.55 27.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[22.55 22.55 27.55 27.55 22." "55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[17.55 17.55 22.55 22.55 17.55 ],[1 1 1 ]);\npa" "tch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[12.55 12.55 17.55 12.55 17.55 17.55 12.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('z" "^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\nor');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "11843" Ports [3, 1] Position [625, 318, 665, 362] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "3" en off latency "1" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,44,3,1,white,blue,0,e36395a3,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 44 44 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 44 44 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[27.55 27.55 32." "55 27.55 32.55 32.55 32.55 27.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[22.55 22.55 27.55 27.55 22." "55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[17.55 17.55 22.55 22.55 17.55 ],[1 1 1 ]);\npa" "tch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[12.55 12.55 17.55 12.55 17.55 17.55 12.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\ncolor('black');disp(" "'z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\nand');\nfprintf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Small Peak" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Logical4" SID "11844" Ports [2, 1] Position [915, 263, 955, 307] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "1" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,44,2,1,white,blue,0,bc838b24,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 44 44 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 44 44 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[27.55 27.55 32." "55 27.55 32.55 32.55 32.55 27.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[22.55 22.55 27.55 27.55 22." "55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[17.55 17.55 22.55 22.55 17.55 ],[1 1 1 ]);\npa" "tch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[12.55 12.55 17.55 12.55 17.55 17.55 12.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('z" "^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\nor');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "MSB" SID "11845" Ports [1, 1] Position [385, 250, 420, 270] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type" " is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardw" "are notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Upper Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "35,20,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 20 20 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[12.22 12.22" " 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[10.22 10.22 12.22 12.22" " 10.22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\n" "patch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('ou" "tput',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational1" SID "11846" Ports [2, 1] Position [445, 333, 490, 377] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a>b" en off latency "1" dbl_ovrd off xl_use_area off xl_area "[10 0 0 19 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,2,1,white,blue,0,3049caaa,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 28.66 3" "4.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 28.66 22" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('" "input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa > b','texmo" "de','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\n ');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Outport Name "Det" SID "11847" Position [1040, 278, 1070, 292] IconDisplay "Port number" } Line { SrcBlock "Corr" SrcPort 1 Points [50, 0] Branch { Points [0, 75] DstBlock "AddSub" DstPort 1 } Branch { Points [360, 0; 0, -70] DstBlock "Gateway Out2" DstPort 1 } } Line { Name "Corr" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 DstBlock "LTS Corr Decision" DstPort 2 } Line { Name "Big Peak" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 DstBlock "LTS Corr Decision" DstPort 3 } Line { Name "Small Peak" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 DstBlock "LTS Corr Decision" DstPort 4 } Line { SrcBlock "Corr Thresh" SrcPort 1 DstBlock "AddSub" DstPort 2 } Line { SrcBlock "AddSub" SrcPort 1 Points [5, 0] Branch { Points [0, 85] DstBlock "Relational1" DstPort 1 } Branch { DstBlock "MSB" DstPort 1 } } Line { SrcBlock "MSB" SrcPort 1 DstBlock "Inverter1" DstPort 1 } Line { SrcBlock "Relational1" SrcPort 1 Points [40, 0] Branch { DstBlock "Inverter" DstPort 1 } Branch { Points [0, -80] DstBlock "Logical" DstPort 3 } } Line { SrcBlock "Peak Type Thresh" SrcPort 1 DstBlock "Relational1" DstPort 2 } Line { Name "Big Peak" Labels [0, 0] SrcBlock "Logical" SrcPort 1 Points [40, 0] Branch { DstBlock "Dual Peak Det" DstPort 1 } Branch { Points [0, -135] Branch { DstBlock "Gateway Out3" DstPort 1 } Branch { Points [0, -100] DstBlock "Goto" DstPort 1 } } Branch { Points [0, 210] DstBlock "Logical1" DstPort 2 } } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical2" DstPort 3 } Line { Name "Corr Event" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 DstBlock "LTS Corr Decision" DstPort 5 } Line { SrcBlock "IQ Valid" SrcPort 1 Points [520, 0; 0, -35] Branch { Points [0, -80] DstBlock "Dual Peak Det" DstPort 2 } Branch { DstBlock "Dual Peak Det1" DstPort 2 } } Line { SrcBlock "Inverter1" SrcPort 1 Points [105, 0] Branch { DstBlock "Logical" DstPort 2 } Branch { Points [0, 80] DstBlock "Logical2" DstPort 2 } } Line { SrcBlock "En" SrcPort 1 Points [405, 0] Branch { Points [0, 105] Branch { DstBlock "Logical" DstPort 1 } Branch { DstBlock "Logical2" DstPort 1 } } Branch { Points [0, -55] DstBlock "Gateway Out1" DstPort 1 } } Line { Name "En" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 DstBlock "LTS Corr Decision" DstPort 1 } Line { Name "Small Peak" Labels [0, 0] SrcBlock "Logical2" SrcPort 1 Points [45, 0] Branch { DstBlock "Dual Peak Det1" DstPort 1 } Branch { Points [0, -195] Branch { DstBlock "Gateway Out4" DstPort 1 } Branch { Points [0, -100] DstBlock "Goto1" DstPort 1 } } Branch { Points [0, 110] DstBlock "Logical1" DstPort 1 } } Line { SrcBlock "Dual Peak Det" SrcPort 1 DstBlock "Logical4" DstPort 1 } Line { SrcBlock "Dual Peak Det1" SrcPort 1 Points [55, 0; 0, -60] DstBlock "Logical4" DstPort 2 } Line { SrcBlock "Logical4" SrcPort 1 Points [35, 0] Branch { DstBlock "Det" DstPort 1 } Branch { Points [0, -120] Branch { DstBlock "Gateway Out6" DstPort 1 } Branch { Points [0, -100] DstBlock "Goto2" DstPort 1 } } } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Goto3" DstPort 1 } } } Block { BlockType SubSystem Name "Correlator" SID "11848" Ports [3, 1] Position [445, 275, 505, 385] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Correlator" Location [480, 85, 2304, 1471] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Rx I" SID "11849" Position [185, 168, 215, 182] IconDisplay "Port number" } Block { BlockType Inport Name "Rx Q" SID "11850" Position [185, 258, 215, 272] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "rx_IQ_valid" SID "11851" Position [140, 303, 170, 317] Port "3" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub1" SID "11852" Ports [2, 1] Position [895, 239, 935, 286] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "1" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[4 7 0 6 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,47,2,1,white,blue,0,e85d8a90,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 47 47 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 47 47 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[28.55 28.55 33." "55 28.55 33.55 33.55 33.55 28.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[23.55 23.55 28.55 28.55 23." "55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[18.55 18.55 23.55 23.55 18.55 ],[1 1 1 ]);\npa" "tch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[13.55 13.55 18.55 13.55 18.55 18.55 13.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i" "nput',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bf{a + b}','texm" "ode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\newline\\bf{}','texm" "ode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub2" SID "11853" Ports [2, 1] Position [895, 344, 935, 391] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "1" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[4 7 0 6 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,47,2,1,white,blue,0,e85d8a90,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 47 47 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 47 47 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[28.55 28.55 33." "55 28.55 33.55 33.55 33.55 28.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[23.55 23.55 28.55 28.55 23." "55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[18.55 18.55 23.55 23.55 18.55 ],[1 1 1 ]);\npa" "tch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[13.55 13.55 18.55 13.55 18.55 18.55 13.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i" "nput',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bf{a + b}','texm" "ode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\newline\\bf{}','texm" "ode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub3" SID "11854" Ports [2, 1] Position [895, 429, 935, 476] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "1" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[4 7 0 6 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,47,2,1,white,blue,0,e85d8a90,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 47 47 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 47 47 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[28.55 28.55 33." "55 28.55 33.55 33.55 33.55 28.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[23.55 23.55 28.55 28.55 23." "55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[18.55 18.55 23.55 23.55 18.55 ],[1 1 1 ]);\npa" "tch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[13.55 13.55 18.55 13.55 18.55 18.55 13.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i" "nput',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bf{a + b}','texm" "ode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\newline\\bf{}','texm" "ode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub4" SID "11855" Ports [2, 1] Position [895, 144, 935, 191] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "1" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[4 7 0 6 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,47,2,1,white,blue,0,e85d8a90,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 47 47 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 47 47 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[28.55 28.55 33." "55 28.55 33.55 33.55 33.55 28.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[23.55 23.55 28.55 28.55 23." "55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[18.55 18.55 23.55 23.55 18.55 ],[1 1 1 ]);\npa" "tch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[13.55 13.55 18.55 13.55 18.55 18.55 13.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i" "nput',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bf{a + b}','texm" "ode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\newline\\bf{}','texm" "ode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "C1" SID "11856" Ports [2, 4] Position [585, 163, 670, 232] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskPromptString "Coefficients/correlator|Coefficients|Input sample period" MaskStyleString "edit,edit,edit" MaskVariables "N=@1;h=@2;Ts_In=@3;" MaskTunableValueString "on,on,on" MaskCallbackString "||" MaskEnableString "on,on,on" MaskVisibilityString "on,on,on" MaskToolTipString "on,on,on" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "4|longCorr_coef_i(1:32)|4" System { Name "C1" Location [480, 85, 2304, 1455] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "156" Block { BlockType Inport Name "x" SID "11857" Position [35, 213, 65, 227] IconDisplay "Port number" } Block { BlockType Inport Name "x_valid" SID "11858" Position [35, 253, 65, 267] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub1" SID "11859" Ports [2, 1] Position [915, 455, 955, 495] BlockRotation 270 BlockMirror on NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "1" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[3 6 0 5 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,40,2,1,white,blue,0,e85d8a90,down,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bf{a + b}','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\ne" "wline\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub12" SID "11860" Ports [2, 1] Position [684, 360, 731, 400] BlockRotation 270 BlockMirror on NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "1" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[3 5 0 4 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "47,40,2,1,white,blue,0,e85d8a90,down,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 47 47 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 47 47 0 0 ],[0 0 40 40 0 ]);\npatch([11.875 19.1 24.1 29.1 34.1 24.1 16.875 11.875 ],[25.55 2" "5.55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([16.875 24.1 19.1 11.875 16.875 ],[20.55 20.55 25.5" "5 25.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([11.875 19.1 24.1 16.875 11.875 ],[15.55 15.55 20.55 20.55 15.55 ]" ",[1 1 1 ]);\npatch([16.875 34.1 29.1 24.1 19.1 11.875 16.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('b" "lack');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output'" ",1,'\\bf{a + b}','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(" "' \\newline\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub13" SID "11861" Ports [2, 1] Position [680, 455, 720, 495] BlockRotation 270 BlockMirror on NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "1" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[3 6 0 5 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,40,2,1,white,blue,0,e85d8a90,down,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bf{a + b}','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\ne" "wline\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub4" SID "11862" Ports [2, 1] Position [960, 549, 1000, 596] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "1" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[4 7 0 6 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,47,2,1,white,blue,0,e85d8a90,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 47 47 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 47 47 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[28.55 28." "55 33.55 28.55 33.55 33.55 33.55 28.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[23.55 23.55 28.55 2" "8.55 23.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[18.55 18.55 23.55 23.55 18.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[13.55 13.55 18.55 13.55 18.55 18.55 13.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bf{a + b}','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\ne" "wline\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub5" SID "11863" Ports [2, 1] Position [475, 360, 515, 400] BlockRotation 270 BlockMirror on NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "1" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[3 6 0 5 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,40,2,1,white,blue,0,e85d8a90,down,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bf{a + b}','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\ne" "wline\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub6" SID "11864" Ports [2, 1] Position [899, 360, 946, 400] BlockRotation 270 BlockMirror on NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "1" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[3 5 0 4 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "47,40,2,1,white,blue,0,e85d8a90,down,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 47 47 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 47 47 0 0 ],[0 0 40 40 0 ]);\npatch([11.875 19.1 24.1 29.1 34.1 24.1 16.875 11.875 ],[25.55 2" "5.55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([16.875 24.1 19.1 11.875 16.875 ],[20.55 20.55 25.5" "5 25.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([11.875 19.1 24.1 16.875 11.875 ],[15.55 15.55 20.55 20.55 15.55 ]" ",[1 1 1 ]);\npatch([16.875 34.1 29.1 24.1 19.1 11.875 16.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('b" "lack');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output'" ",1,'\\bf{a + b}','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(" "' \\newline\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub7" SID "11865" Ports [2, 1] Position [1109, 360, 1156, 400] BlockRotation 270 BlockMirror on NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "1" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[3 5 0 4 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "47,40,2,1,white,blue,0,e85d8a90,down,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 47 47 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 47 47 0 0 ],[0 0 40 40 0 ]);\npatch([11.875 19.1 24.1 29.1 34.1 24.1 16.875 11.875 ],[25.55 2" "5.55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([16.875 24.1 19.1 11.875 16.875 ],[20.55 20.55 25.5" "5 25.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([11.875 19.1 24.1 16.875 11.875 ],[15.55 15.55 20.55 20.55 15.55 ]" ",[1 1 1 ]);\npatch([16.875 34.1 29.1 24.1 19.1 11.875 16.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('b" "lack');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output'" ",1,'\\bf{a + b}','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(" "' \\newline\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "C1" SID "11866" Ports [4, 4] Position [300, 207, 370, 293] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskPromptString "Coefficients (all)|Sub-correlator Ind|Coef/correlator" MaskStyleString "edit,edit,edit" MaskVariables "h=@1;c_ind=@2;N=@3;" MaskTunableValueString "on,on,on" MaskCallbackString "||" MaskEnableString "on,on,on" MaskVisibilityString "on,on,on" MaskToolTipString "on,on,on" MaskInitialization "coef2 = h((c_ind*N+1) : (c_ind + 1)*N);" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "h|0|N" System { Name "C1" Location [480, 85, 2304, 1471] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "122" Block { BlockType Inport Name "x" SID "11867" Position [265, 263, 295, 277] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "vin" SID "11868" Position [270, 303, 300, 317] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "11869" Position [270, 458, 300, 472] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "11870" Position [270, 503, 300, 517] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "ASR" SID "11871" Ports [3, 1] Position [445, 260, 490, 320] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Addressable Shift Register" SourceType "Xilinx Addressable Shift Register Block" infoedit "Delay of configurable length. Any element in the delay line can be addressed and driven onto the" " output port.

Hardware notes: This block is implemented using SRL16s. If Virtex-4 or Spartan-3 device is " "used, multiple SRLC16s are cascaded together." infer_latency off depth "length(coef2)" initVector "[0]" en on dbl_ovrd off use_behavioral_HDL off Optimization "Resource" xl_use_area off xl_area "[1 0 0 2 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,401" block_type "addrsr" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,60,3,1,white,blue,0,f8ea6153,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 60 60 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 60 60 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[36.66 3" "6.66 42.66 36.66 42.66 42.66 42.66 36.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[30.66 30.66 36.66 " "36.66 30.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[24.66 24.66 30.66 30.66 24.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[18.66 18.66 24.66 18.66 24.66 24.66 18.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'addr');\ncolor('black');port_label('input',3," "'en');\ncolor('black');port_label('output',1,'q');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Delay" SID "11872" Ports [1, 1] Position [705, 441, 730, 469] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "25,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 " "17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33" " 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('blac" "k');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "11873" Position [210, 280, 300, 300] ZOrder -9 ShowName off GotoTag "ltsCorr_dAddr" TagVisibility "scoped" } Block { BlockType From Name "From1" SID "11874" Position [210, 340, 300, 360] ZOrder -9 ShowName off GotoTag "ltsCorr_cAddr" TagVisibility "scoped" } Block { BlockType From Name "From2" SID "11875" Position [210, 380, 300, 400] ZOrder -9 ShowName off GotoTag "ltsCorr_ld" TagVisibility "scoped" } Block { BlockType Reference Name "Gateway Out1" SID "11876" Ports [1, 1] Position [745, 615, 780, 625] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "11877" Ports [1, 1] Position [745, 630, 780, 640] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "11878" Ports [1, 1] Position [745, 645, 780, 655] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Ld" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "11879" Ports [1, 1] Position [745, 660, 780, 670] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "11880" Ports [1, 1] Position [745, 675, 780, 685] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "11881" Ports [1, 1] Position [745, 570, 780, 580] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X In" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "11882" Ports [1, 1] Position [745, 585, 780, 595] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "11883" Ports [1, 1] Position [745, 600, 780, 610] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X Vin" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType SubSystem Name "MAC" SID "11884" Ports [4, 2] Position [575, 279, 660, 376] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "MAC" Location [88, 301, 2330, 1301] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "a" SID "11885" Position [35, 143, 65, 157] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "coeff" SID "11886" Position [35, 108, 65, 122] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "ld" SID "11887" Position [35, 178, 65, 192] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "rst" SID "11888" Position [35, 233, 65, 247] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub" SID "11889" Ports [3, 1] Position [340, 113, 385, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition or Subtraction" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Signed (2's comp)" n_bits "long_cor_acc_n_bits" bin_pt "0" quantization "Truncate" overflow "Flag as error" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[2 0 0 4 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,344" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,3,1,white,blue,0,02f64c57,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('input',3,'su" "b');\ncolor('black');port_label('output',1,'\\bf{a \\pm b}','texmode','on');\nfprintf('','COMMENT: end icon text" "');\n" } Block { BlockType Reference Name "Gateway Out1" SID "11890" Ports [1, 1] Position [475, 450, 510, 460] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out2" SID "11891" Ports [1, 1] Position [475, 465, 510, 475] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out3" SID "11892" Ports [1, 1] Position [475, 480, 510, 490] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out6" SID "11893" Ports [1, 1] Position [475, 405, 510, 415] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out7" SID "11894" Ports [1, 1] Position [475, 420, 510, 430] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out8" SID "11895" Ports [1, 1] Position [475, 435, 510, 445] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "11896" Ports [2, 1] Position [345, 30, 385, 70] BlockMirror on NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,40,2,1,white,blue,0,140cc11c,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'" "q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "11897" Ports [2, 1] Position [465, 110, 495, 210] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,100,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 100 100 0 ],[0.77 0." "82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 100 100 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[54.44 " "54.44 58.44 54.44 58.44 58.44 58.44 54.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[50.44 50.44 54.44 54" ".44 50.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[46.44 46.44 50.44 50.44 46.44 ],[1 1 1 ])" ";\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[42.44 42.44 46.44 42.44 46.44 46.44 42.44 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\nco" "lor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc2" SID "11898" Ports [1, 1] Position [265, 143, 290, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc3" SID "11899" Ports [1, 1] Position [135, 178, 160, 192] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "yn" SID "11900" Position [545, 153, 575, 167] IconDisplay "Port number" } Block { BlockType Outport Name "accrm" SID "11901" Position [520, 288, 550, 302] Port "2" IconDisplay "Port number" } Line { SrcBlock "coeff" SrcPort 1 Points [95, 0; 0, 20; 50, 0] Branch { DstBlock "AddSub" DstPort 2 } Branch { Points [0, 275] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "bc2" SrcPort 1 DstBlock "AddSub" DstPort 3 } Line { SrcBlock "bc3" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "ld" SrcPort 1 Points [45, 0] Branch { DstBlock "bc3" DstPort 1 } Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "Register1" SrcPort 1 Points [-15, 0] DstBlock "AddSub" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 Points [15, 0] Branch { DstBlock "yn" DstPort 1 } Branch { Points [0, 50; 110, 0; 0, 385; -260, 0; 0, -110] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "AddSub" SrcPort 1 Points [0, 0; 5, 0] Branch { Points [40, 0] Branch { DstBlock "Register2" DstPort 1 } Branch { Points [0, -95] DstBlock "Register1" DstPort 1 } Branch { Points [0, 160] DstBlock "accrm" DstPort 1 } } Branch { Points [0, 305] DstBlock "Gateway Out8" DstPort 1 } } Line { SrcBlock "a" SrcPort 1 Points [140, 0] Branch { DstBlock "bc2" DstPort 1 } Branch { Points [0, 275] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "Gateway Out8" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out7" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out6" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out1" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out2" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out3" SrcPort 1 Points [50, 0] } Line { SrcBlock "rst" SrcPort 1 Points [90, 0] Branch { Points [255, 0; 0, -180] DstBlock "Register1" DstPort 2 } Branch { Points [0, 215] DstBlock "Gateway Out1" DstPort 1 } } } } Block { BlockType Reference Name "ROM" SID "11902" Ports [1, 1] Position [440, 328, 490, 372] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/ROM" SourceType "Xilinx Single Port Read-Only Memory Block" depth "length(coef2)" initVector "coef2" distributed_mem "Distributed memory" rst off init_reg "0" en off latency "1" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "longCorr_coef_nbits" bin_pt "longCorr_coef_bp" preci_type "Single" exp_width "8" frac_width "24" dbl_ovrd off optimize "Area" use_rpm off xl_use_area off xl_area "[1 1 0 1 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,308" block_type "sprom" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,44,1,1,white,blue,0,bbc23d60,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 44 44 0 ]);\npatch([11.65 20.32 26.32 32.32 38.32 26.32 17.65 11.65 ],[28.66" " 28.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([17.65 26.32 20.32 11.65 17.65 ],[22.66 22.66 28." "66 28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([11.65 20.32 26.32 17.65 11.65 ],[16.66 16.66 22.66 22.66 16.66 ]" ",[1 1 1 ]);\npatch([17.65 38.32 32.32 26.32 20.32 11.65 17.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'addr');\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end" " icon text');\n" } Block { BlockType Outport Name "x_dly" SID "11903" Position [790, 178, 820, 192] IconDisplay "Port number" } Block { BlockType Outport Name "x_dly_vout" SID "11904" Position [790, 223, 820, 237] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "y" SID "11905" Position [790, 293, 820, 307] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "y_vout" SID "11906" Position [785, 448, 815, 462] Port "4" IconDisplay "Port number" } Line { SrcBlock "From2" SrcPort 1 Points [145, 0] Branch { Points [90, 0] Branch { Points [0, -50] Branch { DstBlock "MAC" DstPort 3 } Branch { Points [0, -90; 160, 0] } } Branch { Points [0, 65] DstBlock "Delay" DstPort 1 } } Branch { Points [0, 260] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "ROM" SrcPort 1 Points [5, 0] Branch { Points [0, -35] DstBlock "MAC" DstPort 2 } Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "MAC" SrcPort 1 Points [0, -5; 15, 0] Branch { DstBlock "y" DstPort 1 } Branch { Points [0, 365] DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "ASR" SrcPort 1 Points [35, 0] Branch { DstBlock "MAC" DstPort 1 } Branch { Points [0, -105] DstBlock "x_dly" DstPort 1 } Branch { Points [0, 330] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "From1" SrcPort 1 Points [5, 0] Branch { DstBlock "ROM" DstPort 1 } Branch { Points [0, 330] DstBlock "Gateway Out5" DstPort 1 } } Line { SrcBlock "From" SrcPort 1 Points [90, 0] Branch { DstBlock "ASR" DstPort 2 } Branch { Points [0, 300] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "x" SrcPort 1 Points [100, 0] Branch { DstBlock "ASR" DstPort 1 } Branch { Points [0, 305] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "vin" SrcPort 1 Points [25, 0] Branch { DstBlock "ASR" DstPort 3 } Branch { Points [0, 100] Branch { Points [0, 195] DstBlock "Gateway Out8" DstPort 1 } Branch { Points [230, 0] DstBlock "MAC" DstPort 4 } } Branch { Points [0, -80] DstBlock "x_dly_vout" DstPort 1 } } Line { SrcBlock "Delay" SrcPort 1 DstBlock "y_vout" DstPort 1 } Line { Name "X Vin" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 Points [150, 0] } Line { Name "ASR Addr" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 Points [150, 0] } Line { Name "X In" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 Points [150, 0] } Line { Name "ASR Out" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 Points [150, 0] } Line { Name "ROM Out" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 Points [150, 0] } Line { Name "Corr Ld" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 Points [150, 0] } Line { Name "Corr Out" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 Points [150, 0] } Line { Name "ROM Addr" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 Points [150, 0] } } } Block { BlockType SubSystem Name "C2" SID "11907" Ports [4, 4] Position [410, 207, 480, 293] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskPromptString "Coefficients (all)|Sub-correlator Ind|Coef/correlator" MaskStyleString "edit,edit,edit" MaskVariables "h=@1;c_ind=@2;N=@3;" MaskTunableValueString "on,on,on" MaskCallbackString "||" MaskEnableString "on,on,on" MaskVisibilityString "on,on,on" MaskToolTipString "on,on,on" MaskInitialization "coef2 = h((c_ind*N+1) : (c_ind + 1)*N);" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "h|1|N" System { Name "C2" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "122" Block { BlockType Inport Name "x" SID "11908" Position [265, 263, 295, 277] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "vin" SID "11909" Position [270, 303, 300, 317] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "11910" Position [270, 458, 300, 472] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "11911" Position [270, 503, 300, 517] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "ASR" SID "11912" Ports [3, 1] Position [445, 260, 490, 320] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Addressable Shift Register" SourceType "Xilinx Addressable Shift Register Block" infoedit "Delay of configurable length. Any element in the delay line can be addressed and driven onto the" " output port.

Hardware notes: This block is implemented using SRL16s. If Virtex-4 or Spartan-3 device is " "used, multiple SRLC16s are cascaded together." infer_latency off depth "length(coef2)" initVector "[0]" en on dbl_ovrd off use_behavioral_HDL off Optimization "Resource" xl_use_area off xl_area "[1 0 0 2 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,401" block_type "addrsr" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,60,3,1,white,blue,0,f8ea6153,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 60 60 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 60 60 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[36.66 3" "6.66 42.66 36.66 42.66 42.66 42.66 36.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[30.66 30.66 36.66 " "36.66 30.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[24.66 24.66 30.66 30.66 24.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[18.66 18.66 24.66 18.66 24.66 24.66 18.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'addr');\ncolor('black');port_label('input',3," "'en');\ncolor('black');port_label('output',1,'q');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Delay" SID "11913" Ports [1, 1] Position [705, 441, 730, 469] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "25,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 " "17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33" " 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('blac" "k');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "11914" Position [210, 280, 300, 300] ZOrder -9 ShowName off GotoTag "ltsCorr_dAddr" TagVisibility "scoped" } Block { BlockType From Name "From1" SID "11915" Position [210, 340, 300, 360] ZOrder -9 ShowName off GotoTag "ltsCorr_cAddr" TagVisibility "scoped" } Block { BlockType From Name "From2" SID "11916" Position [210, 380, 300, 400] ZOrder -9 ShowName off GotoTag "ltsCorr_ld" TagVisibility "scoped" } Block { BlockType Reference Name "Gateway Out1" SID "11917" Ports [1, 1] Position [745, 615, 780, 625] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "11918" Ports [1, 1] Position [745, 630, 780, 640] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "11919" Ports [1, 1] Position [745, 645, 780, 655] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Ld" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "11920" Ports [1, 1] Position [745, 660, 780, 670] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "11921" Ports [1, 1] Position [745, 675, 780, 685] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "11922" Ports [1, 1] Position [745, 570, 780, 580] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X In" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "11923" Ports [1, 1] Position [745, 585, 780, 595] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "11924" Ports [1, 1] Position [745, 600, 780, 610] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X Vin" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType SubSystem Name "MAC" SID "11925" Ports [4, 2] Position [575, 279, 660, 376] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "MAC" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "a" SID "11926" Position [35, 143, 65, 157] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "coeff" SID "11927" Position [35, 108, 65, 122] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "ld" SID "11928" Position [35, 178, 65, 192] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "rst" SID "11929" Position [35, 233, 65, 247] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub" SID "11930" Ports [3, 1] Position [340, 113, 385, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition or Subtraction" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Signed (2's comp)" n_bits "long_cor_acc_n_bits" bin_pt "0" quantization "Truncate" overflow "Flag as error" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[2 0 0 4 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,344" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,3,1,white,blue,0,02f64c57,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('input',3,'su" "b');\ncolor('black');port_label('output',1,'\\bf{a \\pm b}','texmode','on');\nfprintf('','COMMENT: end icon text" "');\n" } Block { BlockType Reference Name "Gateway Out1" SID "11931" Ports [1, 1] Position [475, 450, 510, 460] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out2" SID "11932" Ports [1, 1] Position [475, 465, 510, 475] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out3" SID "11933" Ports [1, 1] Position [475, 480, 510, 490] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out6" SID "11934" Ports [1, 1] Position [475, 405, 510, 415] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out7" SID "11935" Ports [1, 1] Position [475, 420, 510, 430] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out8" SID "11936" Ports [1, 1] Position [475, 435, 510, 445] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "11937" Ports [2, 1] Position [345, 30, 385, 70] BlockMirror on NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,40,2,1,white,blue,0,140cc11c,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'" "q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "11938" Ports [2, 1] Position [465, 110, 495, 210] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,100,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 100 100 0 ],[0.77 0." "82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 100 100 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[54.44 " "54.44 58.44 54.44 58.44 58.44 58.44 54.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[50.44 50.44 54.44 54" ".44 50.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[46.44 46.44 50.44 50.44 46.44 ],[1 1 1 ])" ";\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[42.44 42.44 46.44 42.44 46.44 46.44 42.44 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\nco" "lor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc2" SID "11939" Ports [1, 1] Position [265, 143, 290, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc3" SID "11940" Ports [1, 1] Position [135, 178, 160, 192] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "yn" SID "11941" Position [545, 153, 575, 167] IconDisplay "Port number" } Block { BlockType Outport Name "accrm" SID "11942" Position [520, 288, 550, 302] Port "2" IconDisplay "Port number" } Line { SrcBlock "rst" SrcPort 1 Points [90, 0] Branch { Points [0, 215] DstBlock "Gateway Out1" DstPort 1 } Branch { Points [255, 0; 0, -180] DstBlock "Register1" DstPort 2 } } Line { SrcBlock "Gateway Out3" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out2" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out1" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out6" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out7" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out8" SrcPort 1 Points [50, 0] } Line { SrcBlock "a" SrcPort 1 Points [140, 0] Branch { Points [0, 275] DstBlock "Gateway Out7" DstPort 1 } Branch { DstBlock "bc2" DstPort 1 } } Line { SrcBlock "AddSub" SrcPort 1 Points [0, 0; 5, 0] Branch { Points [0, 305] DstBlock "Gateway Out8" DstPort 1 } Branch { Points [40, 0] Branch { Points [0, 160] DstBlock "accrm" DstPort 1 } Branch { Points [0, -95] DstBlock "Register1" DstPort 1 } Branch { DstBlock "Register2" DstPort 1 } } } Line { SrcBlock "Register2" SrcPort 1 Points [15, 0] Branch { Points [0, 50; 110, 0; 0, 385; -260, 0; 0, -110] DstBlock "Gateway Out3" DstPort 1 } Branch { DstBlock "yn" DstPort 1 } } Line { SrcBlock "Register1" SrcPort 1 Points [-15, 0] DstBlock "AddSub" DstPort 1 } Line { SrcBlock "ld" SrcPort 1 Points [45, 0] Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } Branch { DstBlock "bc3" DstPort 1 } } Line { SrcBlock "bc3" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "bc2" SrcPort 1 DstBlock "AddSub" DstPort 3 } Line { SrcBlock "coeff" SrcPort 1 Points [95, 0; 0, 20; 50, 0] Branch { Points [0, 275] DstBlock "Gateway Out6" DstPort 1 } Branch { DstBlock "AddSub" DstPort 2 } } } } Block { BlockType Reference Name "ROM" SID "11943" Ports [1, 1] Position [440, 328, 490, 372] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/ROM" SourceType "Xilinx Single Port Read-Only Memory Block" depth "length(coef2)" initVector "coef2" distributed_mem "Distributed memory" rst off init_reg "0" en off latency "1" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "longCorr_coef_nbits" bin_pt "longCorr_coef_bp" preci_type "Single" exp_width "8" frac_width "24" dbl_ovrd off optimize "Area" use_rpm off xl_use_area off xl_area "[1 1 0 1 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,308" block_type "sprom" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,44,1,1,white,blue,0,bbc23d60,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 44 44 0 ]);\npatch([11.65 20.32 26.32 32.32 38.32 26.32 17.65 11.65 ],[28.66" " 28.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([17.65 26.32 20.32 11.65 17.65 ],[22.66 22.66 28." "66 28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([11.65 20.32 26.32 17.65 11.65 ],[16.66 16.66 22.66 22.66 16.66 ]" ",[1 1 1 ]);\npatch([17.65 38.32 32.32 26.32 20.32 11.65 17.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'addr');\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end" " icon text');\n" } Block { BlockType Outport Name "x_dly" SID "11944" Position [790, 178, 820, 192] IconDisplay "Port number" } Block { BlockType Outport Name "x_dly_vout" SID "11945" Position [790, 223, 820, 237] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "y" SID "11946" Position [790, 293, 820, 307] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "y_vout" SID "11947" Position [785, 448, 815, 462] Port "4" IconDisplay "Port number" } Line { Name "ROM Addr" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 Points [150, 0] } Line { Name "Corr Out" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 Points [150, 0] } Line { Name "Corr Ld" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 Points [150, 0] } Line { Name "ROM Out" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 Points [150, 0] } Line { Name "ASR Out" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 Points [150, 0] } Line { Name "X In" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 Points [150, 0] } Line { Name "ASR Addr" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 Points [150, 0] } Line { Name "X Vin" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 Points [150, 0] } Line { SrcBlock "Delay" SrcPort 1 DstBlock "y_vout" DstPort 1 } Line { SrcBlock "vin" SrcPort 1 Points [25, 0] Branch { Points [0, -80] DstBlock "x_dly_vout" DstPort 1 } Branch { Points [0, 100] Branch { Points [230, 0] DstBlock "MAC" DstPort 4 } Branch { Points [0, 195] DstBlock "Gateway Out8" DstPort 1 } } Branch { DstBlock "ASR" DstPort 3 } } Line { SrcBlock "x" SrcPort 1 Points [100, 0] Branch { Points [0, 305] DstBlock "Gateway Out6" DstPort 1 } Branch { DstBlock "ASR" DstPort 1 } } Line { SrcBlock "From" SrcPort 1 Points [90, 0] Branch { Points [0, 300] DstBlock "Gateway Out7" DstPort 1 } Branch { DstBlock "ASR" DstPort 2 } } Line { SrcBlock "From1" SrcPort 1 Points [5, 0] Branch { Points [0, 330] DstBlock "Gateway Out5" DstPort 1 } Branch { DstBlock "ROM" DstPort 1 } } Line { SrcBlock "ASR" SrcPort 1 Points [35, 0] Branch { Points [0, 330] DstBlock "Gateway Out1" DstPort 1 } Branch { Points [0, -105] DstBlock "x_dly" DstPort 1 } Branch { DstBlock "MAC" DstPort 1 } } Line { SrcBlock "MAC" SrcPort 1 Points [0, -5; 15, 0] Branch { Points [0, 365] DstBlock "Gateway Out4" DstPort 1 } Branch { DstBlock "y" DstPort 1 } } Line { SrcBlock "ROM" SrcPort 1 Points [5, 0] Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } Branch { Points [0, -35] DstBlock "MAC" DstPort 2 } } Line { SrcBlock "From2" SrcPort 1 Points [145, 0] Branch { Points [0, 260] DstBlock "Gateway Out3" DstPort 1 } Branch { Points [90, 0] Branch { Points [0, 65] DstBlock "Delay" DstPort 1 } Branch { Points [0, -50] Branch { Points [0, -90; 160, 0] } Branch { DstBlock "MAC" DstPort 3 } } } } } } Block { BlockType SubSystem Name "C3" SID "11948" Ports [4, 4] Position [520, 207, 590, 293] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskPromptString "Coefficients (all)|Sub-correlator Ind|Coef/correlator" MaskStyleString "edit,edit,edit" MaskVariables "h=@1;c_ind=@2;N=@3;" MaskTunableValueString "on,on,on" MaskCallbackString "||" MaskEnableString "on,on,on" MaskVisibilityString "on,on,on" MaskToolTipString "on,on,on" MaskInitialization "coef2 = h((c_ind*N+1) : (c_ind + 1)*N);" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "h|2|N" System { Name "C3" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "122" Block { BlockType Inport Name "x" SID "11949" Position [265, 263, 295, 277] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "vin" SID "11950" Position [270, 303, 300, 317] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "11951" Position [270, 458, 300, 472] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "11952" Position [270, 503, 300, 517] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "ASR" SID "11953" Ports [3, 1] Position [445, 260, 490, 320] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Addressable Shift Register" SourceType "Xilinx Addressable Shift Register Block" infoedit "Delay of configurable length. Any element in the delay line can be addressed and driven onto the" " output port.

Hardware notes: This block is implemented using SRL16s. If Virtex-4 or Spartan-3 device is " "used, multiple SRLC16s are cascaded together." infer_latency off depth "length(coef2)" initVector "[0]" en on dbl_ovrd off use_behavioral_HDL off Optimization "Resource" xl_use_area off xl_area "[1 0 0 2 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,401" block_type "addrsr" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,60,3,1,white,blue,0,f8ea6153,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 60 60 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 60 60 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[36.66 3" "6.66 42.66 36.66 42.66 42.66 42.66 36.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[30.66 30.66 36.66 " "36.66 30.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[24.66 24.66 30.66 30.66 24.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[18.66 18.66 24.66 18.66 24.66 24.66 18.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'addr');\ncolor('black');port_label('input',3," "'en');\ncolor('black');port_label('output',1,'q');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Delay" SID "11954" Ports [1, 1] Position [705, 441, 730, 469] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "25,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 " "17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33" " 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('blac" "k');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "11955" Position [210, 280, 300, 300] ZOrder -9 ShowName off GotoTag "ltsCorr_dAddr" TagVisibility "scoped" } Block { BlockType From Name "From1" SID "11956" Position [210, 340, 300, 360] ZOrder -9 ShowName off GotoTag "ltsCorr_cAddr" TagVisibility "scoped" } Block { BlockType From Name "From2" SID "11957" Position [210, 380, 300, 400] ZOrder -9 ShowName off GotoTag "ltsCorr_ld" TagVisibility "scoped" } Block { BlockType Reference Name "Gateway Out1" SID "11958" Ports [1, 1] Position [745, 615, 780, 625] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "11959" Ports [1, 1] Position [745, 630, 780, 640] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "11960" Ports [1, 1] Position [745, 645, 780, 655] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Ld" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "11961" Ports [1, 1] Position [745, 660, 780, 670] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "11962" Ports [1, 1] Position [745, 675, 780, 685] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "11963" Ports [1, 1] Position [745, 570, 780, 580] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X In" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "11964" Ports [1, 1] Position [745, 585, 780, 595] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "11965" Ports [1, 1] Position [745, 600, 780, 610] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X Vin" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType SubSystem Name "MAC" SID "11966" Ports [4, 2] Position [575, 279, 660, 376] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "MAC" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "a" SID "11967" Position [35, 143, 65, 157] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "coeff" SID "11968" Position [35, 108, 65, 122] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "ld" SID "11969" Position [35, 178, 65, 192] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "rst" SID "11970" Position [35, 233, 65, 247] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub" SID "11971" Ports [3, 1] Position [340, 113, 385, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition or Subtraction" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Signed (2's comp)" n_bits "long_cor_acc_n_bits" bin_pt "0" quantization "Truncate" overflow "Flag as error" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[2 0 0 4 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,344" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,3,1,white,blue,0,02f64c57,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('input',3,'su" "b');\ncolor('black');port_label('output',1,'\\bf{a \\pm b}','texmode','on');\nfprintf('','COMMENT: end icon text" "');\n" } Block { BlockType Reference Name "Gateway Out1" SID "11972" Ports [1, 1] Position [475, 450, 510, 460] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out2" SID "11973" Ports [1, 1] Position [475, 465, 510, 475] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out3" SID "11974" Ports [1, 1] Position [475, 480, 510, 490] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out6" SID "11975" Ports [1, 1] Position [475, 405, 510, 415] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out7" SID "11976" Ports [1, 1] Position [475, 420, 510, 430] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out8" SID "11977" Ports [1, 1] Position [475, 435, 510, 445] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "11978" Ports [2, 1] Position [345, 30, 385, 70] BlockMirror on NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,40,2,1,white,blue,0,140cc11c,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'" "q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "11979" Ports [2, 1] Position [465, 110, 495, 210] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,100,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 100 100 0 ],[0.77 0." "82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 100 100 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[54.44 " "54.44 58.44 54.44 58.44 58.44 58.44 54.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[50.44 50.44 54.44 54" ".44 50.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[46.44 46.44 50.44 50.44 46.44 ],[1 1 1 ])" ";\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[42.44 42.44 46.44 42.44 46.44 46.44 42.44 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\nco" "lor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc2" SID "11980" Ports [1, 1] Position [265, 143, 290, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc3" SID "11981" Ports [1, 1] Position [135, 178, 160, 192] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "yn" SID "11982" Position [545, 153, 575, 167] IconDisplay "Port number" } Block { BlockType Outport Name "accrm" SID "11983" Position [520, 288, 550, 302] Port "2" IconDisplay "Port number" } Line { SrcBlock "coeff" SrcPort 1 Points [95, 0; 0, 20; 50, 0] Branch { DstBlock "AddSub" DstPort 2 } Branch { Points [0, 275] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "bc2" SrcPort 1 DstBlock "AddSub" DstPort 3 } Line { SrcBlock "bc3" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "ld" SrcPort 1 Points [45, 0] Branch { DstBlock "bc3" DstPort 1 } Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "Register1" SrcPort 1 Points [-15, 0] DstBlock "AddSub" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 Points [15, 0] Branch { DstBlock "yn" DstPort 1 } Branch { Points [0, 50; 110, 0; 0, 385; -260, 0; 0, -110] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "AddSub" SrcPort 1 Points [0, 0; 5, 0] Branch { Points [40, 0] Branch { DstBlock "Register2" DstPort 1 } Branch { Points [0, -95] DstBlock "Register1" DstPort 1 } Branch { Points [0, 160] DstBlock "accrm" DstPort 1 } } Branch { Points [0, 305] DstBlock "Gateway Out8" DstPort 1 } } Line { SrcBlock "a" SrcPort 1 Points [140, 0] Branch { DstBlock "bc2" DstPort 1 } Branch { Points [0, 275] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "Gateway Out8" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out7" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out6" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out1" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out2" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out3" SrcPort 1 Points [50, 0] } Line { SrcBlock "rst" SrcPort 1 Points [90, 0] Branch { Points [255, 0; 0, -180] DstBlock "Register1" DstPort 2 } Branch { Points [0, 215] DstBlock "Gateway Out1" DstPort 1 } } } } Block { BlockType Reference Name "ROM" SID "11984" Ports [1, 1] Position [440, 328, 490, 372] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/ROM" SourceType "Xilinx Single Port Read-Only Memory Block" depth "length(coef2)" initVector "coef2" distributed_mem "Distributed memory" rst off init_reg "0" en off latency "1" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "longCorr_coef_nbits" bin_pt "longCorr_coef_bp" preci_type "Single" exp_width "8" frac_width "24" dbl_ovrd off optimize "Area" use_rpm off xl_use_area off xl_area "[1 1 0 1 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,308" block_type "sprom" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,44,1,1,white,blue,0,bbc23d60,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 44 44 0 ]);\npatch([11.65 20.32 26.32 32.32 38.32 26.32 17.65 11.65 ],[28.66" " 28.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([17.65 26.32 20.32 11.65 17.65 ],[22.66 22.66 28." "66 28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([11.65 20.32 26.32 17.65 11.65 ],[16.66 16.66 22.66 22.66 16.66 ]" ",[1 1 1 ]);\npatch([17.65 38.32 32.32 26.32 20.32 11.65 17.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'addr');\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end" " icon text');\n" } Block { BlockType Outport Name "x_dly" SID "11985" Position [790, 178, 820, 192] IconDisplay "Port number" } Block { BlockType Outport Name "x_dly_vout" SID "11986" Position [790, 223, 820, 237] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "y" SID "11987" Position [790, 293, 820, 307] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "y_vout" SID "11988" Position [785, 448, 815, 462] Port "4" IconDisplay "Port number" } Line { SrcBlock "From2" SrcPort 1 Points [145, 0] Branch { Points [90, 0] Branch { Points [0, -50] Branch { DstBlock "MAC" DstPort 3 } Branch { Points [0, -90; 160, 0] } } Branch { Points [0, 65] DstBlock "Delay" DstPort 1 } } Branch { Points [0, 260] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "ROM" SrcPort 1 Points [5, 0] Branch { Points [0, -35] DstBlock "MAC" DstPort 2 } Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "MAC" SrcPort 1 Points [0, -5; 15, 0] Branch { DstBlock "y" DstPort 1 } Branch { Points [0, 365] DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "ASR" SrcPort 1 Points [35, 0] Branch { DstBlock "MAC" DstPort 1 } Branch { Points [0, -105] DstBlock "x_dly" DstPort 1 } Branch { Points [0, 330] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "From1" SrcPort 1 Points [5, 0] Branch { DstBlock "ROM" DstPort 1 } Branch { Points [0, 330] DstBlock "Gateway Out5" DstPort 1 } } Line { SrcBlock "From" SrcPort 1 Points [90, 0] Branch { DstBlock "ASR" DstPort 2 } Branch { Points [0, 300] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "x" SrcPort 1 Points [100, 0] Branch { DstBlock "ASR" DstPort 1 } Branch { Points [0, 305] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "vin" SrcPort 1 Points [25, 0] Branch { DstBlock "ASR" DstPort 3 } Branch { Points [0, 100] Branch { Points [0, 195] DstBlock "Gateway Out8" DstPort 1 } Branch { Points [230, 0] DstBlock "MAC" DstPort 4 } } Branch { Points [0, -80] DstBlock "x_dly_vout" DstPort 1 } } Line { SrcBlock "Delay" SrcPort 1 DstBlock "y_vout" DstPort 1 } Line { Name "X Vin" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 Points [150, 0] } Line { Name "ASR Addr" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 Points [150, 0] } Line { Name "X In" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 Points [150, 0] } Line { Name "ASR Out" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 Points [150, 0] } Line { Name "ROM Out" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 Points [150, 0] } Line { Name "Corr Ld" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 Points [150, 0] } Line { Name "Corr Out" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 Points [150, 0] } Line { Name "ROM Addr" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 Points [150, 0] } } } Block { BlockType SubSystem Name "C4" SID "11989" Ports [4, 4] Position [630, 207, 700, 293] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskPromptString "Coefficients (all)|Sub-correlator Ind|Coef/correlator" MaskStyleString "edit,edit,edit" MaskVariables "h=@1;c_ind=@2;N=@3;" MaskTunableValueString "on,on,on" MaskCallbackString "||" MaskEnableString "on,on,on" MaskVisibilityString "on,on,on" MaskToolTipString "on,on,on" MaskInitialization "coef2 = h((c_ind*N+1) : (c_ind + 1)*N);" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "h|3|N" System { Name "C4" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "122" Block { BlockType Inport Name "x" SID "11990" Position [265, 263, 295, 277] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "vin" SID "11991" Position [270, 303, 300, 317] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "11992" Position [270, 458, 300, 472] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "11993" Position [270, 503, 300, 517] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "ASR" SID "11994" Ports [3, 1] Position [445, 260, 490, 320] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Addressable Shift Register" SourceType "Xilinx Addressable Shift Register Block" infoedit "Delay of configurable length. Any element in the delay line can be addressed and driven onto the" " output port.

Hardware notes: This block is implemented using SRL16s. If Virtex-4 or Spartan-3 device is " "used, multiple SRLC16s are cascaded together." infer_latency off depth "length(coef2)" initVector "[0]" en on dbl_ovrd off use_behavioral_HDL off Optimization "Resource" xl_use_area off xl_area "[1 0 0 2 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,401" block_type "addrsr" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,60,3,1,white,blue,0,f8ea6153,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 60 60 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 60 60 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[36.66 3" "6.66 42.66 36.66 42.66 42.66 42.66 36.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[30.66 30.66 36.66 " "36.66 30.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[24.66 24.66 30.66 30.66 24.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[18.66 18.66 24.66 18.66 24.66 24.66 18.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'addr');\ncolor('black');port_label('input',3," "'en');\ncolor('black');port_label('output',1,'q');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Delay" SID "11995" Ports [1, 1] Position [705, 441, 730, 469] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "25,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 " "17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33" " 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('blac" "k');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "11996" Position [210, 280, 300, 300] ZOrder -9 ShowName off GotoTag "ltsCorr_dAddr" TagVisibility "scoped" } Block { BlockType From Name "From1" SID "11997" Position [210, 340, 300, 360] ZOrder -9 ShowName off GotoTag "ltsCorr_cAddr" TagVisibility "scoped" } Block { BlockType From Name "From2" SID "11998" Position [210, 380, 300, 400] ZOrder -9 ShowName off GotoTag "ltsCorr_ld" TagVisibility "scoped" } Block { BlockType Reference Name "Gateway Out1" SID "11999" Ports [1, 1] Position [745, 615, 780, 625] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "12000" Ports [1, 1] Position [745, 630, 780, 640] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "12001" Ports [1, 1] Position [745, 645, 780, 655] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Ld" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "12002" Ports [1, 1] Position [745, 660, 780, 670] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "12003" Ports [1, 1] Position [745, 675, 780, 685] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "12004" Ports [1, 1] Position [745, 570, 780, 580] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X In" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "12005" Ports [1, 1] Position [745, 585, 780, 595] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "12006" Ports [1, 1] Position [745, 600, 780, 610] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X Vin" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType SubSystem Name "MAC" SID "12007" Ports [4, 2] Position [575, 279, 660, 376] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "MAC" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "a" SID "12008" Position [35, 143, 65, 157] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "coeff" SID "12009" Position [35, 108, 65, 122] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "ld" SID "12010" Position [35, 178, 65, 192] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "rst" SID "12011" Position [35, 233, 65, 247] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub" SID "12012" Ports [3, 1] Position [340, 113, 385, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition or Subtraction" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Signed (2's comp)" n_bits "long_cor_acc_n_bits" bin_pt "0" quantization "Truncate" overflow "Flag as error" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[2 0 0 4 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,344" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,3,1,white,blue,0,02f64c57,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('input',3,'su" "b');\ncolor('black');port_label('output',1,'\\bf{a \\pm b}','texmode','on');\nfprintf('','COMMENT: end icon text" "');\n" } Block { BlockType Reference Name "Gateway Out1" SID "12013" Ports [1, 1] Position [475, 450, 510, 460] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out2" SID "12014" Ports [1, 1] Position [475, 465, 510, 475] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out3" SID "12015" Ports [1, 1] Position [475, 480, 510, 490] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out6" SID "12016" Ports [1, 1] Position [475, 405, 510, 415] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out7" SID "12017" Ports [1, 1] Position [475, 420, 510, 430] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out8" SID "12018" Ports [1, 1] Position [475, 435, 510, 445] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "12019" Ports [2, 1] Position [345, 30, 385, 70] BlockMirror on NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,40,2,1,white,blue,0,140cc11c,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'" "q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "12020" Ports [2, 1] Position [465, 110, 495, 210] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,100,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 100 100 0 ],[0.77 0." "82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 100 100 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[54.44 " "54.44 58.44 54.44 58.44 58.44 58.44 54.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[50.44 50.44 54.44 54" ".44 50.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[46.44 46.44 50.44 50.44 46.44 ],[1 1 1 ])" ";\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[42.44 42.44 46.44 42.44 46.44 46.44 42.44 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\nco" "lor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc2" SID "12021" Ports [1, 1] Position [265, 143, 290, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc3" SID "12022" Ports [1, 1] Position [135, 178, 160, 192] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "yn" SID "12023" Position [545, 153, 575, 167] IconDisplay "Port number" } Block { BlockType Outport Name "accrm" SID "12024" Position [520, 288, 550, 302] Port "2" IconDisplay "Port number" } Line { SrcBlock "rst" SrcPort 1 Points [90, 0] Branch { Points [0, 215] DstBlock "Gateway Out1" DstPort 1 } Branch { Points [255, 0; 0, -180] DstBlock "Register1" DstPort 2 } } Line { SrcBlock "Gateway Out3" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out2" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out1" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out6" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out7" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out8" SrcPort 1 Points [50, 0] } Line { SrcBlock "a" SrcPort 1 Points [140, 0] Branch { Points [0, 275] DstBlock "Gateway Out7" DstPort 1 } Branch { DstBlock "bc2" DstPort 1 } } Line { SrcBlock "AddSub" SrcPort 1 Points [0, 0; 5, 0] Branch { Points [0, 305] DstBlock "Gateway Out8" DstPort 1 } Branch { Points [40, 0] Branch { Points [0, 160] DstBlock "accrm" DstPort 1 } Branch { Points [0, -95] DstBlock "Register1" DstPort 1 } Branch { DstBlock "Register2" DstPort 1 } } } Line { SrcBlock "Register2" SrcPort 1 Points [15, 0] Branch { Points [0, 50; 110, 0; 0, 385; -260, 0; 0, -110] DstBlock "Gateway Out3" DstPort 1 } Branch { DstBlock "yn" DstPort 1 } } Line { SrcBlock "Register1" SrcPort 1 Points [-15, 0] DstBlock "AddSub" DstPort 1 } Line { SrcBlock "ld" SrcPort 1 Points [45, 0] Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } Branch { DstBlock "bc3" DstPort 1 } } Line { SrcBlock "bc3" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "bc2" SrcPort 1 DstBlock "AddSub" DstPort 3 } Line { SrcBlock "coeff" SrcPort 1 Points [95, 0; 0, 20; 50, 0] Branch { Points [0, 275] DstBlock "Gateway Out6" DstPort 1 } Branch { DstBlock "AddSub" DstPort 2 } } } } Block { BlockType Reference Name "ROM" SID "12025" Ports [1, 1] Position [440, 328, 490, 372] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/ROM" SourceType "Xilinx Single Port Read-Only Memory Block" depth "length(coef2)" initVector "coef2" distributed_mem "Distributed memory" rst off init_reg "0" en off latency "1" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "longCorr_coef_nbits" bin_pt "longCorr_coef_bp" preci_type "Single" exp_width "8" frac_width "24" dbl_ovrd off optimize "Area" use_rpm off xl_use_area off xl_area "[1 1 0 1 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,308" block_type "sprom" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,44,1,1,white,blue,0,bbc23d60,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 44 44 0 ]);\npatch([11.65 20.32 26.32 32.32 38.32 26.32 17.65 11.65 ],[28.66" " 28.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([17.65 26.32 20.32 11.65 17.65 ],[22.66 22.66 28." "66 28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([11.65 20.32 26.32 17.65 11.65 ],[16.66 16.66 22.66 22.66 16.66 ]" ",[1 1 1 ]);\npatch([17.65 38.32 32.32 26.32 20.32 11.65 17.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'addr');\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end" " icon text');\n" } Block { BlockType Outport Name "x_dly" SID "12026" Position [790, 178, 820, 192] IconDisplay "Port number" } Block { BlockType Outport Name "x_dly_vout" SID "12027" Position [790, 223, 820, 237] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "y" SID "12028" Position [790, 293, 820, 307] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "y_vout" SID "12029" Position [785, 448, 815, 462] Port "4" IconDisplay "Port number" } Line { Name "ROM Addr" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 Points [150, 0] } Line { Name "Corr Out" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 Points [150, 0] } Line { Name "Corr Ld" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 Points [150, 0] } Line { Name "ROM Out" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 Points [150, 0] } Line { Name "ASR Out" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 Points [150, 0] } Line { Name "X In" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 Points [150, 0] } Line { Name "ASR Addr" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 Points [150, 0] } Line { Name "X Vin" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 Points [150, 0] } Line { SrcBlock "Delay" SrcPort 1 DstBlock "y_vout" DstPort 1 } Line { SrcBlock "vin" SrcPort 1 Points [25, 0] Branch { Points [0, -80] DstBlock "x_dly_vout" DstPort 1 } Branch { Points [0, 100] Branch { Points [230, 0] DstBlock "MAC" DstPort 4 } Branch { Points [0, 195] DstBlock "Gateway Out8" DstPort 1 } } Branch { DstBlock "ASR" DstPort 3 } } Line { SrcBlock "x" SrcPort 1 Points [100, 0] Branch { Points [0, 305] DstBlock "Gateway Out6" DstPort 1 } Branch { DstBlock "ASR" DstPort 1 } } Line { SrcBlock "From" SrcPort 1 Points [90, 0] Branch { Points [0, 300] DstBlock "Gateway Out7" DstPort 1 } Branch { DstBlock "ASR" DstPort 2 } } Line { SrcBlock "From1" SrcPort 1 Points [5, 0] Branch { Points [0, 330] DstBlock "Gateway Out5" DstPort 1 } Branch { DstBlock "ROM" DstPort 1 } } Line { SrcBlock "ASR" SrcPort 1 Points [35, 0] Branch { Points [0, 330] DstBlock "Gateway Out1" DstPort 1 } Branch { Points [0, -105] DstBlock "x_dly" DstPort 1 } Branch { DstBlock "MAC" DstPort 1 } } Line { SrcBlock "MAC" SrcPort 1 Points [0, -5; 15, 0] Branch { Points [0, 365] DstBlock "Gateway Out4" DstPort 1 } Branch { DstBlock "y" DstPort 1 } } Line { SrcBlock "ROM" SrcPort 1 Points [5, 0] Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } Branch { Points [0, -35] DstBlock "MAC" DstPort 2 } } Line { SrcBlock "From2" SrcPort 1 Points [145, 0] Branch { Points [0, 260] DstBlock "Gateway Out3" DstPort 1 } Branch { Points [90, 0] Branch { Points [0, 65] DstBlock "Delay" DstPort 1 } Branch { Points [0, -50] Branch { Points [0, -90; 160, 0] } Branch { DstBlock "MAC" DstPort 3 } } } } } } Block { BlockType SubSystem Name "C5" SID "12030" Ports [4, 4] Position [740, 207, 810, 293] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskPromptString "Coefficients (all)|Sub-correlator Ind|Coef/correlator" MaskStyleString "edit,edit,edit" MaskVariables "h=@1;c_ind=@2;N=@3;" MaskTunableValueString "on,on,on" MaskCallbackString "||" MaskEnableString "on,on,on" MaskVisibilityString "on,on,on" MaskToolTipString "on,on,on" MaskInitialization "coef2 = h((c_ind*N+1) : (c_ind + 1)*N);" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "h|4|N" System { Name "C5" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "122" Block { BlockType Inport Name "x" SID "12031" Position [265, 263, 295, 277] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "vin" SID "12032" Position [270, 303, 300, 317] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "12033" Position [270, 458, 300, 472] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "12034" Position [270, 503, 300, 517] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "ASR" SID "12035" Ports [3, 1] Position [445, 260, 490, 320] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Addressable Shift Register" SourceType "Xilinx Addressable Shift Register Block" infoedit "Delay of configurable length. Any element in the delay line can be addressed and driven onto the" " output port.

Hardware notes: This block is implemented using SRL16s. If Virtex-4 or Spartan-3 device is " "used, multiple SRLC16s are cascaded together." infer_latency off depth "length(coef2)" initVector "[0]" en on dbl_ovrd off use_behavioral_HDL off Optimization "Resource" xl_use_area off xl_area "[1 0 0 2 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,401" block_type "addrsr" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,60,3,1,white,blue,0,f8ea6153,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 60 60 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 60 60 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[36.66 3" "6.66 42.66 36.66 42.66 42.66 42.66 36.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[30.66 30.66 36.66 " "36.66 30.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[24.66 24.66 30.66 30.66 24.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[18.66 18.66 24.66 18.66 24.66 24.66 18.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'addr');\ncolor('black');port_label('input',3," "'en');\ncolor('black');port_label('output',1,'q');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Delay" SID "12036" Ports [1, 1] Position [705, 441, 730, 469] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "25,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 " "17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33" " 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('blac" "k');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "12037" Position [210, 280, 300, 300] ZOrder -9 ShowName off GotoTag "ltsCorr_dAddr" TagVisibility "scoped" } Block { BlockType From Name "From1" SID "12038" Position [210, 340, 300, 360] ZOrder -9 ShowName off GotoTag "ltsCorr_cAddr" TagVisibility "scoped" } Block { BlockType From Name "From2" SID "12039" Position [210, 380, 300, 400] ZOrder -9 ShowName off GotoTag "ltsCorr_ld" TagVisibility "scoped" } Block { BlockType Reference Name "Gateway Out1" SID "12040" Ports [1, 1] Position [745, 615, 780, 625] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "12041" Ports [1, 1] Position [745, 630, 780, 640] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "12042" Ports [1, 1] Position [745, 645, 780, 655] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Ld" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "12043" Ports [1, 1] Position [745, 660, 780, 670] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "12044" Ports [1, 1] Position [745, 675, 780, 685] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "12045" Ports [1, 1] Position [745, 570, 780, 580] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X In" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "12046" Ports [1, 1] Position [745, 585, 780, 595] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "12047" Ports [1, 1] Position [745, 600, 780, 610] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X Vin" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType SubSystem Name "MAC" SID "12048" Ports [4, 2] Position [575, 279, 660, 376] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "MAC" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "a" SID "12049" Position [35, 143, 65, 157] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "coeff" SID "12050" Position [35, 108, 65, 122] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "ld" SID "12051" Position [35, 178, 65, 192] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "rst" SID "12052" Position [35, 233, 65, 247] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub" SID "12053" Ports [3, 1] Position [340, 113, 385, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition or Subtraction" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Signed (2's comp)" n_bits "long_cor_acc_n_bits" bin_pt "0" quantization "Truncate" overflow "Flag as error" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[2 0 0 4 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,344" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,3,1,white,blue,0,02f64c57,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('input',3,'su" "b');\ncolor('black');port_label('output',1,'\\bf{a \\pm b}','texmode','on');\nfprintf('','COMMENT: end icon text" "');\n" } Block { BlockType Reference Name "Gateway Out1" SID "12054" Ports [1, 1] Position [475, 450, 510, 460] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out2" SID "12055" Ports [1, 1] Position [475, 465, 510, 475] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out3" SID "12056" Ports [1, 1] Position [475, 480, 510, 490] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out6" SID "12057" Ports [1, 1] Position [475, 405, 510, 415] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out7" SID "12058" Ports [1, 1] Position [475, 420, 510, 430] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out8" SID "12059" Ports [1, 1] Position [475, 435, 510, 445] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "12060" Ports [2, 1] Position [345, 30, 385, 70] BlockMirror on NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,40,2,1,white,blue,0,140cc11c,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'" "q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "12061" Ports [2, 1] Position [465, 110, 495, 210] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,100,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 100 100 0 ],[0.77 0." "82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 100 100 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[54.44 " "54.44 58.44 54.44 58.44 58.44 58.44 54.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[50.44 50.44 54.44 54" ".44 50.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[46.44 46.44 50.44 50.44 46.44 ],[1 1 1 ])" ";\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[42.44 42.44 46.44 42.44 46.44 46.44 42.44 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\nco" "lor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc2" SID "12062" Ports [1, 1] Position [265, 143, 290, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc3" SID "12063" Ports [1, 1] Position [135, 178, 160, 192] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "yn" SID "12064" Position [545, 153, 575, 167] IconDisplay "Port number" } Block { BlockType Outport Name "accrm" SID "12065" Position [520, 288, 550, 302] Port "2" IconDisplay "Port number" } Line { SrcBlock "coeff" SrcPort 1 Points [95, 0; 0, 20; 50, 0] Branch { DstBlock "AddSub" DstPort 2 } Branch { Points [0, 275] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "bc2" SrcPort 1 DstBlock "AddSub" DstPort 3 } Line { SrcBlock "bc3" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "ld" SrcPort 1 Points [45, 0] Branch { DstBlock "bc3" DstPort 1 } Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "Register1" SrcPort 1 Points [-15, 0] DstBlock "AddSub" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 Points [15, 0] Branch { DstBlock "yn" DstPort 1 } Branch { Points [0, 50; 110, 0; 0, 385; -260, 0; 0, -110] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "AddSub" SrcPort 1 Points [0, 0; 5, 0] Branch { Points [40, 0] Branch { DstBlock "Register2" DstPort 1 } Branch { Points [0, -95] DstBlock "Register1" DstPort 1 } Branch { Points [0, 160] DstBlock "accrm" DstPort 1 } } Branch { Points [0, 305] DstBlock "Gateway Out8" DstPort 1 } } Line { SrcBlock "a" SrcPort 1 Points [140, 0] Branch { DstBlock "bc2" DstPort 1 } Branch { Points [0, 275] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "Gateway Out8" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out7" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out6" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out1" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out2" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out3" SrcPort 1 Points [50, 0] } Line { SrcBlock "rst" SrcPort 1 Points [90, 0] Branch { Points [255, 0; 0, -180] DstBlock "Register1" DstPort 2 } Branch { Points [0, 215] DstBlock "Gateway Out1" DstPort 1 } } } } Block { BlockType Reference Name "ROM" SID "12066" Ports [1, 1] Position [440, 328, 490, 372] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/ROM" SourceType "Xilinx Single Port Read-Only Memory Block" depth "length(coef2)" initVector "coef2" distributed_mem "Distributed memory" rst off init_reg "0" en off latency "1" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "longCorr_coef_nbits" bin_pt "longCorr_coef_bp" preci_type "Single" exp_width "8" frac_width "24" dbl_ovrd off optimize "Area" use_rpm off xl_use_area off xl_area "[1 1 0 1 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,308" block_type "sprom" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,44,1,1,white,blue,0,bbc23d60,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 44 44 0 ]);\npatch([11.65 20.32 26.32 32.32 38.32 26.32 17.65 11.65 ],[28.66" " 28.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([17.65 26.32 20.32 11.65 17.65 ],[22.66 22.66 28." "66 28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([11.65 20.32 26.32 17.65 11.65 ],[16.66 16.66 22.66 22.66 16.66 ]" ",[1 1 1 ]);\npatch([17.65 38.32 32.32 26.32 20.32 11.65 17.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'addr');\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end" " icon text');\n" } Block { BlockType Outport Name "x_dly" SID "12067" Position [790, 178, 820, 192] IconDisplay "Port number" } Block { BlockType Outport Name "x_dly_vout" SID "12068" Position [790, 223, 820, 237] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "y" SID "12069" Position [790, 293, 820, 307] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "y_vout" SID "12070" Position [785, 448, 815, 462] Port "4" IconDisplay "Port number" } Line { SrcBlock "From2" SrcPort 1 Points [145, 0] Branch { Points [90, 0] Branch { Points [0, -50] Branch { DstBlock "MAC" DstPort 3 } Branch { Points [0, -90; 160, 0] } } Branch { Points [0, 65] DstBlock "Delay" DstPort 1 } } Branch { Points [0, 260] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "ROM" SrcPort 1 Points [5, 0] Branch { Points [0, -35] DstBlock "MAC" DstPort 2 } Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "MAC" SrcPort 1 Points [0, -5; 15, 0] Branch { DstBlock "y" DstPort 1 } Branch { Points [0, 365] DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "ASR" SrcPort 1 Points [35, 0] Branch { DstBlock "MAC" DstPort 1 } Branch { Points [0, -105] DstBlock "x_dly" DstPort 1 } Branch { Points [0, 330] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "From1" SrcPort 1 Points [5, 0] Branch { DstBlock "ROM" DstPort 1 } Branch { Points [0, 330] DstBlock "Gateway Out5" DstPort 1 } } Line { SrcBlock "From" SrcPort 1 Points [90, 0] Branch { DstBlock "ASR" DstPort 2 } Branch { Points [0, 300] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "x" SrcPort 1 Points [100, 0] Branch { DstBlock "ASR" DstPort 1 } Branch { Points [0, 305] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "vin" SrcPort 1 Points [25, 0] Branch { DstBlock "ASR" DstPort 3 } Branch { Points [0, 100] Branch { Points [0, 195] DstBlock "Gateway Out8" DstPort 1 } Branch { Points [230, 0] DstBlock "MAC" DstPort 4 } } Branch { Points [0, -80] DstBlock "x_dly_vout" DstPort 1 } } Line { SrcBlock "Delay" SrcPort 1 DstBlock "y_vout" DstPort 1 } Line { Name "X Vin" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 Points [150, 0] } Line { Name "ASR Addr" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 Points [150, 0] } Line { Name "X In" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 Points [150, 0] } Line { Name "ASR Out" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 Points [150, 0] } Line { Name "ROM Out" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 Points [150, 0] } Line { Name "Corr Ld" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 Points [150, 0] } Line { Name "Corr Out" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 Points [150, 0] } Line { Name "ROM Addr" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 Points [150, 0] } } } Block { BlockType SubSystem Name "C6" SID "12071" Ports [4, 4] Position [845, 207, 915, 293] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskPromptString "Coefficients (all)|Sub-correlator Ind|Coef/correlator" MaskStyleString "edit,edit,edit" MaskVariables "h=@1;c_ind=@2;N=@3;" MaskTunableValueString "on,on,on" MaskCallbackString "||" MaskEnableString "on,on,on" MaskVisibilityString "on,on,on" MaskToolTipString "on,on,on" MaskInitialization "coef2 = h((c_ind*N+1) : (c_ind + 1)*N);" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "h|5|N" System { Name "C6" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "122" Block { BlockType Inport Name "x" SID "12072" Position [265, 263, 295, 277] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "vin" SID "12073" Position [270, 303, 300, 317] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "12074" Position [270, 458, 300, 472] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "12075" Position [270, 503, 300, 517] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "ASR" SID "12076" Ports [3, 1] Position [445, 260, 490, 320] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Addressable Shift Register" SourceType "Xilinx Addressable Shift Register Block" infoedit "Delay of configurable length. Any element in the delay line can be addressed and driven onto the" " output port.

Hardware notes: This block is implemented using SRL16s. If Virtex-4 or Spartan-3 device is " "used, multiple SRLC16s are cascaded together." infer_latency off depth "length(coef2)" initVector "[0]" en on dbl_ovrd off use_behavioral_HDL off Optimization "Resource" xl_use_area off xl_area "[1 0 0 2 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,401" block_type "addrsr" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,60,3,1,white,blue,0,f8ea6153,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 60 60 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 60 60 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[36.66 3" "6.66 42.66 36.66 42.66 42.66 42.66 36.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[30.66 30.66 36.66 " "36.66 30.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[24.66 24.66 30.66 30.66 24.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[18.66 18.66 24.66 18.66 24.66 24.66 18.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'addr');\ncolor('black');port_label('input',3," "'en');\ncolor('black');port_label('output',1,'q');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Delay" SID "12077" Ports [1, 1] Position [705, 441, 730, 469] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "25,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 " "17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33" " 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('blac" "k');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "12078" Position [210, 280, 300, 300] ZOrder -9 ShowName off GotoTag "ltsCorr_dAddr" TagVisibility "scoped" } Block { BlockType From Name "From1" SID "12079" Position [210, 340, 300, 360] ZOrder -9 ShowName off GotoTag "ltsCorr_cAddr" TagVisibility "scoped" } Block { BlockType From Name "From2" SID "12080" Position [210, 380, 300, 400] ZOrder -9 ShowName off GotoTag "ltsCorr_ld" TagVisibility "scoped" } Block { BlockType Reference Name "Gateway Out1" SID "12081" Ports [1, 1] Position [745, 615, 780, 625] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "12082" Ports [1, 1] Position [745, 630, 780, 640] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "12083" Ports [1, 1] Position [745, 645, 780, 655] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Ld" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "12084" Ports [1, 1] Position [745, 660, 780, 670] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "12085" Ports [1, 1] Position [745, 675, 780, 685] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "12086" Ports [1, 1] Position [745, 570, 780, 580] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X In" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "12087" Ports [1, 1] Position [745, 585, 780, 595] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "12088" Ports [1, 1] Position [745, 600, 780, 610] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X Vin" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType SubSystem Name "MAC" SID "12089" Ports [4, 2] Position [575, 279, 660, 376] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "MAC" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "a" SID "12090" Position [35, 143, 65, 157] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "coeff" SID "12091" Position [35, 108, 65, 122] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "ld" SID "12092" Position [35, 178, 65, 192] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "rst" SID "12093" Position [35, 233, 65, 247] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub" SID "12094" Ports [3, 1] Position [340, 113, 385, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition or Subtraction" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Signed (2's comp)" n_bits "long_cor_acc_n_bits" bin_pt "0" quantization "Truncate" overflow "Flag as error" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[2 0 0 4 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,344" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,3,1,white,blue,0,02f64c57,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('input',3,'su" "b');\ncolor('black');port_label('output',1,'\\bf{a \\pm b}','texmode','on');\nfprintf('','COMMENT: end icon text" "');\n" } Block { BlockType Reference Name "Gateway Out1" SID "12095" Ports [1, 1] Position [475, 450, 510, 460] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out2" SID "12096" Ports [1, 1] Position [475, 465, 510, 475] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out3" SID "12097" Ports [1, 1] Position [475, 480, 510, 490] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out6" SID "12098" Ports [1, 1] Position [475, 405, 510, 415] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out7" SID "12099" Ports [1, 1] Position [475, 420, 510, 430] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out8" SID "12100" Ports [1, 1] Position [475, 435, 510, 445] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "12101" Ports [2, 1] Position [345, 30, 385, 70] BlockMirror on NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,40,2,1,white,blue,0,140cc11c,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'" "q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "12102" Ports [2, 1] Position [465, 110, 495, 210] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,100,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 100 100 0 ],[0.77 0." "82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 100 100 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[54.44 " "54.44 58.44 54.44 58.44 58.44 58.44 54.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[50.44 50.44 54.44 54" ".44 50.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[46.44 46.44 50.44 50.44 46.44 ],[1 1 1 ])" ";\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[42.44 42.44 46.44 42.44 46.44 46.44 42.44 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\nco" "lor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc2" SID "12103" Ports [1, 1] Position [265, 143, 290, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc3" SID "12104" Ports [1, 1] Position [135, 178, 160, 192] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "yn" SID "12105" Position [545, 153, 575, 167] IconDisplay "Port number" } Block { BlockType Outport Name "accrm" SID "12106" Position [520, 288, 550, 302] Port "2" IconDisplay "Port number" } Line { SrcBlock "rst" SrcPort 1 Points [90, 0] Branch { Points [0, 215] DstBlock "Gateway Out1" DstPort 1 } Branch { Points [255, 0; 0, -180] DstBlock "Register1" DstPort 2 } } Line { SrcBlock "Gateway Out3" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out2" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out1" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out6" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out7" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out8" SrcPort 1 Points [50, 0] } Line { SrcBlock "a" SrcPort 1 Points [140, 0] Branch { Points [0, 275] DstBlock "Gateway Out7" DstPort 1 } Branch { DstBlock "bc2" DstPort 1 } } Line { SrcBlock "AddSub" SrcPort 1 Points [0, 0; 5, 0] Branch { Points [0, 305] DstBlock "Gateway Out8" DstPort 1 } Branch { Points [40, 0] Branch { Points [0, 160] DstBlock "accrm" DstPort 1 } Branch { Points [0, -95] DstBlock "Register1" DstPort 1 } Branch { DstBlock "Register2" DstPort 1 } } } Line { SrcBlock "Register2" SrcPort 1 Points [15, 0] Branch { Points [0, 50; 110, 0; 0, 385; -260, 0; 0, -110] DstBlock "Gateway Out3" DstPort 1 } Branch { DstBlock "yn" DstPort 1 } } Line { SrcBlock "Register1" SrcPort 1 Points [-15, 0] DstBlock "AddSub" DstPort 1 } Line { SrcBlock "ld" SrcPort 1 Points [45, 0] Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } Branch { DstBlock "bc3" DstPort 1 } } Line { SrcBlock "bc3" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "bc2" SrcPort 1 DstBlock "AddSub" DstPort 3 } Line { SrcBlock "coeff" SrcPort 1 Points [95, 0; 0, 20; 50, 0] Branch { Points [0, 275] DstBlock "Gateway Out6" DstPort 1 } Branch { DstBlock "AddSub" DstPort 2 } } } } Block { BlockType Reference Name "ROM" SID "12107" Ports [1, 1] Position [440, 328, 490, 372] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/ROM" SourceType "Xilinx Single Port Read-Only Memory Block" depth "length(coef2)" initVector "coef2" distributed_mem "Distributed memory" rst off init_reg "0" en off latency "1" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "longCorr_coef_nbits" bin_pt "longCorr_coef_bp" preci_type "Single" exp_width "8" frac_width "24" dbl_ovrd off optimize "Area" use_rpm off xl_use_area off xl_area "[1 1 0 1 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,308" block_type "sprom" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,44,1,1,white,blue,0,bbc23d60,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 44 44 0 ]);\npatch([11.65 20.32 26.32 32.32 38.32 26.32 17.65 11.65 ],[28.66" " 28.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([17.65 26.32 20.32 11.65 17.65 ],[22.66 22.66 28." "66 28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([11.65 20.32 26.32 17.65 11.65 ],[16.66 16.66 22.66 22.66 16.66 ]" ",[1 1 1 ]);\npatch([17.65 38.32 32.32 26.32 20.32 11.65 17.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'addr');\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end" " icon text');\n" } Block { BlockType Outport Name "x_dly" SID "12108" Position [790, 178, 820, 192] IconDisplay "Port number" } Block { BlockType Outport Name "x_dly_vout" SID "12109" Position [790, 223, 820, 237] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "y" SID "12110" Position [790, 293, 820, 307] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "y_vout" SID "12111" Position [785, 448, 815, 462] Port "4" IconDisplay "Port number" } Line { Name "ROM Addr" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 Points [150, 0] } Line { Name "Corr Out" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 Points [150, 0] } Line { Name "Corr Ld" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 Points [150, 0] } Line { Name "ROM Out" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 Points [150, 0] } Line { Name "ASR Out" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 Points [150, 0] } Line { Name "X In" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 Points [150, 0] } Line { Name "ASR Addr" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 Points [150, 0] } Line { Name "X Vin" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 Points [150, 0] } Line { SrcBlock "Delay" SrcPort 1 DstBlock "y_vout" DstPort 1 } Line { SrcBlock "vin" SrcPort 1 Points [25, 0] Branch { Points [0, -80] DstBlock "x_dly_vout" DstPort 1 } Branch { Points [0, 100] Branch { Points [230, 0] DstBlock "MAC" DstPort 4 } Branch { Points [0, 195] DstBlock "Gateway Out8" DstPort 1 } } Branch { DstBlock "ASR" DstPort 3 } } Line { SrcBlock "x" SrcPort 1 Points [100, 0] Branch { Points [0, 305] DstBlock "Gateway Out6" DstPort 1 } Branch { DstBlock "ASR" DstPort 1 } } Line { SrcBlock "From" SrcPort 1 Points [90, 0] Branch { Points [0, 300] DstBlock "Gateway Out7" DstPort 1 } Branch { DstBlock "ASR" DstPort 2 } } Line { SrcBlock "From1" SrcPort 1 Points [5, 0] Branch { Points [0, 330] DstBlock "Gateway Out5" DstPort 1 } Branch { DstBlock "ROM" DstPort 1 } } Line { SrcBlock "ASR" SrcPort 1 Points [35, 0] Branch { Points [0, 330] DstBlock "Gateway Out1" DstPort 1 } Branch { Points [0, -105] DstBlock "x_dly" DstPort 1 } Branch { DstBlock "MAC" DstPort 1 } } Line { SrcBlock "MAC" SrcPort 1 Points [0, -5; 15, 0] Branch { Points [0, 365] DstBlock "Gateway Out4" DstPort 1 } Branch { DstBlock "y" DstPort 1 } } Line { SrcBlock "ROM" SrcPort 1 Points [5, 0] Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } Branch { Points [0, -35] DstBlock "MAC" DstPort 2 } } Line { SrcBlock "From2" SrcPort 1 Points [145, 0] Branch { Points [0, 260] DstBlock "Gateway Out3" DstPort 1 } Branch { Points [90, 0] Branch { Points [0, 65] DstBlock "Delay" DstPort 1 } Branch { Points [0, -50] Branch { Points [0, -90; 160, 0] } Branch { DstBlock "MAC" DstPort 3 } } } } } } Block { BlockType SubSystem Name "C7" SID "12112" Ports [4, 4] Position [950, 207, 1020, 293] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskPromptString "Coefficients (all)|Sub-correlator Ind|Coef/correlator" MaskStyleString "edit,edit,edit" MaskVariables "h=@1;c_ind=@2;N=@3;" MaskTunableValueString "on,on,on" MaskCallbackString "||" MaskEnableString "on,on,on" MaskVisibilityString "on,on,on" MaskToolTipString "on,on,on" MaskInitialization "coef2 = h((c_ind*N+1) : (c_ind + 1)*N);" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "h|6|N" System { Name "C7" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "122" Block { BlockType Inport Name "x" SID "12113" Position [265, 263, 295, 277] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "vin" SID "12114" Position [270, 303, 300, 317] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "12115" Position [270, 458, 300, 472] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "12116" Position [270, 503, 300, 517] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "ASR" SID "12117" Ports [3, 1] Position [445, 260, 490, 320] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Addressable Shift Register" SourceType "Xilinx Addressable Shift Register Block" infoedit "Delay of configurable length. Any element in the delay line can be addressed and driven onto the" " output port.

Hardware notes: This block is implemented using SRL16s. If Virtex-4 or Spartan-3 device is " "used, multiple SRLC16s are cascaded together." infer_latency off depth "length(coef2)" initVector "[0]" en on dbl_ovrd off use_behavioral_HDL off Optimization "Resource" xl_use_area off xl_area "[1 0 0 2 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,401" block_type "addrsr" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,60,3,1,white,blue,0,f8ea6153,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 60 60 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 60 60 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[36.66 3" "6.66 42.66 36.66 42.66 42.66 42.66 36.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[30.66 30.66 36.66 " "36.66 30.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[24.66 24.66 30.66 30.66 24.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[18.66 18.66 24.66 18.66 24.66 24.66 18.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'addr');\ncolor('black');port_label('input',3," "'en');\ncolor('black');port_label('output',1,'q');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Delay" SID "12118" Ports [1, 1] Position [705, 441, 730, 469] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "25,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 " "17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33" " 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('blac" "k');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "12119" Position [210, 280, 300, 300] ZOrder -9 ShowName off GotoTag "ltsCorr_dAddr" TagVisibility "scoped" } Block { BlockType From Name "From1" SID "12120" Position [210, 340, 300, 360] ZOrder -9 ShowName off GotoTag "ltsCorr_cAddr" TagVisibility "scoped" } Block { BlockType From Name "From2" SID "12121" Position [210, 380, 300, 400] ZOrder -9 ShowName off GotoTag "ltsCorr_ld" TagVisibility "scoped" } Block { BlockType Reference Name "Gateway Out1" SID "12122" Ports [1, 1] Position [745, 615, 780, 625] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "12123" Ports [1, 1] Position [745, 630, 780, 640] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "12124" Ports [1, 1] Position [745, 645, 780, 655] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Ld" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "12125" Ports [1, 1] Position [745, 660, 780, 670] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "12126" Ports [1, 1] Position [745, 675, 780, 685] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "12127" Ports [1, 1] Position [745, 570, 780, 580] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X In" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "12128" Ports [1, 1] Position [745, 585, 780, 595] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "12129" Ports [1, 1] Position [745, 600, 780, 610] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X Vin" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType SubSystem Name "MAC" SID "12130" Ports [4, 2] Position [575, 279, 660, 376] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "MAC" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "a" SID "12131" Position [35, 143, 65, 157] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "coeff" SID "12132" Position [35, 108, 65, 122] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "ld" SID "12133" Position [35, 178, 65, 192] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "rst" SID "12134" Position [35, 233, 65, 247] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub" SID "12135" Ports [3, 1] Position [340, 113, 385, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition or Subtraction" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Signed (2's comp)" n_bits "long_cor_acc_n_bits" bin_pt "0" quantization "Truncate" overflow "Flag as error" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[2 0 0 4 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,344" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,3,1,white,blue,0,02f64c57,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('input',3,'su" "b');\ncolor('black');port_label('output',1,'\\bf{a \\pm b}','texmode','on');\nfprintf('','COMMENT: end icon text" "');\n" } Block { BlockType Reference Name "Gateway Out1" SID "12136" Ports [1, 1] Position [475, 450, 510, 460] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out2" SID "12137" Ports [1, 1] Position [475, 465, 510, 475] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out3" SID "12138" Ports [1, 1] Position [475, 480, 510, 490] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out6" SID "12139" Ports [1, 1] Position [475, 405, 510, 415] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out7" SID "12140" Ports [1, 1] Position [475, 420, 510, 430] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out8" SID "12141" Ports [1, 1] Position [475, 435, 510, 445] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "12142" Ports [2, 1] Position [345, 30, 385, 70] BlockMirror on NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,40,2,1,white,blue,0,140cc11c,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'" "q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "12143" Ports [2, 1] Position [465, 110, 495, 210] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,100,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 100 100 0 ],[0.77 0." "82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 100 100 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[54.44 " "54.44 58.44 54.44 58.44 58.44 58.44 54.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[50.44 50.44 54.44 54" ".44 50.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[46.44 46.44 50.44 50.44 46.44 ],[1 1 1 ])" ";\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[42.44 42.44 46.44 42.44 46.44 46.44 42.44 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\nco" "lor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc2" SID "12144" Ports [1, 1] Position [265, 143, 290, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc3" SID "12145" Ports [1, 1] Position [135, 178, 160, 192] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "yn" SID "12146" Position [545, 153, 575, 167] IconDisplay "Port number" } Block { BlockType Outport Name "accrm" SID "12147" Position [520, 288, 550, 302] Port "2" IconDisplay "Port number" } Line { SrcBlock "coeff" SrcPort 1 Points [95, 0; 0, 20; 50, 0] Branch { DstBlock "AddSub" DstPort 2 } Branch { Points [0, 275] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "bc2" SrcPort 1 DstBlock "AddSub" DstPort 3 } Line { SrcBlock "bc3" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "ld" SrcPort 1 Points [45, 0] Branch { DstBlock "bc3" DstPort 1 } Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "Register1" SrcPort 1 Points [-15, 0] DstBlock "AddSub" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 Points [15, 0] Branch { DstBlock "yn" DstPort 1 } Branch { Points [0, 50; 110, 0; 0, 385; -260, 0; 0, -110] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "AddSub" SrcPort 1 Points [0, 0; 5, 0] Branch { Points [40, 0] Branch { DstBlock "Register2" DstPort 1 } Branch { Points [0, -95] DstBlock "Register1" DstPort 1 } Branch { Points [0, 160] DstBlock "accrm" DstPort 1 } } Branch { Points [0, 305] DstBlock "Gateway Out8" DstPort 1 } } Line { SrcBlock "a" SrcPort 1 Points [140, 0] Branch { DstBlock "bc2" DstPort 1 } Branch { Points [0, 275] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "Gateway Out8" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out7" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out6" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out1" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out2" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out3" SrcPort 1 Points [50, 0] } Line { SrcBlock "rst" SrcPort 1 Points [90, 0] Branch { Points [255, 0; 0, -180] DstBlock "Register1" DstPort 2 } Branch { Points [0, 215] DstBlock "Gateway Out1" DstPort 1 } } } } Block { BlockType Reference Name "ROM" SID "12148" Ports [1, 1] Position [440, 328, 490, 372] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/ROM" SourceType "Xilinx Single Port Read-Only Memory Block" depth "length(coef2)" initVector "coef2" distributed_mem "Distributed memory" rst off init_reg "0" en off latency "1" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "longCorr_coef_nbits" bin_pt "longCorr_coef_bp" preci_type "Single" exp_width "8" frac_width "24" dbl_ovrd off optimize "Area" use_rpm off xl_use_area off xl_area "[1 1 0 1 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,308" block_type "sprom" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,44,1,1,white,blue,0,bbc23d60,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 44 44 0 ]);\npatch([11.65 20.32 26.32 32.32 38.32 26.32 17.65 11.65 ],[28.66" " 28.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([17.65 26.32 20.32 11.65 17.65 ],[22.66 22.66 28." "66 28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([11.65 20.32 26.32 17.65 11.65 ],[16.66 16.66 22.66 22.66 16.66 ]" ",[1 1 1 ]);\npatch([17.65 38.32 32.32 26.32 20.32 11.65 17.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'addr');\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end" " icon text');\n" } Block { BlockType Outport Name "x_dly" SID "12149" Position [790, 178, 820, 192] IconDisplay "Port number" } Block { BlockType Outport Name "x_dly_vout" SID "12150" Position [790, 223, 820, 237] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "y" SID "12151" Position [790, 293, 820, 307] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "y_vout" SID "12152" Position [785, 448, 815, 462] Port "4" IconDisplay "Port number" } Line { SrcBlock "From2" SrcPort 1 Points [145, 0] Branch { Points [90, 0] Branch { Points [0, -50] Branch { DstBlock "MAC" DstPort 3 } Branch { Points [0, -90; 160, 0] } } Branch { Points [0, 65] DstBlock "Delay" DstPort 1 } } Branch { Points [0, 260] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "ROM" SrcPort 1 Points [5, 0] Branch { Points [0, -35] DstBlock "MAC" DstPort 2 } Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "MAC" SrcPort 1 Points [0, -5; 15, 0] Branch { DstBlock "y" DstPort 1 } Branch { Points [0, 365] DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "ASR" SrcPort 1 Points [35, 0] Branch { DstBlock "MAC" DstPort 1 } Branch { Points [0, -105] DstBlock "x_dly" DstPort 1 } Branch { Points [0, 330] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "From1" SrcPort 1 Points [5, 0] Branch { DstBlock "ROM" DstPort 1 } Branch { Points [0, 330] DstBlock "Gateway Out5" DstPort 1 } } Line { SrcBlock "From" SrcPort 1 Points [90, 0] Branch { DstBlock "ASR" DstPort 2 } Branch { Points [0, 300] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "x" SrcPort 1 Points [100, 0] Branch { DstBlock "ASR" DstPort 1 } Branch { Points [0, 305] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "vin" SrcPort 1 Points [25, 0] Branch { DstBlock "ASR" DstPort 3 } Branch { Points [0, 100] Branch { Points [0, 195] DstBlock "Gateway Out8" DstPort 1 } Branch { Points [230, 0] DstBlock "MAC" DstPort 4 } } Branch { Points [0, -80] DstBlock "x_dly_vout" DstPort 1 } } Line { SrcBlock "Delay" SrcPort 1 DstBlock "y_vout" DstPort 1 } Line { Name "X Vin" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 Points [150, 0] } Line { Name "ASR Addr" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 Points [150, 0] } Line { Name "X In" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 Points [150, 0] } Line { Name "ASR Out" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 Points [150, 0] } Line { Name "ROM Out" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 Points [150, 0] } Line { Name "Corr Ld" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 Points [150, 0] } Line { Name "Corr Out" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 Points [150, 0] } Line { Name "ROM Addr" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 Points [150, 0] } } } Block { BlockType SubSystem Name "C8" SID "12153" Ports [4, 4] Position [1060, 207, 1130, 293] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskPromptString "Coefficients (all)|Sub-correlator Ind|Coef/correlator" MaskStyleString "edit,edit,edit" MaskVariables "h=@1;c_ind=@2;N=@3;" MaskTunableValueString "on,on,on" MaskCallbackString "||" MaskEnableString "on,on,on" MaskVisibilityString "on,on,on" MaskToolTipString "on,on,on" MaskInitialization "coef2 = h((c_ind*N+1) : (c_ind + 1)*N);" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "h|7|N" System { Name "C8" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "122" Block { BlockType Inport Name "x" SID "12154" Position [265, 263, 295, 277] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "vin" SID "12155" Position [270, 303, 300, 317] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "12156" Position [270, 458, 300, 472] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "12157" Position [270, 503, 300, 517] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "ASR" SID "12158" Ports [3, 1] Position [445, 260, 490, 320] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Addressable Shift Register" SourceType "Xilinx Addressable Shift Register Block" infoedit "Delay of configurable length. Any element in the delay line can be addressed and driven onto the" " output port.

Hardware notes: This block is implemented using SRL16s. If Virtex-4 or Spartan-3 device is " "used, multiple SRLC16s are cascaded together." infer_latency off depth "length(coef2)" initVector "[0]" en on dbl_ovrd off use_behavioral_HDL off Optimization "Resource" xl_use_area off xl_area "[1 0 0 2 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,401" block_type "addrsr" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,60,3,1,white,blue,0,f8ea6153,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 60 60 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 60 60 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[36.66 3" "6.66 42.66 36.66 42.66 42.66 42.66 36.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[30.66 30.66 36.66 " "36.66 30.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[24.66 24.66 30.66 30.66 24.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[18.66 18.66 24.66 18.66 24.66 24.66 18.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'addr');\ncolor('black');port_label('input',3," "'en');\ncolor('black');port_label('output',1,'q');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Delay" SID "12159" Ports [1, 1] Position [705, 441, 730, 469] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "25,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 " "17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33" " 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('blac" "k');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "12160" Position [210, 280, 300, 300] ZOrder -9 ShowName off GotoTag "ltsCorr_dAddr" TagVisibility "scoped" } Block { BlockType From Name "From1" SID "12161" Position [210, 340, 300, 360] ZOrder -9 ShowName off GotoTag "ltsCorr_cAddr" TagVisibility "scoped" } Block { BlockType From Name "From2" SID "12162" Position [210, 380, 300, 400] ZOrder -9 ShowName off GotoTag "ltsCorr_ld" TagVisibility "scoped" } Block { BlockType Reference Name "Gateway Out1" SID "12163" Ports [1, 1] Position [745, 615, 780, 625] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "12164" Ports [1, 1] Position [745, 630, 780, 640] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "12165" Ports [1, 1] Position [745, 645, 780, 655] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Ld" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "12166" Ports [1, 1] Position [745, 660, 780, 670] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "12167" Ports [1, 1] Position [745, 675, 780, 685] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "12168" Ports [1, 1] Position [745, 570, 780, 580] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X In" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "12169" Ports [1, 1] Position [745, 585, 780, 595] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "12170" Ports [1, 1] Position [745, 600, 780, 610] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X Vin" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType SubSystem Name "MAC" SID "12171" Ports [4, 2] Position [575, 279, 660, 376] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "MAC" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "a" SID "12172" Position [35, 143, 65, 157] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "coeff" SID "12173" Position [35, 108, 65, 122] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "ld" SID "12174" Position [35, 178, 65, 192] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "rst" SID "12175" Position [35, 233, 65, 247] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub" SID "12176" Ports [3, 1] Position [340, 113, 385, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition or Subtraction" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Signed (2's comp)" n_bits "long_cor_acc_n_bits" bin_pt "0" quantization "Truncate" overflow "Flag as error" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[2 0 0 4 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,344" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,3,1,white,blue,0,02f64c57,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('input',3,'su" "b');\ncolor('black');port_label('output',1,'\\bf{a \\pm b}','texmode','on');\nfprintf('','COMMENT: end icon text" "');\n" } Block { BlockType Reference Name "Gateway Out1" SID "12177" Ports [1, 1] Position [475, 450, 510, 460] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out2" SID "12178" Ports [1, 1] Position [475, 465, 510, 475] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out3" SID "12179" Ports [1, 1] Position [475, 480, 510, 490] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out6" SID "12180" Ports [1, 1] Position [475, 405, 510, 415] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out7" SID "12181" Ports [1, 1] Position [475, 420, 510, 430] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out8" SID "12182" Ports [1, 1] Position [475, 435, 510, 445] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "12183" Ports [2, 1] Position [345, 30, 385, 70] BlockMirror on NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,40,2,1,white,blue,0,140cc11c,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'" "q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "12184" Ports [2, 1] Position [465, 110, 495, 210] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,100,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 100 100 0 ],[0.77 0." "82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 100 100 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[54.44 " "54.44 58.44 54.44 58.44 58.44 58.44 54.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[50.44 50.44 54.44 54" ".44 50.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[46.44 46.44 50.44 50.44 46.44 ],[1 1 1 ])" ";\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[42.44 42.44 46.44 42.44 46.44 46.44 42.44 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\nco" "lor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc2" SID "12185" Ports [1, 1] Position [265, 143, 290, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc3" SID "12186" Ports [1, 1] Position [135, 178, 160, 192] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "yn" SID "12187" Position [545, 153, 575, 167] IconDisplay "Port number" } Block { BlockType Outport Name "accrm" SID "12188" Position [520, 288, 550, 302] Port "2" IconDisplay "Port number" } Line { SrcBlock "rst" SrcPort 1 Points [90, 0] Branch { Points [0, 215] DstBlock "Gateway Out1" DstPort 1 } Branch { Points [255, 0; 0, -180] DstBlock "Register1" DstPort 2 } } Line { SrcBlock "Gateway Out3" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out2" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out1" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out6" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out7" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out8" SrcPort 1 Points [50, 0] } Line { SrcBlock "a" SrcPort 1 Points [140, 0] Branch { Points [0, 275] DstBlock "Gateway Out7" DstPort 1 } Branch { DstBlock "bc2" DstPort 1 } } Line { SrcBlock "AddSub" SrcPort 1 Points [0, 0; 5, 0] Branch { Points [0, 305] DstBlock "Gateway Out8" DstPort 1 } Branch { Points [40, 0] Branch { Points [0, 160] DstBlock "accrm" DstPort 1 } Branch { Points [0, -95] DstBlock "Register1" DstPort 1 } Branch { DstBlock "Register2" DstPort 1 } } } Line { SrcBlock "Register2" SrcPort 1 Points [15, 0] Branch { Points [0, 50; 110, 0; 0, 385; -260, 0; 0, -110] DstBlock "Gateway Out3" DstPort 1 } Branch { DstBlock "yn" DstPort 1 } } Line { SrcBlock "Register1" SrcPort 1 Points [-15, 0] DstBlock "AddSub" DstPort 1 } Line { SrcBlock "ld" SrcPort 1 Points [45, 0] Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } Branch { DstBlock "bc3" DstPort 1 } } Line { SrcBlock "bc3" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "bc2" SrcPort 1 DstBlock "AddSub" DstPort 3 } Line { SrcBlock "coeff" SrcPort 1 Points [95, 0; 0, 20; 50, 0] Branch { Points [0, 275] DstBlock "Gateway Out6" DstPort 1 } Branch { DstBlock "AddSub" DstPort 2 } } } } Block { BlockType Reference Name "ROM" SID "12189" Ports [1, 1] Position [440, 328, 490, 372] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/ROM" SourceType "Xilinx Single Port Read-Only Memory Block" depth "length(coef2)" initVector "coef2" distributed_mem "Distributed memory" rst off init_reg "0" en off latency "1" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "longCorr_coef_nbits" bin_pt "longCorr_coef_bp" preci_type "Single" exp_width "8" frac_width "24" dbl_ovrd off optimize "Area" use_rpm off xl_use_area off xl_area "[1 1 0 1 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,308" block_type "sprom" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,44,1,1,white,blue,0,bbc23d60,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 44 44 0 ]);\npatch([11.65 20.32 26.32 32.32 38.32 26.32 17.65 11.65 ],[28.66" " 28.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([17.65 26.32 20.32 11.65 17.65 ],[22.66 22.66 28." "66 28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([11.65 20.32 26.32 17.65 11.65 ],[16.66 16.66 22.66 22.66 16.66 ]" ",[1 1 1 ]);\npatch([17.65 38.32 32.32 26.32 20.32 11.65 17.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'addr');\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end" " icon text');\n" } Block { BlockType Outport Name "x_dly" SID "12190" Position [790, 178, 820, 192] IconDisplay "Port number" } Block { BlockType Outport Name "x_dly_vout" SID "12191" Position [790, 223, 820, 237] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "y" SID "12192" Position [790, 293, 820, 307] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "y_vout" SID "12193" Position [785, 448, 815, 462] Port "4" IconDisplay "Port number" } Line { Name "ROM Addr" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 Points [150, 0] } Line { Name "Corr Out" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 Points [150, 0] } Line { Name "Corr Ld" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 Points [150, 0] } Line { Name "ROM Out" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 Points [150, 0] } Line { Name "ASR Out" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 Points [150, 0] } Line { Name "X In" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 Points [150, 0] } Line { Name "ASR Addr" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 Points [150, 0] } Line { Name "X Vin" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 Points [150, 0] } Line { SrcBlock "Delay" SrcPort 1 DstBlock "y_vout" DstPort 1 } Line { SrcBlock "vin" SrcPort 1 Points [25, 0] Branch { Points [0, -80] DstBlock "x_dly_vout" DstPort 1 } Branch { Points [0, 100] Branch { Points [230, 0] DstBlock "MAC" DstPort 4 } Branch { Points [0, 195] DstBlock "Gateway Out8" DstPort 1 } } Branch { DstBlock "ASR" DstPort 3 } } Line { SrcBlock "x" SrcPort 1 Points [100, 0] Branch { Points [0, 305] DstBlock "Gateway Out6" DstPort 1 } Branch { DstBlock "ASR" DstPort 1 } } Line { SrcBlock "From" SrcPort 1 Points [90, 0] Branch { Points [0, 300] DstBlock "Gateway Out7" DstPort 1 } Branch { DstBlock "ASR" DstPort 2 } } Line { SrcBlock "From1" SrcPort 1 Points [5, 0] Branch { Points [0, 330] DstBlock "Gateway Out5" DstPort 1 } Branch { DstBlock "ROM" DstPort 1 } } Line { SrcBlock "ASR" SrcPort 1 Points [35, 0] Branch { Points [0, 330] DstBlock "Gateway Out1" DstPort 1 } Branch { Points [0, -105] DstBlock "x_dly" DstPort 1 } Branch { DstBlock "MAC" DstPort 1 } } Line { SrcBlock "MAC" SrcPort 1 Points [0, -5; 15, 0] Branch { Points [0, 365] DstBlock "Gateway Out4" DstPort 1 } Branch { DstBlock "y" DstPort 1 } } Line { SrcBlock "ROM" SrcPort 1 Points [5, 0] Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } Branch { Points [0, -35] DstBlock "MAC" DstPort 2 } } Line { SrcBlock "From2" SrcPort 1 Points [145, 0] Branch { Points [0, 260] DstBlock "Gateway Out3" DstPort 1 } Branch { Points [90, 0] Branch { Points [0, 65] DstBlock "Delay" DstPort 1 } Branch { Points [0, -50] Branch { Points [0, -90; 160, 0] } Branch { DstBlock "MAC" DstPort 3 } } } } } } Block { BlockType Reference Name "Gateway Out1" SID "12194" Ports [1, 1] Position [1195, 75, 1230, 85] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out10" SID "12195" Ports [1, 1] Position [1195, 120, 1230, 130] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out11" SID "12196" Ports [1, 1] Position [1195, 135, 1230, 145] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out12" SID "12197" Ports [1, 1] Position [1195, 150, 1230, 160] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out13" SID "12198" Ports [1, 1] Position [1195, 165, 1230, 175] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out14" SID "12199" Ports [1, 1] Position [1225, 180, 1260, 190] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out2" SID "12200" Ports [1, 1] Position [740, 720, 775, 730] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out3" SID "12201" Ports [1, 1] Position [740, 690, 775, 700] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out4" SID "12202" Ports [1, 1] Position [740, 705, 775, 715] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out5" SID "12203" Ports [1, 1] Position [740, 735, 775, 745] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out6" SID "12204" Ports [1, 1] Position [1195, 45, 1230, 55] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out7" SID "12205" Ports [1, 1] Position [1195, 60, 1230, 70] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out8" SID "12206" Ports [1, 1] Position [1195, 90, 1230, 100] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out9" SID "12207" Ports [1, 1] Position [1195, 105, 1230, 115] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Outport Name "y" SID "12208" Position [1290, 568, 1320, 582] IconDisplay "Port number" } Block { BlockType Outport Name "y_vout" SID "12209" Position [1290, 523, 1320, 537] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "x_dly" SID "12210" Position [1260, 213, 1290, 227] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "x_dly_vout" SID "12211" Position [1260, 253, 1290, 267] Port "4" IconDisplay "Port number" } Line { SrcBlock "x" SrcPort 1 Points [210, 0] Branch { DstBlock "C1" DstPort 1 } Branch { Points [0, 475] DstBlock "Gateway Out3" DstPort 1 } Branch { Points [0, -170] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "AddSub12" SrcPort 1 DstBlock "AddSub13" DstPort 2 } Line { SrcBlock "AddSub5" SrcPort 1 Points [0, 35] DstBlock "AddSub13" DstPort 1 } Line { SrcBlock "Gateway Out4" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out3" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out5" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out2" SrcPort 1 Points [50, 0] } Line { Points [780, 755; 50, 0] } Line { SrcBlock "x_valid" SrcPort 1 Points [200, 0] Branch { Points [0, -20] DstBlock "C1" DstPort 2 } Branch { Points [0, 450] DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "C1" SrcPort 1 DstBlock "C2" DstPort 1 } Line { SrcBlock "C1" SrcPort 2 DstBlock "C2" DstPort 2 } Line { SrcBlock "C2" SrcPort 1 DstBlock "C3" DstPort 1 } Line { SrcBlock "C2" SrcPort 2 DstBlock "C3" DstPort 2 } Line { SrcBlock "C2" SrcPort 3 Points [20, 0] Branch { DstBlock "AddSub5" DstPort 2 } Branch { Points [0, -180] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "C1" SrcPort 3 Points [15, 0] Branch { Points [0, 55] Branch { Points [0, 5; 95, 0] DstBlock "AddSub5" DstPort 1 } Branch { Points [0, 410] DstBlock "Gateway Out2" DstPort 1 } } Branch { Points [0, -195] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "C3" SrcPort 1 DstBlock "C4" DstPort 1 } Line { SrcBlock "C3" SrcPort 2 DstBlock "C4" DstPort 2 } Line { SrcBlock "C3" SrcPort 3 Points [20, 0] Branch { Points [0, 65; 80, 0] DstBlock "AddSub12" DstPort 1 } Branch { Points [0, -165] DstBlock "Gateway Out8" DstPort 1 } } Line { SrcBlock "C4" SrcPort 1 DstBlock "C5" DstPort 1 } Line { SrcBlock "C4" SrcPort 2 DstBlock "C5" DstPort 2 } Line { SrcBlock "C4" SrcPort 3 Points [15, 0] Branch { DstBlock "AddSub12" DstPort 2 } Branch { Points [0, -150] DstBlock "Gateway Out9" DstPort 1 } } Line { SrcBlock "C5" SrcPort 1 DstBlock "C6" DstPort 1 } Line { SrcBlock "C5" SrcPort 2 DstBlock "C6" DstPort 2 } Line { SrcBlock "C6" SrcPort 1 DstBlock "C7" DstPort 1 } Line { SrcBlock "C6" SrcPort 2 DstBlock "C7" DstPort 2 } Line { SrcBlock "C7" SrcPort 1 DstBlock "C8" DstPort 1 } Line { SrcBlock "C7" SrcPort 2 DstBlock "C8" DstPort 2 } Line { SrcBlock "C6" SrcPort 3 Points [15, 0] Branch { DstBlock "AddSub6" DstPort 2 } Branch { Points [0, -120] DstBlock "Gateway Out11" DstPort 1 } } Line { SrcBlock "C5" SrcPort 3 Points [10, 0] Branch { Points [0, 70; 85, 0] DstBlock "AddSub6" DstPort 1 } Branch { Points [0, -135] DstBlock "Gateway Out10" DstPort 1 } } Line { SrcBlock "C8" SrcPort 3 Points [10, 0] Branch { DstBlock "AddSub7" DstPort 2 } Branch { Points [0, -90] DstBlock "Gateway Out13" DstPort 1 } } Line { SrcBlock "C7" SrcPort 3 Points [20, 0] Branch { Points [0, 65; 75, 0] DstBlock "AddSub7" DstPort 1 } Branch { Points [0, -105] DstBlock "Gateway Out12" DstPort 1 } } Line { SrcBlock "AddSub6" SrcPort 1 DstBlock "AddSub1" DstPort 1 } Line { SrcBlock "AddSub7" SrcPort 1 Points [0, 35] DstBlock "AddSub1" DstPort 2 } Line { SrcBlock "AddSub13" SrcPort 1 Points [0, 85] DstBlock "AddSub4" DstPort 2 } Line { SrcBlock "AddSub1" SrcPort 1 Points [0, 60] DstBlock "AddSub4" DstPort 1 } Line { SrcBlock "AddSub4" SrcPort 1 Points [45, 0] Branch { Points [0, 75; -400, 0; 0, 90] DstBlock "Gateway Out5" DstPort 1 } Branch { Points [155, 0] Branch { DstBlock "y" DstPort 1 } Branch { Points [0, -390] DstBlock "Gateway Out14" DstPort 1 } } } Line { SrcBlock "C8" SrcPort 4 Points [40, 0; 0, 250] DstBlock "y_vout" DstPort 1 } Line { SrcBlock "Gateway Out7" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out6" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out8" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out1" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out9" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out10" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out11" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out12" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out13" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out14" SrcPort 1 Points [20, 0] } Line { SrcBlock "C8" SrcPort 1 DstBlock "x_dly" DstPort 1 } Line { SrcBlock "C8" SrcPort 2 Points [110, 0] DstBlock "x_dly_vout" DstPort 1 } } } Block { BlockType SubSystem Name "C2" SID "12212" Ports [2, 4] Position [585, 448, 670, 517] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskPromptString "Coefficients/correlator|Coefficients|Input sample period" MaskStyleString "edit,edit,edit" MaskVariables "N=@1;h=@2;Ts_In=@3;" MaskTunableValueString "on,on,on" MaskCallbackString "||" MaskEnableString "on,on,on" MaskVisibilityString "on,on,on" MaskToolTipString "on,on,on" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "4|longCorr_coef_i(1:32)|4" System { Name "C2" Location [480, 85, 2304, 1455] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "156" Block { BlockType Inport Name "x" SID "12213" Position [35, 213, 65, 227] IconDisplay "Port number" } Block { BlockType Inport Name "x_valid" SID "12214" Position [35, 253, 65, 267] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub1" SID "12215" Ports [2, 1] Position [915, 455, 955, 495] BlockRotation 270 BlockMirror on NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "1" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[3 6 0 5 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,40,2,1,white,blue,0,e85d8a90,down,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bf{a + b}','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\ne" "wline\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub12" SID "12216" Ports [2, 1] Position [684, 360, 731, 400] BlockRotation 270 BlockMirror on NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "1" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[3 5 0 4 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "47,40,2,1,white,blue,0,e85d8a90,down,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 47 47 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 47 47 0 0 ],[0 0 40 40 0 ]);\npatch([11.875 19.1 24.1 29.1 34.1 24.1 16.875 11.875 ],[25.55 2" "5.55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([16.875 24.1 19.1 11.875 16.875 ],[20.55 20.55 25.5" "5 25.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([11.875 19.1 24.1 16.875 11.875 ],[15.55 15.55 20.55 20.55 15.55 ]" ",[1 1 1 ]);\npatch([16.875 34.1 29.1 24.1 19.1 11.875 16.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('b" "lack');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output'" ",1,'\\bf{a + b}','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(" "' \\newline\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub13" SID "12217" Ports [2, 1] Position [680, 455, 720, 495] BlockRotation 270 BlockMirror on NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "1" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[3 6 0 5 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,40,2,1,white,blue,0,e85d8a90,down,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bf{a + b}','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\ne" "wline\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub4" SID "12218" Ports [2, 1] Position [960, 549, 1000, 596] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "1" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[4 7 0 6 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,47,2,1,white,blue,0,e85d8a90,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 47 47 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 47 47 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[28.55 28." "55 33.55 28.55 33.55 33.55 33.55 28.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[23.55 23.55 28.55 2" "8.55 23.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[18.55 18.55 23.55 23.55 18.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[13.55 13.55 18.55 13.55 18.55 18.55 13.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bf{a + b}','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\ne" "wline\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub5" SID "12219" Ports [2, 1] Position [475, 360, 515, 400] BlockRotation 270 BlockMirror on NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "1" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[3 6 0 5 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,40,2,1,white,blue,0,e85d8a90,down,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bf{a + b}','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\ne" "wline\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub6" SID "12220" Ports [2, 1] Position [899, 360, 946, 400] BlockRotation 270 BlockMirror on NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "1" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[3 5 0 4 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "47,40,2,1,white,blue,0,e85d8a90,down,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 47 47 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 47 47 0 0 ],[0 0 40 40 0 ]);\npatch([11.875 19.1 24.1 29.1 34.1 24.1 16.875 11.875 ],[25.55 2" "5.55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([16.875 24.1 19.1 11.875 16.875 ],[20.55 20.55 25.5" "5 25.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([11.875 19.1 24.1 16.875 11.875 ],[15.55 15.55 20.55 20.55 15.55 ]" ",[1 1 1 ]);\npatch([16.875 34.1 29.1 24.1 19.1 11.875 16.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('b" "lack');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output'" ",1,'\\bf{a + b}','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(" "' \\newline\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub7" SID "12221" Ports [2, 1] Position [1109, 360, 1156, 400] BlockRotation 270 BlockMirror on NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "1" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[3 5 0 4 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "47,40,2,1,white,blue,0,e85d8a90,down,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 47 47 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 47 47 0 0 ],[0 0 40 40 0 ]);\npatch([11.875 19.1 24.1 29.1 34.1 24.1 16.875 11.875 ],[25.55 2" "5.55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([16.875 24.1 19.1 11.875 16.875 ],[20.55 20.55 25.5" "5 25.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([11.875 19.1 24.1 16.875 11.875 ],[15.55 15.55 20.55 20.55 15.55 ]" ",[1 1 1 ]);\npatch([16.875 34.1 29.1 24.1 19.1 11.875 16.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('b" "lack');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output'" ",1,'\\bf{a + b}','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(" "' \\newline\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "C1" SID "12222" Ports [4, 4] Position [300, 207, 370, 293] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskPromptString "Coefficients (all)|Sub-correlator Ind|Coef/correlator" MaskStyleString "edit,edit,edit" MaskVariables "h=@1;c_ind=@2;N=@3;" MaskTunableValueString "on,on,on" MaskCallbackString "||" MaskEnableString "on,on,on" MaskVisibilityString "on,on,on" MaskToolTipString "on,on,on" MaskInitialization "coef2 = h((c_ind*N+1) : (c_ind + 1)*N);" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "h|0|N" System { Name "C1" Location [480, 85, 2304, 1471] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "122" Block { BlockType Inport Name "x" SID "12223" Position [265, 263, 295, 277] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "vin" SID "12224" Position [270, 303, 300, 317] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "12225" Position [270, 458, 300, 472] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "12226" Position [270, 503, 300, 517] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "ASR" SID "12227" Ports [3, 1] Position [445, 260, 490, 320] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Addressable Shift Register" SourceType "Xilinx Addressable Shift Register Block" infoedit "Delay of configurable length. Any element in the delay line can be addressed and driven onto the" " output port.

Hardware notes: This block is implemented using SRL16s. If Virtex-4 or Spartan-3 device is " "used, multiple SRLC16s are cascaded together." infer_latency off depth "length(coef2)" initVector "[0]" en on dbl_ovrd off use_behavioral_HDL off Optimization "Resource" xl_use_area off xl_area "[1 0 0 2 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,401" block_type "addrsr" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,60,3,1,white,blue,0,f8ea6153,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 60 60 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 60 60 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[36.66 3" "6.66 42.66 36.66 42.66 42.66 42.66 36.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[30.66 30.66 36.66 " "36.66 30.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[24.66 24.66 30.66 30.66 24.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[18.66 18.66 24.66 18.66 24.66 24.66 18.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'addr');\ncolor('black');port_label('input',3," "'en');\ncolor('black');port_label('output',1,'q');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Delay" SID "12228" Ports [1, 1] Position [705, 441, 730, 469] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "25,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 " "17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33" " 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('blac" "k');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "12229" Position [210, 280, 300, 300] ZOrder -9 ShowName off GotoTag "ltsCorr_dAddr" TagVisibility "scoped" } Block { BlockType From Name "From1" SID "12230" Position [210, 340, 300, 360] ZOrder -9 ShowName off GotoTag "ltsCorr_cAddr" TagVisibility "scoped" } Block { BlockType From Name "From2" SID "12231" Position [210, 380, 300, 400] ZOrder -9 ShowName off GotoTag "ltsCorr_ld" TagVisibility "scoped" } Block { BlockType Reference Name "Gateway Out1" SID "12232" Ports [1, 1] Position [745, 615, 780, 625] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "12233" Ports [1, 1] Position [745, 630, 780, 640] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "12234" Ports [1, 1] Position [745, 645, 780, 655] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Ld" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "12235" Ports [1, 1] Position [745, 660, 780, 670] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "12236" Ports [1, 1] Position [745, 675, 780, 685] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "12237" Ports [1, 1] Position [745, 570, 780, 580] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X In" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "12238" Ports [1, 1] Position [745, 585, 780, 595] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "12239" Ports [1, 1] Position [745, 600, 780, 610] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X Vin" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType SubSystem Name "MAC" SID "12240" Ports [4, 2] Position [575, 279, 660, 376] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "MAC" Location [88, 301, 2330, 1301] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "a" SID "12241" Position [35, 143, 65, 157] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "coeff" SID "12242" Position [35, 108, 65, 122] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "ld" SID "12243" Position [35, 178, 65, 192] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "rst" SID "12244" Position [35, 233, 65, 247] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub" SID "12245" Ports [3, 1] Position [340, 113, 385, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition or Subtraction" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Signed (2's comp)" n_bits "long_cor_acc_n_bits" bin_pt "0" quantization "Truncate" overflow "Flag as error" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[2 0 0 4 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,344" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,3,1,white,blue,0,02f64c57,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('input',3,'su" "b');\ncolor('black');port_label('output',1,'\\bf{a \\pm b}','texmode','on');\nfprintf('','COMMENT: end icon text" "');\n" } Block { BlockType Reference Name "Gateway Out1" SID "12246" Ports [1, 1] Position [475, 450, 510, 460] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out2" SID "12247" Ports [1, 1] Position [475, 465, 510, 475] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out3" SID "12248" Ports [1, 1] Position [475, 480, 510, 490] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out6" SID "12249" Ports [1, 1] Position [475, 405, 510, 415] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out7" SID "12250" Ports [1, 1] Position [475, 420, 510, 430] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out8" SID "12251" Ports [1, 1] Position [475, 435, 510, 445] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "12252" Ports [2, 1] Position [345, 30, 385, 70] BlockMirror on NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,40,2,1,white,blue,0,140cc11c,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'" "q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "12253" Ports [2, 1] Position [465, 110, 495, 210] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,100,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 100 100 0 ],[0.77 0." "82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 100 100 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[54.44 " "54.44 58.44 54.44 58.44 58.44 58.44 54.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[50.44 50.44 54.44 54" ".44 50.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[46.44 46.44 50.44 50.44 46.44 ],[1 1 1 ])" ";\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[42.44 42.44 46.44 42.44 46.44 46.44 42.44 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\nco" "lor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc2" SID "12254" Ports [1, 1] Position [265, 143, 290, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc3" SID "12255" Ports [1, 1] Position [135, 178, 160, 192] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "yn" SID "12256" Position [545, 153, 575, 167] IconDisplay "Port number" } Block { BlockType Outport Name "accrm" SID "12257" Position [520, 288, 550, 302] Port "2" IconDisplay "Port number" } Line { SrcBlock "rst" SrcPort 1 Points [90, 0] Branch { Points [0, 215] DstBlock "Gateway Out1" DstPort 1 } Branch { Points [255, 0; 0, -180] DstBlock "Register1" DstPort 2 } } Line { SrcBlock "Gateway Out3" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out2" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out1" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out6" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out7" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out8" SrcPort 1 Points [50, 0] } Line { SrcBlock "a" SrcPort 1 Points [140, 0] Branch { Points [0, 275] DstBlock "Gateway Out7" DstPort 1 } Branch { DstBlock "bc2" DstPort 1 } } Line { SrcBlock "AddSub" SrcPort 1 Points [0, 0; 5, 0] Branch { Points [0, 305] DstBlock "Gateway Out8" DstPort 1 } Branch { Points [40, 0] Branch { Points [0, 160] DstBlock "accrm" DstPort 1 } Branch { Points [0, -95] DstBlock "Register1" DstPort 1 } Branch { DstBlock "Register2" DstPort 1 } } } Line { SrcBlock "Register2" SrcPort 1 Points [15, 0] Branch { Points [0, 50; 110, 0; 0, 385; -260, 0; 0, -110] DstBlock "Gateway Out3" DstPort 1 } Branch { DstBlock "yn" DstPort 1 } } Line { SrcBlock "Register1" SrcPort 1 Points [-15, 0] DstBlock "AddSub" DstPort 1 } Line { SrcBlock "ld" SrcPort 1 Points [45, 0] Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } Branch { DstBlock "bc3" DstPort 1 } } Line { SrcBlock "bc3" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "bc2" SrcPort 1 DstBlock "AddSub" DstPort 3 } Line { SrcBlock "coeff" SrcPort 1 Points [95, 0; 0, 20; 50, 0] Branch { Points [0, 275] DstBlock "Gateway Out6" DstPort 1 } Branch { DstBlock "AddSub" DstPort 2 } } } } Block { BlockType Reference Name "ROM" SID "12258" Ports [1, 1] Position [440, 328, 490, 372] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/ROM" SourceType "Xilinx Single Port Read-Only Memory Block" depth "length(coef2)" initVector "coef2" distributed_mem "Distributed memory" rst off init_reg "0" en off latency "1" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "longCorr_coef_nbits" bin_pt "longCorr_coef_bp" preci_type "Single" exp_width "8" frac_width "24" dbl_ovrd off optimize "Area" use_rpm off xl_use_area off xl_area "[1 1 0 1 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,308" block_type "sprom" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,44,1,1,white,blue,0,bbc23d60,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 44 44 0 ]);\npatch([11.65 20.32 26.32 32.32 38.32 26.32 17.65 11.65 ],[28.66" " 28.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([17.65 26.32 20.32 11.65 17.65 ],[22.66 22.66 28." "66 28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([11.65 20.32 26.32 17.65 11.65 ],[16.66 16.66 22.66 22.66 16.66 ]" ",[1 1 1 ]);\npatch([17.65 38.32 32.32 26.32 20.32 11.65 17.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'addr');\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end" " icon text');\n" } Block { BlockType Outport Name "x_dly" SID "12259" Position [790, 178, 820, 192] IconDisplay "Port number" } Block { BlockType Outport Name "x_dly_vout" SID "12260" Position [790, 223, 820, 237] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "y" SID "12261" Position [790, 293, 820, 307] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "y_vout" SID "12262" Position [785, 448, 815, 462] Port "4" IconDisplay "Port number" } Line { Name "ROM Addr" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 Points [150, 0] } Line { Name "Corr Out" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 Points [150, 0] } Line { Name "Corr Ld" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 Points [150, 0] } Line { Name "ROM Out" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 Points [150, 0] } Line { Name "ASR Out" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 Points [150, 0] } Line { Name "X In" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 Points [150, 0] } Line { Name "ASR Addr" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 Points [150, 0] } Line { Name "X Vin" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 Points [150, 0] } Line { SrcBlock "Delay" SrcPort 1 DstBlock "y_vout" DstPort 1 } Line { SrcBlock "vin" SrcPort 1 Points [25, 0] Branch { Points [0, -80] DstBlock "x_dly_vout" DstPort 1 } Branch { Points [0, 100] Branch { Points [230, 0] DstBlock "MAC" DstPort 4 } Branch { Points [0, 195] DstBlock "Gateway Out8" DstPort 1 } } Branch { DstBlock "ASR" DstPort 3 } } Line { SrcBlock "x" SrcPort 1 Points [100, 0] Branch { Points [0, 305] DstBlock "Gateway Out6" DstPort 1 } Branch { DstBlock "ASR" DstPort 1 } } Line { SrcBlock "From" SrcPort 1 Points [90, 0] Branch { Points [0, 300] DstBlock "Gateway Out7" DstPort 1 } Branch { DstBlock "ASR" DstPort 2 } } Line { SrcBlock "From1" SrcPort 1 Points [5, 0] Branch { Points [0, 330] DstBlock "Gateway Out5" DstPort 1 } Branch { DstBlock "ROM" DstPort 1 } } Line { SrcBlock "ASR" SrcPort 1 Points [35, 0] Branch { Points [0, 330] DstBlock "Gateway Out1" DstPort 1 } Branch { Points [0, -105] DstBlock "x_dly" DstPort 1 } Branch { DstBlock "MAC" DstPort 1 } } Line { SrcBlock "MAC" SrcPort 1 Points [0, -5; 15, 0] Branch { Points [0, 365] DstBlock "Gateway Out4" DstPort 1 } Branch { DstBlock "y" DstPort 1 } } Line { SrcBlock "ROM" SrcPort 1 Points [5, 0] Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } Branch { Points [0, -35] DstBlock "MAC" DstPort 2 } } Line { SrcBlock "From2" SrcPort 1 Points [145, 0] Branch { Points [0, 260] DstBlock "Gateway Out3" DstPort 1 } Branch { Points [90, 0] Branch { Points [0, 65] DstBlock "Delay" DstPort 1 } Branch { Points [0, -50] Branch { Points [0, -90; 160, 0] } Branch { DstBlock "MAC" DstPort 3 } } } } } } Block { BlockType SubSystem Name "C2" SID "12263" Ports [4, 4] Position [410, 207, 480, 293] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskPromptString "Coefficients (all)|Sub-correlator Ind|Coef/correlator" MaskStyleString "edit,edit,edit" MaskVariables "h=@1;c_ind=@2;N=@3;" MaskTunableValueString "on,on,on" MaskCallbackString "||" MaskEnableString "on,on,on" MaskVisibilityString "on,on,on" MaskToolTipString "on,on,on" MaskInitialization "coef2 = h((c_ind*N+1) : (c_ind + 1)*N);" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "h|1|N" System { Name "C2" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "122" Block { BlockType Inport Name "x" SID "12264" Position [265, 263, 295, 277] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "vin" SID "12265" Position [270, 303, 300, 317] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "12266" Position [270, 458, 300, 472] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "12267" Position [270, 503, 300, 517] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "ASR" SID "12268" Ports [3, 1] Position [445, 260, 490, 320] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Addressable Shift Register" SourceType "Xilinx Addressable Shift Register Block" infoedit "Delay of configurable length. Any element in the delay line can be addressed and driven onto the" " output port.

Hardware notes: This block is implemented using SRL16s. If Virtex-4 or Spartan-3 device is " "used, multiple SRLC16s are cascaded together." infer_latency off depth "length(coef2)" initVector "[0]" en on dbl_ovrd off use_behavioral_HDL off Optimization "Resource" xl_use_area off xl_area "[1 0 0 2 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,401" block_type "addrsr" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,60,3,1,white,blue,0,f8ea6153,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 60 60 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 60 60 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[36.66 3" "6.66 42.66 36.66 42.66 42.66 42.66 36.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[30.66 30.66 36.66 " "36.66 30.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[24.66 24.66 30.66 30.66 24.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[18.66 18.66 24.66 18.66 24.66 24.66 18.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'addr');\ncolor('black');port_label('input',3," "'en');\ncolor('black');port_label('output',1,'q');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Delay" SID "12269" Ports [1, 1] Position [705, 441, 730, 469] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "25,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 " "17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33" " 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('blac" "k');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "12270" Position [210, 280, 300, 300] ZOrder -9 ShowName off GotoTag "ltsCorr_dAddr" TagVisibility "scoped" } Block { BlockType From Name "From1" SID "12271" Position [210, 340, 300, 360] ZOrder -9 ShowName off GotoTag "ltsCorr_cAddr" TagVisibility "scoped" } Block { BlockType From Name "From2" SID "12272" Position [210, 380, 300, 400] ZOrder -9 ShowName off GotoTag "ltsCorr_ld" TagVisibility "scoped" } Block { BlockType Reference Name "Gateway Out1" SID "12273" Ports [1, 1] Position [745, 615, 780, 625] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "12274" Ports [1, 1] Position [745, 630, 780, 640] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "12275" Ports [1, 1] Position [745, 645, 780, 655] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Ld" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "12276" Ports [1, 1] Position [745, 660, 780, 670] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "12277" Ports [1, 1] Position [745, 675, 780, 685] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "12278" Ports [1, 1] Position [745, 570, 780, 580] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X In" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "12279" Ports [1, 1] Position [745, 585, 780, 595] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "12280" Ports [1, 1] Position [745, 600, 780, 610] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X Vin" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType SubSystem Name "MAC" SID "12281" Ports [4, 2] Position [575, 279, 660, 376] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "MAC" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "a" SID "12282" Position [35, 143, 65, 157] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "coeff" SID "12283" Position [35, 108, 65, 122] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "ld" SID "12284" Position [35, 178, 65, 192] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "rst" SID "12285" Position [35, 233, 65, 247] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub" SID "12286" Ports [3, 1] Position [340, 113, 385, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition or Subtraction" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Signed (2's comp)" n_bits "long_cor_acc_n_bits" bin_pt "0" quantization "Truncate" overflow "Flag as error" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[2 0 0 4 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,344" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,3,1,white,blue,0,02f64c57,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('input',3,'su" "b');\ncolor('black');port_label('output',1,'\\bf{a \\pm b}','texmode','on');\nfprintf('','COMMENT: end icon text" "');\n" } Block { BlockType Reference Name "Gateway Out1" SID "12287" Ports [1, 1] Position [475, 450, 510, 460] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out2" SID "12288" Ports [1, 1] Position [475, 465, 510, 475] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out3" SID "12289" Ports [1, 1] Position [475, 480, 510, 490] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out6" SID "12290" Ports [1, 1] Position [475, 405, 510, 415] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out7" SID "12291" Ports [1, 1] Position [475, 420, 510, 430] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out8" SID "12292" Ports [1, 1] Position [475, 435, 510, 445] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "12293" Ports [2, 1] Position [345, 30, 385, 70] BlockMirror on NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,40,2,1,white,blue,0,140cc11c,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'" "q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "12294" Ports [2, 1] Position [465, 110, 495, 210] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,100,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 100 100 0 ],[0.77 0." "82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 100 100 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[54.44 " "54.44 58.44 54.44 58.44 58.44 58.44 54.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[50.44 50.44 54.44 54" ".44 50.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[46.44 46.44 50.44 50.44 46.44 ],[1 1 1 ])" ";\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[42.44 42.44 46.44 42.44 46.44 46.44 42.44 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\nco" "lor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc2" SID "12295" Ports [1, 1] Position [265, 143, 290, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc3" SID "12296" Ports [1, 1] Position [135, 178, 160, 192] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "yn" SID "12297" Position [545, 153, 575, 167] IconDisplay "Port number" } Block { BlockType Outport Name "accrm" SID "12298" Position [520, 288, 550, 302] Port "2" IconDisplay "Port number" } Line { SrcBlock "coeff" SrcPort 1 Points [95, 0; 0, 20; 50, 0] Branch { DstBlock "AddSub" DstPort 2 } Branch { Points [0, 275] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "bc2" SrcPort 1 DstBlock "AddSub" DstPort 3 } Line { SrcBlock "bc3" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "ld" SrcPort 1 Points [45, 0] Branch { DstBlock "bc3" DstPort 1 } Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "Register1" SrcPort 1 Points [-15, 0] DstBlock "AddSub" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 Points [15, 0] Branch { DstBlock "yn" DstPort 1 } Branch { Points [0, 50; 110, 0; 0, 385; -260, 0; 0, -110] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "AddSub" SrcPort 1 Points [0, 0; 5, 0] Branch { Points [40, 0] Branch { DstBlock "Register2" DstPort 1 } Branch { Points [0, -95] DstBlock "Register1" DstPort 1 } Branch { Points [0, 160] DstBlock "accrm" DstPort 1 } } Branch { Points [0, 305] DstBlock "Gateway Out8" DstPort 1 } } Line { SrcBlock "a" SrcPort 1 Points [140, 0] Branch { DstBlock "bc2" DstPort 1 } Branch { Points [0, 275] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "Gateway Out8" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out7" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out6" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out1" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out2" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out3" SrcPort 1 Points [50, 0] } Line { SrcBlock "rst" SrcPort 1 Points [90, 0] Branch { Points [255, 0; 0, -180] DstBlock "Register1" DstPort 2 } Branch { Points [0, 215] DstBlock "Gateway Out1" DstPort 1 } } } } Block { BlockType Reference Name "ROM" SID "12299" Ports [1, 1] Position [440, 328, 490, 372] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/ROM" SourceType "Xilinx Single Port Read-Only Memory Block" depth "length(coef2)" initVector "coef2" distributed_mem "Distributed memory" rst off init_reg "0" en off latency "1" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "longCorr_coef_nbits" bin_pt "longCorr_coef_bp" preci_type "Single" exp_width "8" frac_width "24" dbl_ovrd off optimize "Area" use_rpm off xl_use_area off xl_area "[1 1 0 1 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,308" block_type "sprom" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,44,1,1,white,blue,0,bbc23d60,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 44 44 0 ]);\npatch([11.65 20.32 26.32 32.32 38.32 26.32 17.65 11.65 ],[28.66" " 28.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([17.65 26.32 20.32 11.65 17.65 ],[22.66 22.66 28." "66 28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([11.65 20.32 26.32 17.65 11.65 ],[16.66 16.66 22.66 22.66 16.66 ]" ",[1 1 1 ]);\npatch([17.65 38.32 32.32 26.32 20.32 11.65 17.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'addr');\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end" " icon text');\n" } Block { BlockType Outport Name "x_dly" SID "12300" Position [790, 178, 820, 192] IconDisplay "Port number" } Block { BlockType Outport Name "x_dly_vout" SID "12301" Position [790, 223, 820, 237] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "y" SID "12302" Position [790, 293, 820, 307] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "y_vout" SID "12303" Position [785, 448, 815, 462] Port "4" IconDisplay "Port number" } Line { SrcBlock "From2" SrcPort 1 Points [145, 0] Branch { Points [90, 0] Branch { Points [0, -50] Branch { DstBlock "MAC" DstPort 3 } Branch { Points [0, -90; 160, 0] } } Branch { Points [0, 65] DstBlock "Delay" DstPort 1 } } Branch { Points [0, 260] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "ROM" SrcPort 1 Points [5, 0] Branch { Points [0, -35] DstBlock "MAC" DstPort 2 } Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "MAC" SrcPort 1 Points [0, -5; 15, 0] Branch { DstBlock "y" DstPort 1 } Branch { Points [0, 365] DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "ASR" SrcPort 1 Points [35, 0] Branch { DstBlock "MAC" DstPort 1 } Branch { Points [0, -105] DstBlock "x_dly" DstPort 1 } Branch { Points [0, 330] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "From1" SrcPort 1 Points [5, 0] Branch { DstBlock "ROM" DstPort 1 } Branch { Points [0, 330] DstBlock "Gateway Out5" DstPort 1 } } Line { SrcBlock "From" SrcPort 1 Points [90, 0] Branch { DstBlock "ASR" DstPort 2 } Branch { Points [0, 300] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "x" SrcPort 1 Points [100, 0] Branch { DstBlock "ASR" DstPort 1 } Branch { Points [0, 305] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "vin" SrcPort 1 Points [25, 0] Branch { DstBlock "ASR" DstPort 3 } Branch { Points [0, 100] Branch { Points [0, 195] DstBlock "Gateway Out8" DstPort 1 } Branch { Points [230, 0] DstBlock "MAC" DstPort 4 } } Branch { Points [0, -80] DstBlock "x_dly_vout" DstPort 1 } } Line { SrcBlock "Delay" SrcPort 1 DstBlock "y_vout" DstPort 1 } Line { Name "X Vin" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 Points [150, 0] } Line { Name "ASR Addr" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 Points [150, 0] } Line { Name "X In" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 Points [150, 0] } Line { Name "ASR Out" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 Points [150, 0] } Line { Name "ROM Out" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 Points [150, 0] } Line { Name "Corr Ld" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 Points [150, 0] } Line { Name "Corr Out" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 Points [150, 0] } Line { Name "ROM Addr" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 Points [150, 0] } } } Block { BlockType SubSystem Name "C3" SID "12304" Ports [4, 4] Position [520, 207, 590, 293] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskPromptString "Coefficients (all)|Sub-correlator Ind|Coef/correlator" MaskStyleString "edit,edit,edit" MaskVariables "h=@1;c_ind=@2;N=@3;" MaskTunableValueString "on,on,on" MaskCallbackString "||" MaskEnableString "on,on,on" MaskVisibilityString "on,on,on" MaskToolTipString "on,on,on" MaskInitialization "coef2 = h((c_ind*N+1) : (c_ind + 1)*N);" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "h|2|N" System { Name "C3" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "122" Block { BlockType Inport Name "x" SID "12305" Position [265, 263, 295, 277] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "vin" SID "12306" Position [270, 303, 300, 317] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "12307" Position [270, 458, 300, 472] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "12308" Position [270, 503, 300, 517] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "ASR" SID "12309" Ports [3, 1] Position [445, 260, 490, 320] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Addressable Shift Register" SourceType "Xilinx Addressable Shift Register Block" infoedit "Delay of configurable length. Any element in the delay line can be addressed and driven onto the" " output port.

Hardware notes: This block is implemented using SRL16s. If Virtex-4 or Spartan-3 device is " "used, multiple SRLC16s are cascaded together." infer_latency off depth "length(coef2)" initVector "[0]" en on dbl_ovrd off use_behavioral_HDL off Optimization "Resource" xl_use_area off xl_area "[1 0 0 2 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,401" block_type "addrsr" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,60,3,1,white,blue,0,f8ea6153,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 60 60 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 60 60 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[36.66 3" "6.66 42.66 36.66 42.66 42.66 42.66 36.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[30.66 30.66 36.66 " "36.66 30.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[24.66 24.66 30.66 30.66 24.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[18.66 18.66 24.66 18.66 24.66 24.66 18.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'addr');\ncolor('black');port_label('input',3," "'en');\ncolor('black');port_label('output',1,'q');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Delay" SID "12310" Ports [1, 1] Position [705, 441, 730, 469] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "25,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 " "17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33" " 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('blac" "k');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "12311" Position [210, 280, 300, 300] ZOrder -9 ShowName off GotoTag "ltsCorr_dAddr" TagVisibility "scoped" } Block { BlockType From Name "From1" SID "12312" Position [210, 340, 300, 360] ZOrder -9 ShowName off GotoTag "ltsCorr_cAddr" TagVisibility "scoped" } Block { BlockType From Name "From2" SID "12313" Position [210, 380, 300, 400] ZOrder -9 ShowName off GotoTag "ltsCorr_ld" TagVisibility "scoped" } Block { BlockType Reference Name "Gateway Out1" SID "12314" Ports [1, 1] Position [745, 615, 780, 625] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "12315" Ports [1, 1] Position [745, 630, 780, 640] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "12316" Ports [1, 1] Position [745, 645, 780, 655] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Ld" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "12317" Ports [1, 1] Position [745, 660, 780, 670] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "12318" Ports [1, 1] Position [745, 675, 780, 685] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "12319" Ports [1, 1] Position [745, 570, 780, 580] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X In" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "12320" Ports [1, 1] Position [745, 585, 780, 595] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "12321" Ports [1, 1] Position [745, 600, 780, 610] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X Vin" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType SubSystem Name "MAC" SID "12322" Ports [4, 2] Position [575, 279, 660, 376] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "MAC" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "a" SID "12323" Position [35, 143, 65, 157] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "coeff" SID "12324" Position [35, 108, 65, 122] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "ld" SID "12325" Position [35, 178, 65, 192] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "rst" SID "12326" Position [35, 233, 65, 247] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub" SID "12327" Ports [3, 1] Position [340, 113, 385, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition or Subtraction" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Signed (2's comp)" n_bits "long_cor_acc_n_bits" bin_pt "0" quantization "Truncate" overflow "Flag as error" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[2 0 0 4 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,344" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,3,1,white,blue,0,02f64c57,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('input',3,'su" "b');\ncolor('black');port_label('output',1,'\\bf{a \\pm b}','texmode','on');\nfprintf('','COMMENT: end icon text" "');\n" } Block { BlockType Reference Name "Gateway Out1" SID "12328" Ports [1, 1] Position [475, 450, 510, 460] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out2" SID "12329" Ports [1, 1] Position [475, 465, 510, 475] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out3" SID "12330" Ports [1, 1] Position [475, 480, 510, 490] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out6" SID "12331" Ports [1, 1] Position [475, 405, 510, 415] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out7" SID "12332" Ports [1, 1] Position [475, 420, 510, 430] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out8" SID "12333" Ports [1, 1] Position [475, 435, 510, 445] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "12334" Ports [2, 1] Position [345, 30, 385, 70] BlockMirror on NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,40,2,1,white,blue,0,140cc11c,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'" "q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "12335" Ports [2, 1] Position [465, 110, 495, 210] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,100,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 100 100 0 ],[0.77 0." "82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 100 100 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[54.44 " "54.44 58.44 54.44 58.44 58.44 58.44 54.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[50.44 50.44 54.44 54" ".44 50.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[46.44 46.44 50.44 50.44 46.44 ],[1 1 1 ])" ";\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[42.44 42.44 46.44 42.44 46.44 46.44 42.44 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\nco" "lor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc2" SID "12336" Ports [1, 1] Position [265, 143, 290, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc3" SID "12337" Ports [1, 1] Position [135, 178, 160, 192] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "yn" SID "12338" Position [545, 153, 575, 167] IconDisplay "Port number" } Block { BlockType Outport Name "accrm" SID "12339" Position [520, 288, 550, 302] Port "2" IconDisplay "Port number" } Line { SrcBlock "rst" SrcPort 1 Points [90, 0] Branch { Points [0, 215] DstBlock "Gateway Out1" DstPort 1 } Branch { Points [255, 0; 0, -180] DstBlock "Register1" DstPort 2 } } Line { SrcBlock "Gateway Out3" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out2" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out1" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out6" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out7" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out8" SrcPort 1 Points [50, 0] } Line { SrcBlock "a" SrcPort 1 Points [140, 0] Branch { Points [0, 275] DstBlock "Gateway Out7" DstPort 1 } Branch { DstBlock "bc2" DstPort 1 } } Line { SrcBlock "AddSub" SrcPort 1 Points [0, 0; 5, 0] Branch { Points [0, 305] DstBlock "Gateway Out8" DstPort 1 } Branch { Points [40, 0] Branch { Points [0, 160] DstBlock "accrm" DstPort 1 } Branch { Points [0, -95] DstBlock "Register1" DstPort 1 } Branch { DstBlock "Register2" DstPort 1 } } } Line { SrcBlock "Register2" SrcPort 1 Points [15, 0] Branch { Points [0, 50; 110, 0; 0, 385; -260, 0; 0, -110] DstBlock "Gateway Out3" DstPort 1 } Branch { DstBlock "yn" DstPort 1 } } Line { SrcBlock "Register1" SrcPort 1 Points [-15, 0] DstBlock "AddSub" DstPort 1 } Line { SrcBlock "ld" SrcPort 1 Points [45, 0] Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } Branch { DstBlock "bc3" DstPort 1 } } Line { SrcBlock "bc3" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "bc2" SrcPort 1 DstBlock "AddSub" DstPort 3 } Line { SrcBlock "coeff" SrcPort 1 Points [95, 0; 0, 20; 50, 0] Branch { Points [0, 275] DstBlock "Gateway Out6" DstPort 1 } Branch { DstBlock "AddSub" DstPort 2 } } } } Block { BlockType Reference Name "ROM" SID "12340" Ports [1, 1] Position [440, 328, 490, 372] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/ROM" SourceType "Xilinx Single Port Read-Only Memory Block" depth "length(coef2)" initVector "coef2" distributed_mem "Distributed memory" rst off init_reg "0" en off latency "1" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "longCorr_coef_nbits" bin_pt "longCorr_coef_bp" preci_type "Single" exp_width "8" frac_width "24" dbl_ovrd off optimize "Area" use_rpm off xl_use_area off xl_area "[1 1 0 1 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,308" block_type "sprom" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,44,1,1,white,blue,0,bbc23d60,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 44 44 0 ]);\npatch([11.65 20.32 26.32 32.32 38.32 26.32 17.65 11.65 ],[28.66" " 28.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([17.65 26.32 20.32 11.65 17.65 ],[22.66 22.66 28." "66 28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([11.65 20.32 26.32 17.65 11.65 ],[16.66 16.66 22.66 22.66 16.66 ]" ",[1 1 1 ]);\npatch([17.65 38.32 32.32 26.32 20.32 11.65 17.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'addr');\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end" " icon text');\n" } Block { BlockType Outport Name "x_dly" SID "12341" Position [790, 178, 820, 192] IconDisplay "Port number" } Block { BlockType Outport Name "x_dly_vout" SID "12342" Position [790, 223, 820, 237] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "y" SID "12343" Position [790, 293, 820, 307] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "y_vout" SID "12344" Position [785, 448, 815, 462] Port "4" IconDisplay "Port number" } Line { Name "ROM Addr" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 Points [150, 0] } Line { Name "Corr Out" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 Points [150, 0] } Line { Name "Corr Ld" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 Points [150, 0] } Line { Name "ROM Out" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 Points [150, 0] } Line { Name "ASR Out" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 Points [150, 0] } Line { Name "X In" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 Points [150, 0] } Line { Name "ASR Addr" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 Points [150, 0] } Line { Name "X Vin" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 Points [150, 0] } Line { SrcBlock "Delay" SrcPort 1 DstBlock "y_vout" DstPort 1 } Line { SrcBlock "vin" SrcPort 1 Points [25, 0] Branch { Points [0, -80] DstBlock "x_dly_vout" DstPort 1 } Branch { Points [0, 100] Branch { Points [230, 0] DstBlock "MAC" DstPort 4 } Branch { Points [0, 195] DstBlock "Gateway Out8" DstPort 1 } } Branch { DstBlock "ASR" DstPort 3 } } Line { SrcBlock "x" SrcPort 1 Points [100, 0] Branch { Points [0, 305] DstBlock "Gateway Out6" DstPort 1 } Branch { DstBlock "ASR" DstPort 1 } } Line { SrcBlock "From" SrcPort 1 Points [90, 0] Branch { Points [0, 300] DstBlock "Gateway Out7" DstPort 1 } Branch { DstBlock "ASR" DstPort 2 } } Line { SrcBlock "From1" SrcPort 1 Points [5, 0] Branch { Points [0, 330] DstBlock "Gateway Out5" DstPort 1 } Branch { DstBlock "ROM" DstPort 1 } } Line { SrcBlock "ASR" SrcPort 1 Points [35, 0] Branch { Points [0, 330] DstBlock "Gateway Out1" DstPort 1 } Branch { Points [0, -105] DstBlock "x_dly" DstPort 1 } Branch { DstBlock "MAC" DstPort 1 } } Line { SrcBlock "MAC" SrcPort 1 Points [0, -5; 15, 0] Branch { Points [0, 365] DstBlock "Gateway Out4" DstPort 1 } Branch { DstBlock "y" DstPort 1 } } Line { SrcBlock "ROM" SrcPort 1 Points [5, 0] Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } Branch { Points [0, -35] DstBlock "MAC" DstPort 2 } } Line { SrcBlock "From2" SrcPort 1 Points [145, 0] Branch { Points [0, 260] DstBlock "Gateway Out3" DstPort 1 } Branch { Points [90, 0] Branch { Points [0, 65] DstBlock "Delay" DstPort 1 } Branch { Points [0, -50] Branch { Points [0, -90; 160, 0] } Branch { DstBlock "MAC" DstPort 3 } } } } } } Block { BlockType SubSystem Name "C4" SID "12345" Ports [4, 4] Position [630, 207, 700, 293] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskPromptString "Coefficients (all)|Sub-correlator Ind|Coef/correlator" MaskStyleString "edit,edit,edit" MaskVariables "h=@1;c_ind=@2;N=@3;" MaskTunableValueString "on,on,on" MaskCallbackString "||" MaskEnableString "on,on,on" MaskVisibilityString "on,on,on" MaskToolTipString "on,on,on" MaskInitialization "coef2 = h((c_ind*N+1) : (c_ind + 1)*N);" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "h|3|N" System { Name "C4" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "122" Block { BlockType Inport Name "x" SID "12346" Position [265, 263, 295, 277] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "vin" SID "12347" Position [270, 303, 300, 317] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "12348" Position [270, 458, 300, 472] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "12349" Position [270, 503, 300, 517] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "ASR" SID "12350" Ports [3, 1] Position [445, 260, 490, 320] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Addressable Shift Register" SourceType "Xilinx Addressable Shift Register Block" infoedit "Delay of configurable length. Any element in the delay line can be addressed and driven onto the" " output port.

Hardware notes: This block is implemented using SRL16s. If Virtex-4 or Spartan-3 device is " "used, multiple SRLC16s are cascaded together." infer_latency off depth "length(coef2)" initVector "[0]" en on dbl_ovrd off use_behavioral_HDL off Optimization "Resource" xl_use_area off xl_area "[1 0 0 2 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,401" block_type "addrsr" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,60,3,1,white,blue,0,f8ea6153,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 60 60 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 60 60 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[36.66 3" "6.66 42.66 36.66 42.66 42.66 42.66 36.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[30.66 30.66 36.66 " "36.66 30.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[24.66 24.66 30.66 30.66 24.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[18.66 18.66 24.66 18.66 24.66 24.66 18.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'addr');\ncolor('black');port_label('input',3," "'en');\ncolor('black');port_label('output',1,'q');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Delay" SID "12351" Ports [1, 1] Position [705, 441, 730, 469] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "25,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 " "17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33" " 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('blac" "k');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "12352" Position [210, 280, 300, 300] ZOrder -9 ShowName off GotoTag "ltsCorr_dAddr" TagVisibility "scoped" } Block { BlockType From Name "From1" SID "12353" Position [210, 340, 300, 360] ZOrder -9 ShowName off GotoTag "ltsCorr_cAddr" TagVisibility "scoped" } Block { BlockType From Name "From2" SID "12354" Position [210, 380, 300, 400] ZOrder -9 ShowName off GotoTag "ltsCorr_ld" TagVisibility "scoped" } Block { BlockType Reference Name "Gateway Out1" SID "12355" Ports [1, 1] Position [745, 615, 780, 625] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "12356" Ports [1, 1] Position [745, 630, 780, 640] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "12357" Ports [1, 1] Position [745, 645, 780, 655] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Ld" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "12358" Ports [1, 1] Position [745, 660, 780, 670] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "12359" Ports [1, 1] Position [745, 675, 780, 685] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "12360" Ports [1, 1] Position [745, 570, 780, 580] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X In" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "12361" Ports [1, 1] Position [745, 585, 780, 595] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "12362" Ports [1, 1] Position [745, 600, 780, 610] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X Vin" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType SubSystem Name "MAC" SID "12363" Ports [4, 2] Position [575, 279, 660, 376] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "MAC" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "a" SID "12364" Position [35, 143, 65, 157] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "coeff" SID "12365" Position [35, 108, 65, 122] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "ld" SID "12366" Position [35, 178, 65, 192] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "rst" SID "12367" Position [35, 233, 65, 247] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub" SID "12368" Ports [3, 1] Position [340, 113, 385, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition or Subtraction" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Signed (2's comp)" n_bits "long_cor_acc_n_bits" bin_pt "0" quantization "Truncate" overflow "Flag as error" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[2 0 0 4 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,344" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,3,1,white,blue,0,02f64c57,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('input',3,'su" "b');\ncolor('black');port_label('output',1,'\\bf{a \\pm b}','texmode','on');\nfprintf('','COMMENT: end icon text" "');\n" } Block { BlockType Reference Name "Gateway Out1" SID "12369" Ports [1, 1] Position [475, 450, 510, 460] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out2" SID "12370" Ports [1, 1] Position [475, 465, 510, 475] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out3" SID "12371" Ports [1, 1] Position [475, 480, 510, 490] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out6" SID "12372" Ports [1, 1] Position [475, 405, 510, 415] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out7" SID "12373" Ports [1, 1] Position [475, 420, 510, 430] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out8" SID "12374" Ports [1, 1] Position [475, 435, 510, 445] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "12375" Ports [2, 1] Position [345, 30, 385, 70] BlockMirror on NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,40,2,1,white,blue,0,140cc11c,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'" "q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "12376" Ports [2, 1] Position [465, 110, 495, 210] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,100,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 100 100 0 ],[0.77 0." "82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 100 100 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[54.44 " "54.44 58.44 54.44 58.44 58.44 58.44 54.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[50.44 50.44 54.44 54" ".44 50.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[46.44 46.44 50.44 50.44 46.44 ],[1 1 1 ])" ";\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[42.44 42.44 46.44 42.44 46.44 46.44 42.44 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\nco" "lor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc2" SID "12377" Ports [1, 1] Position [265, 143, 290, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc3" SID "12378" Ports [1, 1] Position [135, 178, 160, 192] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "yn" SID "12379" Position [545, 153, 575, 167] IconDisplay "Port number" } Block { BlockType Outport Name "accrm" SID "12380" Position [520, 288, 550, 302] Port "2" IconDisplay "Port number" } Line { SrcBlock "coeff" SrcPort 1 Points [95, 0; 0, 20; 50, 0] Branch { DstBlock "AddSub" DstPort 2 } Branch { Points [0, 275] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "bc2" SrcPort 1 DstBlock "AddSub" DstPort 3 } Line { SrcBlock "bc3" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "ld" SrcPort 1 Points [45, 0] Branch { DstBlock "bc3" DstPort 1 } Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "Register1" SrcPort 1 Points [-15, 0] DstBlock "AddSub" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 Points [15, 0] Branch { DstBlock "yn" DstPort 1 } Branch { Points [0, 50; 110, 0; 0, 385; -260, 0; 0, -110] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "AddSub" SrcPort 1 Points [0, 0; 5, 0] Branch { Points [40, 0] Branch { DstBlock "Register2" DstPort 1 } Branch { Points [0, -95] DstBlock "Register1" DstPort 1 } Branch { Points [0, 160] DstBlock "accrm" DstPort 1 } } Branch { Points [0, 305] DstBlock "Gateway Out8" DstPort 1 } } Line { SrcBlock "a" SrcPort 1 Points [140, 0] Branch { DstBlock "bc2" DstPort 1 } Branch { Points [0, 275] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "Gateway Out8" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out7" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out6" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out1" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out2" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out3" SrcPort 1 Points [50, 0] } Line { SrcBlock "rst" SrcPort 1 Points [90, 0] Branch { Points [255, 0; 0, -180] DstBlock "Register1" DstPort 2 } Branch { Points [0, 215] DstBlock "Gateway Out1" DstPort 1 } } } } Block { BlockType Reference Name "ROM" SID "12381" Ports [1, 1] Position [440, 328, 490, 372] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/ROM" SourceType "Xilinx Single Port Read-Only Memory Block" depth "length(coef2)" initVector "coef2" distributed_mem "Distributed memory" rst off init_reg "0" en off latency "1" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "longCorr_coef_nbits" bin_pt "longCorr_coef_bp" preci_type "Single" exp_width "8" frac_width "24" dbl_ovrd off optimize "Area" use_rpm off xl_use_area off xl_area "[1 1 0 1 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,308" block_type "sprom" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,44,1,1,white,blue,0,bbc23d60,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 44 44 0 ]);\npatch([11.65 20.32 26.32 32.32 38.32 26.32 17.65 11.65 ],[28.66" " 28.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([17.65 26.32 20.32 11.65 17.65 ],[22.66 22.66 28." "66 28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([11.65 20.32 26.32 17.65 11.65 ],[16.66 16.66 22.66 22.66 16.66 ]" ",[1 1 1 ]);\npatch([17.65 38.32 32.32 26.32 20.32 11.65 17.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'addr');\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end" " icon text');\n" } Block { BlockType Outport Name "x_dly" SID "12382" Position [790, 178, 820, 192] IconDisplay "Port number" } Block { BlockType Outport Name "x_dly_vout" SID "12383" Position [790, 223, 820, 237] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "y" SID "12384" Position [790, 293, 820, 307] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "y_vout" SID "12385" Position [785, 448, 815, 462] Port "4" IconDisplay "Port number" } Line { SrcBlock "From2" SrcPort 1 Points [145, 0] Branch { Points [90, 0] Branch { Points [0, -50] Branch { DstBlock "MAC" DstPort 3 } Branch { Points [0, -90; 160, 0] } } Branch { Points [0, 65] DstBlock "Delay" DstPort 1 } } Branch { Points [0, 260] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "ROM" SrcPort 1 Points [5, 0] Branch { Points [0, -35] DstBlock "MAC" DstPort 2 } Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "MAC" SrcPort 1 Points [0, -5; 15, 0] Branch { DstBlock "y" DstPort 1 } Branch { Points [0, 365] DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "ASR" SrcPort 1 Points [35, 0] Branch { DstBlock "MAC" DstPort 1 } Branch { Points [0, -105] DstBlock "x_dly" DstPort 1 } Branch { Points [0, 330] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "From1" SrcPort 1 Points [5, 0] Branch { DstBlock "ROM" DstPort 1 } Branch { Points [0, 330] DstBlock "Gateway Out5" DstPort 1 } } Line { SrcBlock "From" SrcPort 1 Points [90, 0] Branch { DstBlock "ASR" DstPort 2 } Branch { Points [0, 300] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "x" SrcPort 1 Points [100, 0] Branch { DstBlock "ASR" DstPort 1 } Branch { Points [0, 305] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "vin" SrcPort 1 Points [25, 0] Branch { DstBlock "ASR" DstPort 3 } Branch { Points [0, 100] Branch { Points [0, 195] DstBlock "Gateway Out8" DstPort 1 } Branch { Points [230, 0] DstBlock "MAC" DstPort 4 } } Branch { Points [0, -80] DstBlock "x_dly_vout" DstPort 1 } } Line { SrcBlock "Delay" SrcPort 1 DstBlock "y_vout" DstPort 1 } Line { Name "X Vin" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 Points [150, 0] } Line { Name "ASR Addr" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 Points [150, 0] } Line { Name "X In" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 Points [150, 0] } Line { Name "ASR Out" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 Points [150, 0] } Line { Name "ROM Out" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 Points [150, 0] } Line { Name "Corr Ld" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 Points [150, 0] } Line { Name "Corr Out" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 Points [150, 0] } Line { Name "ROM Addr" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 Points [150, 0] } } } Block { BlockType SubSystem Name "C5" SID "12386" Ports [4, 4] Position [740, 207, 810, 293] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskPromptString "Coefficients (all)|Sub-correlator Ind|Coef/correlator" MaskStyleString "edit,edit,edit" MaskVariables "h=@1;c_ind=@2;N=@3;" MaskTunableValueString "on,on,on" MaskCallbackString "||" MaskEnableString "on,on,on" MaskVisibilityString "on,on,on" MaskToolTipString "on,on,on" MaskInitialization "coef2 = h((c_ind*N+1) : (c_ind + 1)*N);" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "h|4|N" System { Name "C5" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "122" Block { BlockType Inport Name "x" SID "12387" Position [265, 263, 295, 277] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "vin" SID "12388" Position [270, 303, 300, 317] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "12389" Position [270, 458, 300, 472] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "12390" Position [270, 503, 300, 517] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "ASR" SID "12391" Ports [3, 1] Position [445, 260, 490, 320] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Addressable Shift Register" SourceType "Xilinx Addressable Shift Register Block" infoedit "Delay of configurable length. Any element in the delay line can be addressed and driven onto the" " output port.

Hardware notes: This block is implemented using SRL16s. If Virtex-4 or Spartan-3 device is " "used, multiple SRLC16s are cascaded together." infer_latency off depth "length(coef2)" initVector "[0]" en on dbl_ovrd off use_behavioral_HDL off Optimization "Resource" xl_use_area off xl_area "[1 0 0 2 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,401" block_type "addrsr" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,60,3,1,white,blue,0,f8ea6153,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 60 60 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 60 60 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[36.66 3" "6.66 42.66 36.66 42.66 42.66 42.66 36.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[30.66 30.66 36.66 " "36.66 30.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[24.66 24.66 30.66 30.66 24.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[18.66 18.66 24.66 18.66 24.66 24.66 18.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'addr');\ncolor('black');port_label('input',3," "'en');\ncolor('black');port_label('output',1,'q');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Delay" SID "12392" Ports [1, 1] Position [705, 441, 730, 469] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "25,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 " "17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33" " 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('blac" "k');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "12393" Position [210, 280, 300, 300] ZOrder -9 ShowName off GotoTag "ltsCorr_dAddr" TagVisibility "scoped" } Block { BlockType From Name "From1" SID "12394" Position [210, 340, 300, 360] ZOrder -9 ShowName off GotoTag "ltsCorr_cAddr" TagVisibility "scoped" } Block { BlockType From Name "From2" SID "12395" Position [210, 380, 300, 400] ZOrder -9 ShowName off GotoTag "ltsCorr_ld" TagVisibility "scoped" } Block { BlockType Reference Name "Gateway Out1" SID "12396" Ports [1, 1] Position [745, 615, 780, 625] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "12397" Ports [1, 1] Position [745, 630, 780, 640] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "12398" Ports [1, 1] Position [745, 645, 780, 655] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Ld" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "12399" Ports [1, 1] Position [745, 660, 780, 670] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "12400" Ports [1, 1] Position [745, 675, 780, 685] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "12401" Ports [1, 1] Position [745, 570, 780, 580] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X In" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "12402" Ports [1, 1] Position [745, 585, 780, 595] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "12403" Ports [1, 1] Position [745, 600, 780, 610] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X Vin" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType SubSystem Name "MAC" SID "12404" Ports [4, 2] Position [575, 279, 660, 376] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "MAC" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "a" SID "12405" Position [35, 143, 65, 157] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "coeff" SID "12406" Position [35, 108, 65, 122] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "ld" SID "12407" Position [35, 178, 65, 192] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "rst" SID "12408" Position [35, 233, 65, 247] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub" SID "12409" Ports [3, 1] Position [340, 113, 385, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition or Subtraction" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Signed (2's comp)" n_bits "long_cor_acc_n_bits" bin_pt "0" quantization "Truncate" overflow "Flag as error" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[2 0 0 4 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,344" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,3,1,white,blue,0,02f64c57,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('input',3,'su" "b');\ncolor('black');port_label('output',1,'\\bf{a \\pm b}','texmode','on');\nfprintf('','COMMENT: end icon text" "');\n" } Block { BlockType Reference Name "Gateway Out1" SID "12410" Ports [1, 1] Position [475, 450, 510, 460] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out2" SID "12411" Ports [1, 1] Position [475, 465, 510, 475] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out3" SID "12412" Ports [1, 1] Position [475, 480, 510, 490] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out6" SID "12413" Ports [1, 1] Position [475, 405, 510, 415] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out7" SID "12414" Ports [1, 1] Position [475, 420, 510, 430] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out8" SID "12415" Ports [1, 1] Position [475, 435, 510, 445] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "12416" Ports [2, 1] Position [345, 30, 385, 70] BlockMirror on NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,40,2,1,white,blue,0,140cc11c,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'" "q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "12417" Ports [2, 1] Position [465, 110, 495, 210] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,100,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 100 100 0 ],[0.77 0." "82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 100 100 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[54.44 " "54.44 58.44 54.44 58.44 58.44 58.44 54.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[50.44 50.44 54.44 54" ".44 50.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[46.44 46.44 50.44 50.44 46.44 ],[1 1 1 ])" ";\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[42.44 42.44 46.44 42.44 46.44 46.44 42.44 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\nco" "lor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc2" SID "12418" Ports [1, 1] Position [265, 143, 290, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc3" SID "12419" Ports [1, 1] Position [135, 178, 160, 192] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "yn" SID "12420" Position [545, 153, 575, 167] IconDisplay "Port number" } Block { BlockType Outport Name "accrm" SID "12421" Position [520, 288, 550, 302] Port "2" IconDisplay "Port number" } Line { SrcBlock "rst" SrcPort 1 Points [90, 0] Branch { Points [0, 215] DstBlock "Gateway Out1" DstPort 1 } Branch { Points [255, 0; 0, -180] DstBlock "Register1" DstPort 2 } } Line { SrcBlock "Gateway Out3" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out2" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out1" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out6" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out7" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out8" SrcPort 1 Points [50, 0] } Line { SrcBlock "a" SrcPort 1 Points [140, 0] Branch { Points [0, 275] DstBlock "Gateway Out7" DstPort 1 } Branch { DstBlock "bc2" DstPort 1 } } Line { SrcBlock "AddSub" SrcPort 1 Points [0, 0; 5, 0] Branch { Points [0, 305] DstBlock "Gateway Out8" DstPort 1 } Branch { Points [40, 0] Branch { Points [0, 160] DstBlock "accrm" DstPort 1 } Branch { Points [0, -95] DstBlock "Register1" DstPort 1 } Branch { DstBlock "Register2" DstPort 1 } } } Line { SrcBlock "Register2" SrcPort 1 Points [15, 0] Branch { Points [0, 50; 110, 0; 0, 385; -260, 0; 0, -110] DstBlock "Gateway Out3" DstPort 1 } Branch { DstBlock "yn" DstPort 1 } } Line { SrcBlock "Register1" SrcPort 1 Points [-15, 0] DstBlock "AddSub" DstPort 1 } Line { SrcBlock "ld" SrcPort 1 Points [45, 0] Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } Branch { DstBlock "bc3" DstPort 1 } } Line { SrcBlock "bc3" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "bc2" SrcPort 1 DstBlock "AddSub" DstPort 3 } Line { SrcBlock "coeff" SrcPort 1 Points [95, 0; 0, 20; 50, 0] Branch { Points [0, 275] DstBlock "Gateway Out6" DstPort 1 } Branch { DstBlock "AddSub" DstPort 2 } } } } Block { BlockType Reference Name "ROM" SID "12422" Ports [1, 1] Position [440, 328, 490, 372] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/ROM" SourceType "Xilinx Single Port Read-Only Memory Block" depth "length(coef2)" initVector "coef2" distributed_mem "Distributed memory" rst off init_reg "0" en off latency "1" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "longCorr_coef_nbits" bin_pt "longCorr_coef_bp" preci_type "Single" exp_width "8" frac_width "24" dbl_ovrd off optimize "Area" use_rpm off xl_use_area off xl_area "[1 1 0 1 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,308" block_type "sprom" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,44,1,1,white,blue,0,bbc23d60,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 44 44 0 ]);\npatch([11.65 20.32 26.32 32.32 38.32 26.32 17.65 11.65 ],[28.66" " 28.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([17.65 26.32 20.32 11.65 17.65 ],[22.66 22.66 28." "66 28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([11.65 20.32 26.32 17.65 11.65 ],[16.66 16.66 22.66 22.66 16.66 ]" ",[1 1 1 ]);\npatch([17.65 38.32 32.32 26.32 20.32 11.65 17.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'addr');\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end" " icon text');\n" } Block { BlockType Outport Name "x_dly" SID "12423" Position [790, 178, 820, 192] IconDisplay "Port number" } Block { BlockType Outport Name "x_dly_vout" SID "12424" Position [790, 223, 820, 237] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "y" SID "12425" Position [790, 293, 820, 307] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "y_vout" SID "12426" Position [785, 448, 815, 462] Port "4" IconDisplay "Port number" } Line { Name "ROM Addr" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 Points [150, 0] } Line { Name "Corr Out" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 Points [150, 0] } Line { Name "Corr Ld" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 Points [150, 0] } Line { Name "ROM Out" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 Points [150, 0] } Line { Name "ASR Out" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 Points [150, 0] } Line { Name "X In" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 Points [150, 0] } Line { Name "ASR Addr" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 Points [150, 0] } Line { Name "X Vin" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 Points [150, 0] } Line { SrcBlock "Delay" SrcPort 1 DstBlock "y_vout" DstPort 1 } Line { SrcBlock "vin" SrcPort 1 Points [25, 0] Branch { Points [0, -80] DstBlock "x_dly_vout" DstPort 1 } Branch { Points [0, 100] Branch { Points [230, 0] DstBlock "MAC" DstPort 4 } Branch { Points [0, 195] DstBlock "Gateway Out8" DstPort 1 } } Branch { DstBlock "ASR" DstPort 3 } } Line { SrcBlock "x" SrcPort 1 Points [100, 0] Branch { Points [0, 305] DstBlock "Gateway Out6" DstPort 1 } Branch { DstBlock "ASR" DstPort 1 } } Line { SrcBlock "From" SrcPort 1 Points [90, 0] Branch { Points [0, 300] DstBlock "Gateway Out7" DstPort 1 } Branch { DstBlock "ASR" DstPort 2 } } Line { SrcBlock "From1" SrcPort 1 Points [5, 0] Branch { Points [0, 330] DstBlock "Gateway Out5" DstPort 1 } Branch { DstBlock "ROM" DstPort 1 } } Line { SrcBlock "ASR" SrcPort 1 Points [35, 0] Branch { Points [0, 330] DstBlock "Gateway Out1" DstPort 1 } Branch { Points [0, -105] DstBlock "x_dly" DstPort 1 } Branch { DstBlock "MAC" DstPort 1 } } Line { SrcBlock "MAC" SrcPort 1 Points [0, -5; 15, 0] Branch { Points [0, 365] DstBlock "Gateway Out4" DstPort 1 } Branch { DstBlock "y" DstPort 1 } } Line { SrcBlock "ROM" SrcPort 1 Points [5, 0] Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } Branch { Points [0, -35] DstBlock "MAC" DstPort 2 } } Line { SrcBlock "From2" SrcPort 1 Points [145, 0] Branch { Points [0, 260] DstBlock "Gateway Out3" DstPort 1 } Branch { Points [90, 0] Branch { Points [0, 65] DstBlock "Delay" DstPort 1 } Branch { Points [0, -50] Branch { Points [0, -90; 160, 0] } Branch { DstBlock "MAC" DstPort 3 } } } } } } Block { BlockType SubSystem Name "C6" SID "12427" Ports [4, 4] Position [845, 207, 915, 293] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskPromptString "Coefficients (all)|Sub-correlator Ind|Coef/correlator" MaskStyleString "edit,edit,edit" MaskVariables "h=@1;c_ind=@2;N=@3;" MaskTunableValueString "on,on,on" MaskCallbackString "||" MaskEnableString "on,on,on" MaskVisibilityString "on,on,on" MaskToolTipString "on,on,on" MaskInitialization "coef2 = h((c_ind*N+1) : (c_ind + 1)*N);" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "h|5|N" System { Name "C6" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "122" Block { BlockType Inport Name "x" SID "12428" Position [265, 263, 295, 277] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "vin" SID "12429" Position [270, 303, 300, 317] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "12430" Position [270, 458, 300, 472] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "12431" Position [270, 503, 300, 517] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "ASR" SID "12432" Ports [3, 1] Position [445, 260, 490, 320] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Addressable Shift Register" SourceType "Xilinx Addressable Shift Register Block" infoedit "Delay of configurable length. Any element in the delay line can be addressed and driven onto the" " output port.

Hardware notes: This block is implemented using SRL16s. If Virtex-4 or Spartan-3 device is " "used, multiple SRLC16s are cascaded together." infer_latency off depth "length(coef2)" initVector "[0]" en on dbl_ovrd off use_behavioral_HDL off Optimization "Resource" xl_use_area off xl_area "[1 0 0 2 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,401" block_type "addrsr" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,60,3,1,white,blue,0,f8ea6153,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 60 60 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 60 60 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[36.66 3" "6.66 42.66 36.66 42.66 42.66 42.66 36.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[30.66 30.66 36.66 " "36.66 30.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[24.66 24.66 30.66 30.66 24.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[18.66 18.66 24.66 18.66 24.66 24.66 18.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'addr');\ncolor('black');port_label('input',3," "'en');\ncolor('black');port_label('output',1,'q');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Delay" SID "12433" Ports [1, 1] Position [705, 441, 730, 469] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "25,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 " "17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33" " 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('blac" "k');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "12434" Position [210, 280, 300, 300] ZOrder -9 ShowName off GotoTag "ltsCorr_dAddr" TagVisibility "scoped" } Block { BlockType From Name "From1" SID "12435" Position [210, 340, 300, 360] ZOrder -9 ShowName off GotoTag "ltsCorr_cAddr" TagVisibility "scoped" } Block { BlockType From Name "From2" SID "12436" Position [210, 380, 300, 400] ZOrder -9 ShowName off GotoTag "ltsCorr_ld" TagVisibility "scoped" } Block { BlockType Reference Name "Gateway Out1" SID "12437" Ports [1, 1] Position [745, 615, 780, 625] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "12438" Ports [1, 1] Position [745, 630, 780, 640] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "12439" Ports [1, 1] Position [745, 645, 780, 655] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Ld" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "12440" Ports [1, 1] Position [745, 660, 780, 670] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "12441" Ports [1, 1] Position [745, 675, 780, 685] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "12442" Ports [1, 1] Position [745, 570, 780, 580] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X In" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "12443" Ports [1, 1] Position [745, 585, 780, 595] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "12444" Ports [1, 1] Position [745, 600, 780, 610] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X Vin" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType SubSystem Name "MAC" SID "12445" Ports [4, 2] Position [575, 279, 660, 376] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "MAC" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "a" SID "12446" Position [35, 143, 65, 157] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "coeff" SID "12447" Position [35, 108, 65, 122] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "ld" SID "12448" Position [35, 178, 65, 192] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "rst" SID "12449" Position [35, 233, 65, 247] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub" SID "12450" Ports [3, 1] Position [340, 113, 385, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition or Subtraction" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Signed (2's comp)" n_bits "long_cor_acc_n_bits" bin_pt "0" quantization "Truncate" overflow "Flag as error" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[2 0 0 4 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,344" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,3,1,white,blue,0,02f64c57,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('input',3,'su" "b');\ncolor('black');port_label('output',1,'\\bf{a \\pm b}','texmode','on');\nfprintf('','COMMENT: end icon text" "');\n" } Block { BlockType Reference Name "Gateway Out1" SID "12451" Ports [1, 1] Position [475, 450, 510, 460] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out2" SID "12452" Ports [1, 1] Position [475, 465, 510, 475] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out3" SID "12453" Ports [1, 1] Position [475, 480, 510, 490] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out6" SID "12454" Ports [1, 1] Position [475, 405, 510, 415] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out7" SID "12455" Ports [1, 1] Position [475, 420, 510, 430] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out8" SID "12456" Ports [1, 1] Position [475, 435, 510, 445] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "12457" Ports [2, 1] Position [345, 30, 385, 70] BlockMirror on NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,40,2,1,white,blue,0,140cc11c,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'" "q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "12458" Ports [2, 1] Position [465, 110, 495, 210] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,100,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 100 100 0 ],[0.77 0." "82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 100 100 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[54.44 " "54.44 58.44 54.44 58.44 58.44 58.44 54.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[50.44 50.44 54.44 54" ".44 50.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[46.44 46.44 50.44 50.44 46.44 ],[1 1 1 ])" ";\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[42.44 42.44 46.44 42.44 46.44 46.44 42.44 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\nco" "lor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc2" SID "12459" Ports [1, 1] Position [265, 143, 290, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc3" SID "12460" Ports [1, 1] Position [135, 178, 160, 192] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "yn" SID "12461" Position [545, 153, 575, 167] IconDisplay "Port number" } Block { BlockType Outport Name "accrm" SID "12462" Position [520, 288, 550, 302] Port "2" IconDisplay "Port number" } Line { SrcBlock "coeff" SrcPort 1 Points [95, 0; 0, 20; 50, 0] Branch { DstBlock "AddSub" DstPort 2 } Branch { Points [0, 275] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "bc2" SrcPort 1 DstBlock "AddSub" DstPort 3 } Line { SrcBlock "bc3" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "ld" SrcPort 1 Points [45, 0] Branch { DstBlock "bc3" DstPort 1 } Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "Register1" SrcPort 1 Points [-15, 0] DstBlock "AddSub" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 Points [15, 0] Branch { DstBlock "yn" DstPort 1 } Branch { Points [0, 50; 110, 0; 0, 385; -260, 0; 0, -110] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "AddSub" SrcPort 1 Points [0, 0; 5, 0] Branch { Points [40, 0] Branch { DstBlock "Register2" DstPort 1 } Branch { Points [0, -95] DstBlock "Register1" DstPort 1 } Branch { Points [0, 160] DstBlock "accrm" DstPort 1 } } Branch { Points [0, 305] DstBlock "Gateway Out8" DstPort 1 } } Line { SrcBlock "a" SrcPort 1 Points [140, 0] Branch { DstBlock "bc2" DstPort 1 } Branch { Points [0, 275] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "Gateway Out8" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out7" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out6" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out1" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out2" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out3" SrcPort 1 Points [50, 0] } Line { SrcBlock "rst" SrcPort 1 Points [90, 0] Branch { Points [255, 0; 0, -180] DstBlock "Register1" DstPort 2 } Branch { Points [0, 215] DstBlock "Gateway Out1" DstPort 1 } } } } Block { BlockType Reference Name "ROM" SID "12463" Ports [1, 1] Position [440, 328, 490, 372] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/ROM" SourceType "Xilinx Single Port Read-Only Memory Block" depth "length(coef2)" initVector "coef2" distributed_mem "Distributed memory" rst off init_reg "0" en off latency "1" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "longCorr_coef_nbits" bin_pt "longCorr_coef_bp" preci_type "Single" exp_width "8" frac_width "24" dbl_ovrd off optimize "Area" use_rpm off xl_use_area off xl_area "[1 1 0 1 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,308" block_type "sprom" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,44,1,1,white,blue,0,bbc23d60,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 44 44 0 ]);\npatch([11.65 20.32 26.32 32.32 38.32 26.32 17.65 11.65 ],[28.66" " 28.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([17.65 26.32 20.32 11.65 17.65 ],[22.66 22.66 28." "66 28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([11.65 20.32 26.32 17.65 11.65 ],[16.66 16.66 22.66 22.66 16.66 ]" ",[1 1 1 ]);\npatch([17.65 38.32 32.32 26.32 20.32 11.65 17.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'addr');\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end" " icon text');\n" } Block { BlockType Outport Name "x_dly" SID "12464" Position [790, 178, 820, 192] IconDisplay "Port number" } Block { BlockType Outport Name "x_dly_vout" SID "12465" Position [790, 223, 820, 237] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "y" SID "12466" Position [790, 293, 820, 307] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "y_vout" SID "12467" Position [785, 448, 815, 462] Port "4" IconDisplay "Port number" } Line { SrcBlock "From2" SrcPort 1 Points [145, 0] Branch { Points [90, 0] Branch { Points [0, -50] Branch { DstBlock "MAC" DstPort 3 } Branch { Points [0, -90; 160, 0] } } Branch { Points [0, 65] DstBlock "Delay" DstPort 1 } } Branch { Points [0, 260] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "ROM" SrcPort 1 Points [5, 0] Branch { Points [0, -35] DstBlock "MAC" DstPort 2 } Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "MAC" SrcPort 1 Points [0, -5; 15, 0] Branch { DstBlock "y" DstPort 1 } Branch { Points [0, 365] DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "ASR" SrcPort 1 Points [35, 0] Branch { DstBlock "MAC" DstPort 1 } Branch { Points [0, -105] DstBlock "x_dly" DstPort 1 } Branch { Points [0, 330] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "From1" SrcPort 1 Points [5, 0] Branch { DstBlock "ROM" DstPort 1 } Branch { Points [0, 330] DstBlock "Gateway Out5" DstPort 1 } } Line { SrcBlock "From" SrcPort 1 Points [90, 0] Branch { DstBlock "ASR" DstPort 2 } Branch { Points [0, 300] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "x" SrcPort 1 Points [100, 0] Branch { DstBlock "ASR" DstPort 1 } Branch { Points [0, 305] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "vin" SrcPort 1 Points [25, 0] Branch { DstBlock "ASR" DstPort 3 } Branch { Points [0, 100] Branch { Points [0, 195] DstBlock "Gateway Out8" DstPort 1 } Branch { Points [230, 0] DstBlock "MAC" DstPort 4 } } Branch { Points [0, -80] DstBlock "x_dly_vout" DstPort 1 } } Line { SrcBlock "Delay" SrcPort 1 DstBlock "y_vout" DstPort 1 } Line { Name "X Vin" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 Points [150, 0] } Line { Name "ASR Addr" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 Points [150, 0] } Line { Name "X In" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 Points [150, 0] } Line { Name "ASR Out" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 Points [150, 0] } Line { Name "ROM Out" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 Points [150, 0] } Line { Name "Corr Ld" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 Points [150, 0] } Line { Name "Corr Out" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 Points [150, 0] } Line { Name "ROM Addr" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 Points [150, 0] } } } Block { BlockType SubSystem Name "C7" SID "12468" Ports [4, 4] Position [950, 207, 1020, 293] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskPromptString "Coefficients (all)|Sub-correlator Ind|Coef/correlator" MaskStyleString "edit,edit,edit" MaskVariables "h=@1;c_ind=@2;N=@3;" MaskTunableValueString "on,on,on" MaskCallbackString "||" MaskEnableString "on,on,on" MaskVisibilityString "on,on,on" MaskToolTipString "on,on,on" MaskInitialization "coef2 = h((c_ind*N+1) : (c_ind + 1)*N);" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "h|6|N" System { Name "C7" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "122" Block { BlockType Inport Name "x" SID "12469" Position [265, 263, 295, 277] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "vin" SID "12470" Position [270, 303, 300, 317] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "12471" Position [270, 458, 300, 472] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "12472" Position [270, 503, 300, 517] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "ASR" SID "12473" Ports [3, 1] Position [445, 260, 490, 320] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Addressable Shift Register" SourceType "Xilinx Addressable Shift Register Block" infoedit "Delay of configurable length. Any element in the delay line can be addressed and driven onto the" " output port.

Hardware notes: This block is implemented using SRL16s. If Virtex-4 or Spartan-3 device is " "used, multiple SRLC16s are cascaded together." infer_latency off depth "length(coef2)" initVector "[0]" en on dbl_ovrd off use_behavioral_HDL off Optimization "Resource" xl_use_area off xl_area "[1 0 0 2 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,401" block_type "addrsr" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,60,3,1,white,blue,0,f8ea6153,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 60 60 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 60 60 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[36.66 3" "6.66 42.66 36.66 42.66 42.66 42.66 36.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[30.66 30.66 36.66 " "36.66 30.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[24.66 24.66 30.66 30.66 24.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[18.66 18.66 24.66 18.66 24.66 24.66 18.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'addr');\ncolor('black');port_label('input',3," "'en');\ncolor('black');port_label('output',1,'q');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Delay" SID "12474" Ports [1, 1] Position [705, 441, 730, 469] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "25,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 " "17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33" " 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('blac" "k');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "12475" Position [210, 280, 300, 300] ZOrder -9 ShowName off GotoTag "ltsCorr_dAddr" TagVisibility "scoped" } Block { BlockType From Name "From1" SID "12476" Position [210, 340, 300, 360] ZOrder -9 ShowName off GotoTag "ltsCorr_cAddr" TagVisibility "scoped" } Block { BlockType From Name "From2" SID "12477" Position [210, 380, 300, 400] ZOrder -9 ShowName off GotoTag "ltsCorr_ld" TagVisibility "scoped" } Block { BlockType Reference Name "Gateway Out1" SID "12478" Ports [1, 1] Position [745, 615, 780, 625] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "12479" Ports [1, 1] Position [745, 630, 780, 640] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "12480" Ports [1, 1] Position [745, 645, 780, 655] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Ld" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "12481" Ports [1, 1] Position [745, 660, 780, 670] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "12482" Ports [1, 1] Position [745, 675, 780, 685] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "12483" Ports [1, 1] Position [745, 570, 780, 580] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X In" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "12484" Ports [1, 1] Position [745, 585, 780, 595] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "12485" Ports [1, 1] Position [745, 600, 780, 610] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X Vin" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType SubSystem Name "MAC" SID "12486" Ports [4, 2] Position [575, 279, 660, 376] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "MAC" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "a" SID "12487" Position [35, 143, 65, 157] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "coeff" SID "12488" Position [35, 108, 65, 122] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "ld" SID "12489" Position [35, 178, 65, 192] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "rst" SID "12490" Position [35, 233, 65, 247] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub" SID "12491" Ports [3, 1] Position [340, 113, 385, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition or Subtraction" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Signed (2's comp)" n_bits "long_cor_acc_n_bits" bin_pt "0" quantization "Truncate" overflow "Flag as error" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[2 0 0 4 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,344" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,3,1,white,blue,0,02f64c57,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('input',3,'su" "b');\ncolor('black');port_label('output',1,'\\bf{a \\pm b}','texmode','on');\nfprintf('','COMMENT: end icon text" "');\n" } Block { BlockType Reference Name "Gateway Out1" SID "12492" Ports [1, 1] Position [475, 450, 510, 460] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out2" SID "12493" Ports [1, 1] Position [475, 465, 510, 475] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out3" SID "12494" Ports [1, 1] Position [475, 480, 510, 490] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out6" SID "12495" Ports [1, 1] Position [475, 405, 510, 415] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out7" SID "12496" Ports [1, 1] Position [475, 420, 510, 430] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out8" SID "12497" Ports [1, 1] Position [475, 435, 510, 445] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "12498" Ports [2, 1] Position [345, 30, 385, 70] BlockMirror on NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,40,2,1,white,blue,0,140cc11c,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'" "q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "12499" Ports [2, 1] Position [465, 110, 495, 210] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,100,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 100 100 0 ],[0.77 0." "82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 100 100 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[54.44 " "54.44 58.44 54.44 58.44 58.44 58.44 54.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[50.44 50.44 54.44 54" ".44 50.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[46.44 46.44 50.44 50.44 46.44 ],[1 1 1 ])" ";\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[42.44 42.44 46.44 42.44 46.44 46.44 42.44 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\nco" "lor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc2" SID "12500" Ports [1, 1] Position [265, 143, 290, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc3" SID "12501" Ports [1, 1] Position [135, 178, 160, 192] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "yn" SID "12502" Position [545, 153, 575, 167] IconDisplay "Port number" } Block { BlockType Outport Name "accrm" SID "12503" Position [520, 288, 550, 302] Port "2" IconDisplay "Port number" } Line { SrcBlock "rst" SrcPort 1 Points [90, 0] Branch { Points [0, 215] DstBlock "Gateway Out1" DstPort 1 } Branch { Points [255, 0; 0, -180] DstBlock "Register1" DstPort 2 } } Line { SrcBlock "Gateway Out3" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out2" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out1" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out6" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out7" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out8" SrcPort 1 Points [50, 0] } Line { SrcBlock "a" SrcPort 1 Points [140, 0] Branch { Points [0, 275] DstBlock "Gateway Out7" DstPort 1 } Branch { DstBlock "bc2" DstPort 1 } } Line { SrcBlock "AddSub" SrcPort 1 Points [0, 0; 5, 0] Branch { Points [0, 305] DstBlock "Gateway Out8" DstPort 1 } Branch { Points [40, 0] Branch { Points [0, 160] DstBlock "accrm" DstPort 1 } Branch { Points [0, -95] DstBlock "Register1" DstPort 1 } Branch { DstBlock "Register2" DstPort 1 } } } Line { SrcBlock "Register2" SrcPort 1 Points [15, 0] Branch { Points [0, 50; 110, 0; 0, 385; -260, 0; 0, -110] DstBlock "Gateway Out3" DstPort 1 } Branch { DstBlock "yn" DstPort 1 } } Line { SrcBlock "Register1" SrcPort 1 Points [-15, 0] DstBlock "AddSub" DstPort 1 } Line { SrcBlock "ld" SrcPort 1 Points [45, 0] Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } Branch { DstBlock "bc3" DstPort 1 } } Line { SrcBlock "bc3" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "bc2" SrcPort 1 DstBlock "AddSub" DstPort 3 } Line { SrcBlock "coeff" SrcPort 1 Points [95, 0; 0, 20; 50, 0] Branch { Points [0, 275] DstBlock "Gateway Out6" DstPort 1 } Branch { DstBlock "AddSub" DstPort 2 } } } } Block { BlockType Reference Name "ROM" SID "12504" Ports [1, 1] Position [440, 328, 490, 372] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/ROM" SourceType "Xilinx Single Port Read-Only Memory Block" depth "length(coef2)" initVector "coef2" distributed_mem "Distributed memory" rst off init_reg "0" en off latency "1" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "longCorr_coef_nbits" bin_pt "longCorr_coef_bp" preci_type "Single" exp_width "8" frac_width "24" dbl_ovrd off optimize "Area" use_rpm off xl_use_area off xl_area "[1 1 0 1 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,308" block_type "sprom" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,44,1,1,white,blue,0,bbc23d60,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 44 44 0 ]);\npatch([11.65 20.32 26.32 32.32 38.32 26.32 17.65 11.65 ],[28.66" " 28.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([17.65 26.32 20.32 11.65 17.65 ],[22.66 22.66 28." "66 28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([11.65 20.32 26.32 17.65 11.65 ],[16.66 16.66 22.66 22.66 16.66 ]" ",[1 1 1 ]);\npatch([17.65 38.32 32.32 26.32 20.32 11.65 17.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'addr');\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end" " icon text');\n" } Block { BlockType Outport Name "x_dly" SID "12505" Position [790, 178, 820, 192] IconDisplay "Port number" } Block { BlockType Outport Name "x_dly_vout" SID "12506" Position [790, 223, 820, 237] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "y" SID "12507" Position [790, 293, 820, 307] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "y_vout" SID "12508" Position [785, 448, 815, 462] Port "4" IconDisplay "Port number" } Line { Name "ROM Addr" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 Points [150, 0] } Line { Name "Corr Out" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 Points [150, 0] } Line { Name "Corr Ld" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 Points [150, 0] } Line { Name "ROM Out" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 Points [150, 0] } Line { Name "ASR Out" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 Points [150, 0] } Line { Name "X In" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 Points [150, 0] } Line { Name "ASR Addr" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 Points [150, 0] } Line { Name "X Vin" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 Points [150, 0] } Line { SrcBlock "Delay" SrcPort 1 DstBlock "y_vout" DstPort 1 } Line { SrcBlock "vin" SrcPort 1 Points [25, 0] Branch { Points [0, -80] DstBlock "x_dly_vout" DstPort 1 } Branch { Points [0, 100] Branch { Points [230, 0] DstBlock "MAC" DstPort 4 } Branch { Points [0, 195] DstBlock "Gateway Out8" DstPort 1 } } Branch { DstBlock "ASR" DstPort 3 } } Line { SrcBlock "x" SrcPort 1 Points [100, 0] Branch { Points [0, 305] DstBlock "Gateway Out6" DstPort 1 } Branch { DstBlock "ASR" DstPort 1 } } Line { SrcBlock "From" SrcPort 1 Points [90, 0] Branch { Points [0, 300] DstBlock "Gateway Out7" DstPort 1 } Branch { DstBlock "ASR" DstPort 2 } } Line { SrcBlock "From1" SrcPort 1 Points [5, 0] Branch { Points [0, 330] DstBlock "Gateway Out5" DstPort 1 } Branch { DstBlock "ROM" DstPort 1 } } Line { SrcBlock "ASR" SrcPort 1 Points [35, 0] Branch { Points [0, 330] DstBlock "Gateway Out1" DstPort 1 } Branch { Points [0, -105] DstBlock "x_dly" DstPort 1 } Branch { DstBlock "MAC" DstPort 1 } } Line { SrcBlock "MAC" SrcPort 1 Points [0, -5; 15, 0] Branch { Points [0, 365] DstBlock "Gateway Out4" DstPort 1 } Branch { DstBlock "y" DstPort 1 } } Line { SrcBlock "ROM" SrcPort 1 Points [5, 0] Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } Branch { Points [0, -35] DstBlock "MAC" DstPort 2 } } Line { SrcBlock "From2" SrcPort 1 Points [145, 0] Branch { Points [0, 260] DstBlock "Gateway Out3" DstPort 1 } Branch { Points [90, 0] Branch { Points [0, 65] DstBlock "Delay" DstPort 1 } Branch { Points [0, -50] Branch { Points [0, -90; 160, 0] } Branch { DstBlock "MAC" DstPort 3 } } } } } } Block { BlockType SubSystem Name "C8" SID "12509" Ports [4, 4] Position [1060, 207, 1130, 293] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskPromptString "Coefficients (all)|Sub-correlator Ind|Coef/correlator" MaskStyleString "edit,edit,edit" MaskVariables "h=@1;c_ind=@2;N=@3;" MaskTunableValueString "on,on,on" MaskCallbackString "||" MaskEnableString "on,on,on" MaskVisibilityString "on,on,on" MaskToolTipString "on,on,on" MaskInitialization "coef2 = h((c_ind*N+1) : (c_ind + 1)*N);" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "h|7|N" System { Name "C8" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "122" Block { BlockType Inport Name "x" SID "12510" Position [265, 263, 295, 277] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "vin" SID "12511" Position [270, 303, 300, 317] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "12512" Position [270, 458, 300, 472] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "12513" Position [270, 503, 300, 517] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "ASR" SID "12514" Ports [3, 1] Position [445, 260, 490, 320] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Addressable Shift Register" SourceType "Xilinx Addressable Shift Register Block" infoedit "Delay of configurable length. Any element in the delay line can be addressed and driven onto the" " output port.

Hardware notes: This block is implemented using SRL16s. If Virtex-4 or Spartan-3 device is " "used, multiple SRLC16s are cascaded together." infer_latency off depth "length(coef2)" initVector "[0]" en on dbl_ovrd off use_behavioral_HDL off Optimization "Resource" xl_use_area off xl_area "[1 0 0 2 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,401" block_type "addrsr" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,60,3,1,white,blue,0,f8ea6153,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 60 60 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 60 60 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[36.66 3" "6.66 42.66 36.66 42.66 42.66 42.66 36.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[30.66 30.66 36.66 " "36.66 30.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[24.66 24.66 30.66 30.66 24.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[18.66 18.66 24.66 18.66 24.66 24.66 18.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'addr');\ncolor('black');port_label('input',3," "'en');\ncolor('black');port_label('output',1,'q');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Delay" SID "12515" Ports [1, 1] Position [705, 441, 730, 469] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "25,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 " "17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33" " 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('blac" "k');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "12516" Position [210, 280, 300, 300] ZOrder -9 ShowName off GotoTag "ltsCorr_dAddr" TagVisibility "scoped" } Block { BlockType From Name "From1" SID "12517" Position [210, 340, 300, 360] ZOrder -9 ShowName off GotoTag "ltsCorr_cAddr" TagVisibility "scoped" } Block { BlockType From Name "From2" SID "12518" Position [210, 380, 300, 400] ZOrder -9 ShowName off GotoTag "ltsCorr_ld" TagVisibility "scoped" } Block { BlockType Reference Name "Gateway Out1" SID "12519" Ports [1, 1] Position [745, 615, 780, 625] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "12520" Ports [1, 1] Position [745, 630, 780, 640] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "12521" Ports [1, 1] Position [745, 645, 780, 655] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Ld" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "12522" Ports [1, 1] Position [745, 660, 780, 670] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "12523" Ports [1, 1] Position [745, 675, 780, 685] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "12524" Ports [1, 1] Position [745, 570, 780, 580] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X In" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "12525" Ports [1, 1] Position [745, 585, 780, 595] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "12526" Ports [1, 1] Position [745, 600, 780, 610] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X Vin" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType SubSystem Name "MAC" SID "12527" Ports [4, 2] Position [575, 279, 660, 376] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "MAC" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "a" SID "12528" Position [35, 143, 65, 157] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "coeff" SID "12529" Position [35, 108, 65, 122] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "ld" SID "12530" Position [35, 178, 65, 192] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "rst" SID "12531" Position [35, 233, 65, 247] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub" SID "12532" Ports [3, 1] Position [340, 113, 385, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition or Subtraction" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Signed (2's comp)" n_bits "long_cor_acc_n_bits" bin_pt "0" quantization "Truncate" overflow "Flag as error" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[2 0 0 4 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,344" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,3,1,white,blue,0,02f64c57,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('input',3,'su" "b');\ncolor('black');port_label('output',1,'\\bf{a \\pm b}','texmode','on');\nfprintf('','COMMENT: end icon text" "');\n" } Block { BlockType Reference Name "Gateway Out1" SID "12533" Ports [1, 1] Position [475, 450, 510, 460] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out2" SID "12534" Ports [1, 1] Position [475, 465, 510, 475] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out3" SID "12535" Ports [1, 1] Position [475, 480, 510, 490] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out6" SID "12536" Ports [1, 1] Position [475, 405, 510, 415] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out7" SID "12537" Ports [1, 1] Position [475, 420, 510, 430] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out8" SID "12538" Ports [1, 1] Position [475, 435, 510, 445] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "12539" Ports [2, 1] Position [345, 30, 385, 70] BlockMirror on NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,40,2,1,white,blue,0,140cc11c,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'" "q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "12540" Ports [2, 1] Position [465, 110, 495, 210] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,100,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 100 100 0 ],[0.77 0." "82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 100 100 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[54.44 " "54.44 58.44 54.44 58.44 58.44 58.44 54.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[50.44 50.44 54.44 54" ".44 50.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[46.44 46.44 50.44 50.44 46.44 ],[1 1 1 ])" ";\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[42.44 42.44 46.44 42.44 46.44 46.44 42.44 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\nco" "lor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc2" SID "12541" Ports [1, 1] Position [265, 143, 290, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc3" SID "12542" Ports [1, 1] Position [135, 178, 160, 192] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "yn" SID "12543" Position [545, 153, 575, 167] IconDisplay "Port number" } Block { BlockType Outport Name "accrm" SID "12544" Position [520, 288, 550, 302] Port "2" IconDisplay "Port number" } Line { SrcBlock "coeff" SrcPort 1 Points [95, 0; 0, 20; 50, 0] Branch { DstBlock "AddSub" DstPort 2 } Branch { Points [0, 275] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "bc2" SrcPort 1 DstBlock "AddSub" DstPort 3 } Line { SrcBlock "bc3" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "ld" SrcPort 1 Points [45, 0] Branch { DstBlock "bc3" DstPort 1 } Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "Register1" SrcPort 1 Points [-15, 0] DstBlock "AddSub" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 Points [15, 0] Branch { DstBlock "yn" DstPort 1 } Branch { Points [0, 50; 110, 0; 0, 385; -260, 0; 0, -110] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "AddSub" SrcPort 1 Points [0, 0; 5, 0] Branch { Points [40, 0] Branch { DstBlock "Register2" DstPort 1 } Branch { Points [0, -95] DstBlock "Register1" DstPort 1 } Branch { Points [0, 160] DstBlock "accrm" DstPort 1 } } Branch { Points [0, 305] DstBlock "Gateway Out8" DstPort 1 } } Line { SrcBlock "a" SrcPort 1 Points [140, 0] Branch { DstBlock "bc2" DstPort 1 } Branch { Points [0, 275] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "Gateway Out8" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out7" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out6" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out1" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out2" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out3" SrcPort 1 Points [50, 0] } Line { SrcBlock "rst" SrcPort 1 Points [90, 0] Branch { Points [255, 0; 0, -180] DstBlock "Register1" DstPort 2 } Branch { Points [0, 215] DstBlock "Gateway Out1" DstPort 1 } } } } Block { BlockType Reference Name "ROM" SID "12545" Ports [1, 1] Position [440, 328, 490, 372] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/ROM" SourceType "Xilinx Single Port Read-Only Memory Block" depth "length(coef2)" initVector "coef2" distributed_mem "Distributed memory" rst off init_reg "0" en off latency "1" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "longCorr_coef_nbits" bin_pt "longCorr_coef_bp" preci_type "Single" exp_width "8" frac_width "24" dbl_ovrd off optimize "Area" use_rpm off xl_use_area off xl_area "[1 1 0 1 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,308" block_type "sprom" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,44,1,1,white,blue,0,bbc23d60,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 44 44 0 ]);\npatch([11.65 20.32 26.32 32.32 38.32 26.32 17.65 11.65 ],[28.66" " 28.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([17.65 26.32 20.32 11.65 17.65 ],[22.66 22.66 28." "66 28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([11.65 20.32 26.32 17.65 11.65 ],[16.66 16.66 22.66 22.66 16.66 ]" ",[1 1 1 ]);\npatch([17.65 38.32 32.32 26.32 20.32 11.65 17.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'addr');\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end" " icon text');\n" } Block { BlockType Outport Name "x_dly" SID "12546" Position [790, 178, 820, 192] IconDisplay "Port number" } Block { BlockType Outport Name "x_dly_vout" SID "12547" Position [790, 223, 820, 237] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "y" SID "12548" Position [790, 293, 820, 307] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "y_vout" SID "12549" Position [785, 448, 815, 462] Port "4" IconDisplay "Port number" } Line { SrcBlock "From2" SrcPort 1 Points [145, 0] Branch { Points [90, 0] Branch { Points [0, -50] Branch { DstBlock "MAC" DstPort 3 } Branch { Points [0, -90; 160, 0] } } Branch { Points [0, 65] DstBlock "Delay" DstPort 1 } } Branch { Points [0, 260] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "ROM" SrcPort 1 Points [5, 0] Branch { Points [0, -35] DstBlock "MAC" DstPort 2 } Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "MAC" SrcPort 1 Points [0, -5; 15, 0] Branch { DstBlock "y" DstPort 1 } Branch { Points [0, 365] DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "ASR" SrcPort 1 Points [35, 0] Branch { DstBlock "MAC" DstPort 1 } Branch { Points [0, -105] DstBlock "x_dly" DstPort 1 } Branch { Points [0, 330] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "From1" SrcPort 1 Points [5, 0] Branch { DstBlock "ROM" DstPort 1 } Branch { Points [0, 330] DstBlock "Gateway Out5" DstPort 1 } } Line { SrcBlock "From" SrcPort 1 Points [90, 0] Branch { DstBlock "ASR" DstPort 2 } Branch { Points [0, 300] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "x" SrcPort 1 Points [100, 0] Branch { DstBlock "ASR" DstPort 1 } Branch { Points [0, 305] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "vin" SrcPort 1 Points [25, 0] Branch { DstBlock "ASR" DstPort 3 } Branch { Points [0, 100] Branch { Points [0, 195] DstBlock "Gateway Out8" DstPort 1 } Branch { Points [230, 0] DstBlock "MAC" DstPort 4 } } Branch { Points [0, -80] DstBlock "x_dly_vout" DstPort 1 } } Line { SrcBlock "Delay" SrcPort 1 DstBlock "y_vout" DstPort 1 } Line { Name "X Vin" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 Points [150, 0] } Line { Name "ASR Addr" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 Points [150, 0] } Line { Name "X In" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 Points [150, 0] } Line { Name "ASR Out" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 Points [150, 0] } Line { Name "ROM Out" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 Points [150, 0] } Line { Name "Corr Ld" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 Points [150, 0] } Line { Name "Corr Out" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 Points [150, 0] } Line { Name "ROM Addr" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 Points [150, 0] } } } Block { BlockType Reference Name "Gateway Out1" SID "12550" Ports [1, 1] Position [1195, 75, 1230, 85] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out10" SID "12551" Ports [1, 1] Position [1195, 120, 1230, 130] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out11" SID "12552" Ports [1, 1] Position [1195, 135, 1230, 145] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out12" SID "12553" Ports [1, 1] Position [1195, 150, 1230, 160] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out13" SID "12554" Ports [1, 1] Position [1195, 165, 1230, 175] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out14" SID "12555" Ports [1, 1] Position [1225, 180, 1260, 190] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out2" SID "12556" Ports [1, 1] Position [740, 720, 775, 730] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out3" SID "12557" Ports [1, 1] Position [740, 690, 775, 700] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out4" SID "12558" Ports [1, 1] Position [740, 705, 775, 715] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out5" SID "12559" Ports [1, 1] Position [740, 735, 775, 745] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out6" SID "12560" Ports [1, 1] Position [1195, 45, 1230, 55] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out7" SID "12561" Ports [1, 1] Position [1195, 60, 1230, 70] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out8" SID "12562" Ports [1, 1] Position [1195, 90, 1230, 100] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out9" SID "12563" Ports [1, 1] Position [1195, 105, 1230, 115] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Outport Name "y" SID "12564" Position [1290, 568, 1320, 582] IconDisplay "Port number" } Block { BlockType Outport Name "y_vout" SID "12565" Position [1290, 523, 1320, 537] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "x_dly" SID "12566" Position [1260, 213, 1290, 227] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "x_dly_vout" SID "12567" Position [1260, 253, 1290, 267] Port "4" IconDisplay "Port number" } Line { SrcBlock "C8" SrcPort 2 Points [110, 0] DstBlock "x_dly_vout" DstPort 1 } Line { SrcBlock "C8" SrcPort 1 DstBlock "x_dly" DstPort 1 } Line { SrcBlock "Gateway Out14" SrcPort 1 Points [20, 0] } Line { SrcBlock "Gateway Out13" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out12" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out11" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out10" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out9" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out1" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out8" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out6" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out7" SrcPort 1 Points [50, 0] } Line { SrcBlock "C8" SrcPort 4 Points [40, 0; 0, 250] DstBlock "y_vout" DstPort 1 } Line { SrcBlock "AddSub4" SrcPort 1 Points [45, 0] Branch { Points [155, 0] Branch { Points [0, -390] DstBlock "Gateway Out14" DstPort 1 } Branch { DstBlock "y" DstPort 1 } } Branch { Points [0, 75; -400, 0; 0, 90] DstBlock "Gateway Out5" DstPort 1 } } Line { SrcBlock "AddSub1" SrcPort 1 Points [0, 60] DstBlock "AddSub4" DstPort 1 } Line { SrcBlock "AddSub13" SrcPort 1 Points [0, 85] DstBlock "AddSub4" DstPort 2 } Line { SrcBlock "AddSub7" SrcPort 1 Points [0, 35] DstBlock "AddSub1" DstPort 2 } Line { SrcBlock "AddSub6" SrcPort 1 DstBlock "AddSub1" DstPort 1 } Line { SrcBlock "C7" SrcPort 3 Points [20, 0] Branch { Points [0, -105] DstBlock "Gateway Out12" DstPort 1 } Branch { Points [0, 65; 75, 0] DstBlock "AddSub7" DstPort 1 } } Line { SrcBlock "C8" SrcPort 3 Points [10, 0] Branch { Points [0, -90] DstBlock "Gateway Out13" DstPort 1 } Branch { DstBlock "AddSub7" DstPort 2 } } Line { SrcBlock "C5" SrcPort 3 Points [10, 0] Branch { Points [0, -135] DstBlock "Gateway Out10" DstPort 1 } Branch { Points [0, 70; 85, 0] DstBlock "AddSub6" DstPort 1 } } Line { SrcBlock "C6" SrcPort 3 Points [15, 0] Branch { Points [0, -120] DstBlock "Gateway Out11" DstPort 1 } Branch { DstBlock "AddSub6" DstPort 2 } } Line { SrcBlock "C7" SrcPort 2 DstBlock "C8" DstPort 2 } Line { SrcBlock "C7" SrcPort 1 DstBlock "C8" DstPort 1 } Line { SrcBlock "C6" SrcPort 2 DstBlock "C7" DstPort 2 } Line { SrcBlock "C6" SrcPort 1 DstBlock "C7" DstPort 1 } Line { SrcBlock "C5" SrcPort 2 DstBlock "C6" DstPort 2 } Line { SrcBlock "C5" SrcPort 1 DstBlock "C6" DstPort 1 } Line { SrcBlock "C4" SrcPort 3 Points [15, 0] Branch { Points [0, -150] DstBlock "Gateway Out9" DstPort 1 } Branch { DstBlock "AddSub12" DstPort 2 } } Line { SrcBlock "C4" SrcPort 2 DstBlock "C5" DstPort 2 } Line { SrcBlock "C4" SrcPort 1 DstBlock "C5" DstPort 1 } Line { SrcBlock "C3" SrcPort 3 Points [20, 0] Branch { Points [0, -165] DstBlock "Gateway Out8" DstPort 1 } Branch { Points [0, 65; 80, 0] DstBlock "AddSub12" DstPort 1 } } Line { SrcBlock "C3" SrcPort 2 DstBlock "C4" DstPort 2 } Line { SrcBlock "C3" SrcPort 1 DstBlock "C4" DstPort 1 } Line { SrcBlock "C1" SrcPort 3 Points [15, 0] Branch { Points [0, -195] DstBlock "Gateway Out7" DstPort 1 } Branch { Points [0, 55] Branch { Points [0, 410] DstBlock "Gateway Out2" DstPort 1 } Branch { Points [0, 5; 95, 0] DstBlock "AddSub5" DstPort 1 } } } Line { SrcBlock "C2" SrcPort 3 Points [20, 0] Branch { Points [0, -180] DstBlock "Gateway Out1" DstPort 1 } Branch { DstBlock "AddSub5" DstPort 2 } } Line { SrcBlock "C2" SrcPort 2 DstBlock "C3" DstPort 2 } Line { SrcBlock "C2" SrcPort 1 DstBlock "C3" DstPort 1 } Line { SrcBlock "C1" SrcPort 2 DstBlock "C2" DstPort 2 } Line { SrcBlock "C1" SrcPort 1 DstBlock "C2" DstPort 1 } Line { SrcBlock "x_valid" SrcPort 1 Points [200, 0] Branch { Points [0, 450] DstBlock "Gateway Out4" DstPort 1 } Branch { Points [0, -20] DstBlock "C1" DstPort 2 } } Line { Points [780, 755; 50, 0] } Line { SrcBlock "Gateway Out2" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out5" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out3" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out4" SrcPort 1 Points [50, 0] } Line { SrcBlock "AddSub5" SrcPort 1 Points [0, 35] DstBlock "AddSub13" DstPort 1 } Line { SrcBlock "AddSub12" SrcPort 1 DstBlock "AddSub13" DstPort 2 } Line { SrcBlock "x" SrcPort 1 Points [210, 0] Branch { Points [0, -170] DstBlock "Gateway Out6" DstPort 1 } Branch { Points [0, 475] DstBlock "Gateway Out3" DstPort 1 } Branch { DstBlock "C1" DstPort 1 } } } } Block { BlockType SubSystem Name "C3" SID "12568" Ports [2, 4] Position [725, 168, 810, 237] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskPromptString "Coefficients/correlator|Coefficients|Input sample period" MaskStyleString "edit,edit,edit" MaskVariables "N=@1;h=@2;Ts_In=@3;" MaskTunableValueString "on,on,on" MaskCallbackString "||" MaskEnableString "on,on,on" MaskVisibilityString "on,on,on" MaskToolTipString "on,on,on" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "4|longCorr_coef_i(33:64)|4" System { Name "C3" Location [480, 85, 2304, 1455] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "156" Block { BlockType Inport Name "x" SID "12569" Position [35, 213, 65, 227] IconDisplay "Port number" } Block { BlockType Inport Name "x_valid" SID "12570" Position [35, 253, 65, 267] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub1" SID "12571" Ports [2, 1] Position [915, 455, 955, 495] BlockRotation 270 BlockMirror on NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "1" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[3 6 0 5 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,40,2,1,white,blue,0,e85d8a90,down,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bf{a + b}','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\ne" "wline\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub12" SID "12572" Ports [2, 1] Position [684, 360, 731, 400] BlockRotation 270 BlockMirror on NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "1" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[3 5 0 4 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "47,40,2,1,white,blue,0,e85d8a90,down,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 47 47 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 47 47 0 0 ],[0 0 40 40 0 ]);\npatch([11.875 19.1 24.1 29.1 34.1 24.1 16.875 11.875 ],[25.55 2" "5.55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([16.875 24.1 19.1 11.875 16.875 ],[20.55 20.55 25.5" "5 25.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([11.875 19.1 24.1 16.875 11.875 ],[15.55 15.55 20.55 20.55 15.55 ]" ",[1 1 1 ]);\npatch([16.875 34.1 29.1 24.1 19.1 11.875 16.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('b" "lack');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output'" ",1,'\\bf{a + b}','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(" "' \\newline\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub13" SID "12573" Ports [2, 1] Position [680, 455, 720, 495] BlockRotation 270 BlockMirror on NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "1" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[3 6 0 5 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,40,2,1,white,blue,0,e85d8a90,down,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bf{a + b}','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\ne" "wline\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub4" SID "12574" Ports [2, 1] Position [960, 549, 1000, 596] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "1" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[4 7 0 6 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,47,2,1,white,blue,0,e85d8a90,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 47 47 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 47 47 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[28.55 28." "55 33.55 28.55 33.55 33.55 33.55 28.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[23.55 23.55 28.55 2" "8.55 23.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[18.55 18.55 23.55 23.55 18.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[13.55 13.55 18.55 13.55 18.55 18.55 13.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bf{a + b}','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\ne" "wline\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub5" SID "12575" Ports [2, 1] Position [475, 360, 515, 400] BlockRotation 270 BlockMirror on NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "1" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[3 6 0 5 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,40,2,1,white,blue,0,e85d8a90,down,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bf{a + b}','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\ne" "wline\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub6" SID "12576" Ports [2, 1] Position [899, 360, 946, 400] BlockRotation 270 BlockMirror on NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "1" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[3 5 0 4 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "47,40,2,1,white,blue,0,e85d8a90,down,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 47 47 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 47 47 0 0 ],[0 0 40 40 0 ]);\npatch([11.875 19.1 24.1 29.1 34.1 24.1 16.875 11.875 ],[25.55 2" "5.55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([16.875 24.1 19.1 11.875 16.875 ],[20.55 20.55 25.5" "5 25.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([11.875 19.1 24.1 16.875 11.875 ],[15.55 15.55 20.55 20.55 15.55 ]" ",[1 1 1 ]);\npatch([16.875 34.1 29.1 24.1 19.1 11.875 16.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('b" "lack');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output'" ",1,'\\bf{a + b}','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(" "' \\newline\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub7" SID "12577" Ports [2, 1] Position [1109, 360, 1156, 400] BlockRotation 270 BlockMirror on NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "1" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[3 5 0 4 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "47,40,2,1,white,blue,0,e85d8a90,down,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 47 47 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 47 47 0 0 ],[0 0 40 40 0 ]);\npatch([11.875 19.1 24.1 29.1 34.1 24.1 16.875 11.875 ],[25.55 2" "5.55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([16.875 24.1 19.1 11.875 16.875 ],[20.55 20.55 25.5" "5 25.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([11.875 19.1 24.1 16.875 11.875 ],[15.55 15.55 20.55 20.55 15.55 ]" ",[1 1 1 ]);\npatch([16.875 34.1 29.1 24.1 19.1 11.875 16.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('b" "lack');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output'" ",1,'\\bf{a + b}','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(" "' \\newline\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "C1" SID "12578" Ports [4, 4] Position [300, 207, 370, 293] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskPromptString "Coefficients (all)|Sub-correlator Ind|Coef/correlator" MaskStyleString "edit,edit,edit" MaskVariables "h=@1;c_ind=@2;N=@3;" MaskTunableValueString "on,on,on" MaskCallbackString "||" MaskEnableString "on,on,on" MaskVisibilityString "on,on,on" MaskToolTipString "on,on,on" MaskInitialization "coef2 = h((c_ind*N+1) : (c_ind + 1)*N);" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "h|0|N" System { Name "C1" Location [480, 85, 2304, 1471] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "122" Block { BlockType Inport Name "x" SID "12579" Position [265, 263, 295, 277] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "vin" SID "12580" Position [270, 303, 300, 317] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "12581" Position [270, 458, 300, 472] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "12582" Position [270, 503, 300, 517] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "ASR" SID "12583" Ports [3, 1] Position [445, 260, 490, 320] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Addressable Shift Register" SourceType "Xilinx Addressable Shift Register Block" infoedit "Delay of configurable length. Any element in the delay line can be addressed and driven onto the" " output port.

Hardware notes: This block is implemented using SRL16s. If Virtex-4 or Spartan-3 device is " "used, multiple SRLC16s are cascaded together." infer_latency off depth "length(coef2)" initVector "[0]" en on dbl_ovrd off use_behavioral_HDL off Optimization "Resource" xl_use_area off xl_area "[1 0 0 2 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,401" block_type "addrsr" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,60,3,1,white,blue,0,f8ea6153,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 60 60 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 60 60 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[36.66 3" "6.66 42.66 36.66 42.66 42.66 42.66 36.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[30.66 30.66 36.66 " "36.66 30.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[24.66 24.66 30.66 30.66 24.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[18.66 18.66 24.66 18.66 24.66 24.66 18.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'addr');\ncolor('black');port_label('input',3," "'en');\ncolor('black');port_label('output',1,'q');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Delay" SID "12584" Ports [1, 1] Position [705, 441, 730, 469] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "25,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 " "17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33" " 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('blac" "k');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "12585" Position [210, 280, 300, 300] ZOrder -9 ShowName off GotoTag "ltsCorr_dAddr" TagVisibility "scoped" } Block { BlockType From Name "From1" SID "12586" Position [210, 340, 300, 360] ZOrder -9 ShowName off GotoTag "ltsCorr_cAddr" TagVisibility "scoped" } Block { BlockType From Name "From2" SID "12587" Position [210, 380, 300, 400] ZOrder -9 ShowName off GotoTag "ltsCorr_ld" TagVisibility "scoped" } Block { BlockType Reference Name "Gateway Out1" SID "12588" Ports [1, 1] Position [745, 615, 780, 625] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "12589" Ports [1, 1] Position [745, 630, 780, 640] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "12590" Ports [1, 1] Position [745, 645, 780, 655] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Ld" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "12591" Ports [1, 1] Position [745, 660, 780, 670] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "12592" Ports [1, 1] Position [745, 675, 780, 685] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "12593" Ports [1, 1] Position [745, 570, 780, 580] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X In" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "12594" Ports [1, 1] Position [745, 585, 780, 595] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "12595" Ports [1, 1] Position [745, 600, 780, 610] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X Vin" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType SubSystem Name "MAC" SID "12596" Ports [4, 2] Position [575, 279, 660, 376] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "MAC" Location [88, 301, 2330, 1301] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "a" SID "12597" Position [35, 143, 65, 157] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "coeff" SID "12598" Position [35, 108, 65, 122] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "ld" SID "12599" Position [35, 178, 65, 192] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "rst" SID "12600" Position [35, 233, 65, 247] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub" SID "12601" Ports [3, 1] Position [340, 113, 385, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition or Subtraction" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Signed (2's comp)" n_bits "long_cor_acc_n_bits" bin_pt "0" quantization "Truncate" overflow "Flag as error" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[2 0 0 4 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,344" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,3,1,white,blue,0,02f64c57,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('input',3,'su" "b');\ncolor('black');port_label('output',1,'\\bf{a \\pm b}','texmode','on');\nfprintf('','COMMENT: end icon text" "');\n" } Block { BlockType Reference Name "Gateway Out1" SID "12602" Ports [1, 1] Position [475, 450, 510, 460] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out2" SID "12603" Ports [1, 1] Position [475, 465, 510, 475] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out3" SID "12604" Ports [1, 1] Position [475, 480, 510, 490] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out6" SID "12605" Ports [1, 1] Position [475, 405, 510, 415] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out7" SID "12606" Ports [1, 1] Position [475, 420, 510, 430] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out8" SID "12607" Ports [1, 1] Position [475, 435, 510, 445] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "12608" Ports [2, 1] Position [345, 30, 385, 70] BlockMirror on NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,40,2,1,white,blue,0,140cc11c,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'" "q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "12609" Ports [2, 1] Position [465, 110, 495, 210] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,100,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 100 100 0 ],[0.77 0." "82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 100 100 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[54.44 " "54.44 58.44 54.44 58.44 58.44 58.44 54.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[50.44 50.44 54.44 54" ".44 50.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[46.44 46.44 50.44 50.44 46.44 ],[1 1 1 ])" ";\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[42.44 42.44 46.44 42.44 46.44 46.44 42.44 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\nco" "lor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc2" SID "12610" Ports [1, 1] Position [265, 143, 290, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc3" SID "12611" Ports [1, 1] Position [135, 178, 160, 192] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "yn" SID "12612" Position [545, 153, 575, 167] IconDisplay "Port number" } Block { BlockType Outport Name "accrm" SID "12613" Position [520, 288, 550, 302] Port "2" IconDisplay "Port number" } Line { SrcBlock "rst" SrcPort 1 Points [90, 0] Branch { Points [0, 215] DstBlock "Gateway Out1" DstPort 1 } Branch { Points [255, 0; 0, -180] DstBlock "Register1" DstPort 2 } } Line { SrcBlock "Gateway Out3" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out2" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out1" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out6" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out7" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out8" SrcPort 1 Points [50, 0] } Line { SrcBlock "a" SrcPort 1 Points [140, 0] Branch { Points [0, 275] DstBlock "Gateway Out7" DstPort 1 } Branch { DstBlock "bc2" DstPort 1 } } Line { SrcBlock "AddSub" SrcPort 1 Points [0, 0; 5, 0] Branch { Points [0, 305] DstBlock "Gateway Out8" DstPort 1 } Branch { Points [40, 0] Branch { Points [0, 160] DstBlock "accrm" DstPort 1 } Branch { Points [0, -95] DstBlock "Register1" DstPort 1 } Branch { DstBlock "Register2" DstPort 1 } } } Line { SrcBlock "Register2" SrcPort 1 Points [15, 0] Branch { Points [0, 50; 110, 0; 0, 385; -260, 0; 0, -110] DstBlock "Gateway Out3" DstPort 1 } Branch { DstBlock "yn" DstPort 1 } } Line { SrcBlock "Register1" SrcPort 1 Points [-15, 0] DstBlock "AddSub" DstPort 1 } Line { SrcBlock "ld" SrcPort 1 Points [45, 0] Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } Branch { DstBlock "bc3" DstPort 1 } } Line { SrcBlock "bc3" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "bc2" SrcPort 1 DstBlock "AddSub" DstPort 3 } Line { SrcBlock "coeff" SrcPort 1 Points [95, 0; 0, 20; 50, 0] Branch { Points [0, 275] DstBlock "Gateway Out6" DstPort 1 } Branch { DstBlock "AddSub" DstPort 2 } } } } Block { BlockType Reference Name "ROM" SID "12614" Ports [1, 1] Position [440, 328, 490, 372] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/ROM" SourceType "Xilinx Single Port Read-Only Memory Block" depth "length(coef2)" initVector "coef2" distributed_mem "Distributed memory" rst off init_reg "0" en off latency "1" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "longCorr_coef_nbits" bin_pt "longCorr_coef_bp" preci_type "Single" exp_width "8" frac_width "24" dbl_ovrd off optimize "Area" use_rpm off xl_use_area off xl_area "[1 1 0 1 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,308" block_type "sprom" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,44,1,1,white,blue,0,bbc23d60,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 44 44 0 ]);\npatch([11.65 20.32 26.32 32.32 38.32 26.32 17.65 11.65 ],[28.66" " 28.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([17.65 26.32 20.32 11.65 17.65 ],[22.66 22.66 28." "66 28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([11.65 20.32 26.32 17.65 11.65 ],[16.66 16.66 22.66 22.66 16.66 ]" ",[1 1 1 ]);\npatch([17.65 38.32 32.32 26.32 20.32 11.65 17.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'addr');\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end" " icon text');\n" } Block { BlockType Outport Name "x_dly" SID "12615" Position [790, 178, 820, 192] IconDisplay "Port number" } Block { BlockType Outport Name "x_dly_vout" SID "12616" Position [790, 223, 820, 237] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "y" SID "12617" Position [790, 293, 820, 307] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "y_vout" SID "12618" Position [785, 448, 815, 462] Port "4" IconDisplay "Port number" } Line { Name "ROM Addr" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 Points [150, 0] } Line { Name "Corr Out" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 Points [150, 0] } Line { Name "Corr Ld" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 Points [150, 0] } Line { Name "ROM Out" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 Points [150, 0] } Line { Name "ASR Out" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 Points [150, 0] } Line { Name "X In" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 Points [150, 0] } Line { Name "ASR Addr" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 Points [150, 0] } Line { Name "X Vin" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 Points [150, 0] } Line { SrcBlock "Delay" SrcPort 1 DstBlock "y_vout" DstPort 1 } Line { SrcBlock "vin" SrcPort 1 Points [25, 0] Branch { Points [0, -80] DstBlock "x_dly_vout" DstPort 1 } Branch { Points [0, 100] Branch { Points [230, 0] DstBlock "MAC" DstPort 4 } Branch { Points [0, 195] DstBlock "Gateway Out8" DstPort 1 } } Branch { DstBlock "ASR" DstPort 3 } } Line { SrcBlock "x" SrcPort 1 Points [100, 0] Branch { Points [0, 305] DstBlock "Gateway Out6" DstPort 1 } Branch { DstBlock "ASR" DstPort 1 } } Line { SrcBlock "From" SrcPort 1 Points [90, 0] Branch { Points [0, 300] DstBlock "Gateway Out7" DstPort 1 } Branch { DstBlock "ASR" DstPort 2 } } Line { SrcBlock "From1" SrcPort 1 Points [5, 0] Branch { Points [0, 330] DstBlock "Gateway Out5" DstPort 1 } Branch { DstBlock "ROM" DstPort 1 } } Line { SrcBlock "ASR" SrcPort 1 Points [35, 0] Branch { Points [0, 330] DstBlock "Gateway Out1" DstPort 1 } Branch { Points [0, -105] DstBlock "x_dly" DstPort 1 } Branch { DstBlock "MAC" DstPort 1 } } Line { SrcBlock "MAC" SrcPort 1 Points [0, -5; 15, 0] Branch { Points [0, 365] DstBlock "Gateway Out4" DstPort 1 } Branch { DstBlock "y" DstPort 1 } } Line { SrcBlock "ROM" SrcPort 1 Points [5, 0] Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } Branch { Points [0, -35] DstBlock "MAC" DstPort 2 } } Line { SrcBlock "From2" SrcPort 1 Points [145, 0] Branch { Points [0, 260] DstBlock "Gateway Out3" DstPort 1 } Branch { Points [90, 0] Branch { Points [0, 65] DstBlock "Delay" DstPort 1 } Branch { Points [0, -50] Branch { Points [0, -90; 160, 0] } Branch { DstBlock "MAC" DstPort 3 } } } } } } Block { BlockType SubSystem Name "C2" SID "12619" Ports [4, 4] Position [410, 207, 480, 293] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskPromptString "Coefficients (all)|Sub-correlator Ind|Coef/correlator" MaskStyleString "edit,edit,edit" MaskVariables "h=@1;c_ind=@2;N=@3;" MaskTunableValueString "on,on,on" MaskCallbackString "||" MaskEnableString "on,on,on" MaskVisibilityString "on,on,on" MaskToolTipString "on,on,on" MaskInitialization "coef2 = h((c_ind*N+1) : (c_ind + 1)*N);" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "h|1|N" System { Name "C2" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "122" Block { BlockType Inport Name "x" SID "12620" Position [265, 263, 295, 277] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "vin" SID "12621" Position [270, 303, 300, 317] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "12622" Position [270, 458, 300, 472] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "12623" Position [270, 503, 300, 517] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "ASR" SID "12624" Ports [3, 1] Position [445, 260, 490, 320] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Addressable Shift Register" SourceType "Xilinx Addressable Shift Register Block" infoedit "Delay of configurable length. Any element in the delay line can be addressed and driven onto the" " output port.

Hardware notes: This block is implemented using SRL16s. If Virtex-4 or Spartan-3 device is " "used, multiple SRLC16s are cascaded together." infer_latency off depth "length(coef2)" initVector "[0]" en on dbl_ovrd off use_behavioral_HDL off Optimization "Resource" xl_use_area off xl_area "[1 0 0 2 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,401" block_type "addrsr" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,60,3,1,white,blue,0,f8ea6153,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 60 60 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 60 60 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[36.66 3" "6.66 42.66 36.66 42.66 42.66 42.66 36.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[30.66 30.66 36.66 " "36.66 30.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[24.66 24.66 30.66 30.66 24.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[18.66 18.66 24.66 18.66 24.66 24.66 18.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'addr');\ncolor('black');port_label('input',3," "'en');\ncolor('black');port_label('output',1,'q');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Delay" SID "12625" Ports [1, 1] Position [705, 441, 730, 469] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "25,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 " "17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33" " 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('blac" "k');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "12626" Position [210, 280, 300, 300] ZOrder -9 ShowName off GotoTag "ltsCorr_dAddr" TagVisibility "scoped" } Block { BlockType From Name "From1" SID "12627" Position [210, 340, 300, 360] ZOrder -9 ShowName off GotoTag "ltsCorr_cAddr" TagVisibility "scoped" } Block { BlockType From Name "From2" SID "12628" Position [210, 380, 300, 400] ZOrder -9 ShowName off GotoTag "ltsCorr_ld" TagVisibility "scoped" } Block { BlockType Reference Name "Gateway Out1" SID "12629" Ports [1, 1] Position [745, 615, 780, 625] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "12630" Ports [1, 1] Position [745, 630, 780, 640] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "12631" Ports [1, 1] Position [745, 645, 780, 655] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Ld" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "12632" Ports [1, 1] Position [745, 660, 780, 670] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "12633" Ports [1, 1] Position [745, 675, 780, 685] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "12634" Ports [1, 1] Position [745, 570, 780, 580] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X In" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "12635" Ports [1, 1] Position [745, 585, 780, 595] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "12636" Ports [1, 1] Position [745, 600, 780, 610] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X Vin" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType SubSystem Name "MAC" SID "12637" Ports [4, 2] Position [575, 279, 660, 376] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "MAC" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "a" SID "12638" Position [35, 143, 65, 157] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "coeff" SID "12639" Position [35, 108, 65, 122] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "ld" SID "12640" Position [35, 178, 65, 192] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "rst" SID "12641" Position [35, 233, 65, 247] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub" SID "12642" Ports [3, 1] Position [340, 113, 385, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition or Subtraction" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Signed (2's comp)" n_bits "long_cor_acc_n_bits" bin_pt "0" quantization "Truncate" overflow "Flag as error" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[2 0 0 4 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,344" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,3,1,white,blue,0,02f64c57,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('input',3,'su" "b');\ncolor('black');port_label('output',1,'\\bf{a \\pm b}','texmode','on');\nfprintf('','COMMENT: end icon text" "');\n" } Block { BlockType Reference Name "Gateway Out1" SID "12643" Ports [1, 1] Position [475, 450, 510, 460] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out2" SID "12644" Ports [1, 1] Position [475, 465, 510, 475] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out3" SID "12645" Ports [1, 1] Position [475, 480, 510, 490] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out6" SID "12646" Ports [1, 1] Position [475, 405, 510, 415] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out7" SID "12647" Ports [1, 1] Position [475, 420, 510, 430] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out8" SID "12648" Ports [1, 1] Position [475, 435, 510, 445] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "12649" Ports [2, 1] Position [345, 30, 385, 70] BlockMirror on NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,40,2,1,white,blue,0,140cc11c,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'" "q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "12650" Ports [2, 1] Position [465, 110, 495, 210] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,100,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 100 100 0 ],[0.77 0." "82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 100 100 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[54.44 " "54.44 58.44 54.44 58.44 58.44 58.44 54.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[50.44 50.44 54.44 54" ".44 50.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[46.44 46.44 50.44 50.44 46.44 ],[1 1 1 ])" ";\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[42.44 42.44 46.44 42.44 46.44 46.44 42.44 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\nco" "lor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc2" SID "12651" Ports [1, 1] Position [265, 143, 290, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc3" SID "12652" Ports [1, 1] Position [135, 178, 160, 192] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "yn" SID "12653" Position [545, 153, 575, 167] IconDisplay "Port number" } Block { BlockType Outport Name "accrm" SID "12654" Position [520, 288, 550, 302] Port "2" IconDisplay "Port number" } Line { SrcBlock "coeff" SrcPort 1 Points [95, 0; 0, 20; 50, 0] Branch { DstBlock "AddSub" DstPort 2 } Branch { Points [0, 275] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "bc2" SrcPort 1 DstBlock "AddSub" DstPort 3 } Line { SrcBlock "bc3" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "ld" SrcPort 1 Points [45, 0] Branch { DstBlock "bc3" DstPort 1 } Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "Register1" SrcPort 1 Points [-15, 0] DstBlock "AddSub" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 Points [15, 0] Branch { DstBlock "yn" DstPort 1 } Branch { Points [0, 50; 110, 0; 0, 385; -260, 0; 0, -110] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "AddSub" SrcPort 1 Points [0, 0; 5, 0] Branch { Points [40, 0] Branch { DstBlock "Register2" DstPort 1 } Branch { Points [0, -95] DstBlock "Register1" DstPort 1 } Branch { Points [0, 160] DstBlock "accrm" DstPort 1 } } Branch { Points [0, 305] DstBlock "Gateway Out8" DstPort 1 } } Line { SrcBlock "a" SrcPort 1 Points [140, 0] Branch { DstBlock "bc2" DstPort 1 } Branch { Points [0, 275] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "Gateway Out8" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out7" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out6" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out1" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out2" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out3" SrcPort 1 Points [50, 0] } Line { SrcBlock "rst" SrcPort 1 Points [90, 0] Branch { Points [255, 0; 0, -180] DstBlock "Register1" DstPort 2 } Branch { Points [0, 215] DstBlock "Gateway Out1" DstPort 1 } } } } Block { BlockType Reference Name "ROM" SID "12655" Ports [1, 1] Position [440, 328, 490, 372] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/ROM" SourceType "Xilinx Single Port Read-Only Memory Block" depth "length(coef2)" initVector "coef2" distributed_mem "Distributed memory" rst off init_reg "0" en off latency "1" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "longCorr_coef_nbits" bin_pt "longCorr_coef_bp" preci_type "Single" exp_width "8" frac_width "24" dbl_ovrd off optimize "Area" use_rpm off xl_use_area off xl_area "[1 1 0 1 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,308" block_type "sprom" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,44,1,1,white,blue,0,bbc23d60,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 44 44 0 ]);\npatch([11.65 20.32 26.32 32.32 38.32 26.32 17.65 11.65 ],[28.66" " 28.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([17.65 26.32 20.32 11.65 17.65 ],[22.66 22.66 28." "66 28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([11.65 20.32 26.32 17.65 11.65 ],[16.66 16.66 22.66 22.66 16.66 ]" ",[1 1 1 ]);\npatch([17.65 38.32 32.32 26.32 20.32 11.65 17.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'addr');\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end" " icon text');\n" } Block { BlockType Outport Name "x_dly" SID "12656" Position [790, 178, 820, 192] IconDisplay "Port number" } Block { BlockType Outport Name "x_dly_vout" SID "12657" Position [790, 223, 820, 237] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "y" SID "12658" Position [790, 293, 820, 307] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "y_vout" SID "12659" Position [785, 448, 815, 462] Port "4" IconDisplay "Port number" } Line { SrcBlock "From2" SrcPort 1 Points [145, 0] Branch { Points [90, 0] Branch { Points [0, -50] Branch { DstBlock "MAC" DstPort 3 } Branch { Points [0, -90; 160, 0] } } Branch { Points [0, 65] DstBlock "Delay" DstPort 1 } } Branch { Points [0, 260] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "ROM" SrcPort 1 Points [5, 0] Branch { Points [0, -35] DstBlock "MAC" DstPort 2 } Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "MAC" SrcPort 1 Points [0, -5; 15, 0] Branch { DstBlock "y" DstPort 1 } Branch { Points [0, 365] DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "ASR" SrcPort 1 Points [35, 0] Branch { DstBlock "MAC" DstPort 1 } Branch { Points [0, -105] DstBlock "x_dly" DstPort 1 } Branch { Points [0, 330] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "From1" SrcPort 1 Points [5, 0] Branch { DstBlock "ROM" DstPort 1 } Branch { Points [0, 330] DstBlock "Gateway Out5" DstPort 1 } } Line { SrcBlock "From" SrcPort 1 Points [90, 0] Branch { DstBlock "ASR" DstPort 2 } Branch { Points [0, 300] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "x" SrcPort 1 Points [100, 0] Branch { DstBlock "ASR" DstPort 1 } Branch { Points [0, 305] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "vin" SrcPort 1 Points [25, 0] Branch { DstBlock "ASR" DstPort 3 } Branch { Points [0, 100] Branch { Points [0, 195] DstBlock "Gateway Out8" DstPort 1 } Branch { Points [230, 0] DstBlock "MAC" DstPort 4 } } Branch { Points [0, -80] DstBlock "x_dly_vout" DstPort 1 } } Line { SrcBlock "Delay" SrcPort 1 DstBlock "y_vout" DstPort 1 } Line { Name "X Vin" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 Points [150, 0] } Line { Name "ASR Addr" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 Points [150, 0] } Line { Name "X In" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 Points [150, 0] } Line { Name "ASR Out" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 Points [150, 0] } Line { Name "ROM Out" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 Points [150, 0] } Line { Name "Corr Ld" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 Points [150, 0] } Line { Name "Corr Out" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 Points [150, 0] } Line { Name "ROM Addr" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 Points [150, 0] } } } Block { BlockType SubSystem Name "C3" SID "12660" Ports [4, 4] Position [520, 207, 590, 293] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskPromptString "Coefficients (all)|Sub-correlator Ind|Coef/correlator" MaskStyleString "edit,edit,edit" MaskVariables "h=@1;c_ind=@2;N=@3;" MaskTunableValueString "on,on,on" MaskCallbackString "||" MaskEnableString "on,on,on" MaskVisibilityString "on,on,on" MaskToolTipString "on,on,on" MaskInitialization "coef2 = h((c_ind*N+1) : (c_ind + 1)*N);" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "h|2|N" System { Name "C3" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "122" Block { BlockType Inport Name "x" SID "12661" Position [265, 263, 295, 277] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "vin" SID "12662" Position [270, 303, 300, 317] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "12663" Position [270, 458, 300, 472] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "12664" Position [270, 503, 300, 517] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "ASR" SID "12665" Ports [3, 1] Position [445, 260, 490, 320] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Addressable Shift Register" SourceType "Xilinx Addressable Shift Register Block" infoedit "Delay of configurable length. Any element in the delay line can be addressed and driven onto the" " output port.

Hardware notes: This block is implemented using SRL16s. If Virtex-4 or Spartan-3 device is " "used, multiple SRLC16s are cascaded together." infer_latency off depth "length(coef2)" initVector "[0]" en on dbl_ovrd off use_behavioral_HDL off Optimization "Resource" xl_use_area off xl_area "[1 0 0 2 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,401" block_type "addrsr" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,60,3,1,white,blue,0,f8ea6153,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 60 60 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 60 60 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[36.66 3" "6.66 42.66 36.66 42.66 42.66 42.66 36.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[30.66 30.66 36.66 " "36.66 30.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[24.66 24.66 30.66 30.66 24.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[18.66 18.66 24.66 18.66 24.66 24.66 18.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'addr');\ncolor('black');port_label('input',3," "'en');\ncolor('black');port_label('output',1,'q');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Delay" SID "12666" Ports [1, 1] Position [705, 441, 730, 469] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "25,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 " "17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33" " 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('blac" "k');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "12667" Position [210, 280, 300, 300] ZOrder -9 ShowName off GotoTag "ltsCorr_dAddr" TagVisibility "scoped" } Block { BlockType From Name "From1" SID "12668" Position [210, 340, 300, 360] ZOrder -9 ShowName off GotoTag "ltsCorr_cAddr" TagVisibility "scoped" } Block { BlockType From Name "From2" SID "12669" Position [210, 380, 300, 400] ZOrder -9 ShowName off GotoTag "ltsCorr_ld" TagVisibility "scoped" } Block { BlockType Reference Name "Gateway Out1" SID "12670" Ports [1, 1] Position [745, 615, 780, 625] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "12671" Ports [1, 1] Position [745, 630, 780, 640] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "12672" Ports [1, 1] Position [745, 645, 780, 655] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Ld" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "12673" Ports [1, 1] Position [745, 660, 780, 670] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "12674" Ports [1, 1] Position [745, 675, 780, 685] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "12675" Ports [1, 1] Position [745, 570, 780, 580] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X In" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "12676" Ports [1, 1] Position [745, 585, 780, 595] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "12677" Ports [1, 1] Position [745, 600, 780, 610] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X Vin" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType SubSystem Name "MAC" SID "12678" Ports [4, 2] Position [575, 279, 660, 376] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "MAC" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "a" SID "12679" Position [35, 143, 65, 157] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "coeff" SID "12680" Position [35, 108, 65, 122] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "ld" SID "12681" Position [35, 178, 65, 192] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "rst" SID "12682" Position [35, 233, 65, 247] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub" SID "12683" Ports [3, 1] Position [340, 113, 385, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition or Subtraction" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Signed (2's comp)" n_bits "long_cor_acc_n_bits" bin_pt "0" quantization "Truncate" overflow "Flag as error" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[2 0 0 4 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,344" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,3,1,white,blue,0,02f64c57,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('input',3,'su" "b');\ncolor('black');port_label('output',1,'\\bf{a \\pm b}','texmode','on');\nfprintf('','COMMENT: end icon text" "');\n" } Block { BlockType Reference Name "Gateway Out1" SID "12684" Ports [1, 1] Position [475, 450, 510, 460] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out2" SID "12685" Ports [1, 1] Position [475, 465, 510, 475] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out3" SID "12686" Ports [1, 1] Position [475, 480, 510, 490] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out6" SID "12687" Ports [1, 1] Position [475, 405, 510, 415] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out7" SID "12688" Ports [1, 1] Position [475, 420, 510, 430] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out8" SID "12689" Ports [1, 1] Position [475, 435, 510, 445] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "12690" Ports [2, 1] Position [345, 30, 385, 70] BlockMirror on NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,40,2,1,white,blue,0,140cc11c,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'" "q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "12691" Ports [2, 1] Position [465, 110, 495, 210] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,100,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 100 100 0 ],[0.77 0." "82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 100 100 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[54.44 " "54.44 58.44 54.44 58.44 58.44 58.44 54.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[50.44 50.44 54.44 54" ".44 50.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[46.44 46.44 50.44 50.44 46.44 ],[1 1 1 ])" ";\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[42.44 42.44 46.44 42.44 46.44 46.44 42.44 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\nco" "lor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc2" SID "12692" Ports [1, 1] Position [265, 143, 290, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc3" SID "12693" Ports [1, 1] Position [135, 178, 160, 192] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "yn" SID "12694" Position [545, 153, 575, 167] IconDisplay "Port number" } Block { BlockType Outport Name "accrm" SID "12695" Position [520, 288, 550, 302] Port "2" IconDisplay "Port number" } Line { SrcBlock "rst" SrcPort 1 Points [90, 0] Branch { Points [0, 215] DstBlock "Gateway Out1" DstPort 1 } Branch { Points [255, 0; 0, -180] DstBlock "Register1" DstPort 2 } } Line { SrcBlock "Gateway Out3" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out2" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out1" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out6" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out7" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out8" SrcPort 1 Points [50, 0] } Line { SrcBlock "a" SrcPort 1 Points [140, 0] Branch { Points [0, 275] DstBlock "Gateway Out7" DstPort 1 } Branch { DstBlock "bc2" DstPort 1 } } Line { SrcBlock "AddSub" SrcPort 1 Points [0, 0; 5, 0] Branch { Points [0, 305] DstBlock "Gateway Out8" DstPort 1 } Branch { Points [40, 0] Branch { Points [0, 160] DstBlock "accrm" DstPort 1 } Branch { Points [0, -95] DstBlock "Register1" DstPort 1 } Branch { DstBlock "Register2" DstPort 1 } } } Line { SrcBlock "Register2" SrcPort 1 Points [15, 0] Branch { Points [0, 50; 110, 0; 0, 385; -260, 0; 0, -110] DstBlock "Gateway Out3" DstPort 1 } Branch { DstBlock "yn" DstPort 1 } } Line { SrcBlock "Register1" SrcPort 1 Points [-15, 0] DstBlock "AddSub" DstPort 1 } Line { SrcBlock "ld" SrcPort 1 Points [45, 0] Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } Branch { DstBlock "bc3" DstPort 1 } } Line { SrcBlock "bc3" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "bc2" SrcPort 1 DstBlock "AddSub" DstPort 3 } Line { SrcBlock "coeff" SrcPort 1 Points [95, 0; 0, 20; 50, 0] Branch { Points [0, 275] DstBlock "Gateway Out6" DstPort 1 } Branch { DstBlock "AddSub" DstPort 2 } } } } Block { BlockType Reference Name "ROM" SID "12696" Ports [1, 1] Position [440, 328, 490, 372] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/ROM" SourceType "Xilinx Single Port Read-Only Memory Block" depth "length(coef2)" initVector "coef2" distributed_mem "Distributed memory" rst off init_reg "0" en off latency "1" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "longCorr_coef_nbits" bin_pt "longCorr_coef_bp" preci_type "Single" exp_width "8" frac_width "24" dbl_ovrd off optimize "Area" use_rpm off xl_use_area off xl_area "[1 1 0 1 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,308" block_type "sprom" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,44,1,1,white,blue,0,bbc23d60,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 44 44 0 ]);\npatch([11.65 20.32 26.32 32.32 38.32 26.32 17.65 11.65 ],[28.66" " 28.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([17.65 26.32 20.32 11.65 17.65 ],[22.66 22.66 28." "66 28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([11.65 20.32 26.32 17.65 11.65 ],[16.66 16.66 22.66 22.66 16.66 ]" ",[1 1 1 ]);\npatch([17.65 38.32 32.32 26.32 20.32 11.65 17.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'addr');\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end" " icon text');\n" } Block { BlockType Outport Name "x_dly" SID "12697" Position [790, 178, 820, 192] IconDisplay "Port number" } Block { BlockType Outport Name "x_dly_vout" SID "12698" Position [790, 223, 820, 237] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "y" SID "12699" Position [790, 293, 820, 307] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "y_vout" SID "12700" Position [785, 448, 815, 462] Port "4" IconDisplay "Port number" } Line { Name "ROM Addr" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 Points [150, 0] } Line { Name "Corr Out" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 Points [150, 0] } Line { Name "Corr Ld" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 Points [150, 0] } Line { Name "ROM Out" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 Points [150, 0] } Line { Name "ASR Out" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 Points [150, 0] } Line { Name "X In" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 Points [150, 0] } Line { Name "ASR Addr" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 Points [150, 0] } Line { Name "X Vin" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 Points [150, 0] } Line { SrcBlock "Delay" SrcPort 1 DstBlock "y_vout" DstPort 1 } Line { SrcBlock "vin" SrcPort 1 Points [25, 0] Branch { Points [0, -80] DstBlock "x_dly_vout" DstPort 1 } Branch { Points [0, 100] Branch { Points [230, 0] DstBlock "MAC" DstPort 4 } Branch { Points [0, 195] DstBlock "Gateway Out8" DstPort 1 } } Branch { DstBlock "ASR" DstPort 3 } } Line { SrcBlock "x" SrcPort 1 Points [100, 0] Branch { Points [0, 305] DstBlock "Gateway Out6" DstPort 1 } Branch { DstBlock "ASR" DstPort 1 } } Line { SrcBlock "From" SrcPort 1 Points [90, 0] Branch { Points [0, 300] DstBlock "Gateway Out7" DstPort 1 } Branch { DstBlock "ASR" DstPort 2 } } Line { SrcBlock "From1" SrcPort 1 Points [5, 0] Branch { Points [0, 330] DstBlock "Gateway Out5" DstPort 1 } Branch { DstBlock "ROM" DstPort 1 } } Line { SrcBlock "ASR" SrcPort 1 Points [35, 0] Branch { Points [0, 330] DstBlock "Gateway Out1" DstPort 1 } Branch { Points [0, -105] DstBlock "x_dly" DstPort 1 } Branch { DstBlock "MAC" DstPort 1 } } Line { SrcBlock "MAC" SrcPort 1 Points [0, -5; 15, 0] Branch { Points [0, 365] DstBlock "Gateway Out4" DstPort 1 } Branch { DstBlock "y" DstPort 1 } } Line { SrcBlock "ROM" SrcPort 1 Points [5, 0] Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } Branch { Points [0, -35] DstBlock "MAC" DstPort 2 } } Line { SrcBlock "From2" SrcPort 1 Points [145, 0] Branch { Points [0, 260] DstBlock "Gateway Out3" DstPort 1 } Branch { Points [90, 0] Branch { Points [0, 65] DstBlock "Delay" DstPort 1 } Branch { Points [0, -50] Branch { Points [0, -90; 160, 0] } Branch { DstBlock "MAC" DstPort 3 } } } } } } Block { BlockType SubSystem Name "C4" SID "12701" Ports [4, 4] Position [630, 207, 700, 293] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskPromptString "Coefficients (all)|Sub-correlator Ind|Coef/correlator" MaskStyleString "edit,edit,edit" MaskVariables "h=@1;c_ind=@2;N=@3;" MaskTunableValueString "on,on,on" MaskCallbackString "||" MaskEnableString "on,on,on" MaskVisibilityString "on,on,on" MaskToolTipString "on,on,on" MaskInitialization "coef2 = h((c_ind*N+1) : (c_ind + 1)*N);" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "h|3|N" System { Name "C4" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "122" Block { BlockType Inport Name "x" SID "12702" Position [265, 263, 295, 277] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "vin" SID "12703" Position [270, 303, 300, 317] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "12704" Position [270, 458, 300, 472] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "12705" Position [270, 503, 300, 517] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "ASR" SID "12706" Ports [3, 1] Position [445, 260, 490, 320] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Addressable Shift Register" SourceType "Xilinx Addressable Shift Register Block" infoedit "Delay of configurable length. Any element in the delay line can be addressed and driven onto the" " output port.

Hardware notes: This block is implemented using SRL16s. If Virtex-4 or Spartan-3 device is " "used, multiple SRLC16s are cascaded together." infer_latency off depth "length(coef2)" initVector "[0]" en on dbl_ovrd off use_behavioral_HDL off Optimization "Resource" xl_use_area off xl_area "[1 0 0 2 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,401" block_type "addrsr" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,60,3,1,white,blue,0,f8ea6153,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 60 60 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 60 60 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[36.66 3" "6.66 42.66 36.66 42.66 42.66 42.66 36.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[30.66 30.66 36.66 " "36.66 30.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[24.66 24.66 30.66 30.66 24.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[18.66 18.66 24.66 18.66 24.66 24.66 18.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'addr');\ncolor('black');port_label('input',3," "'en');\ncolor('black');port_label('output',1,'q');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Delay" SID "12707" Ports [1, 1] Position [705, 441, 730, 469] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "25,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 " "17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33" " 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('blac" "k');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "12708" Position [210, 280, 300, 300] ZOrder -9 ShowName off GotoTag "ltsCorr_dAddr" TagVisibility "scoped" } Block { BlockType From Name "From1" SID "12709" Position [210, 340, 300, 360] ZOrder -9 ShowName off GotoTag "ltsCorr_cAddr" TagVisibility "scoped" } Block { BlockType From Name "From2" SID "12710" Position [210, 380, 300, 400] ZOrder -9 ShowName off GotoTag "ltsCorr_ld" TagVisibility "scoped" } Block { BlockType Reference Name "Gateway Out1" SID "12711" Ports [1, 1] Position [745, 615, 780, 625] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "12712" Ports [1, 1] Position [745, 630, 780, 640] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "12713" Ports [1, 1] Position [745, 645, 780, 655] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Ld" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "12714" Ports [1, 1] Position [745, 660, 780, 670] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "12715" Ports [1, 1] Position [745, 675, 780, 685] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "12716" Ports [1, 1] Position [745, 570, 780, 580] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X In" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "12717" Ports [1, 1] Position [745, 585, 780, 595] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "12718" Ports [1, 1] Position [745, 600, 780, 610] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X Vin" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType SubSystem Name "MAC" SID "12719" Ports [4, 2] Position [575, 279, 660, 376] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "MAC" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "a" SID "12720" Position [35, 143, 65, 157] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "coeff" SID "12721" Position [35, 108, 65, 122] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "ld" SID "12722" Position [35, 178, 65, 192] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "rst" SID "12723" Position [35, 233, 65, 247] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub" SID "12724" Ports [3, 1] Position [340, 113, 385, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition or Subtraction" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Signed (2's comp)" n_bits "long_cor_acc_n_bits" bin_pt "0" quantization "Truncate" overflow "Flag as error" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[2 0 0 4 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,344" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,3,1,white,blue,0,02f64c57,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('input',3,'su" "b');\ncolor('black');port_label('output',1,'\\bf{a \\pm b}','texmode','on');\nfprintf('','COMMENT: end icon text" "');\n" } Block { BlockType Reference Name "Gateway Out1" SID "12725" Ports [1, 1] Position [475, 450, 510, 460] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out2" SID "12726" Ports [1, 1] Position [475, 465, 510, 475] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out3" SID "12727" Ports [1, 1] Position [475, 480, 510, 490] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out6" SID "12728" Ports [1, 1] Position [475, 405, 510, 415] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out7" SID "12729" Ports [1, 1] Position [475, 420, 510, 430] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out8" SID "12730" Ports [1, 1] Position [475, 435, 510, 445] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "12731" Ports [2, 1] Position [345, 30, 385, 70] BlockMirror on NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,40,2,1,white,blue,0,140cc11c,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'" "q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "12732" Ports [2, 1] Position [465, 110, 495, 210] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,100,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 100 100 0 ],[0.77 0." "82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 100 100 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[54.44 " "54.44 58.44 54.44 58.44 58.44 58.44 54.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[50.44 50.44 54.44 54" ".44 50.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[46.44 46.44 50.44 50.44 46.44 ],[1 1 1 ])" ";\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[42.44 42.44 46.44 42.44 46.44 46.44 42.44 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\nco" "lor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc2" SID "12733" Ports [1, 1] Position [265, 143, 290, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc3" SID "12734" Ports [1, 1] Position [135, 178, 160, 192] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "yn" SID "12735" Position [545, 153, 575, 167] IconDisplay "Port number" } Block { BlockType Outport Name "accrm" SID "12736" Position [520, 288, 550, 302] Port "2" IconDisplay "Port number" } Line { SrcBlock "coeff" SrcPort 1 Points [95, 0; 0, 20; 50, 0] Branch { DstBlock "AddSub" DstPort 2 } Branch { Points [0, 275] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "bc2" SrcPort 1 DstBlock "AddSub" DstPort 3 } Line { SrcBlock "bc3" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "ld" SrcPort 1 Points [45, 0] Branch { DstBlock "bc3" DstPort 1 } Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "Register1" SrcPort 1 Points [-15, 0] DstBlock "AddSub" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 Points [15, 0] Branch { DstBlock "yn" DstPort 1 } Branch { Points [0, 50; 110, 0; 0, 385; -260, 0; 0, -110] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "AddSub" SrcPort 1 Points [0, 0; 5, 0] Branch { Points [40, 0] Branch { DstBlock "Register2" DstPort 1 } Branch { Points [0, -95] DstBlock "Register1" DstPort 1 } Branch { Points [0, 160] DstBlock "accrm" DstPort 1 } } Branch { Points [0, 305] DstBlock "Gateway Out8" DstPort 1 } } Line { SrcBlock "a" SrcPort 1 Points [140, 0] Branch { DstBlock "bc2" DstPort 1 } Branch { Points [0, 275] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "Gateway Out8" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out7" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out6" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out1" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out2" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out3" SrcPort 1 Points [50, 0] } Line { SrcBlock "rst" SrcPort 1 Points [90, 0] Branch { Points [255, 0; 0, -180] DstBlock "Register1" DstPort 2 } Branch { Points [0, 215] DstBlock "Gateway Out1" DstPort 1 } } } } Block { BlockType Reference Name "ROM" SID "12737" Ports [1, 1] Position [440, 328, 490, 372] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/ROM" SourceType "Xilinx Single Port Read-Only Memory Block" depth "length(coef2)" initVector "coef2" distributed_mem "Distributed memory" rst off init_reg "0" en off latency "1" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "longCorr_coef_nbits" bin_pt "longCorr_coef_bp" preci_type "Single" exp_width "8" frac_width "24" dbl_ovrd off optimize "Area" use_rpm off xl_use_area off xl_area "[1 1 0 1 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,308" block_type "sprom" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,44,1,1,white,blue,0,bbc23d60,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 44 44 0 ]);\npatch([11.65 20.32 26.32 32.32 38.32 26.32 17.65 11.65 ],[28.66" " 28.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([17.65 26.32 20.32 11.65 17.65 ],[22.66 22.66 28." "66 28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([11.65 20.32 26.32 17.65 11.65 ],[16.66 16.66 22.66 22.66 16.66 ]" ",[1 1 1 ]);\npatch([17.65 38.32 32.32 26.32 20.32 11.65 17.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'addr');\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end" " icon text');\n" } Block { BlockType Outport Name "x_dly" SID "12738" Position [790, 178, 820, 192] IconDisplay "Port number" } Block { BlockType Outport Name "x_dly_vout" SID "12739" Position [790, 223, 820, 237] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "y" SID "12740" Position [790, 293, 820, 307] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "y_vout" SID "12741" Position [785, 448, 815, 462] Port "4" IconDisplay "Port number" } Line { SrcBlock "From2" SrcPort 1 Points [145, 0] Branch { Points [90, 0] Branch { Points [0, -50] Branch { DstBlock "MAC" DstPort 3 } Branch { Points [0, -90; 160, 0] } } Branch { Points [0, 65] DstBlock "Delay" DstPort 1 } } Branch { Points [0, 260] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "ROM" SrcPort 1 Points [5, 0] Branch { Points [0, -35] DstBlock "MAC" DstPort 2 } Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "MAC" SrcPort 1 Points [0, -5; 15, 0] Branch { DstBlock "y" DstPort 1 } Branch { Points [0, 365] DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "ASR" SrcPort 1 Points [35, 0] Branch { DstBlock "MAC" DstPort 1 } Branch { Points [0, -105] DstBlock "x_dly" DstPort 1 } Branch { Points [0, 330] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "From1" SrcPort 1 Points [5, 0] Branch { DstBlock "ROM" DstPort 1 } Branch { Points [0, 330] DstBlock "Gateway Out5" DstPort 1 } } Line { SrcBlock "From" SrcPort 1 Points [90, 0] Branch { DstBlock "ASR" DstPort 2 } Branch { Points [0, 300] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "x" SrcPort 1 Points [100, 0] Branch { DstBlock "ASR" DstPort 1 } Branch { Points [0, 305] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "vin" SrcPort 1 Points [25, 0] Branch { DstBlock "ASR" DstPort 3 } Branch { Points [0, 100] Branch { Points [0, 195] DstBlock "Gateway Out8" DstPort 1 } Branch { Points [230, 0] DstBlock "MAC" DstPort 4 } } Branch { Points [0, -80] DstBlock "x_dly_vout" DstPort 1 } } Line { SrcBlock "Delay" SrcPort 1 DstBlock "y_vout" DstPort 1 } Line { Name "X Vin" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 Points [150, 0] } Line { Name "ASR Addr" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 Points [150, 0] } Line { Name "X In" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 Points [150, 0] } Line { Name "ASR Out" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 Points [150, 0] } Line { Name "ROM Out" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 Points [150, 0] } Line { Name "Corr Ld" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 Points [150, 0] } Line { Name "Corr Out" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 Points [150, 0] } Line { Name "ROM Addr" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 Points [150, 0] } } } Block { BlockType SubSystem Name "C5" SID "12742" Ports [4, 4] Position [740, 207, 810, 293] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskPromptString "Coefficients (all)|Sub-correlator Ind|Coef/correlator" MaskStyleString "edit,edit,edit" MaskVariables "h=@1;c_ind=@2;N=@3;" MaskTunableValueString "on,on,on" MaskCallbackString "||" MaskEnableString "on,on,on" MaskVisibilityString "on,on,on" MaskToolTipString "on,on,on" MaskInitialization "coef2 = h((c_ind*N+1) : (c_ind + 1)*N);" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "h|4|N" System { Name "C5" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "122" Block { BlockType Inport Name "x" SID "12743" Position [265, 263, 295, 277] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "vin" SID "12744" Position [270, 303, 300, 317] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "12745" Position [270, 458, 300, 472] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "12746" Position [270, 503, 300, 517] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "ASR" SID "12747" Ports [3, 1] Position [445, 260, 490, 320] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Addressable Shift Register" SourceType "Xilinx Addressable Shift Register Block" infoedit "Delay of configurable length. Any element in the delay line can be addressed and driven onto the" " output port.

Hardware notes: This block is implemented using SRL16s. If Virtex-4 or Spartan-3 device is " "used, multiple SRLC16s are cascaded together." infer_latency off depth "length(coef2)" initVector "[0]" en on dbl_ovrd off use_behavioral_HDL off Optimization "Resource" xl_use_area off xl_area "[1 0 0 2 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,401" block_type "addrsr" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,60,3,1,white,blue,0,f8ea6153,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 60 60 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 60 60 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[36.66 3" "6.66 42.66 36.66 42.66 42.66 42.66 36.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[30.66 30.66 36.66 " "36.66 30.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[24.66 24.66 30.66 30.66 24.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[18.66 18.66 24.66 18.66 24.66 24.66 18.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'addr');\ncolor('black');port_label('input',3," "'en');\ncolor('black');port_label('output',1,'q');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Delay" SID "12748" Ports [1, 1] Position [705, 441, 730, 469] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "25,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 " "17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33" " 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('blac" "k');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "12749" Position [210, 280, 300, 300] ZOrder -9 ShowName off GotoTag "ltsCorr_dAddr" TagVisibility "scoped" } Block { BlockType From Name "From1" SID "12750" Position [210, 340, 300, 360] ZOrder -9 ShowName off GotoTag "ltsCorr_cAddr" TagVisibility "scoped" } Block { BlockType From Name "From2" SID "12751" Position [210, 380, 300, 400] ZOrder -9 ShowName off GotoTag "ltsCorr_ld" TagVisibility "scoped" } Block { BlockType Reference Name "Gateway Out1" SID "12752" Ports [1, 1] Position [745, 615, 780, 625] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "12753" Ports [1, 1] Position [745, 630, 780, 640] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "12754" Ports [1, 1] Position [745, 645, 780, 655] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Ld" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "12755" Ports [1, 1] Position [745, 660, 780, 670] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "12756" Ports [1, 1] Position [745, 675, 780, 685] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "12757" Ports [1, 1] Position [745, 570, 780, 580] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X In" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "12758" Ports [1, 1] Position [745, 585, 780, 595] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "12759" Ports [1, 1] Position [745, 600, 780, 610] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X Vin" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType SubSystem Name "MAC" SID "12760" Ports [4, 2] Position [575, 279, 660, 376] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "MAC" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "a" SID "12761" Position [35, 143, 65, 157] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "coeff" SID "12762" Position [35, 108, 65, 122] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "ld" SID "12763" Position [35, 178, 65, 192] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "rst" SID "12764" Position [35, 233, 65, 247] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub" SID "12765" Ports [3, 1] Position [340, 113, 385, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition or Subtraction" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Signed (2's comp)" n_bits "long_cor_acc_n_bits" bin_pt "0" quantization "Truncate" overflow "Flag as error" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[2 0 0 4 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,344" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,3,1,white,blue,0,02f64c57,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('input',3,'su" "b');\ncolor('black');port_label('output',1,'\\bf{a \\pm b}','texmode','on');\nfprintf('','COMMENT: end icon text" "');\n" } Block { BlockType Reference Name "Gateway Out1" SID "12766" Ports [1, 1] Position [475, 450, 510, 460] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out2" SID "12767" Ports [1, 1] Position [475, 465, 510, 475] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out3" SID "12768" Ports [1, 1] Position [475, 480, 510, 490] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out6" SID "12769" Ports [1, 1] Position [475, 405, 510, 415] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out7" SID "12770" Ports [1, 1] Position [475, 420, 510, 430] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out8" SID "12771" Ports [1, 1] Position [475, 435, 510, 445] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "12772" Ports [2, 1] Position [345, 30, 385, 70] BlockMirror on NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,40,2,1,white,blue,0,140cc11c,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'" "q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "12773" Ports [2, 1] Position [465, 110, 495, 210] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,100,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 100 100 0 ],[0.77 0." "82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 100 100 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[54.44 " "54.44 58.44 54.44 58.44 58.44 58.44 54.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[50.44 50.44 54.44 54" ".44 50.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[46.44 46.44 50.44 50.44 46.44 ],[1 1 1 ])" ";\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[42.44 42.44 46.44 42.44 46.44 46.44 42.44 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\nco" "lor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc2" SID "12774" Ports [1, 1] Position [265, 143, 290, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc3" SID "12775" Ports [1, 1] Position [135, 178, 160, 192] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "yn" SID "12776" Position [545, 153, 575, 167] IconDisplay "Port number" } Block { BlockType Outport Name "accrm" SID "12777" Position [520, 288, 550, 302] Port "2" IconDisplay "Port number" } Line { SrcBlock "rst" SrcPort 1 Points [90, 0] Branch { Points [0, 215] DstBlock "Gateway Out1" DstPort 1 } Branch { Points [255, 0; 0, -180] DstBlock "Register1" DstPort 2 } } Line { SrcBlock "Gateway Out3" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out2" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out1" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out6" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out7" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out8" SrcPort 1 Points [50, 0] } Line { SrcBlock "a" SrcPort 1 Points [140, 0] Branch { Points [0, 275] DstBlock "Gateway Out7" DstPort 1 } Branch { DstBlock "bc2" DstPort 1 } } Line { SrcBlock "AddSub" SrcPort 1 Points [0, 0; 5, 0] Branch { Points [0, 305] DstBlock "Gateway Out8" DstPort 1 } Branch { Points [40, 0] Branch { Points [0, 160] DstBlock "accrm" DstPort 1 } Branch { Points [0, -95] DstBlock "Register1" DstPort 1 } Branch { DstBlock "Register2" DstPort 1 } } } Line { SrcBlock "Register2" SrcPort 1 Points [15, 0] Branch { Points [0, 50; 110, 0; 0, 385; -260, 0; 0, -110] DstBlock "Gateway Out3" DstPort 1 } Branch { DstBlock "yn" DstPort 1 } } Line { SrcBlock "Register1" SrcPort 1 Points [-15, 0] DstBlock "AddSub" DstPort 1 } Line { SrcBlock "ld" SrcPort 1 Points [45, 0] Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } Branch { DstBlock "bc3" DstPort 1 } } Line { SrcBlock "bc3" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "bc2" SrcPort 1 DstBlock "AddSub" DstPort 3 } Line { SrcBlock "coeff" SrcPort 1 Points [95, 0; 0, 20; 50, 0] Branch { Points [0, 275] DstBlock "Gateway Out6" DstPort 1 } Branch { DstBlock "AddSub" DstPort 2 } } } } Block { BlockType Reference Name "ROM" SID "12778" Ports [1, 1] Position [440, 328, 490, 372] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/ROM" SourceType "Xilinx Single Port Read-Only Memory Block" depth "length(coef2)" initVector "coef2" distributed_mem "Distributed memory" rst off init_reg "0" en off latency "1" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "longCorr_coef_nbits" bin_pt "longCorr_coef_bp" preci_type "Single" exp_width "8" frac_width "24" dbl_ovrd off optimize "Area" use_rpm off xl_use_area off xl_area "[1 1 0 1 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,308" block_type "sprom" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,44,1,1,white,blue,0,bbc23d60,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 44 44 0 ]);\npatch([11.65 20.32 26.32 32.32 38.32 26.32 17.65 11.65 ],[28.66" " 28.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([17.65 26.32 20.32 11.65 17.65 ],[22.66 22.66 28." "66 28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([11.65 20.32 26.32 17.65 11.65 ],[16.66 16.66 22.66 22.66 16.66 ]" ",[1 1 1 ]);\npatch([17.65 38.32 32.32 26.32 20.32 11.65 17.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'addr');\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end" " icon text');\n" } Block { BlockType Outport Name "x_dly" SID "12779" Position [790, 178, 820, 192] IconDisplay "Port number" } Block { BlockType Outport Name "x_dly_vout" SID "12780" Position [790, 223, 820, 237] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "y" SID "12781" Position [790, 293, 820, 307] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "y_vout" SID "12782" Position [785, 448, 815, 462] Port "4" IconDisplay "Port number" } Line { Name "ROM Addr" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 Points [150, 0] } Line { Name "Corr Out" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 Points [150, 0] } Line { Name "Corr Ld" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 Points [150, 0] } Line { Name "ROM Out" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 Points [150, 0] } Line { Name "ASR Out" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 Points [150, 0] } Line { Name "X In" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 Points [150, 0] } Line { Name "ASR Addr" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 Points [150, 0] } Line { Name "X Vin" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 Points [150, 0] } Line { SrcBlock "Delay" SrcPort 1 DstBlock "y_vout" DstPort 1 } Line { SrcBlock "vin" SrcPort 1 Points [25, 0] Branch { Points [0, -80] DstBlock "x_dly_vout" DstPort 1 } Branch { Points [0, 100] Branch { Points [230, 0] DstBlock "MAC" DstPort 4 } Branch { Points [0, 195] DstBlock "Gateway Out8" DstPort 1 } } Branch { DstBlock "ASR" DstPort 3 } } Line { SrcBlock "x" SrcPort 1 Points [100, 0] Branch { Points [0, 305] DstBlock "Gateway Out6" DstPort 1 } Branch { DstBlock "ASR" DstPort 1 } } Line { SrcBlock "From" SrcPort 1 Points [90, 0] Branch { Points [0, 300] DstBlock "Gateway Out7" DstPort 1 } Branch { DstBlock "ASR" DstPort 2 } } Line { SrcBlock "From1" SrcPort 1 Points [5, 0] Branch { Points [0, 330] DstBlock "Gateway Out5" DstPort 1 } Branch { DstBlock "ROM" DstPort 1 } } Line { SrcBlock "ASR" SrcPort 1 Points [35, 0] Branch { Points [0, 330] DstBlock "Gateway Out1" DstPort 1 } Branch { Points [0, -105] DstBlock "x_dly" DstPort 1 } Branch { DstBlock "MAC" DstPort 1 } } Line { SrcBlock "MAC" SrcPort 1 Points [0, -5; 15, 0] Branch { Points [0, 365] DstBlock "Gateway Out4" DstPort 1 } Branch { DstBlock "y" DstPort 1 } } Line { SrcBlock "ROM" SrcPort 1 Points [5, 0] Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } Branch { Points [0, -35] DstBlock "MAC" DstPort 2 } } Line { SrcBlock "From2" SrcPort 1 Points [145, 0] Branch { Points [0, 260] DstBlock "Gateway Out3" DstPort 1 } Branch { Points [90, 0] Branch { Points [0, 65] DstBlock "Delay" DstPort 1 } Branch { Points [0, -50] Branch { Points [0, -90; 160, 0] } Branch { DstBlock "MAC" DstPort 3 } } } } } } Block { BlockType SubSystem Name "C6" SID "12783" Ports [4, 4] Position [845, 207, 915, 293] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskPromptString "Coefficients (all)|Sub-correlator Ind|Coef/correlator" MaskStyleString "edit,edit,edit" MaskVariables "h=@1;c_ind=@2;N=@3;" MaskTunableValueString "on,on,on" MaskCallbackString "||" MaskEnableString "on,on,on" MaskVisibilityString "on,on,on" MaskToolTipString "on,on,on" MaskInitialization "coef2 = h((c_ind*N+1) : (c_ind + 1)*N);" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "h|5|N" System { Name "C6" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "122" Block { BlockType Inport Name "x" SID "12784" Position [265, 263, 295, 277] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "vin" SID "12785" Position [270, 303, 300, 317] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "12786" Position [270, 458, 300, 472] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "12787" Position [270, 503, 300, 517] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "ASR" SID "12788" Ports [3, 1] Position [445, 260, 490, 320] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Addressable Shift Register" SourceType "Xilinx Addressable Shift Register Block" infoedit "Delay of configurable length. Any element in the delay line can be addressed and driven onto the" " output port.

Hardware notes: This block is implemented using SRL16s. If Virtex-4 or Spartan-3 device is " "used, multiple SRLC16s are cascaded together." infer_latency off depth "length(coef2)" initVector "[0]" en on dbl_ovrd off use_behavioral_HDL off Optimization "Resource" xl_use_area off xl_area "[1 0 0 2 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,401" block_type "addrsr" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,60,3,1,white,blue,0,f8ea6153,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 60 60 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 60 60 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[36.66 3" "6.66 42.66 36.66 42.66 42.66 42.66 36.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[30.66 30.66 36.66 " "36.66 30.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[24.66 24.66 30.66 30.66 24.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[18.66 18.66 24.66 18.66 24.66 24.66 18.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'addr');\ncolor('black');port_label('input',3," "'en');\ncolor('black');port_label('output',1,'q');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Delay" SID "12789" Ports [1, 1] Position [705, 441, 730, 469] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "25,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 " "17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33" " 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('blac" "k');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "12790" Position [210, 280, 300, 300] ZOrder -9 ShowName off GotoTag "ltsCorr_dAddr" TagVisibility "scoped" } Block { BlockType From Name "From1" SID "12791" Position [210, 340, 300, 360] ZOrder -9 ShowName off GotoTag "ltsCorr_cAddr" TagVisibility "scoped" } Block { BlockType From Name "From2" SID "12792" Position [210, 380, 300, 400] ZOrder -9 ShowName off GotoTag "ltsCorr_ld" TagVisibility "scoped" } Block { BlockType Reference Name "Gateway Out1" SID "12793" Ports [1, 1] Position [745, 615, 780, 625] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "12794" Ports [1, 1] Position [745, 630, 780, 640] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "12795" Ports [1, 1] Position [745, 645, 780, 655] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Ld" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "12796" Ports [1, 1] Position [745, 660, 780, 670] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "12797" Ports [1, 1] Position [745, 675, 780, 685] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "12798" Ports [1, 1] Position [745, 570, 780, 580] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X In" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "12799" Ports [1, 1] Position [745, 585, 780, 595] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "12800" Ports [1, 1] Position [745, 600, 780, 610] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X Vin" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType SubSystem Name "MAC" SID "12801" Ports [4, 2] Position [575, 279, 660, 376] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "MAC" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "a" SID "12802" Position [35, 143, 65, 157] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "coeff" SID "12803" Position [35, 108, 65, 122] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "ld" SID "12804" Position [35, 178, 65, 192] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "rst" SID "12805" Position [35, 233, 65, 247] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub" SID "12806" Ports [3, 1] Position [340, 113, 385, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition or Subtraction" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Signed (2's comp)" n_bits "long_cor_acc_n_bits" bin_pt "0" quantization "Truncate" overflow "Flag as error" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[2 0 0 4 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,344" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,3,1,white,blue,0,02f64c57,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('input',3,'su" "b');\ncolor('black');port_label('output',1,'\\bf{a \\pm b}','texmode','on');\nfprintf('','COMMENT: end icon text" "');\n" } Block { BlockType Reference Name "Gateway Out1" SID "12807" Ports [1, 1] Position [475, 450, 510, 460] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out2" SID "12808" Ports [1, 1] Position [475, 465, 510, 475] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out3" SID "12809" Ports [1, 1] Position [475, 480, 510, 490] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out6" SID "12810" Ports [1, 1] Position [475, 405, 510, 415] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out7" SID "12811" Ports [1, 1] Position [475, 420, 510, 430] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out8" SID "12812" Ports [1, 1] Position [475, 435, 510, 445] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "12813" Ports [2, 1] Position [345, 30, 385, 70] BlockMirror on NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,40,2,1,white,blue,0,140cc11c,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'" "q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "12814" Ports [2, 1] Position [465, 110, 495, 210] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,100,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 100 100 0 ],[0.77 0." "82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 100 100 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[54.44 " "54.44 58.44 54.44 58.44 58.44 58.44 54.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[50.44 50.44 54.44 54" ".44 50.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[46.44 46.44 50.44 50.44 46.44 ],[1 1 1 ])" ";\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[42.44 42.44 46.44 42.44 46.44 46.44 42.44 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\nco" "lor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc2" SID "12815" Ports [1, 1] Position [265, 143, 290, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc3" SID "12816" Ports [1, 1] Position [135, 178, 160, 192] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "yn" SID "12817" Position [545, 153, 575, 167] IconDisplay "Port number" } Block { BlockType Outport Name "accrm" SID "12818" Position [520, 288, 550, 302] Port "2" IconDisplay "Port number" } Line { SrcBlock "coeff" SrcPort 1 Points [95, 0; 0, 20; 50, 0] Branch { DstBlock "AddSub" DstPort 2 } Branch { Points [0, 275] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "bc2" SrcPort 1 DstBlock "AddSub" DstPort 3 } Line { SrcBlock "bc3" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "ld" SrcPort 1 Points [45, 0] Branch { DstBlock "bc3" DstPort 1 } Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "Register1" SrcPort 1 Points [-15, 0] DstBlock "AddSub" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 Points [15, 0] Branch { DstBlock "yn" DstPort 1 } Branch { Points [0, 50; 110, 0; 0, 385; -260, 0; 0, -110] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "AddSub" SrcPort 1 Points [0, 0; 5, 0] Branch { Points [40, 0] Branch { DstBlock "Register2" DstPort 1 } Branch { Points [0, -95] DstBlock "Register1" DstPort 1 } Branch { Points [0, 160] DstBlock "accrm" DstPort 1 } } Branch { Points [0, 305] DstBlock "Gateway Out8" DstPort 1 } } Line { SrcBlock "a" SrcPort 1 Points [140, 0] Branch { DstBlock "bc2" DstPort 1 } Branch { Points [0, 275] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "Gateway Out8" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out7" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out6" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out1" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out2" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out3" SrcPort 1 Points [50, 0] } Line { SrcBlock "rst" SrcPort 1 Points [90, 0] Branch { Points [255, 0; 0, -180] DstBlock "Register1" DstPort 2 } Branch { Points [0, 215] DstBlock "Gateway Out1" DstPort 1 } } } } Block { BlockType Reference Name "ROM" SID "12819" Ports [1, 1] Position [440, 328, 490, 372] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/ROM" SourceType "Xilinx Single Port Read-Only Memory Block" depth "length(coef2)" initVector "coef2" distributed_mem "Distributed memory" rst off init_reg "0" en off latency "1" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "longCorr_coef_nbits" bin_pt "longCorr_coef_bp" preci_type "Single" exp_width "8" frac_width "24" dbl_ovrd off optimize "Area" use_rpm off xl_use_area off xl_area "[1 1 0 1 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,308" block_type "sprom" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,44,1,1,white,blue,0,bbc23d60,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 44 44 0 ]);\npatch([11.65 20.32 26.32 32.32 38.32 26.32 17.65 11.65 ],[28.66" " 28.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([17.65 26.32 20.32 11.65 17.65 ],[22.66 22.66 28." "66 28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([11.65 20.32 26.32 17.65 11.65 ],[16.66 16.66 22.66 22.66 16.66 ]" ",[1 1 1 ]);\npatch([17.65 38.32 32.32 26.32 20.32 11.65 17.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'addr');\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end" " icon text');\n" } Block { BlockType Outport Name "x_dly" SID "12820" Position [790, 178, 820, 192] IconDisplay "Port number" } Block { BlockType Outport Name "x_dly_vout" SID "12821" Position [790, 223, 820, 237] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "y" SID "12822" Position [790, 293, 820, 307] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "y_vout" SID "12823" Position [785, 448, 815, 462] Port "4" IconDisplay "Port number" } Line { SrcBlock "From2" SrcPort 1 Points [145, 0] Branch { Points [90, 0] Branch { Points [0, -50] Branch { DstBlock "MAC" DstPort 3 } Branch { Points [0, -90; 160, 0] } } Branch { Points [0, 65] DstBlock "Delay" DstPort 1 } } Branch { Points [0, 260] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "ROM" SrcPort 1 Points [5, 0] Branch { Points [0, -35] DstBlock "MAC" DstPort 2 } Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "MAC" SrcPort 1 Points [0, -5; 15, 0] Branch { DstBlock "y" DstPort 1 } Branch { Points [0, 365] DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "ASR" SrcPort 1 Points [35, 0] Branch { DstBlock "MAC" DstPort 1 } Branch { Points [0, -105] DstBlock "x_dly" DstPort 1 } Branch { Points [0, 330] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "From1" SrcPort 1 Points [5, 0] Branch { DstBlock "ROM" DstPort 1 } Branch { Points [0, 330] DstBlock "Gateway Out5" DstPort 1 } } Line { SrcBlock "From" SrcPort 1 Points [90, 0] Branch { DstBlock "ASR" DstPort 2 } Branch { Points [0, 300] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "x" SrcPort 1 Points [100, 0] Branch { DstBlock "ASR" DstPort 1 } Branch { Points [0, 305] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "vin" SrcPort 1 Points [25, 0] Branch { DstBlock "ASR" DstPort 3 } Branch { Points [0, 100] Branch { Points [0, 195] DstBlock "Gateway Out8" DstPort 1 } Branch { Points [230, 0] DstBlock "MAC" DstPort 4 } } Branch { Points [0, -80] DstBlock "x_dly_vout" DstPort 1 } } Line { SrcBlock "Delay" SrcPort 1 DstBlock "y_vout" DstPort 1 } Line { Name "X Vin" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 Points [150, 0] } Line { Name "ASR Addr" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 Points [150, 0] } Line { Name "X In" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 Points [150, 0] } Line { Name "ASR Out" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 Points [150, 0] } Line { Name "ROM Out" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 Points [150, 0] } Line { Name "Corr Ld" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 Points [150, 0] } Line { Name "Corr Out" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 Points [150, 0] } Line { Name "ROM Addr" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 Points [150, 0] } } } Block { BlockType SubSystem Name "C7" SID "12824" Ports [4, 4] Position [950, 207, 1020, 293] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskPromptString "Coefficients (all)|Sub-correlator Ind|Coef/correlator" MaskStyleString "edit,edit,edit" MaskVariables "h=@1;c_ind=@2;N=@3;" MaskTunableValueString "on,on,on" MaskCallbackString "||" MaskEnableString "on,on,on" MaskVisibilityString "on,on,on" MaskToolTipString "on,on,on" MaskInitialization "coef2 = h((c_ind*N+1) : (c_ind + 1)*N);" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "h|6|N" System { Name "C7" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "122" Block { BlockType Inport Name "x" SID "12825" Position [265, 263, 295, 277] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "vin" SID "12826" Position [270, 303, 300, 317] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "12827" Position [270, 458, 300, 472] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "12828" Position [270, 503, 300, 517] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "ASR" SID "12829" Ports [3, 1] Position [445, 260, 490, 320] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Addressable Shift Register" SourceType "Xilinx Addressable Shift Register Block" infoedit "Delay of configurable length. Any element in the delay line can be addressed and driven onto the" " output port.

Hardware notes: This block is implemented using SRL16s. If Virtex-4 or Spartan-3 device is " "used, multiple SRLC16s are cascaded together." infer_latency off depth "length(coef2)" initVector "[0]" en on dbl_ovrd off use_behavioral_HDL off Optimization "Resource" xl_use_area off xl_area "[1 0 0 2 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,401" block_type "addrsr" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,60,3,1,white,blue,0,f8ea6153,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 60 60 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 60 60 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[36.66 3" "6.66 42.66 36.66 42.66 42.66 42.66 36.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[30.66 30.66 36.66 " "36.66 30.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[24.66 24.66 30.66 30.66 24.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[18.66 18.66 24.66 18.66 24.66 24.66 18.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'addr');\ncolor('black');port_label('input',3," "'en');\ncolor('black');port_label('output',1,'q');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Delay" SID "12830" Ports [1, 1] Position [705, 441, 730, 469] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "25,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 " "17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33" " 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('blac" "k');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "12831" Position [210, 280, 300, 300] ZOrder -9 ShowName off GotoTag "ltsCorr_dAddr" TagVisibility "scoped" } Block { BlockType From Name "From1" SID "12832" Position [210, 340, 300, 360] ZOrder -9 ShowName off GotoTag "ltsCorr_cAddr" TagVisibility "scoped" } Block { BlockType From Name "From2" SID "12833" Position [210, 380, 300, 400] ZOrder -9 ShowName off GotoTag "ltsCorr_ld" TagVisibility "scoped" } Block { BlockType Reference Name "Gateway Out1" SID "12834" Ports [1, 1] Position [745, 615, 780, 625] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "12835" Ports [1, 1] Position [745, 630, 780, 640] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "12836" Ports [1, 1] Position [745, 645, 780, 655] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Ld" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "12837" Ports [1, 1] Position [745, 660, 780, 670] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "12838" Ports [1, 1] Position [745, 675, 780, 685] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "12839" Ports [1, 1] Position [745, 570, 780, 580] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X In" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "12840" Ports [1, 1] Position [745, 585, 780, 595] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "12841" Ports [1, 1] Position [745, 600, 780, 610] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X Vin" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType SubSystem Name "MAC" SID "12842" Ports [4, 2] Position [575, 279, 660, 376] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "MAC" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "a" SID "12843" Position [35, 143, 65, 157] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "coeff" SID "12844" Position [35, 108, 65, 122] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "ld" SID "12845" Position [35, 178, 65, 192] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "rst" SID "12846" Position [35, 233, 65, 247] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub" SID "12847" Ports [3, 1] Position [340, 113, 385, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition or Subtraction" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Signed (2's comp)" n_bits "long_cor_acc_n_bits" bin_pt "0" quantization "Truncate" overflow "Flag as error" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[2 0 0 4 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,344" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,3,1,white,blue,0,02f64c57,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('input',3,'su" "b');\ncolor('black');port_label('output',1,'\\bf{a \\pm b}','texmode','on');\nfprintf('','COMMENT: end icon text" "');\n" } Block { BlockType Reference Name "Gateway Out1" SID "12848" Ports [1, 1] Position [475, 450, 510, 460] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out2" SID "12849" Ports [1, 1] Position [475, 465, 510, 475] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out3" SID "12850" Ports [1, 1] Position [475, 480, 510, 490] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out6" SID "12851" Ports [1, 1] Position [475, 405, 510, 415] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out7" SID "12852" Ports [1, 1] Position [475, 420, 510, 430] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out8" SID "12853" Ports [1, 1] Position [475, 435, 510, 445] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "12854" Ports [2, 1] Position [345, 30, 385, 70] BlockMirror on NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,40,2,1,white,blue,0,140cc11c,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'" "q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "12855" Ports [2, 1] Position [465, 110, 495, 210] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,100,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 100 100 0 ],[0.77 0." "82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 100 100 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[54.44 " "54.44 58.44 54.44 58.44 58.44 58.44 54.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[50.44 50.44 54.44 54" ".44 50.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[46.44 46.44 50.44 50.44 46.44 ],[1 1 1 ])" ";\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[42.44 42.44 46.44 42.44 46.44 46.44 42.44 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\nco" "lor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc2" SID "12856" Ports [1, 1] Position [265, 143, 290, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc3" SID "12857" Ports [1, 1] Position [135, 178, 160, 192] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "yn" SID "12858" Position [545, 153, 575, 167] IconDisplay "Port number" } Block { BlockType Outport Name "accrm" SID "12859" Position [520, 288, 550, 302] Port "2" IconDisplay "Port number" } Line { SrcBlock "rst" SrcPort 1 Points [90, 0] Branch { Points [0, 215] DstBlock "Gateway Out1" DstPort 1 } Branch { Points [255, 0; 0, -180] DstBlock "Register1" DstPort 2 } } Line { SrcBlock "Gateway Out3" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out2" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out1" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out6" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out7" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out8" SrcPort 1 Points [50, 0] } Line { SrcBlock "a" SrcPort 1 Points [140, 0] Branch { Points [0, 275] DstBlock "Gateway Out7" DstPort 1 } Branch { DstBlock "bc2" DstPort 1 } } Line { SrcBlock "AddSub" SrcPort 1 Points [0, 0; 5, 0] Branch { Points [0, 305] DstBlock "Gateway Out8" DstPort 1 } Branch { Points [40, 0] Branch { Points [0, 160] DstBlock "accrm" DstPort 1 } Branch { Points [0, -95] DstBlock "Register1" DstPort 1 } Branch { DstBlock "Register2" DstPort 1 } } } Line { SrcBlock "Register2" SrcPort 1 Points [15, 0] Branch { Points [0, 50; 110, 0; 0, 385; -260, 0; 0, -110] DstBlock "Gateway Out3" DstPort 1 } Branch { DstBlock "yn" DstPort 1 } } Line { SrcBlock "Register1" SrcPort 1 Points [-15, 0] DstBlock "AddSub" DstPort 1 } Line { SrcBlock "ld" SrcPort 1 Points [45, 0] Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } Branch { DstBlock "bc3" DstPort 1 } } Line { SrcBlock "bc3" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "bc2" SrcPort 1 DstBlock "AddSub" DstPort 3 } Line { SrcBlock "coeff" SrcPort 1 Points [95, 0; 0, 20; 50, 0] Branch { Points [0, 275] DstBlock "Gateway Out6" DstPort 1 } Branch { DstBlock "AddSub" DstPort 2 } } } } Block { BlockType Reference Name "ROM" SID "12860" Ports [1, 1] Position [440, 328, 490, 372] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/ROM" SourceType "Xilinx Single Port Read-Only Memory Block" depth "length(coef2)" initVector "coef2" distributed_mem "Distributed memory" rst off init_reg "0" en off latency "1" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "longCorr_coef_nbits" bin_pt "longCorr_coef_bp" preci_type "Single" exp_width "8" frac_width "24" dbl_ovrd off optimize "Area" use_rpm off xl_use_area off xl_area "[1 1 0 1 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,308" block_type "sprom" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,44,1,1,white,blue,0,bbc23d60,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 44 44 0 ]);\npatch([11.65 20.32 26.32 32.32 38.32 26.32 17.65 11.65 ],[28.66" " 28.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([17.65 26.32 20.32 11.65 17.65 ],[22.66 22.66 28." "66 28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([11.65 20.32 26.32 17.65 11.65 ],[16.66 16.66 22.66 22.66 16.66 ]" ",[1 1 1 ]);\npatch([17.65 38.32 32.32 26.32 20.32 11.65 17.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'addr');\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end" " icon text');\n" } Block { BlockType Outport Name "x_dly" SID "12861" Position [790, 178, 820, 192] IconDisplay "Port number" } Block { BlockType Outport Name "x_dly_vout" SID "12862" Position [790, 223, 820, 237] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "y" SID "12863" Position [790, 293, 820, 307] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "y_vout" SID "12864" Position [785, 448, 815, 462] Port "4" IconDisplay "Port number" } Line { Name "ROM Addr" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 Points [150, 0] } Line { Name "Corr Out" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 Points [150, 0] } Line { Name "Corr Ld" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 Points [150, 0] } Line { Name "ROM Out" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 Points [150, 0] } Line { Name "ASR Out" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 Points [150, 0] } Line { Name "X In" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 Points [150, 0] } Line { Name "ASR Addr" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 Points [150, 0] } Line { Name "X Vin" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 Points [150, 0] } Line { SrcBlock "Delay" SrcPort 1 DstBlock "y_vout" DstPort 1 } Line { SrcBlock "vin" SrcPort 1 Points [25, 0] Branch { Points [0, -80] DstBlock "x_dly_vout" DstPort 1 } Branch { Points [0, 100] Branch { Points [230, 0] DstBlock "MAC" DstPort 4 } Branch { Points [0, 195] DstBlock "Gateway Out8" DstPort 1 } } Branch { DstBlock "ASR" DstPort 3 } } Line { SrcBlock "x" SrcPort 1 Points [100, 0] Branch { Points [0, 305] DstBlock "Gateway Out6" DstPort 1 } Branch { DstBlock "ASR" DstPort 1 } } Line { SrcBlock "From" SrcPort 1 Points [90, 0] Branch { Points [0, 300] DstBlock "Gateway Out7" DstPort 1 } Branch { DstBlock "ASR" DstPort 2 } } Line { SrcBlock "From1" SrcPort 1 Points [5, 0] Branch { Points [0, 330] DstBlock "Gateway Out5" DstPort 1 } Branch { DstBlock "ROM" DstPort 1 } } Line { SrcBlock "ASR" SrcPort 1 Points [35, 0] Branch { Points [0, 330] DstBlock "Gateway Out1" DstPort 1 } Branch { Points [0, -105] DstBlock "x_dly" DstPort 1 } Branch { DstBlock "MAC" DstPort 1 } } Line { SrcBlock "MAC" SrcPort 1 Points [0, -5; 15, 0] Branch { Points [0, 365] DstBlock "Gateway Out4" DstPort 1 } Branch { DstBlock "y" DstPort 1 } } Line { SrcBlock "ROM" SrcPort 1 Points [5, 0] Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } Branch { Points [0, -35] DstBlock "MAC" DstPort 2 } } Line { SrcBlock "From2" SrcPort 1 Points [145, 0] Branch { Points [0, 260] DstBlock "Gateway Out3" DstPort 1 } Branch { Points [90, 0] Branch { Points [0, 65] DstBlock "Delay" DstPort 1 } Branch { Points [0, -50] Branch { Points [0, -90; 160, 0] } Branch { DstBlock "MAC" DstPort 3 } } } } } } Block { BlockType SubSystem Name "C8" SID "12865" Ports [4, 4] Position [1060, 207, 1130, 293] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskPromptString "Coefficients (all)|Sub-correlator Ind|Coef/correlator" MaskStyleString "edit,edit,edit" MaskVariables "h=@1;c_ind=@2;N=@3;" MaskTunableValueString "on,on,on" MaskCallbackString "||" MaskEnableString "on,on,on" MaskVisibilityString "on,on,on" MaskToolTipString "on,on,on" MaskInitialization "coef2 = h((c_ind*N+1) : (c_ind + 1)*N);" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "h|7|N" System { Name "C8" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "122" Block { BlockType Inport Name "x" SID "12866" Position [265, 263, 295, 277] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "vin" SID "12867" Position [270, 303, 300, 317] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "12868" Position [270, 458, 300, 472] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "12869" Position [270, 503, 300, 517] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "ASR" SID "12870" Ports [3, 1] Position [445, 260, 490, 320] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Addressable Shift Register" SourceType "Xilinx Addressable Shift Register Block" infoedit "Delay of configurable length. Any element in the delay line can be addressed and driven onto the" " output port.

Hardware notes: This block is implemented using SRL16s. If Virtex-4 or Spartan-3 device is " "used, multiple SRLC16s are cascaded together." infer_latency off depth "length(coef2)" initVector "[0]" en on dbl_ovrd off use_behavioral_HDL off Optimization "Resource" xl_use_area off xl_area "[1 0 0 2 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,401" block_type "addrsr" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,60,3,1,white,blue,0,f8ea6153,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 60 60 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 60 60 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[36.66 3" "6.66 42.66 36.66 42.66 42.66 42.66 36.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[30.66 30.66 36.66 " "36.66 30.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[24.66 24.66 30.66 30.66 24.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[18.66 18.66 24.66 18.66 24.66 24.66 18.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'addr');\ncolor('black');port_label('input',3," "'en');\ncolor('black');port_label('output',1,'q');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Delay" SID "12871" Ports [1, 1] Position [705, 441, 730, 469] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "25,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 " "17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33" " 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('blac" "k');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "12872" Position [210, 280, 300, 300] ZOrder -9 ShowName off GotoTag "ltsCorr_dAddr" TagVisibility "scoped" } Block { BlockType From Name "From1" SID "12873" Position [210, 340, 300, 360] ZOrder -9 ShowName off GotoTag "ltsCorr_cAddr" TagVisibility "scoped" } Block { BlockType From Name "From2" SID "12874" Position [210, 380, 300, 400] ZOrder -9 ShowName off GotoTag "ltsCorr_ld" TagVisibility "scoped" } Block { BlockType Reference Name "Gateway Out1" SID "12875" Ports [1, 1] Position [745, 615, 780, 625] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "12876" Ports [1, 1] Position [745, 630, 780, 640] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "12877" Ports [1, 1] Position [745, 645, 780, 655] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Ld" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "12878" Ports [1, 1] Position [745, 660, 780, 670] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "12879" Ports [1, 1] Position [745, 675, 780, 685] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "12880" Ports [1, 1] Position [745, 570, 780, 580] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X In" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "12881" Ports [1, 1] Position [745, 585, 780, 595] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "12882" Ports [1, 1] Position [745, 600, 780, 610] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X Vin" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType SubSystem Name "MAC" SID "12883" Ports [4, 2] Position [575, 279, 660, 376] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "MAC" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "a" SID "12884" Position [35, 143, 65, 157] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "coeff" SID "12885" Position [35, 108, 65, 122] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "ld" SID "12886" Position [35, 178, 65, 192] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "rst" SID "12887" Position [35, 233, 65, 247] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub" SID "12888" Ports [3, 1] Position [340, 113, 385, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition or Subtraction" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Signed (2's comp)" n_bits "long_cor_acc_n_bits" bin_pt "0" quantization "Truncate" overflow "Flag as error" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[2 0 0 4 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,344" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,3,1,white,blue,0,02f64c57,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('input',3,'su" "b');\ncolor('black');port_label('output',1,'\\bf{a \\pm b}','texmode','on');\nfprintf('','COMMENT: end icon text" "');\n" } Block { BlockType Reference Name "Gateway Out1" SID "12889" Ports [1, 1] Position [475, 450, 510, 460] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out2" SID "12890" Ports [1, 1] Position [475, 465, 510, 475] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out3" SID "12891" Ports [1, 1] Position [475, 480, 510, 490] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out6" SID "12892" Ports [1, 1] Position [475, 405, 510, 415] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out7" SID "12893" Ports [1, 1] Position [475, 420, 510, 430] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out8" SID "12894" Ports [1, 1] Position [475, 435, 510, 445] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "12895" Ports [2, 1] Position [345, 30, 385, 70] BlockMirror on NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,40,2,1,white,blue,0,140cc11c,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'" "q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "12896" Ports [2, 1] Position [465, 110, 495, 210] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,100,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 100 100 0 ],[0.77 0." "82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 100 100 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[54.44 " "54.44 58.44 54.44 58.44 58.44 58.44 54.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[50.44 50.44 54.44 54" ".44 50.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[46.44 46.44 50.44 50.44 46.44 ],[1 1 1 ])" ";\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[42.44 42.44 46.44 42.44 46.44 46.44 42.44 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\nco" "lor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc2" SID "12897" Ports [1, 1] Position [265, 143, 290, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc3" SID "12898" Ports [1, 1] Position [135, 178, 160, 192] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "yn" SID "12899" Position [545, 153, 575, 167] IconDisplay "Port number" } Block { BlockType Outport Name "accrm" SID "12900" Position [520, 288, 550, 302] Port "2" IconDisplay "Port number" } Line { SrcBlock "coeff" SrcPort 1 Points [95, 0; 0, 20; 50, 0] Branch { DstBlock "AddSub" DstPort 2 } Branch { Points [0, 275] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "bc2" SrcPort 1 DstBlock "AddSub" DstPort 3 } Line { SrcBlock "bc3" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "ld" SrcPort 1 Points [45, 0] Branch { DstBlock "bc3" DstPort 1 } Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "Register1" SrcPort 1 Points [-15, 0] DstBlock "AddSub" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 Points [15, 0] Branch { DstBlock "yn" DstPort 1 } Branch { Points [0, 50; 110, 0; 0, 385; -260, 0; 0, -110] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "AddSub" SrcPort 1 Points [0, 0; 5, 0] Branch { Points [40, 0] Branch { DstBlock "Register2" DstPort 1 } Branch { Points [0, -95] DstBlock "Register1" DstPort 1 } Branch { Points [0, 160] DstBlock "accrm" DstPort 1 } } Branch { Points [0, 305] DstBlock "Gateway Out8" DstPort 1 } } Line { SrcBlock "a" SrcPort 1 Points [140, 0] Branch { DstBlock "bc2" DstPort 1 } Branch { Points [0, 275] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "Gateway Out8" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out7" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out6" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out1" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out2" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out3" SrcPort 1 Points [50, 0] } Line { SrcBlock "rst" SrcPort 1 Points [90, 0] Branch { Points [255, 0; 0, -180] DstBlock "Register1" DstPort 2 } Branch { Points [0, 215] DstBlock "Gateway Out1" DstPort 1 } } } } Block { BlockType Reference Name "ROM" SID "12901" Ports [1, 1] Position [440, 328, 490, 372] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/ROM" SourceType "Xilinx Single Port Read-Only Memory Block" depth "length(coef2)" initVector "coef2" distributed_mem "Distributed memory" rst off init_reg "0" en off latency "1" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "longCorr_coef_nbits" bin_pt "longCorr_coef_bp" preci_type "Single" exp_width "8" frac_width "24" dbl_ovrd off optimize "Area" use_rpm off xl_use_area off xl_area "[1 1 0 1 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,308" block_type "sprom" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,44,1,1,white,blue,0,bbc23d60,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 44 44 0 ]);\npatch([11.65 20.32 26.32 32.32 38.32 26.32 17.65 11.65 ],[28.66" " 28.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([17.65 26.32 20.32 11.65 17.65 ],[22.66 22.66 28." "66 28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([11.65 20.32 26.32 17.65 11.65 ],[16.66 16.66 22.66 22.66 16.66 ]" ",[1 1 1 ]);\npatch([17.65 38.32 32.32 26.32 20.32 11.65 17.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'addr');\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end" " icon text');\n" } Block { BlockType Outport Name "x_dly" SID "12902" Position [790, 178, 820, 192] IconDisplay "Port number" } Block { BlockType Outport Name "x_dly_vout" SID "12903" Position [790, 223, 820, 237] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "y" SID "12904" Position [790, 293, 820, 307] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "y_vout" SID "12905" Position [785, 448, 815, 462] Port "4" IconDisplay "Port number" } Line { SrcBlock "From2" SrcPort 1 Points [145, 0] Branch { Points [90, 0] Branch { Points [0, -50] Branch { DstBlock "MAC" DstPort 3 } Branch { Points [0, -90; 160, 0] } } Branch { Points [0, 65] DstBlock "Delay" DstPort 1 } } Branch { Points [0, 260] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "ROM" SrcPort 1 Points [5, 0] Branch { Points [0, -35] DstBlock "MAC" DstPort 2 } Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "MAC" SrcPort 1 Points [0, -5; 15, 0] Branch { DstBlock "y" DstPort 1 } Branch { Points [0, 365] DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "ASR" SrcPort 1 Points [35, 0] Branch { DstBlock "MAC" DstPort 1 } Branch { Points [0, -105] DstBlock "x_dly" DstPort 1 } Branch { Points [0, 330] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "From1" SrcPort 1 Points [5, 0] Branch { DstBlock "ROM" DstPort 1 } Branch { Points [0, 330] DstBlock "Gateway Out5" DstPort 1 } } Line { SrcBlock "From" SrcPort 1 Points [90, 0] Branch { DstBlock "ASR" DstPort 2 } Branch { Points [0, 300] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "x" SrcPort 1 Points [100, 0] Branch { DstBlock "ASR" DstPort 1 } Branch { Points [0, 305] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "vin" SrcPort 1 Points [25, 0] Branch { DstBlock "ASR" DstPort 3 } Branch { Points [0, 100] Branch { Points [0, 195] DstBlock "Gateway Out8" DstPort 1 } Branch { Points [230, 0] DstBlock "MAC" DstPort 4 } } Branch { Points [0, -80] DstBlock "x_dly_vout" DstPort 1 } } Line { SrcBlock "Delay" SrcPort 1 DstBlock "y_vout" DstPort 1 } Line { Name "X Vin" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 Points [150, 0] } Line { Name "ASR Addr" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 Points [150, 0] } Line { Name "X In" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 Points [150, 0] } Line { Name "ASR Out" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 Points [150, 0] } Line { Name "ROM Out" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 Points [150, 0] } Line { Name "Corr Ld" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 Points [150, 0] } Line { Name "Corr Out" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 Points [150, 0] } Line { Name "ROM Addr" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 Points [150, 0] } } } Block { BlockType Reference Name "Gateway Out1" SID "12906" Ports [1, 1] Position [1195, 75, 1230, 85] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out10" SID "12907" Ports [1, 1] Position [1195, 120, 1230, 130] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out11" SID "12908" Ports [1, 1] Position [1195, 135, 1230, 145] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out12" SID "12909" Ports [1, 1] Position [1195, 150, 1230, 160] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out13" SID "12910" Ports [1, 1] Position [1195, 165, 1230, 175] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out14" SID "12911" Ports [1, 1] Position [1225, 180, 1260, 190] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out2" SID "12912" Ports [1, 1] Position [740, 720, 775, 730] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out3" SID "12913" Ports [1, 1] Position [740, 690, 775, 700] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out4" SID "12914" Ports [1, 1] Position [740, 705, 775, 715] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out5" SID "12915" Ports [1, 1] Position [740, 735, 775, 745] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out6" SID "12916" Ports [1, 1] Position [1195, 45, 1230, 55] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out7" SID "12917" Ports [1, 1] Position [1195, 60, 1230, 70] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out8" SID "12918" Ports [1, 1] Position [1195, 90, 1230, 100] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out9" SID "12919" Ports [1, 1] Position [1195, 105, 1230, 115] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Outport Name "y" SID "12920" Position [1290, 568, 1320, 582] IconDisplay "Port number" } Block { BlockType Outport Name "y_vout" SID "12921" Position [1290, 523, 1320, 537] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "x_dly" SID "12922" Position [1260, 213, 1290, 227] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "x_dly_vout" SID "12923" Position [1260, 253, 1290, 267] Port "4" IconDisplay "Port number" } Line { SrcBlock "C8" SrcPort 2 Points [110, 0] DstBlock "x_dly_vout" DstPort 1 } Line { SrcBlock "C8" SrcPort 1 DstBlock "x_dly" DstPort 1 } Line { SrcBlock "Gateway Out14" SrcPort 1 Points [20, 0] } Line { SrcBlock "Gateway Out13" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out12" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out11" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out10" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out9" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out1" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out8" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out6" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out7" SrcPort 1 Points [50, 0] } Line { SrcBlock "C8" SrcPort 4 Points [40, 0; 0, 250] DstBlock "y_vout" DstPort 1 } Line { SrcBlock "AddSub4" SrcPort 1 Points [45, 0] Branch { Points [155, 0] Branch { Points [0, -390] DstBlock "Gateway Out14" DstPort 1 } Branch { DstBlock "y" DstPort 1 } } Branch { Points [0, 75; -400, 0; 0, 90] DstBlock "Gateway Out5" DstPort 1 } } Line { SrcBlock "AddSub1" SrcPort 1 Points [0, 60] DstBlock "AddSub4" DstPort 1 } Line { SrcBlock "AddSub13" SrcPort 1 Points [0, 85] DstBlock "AddSub4" DstPort 2 } Line { SrcBlock "AddSub7" SrcPort 1 Points [0, 35] DstBlock "AddSub1" DstPort 2 } Line { SrcBlock "AddSub6" SrcPort 1 DstBlock "AddSub1" DstPort 1 } Line { SrcBlock "C7" SrcPort 3 Points [20, 0] Branch { Points [0, -105] DstBlock "Gateway Out12" DstPort 1 } Branch { Points [0, 65; 75, 0] DstBlock "AddSub7" DstPort 1 } } Line { SrcBlock "C8" SrcPort 3 Points [10, 0] Branch { Points [0, -90] DstBlock "Gateway Out13" DstPort 1 } Branch { DstBlock "AddSub7" DstPort 2 } } Line { SrcBlock "C5" SrcPort 3 Points [10, 0] Branch { Points [0, -135] DstBlock "Gateway Out10" DstPort 1 } Branch { Points [0, 70; 85, 0] DstBlock "AddSub6" DstPort 1 } } Line { SrcBlock "C6" SrcPort 3 Points [15, 0] Branch { Points [0, -120] DstBlock "Gateway Out11" DstPort 1 } Branch { DstBlock "AddSub6" DstPort 2 } } Line { SrcBlock "C7" SrcPort 2 DstBlock "C8" DstPort 2 } Line { SrcBlock "C7" SrcPort 1 DstBlock "C8" DstPort 1 } Line { SrcBlock "C6" SrcPort 2 DstBlock "C7" DstPort 2 } Line { SrcBlock "C6" SrcPort 1 DstBlock "C7" DstPort 1 } Line { SrcBlock "C5" SrcPort 2 DstBlock "C6" DstPort 2 } Line { SrcBlock "C5" SrcPort 1 DstBlock "C6" DstPort 1 } Line { SrcBlock "C4" SrcPort 3 Points [15, 0] Branch { Points [0, -150] DstBlock "Gateway Out9" DstPort 1 } Branch { DstBlock "AddSub12" DstPort 2 } } Line { SrcBlock "C4" SrcPort 2 DstBlock "C5" DstPort 2 } Line { SrcBlock "C4" SrcPort 1 DstBlock "C5" DstPort 1 } Line { SrcBlock "C3" SrcPort 3 Points [20, 0] Branch { Points [0, -165] DstBlock "Gateway Out8" DstPort 1 } Branch { Points [0, 65; 80, 0] DstBlock "AddSub12" DstPort 1 } } Line { SrcBlock "C3" SrcPort 2 DstBlock "C4" DstPort 2 } Line { SrcBlock "C3" SrcPort 1 DstBlock "C4" DstPort 1 } Line { SrcBlock "C1" SrcPort 3 Points [15, 0] Branch { Points [0, -195] DstBlock "Gateway Out7" DstPort 1 } Branch { Points [0, 55] Branch { Points [0, 410] DstBlock "Gateway Out2" DstPort 1 } Branch { Points [0, 5; 95, 0] DstBlock "AddSub5" DstPort 1 } } } Line { SrcBlock "C2" SrcPort 3 Points [20, 0] Branch { Points [0, -180] DstBlock "Gateway Out1" DstPort 1 } Branch { DstBlock "AddSub5" DstPort 2 } } Line { SrcBlock "C2" SrcPort 2 DstBlock "C3" DstPort 2 } Line { SrcBlock "C2" SrcPort 1 DstBlock "C3" DstPort 1 } Line { SrcBlock "C1" SrcPort 2 DstBlock "C2" DstPort 2 } Line { SrcBlock "C1" SrcPort 1 DstBlock "C2" DstPort 1 } Line { SrcBlock "x_valid" SrcPort 1 Points [200, 0] Branch { Points [0, 450] DstBlock "Gateway Out4" DstPort 1 } Branch { Points [0, -20] DstBlock "C1" DstPort 2 } } Line { Points [780, 755; 50, 0] } Line { SrcBlock "Gateway Out2" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out5" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out3" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out4" SrcPort 1 Points [50, 0] } Line { SrcBlock "AddSub5" SrcPort 1 Points [0, 35] DstBlock "AddSub13" DstPort 1 } Line { SrcBlock "AddSub12" SrcPort 1 DstBlock "AddSub13" DstPort 2 } Line { SrcBlock "x" SrcPort 1 Points [210, 0] Branch { Points [0, -170] DstBlock "Gateway Out6" DstPort 1 } Branch { Points [0, 475] DstBlock "Gateway Out3" DstPort 1 } Branch { DstBlock "C1" DstPort 1 } } } } Block { BlockType SubSystem Name "C4" SID "12924" Ports [2, 4] Position [725, 453, 810, 522] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskPromptString "Coefficients/correlator|Coefficients|Input sample period" MaskStyleString "edit,edit,edit" MaskVariables "N=@1;h=@2;Ts_In=@3;" MaskTunableValueString "on,on,on" MaskCallbackString "||" MaskEnableString "on,on,on" MaskVisibilityString "on,on,on" MaskToolTipString "on,on,on" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "4|longCorr_coef_i(33:64)|4" System { Name "C4" Location [480, 85, 2304, 1455] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "156" Block { BlockType Inport Name "x" SID "12925" Position [35, 213, 65, 227] IconDisplay "Port number" } Block { BlockType Inport Name "x_valid" SID "12926" Position [35, 253, 65, 267] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub1" SID "12927" Ports [2, 1] Position [915, 455, 955, 495] BlockRotation 270 BlockMirror on NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "1" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[3 6 0 5 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,40,2,1,white,blue,0,e85d8a90,down,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bf{a + b}','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\ne" "wline\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub12" SID "12928" Ports [2, 1] Position [684, 360, 731, 400] BlockRotation 270 BlockMirror on NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "1" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[3 5 0 4 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "47,40,2,1,white,blue,0,e85d8a90,down,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 47 47 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 47 47 0 0 ],[0 0 40 40 0 ]);\npatch([11.875 19.1 24.1 29.1 34.1 24.1 16.875 11.875 ],[25.55 2" "5.55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([16.875 24.1 19.1 11.875 16.875 ],[20.55 20.55 25.5" "5 25.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([11.875 19.1 24.1 16.875 11.875 ],[15.55 15.55 20.55 20.55 15.55 ]" ",[1 1 1 ]);\npatch([16.875 34.1 29.1 24.1 19.1 11.875 16.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('b" "lack');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output'" ",1,'\\bf{a + b}','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(" "' \\newline\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub13" SID "12929" Ports [2, 1] Position [680, 455, 720, 495] BlockRotation 270 BlockMirror on NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "1" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[3 6 0 5 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,40,2,1,white,blue,0,e85d8a90,down,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bf{a + b}','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\ne" "wline\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub4" SID "12930" Ports [2, 1] Position [960, 549, 1000, 596] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "1" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[4 7 0 6 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,47,2,1,white,blue,0,e85d8a90,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 47 47 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 47 47 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[28.55 28." "55 33.55 28.55 33.55 33.55 33.55 28.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[23.55 23.55 28.55 2" "8.55 23.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[18.55 18.55 23.55 23.55 18.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[13.55 13.55 18.55 13.55 18.55 18.55 13.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bf{a + b}','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\ne" "wline\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub5" SID "12931" Ports [2, 1] Position [475, 360, 515, 400] BlockRotation 270 BlockMirror on NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "1" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[3 6 0 5 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,40,2,1,white,blue,0,e85d8a90,down,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bf{a + b}','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\ne" "wline\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub6" SID "12932" Ports [2, 1] Position [899, 360, 946, 400] BlockRotation 270 BlockMirror on NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "1" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[3 5 0 4 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "47,40,2,1,white,blue,0,e85d8a90,down,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 47 47 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 47 47 0 0 ],[0 0 40 40 0 ]);\npatch([11.875 19.1 24.1 29.1 34.1 24.1 16.875 11.875 ],[25.55 2" "5.55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([16.875 24.1 19.1 11.875 16.875 ],[20.55 20.55 25.5" "5 25.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([11.875 19.1 24.1 16.875 11.875 ],[15.55 15.55 20.55 20.55 15.55 ]" ",[1 1 1 ]);\npatch([16.875 34.1 29.1 24.1 19.1 11.875 16.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('b" "lack');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output'" ",1,'\\bf{a + b}','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(" "' \\newline\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub7" SID "12933" Ports [2, 1] Position [1109, 360, 1156, 400] BlockRotation 270 BlockMirror on NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "1" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[3 5 0 4 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "47,40,2,1,white,blue,0,e85d8a90,down,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 47 47 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 47 47 0 0 ],[0 0 40 40 0 ]);\npatch([11.875 19.1 24.1 29.1 34.1 24.1 16.875 11.875 ],[25.55 2" "5.55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([16.875 24.1 19.1 11.875 16.875 ],[20.55 20.55 25.5" "5 25.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([11.875 19.1 24.1 16.875 11.875 ],[15.55 15.55 20.55 20.55 15.55 ]" ",[1 1 1 ]);\npatch([16.875 34.1 29.1 24.1 19.1 11.875 16.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('b" "lack');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output'" ",1,'\\bf{a + b}','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(" "' \\newline\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "C1" SID "12934" Ports [4, 4] Position [300, 207, 370, 293] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskPromptString "Coefficients (all)|Sub-correlator Ind|Coef/correlator" MaskStyleString "edit,edit,edit" MaskVariables "h=@1;c_ind=@2;N=@3;" MaskTunableValueString "on,on,on" MaskCallbackString "||" MaskEnableString "on,on,on" MaskVisibilityString "on,on,on" MaskToolTipString "on,on,on" MaskInitialization "coef2 = h((c_ind*N+1) : (c_ind + 1)*N);" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "h|0|N" System { Name "C1" Location [480, 85, 2304, 1471] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "122" Block { BlockType Inport Name "x" SID "12935" Position [265, 263, 295, 277] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "vin" SID "12936" Position [270, 303, 300, 317] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "12937" Position [270, 458, 300, 472] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "12938" Position [270, 503, 300, 517] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "ASR" SID "12939" Ports [3, 1] Position [445, 260, 490, 320] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Addressable Shift Register" SourceType "Xilinx Addressable Shift Register Block" infoedit "Delay of configurable length. Any element in the delay line can be addressed and driven onto the" " output port.

Hardware notes: This block is implemented using SRL16s. If Virtex-4 or Spartan-3 device is " "used, multiple SRLC16s are cascaded together." infer_latency off depth "length(coef2)" initVector "[0]" en on dbl_ovrd off use_behavioral_HDL off Optimization "Resource" xl_use_area off xl_area "[1 0 0 2 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,401" block_type "addrsr" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,60,3,1,white,blue,0,f8ea6153,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 60 60 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 60 60 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[36.66 3" "6.66 42.66 36.66 42.66 42.66 42.66 36.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[30.66 30.66 36.66 " "36.66 30.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[24.66 24.66 30.66 30.66 24.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[18.66 18.66 24.66 18.66 24.66 24.66 18.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'addr');\ncolor('black');port_label('input',3," "'en');\ncolor('black');port_label('output',1,'q');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Delay" SID "12940" Ports [1, 1] Position [705, 441, 730, 469] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "25,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 " "17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33" " 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('blac" "k');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "12941" Position [210, 280, 300, 300] ZOrder -9 ShowName off GotoTag "ltsCorr_dAddr" TagVisibility "scoped" } Block { BlockType From Name "From1" SID "12942" Position [210, 340, 300, 360] ZOrder -9 ShowName off GotoTag "ltsCorr_cAddr" TagVisibility "scoped" } Block { BlockType From Name "From2" SID "12943" Position [210, 380, 300, 400] ZOrder -9 ShowName off GotoTag "ltsCorr_ld" TagVisibility "scoped" } Block { BlockType Reference Name "Gateway Out1" SID "12944" Ports [1, 1] Position [745, 615, 780, 625] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "12945" Ports [1, 1] Position [745, 630, 780, 640] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "12946" Ports [1, 1] Position [745, 645, 780, 655] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Ld" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "12947" Ports [1, 1] Position [745, 660, 780, 670] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "12948" Ports [1, 1] Position [745, 675, 780, 685] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "12949" Ports [1, 1] Position [745, 570, 780, 580] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X In" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "12950" Ports [1, 1] Position [745, 585, 780, 595] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "12951" Ports [1, 1] Position [745, 600, 780, 610] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X Vin" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType SubSystem Name "MAC" SID "12952" Ports [4, 2] Position [575, 279, 660, 376] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "MAC" Location [88, 301, 2330, 1301] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "a" SID "12953" Position [35, 143, 65, 157] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "coeff" SID "12954" Position [35, 108, 65, 122] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "ld" SID "12955" Position [35, 178, 65, 192] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "rst" SID "12956" Position [35, 233, 65, 247] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub" SID "12957" Ports [3, 1] Position [340, 113, 385, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition or Subtraction" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Signed (2's comp)" n_bits "long_cor_acc_n_bits" bin_pt "0" quantization "Truncate" overflow "Flag as error" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[2 0 0 4 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,344" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,3,1,white,blue,0,02f64c57,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('input',3,'su" "b');\ncolor('black');port_label('output',1,'\\bf{a \\pm b}','texmode','on');\nfprintf('','COMMENT: end icon text" "');\n" } Block { BlockType Reference Name "Gateway Out1" SID "12958" Ports [1, 1] Position [475, 450, 510, 460] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out2" SID "12959" Ports [1, 1] Position [475, 465, 510, 475] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out3" SID "12960" Ports [1, 1] Position [475, 480, 510, 490] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out6" SID "12961" Ports [1, 1] Position [475, 405, 510, 415] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out7" SID "12962" Ports [1, 1] Position [475, 420, 510, 430] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out8" SID "12963" Ports [1, 1] Position [475, 435, 510, 445] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "12964" Ports [2, 1] Position [345, 30, 385, 70] BlockMirror on NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,40,2,1,white,blue,0,140cc11c,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'" "q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "12965" Ports [2, 1] Position [465, 110, 495, 210] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,100,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 100 100 0 ],[0.77 0." "82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 100 100 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[54.44 " "54.44 58.44 54.44 58.44 58.44 58.44 54.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[50.44 50.44 54.44 54" ".44 50.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[46.44 46.44 50.44 50.44 46.44 ],[1 1 1 ])" ";\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[42.44 42.44 46.44 42.44 46.44 46.44 42.44 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\nco" "lor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc2" SID "12966" Ports [1, 1] Position [265, 143, 290, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc3" SID "12967" Ports [1, 1] Position [135, 178, 160, 192] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "yn" SID "12968" Position [545, 153, 575, 167] IconDisplay "Port number" } Block { BlockType Outport Name "accrm" SID "12969" Position [520, 288, 550, 302] Port "2" IconDisplay "Port number" } Line { SrcBlock "coeff" SrcPort 1 Points [95, 0; 0, 20; 50, 0] Branch { DstBlock "AddSub" DstPort 2 } Branch { Points [0, 275] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "bc2" SrcPort 1 DstBlock "AddSub" DstPort 3 } Line { SrcBlock "bc3" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "ld" SrcPort 1 Points [45, 0] Branch { DstBlock "bc3" DstPort 1 } Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "Register1" SrcPort 1 Points [-15, 0] DstBlock "AddSub" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 Points [15, 0] Branch { DstBlock "yn" DstPort 1 } Branch { Points [0, 50; 110, 0; 0, 385; -260, 0; 0, -110] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "AddSub" SrcPort 1 Points [0, 0; 5, 0] Branch { Points [40, 0] Branch { DstBlock "Register2" DstPort 1 } Branch { Points [0, -95] DstBlock "Register1" DstPort 1 } Branch { Points [0, 160] DstBlock "accrm" DstPort 1 } } Branch { Points [0, 305] DstBlock "Gateway Out8" DstPort 1 } } Line { SrcBlock "a" SrcPort 1 Points [140, 0] Branch { DstBlock "bc2" DstPort 1 } Branch { Points [0, 275] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "Gateway Out8" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out7" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out6" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out1" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out2" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out3" SrcPort 1 Points [50, 0] } Line { SrcBlock "rst" SrcPort 1 Points [90, 0] Branch { Points [255, 0; 0, -180] DstBlock "Register1" DstPort 2 } Branch { Points [0, 215] DstBlock "Gateway Out1" DstPort 1 } } } } Block { BlockType Reference Name "ROM" SID "12970" Ports [1, 1] Position [440, 328, 490, 372] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/ROM" SourceType "Xilinx Single Port Read-Only Memory Block" depth "length(coef2)" initVector "coef2" distributed_mem "Distributed memory" rst off init_reg "0" en off latency "1" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "longCorr_coef_nbits" bin_pt "longCorr_coef_bp" preci_type "Single" exp_width "8" frac_width "24" dbl_ovrd off optimize "Area" use_rpm off xl_use_area off xl_area "[1 1 0 1 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,308" block_type "sprom" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,44,1,1,white,blue,0,bbc23d60,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 44 44 0 ]);\npatch([11.65 20.32 26.32 32.32 38.32 26.32 17.65 11.65 ],[28.66" " 28.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([17.65 26.32 20.32 11.65 17.65 ],[22.66 22.66 28." "66 28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([11.65 20.32 26.32 17.65 11.65 ],[16.66 16.66 22.66 22.66 16.66 ]" ",[1 1 1 ]);\npatch([17.65 38.32 32.32 26.32 20.32 11.65 17.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'addr');\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end" " icon text');\n" } Block { BlockType Outport Name "x_dly" SID "12971" Position [790, 178, 820, 192] IconDisplay "Port number" } Block { BlockType Outport Name "x_dly_vout" SID "12972" Position [790, 223, 820, 237] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "y" SID "12973" Position [790, 293, 820, 307] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "y_vout" SID "12974" Position [785, 448, 815, 462] Port "4" IconDisplay "Port number" } Line { SrcBlock "From2" SrcPort 1 Points [145, 0] Branch { Points [90, 0] Branch { Points [0, -50] Branch { DstBlock "MAC" DstPort 3 } Branch { Points [0, -90; 160, 0] } } Branch { Points [0, 65] DstBlock "Delay" DstPort 1 } } Branch { Points [0, 260] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "ROM" SrcPort 1 Points [5, 0] Branch { Points [0, -35] DstBlock "MAC" DstPort 2 } Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "MAC" SrcPort 1 Points [0, -5; 15, 0] Branch { DstBlock "y" DstPort 1 } Branch { Points [0, 365] DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "ASR" SrcPort 1 Points [35, 0] Branch { DstBlock "MAC" DstPort 1 } Branch { Points [0, -105] DstBlock "x_dly" DstPort 1 } Branch { Points [0, 330] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "From1" SrcPort 1 Points [5, 0] Branch { DstBlock "ROM" DstPort 1 } Branch { Points [0, 330] DstBlock "Gateway Out5" DstPort 1 } } Line { SrcBlock "From" SrcPort 1 Points [90, 0] Branch { DstBlock "ASR" DstPort 2 } Branch { Points [0, 300] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "x" SrcPort 1 Points [100, 0] Branch { DstBlock "ASR" DstPort 1 } Branch { Points [0, 305] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "vin" SrcPort 1 Points [25, 0] Branch { DstBlock "ASR" DstPort 3 } Branch { Points [0, 100] Branch { Points [0, 195] DstBlock "Gateway Out8" DstPort 1 } Branch { Points [230, 0] DstBlock "MAC" DstPort 4 } } Branch { Points [0, -80] DstBlock "x_dly_vout" DstPort 1 } } Line { SrcBlock "Delay" SrcPort 1 DstBlock "y_vout" DstPort 1 } Line { Name "X Vin" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 Points [150, 0] } Line { Name "ASR Addr" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 Points [150, 0] } Line { Name "X In" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 Points [150, 0] } Line { Name "ASR Out" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 Points [150, 0] } Line { Name "ROM Out" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 Points [150, 0] } Line { Name "Corr Ld" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 Points [150, 0] } Line { Name "Corr Out" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 Points [150, 0] } Line { Name "ROM Addr" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 Points [150, 0] } } } Block { BlockType SubSystem Name "C2" SID "12975" Ports [4, 4] Position [410, 207, 480, 293] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskPromptString "Coefficients (all)|Sub-correlator Ind|Coef/correlator" MaskStyleString "edit,edit,edit" MaskVariables "h=@1;c_ind=@2;N=@3;" MaskTunableValueString "on,on,on" MaskCallbackString "||" MaskEnableString "on,on,on" MaskVisibilityString "on,on,on" MaskToolTipString "on,on,on" MaskInitialization "coef2 = h((c_ind*N+1) : (c_ind + 1)*N);" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "h|1|N" System { Name "C2" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "122" Block { BlockType Inport Name "x" SID "12976" Position [265, 263, 295, 277] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "vin" SID "12977" Position [270, 303, 300, 317] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "12978" Position [270, 458, 300, 472] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "12979" Position [270, 503, 300, 517] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "ASR" SID "12980" Ports [3, 1] Position [445, 260, 490, 320] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Addressable Shift Register" SourceType "Xilinx Addressable Shift Register Block" infoedit "Delay of configurable length. Any element in the delay line can be addressed and driven onto the" " output port.

Hardware notes: This block is implemented using SRL16s. If Virtex-4 or Spartan-3 device is " "used, multiple SRLC16s are cascaded together." infer_latency off depth "length(coef2)" initVector "[0]" en on dbl_ovrd off use_behavioral_HDL off Optimization "Resource" xl_use_area off xl_area "[1 0 0 2 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,401" block_type "addrsr" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,60,3,1,white,blue,0,f8ea6153,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 60 60 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 60 60 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[36.66 3" "6.66 42.66 36.66 42.66 42.66 42.66 36.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[30.66 30.66 36.66 " "36.66 30.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[24.66 24.66 30.66 30.66 24.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[18.66 18.66 24.66 18.66 24.66 24.66 18.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'addr');\ncolor('black');port_label('input',3," "'en');\ncolor('black');port_label('output',1,'q');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Delay" SID "12981" Ports [1, 1] Position [705, 441, 730, 469] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "25,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 " "17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33" " 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('blac" "k');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "12982" Position [210, 280, 300, 300] ZOrder -9 ShowName off GotoTag "ltsCorr_dAddr" TagVisibility "scoped" } Block { BlockType From Name "From1" SID "12983" Position [210, 340, 300, 360] ZOrder -9 ShowName off GotoTag "ltsCorr_cAddr" TagVisibility "scoped" } Block { BlockType From Name "From2" SID "12984" Position [210, 380, 300, 400] ZOrder -9 ShowName off GotoTag "ltsCorr_ld" TagVisibility "scoped" } Block { BlockType Reference Name "Gateway Out1" SID "12985" Ports [1, 1] Position [745, 615, 780, 625] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "12986" Ports [1, 1] Position [745, 630, 780, 640] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "12987" Ports [1, 1] Position [745, 645, 780, 655] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Ld" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "12988" Ports [1, 1] Position [745, 660, 780, 670] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "12989" Ports [1, 1] Position [745, 675, 780, 685] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "12990" Ports [1, 1] Position [745, 570, 780, 580] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X In" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "12991" Ports [1, 1] Position [745, 585, 780, 595] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "12992" Ports [1, 1] Position [745, 600, 780, 610] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X Vin" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType SubSystem Name "MAC" SID "12993" Ports [4, 2] Position [575, 279, 660, 376] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "MAC" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "a" SID "12994" Position [35, 143, 65, 157] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "coeff" SID "12995" Position [35, 108, 65, 122] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "ld" SID "12996" Position [35, 178, 65, 192] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "rst" SID "12997" Position [35, 233, 65, 247] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub" SID "12998" Ports [3, 1] Position [340, 113, 385, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition or Subtraction" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Signed (2's comp)" n_bits "long_cor_acc_n_bits" bin_pt "0" quantization "Truncate" overflow "Flag as error" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[2 0 0 4 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,344" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,3,1,white,blue,0,02f64c57,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('input',3,'su" "b');\ncolor('black');port_label('output',1,'\\bf{a \\pm b}','texmode','on');\nfprintf('','COMMENT: end icon text" "');\n" } Block { BlockType Reference Name "Gateway Out1" SID "12999" Ports [1, 1] Position [475, 450, 510, 460] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out2" SID "13000" Ports [1, 1] Position [475, 465, 510, 475] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out3" SID "13001" Ports [1, 1] Position [475, 480, 510, 490] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out6" SID "13002" Ports [1, 1] Position [475, 405, 510, 415] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out7" SID "13003" Ports [1, 1] Position [475, 420, 510, 430] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out8" SID "13004" Ports [1, 1] Position [475, 435, 510, 445] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "13005" Ports [2, 1] Position [345, 30, 385, 70] BlockMirror on NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,40,2,1,white,blue,0,140cc11c,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'" "q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "13006" Ports [2, 1] Position [465, 110, 495, 210] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,100,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 100 100 0 ],[0.77 0." "82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 100 100 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[54.44 " "54.44 58.44 54.44 58.44 58.44 58.44 54.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[50.44 50.44 54.44 54" ".44 50.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[46.44 46.44 50.44 50.44 46.44 ],[1 1 1 ])" ";\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[42.44 42.44 46.44 42.44 46.44 46.44 42.44 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\nco" "lor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc2" SID "13007" Ports [1, 1] Position [265, 143, 290, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc3" SID "13008" Ports [1, 1] Position [135, 178, 160, 192] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "yn" SID "13009" Position [545, 153, 575, 167] IconDisplay "Port number" } Block { BlockType Outport Name "accrm" SID "13010" Position [520, 288, 550, 302] Port "2" IconDisplay "Port number" } Line { SrcBlock "rst" SrcPort 1 Points [90, 0] Branch { Points [0, 215] DstBlock "Gateway Out1" DstPort 1 } Branch { Points [255, 0; 0, -180] DstBlock "Register1" DstPort 2 } } Line { SrcBlock "Gateway Out3" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out2" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out1" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out6" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out7" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out8" SrcPort 1 Points [50, 0] } Line { SrcBlock "a" SrcPort 1 Points [140, 0] Branch { Points [0, 275] DstBlock "Gateway Out7" DstPort 1 } Branch { DstBlock "bc2" DstPort 1 } } Line { SrcBlock "AddSub" SrcPort 1 Points [0, 0; 5, 0] Branch { Points [0, 305] DstBlock "Gateway Out8" DstPort 1 } Branch { Points [40, 0] Branch { Points [0, 160] DstBlock "accrm" DstPort 1 } Branch { Points [0, -95] DstBlock "Register1" DstPort 1 } Branch { DstBlock "Register2" DstPort 1 } } } Line { SrcBlock "Register2" SrcPort 1 Points [15, 0] Branch { Points [0, 50; 110, 0; 0, 385; -260, 0; 0, -110] DstBlock "Gateway Out3" DstPort 1 } Branch { DstBlock "yn" DstPort 1 } } Line { SrcBlock "Register1" SrcPort 1 Points [-15, 0] DstBlock "AddSub" DstPort 1 } Line { SrcBlock "ld" SrcPort 1 Points [45, 0] Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } Branch { DstBlock "bc3" DstPort 1 } } Line { SrcBlock "bc3" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "bc2" SrcPort 1 DstBlock "AddSub" DstPort 3 } Line { SrcBlock "coeff" SrcPort 1 Points [95, 0; 0, 20; 50, 0] Branch { Points [0, 275] DstBlock "Gateway Out6" DstPort 1 } Branch { DstBlock "AddSub" DstPort 2 } } } } Block { BlockType Reference Name "ROM" SID "13011" Ports [1, 1] Position [440, 328, 490, 372] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/ROM" SourceType "Xilinx Single Port Read-Only Memory Block" depth "length(coef2)" initVector "coef2" distributed_mem "Distributed memory" rst off init_reg "0" en off latency "1" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "longCorr_coef_nbits" bin_pt "longCorr_coef_bp" preci_type "Single" exp_width "8" frac_width "24" dbl_ovrd off optimize "Area" use_rpm off xl_use_area off xl_area "[1 1 0 1 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,308" block_type "sprom" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,44,1,1,white,blue,0,bbc23d60,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 44 44 0 ]);\npatch([11.65 20.32 26.32 32.32 38.32 26.32 17.65 11.65 ],[28.66" " 28.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([17.65 26.32 20.32 11.65 17.65 ],[22.66 22.66 28." "66 28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([11.65 20.32 26.32 17.65 11.65 ],[16.66 16.66 22.66 22.66 16.66 ]" ",[1 1 1 ]);\npatch([17.65 38.32 32.32 26.32 20.32 11.65 17.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'addr');\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end" " icon text');\n" } Block { BlockType Outport Name "x_dly" SID "13012" Position [790, 178, 820, 192] IconDisplay "Port number" } Block { BlockType Outport Name "x_dly_vout" SID "13013" Position [790, 223, 820, 237] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "y" SID "13014" Position [790, 293, 820, 307] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "y_vout" SID "13015" Position [785, 448, 815, 462] Port "4" IconDisplay "Port number" } Line { Name "ROM Addr" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 Points [150, 0] } Line { Name "Corr Out" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 Points [150, 0] } Line { Name "Corr Ld" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 Points [150, 0] } Line { Name "ROM Out" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 Points [150, 0] } Line { Name "ASR Out" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 Points [150, 0] } Line { Name "X In" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 Points [150, 0] } Line { Name "ASR Addr" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 Points [150, 0] } Line { Name "X Vin" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 Points [150, 0] } Line { SrcBlock "Delay" SrcPort 1 DstBlock "y_vout" DstPort 1 } Line { SrcBlock "vin" SrcPort 1 Points [25, 0] Branch { Points [0, -80] DstBlock "x_dly_vout" DstPort 1 } Branch { Points [0, 100] Branch { Points [230, 0] DstBlock "MAC" DstPort 4 } Branch { Points [0, 195] DstBlock "Gateway Out8" DstPort 1 } } Branch { DstBlock "ASR" DstPort 3 } } Line { SrcBlock "x" SrcPort 1 Points [100, 0] Branch { Points [0, 305] DstBlock "Gateway Out6" DstPort 1 } Branch { DstBlock "ASR" DstPort 1 } } Line { SrcBlock "From" SrcPort 1 Points [90, 0] Branch { Points [0, 300] DstBlock "Gateway Out7" DstPort 1 } Branch { DstBlock "ASR" DstPort 2 } } Line { SrcBlock "From1" SrcPort 1 Points [5, 0] Branch { Points [0, 330] DstBlock "Gateway Out5" DstPort 1 } Branch { DstBlock "ROM" DstPort 1 } } Line { SrcBlock "ASR" SrcPort 1 Points [35, 0] Branch { Points [0, 330] DstBlock "Gateway Out1" DstPort 1 } Branch { Points [0, -105] DstBlock "x_dly" DstPort 1 } Branch { DstBlock "MAC" DstPort 1 } } Line { SrcBlock "MAC" SrcPort 1 Points [0, -5; 15, 0] Branch { Points [0, 365] DstBlock "Gateway Out4" DstPort 1 } Branch { DstBlock "y" DstPort 1 } } Line { SrcBlock "ROM" SrcPort 1 Points [5, 0] Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } Branch { Points [0, -35] DstBlock "MAC" DstPort 2 } } Line { SrcBlock "From2" SrcPort 1 Points [145, 0] Branch { Points [0, 260] DstBlock "Gateway Out3" DstPort 1 } Branch { Points [90, 0] Branch { Points [0, 65] DstBlock "Delay" DstPort 1 } Branch { Points [0, -50] Branch { Points [0, -90; 160, 0] } Branch { DstBlock "MAC" DstPort 3 } } } } } } Block { BlockType SubSystem Name "C3" SID "13016" Ports [4, 4] Position [520, 207, 590, 293] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskPromptString "Coefficients (all)|Sub-correlator Ind|Coef/correlator" MaskStyleString "edit,edit,edit" MaskVariables "h=@1;c_ind=@2;N=@3;" MaskTunableValueString "on,on,on" MaskCallbackString "||" MaskEnableString "on,on,on" MaskVisibilityString "on,on,on" MaskToolTipString "on,on,on" MaskInitialization "coef2 = h((c_ind*N+1) : (c_ind + 1)*N);" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "h|2|N" System { Name "C3" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "122" Block { BlockType Inport Name "x" SID "13017" Position [265, 263, 295, 277] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "vin" SID "13018" Position [270, 303, 300, 317] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "13019" Position [270, 458, 300, 472] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "13020" Position [270, 503, 300, 517] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "ASR" SID "13021" Ports [3, 1] Position [445, 260, 490, 320] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Addressable Shift Register" SourceType "Xilinx Addressable Shift Register Block" infoedit "Delay of configurable length. Any element in the delay line can be addressed and driven onto the" " output port.

Hardware notes: This block is implemented using SRL16s. If Virtex-4 or Spartan-3 device is " "used, multiple SRLC16s are cascaded together." infer_latency off depth "length(coef2)" initVector "[0]" en on dbl_ovrd off use_behavioral_HDL off Optimization "Resource" xl_use_area off xl_area "[1 0 0 2 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,401" block_type "addrsr" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,60,3,1,white,blue,0,f8ea6153,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 60 60 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 60 60 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[36.66 3" "6.66 42.66 36.66 42.66 42.66 42.66 36.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[30.66 30.66 36.66 " "36.66 30.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[24.66 24.66 30.66 30.66 24.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[18.66 18.66 24.66 18.66 24.66 24.66 18.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'addr');\ncolor('black');port_label('input',3," "'en');\ncolor('black');port_label('output',1,'q');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Delay" SID "13022" Ports [1, 1] Position [705, 441, 730, 469] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "25,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 " "17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33" " 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('blac" "k');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "13023" Position [210, 280, 300, 300] ZOrder -9 ShowName off GotoTag "ltsCorr_dAddr" TagVisibility "scoped" } Block { BlockType From Name "From1" SID "13024" Position [210, 340, 300, 360] ZOrder -9 ShowName off GotoTag "ltsCorr_cAddr" TagVisibility "scoped" } Block { BlockType From Name "From2" SID "13025" Position [210, 380, 300, 400] ZOrder -9 ShowName off GotoTag "ltsCorr_ld" TagVisibility "scoped" } Block { BlockType Reference Name "Gateway Out1" SID "13026" Ports [1, 1] Position [745, 615, 780, 625] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "13027" Ports [1, 1] Position [745, 630, 780, 640] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "13028" Ports [1, 1] Position [745, 645, 780, 655] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Ld" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "13029" Ports [1, 1] Position [745, 660, 780, 670] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "13030" Ports [1, 1] Position [745, 675, 780, 685] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "13031" Ports [1, 1] Position [745, 570, 780, 580] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X In" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "13032" Ports [1, 1] Position [745, 585, 780, 595] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "13033" Ports [1, 1] Position [745, 600, 780, 610] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X Vin" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType SubSystem Name "MAC" SID "13034" Ports [4, 2] Position [575, 279, 660, 376] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "MAC" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "a" SID "13035" Position [35, 143, 65, 157] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "coeff" SID "13036" Position [35, 108, 65, 122] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "ld" SID "13037" Position [35, 178, 65, 192] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "rst" SID "13038" Position [35, 233, 65, 247] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub" SID "13039" Ports [3, 1] Position [340, 113, 385, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition or Subtraction" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Signed (2's comp)" n_bits "long_cor_acc_n_bits" bin_pt "0" quantization "Truncate" overflow "Flag as error" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[2 0 0 4 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,344" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,3,1,white,blue,0,02f64c57,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('input',3,'su" "b');\ncolor('black');port_label('output',1,'\\bf{a \\pm b}','texmode','on');\nfprintf('','COMMENT: end icon text" "');\n" } Block { BlockType Reference Name "Gateway Out1" SID "13040" Ports [1, 1] Position [475, 450, 510, 460] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out2" SID "13041" Ports [1, 1] Position [475, 465, 510, 475] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out3" SID "13042" Ports [1, 1] Position [475, 480, 510, 490] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out6" SID "13043" Ports [1, 1] Position [475, 405, 510, 415] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out7" SID "13044" Ports [1, 1] Position [475, 420, 510, 430] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out8" SID "13045" Ports [1, 1] Position [475, 435, 510, 445] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "13046" Ports [2, 1] Position [345, 30, 385, 70] BlockMirror on NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,40,2,1,white,blue,0,140cc11c,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'" "q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "13047" Ports [2, 1] Position [465, 110, 495, 210] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,100,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 100 100 0 ],[0.77 0." "82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 100 100 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[54.44 " "54.44 58.44 54.44 58.44 58.44 58.44 54.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[50.44 50.44 54.44 54" ".44 50.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[46.44 46.44 50.44 50.44 46.44 ],[1 1 1 ])" ";\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[42.44 42.44 46.44 42.44 46.44 46.44 42.44 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\nco" "lor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc2" SID "13048" Ports [1, 1] Position [265, 143, 290, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc3" SID "13049" Ports [1, 1] Position [135, 178, 160, 192] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "yn" SID "13050" Position [545, 153, 575, 167] IconDisplay "Port number" } Block { BlockType Outport Name "accrm" SID "13051" Position [520, 288, 550, 302] Port "2" IconDisplay "Port number" } Line { SrcBlock "coeff" SrcPort 1 Points [95, 0; 0, 20; 50, 0] Branch { DstBlock "AddSub" DstPort 2 } Branch { Points [0, 275] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "bc2" SrcPort 1 DstBlock "AddSub" DstPort 3 } Line { SrcBlock "bc3" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "ld" SrcPort 1 Points [45, 0] Branch { DstBlock "bc3" DstPort 1 } Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "Register1" SrcPort 1 Points [-15, 0] DstBlock "AddSub" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 Points [15, 0] Branch { DstBlock "yn" DstPort 1 } Branch { Points [0, 50; 110, 0; 0, 385; -260, 0; 0, -110] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "AddSub" SrcPort 1 Points [0, 0; 5, 0] Branch { Points [40, 0] Branch { DstBlock "Register2" DstPort 1 } Branch { Points [0, -95] DstBlock "Register1" DstPort 1 } Branch { Points [0, 160] DstBlock "accrm" DstPort 1 } } Branch { Points [0, 305] DstBlock "Gateway Out8" DstPort 1 } } Line { SrcBlock "a" SrcPort 1 Points [140, 0] Branch { DstBlock "bc2" DstPort 1 } Branch { Points [0, 275] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "Gateway Out8" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out7" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out6" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out1" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out2" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out3" SrcPort 1 Points [50, 0] } Line { SrcBlock "rst" SrcPort 1 Points [90, 0] Branch { Points [255, 0; 0, -180] DstBlock "Register1" DstPort 2 } Branch { Points [0, 215] DstBlock "Gateway Out1" DstPort 1 } } } } Block { BlockType Reference Name "ROM" SID "13052" Ports [1, 1] Position [440, 328, 490, 372] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/ROM" SourceType "Xilinx Single Port Read-Only Memory Block" depth "length(coef2)" initVector "coef2" distributed_mem "Distributed memory" rst off init_reg "0" en off latency "1" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "longCorr_coef_nbits" bin_pt "longCorr_coef_bp" preci_type "Single" exp_width "8" frac_width "24" dbl_ovrd off optimize "Area" use_rpm off xl_use_area off xl_area "[1 1 0 1 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,308" block_type "sprom" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,44,1,1,white,blue,0,bbc23d60,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 44 44 0 ]);\npatch([11.65 20.32 26.32 32.32 38.32 26.32 17.65 11.65 ],[28.66" " 28.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([17.65 26.32 20.32 11.65 17.65 ],[22.66 22.66 28." "66 28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([11.65 20.32 26.32 17.65 11.65 ],[16.66 16.66 22.66 22.66 16.66 ]" ",[1 1 1 ]);\npatch([17.65 38.32 32.32 26.32 20.32 11.65 17.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'addr');\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end" " icon text');\n" } Block { BlockType Outport Name "x_dly" SID "13053" Position [790, 178, 820, 192] IconDisplay "Port number" } Block { BlockType Outport Name "x_dly_vout" SID "13054" Position [790, 223, 820, 237] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "y" SID "13055" Position [790, 293, 820, 307] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "y_vout" SID "13056" Position [785, 448, 815, 462] Port "4" IconDisplay "Port number" } Line { SrcBlock "From2" SrcPort 1 Points [145, 0] Branch { Points [90, 0] Branch { Points [0, -50] Branch { DstBlock "MAC" DstPort 3 } Branch { Points [0, -90; 160, 0] } } Branch { Points [0, 65] DstBlock "Delay" DstPort 1 } } Branch { Points [0, 260] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "ROM" SrcPort 1 Points [5, 0] Branch { Points [0, -35] DstBlock "MAC" DstPort 2 } Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "MAC" SrcPort 1 Points [0, -5; 15, 0] Branch { DstBlock "y" DstPort 1 } Branch { Points [0, 365] DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "ASR" SrcPort 1 Points [35, 0] Branch { DstBlock "MAC" DstPort 1 } Branch { Points [0, -105] DstBlock "x_dly" DstPort 1 } Branch { Points [0, 330] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "From1" SrcPort 1 Points [5, 0] Branch { DstBlock "ROM" DstPort 1 } Branch { Points [0, 330] DstBlock "Gateway Out5" DstPort 1 } } Line { SrcBlock "From" SrcPort 1 Points [90, 0] Branch { DstBlock "ASR" DstPort 2 } Branch { Points [0, 300] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "x" SrcPort 1 Points [100, 0] Branch { DstBlock "ASR" DstPort 1 } Branch { Points [0, 305] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "vin" SrcPort 1 Points [25, 0] Branch { DstBlock "ASR" DstPort 3 } Branch { Points [0, 100] Branch { Points [0, 195] DstBlock "Gateway Out8" DstPort 1 } Branch { Points [230, 0] DstBlock "MAC" DstPort 4 } } Branch { Points [0, -80] DstBlock "x_dly_vout" DstPort 1 } } Line { SrcBlock "Delay" SrcPort 1 DstBlock "y_vout" DstPort 1 } Line { Name "X Vin" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 Points [150, 0] } Line { Name "ASR Addr" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 Points [150, 0] } Line { Name "X In" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 Points [150, 0] } Line { Name "ASR Out" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 Points [150, 0] } Line { Name "ROM Out" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 Points [150, 0] } Line { Name "Corr Ld" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 Points [150, 0] } Line { Name "Corr Out" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 Points [150, 0] } Line { Name "ROM Addr" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 Points [150, 0] } } } Block { BlockType SubSystem Name "C4" SID "13057" Ports [4, 4] Position [630, 207, 700, 293] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskPromptString "Coefficients (all)|Sub-correlator Ind|Coef/correlator" MaskStyleString "edit,edit,edit" MaskVariables "h=@1;c_ind=@2;N=@3;" MaskTunableValueString "on,on,on" MaskCallbackString "||" MaskEnableString "on,on,on" MaskVisibilityString "on,on,on" MaskToolTipString "on,on,on" MaskInitialization "coef2 = h((c_ind*N+1) : (c_ind + 1)*N);" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "h|3|N" System { Name "C4" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "122" Block { BlockType Inport Name "x" SID "13058" Position [265, 263, 295, 277] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "vin" SID "13059" Position [270, 303, 300, 317] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "13060" Position [270, 458, 300, 472] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "13061" Position [270, 503, 300, 517] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "ASR" SID "13062" Ports [3, 1] Position [445, 260, 490, 320] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Addressable Shift Register" SourceType "Xilinx Addressable Shift Register Block" infoedit "Delay of configurable length. Any element in the delay line can be addressed and driven onto the" " output port.

Hardware notes: This block is implemented using SRL16s. If Virtex-4 or Spartan-3 device is " "used, multiple SRLC16s are cascaded together." infer_latency off depth "length(coef2)" initVector "[0]" en on dbl_ovrd off use_behavioral_HDL off Optimization "Resource" xl_use_area off xl_area "[1 0 0 2 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,401" block_type "addrsr" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,60,3,1,white,blue,0,f8ea6153,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 60 60 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 60 60 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[36.66 3" "6.66 42.66 36.66 42.66 42.66 42.66 36.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[30.66 30.66 36.66 " "36.66 30.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[24.66 24.66 30.66 30.66 24.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[18.66 18.66 24.66 18.66 24.66 24.66 18.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'addr');\ncolor('black');port_label('input',3," "'en');\ncolor('black');port_label('output',1,'q');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Delay" SID "13063" Ports [1, 1] Position [705, 441, 730, 469] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "25,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 " "17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33" " 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('blac" "k');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "13064" Position [210, 280, 300, 300] ZOrder -9 ShowName off GotoTag "ltsCorr_dAddr" TagVisibility "scoped" } Block { BlockType From Name "From1" SID "13065" Position [210, 340, 300, 360] ZOrder -9 ShowName off GotoTag "ltsCorr_cAddr" TagVisibility "scoped" } Block { BlockType From Name "From2" SID "13066" Position [210, 380, 300, 400] ZOrder -9 ShowName off GotoTag "ltsCorr_ld" TagVisibility "scoped" } Block { BlockType Reference Name "Gateway Out1" SID "13067" Ports [1, 1] Position [745, 615, 780, 625] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "13068" Ports [1, 1] Position [745, 630, 780, 640] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "13069" Ports [1, 1] Position [745, 645, 780, 655] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Ld" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "13070" Ports [1, 1] Position [745, 660, 780, 670] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "13071" Ports [1, 1] Position [745, 675, 780, 685] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "13072" Ports [1, 1] Position [745, 570, 780, 580] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X In" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "13073" Ports [1, 1] Position [745, 585, 780, 595] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "13074" Ports [1, 1] Position [745, 600, 780, 610] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X Vin" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType SubSystem Name "MAC" SID "13075" Ports [4, 2] Position [575, 279, 660, 376] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "MAC" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "a" SID "13076" Position [35, 143, 65, 157] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "coeff" SID "13077" Position [35, 108, 65, 122] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "ld" SID "13078" Position [35, 178, 65, 192] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "rst" SID "13079" Position [35, 233, 65, 247] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub" SID "13080" Ports [3, 1] Position [340, 113, 385, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition or Subtraction" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Signed (2's comp)" n_bits "long_cor_acc_n_bits" bin_pt "0" quantization "Truncate" overflow "Flag as error" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[2 0 0 4 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,344" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,3,1,white,blue,0,02f64c57,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('input',3,'su" "b');\ncolor('black');port_label('output',1,'\\bf{a \\pm b}','texmode','on');\nfprintf('','COMMENT: end icon text" "');\n" } Block { BlockType Reference Name "Gateway Out1" SID "13081" Ports [1, 1] Position [475, 450, 510, 460] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out2" SID "13082" Ports [1, 1] Position [475, 465, 510, 475] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out3" SID "13083" Ports [1, 1] Position [475, 480, 510, 490] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out6" SID "13084" Ports [1, 1] Position [475, 405, 510, 415] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out7" SID "13085" Ports [1, 1] Position [475, 420, 510, 430] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out8" SID "13086" Ports [1, 1] Position [475, 435, 510, 445] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "13087" Ports [2, 1] Position [345, 30, 385, 70] BlockMirror on NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,40,2,1,white,blue,0,140cc11c,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'" "q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "13088" Ports [2, 1] Position [465, 110, 495, 210] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,100,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 100 100 0 ],[0.77 0." "82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 100 100 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[54.44 " "54.44 58.44 54.44 58.44 58.44 58.44 54.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[50.44 50.44 54.44 54" ".44 50.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[46.44 46.44 50.44 50.44 46.44 ],[1 1 1 ])" ";\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[42.44 42.44 46.44 42.44 46.44 46.44 42.44 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\nco" "lor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc2" SID "13089" Ports [1, 1] Position [265, 143, 290, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc3" SID "13090" Ports [1, 1] Position [135, 178, 160, 192] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "yn" SID "13091" Position [545, 153, 575, 167] IconDisplay "Port number" } Block { BlockType Outport Name "accrm" SID "13092" Position [520, 288, 550, 302] Port "2" IconDisplay "Port number" } Line { SrcBlock "rst" SrcPort 1 Points [90, 0] Branch { Points [0, 215] DstBlock "Gateway Out1" DstPort 1 } Branch { Points [255, 0; 0, -180] DstBlock "Register1" DstPort 2 } } Line { SrcBlock "Gateway Out3" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out2" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out1" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out6" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out7" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out8" SrcPort 1 Points [50, 0] } Line { SrcBlock "a" SrcPort 1 Points [140, 0] Branch { Points [0, 275] DstBlock "Gateway Out7" DstPort 1 } Branch { DstBlock "bc2" DstPort 1 } } Line { SrcBlock "AddSub" SrcPort 1 Points [0, 0; 5, 0] Branch { Points [0, 305] DstBlock "Gateway Out8" DstPort 1 } Branch { Points [40, 0] Branch { Points [0, 160] DstBlock "accrm" DstPort 1 } Branch { Points [0, -95] DstBlock "Register1" DstPort 1 } Branch { DstBlock "Register2" DstPort 1 } } } Line { SrcBlock "Register2" SrcPort 1 Points [15, 0] Branch { Points [0, 50; 110, 0; 0, 385; -260, 0; 0, -110] DstBlock "Gateway Out3" DstPort 1 } Branch { DstBlock "yn" DstPort 1 } } Line { SrcBlock "Register1" SrcPort 1 Points [-15, 0] DstBlock "AddSub" DstPort 1 } Line { SrcBlock "ld" SrcPort 1 Points [45, 0] Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } Branch { DstBlock "bc3" DstPort 1 } } Line { SrcBlock "bc3" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "bc2" SrcPort 1 DstBlock "AddSub" DstPort 3 } Line { SrcBlock "coeff" SrcPort 1 Points [95, 0; 0, 20; 50, 0] Branch { Points [0, 275] DstBlock "Gateway Out6" DstPort 1 } Branch { DstBlock "AddSub" DstPort 2 } } } } Block { BlockType Reference Name "ROM" SID "13093" Ports [1, 1] Position [440, 328, 490, 372] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/ROM" SourceType "Xilinx Single Port Read-Only Memory Block" depth "length(coef2)" initVector "coef2" distributed_mem "Distributed memory" rst off init_reg "0" en off latency "1" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "longCorr_coef_nbits" bin_pt "longCorr_coef_bp" preci_type "Single" exp_width "8" frac_width "24" dbl_ovrd off optimize "Area" use_rpm off xl_use_area off xl_area "[1 1 0 1 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,308" block_type "sprom" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,44,1,1,white,blue,0,bbc23d60,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 44 44 0 ]);\npatch([11.65 20.32 26.32 32.32 38.32 26.32 17.65 11.65 ],[28.66" " 28.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([17.65 26.32 20.32 11.65 17.65 ],[22.66 22.66 28." "66 28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([11.65 20.32 26.32 17.65 11.65 ],[16.66 16.66 22.66 22.66 16.66 ]" ",[1 1 1 ]);\npatch([17.65 38.32 32.32 26.32 20.32 11.65 17.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'addr');\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end" " icon text');\n" } Block { BlockType Outport Name "x_dly" SID "13094" Position [790, 178, 820, 192] IconDisplay "Port number" } Block { BlockType Outport Name "x_dly_vout" SID "13095" Position [790, 223, 820, 237] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "y" SID "13096" Position [790, 293, 820, 307] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "y_vout" SID "13097" Position [785, 448, 815, 462] Port "4" IconDisplay "Port number" } Line { Name "ROM Addr" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 Points [150, 0] } Line { Name "Corr Out" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 Points [150, 0] } Line { Name "Corr Ld" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 Points [150, 0] } Line { Name "ROM Out" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 Points [150, 0] } Line { Name "ASR Out" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 Points [150, 0] } Line { Name "X In" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 Points [150, 0] } Line { Name "ASR Addr" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 Points [150, 0] } Line { Name "X Vin" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 Points [150, 0] } Line { SrcBlock "Delay" SrcPort 1 DstBlock "y_vout" DstPort 1 } Line { SrcBlock "vin" SrcPort 1 Points [25, 0] Branch { Points [0, -80] DstBlock "x_dly_vout" DstPort 1 } Branch { Points [0, 100] Branch { Points [230, 0] DstBlock "MAC" DstPort 4 } Branch { Points [0, 195] DstBlock "Gateway Out8" DstPort 1 } } Branch { DstBlock "ASR" DstPort 3 } } Line { SrcBlock "x" SrcPort 1 Points [100, 0] Branch { Points [0, 305] DstBlock "Gateway Out6" DstPort 1 } Branch { DstBlock "ASR" DstPort 1 } } Line { SrcBlock "From" SrcPort 1 Points [90, 0] Branch { Points [0, 300] DstBlock "Gateway Out7" DstPort 1 } Branch { DstBlock "ASR" DstPort 2 } } Line { SrcBlock "From1" SrcPort 1 Points [5, 0] Branch { Points [0, 330] DstBlock "Gateway Out5" DstPort 1 } Branch { DstBlock "ROM" DstPort 1 } } Line { SrcBlock "ASR" SrcPort 1 Points [35, 0] Branch { Points [0, 330] DstBlock "Gateway Out1" DstPort 1 } Branch { Points [0, -105] DstBlock "x_dly" DstPort 1 } Branch { DstBlock "MAC" DstPort 1 } } Line { SrcBlock "MAC" SrcPort 1 Points [0, -5; 15, 0] Branch { Points [0, 365] DstBlock "Gateway Out4" DstPort 1 } Branch { DstBlock "y" DstPort 1 } } Line { SrcBlock "ROM" SrcPort 1 Points [5, 0] Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } Branch { Points [0, -35] DstBlock "MAC" DstPort 2 } } Line { SrcBlock "From2" SrcPort 1 Points [145, 0] Branch { Points [0, 260] DstBlock "Gateway Out3" DstPort 1 } Branch { Points [90, 0] Branch { Points [0, 65] DstBlock "Delay" DstPort 1 } Branch { Points [0, -50] Branch { Points [0, -90; 160, 0] } Branch { DstBlock "MAC" DstPort 3 } } } } } } Block { BlockType SubSystem Name "C5" SID "13098" Ports [4, 4] Position [740, 207, 810, 293] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskPromptString "Coefficients (all)|Sub-correlator Ind|Coef/correlator" MaskStyleString "edit,edit,edit" MaskVariables "h=@1;c_ind=@2;N=@3;" MaskTunableValueString "on,on,on" MaskCallbackString "||" MaskEnableString "on,on,on" MaskVisibilityString "on,on,on" MaskToolTipString "on,on,on" MaskInitialization "coef2 = h((c_ind*N+1) : (c_ind + 1)*N);" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "h|4|N" System { Name "C5" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "122" Block { BlockType Inport Name "x" SID "13099" Position [265, 263, 295, 277] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "vin" SID "13100" Position [270, 303, 300, 317] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "13101" Position [270, 458, 300, 472] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "13102" Position [270, 503, 300, 517] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "ASR" SID "13103" Ports [3, 1] Position [445, 260, 490, 320] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Addressable Shift Register" SourceType "Xilinx Addressable Shift Register Block" infoedit "Delay of configurable length. Any element in the delay line can be addressed and driven onto the" " output port.

Hardware notes: This block is implemented using SRL16s. If Virtex-4 or Spartan-3 device is " "used, multiple SRLC16s are cascaded together." infer_latency off depth "length(coef2)" initVector "[0]" en on dbl_ovrd off use_behavioral_HDL off Optimization "Resource" xl_use_area off xl_area "[1 0 0 2 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,401" block_type "addrsr" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,60,3,1,white,blue,0,f8ea6153,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 60 60 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 60 60 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[36.66 3" "6.66 42.66 36.66 42.66 42.66 42.66 36.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[30.66 30.66 36.66 " "36.66 30.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[24.66 24.66 30.66 30.66 24.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[18.66 18.66 24.66 18.66 24.66 24.66 18.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'addr');\ncolor('black');port_label('input',3," "'en');\ncolor('black');port_label('output',1,'q');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Delay" SID "13104" Ports [1, 1] Position [705, 441, 730, 469] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "25,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 " "17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33" " 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('blac" "k');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "13105" Position [210, 280, 300, 300] ZOrder -9 ShowName off GotoTag "ltsCorr_dAddr" TagVisibility "scoped" } Block { BlockType From Name "From1" SID "13106" Position [210, 340, 300, 360] ZOrder -9 ShowName off GotoTag "ltsCorr_cAddr" TagVisibility "scoped" } Block { BlockType From Name "From2" SID "13107" Position [210, 380, 300, 400] ZOrder -9 ShowName off GotoTag "ltsCorr_ld" TagVisibility "scoped" } Block { BlockType Reference Name "Gateway Out1" SID "13108" Ports [1, 1] Position [745, 615, 780, 625] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "13109" Ports [1, 1] Position [745, 630, 780, 640] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "13110" Ports [1, 1] Position [745, 645, 780, 655] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Ld" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "13111" Ports [1, 1] Position [745, 660, 780, 670] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "13112" Ports [1, 1] Position [745, 675, 780, 685] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "13113" Ports [1, 1] Position [745, 570, 780, 580] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X In" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "13114" Ports [1, 1] Position [745, 585, 780, 595] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "13115" Ports [1, 1] Position [745, 600, 780, 610] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X Vin" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType SubSystem Name "MAC" SID "13116" Ports [4, 2] Position [575, 279, 660, 376] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "MAC" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "a" SID "13117" Position [35, 143, 65, 157] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "coeff" SID "13118" Position [35, 108, 65, 122] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "ld" SID "13119" Position [35, 178, 65, 192] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "rst" SID "13120" Position [35, 233, 65, 247] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub" SID "13121" Ports [3, 1] Position [340, 113, 385, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition or Subtraction" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Signed (2's comp)" n_bits "long_cor_acc_n_bits" bin_pt "0" quantization "Truncate" overflow "Flag as error" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[2 0 0 4 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,344" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,3,1,white,blue,0,02f64c57,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('input',3,'su" "b');\ncolor('black');port_label('output',1,'\\bf{a \\pm b}','texmode','on');\nfprintf('','COMMENT: end icon text" "');\n" } Block { BlockType Reference Name "Gateway Out1" SID "13122" Ports [1, 1] Position [475, 450, 510, 460] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out2" SID "13123" Ports [1, 1] Position [475, 465, 510, 475] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out3" SID "13124" Ports [1, 1] Position [475, 480, 510, 490] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out6" SID "13125" Ports [1, 1] Position [475, 405, 510, 415] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out7" SID "13126" Ports [1, 1] Position [475, 420, 510, 430] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out8" SID "13127" Ports [1, 1] Position [475, 435, 510, 445] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "13128" Ports [2, 1] Position [345, 30, 385, 70] BlockMirror on NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,40,2,1,white,blue,0,140cc11c,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'" "q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "13129" Ports [2, 1] Position [465, 110, 495, 210] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,100,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 100 100 0 ],[0.77 0." "82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 100 100 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[54.44 " "54.44 58.44 54.44 58.44 58.44 58.44 54.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[50.44 50.44 54.44 54" ".44 50.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[46.44 46.44 50.44 50.44 46.44 ],[1 1 1 ])" ";\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[42.44 42.44 46.44 42.44 46.44 46.44 42.44 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\nco" "lor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc2" SID "13130" Ports [1, 1] Position [265, 143, 290, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc3" SID "13131" Ports [1, 1] Position [135, 178, 160, 192] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "yn" SID "13132" Position [545, 153, 575, 167] IconDisplay "Port number" } Block { BlockType Outport Name "accrm" SID "13133" Position [520, 288, 550, 302] Port "2" IconDisplay "Port number" } Line { SrcBlock "coeff" SrcPort 1 Points [95, 0; 0, 20; 50, 0] Branch { DstBlock "AddSub" DstPort 2 } Branch { Points [0, 275] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "bc2" SrcPort 1 DstBlock "AddSub" DstPort 3 } Line { SrcBlock "bc3" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "ld" SrcPort 1 Points [45, 0] Branch { DstBlock "bc3" DstPort 1 } Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "Register1" SrcPort 1 Points [-15, 0] DstBlock "AddSub" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 Points [15, 0] Branch { DstBlock "yn" DstPort 1 } Branch { Points [0, 50; 110, 0; 0, 385; -260, 0; 0, -110] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "AddSub" SrcPort 1 Points [0, 0; 5, 0] Branch { Points [40, 0] Branch { DstBlock "Register2" DstPort 1 } Branch { Points [0, -95] DstBlock "Register1" DstPort 1 } Branch { Points [0, 160] DstBlock "accrm" DstPort 1 } } Branch { Points [0, 305] DstBlock "Gateway Out8" DstPort 1 } } Line { SrcBlock "a" SrcPort 1 Points [140, 0] Branch { DstBlock "bc2" DstPort 1 } Branch { Points [0, 275] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "Gateway Out8" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out7" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out6" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out1" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out2" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out3" SrcPort 1 Points [50, 0] } Line { SrcBlock "rst" SrcPort 1 Points [90, 0] Branch { Points [255, 0; 0, -180] DstBlock "Register1" DstPort 2 } Branch { Points [0, 215] DstBlock "Gateway Out1" DstPort 1 } } } } Block { BlockType Reference Name "ROM" SID "13134" Ports [1, 1] Position [440, 328, 490, 372] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/ROM" SourceType "Xilinx Single Port Read-Only Memory Block" depth "length(coef2)" initVector "coef2" distributed_mem "Distributed memory" rst off init_reg "0" en off latency "1" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "longCorr_coef_nbits" bin_pt "longCorr_coef_bp" preci_type "Single" exp_width "8" frac_width "24" dbl_ovrd off optimize "Area" use_rpm off xl_use_area off xl_area "[1 1 0 1 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,308" block_type "sprom" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,44,1,1,white,blue,0,bbc23d60,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 44 44 0 ]);\npatch([11.65 20.32 26.32 32.32 38.32 26.32 17.65 11.65 ],[28.66" " 28.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([17.65 26.32 20.32 11.65 17.65 ],[22.66 22.66 28." "66 28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([11.65 20.32 26.32 17.65 11.65 ],[16.66 16.66 22.66 22.66 16.66 ]" ",[1 1 1 ]);\npatch([17.65 38.32 32.32 26.32 20.32 11.65 17.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'addr');\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end" " icon text');\n" } Block { BlockType Outport Name "x_dly" SID "13135" Position [790, 178, 820, 192] IconDisplay "Port number" } Block { BlockType Outport Name "x_dly_vout" SID "13136" Position [790, 223, 820, 237] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "y" SID "13137" Position [790, 293, 820, 307] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "y_vout" SID "13138" Position [785, 448, 815, 462] Port "4" IconDisplay "Port number" } Line { SrcBlock "From2" SrcPort 1 Points [145, 0] Branch { Points [90, 0] Branch { Points [0, -50] Branch { DstBlock "MAC" DstPort 3 } Branch { Points [0, -90; 160, 0] } } Branch { Points [0, 65] DstBlock "Delay" DstPort 1 } } Branch { Points [0, 260] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "ROM" SrcPort 1 Points [5, 0] Branch { Points [0, -35] DstBlock "MAC" DstPort 2 } Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "MAC" SrcPort 1 Points [0, -5; 15, 0] Branch { DstBlock "y" DstPort 1 } Branch { Points [0, 365] DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "ASR" SrcPort 1 Points [35, 0] Branch { DstBlock "MAC" DstPort 1 } Branch { Points [0, -105] DstBlock "x_dly" DstPort 1 } Branch { Points [0, 330] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "From1" SrcPort 1 Points [5, 0] Branch { DstBlock "ROM" DstPort 1 } Branch { Points [0, 330] DstBlock "Gateway Out5" DstPort 1 } } Line { SrcBlock "From" SrcPort 1 Points [90, 0] Branch { DstBlock "ASR" DstPort 2 } Branch { Points [0, 300] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "x" SrcPort 1 Points [100, 0] Branch { DstBlock "ASR" DstPort 1 } Branch { Points [0, 305] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "vin" SrcPort 1 Points [25, 0] Branch { DstBlock "ASR" DstPort 3 } Branch { Points [0, 100] Branch { Points [0, 195] DstBlock "Gateway Out8" DstPort 1 } Branch { Points [230, 0] DstBlock "MAC" DstPort 4 } } Branch { Points [0, -80] DstBlock "x_dly_vout" DstPort 1 } } Line { SrcBlock "Delay" SrcPort 1 DstBlock "y_vout" DstPort 1 } Line { Name "X Vin" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 Points [150, 0] } Line { Name "ASR Addr" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 Points [150, 0] } Line { Name "X In" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 Points [150, 0] } Line { Name "ASR Out" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 Points [150, 0] } Line { Name "ROM Out" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 Points [150, 0] } Line { Name "Corr Ld" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 Points [150, 0] } Line { Name "Corr Out" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 Points [150, 0] } Line { Name "ROM Addr" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 Points [150, 0] } } } Block { BlockType SubSystem Name "C6" SID "13139" Ports [4, 4] Position [845, 207, 915, 293] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskPromptString "Coefficients (all)|Sub-correlator Ind|Coef/correlator" MaskStyleString "edit,edit,edit" MaskVariables "h=@1;c_ind=@2;N=@3;" MaskTunableValueString "on,on,on" MaskCallbackString "||" MaskEnableString "on,on,on" MaskVisibilityString "on,on,on" MaskToolTipString "on,on,on" MaskInitialization "coef2 = h((c_ind*N+1) : (c_ind + 1)*N);" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "h|5|N" System { Name "C6" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "122" Block { BlockType Inport Name "x" SID "13140" Position [265, 263, 295, 277] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "vin" SID "13141" Position [270, 303, 300, 317] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "13142" Position [270, 458, 300, 472] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "13143" Position [270, 503, 300, 517] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "ASR" SID "13144" Ports [3, 1] Position [445, 260, 490, 320] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Addressable Shift Register" SourceType "Xilinx Addressable Shift Register Block" infoedit "Delay of configurable length. Any element in the delay line can be addressed and driven onto the" " output port.

Hardware notes: This block is implemented using SRL16s. If Virtex-4 or Spartan-3 device is " "used, multiple SRLC16s are cascaded together." infer_latency off depth "length(coef2)" initVector "[0]" en on dbl_ovrd off use_behavioral_HDL off Optimization "Resource" xl_use_area off xl_area "[1 0 0 2 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,401" block_type "addrsr" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,60,3,1,white,blue,0,f8ea6153,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 60 60 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 60 60 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[36.66 3" "6.66 42.66 36.66 42.66 42.66 42.66 36.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[30.66 30.66 36.66 " "36.66 30.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[24.66 24.66 30.66 30.66 24.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[18.66 18.66 24.66 18.66 24.66 24.66 18.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'addr');\ncolor('black');port_label('input',3," "'en');\ncolor('black');port_label('output',1,'q');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Delay" SID "13145" Ports [1, 1] Position [705, 441, 730, 469] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "25,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 " "17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33" " 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('blac" "k');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "13146" Position [210, 280, 300, 300] ZOrder -9 ShowName off GotoTag "ltsCorr_dAddr" TagVisibility "scoped" } Block { BlockType From Name "From1" SID "13147" Position [210, 340, 300, 360] ZOrder -9 ShowName off GotoTag "ltsCorr_cAddr" TagVisibility "scoped" } Block { BlockType From Name "From2" SID "13148" Position [210, 380, 300, 400] ZOrder -9 ShowName off GotoTag "ltsCorr_ld" TagVisibility "scoped" } Block { BlockType Reference Name "Gateway Out1" SID "13149" Ports [1, 1] Position [745, 615, 780, 625] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "13150" Ports [1, 1] Position [745, 630, 780, 640] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "13151" Ports [1, 1] Position [745, 645, 780, 655] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Ld" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "13152" Ports [1, 1] Position [745, 660, 780, 670] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "13153" Ports [1, 1] Position [745, 675, 780, 685] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "13154" Ports [1, 1] Position [745, 570, 780, 580] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X In" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "13155" Ports [1, 1] Position [745, 585, 780, 595] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "13156" Ports [1, 1] Position [745, 600, 780, 610] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X Vin" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType SubSystem Name "MAC" SID "13157" Ports [4, 2] Position [575, 279, 660, 376] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "MAC" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "a" SID "13158" Position [35, 143, 65, 157] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "coeff" SID "13159" Position [35, 108, 65, 122] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "ld" SID "13160" Position [35, 178, 65, 192] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "rst" SID "13161" Position [35, 233, 65, 247] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub" SID "13162" Ports [3, 1] Position [340, 113, 385, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition or Subtraction" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Signed (2's comp)" n_bits "long_cor_acc_n_bits" bin_pt "0" quantization "Truncate" overflow "Flag as error" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[2 0 0 4 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,344" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,3,1,white,blue,0,02f64c57,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('input',3,'su" "b');\ncolor('black');port_label('output',1,'\\bf{a \\pm b}','texmode','on');\nfprintf('','COMMENT: end icon text" "');\n" } Block { BlockType Reference Name "Gateway Out1" SID "13163" Ports [1, 1] Position [475, 450, 510, 460] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out2" SID "13164" Ports [1, 1] Position [475, 465, 510, 475] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out3" SID "13165" Ports [1, 1] Position [475, 480, 510, 490] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out6" SID "13166" Ports [1, 1] Position [475, 405, 510, 415] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out7" SID "13167" Ports [1, 1] Position [475, 420, 510, 430] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out8" SID "13168" Ports [1, 1] Position [475, 435, 510, 445] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "13169" Ports [2, 1] Position [345, 30, 385, 70] BlockMirror on NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,40,2,1,white,blue,0,140cc11c,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'" "q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "13170" Ports [2, 1] Position [465, 110, 495, 210] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,100,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 100 100 0 ],[0.77 0." "82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 100 100 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[54.44 " "54.44 58.44 54.44 58.44 58.44 58.44 54.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[50.44 50.44 54.44 54" ".44 50.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[46.44 46.44 50.44 50.44 46.44 ],[1 1 1 ])" ";\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[42.44 42.44 46.44 42.44 46.44 46.44 42.44 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\nco" "lor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc2" SID "13171" Ports [1, 1] Position [265, 143, 290, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc3" SID "13172" Ports [1, 1] Position [135, 178, 160, 192] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "yn" SID "13173" Position [545, 153, 575, 167] IconDisplay "Port number" } Block { BlockType Outport Name "accrm" SID "13174" Position [520, 288, 550, 302] Port "2" IconDisplay "Port number" } Line { SrcBlock "rst" SrcPort 1 Points [90, 0] Branch { Points [0, 215] DstBlock "Gateway Out1" DstPort 1 } Branch { Points [255, 0; 0, -180] DstBlock "Register1" DstPort 2 } } Line { SrcBlock "Gateway Out3" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out2" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out1" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out6" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out7" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out8" SrcPort 1 Points [50, 0] } Line { SrcBlock "a" SrcPort 1 Points [140, 0] Branch { Points [0, 275] DstBlock "Gateway Out7" DstPort 1 } Branch { DstBlock "bc2" DstPort 1 } } Line { SrcBlock "AddSub" SrcPort 1 Points [0, 0; 5, 0] Branch { Points [0, 305] DstBlock "Gateway Out8" DstPort 1 } Branch { Points [40, 0] Branch { Points [0, 160] DstBlock "accrm" DstPort 1 } Branch { Points [0, -95] DstBlock "Register1" DstPort 1 } Branch { DstBlock "Register2" DstPort 1 } } } Line { SrcBlock "Register2" SrcPort 1 Points [15, 0] Branch { Points [0, 50; 110, 0; 0, 385; -260, 0; 0, -110] DstBlock "Gateway Out3" DstPort 1 } Branch { DstBlock "yn" DstPort 1 } } Line { SrcBlock "Register1" SrcPort 1 Points [-15, 0] DstBlock "AddSub" DstPort 1 } Line { SrcBlock "ld" SrcPort 1 Points [45, 0] Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } Branch { DstBlock "bc3" DstPort 1 } } Line { SrcBlock "bc3" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "bc2" SrcPort 1 DstBlock "AddSub" DstPort 3 } Line { SrcBlock "coeff" SrcPort 1 Points [95, 0; 0, 20; 50, 0] Branch { Points [0, 275] DstBlock "Gateway Out6" DstPort 1 } Branch { DstBlock "AddSub" DstPort 2 } } } } Block { BlockType Reference Name "ROM" SID "13175" Ports [1, 1] Position [440, 328, 490, 372] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/ROM" SourceType "Xilinx Single Port Read-Only Memory Block" depth "length(coef2)" initVector "coef2" distributed_mem "Distributed memory" rst off init_reg "0" en off latency "1" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "longCorr_coef_nbits" bin_pt "longCorr_coef_bp" preci_type "Single" exp_width "8" frac_width "24" dbl_ovrd off optimize "Area" use_rpm off xl_use_area off xl_area "[1 1 0 1 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,308" block_type "sprom" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,44,1,1,white,blue,0,bbc23d60,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 44 44 0 ]);\npatch([11.65 20.32 26.32 32.32 38.32 26.32 17.65 11.65 ],[28.66" " 28.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([17.65 26.32 20.32 11.65 17.65 ],[22.66 22.66 28." "66 28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([11.65 20.32 26.32 17.65 11.65 ],[16.66 16.66 22.66 22.66 16.66 ]" ",[1 1 1 ]);\npatch([17.65 38.32 32.32 26.32 20.32 11.65 17.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'addr');\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end" " icon text');\n" } Block { BlockType Outport Name "x_dly" SID "13176" Position [790, 178, 820, 192] IconDisplay "Port number" } Block { BlockType Outport Name "x_dly_vout" SID "13177" Position [790, 223, 820, 237] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "y" SID "13178" Position [790, 293, 820, 307] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "y_vout" SID "13179" Position [785, 448, 815, 462] Port "4" IconDisplay "Port number" } Line { Name "ROM Addr" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 Points [150, 0] } Line { Name "Corr Out" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 Points [150, 0] } Line { Name "Corr Ld" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 Points [150, 0] } Line { Name "ROM Out" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 Points [150, 0] } Line { Name "ASR Out" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 Points [150, 0] } Line { Name "X In" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 Points [150, 0] } Line { Name "ASR Addr" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 Points [150, 0] } Line { Name "X Vin" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 Points [150, 0] } Line { SrcBlock "Delay" SrcPort 1 DstBlock "y_vout" DstPort 1 } Line { SrcBlock "vin" SrcPort 1 Points [25, 0] Branch { Points [0, -80] DstBlock "x_dly_vout" DstPort 1 } Branch { Points [0, 100] Branch { Points [230, 0] DstBlock "MAC" DstPort 4 } Branch { Points [0, 195] DstBlock "Gateway Out8" DstPort 1 } } Branch { DstBlock "ASR" DstPort 3 } } Line { SrcBlock "x" SrcPort 1 Points [100, 0] Branch { Points [0, 305] DstBlock "Gateway Out6" DstPort 1 } Branch { DstBlock "ASR" DstPort 1 } } Line { SrcBlock "From" SrcPort 1 Points [90, 0] Branch { Points [0, 300] DstBlock "Gateway Out7" DstPort 1 } Branch { DstBlock "ASR" DstPort 2 } } Line { SrcBlock "From1" SrcPort 1 Points [5, 0] Branch { Points [0, 330] DstBlock "Gateway Out5" DstPort 1 } Branch { DstBlock "ROM" DstPort 1 } } Line { SrcBlock "ASR" SrcPort 1 Points [35, 0] Branch { Points [0, 330] DstBlock "Gateway Out1" DstPort 1 } Branch { Points [0, -105] DstBlock "x_dly" DstPort 1 } Branch { DstBlock "MAC" DstPort 1 } } Line { SrcBlock "MAC" SrcPort 1 Points [0, -5; 15, 0] Branch { Points [0, 365] DstBlock "Gateway Out4" DstPort 1 } Branch { DstBlock "y" DstPort 1 } } Line { SrcBlock "ROM" SrcPort 1 Points [5, 0] Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } Branch { Points [0, -35] DstBlock "MAC" DstPort 2 } } Line { SrcBlock "From2" SrcPort 1 Points [145, 0] Branch { Points [0, 260] DstBlock "Gateway Out3" DstPort 1 } Branch { Points [90, 0] Branch { Points [0, 65] DstBlock "Delay" DstPort 1 } Branch { Points [0, -50] Branch { Points [0, -90; 160, 0] } Branch { DstBlock "MAC" DstPort 3 } } } } } } Block { BlockType SubSystem Name "C7" SID "13180" Ports [4, 4] Position [950, 207, 1020, 293] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskPromptString "Coefficients (all)|Sub-correlator Ind|Coef/correlator" MaskStyleString "edit,edit,edit" MaskVariables "h=@1;c_ind=@2;N=@3;" MaskTunableValueString "on,on,on" MaskCallbackString "||" MaskEnableString "on,on,on" MaskVisibilityString "on,on,on" MaskToolTipString "on,on,on" MaskInitialization "coef2 = h((c_ind*N+1) : (c_ind + 1)*N);" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "h|6|N" System { Name "C7" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "122" Block { BlockType Inport Name "x" SID "13181" Position [265, 263, 295, 277] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "vin" SID "13182" Position [270, 303, 300, 317] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "13183" Position [270, 458, 300, 472] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "13184" Position [270, 503, 300, 517] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "ASR" SID "13185" Ports [3, 1] Position [445, 260, 490, 320] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Addressable Shift Register" SourceType "Xilinx Addressable Shift Register Block" infoedit "Delay of configurable length. Any element in the delay line can be addressed and driven onto the" " output port.

Hardware notes: This block is implemented using SRL16s. If Virtex-4 or Spartan-3 device is " "used, multiple SRLC16s are cascaded together." infer_latency off depth "length(coef2)" initVector "[0]" en on dbl_ovrd off use_behavioral_HDL off Optimization "Resource" xl_use_area off xl_area "[1 0 0 2 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,401" block_type "addrsr" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,60,3,1,white,blue,0,f8ea6153,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 60 60 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 60 60 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[36.66 3" "6.66 42.66 36.66 42.66 42.66 42.66 36.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[30.66 30.66 36.66 " "36.66 30.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[24.66 24.66 30.66 30.66 24.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[18.66 18.66 24.66 18.66 24.66 24.66 18.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'addr');\ncolor('black');port_label('input',3," "'en');\ncolor('black');port_label('output',1,'q');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Delay" SID "13186" Ports [1, 1] Position [705, 441, 730, 469] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "25,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 " "17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33" " 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('blac" "k');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "13187" Position [210, 280, 300, 300] ZOrder -9 ShowName off GotoTag "ltsCorr_dAddr" TagVisibility "scoped" } Block { BlockType From Name "From1" SID "13188" Position [210, 340, 300, 360] ZOrder -9 ShowName off GotoTag "ltsCorr_cAddr" TagVisibility "scoped" } Block { BlockType From Name "From2" SID "13189" Position [210, 380, 300, 400] ZOrder -9 ShowName off GotoTag "ltsCorr_ld" TagVisibility "scoped" } Block { BlockType Reference Name "Gateway Out1" SID "13190" Ports [1, 1] Position [745, 615, 780, 625] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "13191" Ports [1, 1] Position [745, 630, 780, 640] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "13192" Ports [1, 1] Position [745, 645, 780, 655] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Ld" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "13193" Ports [1, 1] Position [745, 660, 780, 670] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "13194" Ports [1, 1] Position [745, 675, 780, 685] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "13195" Ports [1, 1] Position [745, 570, 780, 580] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X In" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "13196" Ports [1, 1] Position [745, 585, 780, 595] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "13197" Ports [1, 1] Position [745, 600, 780, 610] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X Vin" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType SubSystem Name "MAC" SID "13198" Ports [4, 2] Position [575, 279, 660, 376] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "MAC" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "a" SID "13199" Position [35, 143, 65, 157] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "coeff" SID "13200" Position [35, 108, 65, 122] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "ld" SID "13201" Position [35, 178, 65, 192] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "rst" SID "13202" Position [35, 233, 65, 247] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub" SID "13203" Ports [3, 1] Position [340, 113, 385, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition or Subtraction" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Signed (2's comp)" n_bits "long_cor_acc_n_bits" bin_pt "0" quantization "Truncate" overflow "Flag as error" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[2 0 0 4 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,344" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,3,1,white,blue,0,02f64c57,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('input',3,'su" "b');\ncolor('black');port_label('output',1,'\\bf{a \\pm b}','texmode','on');\nfprintf('','COMMENT: end icon text" "');\n" } Block { BlockType Reference Name "Gateway Out1" SID "13204" Ports [1, 1] Position [475, 450, 510, 460] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out2" SID "13205" Ports [1, 1] Position [475, 465, 510, 475] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out3" SID "13206" Ports [1, 1] Position [475, 480, 510, 490] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out6" SID "13207" Ports [1, 1] Position [475, 405, 510, 415] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out7" SID "13208" Ports [1, 1] Position [475, 420, 510, 430] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out8" SID "13209" Ports [1, 1] Position [475, 435, 510, 445] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "13210" Ports [2, 1] Position [345, 30, 385, 70] BlockMirror on NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,40,2,1,white,blue,0,140cc11c,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'" "q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "13211" Ports [2, 1] Position [465, 110, 495, 210] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,100,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 100 100 0 ],[0.77 0." "82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 100 100 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[54.44 " "54.44 58.44 54.44 58.44 58.44 58.44 54.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[50.44 50.44 54.44 54" ".44 50.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[46.44 46.44 50.44 50.44 46.44 ],[1 1 1 ])" ";\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[42.44 42.44 46.44 42.44 46.44 46.44 42.44 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\nco" "lor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc2" SID "13212" Ports [1, 1] Position [265, 143, 290, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc3" SID "13213" Ports [1, 1] Position [135, 178, 160, 192] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "yn" SID "13214" Position [545, 153, 575, 167] IconDisplay "Port number" } Block { BlockType Outport Name "accrm" SID "13215" Position [520, 288, 550, 302] Port "2" IconDisplay "Port number" } Line { SrcBlock "coeff" SrcPort 1 Points [95, 0; 0, 20; 50, 0] Branch { DstBlock "AddSub" DstPort 2 } Branch { Points [0, 275] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "bc2" SrcPort 1 DstBlock "AddSub" DstPort 3 } Line { SrcBlock "bc3" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "ld" SrcPort 1 Points [45, 0] Branch { DstBlock "bc3" DstPort 1 } Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "Register1" SrcPort 1 Points [-15, 0] DstBlock "AddSub" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 Points [15, 0] Branch { DstBlock "yn" DstPort 1 } Branch { Points [0, 50; 110, 0; 0, 385; -260, 0; 0, -110] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "AddSub" SrcPort 1 Points [0, 0; 5, 0] Branch { Points [40, 0] Branch { DstBlock "Register2" DstPort 1 } Branch { Points [0, -95] DstBlock "Register1" DstPort 1 } Branch { Points [0, 160] DstBlock "accrm" DstPort 1 } } Branch { Points [0, 305] DstBlock "Gateway Out8" DstPort 1 } } Line { SrcBlock "a" SrcPort 1 Points [140, 0] Branch { DstBlock "bc2" DstPort 1 } Branch { Points [0, 275] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "Gateway Out8" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out7" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out6" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out1" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out2" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out3" SrcPort 1 Points [50, 0] } Line { SrcBlock "rst" SrcPort 1 Points [90, 0] Branch { Points [255, 0; 0, -180] DstBlock "Register1" DstPort 2 } Branch { Points [0, 215] DstBlock "Gateway Out1" DstPort 1 } } } } Block { BlockType Reference Name "ROM" SID "13216" Ports [1, 1] Position [440, 328, 490, 372] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/ROM" SourceType "Xilinx Single Port Read-Only Memory Block" depth "length(coef2)" initVector "coef2" distributed_mem "Distributed memory" rst off init_reg "0" en off latency "1" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "longCorr_coef_nbits" bin_pt "longCorr_coef_bp" preci_type "Single" exp_width "8" frac_width "24" dbl_ovrd off optimize "Area" use_rpm off xl_use_area off xl_area "[1 1 0 1 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,308" block_type "sprom" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,44,1,1,white,blue,0,bbc23d60,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 44 44 0 ]);\npatch([11.65 20.32 26.32 32.32 38.32 26.32 17.65 11.65 ],[28.66" " 28.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([17.65 26.32 20.32 11.65 17.65 ],[22.66 22.66 28." "66 28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([11.65 20.32 26.32 17.65 11.65 ],[16.66 16.66 22.66 22.66 16.66 ]" ",[1 1 1 ]);\npatch([17.65 38.32 32.32 26.32 20.32 11.65 17.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'addr');\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end" " icon text');\n" } Block { BlockType Outport Name "x_dly" SID "13217" Position [790, 178, 820, 192] IconDisplay "Port number" } Block { BlockType Outport Name "x_dly_vout" SID "13218" Position [790, 223, 820, 237] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "y" SID "13219" Position [790, 293, 820, 307] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "y_vout" SID "13220" Position [785, 448, 815, 462] Port "4" IconDisplay "Port number" } Line { SrcBlock "From2" SrcPort 1 Points [145, 0] Branch { Points [90, 0] Branch { Points [0, -50] Branch { DstBlock "MAC" DstPort 3 } Branch { Points [0, -90; 160, 0] } } Branch { Points [0, 65] DstBlock "Delay" DstPort 1 } } Branch { Points [0, 260] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "ROM" SrcPort 1 Points [5, 0] Branch { Points [0, -35] DstBlock "MAC" DstPort 2 } Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "MAC" SrcPort 1 Points [0, -5; 15, 0] Branch { DstBlock "y" DstPort 1 } Branch { Points [0, 365] DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "ASR" SrcPort 1 Points [35, 0] Branch { DstBlock "MAC" DstPort 1 } Branch { Points [0, -105] DstBlock "x_dly" DstPort 1 } Branch { Points [0, 330] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "From1" SrcPort 1 Points [5, 0] Branch { DstBlock "ROM" DstPort 1 } Branch { Points [0, 330] DstBlock "Gateway Out5" DstPort 1 } } Line { SrcBlock "From" SrcPort 1 Points [90, 0] Branch { DstBlock "ASR" DstPort 2 } Branch { Points [0, 300] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "x" SrcPort 1 Points [100, 0] Branch { DstBlock "ASR" DstPort 1 } Branch { Points [0, 305] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "vin" SrcPort 1 Points [25, 0] Branch { DstBlock "ASR" DstPort 3 } Branch { Points [0, 100] Branch { Points [0, 195] DstBlock "Gateway Out8" DstPort 1 } Branch { Points [230, 0] DstBlock "MAC" DstPort 4 } } Branch { Points [0, -80] DstBlock "x_dly_vout" DstPort 1 } } Line { SrcBlock "Delay" SrcPort 1 DstBlock "y_vout" DstPort 1 } Line { Name "X Vin" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 Points [150, 0] } Line { Name "ASR Addr" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 Points [150, 0] } Line { Name "X In" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 Points [150, 0] } Line { Name "ASR Out" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 Points [150, 0] } Line { Name "ROM Out" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 Points [150, 0] } Line { Name "Corr Ld" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 Points [150, 0] } Line { Name "Corr Out" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 Points [150, 0] } Line { Name "ROM Addr" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 Points [150, 0] } } } Block { BlockType SubSystem Name "C8" SID "13221" Ports [4, 4] Position [1060, 207, 1130, 293] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskPromptString "Coefficients (all)|Sub-correlator Ind|Coef/correlator" MaskStyleString "edit,edit,edit" MaskVariables "h=@1;c_ind=@2;N=@3;" MaskTunableValueString "on,on,on" MaskCallbackString "||" MaskEnableString "on,on,on" MaskVisibilityString "on,on,on" MaskToolTipString "on,on,on" MaskInitialization "coef2 = h((c_ind*N+1) : (c_ind + 1)*N);" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "h|7|N" System { Name "C8" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "122" Block { BlockType Inport Name "x" SID "13222" Position [265, 263, 295, 277] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "vin" SID "13223" Position [270, 303, 300, 317] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "13224" Position [270, 458, 300, 472] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "13225" Position [270, 503, 300, 517] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "ASR" SID "13226" Ports [3, 1] Position [445, 260, 490, 320] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Addressable Shift Register" SourceType "Xilinx Addressable Shift Register Block" infoedit "Delay of configurable length. Any element in the delay line can be addressed and driven onto the" " output port.

Hardware notes: This block is implemented using SRL16s. If Virtex-4 or Spartan-3 device is " "used, multiple SRLC16s are cascaded together." infer_latency off depth "length(coef2)" initVector "[0]" en on dbl_ovrd off use_behavioral_HDL off Optimization "Resource" xl_use_area off xl_area "[1 0 0 2 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,401" block_type "addrsr" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,60,3,1,white,blue,0,f8ea6153,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 60 60 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 60 60 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[36.66 3" "6.66 42.66 36.66 42.66 42.66 42.66 36.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[30.66 30.66 36.66 " "36.66 30.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[24.66 24.66 30.66 30.66 24.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[18.66 18.66 24.66 18.66 24.66 24.66 18.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'addr');\ncolor('black');port_label('input',3," "'en');\ncolor('black');port_label('output',1,'q');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Delay" SID "13227" Ports [1, 1] Position [705, 441, 730, 469] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "25,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 " "17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33" " 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('blac" "k');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "13228" Position [210, 280, 300, 300] ZOrder -9 ShowName off GotoTag "ltsCorr_dAddr" TagVisibility "scoped" } Block { BlockType From Name "From1" SID "13229" Position [210, 340, 300, 360] ZOrder -9 ShowName off GotoTag "ltsCorr_cAddr" TagVisibility "scoped" } Block { BlockType From Name "From2" SID "13230" Position [210, 380, 300, 400] ZOrder -9 ShowName off GotoTag "ltsCorr_ld" TagVisibility "scoped" } Block { BlockType Reference Name "Gateway Out1" SID "13231" Ports [1, 1] Position [745, 615, 780, 625] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "13232" Ports [1, 1] Position [745, 630, 780, 640] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "13233" Ports [1, 1] Position [745, 645, 780, 655] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Ld" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "13234" Ports [1, 1] Position [745, 660, 780, 670] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "13235" Ports [1, 1] Position [745, 675, 780, 685] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "13236" Ports [1, 1] Position [745, 570, 780, 580] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X In" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "13237" Ports [1, 1] Position [745, 585, 780, 595] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "13238" Ports [1, 1] Position [745, 600, 780, 610] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X Vin" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType SubSystem Name "MAC" SID "13239" Ports [4, 2] Position [575, 279, 660, 376] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "MAC" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "a" SID "13240" Position [35, 143, 65, 157] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "coeff" SID "13241" Position [35, 108, 65, 122] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "ld" SID "13242" Position [35, 178, 65, 192] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "rst" SID "13243" Position [35, 233, 65, 247] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub" SID "13244" Ports [3, 1] Position [340, 113, 385, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition or Subtraction" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Signed (2's comp)" n_bits "long_cor_acc_n_bits" bin_pt "0" quantization "Truncate" overflow "Flag as error" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[2 0 0 4 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,344" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,3,1,white,blue,0,02f64c57,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('input',3,'su" "b');\ncolor('black');port_label('output',1,'\\bf{a \\pm b}','texmode','on');\nfprintf('','COMMENT: end icon text" "');\n" } Block { BlockType Reference Name "Gateway Out1" SID "13245" Ports [1, 1] Position [475, 450, 510, 460] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out2" SID "13246" Ports [1, 1] Position [475, 465, 510, 475] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out3" SID "13247" Ports [1, 1] Position [475, 480, 510, 490] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out6" SID "13248" Ports [1, 1] Position [475, 405, 510, 415] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out7" SID "13249" Ports [1, 1] Position [475, 420, 510, 430] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out8" SID "13250" Ports [1, 1] Position [475, 435, 510, 445] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "13251" Ports [2, 1] Position [345, 30, 385, 70] BlockMirror on NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,40,2,1,white,blue,0,140cc11c,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'" "q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "13252" Ports [2, 1] Position [465, 110, 495, 210] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,100,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 100 100 0 ],[0.77 0." "82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 100 100 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[54.44 " "54.44 58.44 54.44 58.44 58.44 58.44 54.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[50.44 50.44 54.44 54" ".44 50.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[46.44 46.44 50.44 50.44 46.44 ],[1 1 1 ])" ";\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[42.44 42.44 46.44 42.44 46.44 46.44 42.44 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\nco" "lor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc2" SID "13253" Ports [1, 1] Position [265, 143, 290, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc3" SID "13254" Ports [1, 1] Position [135, 178, 160, 192] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "yn" SID "13255" Position [545, 153, 575, 167] IconDisplay "Port number" } Block { BlockType Outport Name "accrm" SID "13256" Position [520, 288, 550, 302] Port "2" IconDisplay "Port number" } Line { SrcBlock "rst" SrcPort 1 Points [90, 0] Branch { Points [0, 215] DstBlock "Gateway Out1" DstPort 1 } Branch { Points [255, 0; 0, -180] DstBlock "Register1" DstPort 2 } } Line { SrcBlock "Gateway Out3" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out2" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out1" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out6" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out7" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out8" SrcPort 1 Points [50, 0] } Line { SrcBlock "a" SrcPort 1 Points [140, 0] Branch { Points [0, 275] DstBlock "Gateway Out7" DstPort 1 } Branch { DstBlock "bc2" DstPort 1 } } Line { SrcBlock "AddSub" SrcPort 1 Points [0, 0; 5, 0] Branch { Points [0, 305] DstBlock "Gateway Out8" DstPort 1 } Branch { Points [40, 0] Branch { Points [0, 160] DstBlock "accrm" DstPort 1 } Branch { Points [0, -95] DstBlock "Register1" DstPort 1 } Branch { DstBlock "Register2" DstPort 1 } } } Line { SrcBlock "Register2" SrcPort 1 Points [15, 0] Branch { Points [0, 50; 110, 0; 0, 385; -260, 0; 0, -110] DstBlock "Gateway Out3" DstPort 1 } Branch { DstBlock "yn" DstPort 1 } } Line { SrcBlock "Register1" SrcPort 1 Points [-15, 0] DstBlock "AddSub" DstPort 1 } Line { SrcBlock "ld" SrcPort 1 Points [45, 0] Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } Branch { DstBlock "bc3" DstPort 1 } } Line { SrcBlock "bc3" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "bc2" SrcPort 1 DstBlock "AddSub" DstPort 3 } Line { SrcBlock "coeff" SrcPort 1 Points [95, 0; 0, 20; 50, 0] Branch { Points [0, 275] DstBlock "Gateway Out6" DstPort 1 } Branch { DstBlock "AddSub" DstPort 2 } } } } Block { BlockType Reference Name "ROM" SID "13257" Ports [1, 1] Position [440, 328, 490, 372] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/ROM" SourceType "Xilinx Single Port Read-Only Memory Block" depth "length(coef2)" initVector "coef2" distributed_mem "Distributed memory" rst off init_reg "0" en off latency "1" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "longCorr_coef_nbits" bin_pt "longCorr_coef_bp" preci_type "Single" exp_width "8" frac_width "24" dbl_ovrd off optimize "Area" use_rpm off xl_use_area off xl_area "[1 1 0 1 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,308" block_type "sprom" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,44,1,1,white,blue,0,bbc23d60,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 44 44 0 ]);\npatch([11.65 20.32 26.32 32.32 38.32 26.32 17.65 11.65 ],[28.66" " 28.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([17.65 26.32 20.32 11.65 17.65 ],[22.66 22.66 28." "66 28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([11.65 20.32 26.32 17.65 11.65 ],[16.66 16.66 22.66 22.66 16.66 ]" ",[1 1 1 ]);\npatch([17.65 38.32 32.32 26.32 20.32 11.65 17.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'addr');\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end" " icon text');\n" } Block { BlockType Outport Name "x_dly" SID "13258" Position [790, 178, 820, 192] IconDisplay "Port number" } Block { BlockType Outport Name "x_dly_vout" SID "13259" Position [790, 223, 820, 237] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "y" SID "13260" Position [790, 293, 820, 307] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "y_vout" SID "13261" Position [785, 448, 815, 462] Port "4" IconDisplay "Port number" } Line { Name "ROM Addr" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 Points [150, 0] } Line { Name "Corr Out" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 Points [150, 0] } Line { Name "Corr Ld" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 Points [150, 0] } Line { Name "ROM Out" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 Points [150, 0] } Line { Name "ASR Out" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 Points [150, 0] } Line { Name "X In" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 Points [150, 0] } Line { Name "ASR Addr" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 Points [150, 0] } Line { Name "X Vin" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 Points [150, 0] } Line { SrcBlock "Delay" SrcPort 1 DstBlock "y_vout" DstPort 1 } Line { SrcBlock "vin" SrcPort 1 Points [25, 0] Branch { Points [0, -80] DstBlock "x_dly_vout" DstPort 1 } Branch { Points [0, 100] Branch { Points [230, 0] DstBlock "MAC" DstPort 4 } Branch { Points [0, 195] DstBlock "Gateway Out8" DstPort 1 } } Branch { DstBlock "ASR" DstPort 3 } } Line { SrcBlock "x" SrcPort 1 Points [100, 0] Branch { Points [0, 305] DstBlock "Gateway Out6" DstPort 1 } Branch { DstBlock "ASR" DstPort 1 } } Line { SrcBlock "From" SrcPort 1 Points [90, 0] Branch { Points [0, 300] DstBlock "Gateway Out7" DstPort 1 } Branch { DstBlock "ASR" DstPort 2 } } Line { SrcBlock "From1" SrcPort 1 Points [5, 0] Branch { Points [0, 330] DstBlock "Gateway Out5" DstPort 1 } Branch { DstBlock "ROM" DstPort 1 } } Line { SrcBlock "ASR" SrcPort 1 Points [35, 0] Branch { Points [0, 330] DstBlock "Gateway Out1" DstPort 1 } Branch { Points [0, -105] DstBlock "x_dly" DstPort 1 } Branch { DstBlock "MAC" DstPort 1 } } Line { SrcBlock "MAC" SrcPort 1 Points [0, -5; 15, 0] Branch { Points [0, 365] DstBlock "Gateway Out4" DstPort 1 } Branch { DstBlock "y" DstPort 1 } } Line { SrcBlock "ROM" SrcPort 1 Points [5, 0] Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } Branch { Points [0, -35] DstBlock "MAC" DstPort 2 } } Line { SrcBlock "From2" SrcPort 1 Points [145, 0] Branch { Points [0, 260] DstBlock "Gateway Out3" DstPort 1 } Branch { Points [90, 0] Branch { Points [0, 65] DstBlock "Delay" DstPort 1 } Branch { Points [0, -50] Branch { Points [0, -90; 160, 0] } Branch { DstBlock "MAC" DstPort 3 } } } } } } Block { BlockType Reference Name "Gateway Out1" SID "13262" Ports [1, 1] Position [1195, 75, 1230, 85] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out10" SID "13263" Ports [1, 1] Position [1195, 120, 1230, 130] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out11" SID "13264" Ports [1, 1] Position [1195, 135, 1230, 145] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out12" SID "13265" Ports [1, 1] Position [1195, 150, 1230, 160] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out13" SID "13266" Ports [1, 1] Position [1195, 165, 1230, 175] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out14" SID "13267" Ports [1, 1] Position [1225, 180, 1260, 190] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out2" SID "13268" Ports [1, 1] Position [740, 720, 775, 730] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out3" SID "13269" Ports [1, 1] Position [740, 690, 775, 700] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out4" SID "13270" Ports [1, 1] Position [740, 705, 775, 715] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out5" SID "13271" Ports [1, 1] Position [740, 735, 775, 745] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out6" SID "13272" Ports [1, 1] Position [1195, 45, 1230, 55] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out7" SID "13273" Ports [1, 1] Position [1195, 60, 1230, 70] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out8" SID "13274" Ports [1, 1] Position [1195, 90, 1230, 100] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out9" SID "13275" Ports [1, 1] Position [1195, 105, 1230, 115] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Outport Name "y" SID "13276" Position [1290, 568, 1320, 582] IconDisplay "Port number" } Block { BlockType Outport Name "y_vout" SID "13277" Position [1290, 523, 1320, 537] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "x_dly" SID "13278" Position [1260, 213, 1290, 227] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "x_dly_vout" SID "13279" Position [1260, 253, 1290, 267] Port "4" IconDisplay "Port number" } Line { SrcBlock "x" SrcPort 1 Points [210, 0] Branch { DstBlock "C1" DstPort 1 } Branch { Points [0, 475] DstBlock "Gateway Out3" DstPort 1 } Branch { Points [0, -170] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "AddSub12" SrcPort 1 DstBlock "AddSub13" DstPort 2 } Line { SrcBlock "AddSub5" SrcPort 1 Points [0, 35] DstBlock "AddSub13" DstPort 1 } Line { SrcBlock "Gateway Out4" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out3" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out5" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out2" SrcPort 1 Points [50, 0] } Line { Points [780, 755; 50, 0] } Line { SrcBlock "x_valid" SrcPort 1 Points [200, 0] Branch { Points [0, -20] DstBlock "C1" DstPort 2 } Branch { Points [0, 450] DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "C1" SrcPort 1 DstBlock "C2" DstPort 1 } Line { SrcBlock "C1" SrcPort 2 DstBlock "C2" DstPort 2 } Line { SrcBlock "C2" SrcPort 1 DstBlock "C3" DstPort 1 } Line { SrcBlock "C2" SrcPort 2 DstBlock "C3" DstPort 2 } Line { SrcBlock "C2" SrcPort 3 Points [20, 0] Branch { DstBlock "AddSub5" DstPort 2 } Branch { Points [0, -180] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "C1" SrcPort 3 Points [15, 0] Branch { Points [0, 55] Branch { Points [0, 5; 95, 0] DstBlock "AddSub5" DstPort 1 } Branch { Points [0, 410] DstBlock "Gateway Out2" DstPort 1 } } Branch { Points [0, -195] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "C3" SrcPort 1 DstBlock "C4" DstPort 1 } Line { SrcBlock "C3" SrcPort 2 DstBlock "C4" DstPort 2 } Line { SrcBlock "C3" SrcPort 3 Points [20, 0] Branch { Points [0, 65; 80, 0] DstBlock "AddSub12" DstPort 1 } Branch { Points [0, -165] DstBlock "Gateway Out8" DstPort 1 } } Line { SrcBlock "C4" SrcPort 1 DstBlock "C5" DstPort 1 } Line { SrcBlock "C4" SrcPort 2 DstBlock "C5" DstPort 2 } Line { SrcBlock "C4" SrcPort 3 Points [15, 0] Branch { DstBlock "AddSub12" DstPort 2 } Branch { Points [0, -150] DstBlock "Gateway Out9" DstPort 1 } } Line { SrcBlock "C5" SrcPort 1 DstBlock "C6" DstPort 1 } Line { SrcBlock "C5" SrcPort 2 DstBlock "C6" DstPort 2 } Line { SrcBlock "C6" SrcPort 1 DstBlock "C7" DstPort 1 } Line { SrcBlock "C6" SrcPort 2 DstBlock "C7" DstPort 2 } Line { SrcBlock "C7" SrcPort 1 DstBlock "C8" DstPort 1 } Line { SrcBlock "C7" SrcPort 2 DstBlock "C8" DstPort 2 } Line { SrcBlock "C6" SrcPort 3 Points [15, 0] Branch { DstBlock "AddSub6" DstPort 2 } Branch { Points [0, -120] DstBlock "Gateway Out11" DstPort 1 } } Line { SrcBlock "C5" SrcPort 3 Points [10, 0] Branch { Points [0, 70; 85, 0] DstBlock "AddSub6" DstPort 1 } Branch { Points [0, -135] DstBlock "Gateway Out10" DstPort 1 } } Line { SrcBlock "C8" SrcPort 3 Points [10, 0] Branch { DstBlock "AddSub7" DstPort 2 } Branch { Points [0, -90] DstBlock "Gateway Out13" DstPort 1 } } Line { SrcBlock "C7" SrcPort 3 Points [20, 0] Branch { Points [0, 65; 75, 0] DstBlock "AddSub7" DstPort 1 } Branch { Points [0, -105] DstBlock "Gateway Out12" DstPort 1 } } Line { SrcBlock "AddSub6" SrcPort 1 DstBlock "AddSub1" DstPort 1 } Line { SrcBlock "AddSub7" SrcPort 1 Points [0, 35] DstBlock "AddSub1" DstPort 2 } Line { SrcBlock "AddSub13" SrcPort 1 Points [0, 85] DstBlock "AddSub4" DstPort 2 } Line { SrcBlock "AddSub1" SrcPort 1 Points [0, 60] DstBlock "AddSub4" DstPort 1 } Line { SrcBlock "AddSub4" SrcPort 1 Points [45, 0] Branch { Points [0, 75; -400, 0; 0, 90] DstBlock "Gateway Out5" DstPort 1 } Branch { Points [155, 0] Branch { DstBlock "y" DstPort 1 } Branch { Points [0, -390] DstBlock "Gateway Out14" DstPort 1 } } } Line { SrcBlock "C8" SrcPort 4 Points [40, 0; 0, 250] DstBlock "y_vout" DstPort 1 } Line { SrcBlock "Gateway Out7" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out6" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out8" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out1" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out9" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out10" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out11" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out12" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out13" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out14" SrcPort 1 Points [20, 0] } Line { SrcBlock "C8" SrcPort 1 DstBlock "x_dly" DstPort 1 } Line { SrcBlock "C8" SrcPort 2 Points [110, 0] DstBlock "x_dly_vout" DstPort 1 } } } Block { BlockType SubSystem Name "C5" SID "13280" Ports [2, 4] Position [585, 258, 670, 327] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskPromptString "Coefficients/correlator|Coefficients|Input sample period" MaskStyleString "edit,edit,edit" MaskVariables "N=@1;h=@2;Ts_In=@3;" MaskTunableValueString "on,on,on" MaskCallbackString "||" MaskEnableString "on,on,on" MaskVisibilityString "on,on,on" MaskToolTipString "on,on,on" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "4|longCorr_coef_q(1:32)|4" System { Name "C5" Location [480, 85, 2304, 1455] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "156" Block { BlockType Inport Name "x" SID "13281" Position [35, 213, 65, 227] IconDisplay "Port number" } Block { BlockType Inport Name "x_valid" SID "13282" Position [35, 253, 65, 267] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub1" SID "13283" Ports [2, 1] Position [915, 455, 955, 495] BlockRotation 270 BlockMirror on NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "1" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[3 6 0 5 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,40,2,1,white,blue,0,e85d8a90,down,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bf{a + b}','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\ne" "wline\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub12" SID "13284" Ports [2, 1] Position [684, 360, 731, 400] BlockRotation 270 BlockMirror on NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "1" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[3 5 0 4 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "47,40,2,1,white,blue,0,e85d8a90,down,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 47 47 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 47 47 0 0 ],[0 0 40 40 0 ]);\npatch([11.875 19.1 24.1 29.1 34.1 24.1 16.875 11.875 ],[25.55 2" "5.55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([16.875 24.1 19.1 11.875 16.875 ],[20.55 20.55 25.5" "5 25.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([11.875 19.1 24.1 16.875 11.875 ],[15.55 15.55 20.55 20.55 15.55 ]" ",[1 1 1 ]);\npatch([16.875 34.1 29.1 24.1 19.1 11.875 16.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('b" "lack');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output'" ",1,'\\bf{a + b}','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(" "' \\newline\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub13" SID "13285" Ports [2, 1] Position [680, 455, 720, 495] BlockRotation 270 BlockMirror on NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "1" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[3 6 0 5 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,40,2,1,white,blue,0,e85d8a90,down,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bf{a + b}','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\ne" "wline\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub4" SID "13286" Ports [2, 1] Position [960, 549, 1000, 596] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "1" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[4 7 0 6 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,47,2,1,white,blue,0,e85d8a90,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 47 47 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 47 47 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[28.55 28." "55 33.55 28.55 33.55 33.55 33.55 28.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[23.55 23.55 28.55 2" "8.55 23.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[18.55 18.55 23.55 23.55 18.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[13.55 13.55 18.55 13.55 18.55 18.55 13.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bf{a + b}','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\ne" "wline\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub5" SID "13287" Ports [2, 1] Position [475, 360, 515, 400] BlockRotation 270 BlockMirror on NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "1" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[3 6 0 5 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,40,2,1,white,blue,0,e85d8a90,down,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bf{a + b}','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\ne" "wline\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub6" SID "13288" Ports [2, 1] Position [899, 360, 946, 400] BlockRotation 270 BlockMirror on NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "1" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[3 5 0 4 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "47,40,2,1,white,blue,0,e85d8a90,down,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 47 47 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 47 47 0 0 ],[0 0 40 40 0 ]);\npatch([11.875 19.1 24.1 29.1 34.1 24.1 16.875 11.875 ],[25.55 2" "5.55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([16.875 24.1 19.1 11.875 16.875 ],[20.55 20.55 25.5" "5 25.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([11.875 19.1 24.1 16.875 11.875 ],[15.55 15.55 20.55 20.55 15.55 ]" ",[1 1 1 ]);\npatch([16.875 34.1 29.1 24.1 19.1 11.875 16.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('b" "lack');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output'" ",1,'\\bf{a + b}','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(" "' \\newline\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub7" SID "13289" Ports [2, 1] Position [1109, 360, 1156, 400] BlockRotation 270 BlockMirror on NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "1" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[3 5 0 4 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "47,40,2,1,white,blue,0,e85d8a90,down,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 47 47 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 47 47 0 0 ],[0 0 40 40 0 ]);\npatch([11.875 19.1 24.1 29.1 34.1 24.1 16.875 11.875 ],[25.55 2" "5.55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([16.875 24.1 19.1 11.875 16.875 ],[20.55 20.55 25.5" "5 25.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([11.875 19.1 24.1 16.875 11.875 ],[15.55 15.55 20.55 20.55 15.55 ]" ",[1 1 1 ]);\npatch([16.875 34.1 29.1 24.1 19.1 11.875 16.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('b" "lack');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output'" ",1,'\\bf{a + b}','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(" "' \\newline\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "C1" SID "13290" Ports [4, 4] Position [300, 207, 370, 293] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskPromptString "Coefficients (all)|Sub-correlator Ind|Coef/correlator" MaskStyleString "edit,edit,edit" MaskVariables "h=@1;c_ind=@2;N=@3;" MaskTunableValueString "on,on,on" MaskCallbackString "||" MaskEnableString "on,on,on" MaskVisibilityString "on,on,on" MaskToolTipString "on,on,on" MaskInitialization "coef2 = h((c_ind*N+1) : (c_ind + 1)*N);" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "h|0|N" System { Name "C1" Location [480, 85, 2304, 1471] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "122" Block { BlockType Inport Name "x" SID "13291" Position [265, 263, 295, 277] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "vin" SID "13292" Position [270, 303, 300, 317] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "13293" Position [270, 458, 300, 472] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "13294" Position [270, 503, 300, 517] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "ASR" SID "13295" Ports [3, 1] Position [445, 260, 490, 320] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Addressable Shift Register" SourceType "Xilinx Addressable Shift Register Block" infoedit "Delay of configurable length. Any element in the delay line can be addressed and driven onto the" " output port.

Hardware notes: This block is implemented using SRL16s. If Virtex-4 or Spartan-3 device is " "used, multiple SRLC16s are cascaded together." infer_latency off depth "length(coef2)" initVector "[0]" en on dbl_ovrd off use_behavioral_HDL off Optimization "Resource" xl_use_area off xl_area "[1 0 0 2 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,401" block_type "addrsr" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,60,3,1,white,blue,0,f8ea6153,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 60 60 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 60 60 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[36.66 3" "6.66 42.66 36.66 42.66 42.66 42.66 36.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[30.66 30.66 36.66 " "36.66 30.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[24.66 24.66 30.66 30.66 24.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[18.66 18.66 24.66 18.66 24.66 24.66 18.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'addr');\ncolor('black');port_label('input',3," "'en');\ncolor('black');port_label('output',1,'q');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Delay" SID "13296" Ports [1, 1] Position [705, 441, 730, 469] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "25,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 " "17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33" " 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('blac" "k');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "13297" Position [210, 280, 300, 300] ZOrder -9 ShowName off GotoTag "ltsCorr_dAddr" TagVisibility "scoped" } Block { BlockType From Name "From1" SID "13298" Position [210, 340, 300, 360] ZOrder -9 ShowName off GotoTag "ltsCorr_cAddr" TagVisibility "scoped" } Block { BlockType From Name "From2" SID "13299" Position [210, 380, 300, 400] ZOrder -9 ShowName off GotoTag "ltsCorr_ld" TagVisibility "scoped" } Block { BlockType Reference Name "Gateway Out1" SID "13300" Ports [1, 1] Position [745, 615, 780, 625] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "13301" Ports [1, 1] Position [745, 630, 780, 640] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "13302" Ports [1, 1] Position [745, 645, 780, 655] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Ld" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "13303" Ports [1, 1] Position [745, 660, 780, 670] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "13304" Ports [1, 1] Position [745, 675, 780, 685] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "13305" Ports [1, 1] Position [745, 570, 780, 580] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X In" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "13306" Ports [1, 1] Position [745, 585, 780, 595] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "13307" Ports [1, 1] Position [745, 600, 780, 610] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X Vin" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType SubSystem Name "MAC" SID "13308" Ports [4, 2] Position [575, 279, 660, 376] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "MAC" Location [88, 301, 2330, 1301] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "a" SID "13309" Position [35, 143, 65, 157] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "coeff" SID "13310" Position [35, 108, 65, 122] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "ld" SID "13311" Position [35, 178, 65, 192] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "rst" SID "13312" Position [35, 233, 65, 247] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub" SID "13313" Ports [3, 1] Position [340, 113, 385, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition or Subtraction" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Signed (2's comp)" n_bits "long_cor_acc_n_bits" bin_pt "0" quantization "Truncate" overflow "Flag as error" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[2 0 0 4 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,344" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,3,1,white,blue,0,02f64c57,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('input',3,'su" "b');\ncolor('black');port_label('output',1,'\\bf{a \\pm b}','texmode','on');\nfprintf('','COMMENT: end icon text" "');\n" } Block { BlockType Reference Name "Gateway Out1" SID "13314" Ports [1, 1] Position [475, 450, 510, 460] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out2" SID "13315" Ports [1, 1] Position [475, 465, 510, 475] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out3" SID "13316" Ports [1, 1] Position [475, 480, 510, 490] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out6" SID "13317" Ports [1, 1] Position [475, 405, 510, 415] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out7" SID "13318" Ports [1, 1] Position [475, 420, 510, 430] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out8" SID "13319" Ports [1, 1] Position [475, 435, 510, 445] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "13320" Ports [2, 1] Position [345, 30, 385, 70] BlockMirror on NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,40,2,1,white,blue,0,140cc11c,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'" "q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "13321" Ports [2, 1] Position [465, 110, 495, 210] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,100,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 100 100 0 ],[0.77 0." "82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 100 100 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[54.44 " "54.44 58.44 54.44 58.44 58.44 58.44 54.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[50.44 50.44 54.44 54" ".44 50.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[46.44 46.44 50.44 50.44 46.44 ],[1 1 1 ])" ";\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[42.44 42.44 46.44 42.44 46.44 46.44 42.44 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\nco" "lor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc2" SID "13322" Ports [1, 1] Position [265, 143, 290, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc3" SID "13323" Ports [1, 1] Position [135, 178, 160, 192] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "yn" SID "13324" Position [545, 153, 575, 167] IconDisplay "Port number" } Block { BlockType Outport Name "accrm" SID "13325" Position [520, 288, 550, 302] Port "2" IconDisplay "Port number" } Line { SrcBlock "rst" SrcPort 1 Points [90, 0] Branch { Points [0, 215] DstBlock "Gateway Out1" DstPort 1 } Branch { Points [255, 0; 0, -180] DstBlock "Register1" DstPort 2 } } Line { SrcBlock "Gateway Out3" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out2" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out1" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out6" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out7" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out8" SrcPort 1 Points [50, 0] } Line { SrcBlock "a" SrcPort 1 Points [140, 0] Branch { Points [0, 275] DstBlock "Gateway Out7" DstPort 1 } Branch { DstBlock "bc2" DstPort 1 } } Line { SrcBlock "AddSub" SrcPort 1 Points [0, 0; 5, 0] Branch { Points [0, 305] DstBlock "Gateway Out8" DstPort 1 } Branch { Points [40, 0] Branch { Points [0, 160] DstBlock "accrm" DstPort 1 } Branch { Points [0, -95] DstBlock "Register1" DstPort 1 } Branch { DstBlock "Register2" DstPort 1 } } } Line { SrcBlock "Register2" SrcPort 1 Points [15, 0] Branch { Points [0, 50; 110, 0; 0, 385; -260, 0; 0, -110] DstBlock "Gateway Out3" DstPort 1 } Branch { DstBlock "yn" DstPort 1 } } Line { SrcBlock "Register1" SrcPort 1 Points [-15, 0] DstBlock "AddSub" DstPort 1 } Line { SrcBlock "ld" SrcPort 1 Points [45, 0] Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } Branch { DstBlock "bc3" DstPort 1 } } Line { SrcBlock "bc3" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "bc2" SrcPort 1 DstBlock "AddSub" DstPort 3 } Line { SrcBlock "coeff" SrcPort 1 Points [95, 0; 0, 20; 50, 0] Branch { Points [0, 275] DstBlock "Gateway Out6" DstPort 1 } Branch { DstBlock "AddSub" DstPort 2 } } } } Block { BlockType Reference Name "ROM" SID "13326" Ports [1, 1] Position [440, 328, 490, 372] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/ROM" SourceType "Xilinx Single Port Read-Only Memory Block" depth "length(coef2)" initVector "coef2" distributed_mem "Distributed memory" rst off init_reg "0" en off latency "1" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "longCorr_coef_nbits" bin_pt "longCorr_coef_bp" preci_type "Single" exp_width "8" frac_width "24" dbl_ovrd off optimize "Area" use_rpm off xl_use_area off xl_area "[1 1 0 1 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,308" block_type "sprom" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,44,1,1,white,blue,0,bbc23d60,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 44 44 0 ]);\npatch([11.65 20.32 26.32 32.32 38.32 26.32 17.65 11.65 ],[28.66" " 28.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([17.65 26.32 20.32 11.65 17.65 ],[22.66 22.66 28." "66 28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([11.65 20.32 26.32 17.65 11.65 ],[16.66 16.66 22.66 22.66 16.66 ]" ",[1 1 1 ]);\npatch([17.65 38.32 32.32 26.32 20.32 11.65 17.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'addr');\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end" " icon text');\n" } Block { BlockType Outport Name "x_dly" SID "13327" Position [790, 178, 820, 192] IconDisplay "Port number" } Block { BlockType Outport Name "x_dly_vout" SID "13328" Position [790, 223, 820, 237] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "y" SID "13329" Position [790, 293, 820, 307] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "y_vout" SID "13330" Position [785, 448, 815, 462] Port "4" IconDisplay "Port number" } Line { Name "ROM Addr" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 Points [150, 0] } Line { Name "Corr Out" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 Points [150, 0] } Line { Name "Corr Ld" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 Points [150, 0] } Line { Name "ROM Out" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 Points [150, 0] } Line { Name "ASR Out" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 Points [150, 0] } Line { Name "X In" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 Points [150, 0] } Line { Name "ASR Addr" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 Points [150, 0] } Line { Name "X Vin" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 Points [150, 0] } Line { SrcBlock "Delay" SrcPort 1 DstBlock "y_vout" DstPort 1 } Line { SrcBlock "vin" SrcPort 1 Points [25, 0] Branch { Points [0, -80] DstBlock "x_dly_vout" DstPort 1 } Branch { Points [0, 100] Branch { Points [230, 0] DstBlock "MAC" DstPort 4 } Branch { Points [0, 195] DstBlock "Gateway Out8" DstPort 1 } } Branch { DstBlock "ASR" DstPort 3 } } Line { SrcBlock "x" SrcPort 1 Points [100, 0] Branch { Points [0, 305] DstBlock "Gateway Out6" DstPort 1 } Branch { DstBlock "ASR" DstPort 1 } } Line { SrcBlock "From" SrcPort 1 Points [90, 0] Branch { Points [0, 300] DstBlock "Gateway Out7" DstPort 1 } Branch { DstBlock "ASR" DstPort 2 } } Line { SrcBlock "From1" SrcPort 1 Points [5, 0] Branch { Points [0, 330] DstBlock "Gateway Out5" DstPort 1 } Branch { DstBlock "ROM" DstPort 1 } } Line { SrcBlock "ASR" SrcPort 1 Points [35, 0] Branch { Points [0, 330] DstBlock "Gateway Out1" DstPort 1 } Branch { Points [0, -105] DstBlock "x_dly" DstPort 1 } Branch { DstBlock "MAC" DstPort 1 } } Line { SrcBlock "MAC" SrcPort 1 Points [0, -5; 15, 0] Branch { Points [0, 365] DstBlock "Gateway Out4" DstPort 1 } Branch { DstBlock "y" DstPort 1 } } Line { SrcBlock "ROM" SrcPort 1 Points [5, 0] Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } Branch { Points [0, -35] DstBlock "MAC" DstPort 2 } } Line { SrcBlock "From2" SrcPort 1 Points [145, 0] Branch { Points [0, 260] DstBlock "Gateway Out3" DstPort 1 } Branch { Points [90, 0] Branch { Points [0, 65] DstBlock "Delay" DstPort 1 } Branch { Points [0, -50] Branch { Points [0, -90; 160, 0] } Branch { DstBlock "MAC" DstPort 3 } } } } } } Block { BlockType SubSystem Name "C2" SID "13331" Ports [4, 4] Position [410, 207, 480, 293] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskPromptString "Coefficients (all)|Sub-correlator Ind|Coef/correlator" MaskStyleString "edit,edit,edit" MaskVariables "h=@1;c_ind=@2;N=@3;" MaskTunableValueString "on,on,on" MaskCallbackString "||" MaskEnableString "on,on,on" MaskVisibilityString "on,on,on" MaskToolTipString "on,on,on" MaskInitialization "coef2 = h((c_ind*N+1) : (c_ind + 1)*N);" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "h|1|N" System { Name "C2" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "122" Block { BlockType Inport Name "x" SID "13332" Position [265, 263, 295, 277] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "vin" SID "13333" Position [270, 303, 300, 317] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "13334" Position [270, 458, 300, 472] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "13335" Position [270, 503, 300, 517] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "ASR" SID "13336" Ports [3, 1] Position [445, 260, 490, 320] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Addressable Shift Register" SourceType "Xilinx Addressable Shift Register Block" infoedit "Delay of configurable length. Any element in the delay line can be addressed and driven onto the" " output port.

Hardware notes: This block is implemented using SRL16s. If Virtex-4 or Spartan-3 device is " "used, multiple SRLC16s are cascaded together." infer_latency off depth "length(coef2)" initVector "[0]" en on dbl_ovrd off use_behavioral_HDL off Optimization "Resource" xl_use_area off xl_area "[1 0 0 2 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,401" block_type "addrsr" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,60,3,1,white,blue,0,f8ea6153,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 60 60 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 60 60 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[36.66 3" "6.66 42.66 36.66 42.66 42.66 42.66 36.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[30.66 30.66 36.66 " "36.66 30.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[24.66 24.66 30.66 30.66 24.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[18.66 18.66 24.66 18.66 24.66 24.66 18.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'addr');\ncolor('black');port_label('input',3," "'en');\ncolor('black');port_label('output',1,'q');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Delay" SID "13337" Ports [1, 1] Position [705, 441, 730, 469] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "25,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 " "17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33" " 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('blac" "k');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "13338" Position [210, 280, 300, 300] ZOrder -9 ShowName off GotoTag "ltsCorr_dAddr" TagVisibility "scoped" } Block { BlockType From Name "From1" SID "13339" Position [210, 340, 300, 360] ZOrder -9 ShowName off GotoTag "ltsCorr_cAddr" TagVisibility "scoped" } Block { BlockType From Name "From2" SID "13340" Position [210, 380, 300, 400] ZOrder -9 ShowName off GotoTag "ltsCorr_ld" TagVisibility "scoped" } Block { BlockType Reference Name "Gateway Out1" SID "13341" Ports [1, 1] Position [745, 615, 780, 625] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "13342" Ports [1, 1] Position [745, 630, 780, 640] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "13343" Ports [1, 1] Position [745, 645, 780, 655] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Ld" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "13344" Ports [1, 1] Position [745, 660, 780, 670] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "13345" Ports [1, 1] Position [745, 675, 780, 685] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "13346" Ports [1, 1] Position [745, 570, 780, 580] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X In" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "13347" Ports [1, 1] Position [745, 585, 780, 595] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "13348" Ports [1, 1] Position [745, 600, 780, 610] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X Vin" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType SubSystem Name "MAC" SID "13349" Ports [4, 2] Position [575, 279, 660, 376] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "MAC" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "a" SID "13350" Position [35, 143, 65, 157] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "coeff" SID "13351" Position [35, 108, 65, 122] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "ld" SID "13352" Position [35, 178, 65, 192] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "rst" SID "13353" Position [35, 233, 65, 247] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub" SID "13354" Ports [3, 1] Position [340, 113, 385, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition or Subtraction" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Signed (2's comp)" n_bits "long_cor_acc_n_bits" bin_pt "0" quantization "Truncate" overflow "Flag as error" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[2 0 0 4 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,344" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,3,1,white,blue,0,02f64c57,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('input',3,'su" "b');\ncolor('black');port_label('output',1,'\\bf{a \\pm b}','texmode','on');\nfprintf('','COMMENT: end icon text" "');\n" } Block { BlockType Reference Name "Gateway Out1" SID "13355" Ports [1, 1] Position [475, 450, 510, 460] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out2" SID "13356" Ports [1, 1] Position [475, 465, 510, 475] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out3" SID "13357" Ports [1, 1] Position [475, 480, 510, 490] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out6" SID "13358" Ports [1, 1] Position [475, 405, 510, 415] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out7" SID "13359" Ports [1, 1] Position [475, 420, 510, 430] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out8" SID "13360" Ports [1, 1] Position [475, 435, 510, 445] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "13361" Ports [2, 1] Position [345, 30, 385, 70] BlockMirror on NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,40,2,1,white,blue,0,140cc11c,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'" "q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "13362" Ports [2, 1] Position [465, 110, 495, 210] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,100,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 100 100 0 ],[0.77 0." "82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 100 100 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[54.44 " "54.44 58.44 54.44 58.44 58.44 58.44 54.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[50.44 50.44 54.44 54" ".44 50.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[46.44 46.44 50.44 50.44 46.44 ],[1 1 1 ])" ";\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[42.44 42.44 46.44 42.44 46.44 46.44 42.44 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\nco" "lor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc2" SID "13363" Ports [1, 1] Position [265, 143, 290, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc3" SID "13364" Ports [1, 1] Position [135, 178, 160, 192] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "yn" SID "13365" Position [545, 153, 575, 167] IconDisplay "Port number" } Block { BlockType Outport Name "accrm" SID "13366" Position [520, 288, 550, 302] Port "2" IconDisplay "Port number" } Line { SrcBlock "coeff" SrcPort 1 Points [95, 0; 0, 20; 50, 0] Branch { DstBlock "AddSub" DstPort 2 } Branch { Points [0, 275] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "bc2" SrcPort 1 DstBlock "AddSub" DstPort 3 } Line { SrcBlock "bc3" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "ld" SrcPort 1 Points [45, 0] Branch { DstBlock "bc3" DstPort 1 } Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "Register1" SrcPort 1 Points [-15, 0] DstBlock "AddSub" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 Points [15, 0] Branch { DstBlock "yn" DstPort 1 } Branch { Points [0, 50; 110, 0; 0, 385; -260, 0; 0, -110] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "AddSub" SrcPort 1 Points [0, 0; 5, 0] Branch { Points [40, 0] Branch { DstBlock "Register2" DstPort 1 } Branch { Points [0, -95] DstBlock "Register1" DstPort 1 } Branch { Points [0, 160] DstBlock "accrm" DstPort 1 } } Branch { Points [0, 305] DstBlock "Gateway Out8" DstPort 1 } } Line { SrcBlock "a" SrcPort 1 Points [140, 0] Branch { DstBlock "bc2" DstPort 1 } Branch { Points [0, 275] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "Gateway Out8" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out7" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out6" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out1" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out2" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out3" SrcPort 1 Points [50, 0] } Line { SrcBlock "rst" SrcPort 1 Points [90, 0] Branch { Points [255, 0; 0, -180] DstBlock "Register1" DstPort 2 } Branch { Points [0, 215] DstBlock "Gateway Out1" DstPort 1 } } } } Block { BlockType Reference Name "ROM" SID "13367" Ports [1, 1] Position [440, 328, 490, 372] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/ROM" SourceType "Xilinx Single Port Read-Only Memory Block" depth "length(coef2)" initVector "coef2" distributed_mem "Distributed memory" rst off init_reg "0" en off latency "1" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "longCorr_coef_nbits" bin_pt "longCorr_coef_bp" preci_type "Single" exp_width "8" frac_width "24" dbl_ovrd off optimize "Area" use_rpm off xl_use_area off xl_area "[1 1 0 1 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,308" block_type "sprom" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,44,1,1,white,blue,0,bbc23d60,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 44 44 0 ]);\npatch([11.65 20.32 26.32 32.32 38.32 26.32 17.65 11.65 ],[28.66" " 28.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([17.65 26.32 20.32 11.65 17.65 ],[22.66 22.66 28." "66 28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([11.65 20.32 26.32 17.65 11.65 ],[16.66 16.66 22.66 22.66 16.66 ]" ",[1 1 1 ]);\npatch([17.65 38.32 32.32 26.32 20.32 11.65 17.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'addr');\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end" " icon text');\n" } Block { BlockType Outport Name "x_dly" SID "13368" Position [790, 178, 820, 192] IconDisplay "Port number" } Block { BlockType Outport Name "x_dly_vout" SID "13369" Position [790, 223, 820, 237] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "y" SID "13370" Position [790, 293, 820, 307] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "y_vout" SID "13371" Position [785, 448, 815, 462] Port "4" IconDisplay "Port number" } Line { SrcBlock "From2" SrcPort 1 Points [145, 0] Branch { Points [90, 0] Branch { Points [0, -50] Branch { DstBlock "MAC" DstPort 3 } Branch { Points [0, -90; 160, 0] } } Branch { Points [0, 65] DstBlock "Delay" DstPort 1 } } Branch { Points [0, 260] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "ROM" SrcPort 1 Points [5, 0] Branch { Points [0, -35] DstBlock "MAC" DstPort 2 } Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "MAC" SrcPort 1 Points [0, -5; 15, 0] Branch { DstBlock "y" DstPort 1 } Branch { Points [0, 365] DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "ASR" SrcPort 1 Points [35, 0] Branch { DstBlock "MAC" DstPort 1 } Branch { Points [0, -105] DstBlock "x_dly" DstPort 1 } Branch { Points [0, 330] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "From1" SrcPort 1 Points [5, 0] Branch { DstBlock "ROM" DstPort 1 } Branch { Points [0, 330] DstBlock "Gateway Out5" DstPort 1 } } Line { SrcBlock "From" SrcPort 1 Points [90, 0] Branch { DstBlock "ASR" DstPort 2 } Branch { Points [0, 300] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "x" SrcPort 1 Points [100, 0] Branch { DstBlock "ASR" DstPort 1 } Branch { Points [0, 305] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "vin" SrcPort 1 Points [25, 0] Branch { DstBlock "ASR" DstPort 3 } Branch { Points [0, 100] Branch { Points [0, 195] DstBlock "Gateway Out8" DstPort 1 } Branch { Points [230, 0] DstBlock "MAC" DstPort 4 } } Branch { Points [0, -80] DstBlock "x_dly_vout" DstPort 1 } } Line { SrcBlock "Delay" SrcPort 1 DstBlock "y_vout" DstPort 1 } Line { Name "X Vin" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 Points [150, 0] } Line { Name "ASR Addr" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 Points [150, 0] } Line { Name "X In" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 Points [150, 0] } Line { Name "ASR Out" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 Points [150, 0] } Line { Name "ROM Out" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 Points [150, 0] } Line { Name "Corr Ld" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 Points [150, 0] } Line { Name "Corr Out" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 Points [150, 0] } Line { Name "ROM Addr" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 Points [150, 0] } } } Block { BlockType SubSystem Name "C3" SID "13372" Ports [4, 4] Position [520, 207, 590, 293] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskPromptString "Coefficients (all)|Sub-correlator Ind|Coef/correlator" MaskStyleString "edit,edit,edit" MaskVariables "h=@1;c_ind=@2;N=@3;" MaskTunableValueString "on,on,on" MaskCallbackString "||" MaskEnableString "on,on,on" MaskVisibilityString "on,on,on" MaskToolTipString "on,on,on" MaskInitialization "coef2 = h((c_ind*N+1) : (c_ind + 1)*N);" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "h|2|N" System { Name "C3" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "122" Block { BlockType Inport Name "x" SID "13373" Position [265, 263, 295, 277] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "vin" SID "13374" Position [270, 303, 300, 317] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "13375" Position [270, 458, 300, 472] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "13376" Position [270, 503, 300, 517] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "ASR" SID "13377" Ports [3, 1] Position [445, 260, 490, 320] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Addressable Shift Register" SourceType "Xilinx Addressable Shift Register Block" infoedit "Delay of configurable length. Any element in the delay line can be addressed and driven onto the" " output port.

Hardware notes: This block is implemented using SRL16s. If Virtex-4 or Spartan-3 device is " "used, multiple SRLC16s are cascaded together." infer_latency off depth "length(coef2)" initVector "[0]" en on dbl_ovrd off use_behavioral_HDL off Optimization "Resource" xl_use_area off xl_area "[1 0 0 2 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,401" block_type "addrsr" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,60,3,1,white,blue,0,f8ea6153,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 60 60 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 60 60 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[36.66 3" "6.66 42.66 36.66 42.66 42.66 42.66 36.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[30.66 30.66 36.66 " "36.66 30.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[24.66 24.66 30.66 30.66 24.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[18.66 18.66 24.66 18.66 24.66 24.66 18.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'addr');\ncolor('black');port_label('input',3," "'en');\ncolor('black');port_label('output',1,'q');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Delay" SID "13378" Ports [1, 1] Position [705, 441, 730, 469] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "25,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 " "17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33" " 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('blac" "k');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "13379" Position [210, 280, 300, 300] ZOrder -9 ShowName off GotoTag "ltsCorr_dAddr" TagVisibility "scoped" } Block { BlockType From Name "From1" SID "13380" Position [210, 340, 300, 360] ZOrder -9 ShowName off GotoTag "ltsCorr_cAddr" TagVisibility "scoped" } Block { BlockType From Name "From2" SID "13381" Position [210, 380, 300, 400] ZOrder -9 ShowName off GotoTag "ltsCorr_ld" TagVisibility "scoped" } Block { BlockType Reference Name "Gateway Out1" SID "13382" Ports [1, 1] Position [745, 615, 780, 625] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "13383" Ports [1, 1] Position [745, 630, 780, 640] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "13384" Ports [1, 1] Position [745, 645, 780, 655] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Ld" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "13385" Ports [1, 1] Position [745, 660, 780, 670] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "13386" Ports [1, 1] Position [745, 675, 780, 685] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "13387" Ports [1, 1] Position [745, 570, 780, 580] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X In" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "13388" Ports [1, 1] Position [745, 585, 780, 595] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "13389" Ports [1, 1] Position [745, 600, 780, 610] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X Vin" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType SubSystem Name "MAC" SID "13390" Ports [4, 2] Position [575, 279, 660, 376] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "MAC" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "a" SID "13391" Position [35, 143, 65, 157] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "coeff" SID "13392" Position [35, 108, 65, 122] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "ld" SID "13393" Position [35, 178, 65, 192] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "rst" SID "13394" Position [35, 233, 65, 247] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub" SID "13395" Ports [3, 1] Position [340, 113, 385, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition or Subtraction" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Signed (2's comp)" n_bits "long_cor_acc_n_bits" bin_pt "0" quantization "Truncate" overflow "Flag as error" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[2 0 0 4 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,344" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,3,1,white,blue,0,02f64c57,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('input',3,'su" "b');\ncolor('black');port_label('output',1,'\\bf{a \\pm b}','texmode','on');\nfprintf('','COMMENT: end icon text" "');\n" } Block { BlockType Reference Name "Gateway Out1" SID "13396" Ports [1, 1] Position [475, 450, 510, 460] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out2" SID "13397" Ports [1, 1] Position [475, 465, 510, 475] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out3" SID "13398" Ports [1, 1] Position [475, 480, 510, 490] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out6" SID "13399" Ports [1, 1] Position [475, 405, 510, 415] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out7" SID "13400" Ports [1, 1] Position [475, 420, 510, 430] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out8" SID "13401" Ports [1, 1] Position [475, 435, 510, 445] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "13402" Ports [2, 1] Position [345, 30, 385, 70] BlockMirror on NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,40,2,1,white,blue,0,140cc11c,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'" "q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "13403" Ports [2, 1] Position [465, 110, 495, 210] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,100,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 100 100 0 ],[0.77 0." "82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 100 100 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[54.44 " "54.44 58.44 54.44 58.44 58.44 58.44 54.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[50.44 50.44 54.44 54" ".44 50.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[46.44 46.44 50.44 50.44 46.44 ],[1 1 1 ])" ";\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[42.44 42.44 46.44 42.44 46.44 46.44 42.44 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\nco" "lor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc2" SID "13404" Ports [1, 1] Position [265, 143, 290, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc3" SID "13405" Ports [1, 1] Position [135, 178, 160, 192] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "yn" SID "13406" Position [545, 153, 575, 167] IconDisplay "Port number" } Block { BlockType Outport Name "accrm" SID "13407" Position [520, 288, 550, 302] Port "2" IconDisplay "Port number" } Line { SrcBlock "rst" SrcPort 1 Points [90, 0] Branch { Points [0, 215] DstBlock "Gateway Out1" DstPort 1 } Branch { Points [255, 0; 0, -180] DstBlock "Register1" DstPort 2 } } Line { SrcBlock "Gateway Out3" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out2" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out1" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out6" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out7" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out8" SrcPort 1 Points [50, 0] } Line { SrcBlock "a" SrcPort 1 Points [140, 0] Branch { Points [0, 275] DstBlock "Gateway Out7" DstPort 1 } Branch { DstBlock "bc2" DstPort 1 } } Line { SrcBlock "AddSub" SrcPort 1 Points [0, 0; 5, 0] Branch { Points [0, 305] DstBlock "Gateway Out8" DstPort 1 } Branch { Points [40, 0] Branch { Points [0, 160] DstBlock "accrm" DstPort 1 } Branch { Points [0, -95] DstBlock "Register1" DstPort 1 } Branch { DstBlock "Register2" DstPort 1 } } } Line { SrcBlock "Register2" SrcPort 1 Points [15, 0] Branch { Points [0, 50; 110, 0; 0, 385; -260, 0; 0, -110] DstBlock "Gateway Out3" DstPort 1 } Branch { DstBlock "yn" DstPort 1 } } Line { SrcBlock "Register1" SrcPort 1 Points [-15, 0] DstBlock "AddSub" DstPort 1 } Line { SrcBlock "ld" SrcPort 1 Points [45, 0] Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } Branch { DstBlock "bc3" DstPort 1 } } Line { SrcBlock "bc3" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "bc2" SrcPort 1 DstBlock "AddSub" DstPort 3 } Line { SrcBlock "coeff" SrcPort 1 Points [95, 0; 0, 20; 50, 0] Branch { Points [0, 275] DstBlock "Gateway Out6" DstPort 1 } Branch { DstBlock "AddSub" DstPort 2 } } } } Block { BlockType Reference Name "ROM" SID "13408" Ports [1, 1] Position [440, 328, 490, 372] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/ROM" SourceType "Xilinx Single Port Read-Only Memory Block" depth "length(coef2)" initVector "coef2" distributed_mem "Distributed memory" rst off init_reg "0" en off latency "1" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "longCorr_coef_nbits" bin_pt "longCorr_coef_bp" preci_type "Single" exp_width "8" frac_width "24" dbl_ovrd off optimize "Area" use_rpm off xl_use_area off xl_area "[1 1 0 1 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,308" block_type "sprom" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,44,1,1,white,blue,0,bbc23d60,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 44 44 0 ]);\npatch([11.65 20.32 26.32 32.32 38.32 26.32 17.65 11.65 ],[28.66" " 28.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([17.65 26.32 20.32 11.65 17.65 ],[22.66 22.66 28." "66 28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([11.65 20.32 26.32 17.65 11.65 ],[16.66 16.66 22.66 22.66 16.66 ]" ",[1 1 1 ]);\npatch([17.65 38.32 32.32 26.32 20.32 11.65 17.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'addr');\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end" " icon text');\n" } Block { BlockType Outport Name "x_dly" SID "13409" Position [790, 178, 820, 192] IconDisplay "Port number" } Block { BlockType Outport Name "x_dly_vout" SID "13410" Position [790, 223, 820, 237] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "y" SID "13411" Position [790, 293, 820, 307] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "y_vout" SID "13412" Position [785, 448, 815, 462] Port "4" IconDisplay "Port number" } Line { Name "ROM Addr" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 Points [150, 0] } Line { Name "Corr Out" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 Points [150, 0] } Line { Name "Corr Ld" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 Points [150, 0] } Line { Name "ROM Out" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 Points [150, 0] } Line { Name "ASR Out" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 Points [150, 0] } Line { Name "X In" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 Points [150, 0] } Line { Name "ASR Addr" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 Points [150, 0] } Line { Name "X Vin" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 Points [150, 0] } Line { SrcBlock "Delay" SrcPort 1 DstBlock "y_vout" DstPort 1 } Line { SrcBlock "vin" SrcPort 1 Points [25, 0] Branch { Points [0, -80] DstBlock "x_dly_vout" DstPort 1 } Branch { Points [0, 100] Branch { Points [230, 0] DstBlock "MAC" DstPort 4 } Branch { Points [0, 195] DstBlock "Gateway Out8" DstPort 1 } } Branch { DstBlock "ASR" DstPort 3 } } Line { SrcBlock "x" SrcPort 1 Points [100, 0] Branch { Points [0, 305] DstBlock "Gateway Out6" DstPort 1 } Branch { DstBlock "ASR" DstPort 1 } } Line { SrcBlock "From" SrcPort 1 Points [90, 0] Branch { Points [0, 300] DstBlock "Gateway Out7" DstPort 1 } Branch { DstBlock "ASR" DstPort 2 } } Line { SrcBlock "From1" SrcPort 1 Points [5, 0] Branch { Points [0, 330] DstBlock "Gateway Out5" DstPort 1 } Branch { DstBlock "ROM" DstPort 1 } } Line { SrcBlock "ASR" SrcPort 1 Points [35, 0] Branch { Points [0, 330] DstBlock "Gateway Out1" DstPort 1 } Branch { Points [0, -105] DstBlock "x_dly" DstPort 1 } Branch { DstBlock "MAC" DstPort 1 } } Line { SrcBlock "MAC" SrcPort 1 Points [0, -5; 15, 0] Branch { Points [0, 365] DstBlock "Gateway Out4" DstPort 1 } Branch { DstBlock "y" DstPort 1 } } Line { SrcBlock "ROM" SrcPort 1 Points [5, 0] Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } Branch { Points [0, -35] DstBlock "MAC" DstPort 2 } } Line { SrcBlock "From2" SrcPort 1 Points [145, 0] Branch { Points [0, 260] DstBlock "Gateway Out3" DstPort 1 } Branch { Points [90, 0] Branch { Points [0, 65] DstBlock "Delay" DstPort 1 } Branch { Points [0, -50] Branch { Points [0, -90; 160, 0] } Branch { DstBlock "MAC" DstPort 3 } } } } } } Block { BlockType SubSystem Name "C4" SID "13413" Ports [4, 4] Position [630, 207, 700, 293] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskPromptString "Coefficients (all)|Sub-correlator Ind|Coef/correlator" MaskStyleString "edit,edit,edit" MaskVariables "h=@1;c_ind=@2;N=@3;" MaskTunableValueString "on,on,on" MaskCallbackString "||" MaskEnableString "on,on,on" MaskVisibilityString "on,on,on" MaskToolTipString "on,on,on" MaskInitialization "coef2 = h((c_ind*N+1) : (c_ind + 1)*N);" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "h|3|N" System { Name "C4" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "122" Block { BlockType Inport Name "x" SID "13414" Position [265, 263, 295, 277] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "vin" SID "13415" Position [270, 303, 300, 317] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "13416" Position [270, 458, 300, 472] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "13417" Position [270, 503, 300, 517] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "ASR" SID "13418" Ports [3, 1] Position [445, 260, 490, 320] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Addressable Shift Register" SourceType "Xilinx Addressable Shift Register Block" infoedit "Delay of configurable length. Any element in the delay line can be addressed and driven onto the" " output port.

Hardware notes: This block is implemented using SRL16s. If Virtex-4 or Spartan-3 device is " "used, multiple SRLC16s are cascaded together." infer_latency off depth "length(coef2)" initVector "[0]" en on dbl_ovrd off use_behavioral_HDL off Optimization "Resource" xl_use_area off xl_area "[1 0 0 2 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,401" block_type "addrsr" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,60,3,1,white,blue,0,f8ea6153,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 60 60 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 60 60 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[36.66 3" "6.66 42.66 36.66 42.66 42.66 42.66 36.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[30.66 30.66 36.66 " "36.66 30.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[24.66 24.66 30.66 30.66 24.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[18.66 18.66 24.66 18.66 24.66 24.66 18.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'addr');\ncolor('black');port_label('input',3," "'en');\ncolor('black');port_label('output',1,'q');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Delay" SID "13419" Ports [1, 1] Position [705, 441, 730, 469] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "25,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 " "17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33" " 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('blac" "k');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "13420" Position [210, 280, 300, 300] ZOrder -9 ShowName off GotoTag "ltsCorr_dAddr" TagVisibility "scoped" } Block { BlockType From Name "From1" SID "13421" Position [210, 340, 300, 360] ZOrder -9 ShowName off GotoTag "ltsCorr_cAddr" TagVisibility "scoped" } Block { BlockType From Name "From2" SID "13422" Position [210, 380, 300, 400] ZOrder -9 ShowName off GotoTag "ltsCorr_ld" TagVisibility "scoped" } Block { BlockType Reference Name "Gateway Out1" SID "13423" Ports [1, 1] Position [745, 615, 780, 625] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "13424" Ports [1, 1] Position [745, 630, 780, 640] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "13425" Ports [1, 1] Position [745, 645, 780, 655] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Ld" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "13426" Ports [1, 1] Position [745, 660, 780, 670] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "13427" Ports [1, 1] Position [745, 675, 780, 685] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "13428" Ports [1, 1] Position [745, 570, 780, 580] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X In" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "13429" Ports [1, 1] Position [745, 585, 780, 595] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "13430" Ports [1, 1] Position [745, 600, 780, 610] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X Vin" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType SubSystem Name "MAC" SID "13431" Ports [4, 2] Position [575, 279, 660, 376] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "MAC" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "a" SID "13432" Position [35, 143, 65, 157] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "coeff" SID "13433" Position [35, 108, 65, 122] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "ld" SID "13434" Position [35, 178, 65, 192] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "rst" SID "13435" Position [35, 233, 65, 247] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub" SID "13436" Ports [3, 1] Position [340, 113, 385, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition or Subtraction" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Signed (2's comp)" n_bits "long_cor_acc_n_bits" bin_pt "0" quantization "Truncate" overflow "Flag as error" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[2 0 0 4 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,344" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,3,1,white,blue,0,02f64c57,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('input',3,'su" "b');\ncolor('black');port_label('output',1,'\\bf{a \\pm b}','texmode','on');\nfprintf('','COMMENT: end icon text" "');\n" } Block { BlockType Reference Name "Gateway Out1" SID "13437" Ports [1, 1] Position [475, 450, 510, 460] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out2" SID "13438" Ports [1, 1] Position [475, 465, 510, 475] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out3" SID "13439" Ports [1, 1] Position [475, 480, 510, 490] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out6" SID "13440" Ports [1, 1] Position [475, 405, 510, 415] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out7" SID "13441" Ports [1, 1] Position [475, 420, 510, 430] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out8" SID "13442" Ports [1, 1] Position [475, 435, 510, 445] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "13443" Ports [2, 1] Position [345, 30, 385, 70] BlockMirror on NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,40,2,1,white,blue,0,140cc11c,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'" "q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "13444" Ports [2, 1] Position [465, 110, 495, 210] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,100,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 100 100 0 ],[0.77 0." "82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 100 100 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[54.44 " "54.44 58.44 54.44 58.44 58.44 58.44 54.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[50.44 50.44 54.44 54" ".44 50.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[46.44 46.44 50.44 50.44 46.44 ],[1 1 1 ])" ";\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[42.44 42.44 46.44 42.44 46.44 46.44 42.44 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\nco" "lor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc2" SID "13445" Ports [1, 1] Position [265, 143, 290, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc3" SID "13446" Ports [1, 1] Position [135, 178, 160, 192] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "yn" SID "13447" Position [545, 153, 575, 167] IconDisplay "Port number" } Block { BlockType Outport Name "accrm" SID "13448" Position [520, 288, 550, 302] Port "2" IconDisplay "Port number" } Line { SrcBlock "coeff" SrcPort 1 Points [95, 0; 0, 20; 50, 0] Branch { DstBlock "AddSub" DstPort 2 } Branch { Points [0, 275] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "bc2" SrcPort 1 DstBlock "AddSub" DstPort 3 } Line { SrcBlock "bc3" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "ld" SrcPort 1 Points [45, 0] Branch { DstBlock "bc3" DstPort 1 } Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "Register1" SrcPort 1 Points [-15, 0] DstBlock "AddSub" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 Points [15, 0] Branch { DstBlock "yn" DstPort 1 } Branch { Points [0, 50; 110, 0; 0, 385; -260, 0; 0, -110] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "AddSub" SrcPort 1 Points [0, 0; 5, 0] Branch { Points [40, 0] Branch { DstBlock "Register2" DstPort 1 } Branch { Points [0, -95] DstBlock "Register1" DstPort 1 } Branch { Points [0, 160] DstBlock "accrm" DstPort 1 } } Branch { Points [0, 305] DstBlock "Gateway Out8" DstPort 1 } } Line { SrcBlock "a" SrcPort 1 Points [140, 0] Branch { DstBlock "bc2" DstPort 1 } Branch { Points [0, 275] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "Gateway Out8" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out7" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out6" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out1" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out2" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out3" SrcPort 1 Points [50, 0] } Line { SrcBlock "rst" SrcPort 1 Points [90, 0] Branch { Points [255, 0; 0, -180] DstBlock "Register1" DstPort 2 } Branch { Points [0, 215] DstBlock "Gateway Out1" DstPort 1 } } } } Block { BlockType Reference Name "ROM" SID "13449" Ports [1, 1] Position [440, 328, 490, 372] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/ROM" SourceType "Xilinx Single Port Read-Only Memory Block" depth "length(coef2)" initVector "coef2" distributed_mem "Distributed memory" rst off init_reg "0" en off latency "1" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "longCorr_coef_nbits" bin_pt "longCorr_coef_bp" preci_type "Single" exp_width "8" frac_width "24" dbl_ovrd off optimize "Area" use_rpm off xl_use_area off xl_area "[1 1 0 1 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,308" block_type "sprom" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,44,1,1,white,blue,0,bbc23d60,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 44 44 0 ]);\npatch([11.65 20.32 26.32 32.32 38.32 26.32 17.65 11.65 ],[28.66" " 28.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([17.65 26.32 20.32 11.65 17.65 ],[22.66 22.66 28." "66 28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([11.65 20.32 26.32 17.65 11.65 ],[16.66 16.66 22.66 22.66 16.66 ]" ",[1 1 1 ]);\npatch([17.65 38.32 32.32 26.32 20.32 11.65 17.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'addr');\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end" " icon text');\n" } Block { BlockType Outport Name "x_dly" SID "13450" Position [790, 178, 820, 192] IconDisplay "Port number" } Block { BlockType Outport Name "x_dly_vout" SID "13451" Position [790, 223, 820, 237] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "y" SID "13452" Position [790, 293, 820, 307] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "y_vout" SID "13453" Position [785, 448, 815, 462] Port "4" IconDisplay "Port number" } Line { SrcBlock "From2" SrcPort 1 Points [145, 0] Branch { Points [90, 0] Branch { Points [0, -50] Branch { DstBlock "MAC" DstPort 3 } Branch { Points [0, -90; 160, 0] } } Branch { Points [0, 65] DstBlock "Delay" DstPort 1 } } Branch { Points [0, 260] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "ROM" SrcPort 1 Points [5, 0] Branch { Points [0, -35] DstBlock "MAC" DstPort 2 } Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "MAC" SrcPort 1 Points [0, -5; 15, 0] Branch { DstBlock "y" DstPort 1 } Branch { Points [0, 365] DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "ASR" SrcPort 1 Points [35, 0] Branch { DstBlock "MAC" DstPort 1 } Branch { Points [0, -105] DstBlock "x_dly" DstPort 1 } Branch { Points [0, 330] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "From1" SrcPort 1 Points [5, 0] Branch { DstBlock "ROM" DstPort 1 } Branch { Points [0, 330] DstBlock "Gateway Out5" DstPort 1 } } Line { SrcBlock "From" SrcPort 1 Points [90, 0] Branch { DstBlock "ASR" DstPort 2 } Branch { Points [0, 300] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "x" SrcPort 1 Points [100, 0] Branch { DstBlock "ASR" DstPort 1 } Branch { Points [0, 305] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "vin" SrcPort 1 Points [25, 0] Branch { DstBlock "ASR" DstPort 3 } Branch { Points [0, 100] Branch { Points [0, 195] DstBlock "Gateway Out8" DstPort 1 } Branch { Points [230, 0] DstBlock "MAC" DstPort 4 } } Branch { Points [0, -80] DstBlock "x_dly_vout" DstPort 1 } } Line { SrcBlock "Delay" SrcPort 1 DstBlock "y_vout" DstPort 1 } Line { Name "X Vin" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 Points [150, 0] } Line { Name "ASR Addr" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 Points [150, 0] } Line { Name "X In" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 Points [150, 0] } Line { Name "ASR Out" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 Points [150, 0] } Line { Name "ROM Out" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 Points [150, 0] } Line { Name "Corr Ld" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 Points [150, 0] } Line { Name "Corr Out" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 Points [150, 0] } Line { Name "ROM Addr" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 Points [150, 0] } } } Block { BlockType SubSystem Name "C5" SID "13454" Ports [4, 4] Position [740, 207, 810, 293] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskPromptString "Coefficients (all)|Sub-correlator Ind|Coef/correlator" MaskStyleString "edit,edit,edit" MaskVariables "h=@1;c_ind=@2;N=@3;" MaskTunableValueString "on,on,on" MaskCallbackString "||" MaskEnableString "on,on,on" MaskVisibilityString "on,on,on" MaskToolTipString "on,on,on" MaskInitialization "coef2 = h((c_ind*N+1) : (c_ind + 1)*N);" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "h|4|N" System { Name "C5" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "122" Block { BlockType Inport Name "x" SID "13455" Position [265, 263, 295, 277] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "vin" SID "13456" Position [270, 303, 300, 317] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "13457" Position [270, 458, 300, 472] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "13458" Position [270, 503, 300, 517] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "ASR" SID "13459" Ports [3, 1] Position [445, 260, 490, 320] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Addressable Shift Register" SourceType "Xilinx Addressable Shift Register Block" infoedit "Delay of configurable length. Any element in the delay line can be addressed and driven onto the" " output port.

Hardware notes: This block is implemented using SRL16s. If Virtex-4 or Spartan-3 device is " "used, multiple SRLC16s are cascaded together." infer_latency off depth "length(coef2)" initVector "[0]" en on dbl_ovrd off use_behavioral_HDL off Optimization "Resource" xl_use_area off xl_area "[1 0 0 2 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,401" block_type "addrsr" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,60,3,1,white,blue,0,f8ea6153,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 60 60 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 60 60 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[36.66 3" "6.66 42.66 36.66 42.66 42.66 42.66 36.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[30.66 30.66 36.66 " "36.66 30.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[24.66 24.66 30.66 30.66 24.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[18.66 18.66 24.66 18.66 24.66 24.66 18.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'addr');\ncolor('black');port_label('input',3," "'en');\ncolor('black');port_label('output',1,'q');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Delay" SID "13460" Ports [1, 1] Position [705, 441, 730, 469] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "25,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 " "17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33" " 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('blac" "k');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "13461" Position [210, 280, 300, 300] ZOrder -9 ShowName off GotoTag "ltsCorr_dAddr" TagVisibility "scoped" } Block { BlockType From Name "From1" SID "13462" Position [210, 340, 300, 360] ZOrder -9 ShowName off GotoTag "ltsCorr_cAddr" TagVisibility "scoped" } Block { BlockType From Name "From2" SID "13463" Position [210, 380, 300, 400] ZOrder -9 ShowName off GotoTag "ltsCorr_ld" TagVisibility "scoped" } Block { BlockType Reference Name "Gateway Out1" SID "13464" Ports [1, 1] Position [745, 615, 780, 625] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "13465" Ports [1, 1] Position [745, 630, 780, 640] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "13466" Ports [1, 1] Position [745, 645, 780, 655] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Ld" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "13467" Ports [1, 1] Position [745, 660, 780, 670] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "13468" Ports [1, 1] Position [745, 675, 780, 685] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "13469" Ports [1, 1] Position [745, 570, 780, 580] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X In" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "13470" Ports [1, 1] Position [745, 585, 780, 595] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "13471" Ports [1, 1] Position [745, 600, 780, 610] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X Vin" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType SubSystem Name "MAC" SID "13472" Ports [4, 2] Position [575, 279, 660, 376] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "MAC" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "a" SID "13473" Position [35, 143, 65, 157] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "coeff" SID "13474" Position [35, 108, 65, 122] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "ld" SID "13475" Position [35, 178, 65, 192] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "rst" SID "13476" Position [35, 233, 65, 247] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub" SID "13477" Ports [3, 1] Position [340, 113, 385, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition or Subtraction" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Signed (2's comp)" n_bits "long_cor_acc_n_bits" bin_pt "0" quantization "Truncate" overflow "Flag as error" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[2 0 0 4 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,344" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,3,1,white,blue,0,02f64c57,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('input',3,'su" "b');\ncolor('black');port_label('output',1,'\\bf{a \\pm b}','texmode','on');\nfprintf('','COMMENT: end icon text" "');\n" } Block { BlockType Reference Name "Gateway Out1" SID "13478" Ports [1, 1] Position [475, 450, 510, 460] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out2" SID "13479" Ports [1, 1] Position [475, 465, 510, 475] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out3" SID "13480" Ports [1, 1] Position [475, 480, 510, 490] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out6" SID "13481" Ports [1, 1] Position [475, 405, 510, 415] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out7" SID "13482" Ports [1, 1] Position [475, 420, 510, 430] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out8" SID "13483" Ports [1, 1] Position [475, 435, 510, 445] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "13484" Ports [2, 1] Position [345, 30, 385, 70] BlockMirror on NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,40,2,1,white,blue,0,140cc11c,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'" "q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "13485" Ports [2, 1] Position [465, 110, 495, 210] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,100,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 100 100 0 ],[0.77 0." "82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 100 100 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[54.44 " "54.44 58.44 54.44 58.44 58.44 58.44 54.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[50.44 50.44 54.44 54" ".44 50.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[46.44 46.44 50.44 50.44 46.44 ],[1 1 1 ])" ";\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[42.44 42.44 46.44 42.44 46.44 46.44 42.44 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\nco" "lor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc2" SID "13486" Ports [1, 1] Position [265, 143, 290, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc3" SID "13487" Ports [1, 1] Position [135, 178, 160, 192] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "yn" SID "13488" Position [545, 153, 575, 167] IconDisplay "Port number" } Block { BlockType Outport Name "accrm" SID "13489" Position [520, 288, 550, 302] Port "2" IconDisplay "Port number" } Line { SrcBlock "rst" SrcPort 1 Points [90, 0] Branch { Points [0, 215] DstBlock "Gateway Out1" DstPort 1 } Branch { Points [255, 0; 0, -180] DstBlock "Register1" DstPort 2 } } Line { SrcBlock "Gateway Out3" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out2" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out1" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out6" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out7" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out8" SrcPort 1 Points [50, 0] } Line { SrcBlock "a" SrcPort 1 Points [140, 0] Branch { Points [0, 275] DstBlock "Gateway Out7" DstPort 1 } Branch { DstBlock "bc2" DstPort 1 } } Line { SrcBlock "AddSub" SrcPort 1 Points [0, 0; 5, 0] Branch { Points [0, 305] DstBlock "Gateway Out8" DstPort 1 } Branch { Points [40, 0] Branch { Points [0, 160] DstBlock "accrm" DstPort 1 } Branch { Points [0, -95] DstBlock "Register1" DstPort 1 } Branch { DstBlock "Register2" DstPort 1 } } } Line { SrcBlock "Register2" SrcPort 1 Points [15, 0] Branch { Points [0, 50; 110, 0; 0, 385; -260, 0; 0, -110] DstBlock "Gateway Out3" DstPort 1 } Branch { DstBlock "yn" DstPort 1 } } Line { SrcBlock "Register1" SrcPort 1 Points [-15, 0] DstBlock "AddSub" DstPort 1 } Line { SrcBlock "ld" SrcPort 1 Points [45, 0] Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } Branch { DstBlock "bc3" DstPort 1 } } Line { SrcBlock "bc3" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "bc2" SrcPort 1 DstBlock "AddSub" DstPort 3 } Line { SrcBlock "coeff" SrcPort 1 Points [95, 0; 0, 20; 50, 0] Branch { Points [0, 275] DstBlock "Gateway Out6" DstPort 1 } Branch { DstBlock "AddSub" DstPort 2 } } } } Block { BlockType Reference Name "ROM" SID "13490" Ports [1, 1] Position [440, 328, 490, 372] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/ROM" SourceType "Xilinx Single Port Read-Only Memory Block" depth "length(coef2)" initVector "coef2" distributed_mem "Distributed memory" rst off init_reg "0" en off latency "1" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "longCorr_coef_nbits" bin_pt "longCorr_coef_bp" preci_type "Single" exp_width "8" frac_width "24" dbl_ovrd off optimize "Area" use_rpm off xl_use_area off xl_area "[1 1 0 1 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,308" block_type "sprom" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,44,1,1,white,blue,0,bbc23d60,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 44 44 0 ]);\npatch([11.65 20.32 26.32 32.32 38.32 26.32 17.65 11.65 ],[28.66" " 28.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([17.65 26.32 20.32 11.65 17.65 ],[22.66 22.66 28." "66 28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([11.65 20.32 26.32 17.65 11.65 ],[16.66 16.66 22.66 22.66 16.66 ]" ",[1 1 1 ]);\npatch([17.65 38.32 32.32 26.32 20.32 11.65 17.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'addr');\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end" " icon text');\n" } Block { BlockType Outport Name "x_dly" SID "13491" Position [790, 178, 820, 192] IconDisplay "Port number" } Block { BlockType Outport Name "x_dly_vout" SID "13492" Position [790, 223, 820, 237] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "y" SID "13493" Position [790, 293, 820, 307] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "y_vout" SID "13494" Position [785, 448, 815, 462] Port "4" IconDisplay "Port number" } Line { Name "ROM Addr" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 Points [150, 0] } Line { Name "Corr Out" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 Points [150, 0] } Line { Name "Corr Ld" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 Points [150, 0] } Line { Name "ROM Out" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 Points [150, 0] } Line { Name "ASR Out" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 Points [150, 0] } Line { Name "X In" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 Points [150, 0] } Line { Name "ASR Addr" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 Points [150, 0] } Line { Name "X Vin" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 Points [150, 0] } Line { SrcBlock "Delay" SrcPort 1 DstBlock "y_vout" DstPort 1 } Line { SrcBlock "vin" SrcPort 1 Points [25, 0] Branch { Points [0, -80] DstBlock "x_dly_vout" DstPort 1 } Branch { Points [0, 100] Branch { Points [230, 0] DstBlock "MAC" DstPort 4 } Branch { Points [0, 195] DstBlock "Gateway Out8" DstPort 1 } } Branch { DstBlock "ASR" DstPort 3 } } Line { SrcBlock "x" SrcPort 1 Points [100, 0] Branch { Points [0, 305] DstBlock "Gateway Out6" DstPort 1 } Branch { DstBlock "ASR" DstPort 1 } } Line { SrcBlock "From" SrcPort 1 Points [90, 0] Branch { Points [0, 300] DstBlock "Gateway Out7" DstPort 1 } Branch { DstBlock "ASR" DstPort 2 } } Line { SrcBlock "From1" SrcPort 1 Points [5, 0] Branch { Points [0, 330] DstBlock "Gateway Out5" DstPort 1 } Branch { DstBlock "ROM" DstPort 1 } } Line { SrcBlock "ASR" SrcPort 1 Points [35, 0] Branch { Points [0, 330] DstBlock "Gateway Out1" DstPort 1 } Branch { Points [0, -105] DstBlock "x_dly" DstPort 1 } Branch { DstBlock "MAC" DstPort 1 } } Line { SrcBlock "MAC" SrcPort 1 Points [0, -5; 15, 0] Branch { Points [0, 365] DstBlock "Gateway Out4" DstPort 1 } Branch { DstBlock "y" DstPort 1 } } Line { SrcBlock "ROM" SrcPort 1 Points [5, 0] Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } Branch { Points [0, -35] DstBlock "MAC" DstPort 2 } } Line { SrcBlock "From2" SrcPort 1 Points [145, 0] Branch { Points [0, 260] DstBlock "Gateway Out3" DstPort 1 } Branch { Points [90, 0] Branch { Points [0, 65] DstBlock "Delay" DstPort 1 } Branch { Points [0, -50] Branch { Points [0, -90; 160, 0] } Branch { DstBlock "MAC" DstPort 3 } } } } } } Block { BlockType SubSystem Name "C6" SID "13495" Ports [4, 4] Position [845, 207, 915, 293] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskPromptString "Coefficients (all)|Sub-correlator Ind|Coef/correlator" MaskStyleString "edit,edit,edit" MaskVariables "h=@1;c_ind=@2;N=@3;" MaskTunableValueString "on,on,on" MaskCallbackString "||" MaskEnableString "on,on,on" MaskVisibilityString "on,on,on" MaskToolTipString "on,on,on" MaskInitialization "coef2 = h((c_ind*N+1) : (c_ind + 1)*N);" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "h|5|N" System { Name "C6" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "122" Block { BlockType Inport Name "x" SID "13496" Position [265, 263, 295, 277] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "vin" SID "13497" Position [270, 303, 300, 317] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "13498" Position [270, 458, 300, 472] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "13499" Position [270, 503, 300, 517] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "ASR" SID "13500" Ports [3, 1] Position [445, 260, 490, 320] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Addressable Shift Register" SourceType "Xilinx Addressable Shift Register Block" infoedit "Delay of configurable length. Any element in the delay line can be addressed and driven onto the" " output port.

Hardware notes: This block is implemented using SRL16s. If Virtex-4 or Spartan-3 device is " "used, multiple SRLC16s are cascaded together." infer_latency off depth "length(coef2)" initVector "[0]" en on dbl_ovrd off use_behavioral_HDL off Optimization "Resource" xl_use_area off xl_area "[1 0 0 2 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,401" block_type "addrsr" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,60,3,1,white,blue,0,f8ea6153,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 60 60 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 60 60 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[36.66 3" "6.66 42.66 36.66 42.66 42.66 42.66 36.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[30.66 30.66 36.66 " "36.66 30.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[24.66 24.66 30.66 30.66 24.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[18.66 18.66 24.66 18.66 24.66 24.66 18.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'addr');\ncolor('black');port_label('input',3," "'en');\ncolor('black');port_label('output',1,'q');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Delay" SID "13501" Ports [1, 1] Position [705, 441, 730, 469] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "25,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 " "17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33" " 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('blac" "k');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "13502" Position [210, 280, 300, 300] ZOrder -9 ShowName off GotoTag "ltsCorr_dAddr" TagVisibility "scoped" } Block { BlockType From Name "From1" SID "13503" Position [210, 340, 300, 360] ZOrder -9 ShowName off GotoTag "ltsCorr_cAddr" TagVisibility "scoped" } Block { BlockType From Name "From2" SID "13504" Position [210, 380, 300, 400] ZOrder -9 ShowName off GotoTag "ltsCorr_ld" TagVisibility "scoped" } Block { BlockType Reference Name "Gateway Out1" SID "13505" Ports [1, 1] Position [745, 615, 780, 625] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "13506" Ports [1, 1] Position [745, 630, 780, 640] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "13507" Ports [1, 1] Position [745, 645, 780, 655] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Ld" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "13508" Ports [1, 1] Position [745, 660, 780, 670] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "13509" Ports [1, 1] Position [745, 675, 780, 685] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "13510" Ports [1, 1] Position [745, 570, 780, 580] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X In" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "13511" Ports [1, 1] Position [745, 585, 780, 595] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "13512" Ports [1, 1] Position [745, 600, 780, 610] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X Vin" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType SubSystem Name "MAC" SID "13513" Ports [4, 2] Position [575, 279, 660, 376] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "MAC" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "a" SID "13514" Position [35, 143, 65, 157] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "coeff" SID "13515" Position [35, 108, 65, 122] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "ld" SID "13516" Position [35, 178, 65, 192] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "rst" SID "13517" Position [35, 233, 65, 247] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub" SID "13518" Ports [3, 1] Position [340, 113, 385, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition or Subtraction" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Signed (2's comp)" n_bits "long_cor_acc_n_bits" bin_pt "0" quantization "Truncate" overflow "Flag as error" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[2 0 0 4 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,344" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,3,1,white,blue,0,02f64c57,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('input',3,'su" "b');\ncolor('black');port_label('output',1,'\\bf{a \\pm b}','texmode','on');\nfprintf('','COMMENT: end icon text" "');\n" } Block { BlockType Reference Name "Gateway Out1" SID "13519" Ports [1, 1] Position [475, 450, 510, 460] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out2" SID "13520" Ports [1, 1] Position [475, 465, 510, 475] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out3" SID "13521" Ports [1, 1] Position [475, 480, 510, 490] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out6" SID "13522" Ports [1, 1] Position [475, 405, 510, 415] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out7" SID "13523" Ports [1, 1] Position [475, 420, 510, 430] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out8" SID "13524" Ports [1, 1] Position [475, 435, 510, 445] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "13525" Ports [2, 1] Position [345, 30, 385, 70] BlockMirror on NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,40,2,1,white,blue,0,140cc11c,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'" "q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "13526" Ports [2, 1] Position [465, 110, 495, 210] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,100,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 100 100 0 ],[0.77 0." "82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 100 100 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[54.44 " "54.44 58.44 54.44 58.44 58.44 58.44 54.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[50.44 50.44 54.44 54" ".44 50.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[46.44 46.44 50.44 50.44 46.44 ],[1 1 1 ])" ";\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[42.44 42.44 46.44 42.44 46.44 46.44 42.44 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\nco" "lor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc2" SID "13527" Ports [1, 1] Position [265, 143, 290, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc3" SID "13528" Ports [1, 1] Position [135, 178, 160, 192] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "yn" SID "13529" Position [545, 153, 575, 167] IconDisplay "Port number" } Block { BlockType Outport Name "accrm" SID "13530" Position [520, 288, 550, 302] Port "2" IconDisplay "Port number" } Line { SrcBlock "coeff" SrcPort 1 Points [95, 0; 0, 20; 50, 0] Branch { DstBlock "AddSub" DstPort 2 } Branch { Points [0, 275] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "bc2" SrcPort 1 DstBlock "AddSub" DstPort 3 } Line { SrcBlock "bc3" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "ld" SrcPort 1 Points [45, 0] Branch { DstBlock "bc3" DstPort 1 } Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "Register1" SrcPort 1 Points [-15, 0] DstBlock "AddSub" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 Points [15, 0] Branch { DstBlock "yn" DstPort 1 } Branch { Points [0, 50; 110, 0; 0, 385; -260, 0; 0, -110] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "AddSub" SrcPort 1 Points [0, 0; 5, 0] Branch { Points [40, 0] Branch { DstBlock "Register2" DstPort 1 } Branch { Points [0, -95] DstBlock "Register1" DstPort 1 } Branch { Points [0, 160] DstBlock "accrm" DstPort 1 } } Branch { Points [0, 305] DstBlock "Gateway Out8" DstPort 1 } } Line { SrcBlock "a" SrcPort 1 Points [140, 0] Branch { DstBlock "bc2" DstPort 1 } Branch { Points [0, 275] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "Gateway Out8" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out7" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out6" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out1" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out2" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out3" SrcPort 1 Points [50, 0] } Line { SrcBlock "rst" SrcPort 1 Points [90, 0] Branch { Points [255, 0; 0, -180] DstBlock "Register1" DstPort 2 } Branch { Points [0, 215] DstBlock "Gateway Out1" DstPort 1 } } } } Block { BlockType Reference Name "ROM" SID "13531" Ports [1, 1] Position [440, 328, 490, 372] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/ROM" SourceType "Xilinx Single Port Read-Only Memory Block" depth "length(coef2)" initVector "coef2" distributed_mem "Distributed memory" rst off init_reg "0" en off latency "1" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "longCorr_coef_nbits" bin_pt "longCorr_coef_bp" preci_type "Single" exp_width "8" frac_width "24" dbl_ovrd off optimize "Area" use_rpm off xl_use_area off xl_area "[1 1 0 1 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,308" block_type "sprom" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,44,1,1,white,blue,0,bbc23d60,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 44 44 0 ]);\npatch([11.65 20.32 26.32 32.32 38.32 26.32 17.65 11.65 ],[28.66" " 28.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([17.65 26.32 20.32 11.65 17.65 ],[22.66 22.66 28." "66 28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([11.65 20.32 26.32 17.65 11.65 ],[16.66 16.66 22.66 22.66 16.66 ]" ",[1 1 1 ]);\npatch([17.65 38.32 32.32 26.32 20.32 11.65 17.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'addr');\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end" " icon text');\n" } Block { BlockType Outport Name "x_dly" SID "13532" Position [790, 178, 820, 192] IconDisplay "Port number" } Block { BlockType Outport Name "x_dly_vout" SID "13533" Position [790, 223, 820, 237] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "y" SID "13534" Position [790, 293, 820, 307] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "y_vout" SID "13535" Position [785, 448, 815, 462] Port "4" IconDisplay "Port number" } Line { SrcBlock "From2" SrcPort 1 Points [145, 0] Branch { Points [90, 0] Branch { Points [0, -50] Branch { DstBlock "MAC" DstPort 3 } Branch { Points [0, -90; 160, 0] } } Branch { Points [0, 65] DstBlock "Delay" DstPort 1 } } Branch { Points [0, 260] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "ROM" SrcPort 1 Points [5, 0] Branch { Points [0, -35] DstBlock "MAC" DstPort 2 } Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "MAC" SrcPort 1 Points [0, -5; 15, 0] Branch { DstBlock "y" DstPort 1 } Branch { Points [0, 365] DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "ASR" SrcPort 1 Points [35, 0] Branch { DstBlock "MAC" DstPort 1 } Branch { Points [0, -105] DstBlock "x_dly" DstPort 1 } Branch { Points [0, 330] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "From1" SrcPort 1 Points [5, 0] Branch { DstBlock "ROM" DstPort 1 } Branch { Points [0, 330] DstBlock "Gateway Out5" DstPort 1 } } Line { SrcBlock "From" SrcPort 1 Points [90, 0] Branch { DstBlock "ASR" DstPort 2 } Branch { Points [0, 300] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "x" SrcPort 1 Points [100, 0] Branch { DstBlock "ASR" DstPort 1 } Branch { Points [0, 305] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "vin" SrcPort 1 Points [25, 0] Branch { DstBlock "ASR" DstPort 3 } Branch { Points [0, 100] Branch { Points [0, 195] DstBlock "Gateway Out8" DstPort 1 } Branch { Points [230, 0] DstBlock "MAC" DstPort 4 } } Branch { Points [0, -80] DstBlock "x_dly_vout" DstPort 1 } } Line { SrcBlock "Delay" SrcPort 1 DstBlock "y_vout" DstPort 1 } Line { Name "X Vin" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 Points [150, 0] } Line { Name "ASR Addr" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 Points [150, 0] } Line { Name "X In" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 Points [150, 0] } Line { Name "ASR Out" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 Points [150, 0] } Line { Name "ROM Out" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 Points [150, 0] } Line { Name "Corr Ld" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 Points [150, 0] } Line { Name "Corr Out" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 Points [150, 0] } Line { Name "ROM Addr" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 Points [150, 0] } } } Block { BlockType SubSystem Name "C7" SID "13536" Ports [4, 4] Position [950, 207, 1020, 293] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskPromptString "Coefficients (all)|Sub-correlator Ind|Coef/correlator" MaskStyleString "edit,edit,edit" MaskVariables "h=@1;c_ind=@2;N=@3;" MaskTunableValueString "on,on,on" MaskCallbackString "||" MaskEnableString "on,on,on" MaskVisibilityString "on,on,on" MaskToolTipString "on,on,on" MaskInitialization "coef2 = h((c_ind*N+1) : (c_ind + 1)*N);" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "h|6|N" System { Name "C7" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "122" Block { BlockType Inport Name "x" SID "13537" Position [265, 263, 295, 277] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "vin" SID "13538" Position [270, 303, 300, 317] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "13539" Position [270, 458, 300, 472] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "13540" Position [270, 503, 300, 517] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "ASR" SID "13541" Ports [3, 1] Position [445, 260, 490, 320] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Addressable Shift Register" SourceType "Xilinx Addressable Shift Register Block" infoedit "Delay of configurable length. Any element in the delay line can be addressed and driven onto the" " output port.

Hardware notes: This block is implemented using SRL16s. If Virtex-4 or Spartan-3 device is " "used, multiple SRLC16s are cascaded together." infer_latency off depth "length(coef2)" initVector "[0]" en on dbl_ovrd off use_behavioral_HDL off Optimization "Resource" xl_use_area off xl_area "[1 0 0 2 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,401" block_type "addrsr" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,60,3,1,white,blue,0,f8ea6153,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 60 60 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 60 60 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[36.66 3" "6.66 42.66 36.66 42.66 42.66 42.66 36.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[30.66 30.66 36.66 " "36.66 30.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[24.66 24.66 30.66 30.66 24.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[18.66 18.66 24.66 18.66 24.66 24.66 18.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'addr');\ncolor('black');port_label('input',3," "'en');\ncolor('black');port_label('output',1,'q');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Delay" SID "13542" Ports [1, 1] Position [705, 441, 730, 469] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "25,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 " "17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33" " 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('blac" "k');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "13543" Position [210, 280, 300, 300] ZOrder -9 ShowName off GotoTag "ltsCorr_dAddr" TagVisibility "scoped" } Block { BlockType From Name "From1" SID "13544" Position [210, 340, 300, 360] ZOrder -9 ShowName off GotoTag "ltsCorr_cAddr" TagVisibility "scoped" } Block { BlockType From Name "From2" SID "13545" Position [210, 380, 300, 400] ZOrder -9 ShowName off GotoTag "ltsCorr_ld" TagVisibility "scoped" } Block { BlockType Reference Name "Gateway Out1" SID "13546" Ports [1, 1] Position [745, 615, 780, 625] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "13547" Ports [1, 1] Position [745, 630, 780, 640] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "13548" Ports [1, 1] Position [745, 645, 780, 655] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Ld" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "13549" Ports [1, 1] Position [745, 660, 780, 670] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "13550" Ports [1, 1] Position [745, 675, 780, 685] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "13551" Ports [1, 1] Position [745, 570, 780, 580] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X In" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "13552" Ports [1, 1] Position [745, 585, 780, 595] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "13553" Ports [1, 1] Position [745, 600, 780, 610] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X Vin" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType SubSystem Name "MAC" SID "13554" Ports [4, 2] Position [575, 279, 660, 376] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "MAC" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "a" SID "13555" Position [35, 143, 65, 157] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "coeff" SID "13556" Position [35, 108, 65, 122] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "ld" SID "13557" Position [35, 178, 65, 192] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "rst" SID "13558" Position [35, 233, 65, 247] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub" SID "13559" Ports [3, 1] Position [340, 113, 385, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition or Subtraction" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Signed (2's comp)" n_bits "long_cor_acc_n_bits" bin_pt "0" quantization "Truncate" overflow "Flag as error" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[2 0 0 4 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,344" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,3,1,white,blue,0,02f64c57,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('input',3,'su" "b');\ncolor('black');port_label('output',1,'\\bf{a \\pm b}','texmode','on');\nfprintf('','COMMENT: end icon text" "');\n" } Block { BlockType Reference Name "Gateway Out1" SID "13560" Ports [1, 1] Position [475, 450, 510, 460] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out2" SID "13561" Ports [1, 1] Position [475, 465, 510, 475] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out3" SID "13562" Ports [1, 1] Position [475, 480, 510, 490] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out6" SID "13563" Ports [1, 1] Position [475, 405, 510, 415] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out7" SID "13564" Ports [1, 1] Position [475, 420, 510, 430] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out8" SID "13565" Ports [1, 1] Position [475, 435, 510, 445] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "13566" Ports [2, 1] Position [345, 30, 385, 70] BlockMirror on NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,40,2,1,white,blue,0,140cc11c,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'" "q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "13567" Ports [2, 1] Position [465, 110, 495, 210] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,100,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 100 100 0 ],[0.77 0." "82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 100 100 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[54.44 " "54.44 58.44 54.44 58.44 58.44 58.44 54.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[50.44 50.44 54.44 54" ".44 50.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[46.44 46.44 50.44 50.44 46.44 ],[1 1 1 ])" ";\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[42.44 42.44 46.44 42.44 46.44 46.44 42.44 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\nco" "lor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc2" SID "13568" Ports [1, 1] Position [265, 143, 290, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc3" SID "13569" Ports [1, 1] Position [135, 178, 160, 192] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "yn" SID "13570" Position [545, 153, 575, 167] IconDisplay "Port number" } Block { BlockType Outport Name "accrm" SID "13571" Position [520, 288, 550, 302] Port "2" IconDisplay "Port number" } Line { SrcBlock "rst" SrcPort 1 Points [90, 0] Branch { Points [0, 215] DstBlock "Gateway Out1" DstPort 1 } Branch { Points [255, 0; 0, -180] DstBlock "Register1" DstPort 2 } } Line { SrcBlock "Gateway Out3" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out2" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out1" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out6" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out7" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out8" SrcPort 1 Points [50, 0] } Line { SrcBlock "a" SrcPort 1 Points [140, 0] Branch { Points [0, 275] DstBlock "Gateway Out7" DstPort 1 } Branch { DstBlock "bc2" DstPort 1 } } Line { SrcBlock "AddSub" SrcPort 1 Points [0, 0; 5, 0] Branch { Points [0, 305] DstBlock "Gateway Out8" DstPort 1 } Branch { Points [40, 0] Branch { Points [0, 160] DstBlock "accrm" DstPort 1 } Branch { Points [0, -95] DstBlock "Register1" DstPort 1 } Branch { DstBlock "Register2" DstPort 1 } } } Line { SrcBlock "Register2" SrcPort 1 Points [15, 0] Branch { Points [0, 50; 110, 0; 0, 385; -260, 0; 0, -110] DstBlock "Gateway Out3" DstPort 1 } Branch { DstBlock "yn" DstPort 1 } } Line { SrcBlock "Register1" SrcPort 1 Points [-15, 0] DstBlock "AddSub" DstPort 1 } Line { SrcBlock "ld" SrcPort 1 Points [45, 0] Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } Branch { DstBlock "bc3" DstPort 1 } } Line { SrcBlock "bc3" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "bc2" SrcPort 1 DstBlock "AddSub" DstPort 3 } Line { SrcBlock "coeff" SrcPort 1 Points [95, 0; 0, 20; 50, 0] Branch { Points [0, 275] DstBlock "Gateway Out6" DstPort 1 } Branch { DstBlock "AddSub" DstPort 2 } } } } Block { BlockType Reference Name "ROM" SID "13572" Ports [1, 1] Position [440, 328, 490, 372] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/ROM" SourceType "Xilinx Single Port Read-Only Memory Block" depth "length(coef2)" initVector "coef2" distributed_mem "Distributed memory" rst off init_reg "0" en off latency "1" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "longCorr_coef_nbits" bin_pt "longCorr_coef_bp" preci_type "Single" exp_width "8" frac_width "24" dbl_ovrd off optimize "Area" use_rpm off xl_use_area off xl_area "[1 1 0 1 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,308" block_type "sprom" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,44,1,1,white,blue,0,bbc23d60,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 44 44 0 ]);\npatch([11.65 20.32 26.32 32.32 38.32 26.32 17.65 11.65 ],[28.66" " 28.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([17.65 26.32 20.32 11.65 17.65 ],[22.66 22.66 28." "66 28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([11.65 20.32 26.32 17.65 11.65 ],[16.66 16.66 22.66 22.66 16.66 ]" ",[1 1 1 ]);\npatch([17.65 38.32 32.32 26.32 20.32 11.65 17.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'addr');\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end" " icon text');\n" } Block { BlockType Outport Name "x_dly" SID "13573" Position [790, 178, 820, 192] IconDisplay "Port number" } Block { BlockType Outport Name "x_dly_vout" SID "13574" Position [790, 223, 820, 237] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "y" SID "13575" Position [790, 293, 820, 307] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "y_vout" SID "13576" Position [785, 448, 815, 462] Port "4" IconDisplay "Port number" } Line { Name "ROM Addr" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 Points [150, 0] } Line { Name "Corr Out" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 Points [150, 0] } Line { Name "Corr Ld" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 Points [150, 0] } Line { Name "ROM Out" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 Points [150, 0] } Line { Name "ASR Out" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 Points [150, 0] } Line { Name "X In" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 Points [150, 0] } Line { Name "ASR Addr" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 Points [150, 0] } Line { Name "X Vin" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 Points [150, 0] } Line { SrcBlock "Delay" SrcPort 1 DstBlock "y_vout" DstPort 1 } Line { SrcBlock "vin" SrcPort 1 Points [25, 0] Branch { Points [0, -80] DstBlock "x_dly_vout" DstPort 1 } Branch { Points [0, 100] Branch { Points [230, 0] DstBlock "MAC" DstPort 4 } Branch { Points [0, 195] DstBlock "Gateway Out8" DstPort 1 } } Branch { DstBlock "ASR" DstPort 3 } } Line { SrcBlock "x" SrcPort 1 Points [100, 0] Branch { Points [0, 305] DstBlock "Gateway Out6" DstPort 1 } Branch { DstBlock "ASR" DstPort 1 } } Line { SrcBlock "From" SrcPort 1 Points [90, 0] Branch { Points [0, 300] DstBlock "Gateway Out7" DstPort 1 } Branch { DstBlock "ASR" DstPort 2 } } Line { SrcBlock "From1" SrcPort 1 Points [5, 0] Branch { Points [0, 330] DstBlock "Gateway Out5" DstPort 1 } Branch { DstBlock "ROM" DstPort 1 } } Line { SrcBlock "ASR" SrcPort 1 Points [35, 0] Branch { Points [0, 330] DstBlock "Gateway Out1" DstPort 1 } Branch { Points [0, -105] DstBlock "x_dly" DstPort 1 } Branch { DstBlock "MAC" DstPort 1 } } Line { SrcBlock "MAC" SrcPort 1 Points [0, -5; 15, 0] Branch { Points [0, 365] DstBlock "Gateway Out4" DstPort 1 } Branch { DstBlock "y" DstPort 1 } } Line { SrcBlock "ROM" SrcPort 1 Points [5, 0] Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } Branch { Points [0, -35] DstBlock "MAC" DstPort 2 } } Line { SrcBlock "From2" SrcPort 1 Points [145, 0] Branch { Points [0, 260] DstBlock "Gateway Out3" DstPort 1 } Branch { Points [90, 0] Branch { Points [0, 65] DstBlock "Delay" DstPort 1 } Branch { Points [0, -50] Branch { Points [0, -90; 160, 0] } Branch { DstBlock "MAC" DstPort 3 } } } } } } Block { BlockType SubSystem Name "C8" SID "13577" Ports [4, 4] Position [1060, 207, 1130, 293] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskPromptString "Coefficients (all)|Sub-correlator Ind|Coef/correlator" MaskStyleString "edit,edit,edit" MaskVariables "h=@1;c_ind=@2;N=@3;" MaskTunableValueString "on,on,on" MaskCallbackString "||" MaskEnableString "on,on,on" MaskVisibilityString "on,on,on" MaskToolTipString "on,on,on" MaskInitialization "coef2 = h((c_ind*N+1) : (c_ind + 1)*N);" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "h|7|N" System { Name "C8" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "122" Block { BlockType Inport Name "x" SID "13578" Position [265, 263, 295, 277] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "vin" SID "13579" Position [270, 303, 300, 317] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "13580" Position [270, 458, 300, 472] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "13581" Position [270, 503, 300, 517] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "ASR" SID "13582" Ports [3, 1] Position [445, 260, 490, 320] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Addressable Shift Register" SourceType "Xilinx Addressable Shift Register Block" infoedit "Delay of configurable length. Any element in the delay line can be addressed and driven onto the" " output port.

Hardware notes: This block is implemented using SRL16s. If Virtex-4 or Spartan-3 device is " "used, multiple SRLC16s are cascaded together." infer_latency off depth "length(coef2)" initVector "[0]" en on dbl_ovrd off use_behavioral_HDL off Optimization "Resource" xl_use_area off xl_area "[1 0 0 2 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,401" block_type "addrsr" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,60,3,1,white,blue,0,f8ea6153,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 60 60 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 60 60 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[36.66 3" "6.66 42.66 36.66 42.66 42.66 42.66 36.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[30.66 30.66 36.66 " "36.66 30.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[24.66 24.66 30.66 30.66 24.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[18.66 18.66 24.66 18.66 24.66 24.66 18.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'addr');\ncolor('black');port_label('input',3," "'en');\ncolor('black');port_label('output',1,'q');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Delay" SID "13583" Ports [1, 1] Position [705, 441, 730, 469] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "25,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 " "17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33" " 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('blac" "k');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "13584" Position [210, 280, 300, 300] ZOrder -9 ShowName off GotoTag "ltsCorr_dAddr" TagVisibility "scoped" } Block { BlockType From Name "From1" SID "13585" Position [210, 340, 300, 360] ZOrder -9 ShowName off GotoTag "ltsCorr_cAddr" TagVisibility "scoped" } Block { BlockType From Name "From2" SID "13586" Position [210, 380, 300, 400] ZOrder -9 ShowName off GotoTag "ltsCorr_ld" TagVisibility "scoped" } Block { BlockType Reference Name "Gateway Out1" SID "13587" Ports [1, 1] Position [745, 615, 780, 625] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "13588" Ports [1, 1] Position [745, 630, 780, 640] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "13589" Ports [1, 1] Position [745, 645, 780, 655] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Ld" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "13590" Ports [1, 1] Position [745, 660, 780, 670] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "13591" Ports [1, 1] Position [745, 675, 780, 685] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "13592" Ports [1, 1] Position [745, 570, 780, 580] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X In" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "13593" Ports [1, 1] Position [745, 585, 780, 595] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "13594" Ports [1, 1] Position [745, 600, 780, 610] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X Vin" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType SubSystem Name "MAC" SID "13595" Ports [4, 2] Position [575, 279, 660, 376] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "MAC" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "a" SID "13596" Position [35, 143, 65, 157] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "coeff" SID "13597" Position [35, 108, 65, 122] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "ld" SID "13598" Position [35, 178, 65, 192] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "rst" SID "13599" Position [35, 233, 65, 247] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub" SID "13600" Ports [3, 1] Position [340, 113, 385, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition or Subtraction" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Signed (2's comp)" n_bits "long_cor_acc_n_bits" bin_pt "0" quantization "Truncate" overflow "Flag as error" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[2 0 0 4 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,344" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,3,1,white,blue,0,02f64c57,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('input',3,'su" "b');\ncolor('black');port_label('output',1,'\\bf{a \\pm b}','texmode','on');\nfprintf('','COMMENT: end icon text" "');\n" } Block { BlockType Reference Name "Gateway Out1" SID "13601" Ports [1, 1] Position [475, 450, 510, 460] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out2" SID "13602" Ports [1, 1] Position [475, 465, 510, 475] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out3" SID "13603" Ports [1, 1] Position [475, 480, 510, 490] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out6" SID "13604" Ports [1, 1] Position [475, 405, 510, 415] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out7" SID "13605" Ports [1, 1] Position [475, 420, 510, 430] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out8" SID "13606" Ports [1, 1] Position [475, 435, 510, 445] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "13607" Ports [2, 1] Position [345, 30, 385, 70] BlockMirror on NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,40,2,1,white,blue,0,140cc11c,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'" "q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "13608" Ports [2, 1] Position [465, 110, 495, 210] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,100,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 100 100 0 ],[0.77 0." "82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 100 100 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[54.44 " "54.44 58.44 54.44 58.44 58.44 58.44 54.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[50.44 50.44 54.44 54" ".44 50.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[46.44 46.44 50.44 50.44 46.44 ],[1 1 1 ])" ";\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[42.44 42.44 46.44 42.44 46.44 46.44 42.44 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\nco" "lor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc2" SID "13609" Ports [1, 1] Position [265, 143, 290, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc3" SID "13610" Ports [1, 1] Position [135, 178, 160, 192] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "yn" SID "13611" Position [545, 153, 575, 167] IconDisplay "Port number" } Block { BlockType Outport Name "accrm" SID "13612" Position [520, 288, 550, 302] Port "2" IconDisplay "Port number" } Line { SrcBlock "coeff" SrcPort 1 Points [95, 0; 0, 20; 50, 0] Branch { DstBlock "AddSub" DstPort 2 } Branch { Points [0, 275] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "bc2" SrcPort 1 DstBlock "AddSub" DstPort 3 } Line { SrcBlock "bc3" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "ld" SrcPort 1 Points [45, 0] Branch { DstBlock "bc3" DstPort 1 } Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "Register1" SrcPort 1 Points [-15, 0] DstBlock "AddSub" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 Points [15, 0] Branch { DstBlock "yn" DstPort 1 } Branch { Points [0, 50; 110, 0; 0, 385; -260, 0; 0, -110] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "AddSub" SrcPort 1 Points [0, 0; 5, 0] Branch { Points [40, 0] Branch { DstBlock "Register2" DstPort 1 } Branch { Points [0, -95] DstBlock "Register1" DstPort 1 } Branch { Points [0, 160] DstBlock "accrm" DstPort 1 } } Branch { Points [0, 305] DstBlock "Gateway Out8" DstPort 1 } } Line { SrcBlock "a" SrcPort 1 Points [140, 0] Branch { DstBlock "bc2" DstPort 1 } Branch { Points [0, 275] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "Gateway Out8" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out7" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out6" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out1" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out2" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out3" SrcPort 1 Points [50, 0] } Line { SrcBlock "rst" SrcPort 1 Points [90, 0] Branch { Points [255, 0; 0, -180] DstBlock "Register1" DstPort 2 } Branch { Points [0, 215] DstBlock "Gateway Out1" DstPort 1 } } } } Block { BlockType Reference Name "ROM" SID "13613" Ports [1, 1] Position [440, 328, 490, 372] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/ROM" SourceType "Xilinx Single Port Read-Only Memory Block" depth "length(coef2)" initVector "coef2" distributed_mem "Distributed memory" rst off init_reg "0" en off latency "1" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "longCorr_coef_nbits" bin_pt "longCorr_coef_bp" preci_type "Single" exp_width "8" frac_width "24" dbl_ovrd off optimize "Area" use_rpm off xl_use_area off xl_area "[1 1 0 1 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,308" block_type "sprom" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,44,1,1,white,blue,0,bbc23d60,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 44 44 0 ]);\npatch([11.65 20.32 26.32 32.32 38.32 26.32 17.65 11.65 ],[28.66" " 28.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([17.65 26.32 20.32 11.65 17.65 ],[22.66 22.66 28." "66 28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([11.65 20.32 26.32 17.65 11.65 ],[16.66 16.66 22.66 22.66 16.66 ]" ",[1 1 1 ]);\npatch([17.65 38.32 32.32 26.32 20.32 11.65 17.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'addr');\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end" " icon text');\n" } Block { BlockType Outport Name "x_dly" SID "13614" Position [790, 178, 820, 192] IconDisplay "Port number" } Block { BlockType Outport Name "x_dly_vout" SID "13615" Position [790, 223, 820, 237] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "y" SID "13616" Position [790, 293, 820, 307] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "y_vout" SID "13617" Position [785, 448, 815, 462] Port "4" IconDisplay "Port number" } Line { SrcBlock "From2" SrcPort 1 Points [145, 0] Branch { Points [90, 0] Branch { Points [0, -50] Branch { DstBlock "MAC" DstPort 3 } Branch { Points [0, -90; 160, 0] } } Branch { Points [0, 65] DstBlock "Delay" DstPort 1 } } Branch { Points [0, 260] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "ROM" SrcPort 1 Points [5, 0] Branch { Points [0, -35] DstBlock "MAC" DstPort 2 } Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "MAC" SrcPort 1 Points [0, -5; 15, 0] Branch { DstBlock "y" DstPort 1 } Branch { Points [0, 365] DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "ASR" SrcPort 1 Points [35, 0] Branch { DstBlock "MAC" DstPort 1 } Branch { Points [0, -105] DstBlock "x_dly" DstPort 1 } Branch { Points [0, 330] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "From1" SrcPort 1 Points [5, 0] Branch { DstBlock "ROM" DstPort 1 } Branch { Points [0, 330] DstBlock "Gateway Out5" DstPort 1 } } Line { SrcBlock "From" SrcPort 1 Points [90, 0] Branch { DstBlock "ASR" DstPort 2 } Branch { Points [0, 300] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "x" SrcPort 1 Points [100, 0] Branch { DstBlock "ASR" DstPort 1 } Branch { Points [0, 305] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "vin" SrcPort 1 Points [25, 0] Branch { DstBlock "ASR" DstPort 3 } Branch { Points [0, 100] Branch { Points [0, 195] DstBlock "Gateway Out8" DstPort 1 } Branch { Points [230, 0] DstBlock "MAC" DstPort 4 } } Branch { Points [0, -80] DstBlock "x_dly_vout" DstPort 1 } } Line { SrcBlock "Delay" SrcPort 1 DstBlock "y_vout" DstPort 1 } Line { Name "X Vin" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 Points [150, 0] } Line { Name "ASR Addr" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 Points [150, 0] } Line { Name "X In" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 Points [150, 0] } Line { Name "ASR Out" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 Points [150, 0] } Line { Name "ROM Out" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 Points [150, 0] } Line { Name "Corr Ld" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 Points [150, 0] } Line { Name "Corr Out" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 Points [150, 0] } Line { Name "ROM Addr" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 Points [150, 0] } } } Block { BlockType Reference Name "Gateway Out1" SID "13618" Ports [1, 1] Position [1195, 75, 1230, 85] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out10" SID "13619" Ports [1, 1] Position [1195, 120, 1230, 130] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out11" SID "13620" Ports [1, 1] Position [1195, 135, 1230, 145] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out12" SID "13621" Ports [1, 1] Position [1195, 150, 1230, 160] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out13" SID "13622" Ports [1, 1] Position [1195, 165, 1230, 175] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out14" SID "13623" Ports [1, 1] Position [1225, 180, 1260, 190] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out2" SID "13624" Ports [1, 1] Position [740, 720, 775, 730] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out3" SID "13625" Ports [1, 1] Position [740, 690, 775, 700] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out4" SID "13626" Ports [1, 1] Position [740, 705, 775, 715] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out5" SID "13627" Ports [1, 1] Position [740, 735, 775, 745] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out6" SID "13628" Ports [1, 1] Position [1195, 45, 1230, 55] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out7" SID "13629" Ports [1, 1] Position [1195, 60, 1230, 70] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out8" SID "13630" Ports [1, 1] Position [1195, 90, 1230, 100] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out9" SID "13631" Ports [1, 1] Position [1195, 105, 1230, 115] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Outport Name "y" SID "13632" Position [1290, 568, 1320, 582] IconDisplay "Port number" } Block { BlockType Outport Name "y_vout" SID "13633" Position [1290, 523, 1320, 537] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "x_dly" SID "13634" Position [1260, 213, 1290, 227] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "x_dly_vout" SID "13635" Position [1260, 253, 1290, 267] Port "4" IconDisplay "Port number" } Line { SrcBlock "C8" SrcPort 2 Points [110, 0] DstBlock "x_dly_vout" DstPort 1 } Line { SrcBlock "C8" SrcPort 1 DstBlock "x_dly" DstPort 1 } Line { SrcBlock "Gateway Out14" SrcPort 1 Points [20, 0] } Line { SrcBlock "Gateway Out13" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out12" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out11" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out10" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out9" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out1" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out8" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out6" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out7" SrcPort 1 Points [50, 0] } Line { SrcBlock "C8" SrcPort 4 Points [40, 0; 0, 250] DstBlock "y_vout" DstPort 1 } Line { SrcBlock "AddSub4" SrcPort 1 Points [45, 0] Branch { Points [155, 0] Branch { Points [0, -390] DstBlock "Gateway Out14" DstPort 1 } Branch { DstBlock "y" DstPort 1 } } Branch { Points [0, 75; -400, 0; 0, 90] DstBlock "Gateway Out5" DstPort 1 } } Line { SrcBlock "AddSub1" SrcPort 1 Points [0, 60] DstBlock "AddSub4" DstPort 1 } Line { SrcBlock "AddSub13" SrcPort 1 Points [0, 85] DstBlock "AddSub4" DstPort 2 } Line { SrcBlock "AddSub7" SrcPort 1 Points [0, 35] DstBlock "AddSub1" DstPort 2 } Line { SrcBlock "AddSub6" SrcPort 1 DstBlock "AddSub1" DstPort 1 } Line { SrcBlock "C7" SrcPort 3 Points [20, 0] Branch { Points [0, -105] DstBlock "Gateway Out12" DstPort 1 } Branch { Points [0, 65; 75, 0] DstBlock "AddSub7" DstPort 1 } } Line { SrcBlock "C8" SrcPort 3 Points [10, 0] Branch { Points [0, -90] DstBlock "Gateway Out13" DstPort 1 } Branch { DstBlock "AddSub7" DstPort 2 } } Line { SrcBlock "C5" SrcPort 3 Points [10, 0] Branch { Points [0, -135] DstBlock "Gateway Out10" DstPort 1 } Branch { Points [0, 70; 85, 0] DstBlock "AddSub6" DstPort 1 } } Line { SrcBlock "C6" SrcPort 3 Points [15, 0] Branch { Points [0, -120] DstBlock "Gateway Out11" DstPort 1 } Branch { DstBlock "AddSub6" DstPort 2 } } Line { SrcBlock "C7" SrcPort 2 DstBlock "C8" DstPort 2 } Line { SrcBlock "C7" SrcPort 1 DstBlock "C8" DstPort 1 } Line { SrcBlock "C6" SrcPort 2 DstBlock "C7" DstPort 2 } Line { SrcBlock "C6" SrcPort 1 DstBlock "C7" DstPort 1 } Line { SrcBlock "C5" SrcPort 2 DstBlock "C6" DstPort 2 } Line { SrcBlock "C5" SrcPort 1 DstBlock "C6" DstPort 1 } Line { SrcBlock "C4" SrcPort 3 Points [15, 0] Branch { Points [0, -150] DstBlock "Gateway Out9" DstPort 1 } Branch { DstBlock "AddSub12" DstPort 2 } } Line { SrcBlock "C4" SrcPort 2 DstBlock "C5" DstPort 2 } Line { SrcBlock "C4" SrcPort 1 DstBlock "C5" DstPort 1 } Line { SrcBlock "C3" SrcPort 3 Points [20, 0] Branch { Points [0, -165] DstBlock "Gateway Out8" DstPort 1 } Branch { Points [0, 65; 80, 0] DstBlock "AddSub12" DstPort 1 } } Line { SrcBlock "C3" SrcPort 2 DstBlock "C4" DstPort 2 } Line { SrcBlock "C3" SrcPort 1 DstBlock "C4" DstPort 1 } Line { SrcBlock "C1" SrcPort 3 Points [15, 0] Branch { Points [0, -195] DstBlock "Gateway Out7" DstPort 1 } Branch { Points [0, 55] Branch { Points [0, 410] DstBlock "Gateway Out2" DstPort 1 } Branch { Points [0, 5; 95, 0] DstBlock "AddSub5" DstPort 1 } } } Line { SrcBlock "C2" SrcPort 3 Points [20, 0] Branch { Points [0, -180] DstBlock "Gateway Out1" DstPort 1 } Branch { DstBlock "AddSub5" DstPort 2 } } Line { SrcBlock "C2" SrcPort 2 DstBlock "C3" DstPort 2 } Line { SrcBlock "C2" SrcPort 1 DstBlock "C3" DstPort 1 } Line { SrcBlock "C1" SrcPort 2 DstBlock "C2" DstPort 2 } Line { SrcBlock "C1" SrcPort 1 DstBlock "C2" DstPort 1 } Line { SrcBlock "x_valid" SrcPort 1 Points [200, 0] Branch { Points [0, 450] DstBlock "Gateway Out4" DstPort 1 } Branch { Points [0, -20] DstBlock "C1" DstPort 2 } } Line { Points [780, 755; 50, 0] } Line { SrcBlock "Gateway Out2" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out5" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out3" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out4" SrcPort 1 Points [50, 0] } Line { SrcBlock "AddSub5" SrcPort 1 Points [0, 35] DstBlock "AddSub13" DstPort 1 } Line { SrcBlock "AddSub12" SrcPort 1 DstBlock "AddSub13" DstPort 2 } Line { SrcBlock "x" SrcPort 1 Points [210, 0] Branch { Points [0, -170] DstBlock "Gateway Out6" DstPort 1 } Branch { Points [0, 475] DstBlock "Gateway Out3" DstPort 1 } Branch { DstBlock "C1" DstPort 1 } } } } Block { BlockType SubSystem Name "C6" SID "13636" Ports [2, 4] Position [725, 263, 810, 332] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskPromptString "Coefficients/correlator|Coefficients|Input sample period" MaskStyleString "edit,edit,edit" MaskVariables "N=@1;h=@2;Ts_In=@3;" MaskTunableValueString "on,on,on" MaskCallbackString "||" MaskEnableString "on,on,on" MaskVisibilityString "on,on,on" MaskToolTipString "on,on,on" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "4|longCorr_coef_q(33:64)|4" System { Name "C6" Location [480, 85, 2304, 1455] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "156" Block { BlockType Inport Name "x" SID "13637" Position [35, 213, 65, 227] IconDisplay "Port number" } Block { BlockType Inport Name "x_valid" SID "13638" Position [35, 253, 65, 267] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub1" SID "13639" Ports [2, 1] Position [915, 455, 955, 495] BlockRotation 270 BlockMirror on NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "1" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[3 6 0 5 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,40,2,1,white,blue,0,e85d8a90,down,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bf{a + b}','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\ne" "wline\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub12" SID "13640" Ports [2, 1] Position [684, 360, 731, 400] BlockRotation 270 BlockMirror on NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "1" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[3 5 0 4 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "47,40,2,1,white,blue,0,e85d8a90,down,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 47 47 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 47 47 0 0 ],[0 0 40 40 0 ]);\npatch([11.875 19.1 24.1 29.1 34.1 24.1 16.875 11.875 ],[25.55 2" "5.55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([16.875 24.1 19.1 11.875 16.875 ],[20.55 20.55 25.5" "5 25.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([11.875 19.1 24.1 16.875 11.875 ],[15.55 15.55 20.55 20.55 15.55 ]" ",[1 1 1 ]);\npatch([16.875 34.1 29.1 24.1 19.1 11.875 16.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('b" "lack');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output'" ",1,'\\bf{a + b}','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(" "' \\newline\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub13" SID "13641" Ports [2, 1] Position [680, 455, 720, 495] BlockRotation 270 BlockMirror on NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "1" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[3 6 0 5 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,40,2,1,white,blue,0,e85d8a90,down,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bf{a + b}','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\ne" "wline\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub4" SID "13642" Ports [2, 1] Position [960, 549, 1000, 596] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "1" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[4 7 0 6 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,47,2,1,white,blue,0,e85d8a90,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 47 47 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 47 47 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[28.55 28." "55 33.55 28.55 33.55 33.55 33.55 28.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[23.55 23.55 28.55 2" "8.55 23.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[18.55 18.55 23.55 23.55 18.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[13.55 13.55 18.55 13.55 18.55 18.55 13.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bf{a + b}','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\ne" "wline\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub5" SID "13643" Ports [2, 1] Position [475, 360, 515, 400] BlockRotation 270 BlockMirror on NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "1" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[3 6 0 5 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,40,2,1,white,blue,0,e85d8a90,down,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bf{a + b}','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\ne" "wline\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub6" SID "13644" Ports [2, 1] Position [899, 360, 946, 400] BlockRotation 270 BlockMirror on NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "1" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[3 5 0 4 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "47,40,2,1,white,blue,0,e85d8a90,down,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 47 47 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 47 47 0 0 ],[0 0 40 40 0 ]);\npatch([11.875 19.1 24.1 29.1 34.1 24.1 16.875 11.875 ],[25.55 2" "5.55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([16.875 24.1 19.1 11.875 16.875 ],[20.55 20.55 25.5" "5 25.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([11.875 19.1 24.1 16.875 11.875 ],[15.55 15.55 20.55 20.55 15.55 ]" ",[1 1 1 ]);\npatch([16.875 34.1 29.1 24.1 19.1 11.875 16.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('b" "lack');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output'" ",1,'\\bf{a + b}','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(" "' \\newline\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub7" SID "13645" Ports [2, 1] Position [1109, 360, 1156, 400] BlockRotation 270 BlockMirror on NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "1" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[3 5 0 4 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "47,40,2,1,white,blue,0,e85d8a90,down,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 47 47 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 47 47 0 0 ],[0 0 40 40 0 ]);\npatch([11.875 19.1 24.1 29.1 34.1 24.1 16.875 11.875 ],[25.55 2" "5.55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([16.875 24.1 19.1 11.875 16.875 ],[20.55 20.55 25.5" "5 25.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([11.875 19.1 24.1 16.875 11.875 ],[15.55 15.55 20.55 20.55 15.55 ]" ",[1 1 1 ]);\npatch([16.875 34.1 29.1 24.1 19.1 11.875 16.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('b" "lack');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output'" ",1,'\\bf{a + b}','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(" "' \\newline\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "C1" SID "13646" Ports [4, 4] Position [300, 207, 370, 293] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskPromptString "Coefficients (all)|Sub-correlator Ind|Coef/correlator" MaskStyleString "edit,edit,edit" MaskVariables "h=@1;c_ind=@2;N=@3;" MaskTunableValueString "on,on,on" MaskCallbackString "||" MaskEnableString "on,on,on" MaskVisibilityString "on,on,on" MaskToolTipString "on,on,on" MaskInitialization "coef2 = h((c_ind*N+1) : (c_ind + 1)*N);" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "h|0|N" System { Name "C1" Location [480, 85, 2304, 1471] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "122" Block { BlockType Inport Name "x" SID "13647" Position [265, 263, 295, 277] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "vin" SID "13648" Position [270, 303, 300, 317] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "13649" Position [270, 458, 300, 472] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "13650" Position [270, 503, 300, 517] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "ASR" SID "13651" Ports [3, 1] Position [445, 260, 490, 320] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Addressable Shift Register" SourceType "Xilinx Addressable Shift Register Block" infoedit "Delay of configurable length. Any element in the delay line can be addressed and driven onto the" " output port.

Hardware notes: This block is implemented using SRL16s. If Virtex-4 or Spartan-3 device is " "used, multiple SRLC16s are cascaded together." infer_latency off depth "length(coef2)" initVector "[0]" en on dbl_ovrd off use_behavioral_HDL off Optimization "Resource" xl_use_area off xl_area "[1 0 0 2 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,401" block_type "addrsr" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,60,3,1,white,blue,0,f8ea6153,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 60 60 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 60 60 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[36.66 3" "6.66 42.66 36.66 42.66 42.66 42.66 36.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[30.66 30.66 36.66 " "36.66 30.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[24.66 24.66 30.66 30.66 24.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[18.66 18.66 24.66 18.66 24.66 24.66 18.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'addr');\ncolor('black');port_label('input',3," "'en');\ncolor('black');port_label('output',1,'q');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Delay" SID "13652" Ports [1, 1] Position [705, 441, 730, 469] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "25,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 " "17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33" " 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('blac" "k');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "13653" Position [210, 280, 300, 300] ZOrder -9 ShowName off GotoTag "ltsCorr_dAddr" TagVisibility "scoped" } Block { BlockType From Name "From1" SID "13654" Position [210, 340, 300, 360] ZOrder -9 ShowName off GotoTag "ltsCorr_cAddr" TagVisibility "scoped" } Block { BlockType From Name "From2" SID "13655" Position [210, 380, 300, 400] ZOrder -9 ShowName off GotoTag "ltsCorr_ld" TagVisibility "scoped" } Block { BlockType Reference Name "Gateway Out1" SID "13656" Ports [1, 1] Position [745, 615, 780, 625] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "13657" Ports [1, 1] Position [745, 630, 780, 640] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "13658" Ports [1, 1] Position [745, 645, 780, 655] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Ld" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "13659" Ports [1, 1] Position [745, 660, 780, 670] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "13660" Ports [1, 1] Position [745, 675, 780, 685] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "13661" Ports [1, 1] Position [745, 570, 780, 580] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X In" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "13662" Ports [1, 1] Position [745, 585, 780, 595] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "13663" Ports [1, 1] Position [745, 600, 780, 610] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X Vin" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType SubSystem Name "MAC" SID "13664" Ports [4, 2] Position [575, 279, 660, 376] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "MAC" Location [88, 301, 2330, 1301] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "a" SID "13665" Position [35, 143, 65, 157] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "coeff" SID "13666" Position [35, 108, 65, 122] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "ld" SID "13667" Position [35, 178, 65, 192] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "rst" SID "13668" Position [35, 233, 65, 247] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub" SID "13669" Ports [3, 1] Position [340, 113, 385, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition or Subtraction" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Signed (2's comp)" n_bits "long_cor_acc_n_bits" bin_pt "0" quantization "Truncate" overflow "Flag as error" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[2 0 0 4 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,344" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,3,1,white,blue,0,02f64c57,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('input',3,'su" "b');\ncolor('black');port_label('output',1,'\\bf{a \\pm b}','texmode','on');\nfprintf('','COMMENT: end icon text" "');\n" } Block { BlockType Reference Name "Gateway Out1" SID "13670" Ports [1, 1] Position [475, 450, 510, 460] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out2" SID "13671" Ports [1, 1] Position [475, 465, 510, 475] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out3" SID "13672" Ports [1, 1] Position [475, 480, 510, 490] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out6" SID "13673" Ports [1, 1] Position [475, 405, 510, 415] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out7" SID "13674" Ports [1, 1] Position [475, 420, 510, 430] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out8" SID "13675" Ports [1, 1] Position [475, 435, 510, 445] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "13676" Ports [2, 1] Position [345, 30, 385, 70] BlockMirror on NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,40,2,1,white,blue,0,140cc11c,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'" "q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "13677" Ports [2, 1] Position [465, 110, 495, 210] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,100,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 100 100 0 ],[0.77 0." "82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 100 100 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[54.44 " "54.44 58.44 54.44 58.44 58.44 58.44 54.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[50.44 50.44 54.44 54" ".44 50.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[46.44 46.44 50.44 50.44 46.44 ],[1 1 1 ])" ";\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[42.44 42.44 46.44 42.44 46.44 46.44 42.44 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\nco" "lor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc2" SID "13678" Ports [1, 1] Position [265, 143, 290, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc3" SID "13679" Ports [1, 1] Position [135, 178, 160, 192] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "yn" SID "13680" Position [545, 153, 575, 167] IconDisplay "Port number" } Block { BlockType Outport Name "accrm" SID "13681" Position [520, 288, 550, 302] Port "2" IconDisplay "Port number" } Line { SrcBlock "coeff" SrcPort 1 Points [95, 0; 0, 20; 50, 0] Branch { DstBlock "AddSub" DstPort 2 } Branch { Points [0, 275] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "bc2" SrcPort 1 DstBlock "AddSub" DstPort 3 } Line { SrcBlock "bc3" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "ld" SrcPort 1 Points [45, 0] Branch { DstBlock "bc3" DstPort 1 } Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "Register1" SrcPort 1 Points [-15, 0] DstBlock "AddSub" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 Points [15, 0] Branch { DstBlock "yn" DstPort 1 } Branch { Points [0, 50; 110, 0; 0, 385; -260, 0; 0, -110] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "AddSub" SrcPort 1 Points [0, 0; 5, 0] Branch { Points [40, 0] Branch { DstBlock "Register2" DstPort 1 } Branch { Points [0, -95] DstBlock "Register1" DstPort 1 } Branch { Points [0, 160] DstBlock "accrm" DstPort 1 } } Branch { Points [0, 305] DstBlock "Gateway Out8" DstPort 1 } } Line { SrcBlock "a" SrcPort 1 Points [140, 0] Branch { DstBlock "bc2" DstPort 1 } Branch { Points [0, 275] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "Gateway Out8" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out7" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out6" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out1" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out2" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out3" SrcPort 1 Points [50, 0] } Line { SrcBlock "rst" SrcPort 1 Points [90, 0] Branch { Points [255, 0; 0, -180] DstBlock "Register1" DstPort 2 } Branch { Points [0, 215] DstBlock "Gateway Out1" DstPort 1 } } } } Block { BlockType Reference Name "ROM" SID "13682" Ports [1, 1] Position [440, 328, 490, 372] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/ROM" SourceType "Xilinx Single Port Read-Only Memory Block" depth "length(coef2)" initVector "coef2" distributed_mem "Distributed memory" rst off init_reg "0" en off latency "1" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "longCorr_coef_nbits" bin_pt "longCorr_coef_bp" preci_type "Single" exp_width "8" frac_width "24" dbl_ovrd off optimize "Area" use_rpm off xl_use_area off xl_area "[1 1 0 1 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,308" block_type "sprom" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,44,1,1,white,blue,0,bbc23d60,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 44 44 0 ]);\npatch([11.65 20.32 26.32 32.32 38.32 26.32 17.65 11.65 ],[28.66" " 28.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([17.65 26.32 20.32 11.65 17.65 ],[22.66 22.66 28." "66 28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([11.65 20.32 26.32 17.65 11.65 ],[16.66 16.66 22.66 22.66 16.66 ]" ",[1 1 1 ]);\npatch([17.65 38.32 32.32 26.32 20.32 11.65 17.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'addr');\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end" " icon text');\n" } Block { BlockType Outport Name "x_dly" SID "13683" Position [790, 178, 820, 192] IconDisplay "Port number" } Block { BlockType Outport Name "x_dly_vout" SID "13684" Position [790, 223, 820, 237] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "y" SID "13685" Position [790, 293, 820, 307] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "y_vout" SID "13686" Position [785, 448, 815, 462] Port "4" IconDisplay "Port number" } Line { SrcBlock "From2" SrcPort 1 Points [145, 0] Branch { Points [90, 0] Branch { Points [0, -50] Branch { DstBlock "MAC" DstPort 3 } Branch { Points [0, -90; 160, 0] } } Branch { Points [0, 65] DstBlock "Delay" DstPort 1 } } Branch { Points [0, 260] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "ROM" SrcPort 1 Points [5, 0] Branch { Points [0, -35] DstBlock "MAC" DstPort 2 } Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "MAC" SrcPort 1 Points [0, -5; 15, 0] Branch { DstBlock "y" DstPort 1 } Branch { Points [0, 365] DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "ASR" SrcPort 1 Points [35, 0] Branch { DstBlock "MAC" DstPort 1 } Branch { Points [0, -105] DstBlock "x_dly" DstPort 1 } Branch { Points [0, 330] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "From1" SrcPort 1 Points [5, 0] Branch { DstBlock "ROM" DstPort 1 } Branch { Points [0, 330] DstBlock "Gateway Out5" DstPort 1 } } Line { SrcBlock "From" SrcPort 1 Points [90, 0] Branch { DstBlock "ASR" DstPort 2 } Branch { Points [0, 300] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "x" SrcPort 1 Points [100, 0] Branch { DstBlock "ASR" DstPort 1 } Branch { Points [0, 305] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "vin" SrcPort 1 Points [25, 0] Branch { DstBlock "ASR" DstPort 3 } Branch { Points [0, 100] Branch { Points [0, 195] DstBlock "Gateway Out8" DstPort 1 } Branch { Points [230, 0] DstBlock "MAC" DstPort 4 } } Branch { Points [0, -80] DstBlock "x_dly_vout" DstPort 1 } } Line { SrcBlock "Delay" SrcPort 1 DstBlock "y_vout" DstPort 1 } Line { Name "X Vin" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 Points [150, 0] } Line { Name "ASR Addr" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 Points [150, 0] } Line { Name "X In" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 Points [150, 0] } Line { Name "ASR Out" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 Points [150, 0] } Line { Name "ROM Out" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 Points [150, 0] } Line { Name "Corr Ld" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 Points [150, 0] } Line { Name "Corr Out" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 Points [150, 0] } Line { Name "ROM Addr" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 Points [150, 0] } } } Block { BlockType SubSystem Name "C2" SID "13687" Ports [4, 4] Position [410, 207, 480, 293] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskPromptString "Coefficients (all)|Sub-correlator Ind|Coef/correlator" MaskStyleString "edit,edit,edit" MaskVariables "h=@1;c_ind=@2;N=@3;" MaskTunableValueString "on,on,on" MaskCallbackString "||" MaskEnableString "on,on,on" MaskVisibilityString "on,on,on" MaskToolTipString "on,on,on" MaskInitialization "coef2 = h((c_ind*N+1) : (c_ind + 1)*N);" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "h|1|N" System { Name "C2" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "122" Block { BlockType Inport Name "x" SID "13688" Position [265, 263, 295, 277] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "vin" SID "13689" Position [270, 303, 300, 317] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "13690" Position [270, 458, 300, 472] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "13691" Position [270, 503, 300, 517] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "ASR" SID "13692" Ports [3, 1] Position [445, 260, 490, 320] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Addressable Shift Register" SourceType "Xilinx Addressable Shift Register Block" infoedit "Delay of configurable length. Any element in the delay line can be addressed and driven onto the" " output port.

Hardware notes: This block is implemented using SRL16s. If Virtex-4 or Spartan-3 device is " "used, multiple SRLC16s are cascaded together." infer_latency off depth "length(coef2)" initVector "[0]" en on dbl_ovrd off use_behavioral_HDL off Optimization "Resource" xl_use_area off xl_area "[1 0 0 2 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,401" block_type "addrsr" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,60,3,1,white,blue,0,f8ea6153,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 60 60 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 60 60 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[36.66 3" "6.66 42.66 36.66 42.66 42.66 42.66 36.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[30.66 30.66 36.66 " "36.66 30.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[24.66 24.66 30.66 30.66 24.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[18.66 18.66 24.66 18.66 24.66 24.66 18.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'addr');\ncolor('black');port_label('input',3," "'en');\ncolor('black');port_label('output',1,'q');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Delay" SID "13693" Ports [1, 1] Position [705, 441, 730, 469] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "25,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 " "17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33" " 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('blac" "k');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "13694" Position [210, 280, 300, 300] ZOrder -9 ShowName off GotoTag "ltsCorr_dAddr" TagVisibility "scoped" } Block { BlockType From Name "From1" SID "13695" Position [210, 340, 300, 360] ZOrder -9 ShowName off GotoTag "ltsCorr_cAddr" TagVisibility "scoped" } Block { BlockType From Name "From2" SID "13696" Position [210, 380, 300, 400] ZOrder -9 ShowName off GotoTag "ltsCorr_ld" TagVisibility "scoped" } Block { BlockType Reference Name "Gateway Out1" SID "13697" Ports [1, 1] Position [745, 615, 780, 625] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "13698" Ports [1, 1] Position [745, 630, 780, 640] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "13699" Ports [1, 1] Position [745, 645, 780, 655] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Ld" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "13700" Ports [1, 1] Position [745, 660, 780, 670] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "13701" Ports [1, 1] Position [745, 675, 780, 685] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "13702" Ports [1, 1] Position [745, 570, 780, 580] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X In" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "13703" Ports [1, 1] Position [745, 585, 780, 595] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "13704" Ports [1, 1] Position [745, 600, 780, 610] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X Vin" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType SubSystem Name "MAC" SID "13705" Ports [4, 2] Position [575, 279, 660, 376] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "MAC" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "a" SID "13706" Position [35, 143, 65, 157] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "coeff" SID "13707" Position [35, 108, 65, 122] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "ld" SID "13708" Position [35, 178, 65, 192] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "rst" SID "13709" Position [35, 233, 65, 247] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub" SID "13710" Ports [3, 1] Position [340, 113, 385, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition or Subtraction" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Signed (2's comp)" n_bits "long_cor_acc_n_bits" bin_pt "0" quantization "Truncate" overflow "Flag as error" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[2 0 0 4 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,344" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,3,1,white,blue,0,02f64c57,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('input',3,'su" "b');\ncolor('black');port_label('output',1,'\\bf{a \\pm b}','texmode','on');\nfprintf('','COMMENT: end icon text" "');\n" } Block { BlockType Reference Name "Gateway Out1" SID "13711" Ports [1, 1] Position [475, 450, 510, 460] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out2" SID "13712" Ports [1, 1] Position [475, 465, 510, 475] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out3" SID "13713" Ports [1, 1] Position [475, 480, 510, 490] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out6" SID "13714" Ports [1, 1] Position [475, 405, 510, 415] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out7" SID "13715" Ports [1, 1] Position [475, 420, 510, 430] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out8" SID "13716" Ports [1, 1] Position [475, 435, 510, 445] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "13717" Ports [2, 1] Position [345, 30, 385, 70] BlockMirror on NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,40,2,1,white,blue,0,140cc11c,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'" "q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "13718" Ports [2, 1] Position [465, 110, 495, 210] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,100,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 100 100 0 ],[0.77 0." "82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 100 100 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[54.44 " "54.44 58.44 54.44 58.44 58.44 58.44 54.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[50.44 50.44 54.44 54" ".44 50.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[46.44 46.44 50.44 50.44 46.44 ],[1 1 1 ])" ";\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[42.44 42.44 46.44 42.44 46.44 46.44 42.44 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\nco" "lor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc2" SID "13719" Ports [1, 1] Position [265, 143, 290, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc3" SID "13720" Ports [1, 1] Position [135, 178, 160, 192] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "yn" SID "13721" Position [545, 153, 575, 167] IconDisplay "Port number" } Block { BlockType Outport Name "accrm" SID "13722" Position [520, 288, 550, 302] Port "2" IconDisplay "Port number" } Line { SrcBlock "rst" SrcPort 1 Points [90, 0] Branch { Points [0, 215] DstBlock "Gateway Out1" DstPort 1 } Branch { Points [255, 0; 0, -180] DstBlock "Register1" DstPort 2 } } Line { SrcBlock "Gateway Out3" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out2" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out1" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out6" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out7" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out8" SrcPort 1 Points [50, 0] } Line { SrcBlock "a" SrcPort 1 Points [140, 0] Branch { Points [0, 275] DstBlock "Gateway Out7" DstPort 1 } Branch { DstBlock "bc2" DstPort 1 } } Line { SrcBlock "AddSub" SrcPort 1 Points [0, 0; 5, 0] Branch { Points [0, 305] DstBlock "Gateway Out8" DstPort 1 } Branch { Points [40, 0] Branch { Points [0, 160] DstBlock "accrm" DstPort 1 } Branch { Points [0, -95] DstBlock "Register1" DstPort 1 } Branch { DstBlock "Register2" DstPort 1 } } } Line { SrcBlock "Register2" SrcPort 1 Points [15, 0] Branch { Points [0, 50; 110, 0; 0, 385; -260, 0; 0, -110] DstBlock "Gateway Out3" DstPort 1 } Branch { DstBlock "yn" DstPort 1 } } Line { SrcBlock "Register1" SrcPort 1 Points [-15, 0] DstBlock "AddSub" DstPort 1 } Line { SrcBlock "ld" SrcPort 1 Points [45, 0] Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } Branch { DstBlock "bc3" DstPort 1 } } Line { SrcBlock "bc3" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "bc2" SrcPort 1 DstBlock "AddSub" DstPort 3 } Line { SrcBlock "coeff" SrcPort 1 Points [95, 0; 0, 20; 50, 0] Branch { Points [0, 275] DstBlock "Gateway Out6" DstPort 1 } Branch { DstBlock "AddSub" DstPort 2 } } } } Block { BlockType Reference Name "ROM" SID "13723" Ports [1, 1] Position [440, 328, 490, 372] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/ROM" SourceType "Xilinx Single Port Read-Only Memory Block" depth "length(coef2)" initVector "coef2" distributed_mem "Distributed memory" rst off init_reg "0" en off latency "1" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "longCorr_coef_nbits" bin_pt "longCorr_coef_bp" preci_type "Single" exp_width "8" frac_width "24" dbl_ovrd off optimize "Area" use_rpm off xl_use_area off xl_area "[1 1 0 1 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,308" block_type "sprom" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,44,1,1,white,blue,0,bbc23d60,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 44 44 0 ]);\npatch([11.65 20.32 26.32 32.32 38.32 26.32 17.65 11.65 ],[28.66" " 28.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([17.65 26.32 20.32 11.65 17.65 ],[22.66 22.66 28." "66 28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([11.65 20.32 26.32 17.65 11.65 ],[16.66 16.66 22.66 22.66 16.66 ]" ",[1 1 1 ]);\npatch([17.65 38.32 32.32 26.32 20.32 11.65 17.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'addr');\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end" " icon text');\n" } Block { BlockType Outport Name "x_dly" SID "13724" Position [790, 178, 820, 192] IconDisplay "Port number" } Block { BlockType Outport Name "x_dly_vout" SID "13725" Position [790, 223, 820, 237] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "y" SID "13726" Position [790, 293, 820, 307] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "y_vout" SID "13727" Position [785, 448, 815, 462] Port "4" IconDisplay "Port number" } Line { Name "ROM Addr" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 Points [150, 0] } Line { Name "Corr Out" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 Points [150, 0] } Line { Name "Corr Ld" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 Points [150, 0] } Line { Name "ROM Out" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 Points [150, 0] } Line { Name "ASR Out" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 Points [150, 0] } Line { Name "X In" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 Points [150, 0] } Line { Name "ASR Addr" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 Points [150, 0] } Line { Name "X Vin" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 Points [150, 0] } Line { SrcBlock "Delay" SrcPort 1 DstBlock "y_vout" DstPort 1 } Line { SrcBlock "vin" SrcPort 1 Points [25, 0] Branch { Points [0, -80] DstBlock "x_dly_vout" DstPort 1 } Branch { Points [0, 100] Branch { Points [230, 0] DstBlock "MAC" DstPort 4 } Branch { Points [0, 195] DstBlock "Gateway Out8" DstPort 1 } } Branch { DstBlock "ASR" DstPort 3 } } Line { SrcBlock "x" SrcPort 1 Points [100, 0] Branch { Points [0, 305] DstBlock "Gateway Out6" DstPort 1 } Branch { DstBlock "ASR" DstPort 1 } } Line { SrcBlock "From" SrcPort 1 Points [90, 0] Branch { Points [0, 300] DstBlock "Gateway Out7" DstPort 1 } Branch { DstBlock "ASR" DstPort 2 } } Line { SrcBlock "From1" SrcPort 1 Points [5, 0] Branch { Points [0, 330] DstBlock "Gateway Out5" DstPort 1 } Branch { DstBlock "ROM" DstPort 1 } } Line { SrcBlock "ASR" SrcPort 1 Points [35, 0] Branch { Points [0, 330] DstBlock "Gateway Out1" DstPort 1 } Branch { Points [0, -105] DstBlock "x_dly" DstPort 1 } Branch { DstBlock "MAC" DstPort 1 } } Line { SrcBlock "MAC" SrcPort 1 Points [0, -5; 15, 0] Branch { Points [0, 365] DstBlock "Gateway Out4" DstPort 1 } Branch { DstBlock "y" DstPort 1 } } Line { SrcBlock "ROM" SrcPort 1 Points [5, 0] Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } Branch { Points [0, -35] DstBlock "MAC" DstPort 2 } } Line { SrcBlock "From2" SrcPort 1 Points [145, 0] Branch { Points [0, 260] DstBlock "Gateway Out3" DstPort 1 } Branch { Points [90, 0] Branch { Points [0, 65] DstBlock "Delay" DstPort 1 } Branch { Points [0, -50] Branch { Points [0, -90; 160, 0] } Branch { DstBlock "MAC" DstPort 3 } } } } } } Block { BlockType SubSystem Name "C3" SID "13728" Ports [4, 4] Position [520, 207, 590, 293] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskPromptString "Coefficients (all)|Sub-correlator Ind|Coef/correlator" MaskStyleString "edit,edit,edit" MaskVariables "h=@1;c_ind=@2;N=@3;" MaskTunableValueString "on,on,on" MaskCallbackString "||" MaskEnableString "on,on,on" MaskVisibilityString "on,on,on" MaskToolTipString "on,on,on" MaskInitialization "coef2 = h((c_ind*N+1) : (c_ind + 1)*N);" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "h|2|N" System { Name "C3" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "122" Block { BlockType Inport Name "x" SID "13729" Position [265, 263, 295, 277] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "vin" SID "13730" Position [270, 303, 300, 317] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "13731" Position [270, 458, 300, 472] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "13732" Position [270, 503, 300, 517] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "ASR" SID "13733" Ports [3, 1] Position [445, 260, 490, 320] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Addressable Shift Register" SourceType "Xilinx Addressable Shift Register Block" infoedit "Delay of configurable length. Any element in the delay line can be addressed and driven onto the" " output port.

Hardware notes: This block is implemented using SRL16s. If Virtex-4 or Spartan-3 device is " "used, multiple SRLC16s are cascaded together." infer_latency off depth "length(coef2)" initVector "[0]" en on dbl_ovrd off use_behavioral_HDL off Optimization "Resource" xl_use_area off xl_area "[1 0 0 2 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,401" block_type "addrsr" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,60,3,1,white,blue,0,f8ea6153,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 60 60 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 60 60 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[36.66 3" "6.66 42.66 36.66 42.66 42.66 42.66 36.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[30.66 30.66 36.66 " "36.66 30.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[24.66 24.66 30.66 30.66 24.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[18.66 18.66 24.66 18.66 24.66 24.66 18.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'addr');\ncolor('black');port_label('input',3," "'en');\ncolor('black');port_label('output',1,'q');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Delay" SID "13734" Ports [1, 1] Position [705, 441, 730, 469] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "25,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 " "17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33" " 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('blac" "k');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "13735" Position [210, 280, 300, 300] ZOrder -9 ShowName off GotoTag "ltsCorr_dAddr" TagVisibility "scoped" } Block { BlockType From Name "From1" SID "13736" Position [210, 340, 300, 360] ZOrder -9 ShowName off GotoTag "ltsCorr_cAddr" TagVisibility "scoped" } Block { BlockType From Name "From2" SID "13737" Position [210, 380, 300, 400] ZOrder -9 ShowName off GotoTag "ltsCorr_ld" TagVisibility "scoped" } Block { BlockType Reference Name "Gateway Out1" SID "13738" Ports [1, 1] Position [745, 615, 780, 625] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "13739" Ports [1, 1] Position [745, 630, 780, 640] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "13740" Ports [1, 1] Position [745, 645, 780, 655] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Ld" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "13741" Ports [1, 1] Position [745, 660, 780, 670] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "13742" Ports [1, 1] Position [745, 675, 780, 685] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "13743" Ports [1, 1] Position [745, 570, 780, 580] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X In" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "13744" Ports [1, 1] Position [745, 585, 780, 595] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "13745" Ports [1, 1] Position [745, 600, 780, 610] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X Vin" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType SubSystem Name "MAC" SID "13746" Ports [4, 2] Position [575, 279, 660, 376] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "MAC" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "a" SID "13747" Position [35, 143, 65, 157] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "coeff" SID "13748" Position [35, 108, 65, 122] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "ld" SID "13749" Position [35, 178, 65, 192] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "rst" SID "13750" Position [35, 233, 65, 247] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub" SID "13751" Ports [3, 1] Position [340, 113, 385, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition or Subtraction" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Signed (2's comp)" n_bits "long_cor_acc_n_bits" bin_pt "0" quantization "Truncate" overflow "Flag as error" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[2 0 0 4 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,344" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,3,1,white,blue,0,02f64c57,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('input',3,'su" "b');\ncolor('black');port_label('output',1,'\\bf{a \\pm b}','texmode','on');\nfprintf('','COMMENT: end icon text" "');\n" } Block { BlockType Reference Name "Gateway Out1" SID "13752" Ports [1, 1] Position [475, 450, 510, 460] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out2" SID "13753" Ports [1, 1] Position [475, 465, 510, 475] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out3" SID "13754" Ports [1, 1] Position [475, 480, 510, 490] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out6" SID "13755" Ports [1, 1] Position [475, 405, 510, 415] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out7" SID "13756" Ports [1, 1] Position [475, 420, 510, 430] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out8" SID "13757" Ports [1, 1] Position [475, 435, 510, 445] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "13758" Ports [2, 1] Position [345, 30, 385, 70] BlockMirror on NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,40,2,1,white,blue,0,140cc11c,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'" "q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "13759" Ports [2, 1] Position [465, 110, 495, 210] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,100,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 100 100 0 ],[0.77 0." "82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 100 100 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[54.44 " "54.44 58.44 54.44 58.44 58.44 58.44 54.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[50.44 50.44 54.44 54" ".44 50.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[46.44 46.44 50.44 50.44 46.44 ],[1 1 1 ])" ";\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[42.44 42.44 46.44 42.44 46.44 46.44 42.44 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\nco" "lor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc2" SID "13760" Ports [1, 1] Position [265, 143, 290, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc3" SID "13761" Ports [1, 1] Position [135, 178, 160, 192] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "yn" SID "13762" Position [545, 153, 575, 167] IconDisplay "Port number" } Block { BlockType Outport Name "accrm" SID "13763" Position [520, 288, 550, 302] Port "2" IconDisplay "Port number" } Line { SrcBlock "coeff" SrcPort 1 Points [95, 0; 0, 20; 50, 0] Branch { DstBlock "AddSub" DstPort 2 } Branch { Points [0, 275] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "bc2" SrcPort 1 DstBlock "AddSub" DstPort 3 } Line { SrcBlock "bc3" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "ld" SrcPort 1 Points [45, 0] Branch { DstBlock "bc3" DstPort 1 } Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "Register1" SrcPort 1 Points [-15, 0] DstBlock "AddSub" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 Points [15, 0] Branch { DstBlock "yn" DstPort 1 } Branch { Points [0, 50; 110, 0; 0, 385; -260, 0; 0, -110] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "AddSub" SrcPort 1 Points [0, 0; 5, 0] Branch { Points [40, 0] Branch { DstBlock "Register2" DstPort 1 } Branch { Points [0, -95] DstBlock "Register1" DstPort 1 } Branch { Points [0, 160] DstBlock "accrm" DstPort 1 } } Branch { Points [0, 305] DstBlock "Gateway Out8" DstPort 1 } } Line { SrcBlock "a" SrcPort 1 Points [140, 0] Branch { DstBlock "bc2" DstPort 1 } Branch { Points [0, 275] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "Gateway Out8" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out7" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out6" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out1" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out2" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out3" SrcPort 1 Points [50, 0] } Line { SrcBlock "rst" SrcPort 1 Points [90, 0] Branch { Points [255, 0; 0, -180] DstBlock "Register1" DstPort 2 } Branch { Points [0, 215] DstBlock "Gateway Out1" DstPort 1 } } } } Block { BlockType Reference Name "ROM" SID "13764" Ports [1, 1] Position [440, 328, 490, 372] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/ROM" SourceType "Xilinx Single Port Read-Only Memory Block" depth "length(coef2)" initVector "coef2" distributed_mem "Distributed memory" rst off init_reg "0" en off latency "1" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "longCorr_coef_nbits" bin_pt "longCorr_coef_bp" preci_type "Single" exp_width "8" frac_width "24" dbl_ovrd off optimize "Area" use_rpm off xl_use_area off xl_area "[1 1 0 1 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,308" block_type "sprom" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,44,1,1,white,blue,0,bbc23d60,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 44 44 0 ]);\npatch([11.65 20.32 26.32 32.32 38.32 26.32 17.65 11.65 ],[28.66" " 28.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([17.65 26.32 20.32 11.65 17.65 ],[22.66 22.66 28." "66 28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([11.65 20.32 26.32 17.65 11.65 ],[16.66 16.66 22.66 22.66 16.66 ]" ",[1 1 1 ]);\npatch([17.65 38.32 32.32 26.32 20.32 11.65 17.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'addr');\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end" " icon text');\n" } Block { BlockType Outport Name "x_dly" SID "13765" Position [790, 178, 820, 192] IconDisplay "Port number" } Block { BlockType Outport Name "x_dly_vout" SID "13766" Position [790, 223, 820, 237] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "y" SID "13767" Position [790, 293, 820, 307] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "y_vout" SID "13768" Position [785, 448, 815, 462] Port "4" IconDisplay "Port number" } Line { SrcBlock "From2" SrcPort 1 Points [145, 0] Branch { Points [90, 0] Branch { Points [0, -50] Branch { DstBlock "MAC" DstPort 3 } Branch { Points [0, -90; 160, 0] } } Branch { Points [0, 65] DstBlock "Delay" DstPort 1 } } Branch { Points [0, 260] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "ROM" SrcPort 1 Points [5, 0] Branch { Points [0, -35] DstBlock "MAC" DstPort 2 } Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "MAC" SrcPort 1 Points [0, -5; 15, 0] Branch { DstBlock "y" DstPort 1 } Branch { Points [0, 365] DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "ASR" SrcPort 1 Points [35, 0] Branch { DstBlock "MAC" DstPort 1 } Branch { Points [0, -105] DstBlock "x_dly" DstPort 1 } Branch { Points [0, 330] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "From1" SrcPort 1 Points [5, 0] Branch { DstBlock "ROM" DstPort 1 } Branch { Points [0, 330] DstBlock "Gateway Out5" DstPort 1 } } Line { SrcBlock "From" SrcPort 1 Points [90, 0] Branch { DstBlock "ASR" DstPort 2 } Branch { Points [0, 300] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "x" SrcPort 1 Points [100, 0] Branch { DstBlock "ASR" DstPort 1 } Branch { Points [0, 305] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "vin" SrcPort 1 Points [25, 0] Branch { DstBlock "ASR" DstPort 3 } Branch { Points [0, 100] Branch { Points [0, 195] DstBlock "Gateway Out8" DstPort 1 } Branch { Points [230, 0] DstBlock "MAC" DstPort 4 } } Branch { Points [0, -80] DstBlock "x_dly_vout" DstPort 1 } } Line { SrcBlock "Delay" SrcPort 1 DstBlock "y_vout" DstPort 1 } Line { Name "X Vin" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 Points [150, 0] } Line { Name "ASR Addr" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 Points [150, 0] } Line { Name "X In" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 Points [150, 0] } Line { Name "ASR Out" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 Points [150, 0] } Line { Name "ROM Out" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 Points [150, 0] } Line { Name "Corr Ld" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 Points [150, 0] } Line { Name "Corr Out" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 Points [150, 0] } Line { Name "ROM Addr" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 Points [150, 0] } } } Block { BlockType SubSystem Name "C4" SID "13769" Ports [4, 4] Position [630, 207, 700, 293] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskPromptString "Coefficients (all)|Sub-correlator Ind|Coef/correlator" MaskStyleString "edit,edit,edit" MaskVariables "h=@1;c_ind=@2;N=@3;" MaskTunableValueString "on,on,on" MaskCallbackString "||" MaskEnableString "on,on,on" MaskVisibilityString "on,on,on" MaskToolTipString "on,on,on" MaskInitialization "coef2 = h((c_ind*N+1) : (c_ind + 1)*N);" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "h|3|N" System { Name "C4" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "122" Block { BlockType Inport Name "x" SID "13770" Position [265, 263, 295, 277] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "vin" SID "13771" Position [270, 303, 300, 317] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "13772" Position [270, 458, 300, 472] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "13773" Position [270, 503, 300, 517] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "ASR" SID "13774" Ports [3, 1] Position [445, 260, 490, 320] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Addressable Shift Register" SourceType "Xilinx Addressable Shift Register Block" infoedit "Delay of configurable length. Any element in the delay line can be addressed and driven onto the" " output port.

Hardware notes: This block is implemented using SRL16s. If Virtex-4 or Spartan-3 device is " "used, multiple SRLC16s are cascaded together." infer_latency off depth "length(coef2)" initVector "[0]" en on dbl_ovrd off use_behavioral_HDL off Optimization "Resource" xl_use_area off xl_area "[1 0 0 2 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,401" block_type "addrsr" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,60,3,1,white,blue,0,f8ea6153,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 60 60 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 60 60 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[36.66 3" "6.66 42.66 36.66 42.66 42.66 42.66 36.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[30.66 30.66 36.66 " "36.66 30.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[24.66 24.66 30.66 30.66 24.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[18.66 18.66 24.66 18.66 24.66 24.66 18.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'addr');\ncolor('black');port_label('input',3," "'en');\ncolor('black');port_label('output',1,'q');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Delay" SID "13775" Ports [1, 1] Position [705, 441, 730, 469] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "25,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 " "17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33" " 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('blac" "k');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "13776" Position [210, 280, 300, 300] ZOrder -9 ShowName off GotoTag "ltsCorr_dAddr" TagVisibility "scoped" } Block { BlockType From Name "From1" SID "13777" Position [210, 340, 300, 360] ZOrder -9 ShowName off GotoTag "ltsCorr_cAddr" TagVisibility "scoped" } Block { BlockType From Name "From2" SID "13778" Position [210, 380, 300, 400] ZOrder -9 ShowName off GotoTag "ltsCorr_ld" TagVisibility "scoped" } Block { BlockType Reference Name "Gateway Out1" SID "13779" Ports [1, 1] Position [745, 615, 780, 625] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "13780" Ports [1, 1] Position [745, 630, 780, 640] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "13781" Ports [1, 1] Position [745, 645, 780, 655] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Ld" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "13782" Ports [1, 1] Position [745, 660, 780, 670] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "13783" Ports [1, 1] Position [745, 675, 780, 685] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "13784" Ports [1, 1] Position [745, 570, 780, 580] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X In" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "13785" Ports [1, 1] Position [745, 585, 780, 595] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "13786" Ports [1, 1] Position [745, 600, 780, 610] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X Vin" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType SubSystem Name "MAC" SID "13787" Ports [4, 2] Position [575, 279, 660, 376] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "MAC" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "a" SID "13788" Position [35, 143, 65, 157] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "coeff" SID "13789" Position [35, 108, 65, 122] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "ld" SID "13790" Position [35, 178, 65, 192] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "rst" SID "13791" Position [35, 233, 65, 247] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub" SID "13792" Ports [3, 1] Position [340, 113, 385, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition or Subtraction" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Signed (2's comp)" n_bits "long_cor_acc_n_bits" bin_pt "0" quantization "Truncate" overflow "Flag as error" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[2 0 0 4 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,344" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,3,1,white,blue,0,02f64c57,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('input',3,'su" "b');\ncolor('black');port_label('output',1,'\\bf{a \\pm b}','texmode','on');\nfprintf('','COMMENT: end icon text" "');\n" } Block { BlockType Reference Name "Gateway Out1" SID "13793" Ports [1, 1] Position [475, 450, 510, 460] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out2" SID "13794" Ports [1, 1] Position [475, 465, 510, 475] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out3" SID "13795" Ports [1, 1] Position [475, 480, 510, 490] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out6" SID "13796" Ports [1, 1] Position [475, 405, 510, 415] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out7" SID "13797" Ports [1, 1] Position [475, 420, 510, 430] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out8" SID "13798" Ports [1, 1] Position [475, 435, 510, 445] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "13799" Ports [2, 1] Position [345, 30, 385, 70] BlockMirror on NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,40,2,1,white,blue,0,140cc11c,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'" "q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "13800" Ports [2, 1] Position [465, 110, 495, 210] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,100,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 100 100 0 ],[0.77 0." "82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 100 100 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[54.44 " "54.44 58.44 54.44 58.44 58.44 58.44 54.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[50.44 50.44 54.44 54" ".44 50.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[46.44 46.44 50.44 50.44 46.44 ],[1 1 1 ])" ";\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[42.44 42.44 46.44 42.44 46.44 46.44 42.44 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\nco" "lor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc2" SID "13801" Ports [1, 1] Position [265, 143, 290, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc3" SID "13802" Ports [1, 1] Position [135, 178, 160, 192] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "yn" SID "13803" Position [545, 153, 575, 167] IconDisplay "Port number" } Block { BlockType Outport Name "accrm" SID "13804" Position [520, 288, 550, 302] Port "2" IconDisplay "Port number" } Line { SrcBlock "rst" SrcPort 1 Points [90, 0] Branch { Points [0, 215] DstBlock "Gateway Out1" DstPort 1 } Branch { Points [255, 0; 0, -180] DstBlock "Register1" DstPort 2 } } Line { SrcBlock "Gateway Out3" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out2" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out1" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out6" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out7" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out8" SrcPort 1 Points [50, 0] } Line { SrcBlock "a" SrcPort 1 Points [140, 0] Branch { Points [0, 275] DstBlock "Gateway Out7" DstPort 1 } Branch { DstBlock "bc2" DstPort 1 } } Line { SrcBlock "AddSub" SrcPort 1 Points [0, 0; 5, 0] Branch { Points [0, 305] DstBlock "Gateway Out8" DstPort 1 } Branch { Points [40, 0] Branch { Points [0, 160] DstBlock "accrm" DstPort 1 } Branch { Points [0, -95] DstBlock "Register1" DstPort 1 } Branch { DstBlock "Register2" DstPort 1 } } } Line { SrcBlock "Register2" SrcPort 1 Points [15, 0] Branch { Points [0, 50; 110, 0; 0, 385; -260, 0; 0, -110] DstBlock "Gateway Out3" DstPort 1 } Branch { DstBlock "yn" DstPort 1 } } Line { SrcBlock "Register1" SrcPort 1 Points [-15, 0] DstBlock "AddSub" DstPort 1 } Line { SrcBlock "ld" SrcPort 1 Points [45, 0] Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } Branch { DstBlock "bc3" DstPort 1 } } Line { SrcBlock "bc3" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "bc2" SrcPort 1 DstBlock "AddSub" DstPort 3 } Line { SrcBlock "coeff" SrcPort 1 Points [95, 0; 0, 20; 50, 0] Branch { Points [0, 275] DstBlock "Gateway Out6" DstPort 1 } Branch { DstBlock "AddSub" DstPort 2 } } } } Block { BlockType Reference Name "ROM" SID "13805" Ports [1, 1] Position [440, 328, 490, 372] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/ROM" SourceType "Xilinx Single Port Read-Only Memory Block" depth "length(coef2)" initVector "coef2" distributed_mem "Distributed memory" rst off init_reg "0" en off latency "1" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "longCorr_coef_nbits" bin_pt "longCorr_coef_bp" preci_type "Single" exp_width "8" frac_width "24" dbl_ovrd off optimize "Area" use_rpm off xl_use_area off xl_area "[1 1 0 1 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,308" block_type "sprom" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,44,1,1,white,blue,0,bbc23d60,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 44 44 0 ]);\npatch([11.65 20.32 26.32 32.32 38.32 26.32 17.65 11.65 ],[28.66" " 28.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([17.65 26.32 20.32 11.65 17.65 ],[22.66 22.66 28." "66 28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([11.65 20.32 26.32 17.65 11.65 ],[16.66 16.66 22.66 22.66 16.66 ]" ",[1 1 1 ]);\npatch([17.65 38.32 32.32 26.32 20.32 11.65 17.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'addr');\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end" " icon text');\n" } Block { BlockType Outport Name "x_dly" SID "13806" Position [790, 178, 820, 192] IconDisplay "Port number" } Block { BlockType Outport Name "x_dly_vout" SID "13807" Position [790, 223, 820, 237] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "y" SID "13808" Position [790, 293, 820, 307] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "y_vout" SID "13809" Position [785, 448, 815, 462] Port "4" IconDisplay "Port number" } Line { Name "ROM Addr" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 Points [150, 0] } Line { Name "Corr Out" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 Points [150, 0] } Line { Name "Corr Ld" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 Points [150, 0] } Line { Name "ROM Out" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 Points [150, 0] } Line { Name "ASR Out" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 Points [150, 0] } Line { Name "X In" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 Points [150, 0] } Line { Name "ASR Addr" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 Points [150, 0] } Line { Name "X Vin" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 Points [150, 0] } Line { SrcBlock "Delay" SrcPort 1 DstBlock "y_vout" DstPort 1 } Line { SrcBlock "vin" SrcPort 1 Points [25, 0] Branch { Points [0, -80] DstBlock "x_dly_vout" DstPort 1 } Branch { Points [0, 100] Branch { Points [230, 0] DstBlock "MAC" DstPort 4 } Branch { Points [0, 195] DstBlock "Gateway Out8" DstPort 1 } } Branch { DstBlock "ASR" DstPort 3 } } Line { SrcBlock "x" SrcPort 1 Points [100, 0] Branch { Points [0, 305] DstBlock "Gateway Out6" DstPort 1 } Branch { DstBlock "ASR" DstPort 1 } } Line { SrcBlock "From" SrcPort 1 Points [90, 0] Branch { Points [0, 300] DstBlock "Gateway Out7" DstPort 1 } Branch { DstBlock "ASR" DstPort 2 } } Line { SrcBlock "From1" SrcPort 1 Points [5, 0] Branch { Points [0, 330] DstBlock "Gateway Out5" DstPort 1 } Branch { DstBlock "ROM" DstPort 1 } } Line { SrcBlock "ASR" SrcPort 1 Points [35, 0] Branch { Points [0, 330] DstBlock "Gateway Out1" DstPort 1 } Branch { Points [0, -105] DstBlock "x_dly" DstPort 1 } Branch { DstBlock "MAC" DstPort 1 } } Line { SrcBlock "MAC" SrcPort 1 Points [0, -5; 15, 0] Branch { Points [0, 365] DstBlock "Gateway Out4" DstPort 1 } Branch { DstBlock "y" DstPort 1 } } Line { SrcBlock "ROM" SrcPort 1 Points [5, 0] Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } Branch { Points [0, -35] DstBlock "MAC" DstPort 2 } } Line { SrcBlock "From2" SrcPort 1 Points [145, 0] Branch { Points [0, 260] DstBlock "Gateway Out3" DstPort 1 } Branch { Points [90, 0] Branch { Points [0, 65] DstBlock "Delay" DstPort 1 } Branch { Points [0, -50] Branch { Points [0, -90; 160, 0] } Branch { DstBlock "MAC" DstPort 3 } } } } } } Block { BlockType SubSystem Name "C5" SID "13810" Ports [4, 4] Position [740, 207, 810, 293] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskPromptString "Coefficients (all)|Sub-correlator Ind|Coef/correlator" MaskStyleString "edit,edit,edit" MaskVariables "h=@1;c_ind=@2;N=@3;" MaskTunableValueString "on,on,on" MaskCallbackString "||" MaskEnableString "on,on,on" MaskVisibilityString "on,on,on" MaskToolTipString "on,on,on" MaskInitialization "coef2 = h((c_ind*N+1) : (c_ind + 1)*N);" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "h|4|N" System { Name "C5" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "122" Block { BlockType Inport Name "x" SID "13811" Position [265, 263, 295, 277] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "vin" SID "13812" Position [270, 303, 300, 317] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "13813" Position [270, 458, 300, 472] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "13814" Position [270, 503, 300, 517] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "ASR" SID "13815" Ports [3, 1] Position [445, 260, 490, 320] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Addressable Shift Register" SourceType "Xilinx Addressable Shift Register Block" infoedit "Delay of configurable length. Any element in the delay line can be addressed and driven onto the" " output port.

Hardware notes: This block is implemented using SRL16s. If Virtex-4 or Spartan-3 device is " "used, multiple SRLC16s are cascaded together." infer_latency off depth "length(coef2)" initVector "[0]" en on dbl_ovrd off use_behavioral_HDL off Optimization "Resource" xl_use_area off xl_area "[1 0 0 2 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,401" block_type "addrsr" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,60,3,1,white,blue,0,f8ea6153,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 60 60 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 60 60 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[36.66 3" "6.66 42.66 36.66 42.66 42.66 42.66 36.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[30.66 30.66 36.66 " "36.66 30.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[24.66 24.66 30.66 30.66 24.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[18.66 18.66 24.66 18.66 24.66 24.66 18.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'addr');\ncolor('black');port_label('input',3," "'en');\ncolor('black');port_label('output',1,'q');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Delay" SID "13816" Ports [1, 1] Position [705, 441, 730, 469] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "25,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 " "17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33" " 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('blac" "k');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "13817" Position [210, 280, 300, 300] ZOrder -9 ShowName off GotoTag "ltsCorr_dAddr" TagVisibility "scoped" } Block { BlockType From Name "From1" SID "13818" Position [210, 340, 300, 360] ZOrder -9 ShowName off GotoTag "ltsCorr_cAddr" TagVisibility "scoped" } Block { BlockType From Name "From2" SID "13819" Position [210, 380, 300, 400] ZOrder -9 ShowName off GotoTag "ltsCorr_ld" TagVisibility "scoped" } Block { BlockType Reference Name "Gateway Out1" SID "13820" Ports [1, 1] Position [745, 615, 780, 625] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "13821" Ports [1, 1] Position [745, 630, 780, 640] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "13822" Ports [1, 1] Position [745, 645, 780, 655] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Ld" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "13823" Ports [1, 1] Position [745, 660, 780, 670] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "13824" Ports [1, 1] Position [745, 675, 780, 685] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "13825" Ports [1, 1] Position [745, 570, 780, 580] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X In" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "13826" Ports [1, 1] Position [745, 585, 780, 595] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "13827" Ports [1, 1] Position [745, 600, 780, 610] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X Vin" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType SubSystem Name "MAC" SID "13828" Ports [4, 2] Position [575, 279, 660, 376] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "MAC" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "a" SID "13829" Position [35, 143, 65, 157] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "coeff" SID "13830" Position [35, 108, 65, 122] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "ld" SID "13831" Position [35, 178, 65, 192] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "rst" SID "13832" Position [35, 233, 65, 247] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub" SID "13833" Ports [3, 1] Position [340, 113, 385, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition or Subtraction" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Signed (2's comp)" n_bits "long_cor_acc_n_bits" bin_pt "0" quantization "Truncate" overflow "Flag as error" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[2 0 0 4 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,344" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,3,1,white,blue,0,02f64c57,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('input',3,'su" "b');\ncolor('black');port_label('output',1,'\\bf{a \\pm b}','texmode','on');\nfprintf('','COMMENT: end icon text" "');\n" } Block { BlockType Reference Name "Gateway Out1" SID "13834" Ports [1, 1] Position [475, 450, 510, 460] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out2" SID "13835" Ports [1, 1] Position [475, 465, 510, 475] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out3" SID "13836" Ports [1, 1] Position [475, 480, 510, 490] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out6" SID "13837" Ports [1, 1] Position [475, 405, 510, 415] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out7" SID "13838" Ports [1, 1] Position [475, 420, 510, 430] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out8" SID "13839" Ports [1, 1] Position [475, 435, 510, 445] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "13840" Ports [2, 1] Position [345, 30, 385, 70] BlockMirror on NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,40,2,1,white,blue,0,140cc11c,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'" "q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "13841" Ports [2, 1] Position [465, 110, 495, 210] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,100,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 100 100 0 ],[0.77 0." "82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 100 100 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[54.44 " "54.44 58.44 54.44 58.44 58.44 58.44 54.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[50.44 50.44 54.44 54" ".44 50.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[46.44 46.44 50.44 50.44 46.44 ],[1 1 1 ])" ";\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[42.44 42.44 46.44 42.44 46.44 46.44 42.44 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\nco" "lor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc2" SID "13842" Ports [1, 1] Position [265, 143, 290, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc3" SID "13843" Ports [1, 1] Position [135, 178, 160, 192] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "yn" SID "13844" Position [545, 153, 575, 167] IconDisplay "Port number" } Block { BlockType Outport Name "accrm" SID "13845" Position [520, 288, 550, 302] Port "2" IconDisplay "Port number" } Line { SrcBlock "coeff" SrcPort 1 Points [95, 0; 0, 20; 50, 0] Branch { DstBlock "AddSub" DstPort 2 } Branch { Points [0, 275] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "bc2" SrcPort 1 DstBlock "AddSub" DstPort 3 } Line { SrcBlock "bc3" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "ld" SrcPort 1 Points [45, 0] Branch { DstBlock "bc3" DstPort 1 } Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "Register1" SrcPort 1 Points [-15, 0] DstBlock "AddSub" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 Points [15, 0] Branch { DstBlock "yn" DstPort 1 } Branch { Points [0, 50; 110, 0; 0, 385; -260, 0; 0, -110] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "AddSub" SrcPort 1 Points [0, 0; 5, 0] Branch { Points [40, 0] Branch { DstBlock "Register2" DstPort 1 } Branch { Points [0, -95] DstBlock "Register1" DstPort 1 } Branch { Points [0, 160] DstBlock "accrm" DstPort 1 } } Branch { Points [0, 305] DstBlock "Gateway Out8" DstPort 1 } } Line { SrcBlock "a" SrcPort 1 Points [140, 0] Branch { DstBlock "bc2" DstPort 1 } Branch { Points [0, 275] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "Gateway Out8" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out7" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out6" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out1" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out2" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out3" SrcPort 1 Points [50, 0] } Line { SrcBlock "rst" SrcPort 1 Points [90, 0] Branch { Points [255, 0; 0, -180] DstBlock "Register1" DstPort 2 } Branch { Points [0, 215] DstBlock "Gateway Out1" DstPort 1 } } } } Block { BlockType Reference Name "ROM" SID "13846" Ports [1, 1] Position [440, 328, 490, 372] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/ROM" SourceType "Xilinx Single Port Read-Only Memory Block" depth "length(coef2)" initVector "coef2" distributed_mem "Distributed memory" rst off init_reg "0" en off latency "1" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "longCorr_coef_nbits" bin_pt "longCorr_coef_bp" preci_type "Single" exp_width "8" frac_width "24" dbl_ovrd off optimize "Area" use_rpm off xl_use_area off xl_area "[1 1 0 1 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,308" block_type "sprom" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,44,1,1,white,blue,0,bbc23d60,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 44 44 0 ]);\npatch([11.65 20.32 26.32 32.32 38.32 26.32 17.65 11.65 ],[28.66" " 28.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([17.65 26.32 20.32 11.65 17.65 ],[22.66 22.66 28." "66 28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([11.65 20.32 26.32 17.65 11.65 ],[16.66 16.66 22.66 22.66 16.66 ]" ",[1 1 1 ]);\npatch([17.65 38.32 32.32 26.32 20.32 11.65 17.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'addr');\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end" " icon text');\n" } Block { BlockType Outport Name "x_dly" SID "13847" Position [790, 178, 820, 192] IconDisplay "Port number" } Block { BlockType Outport Name "x_dly_vout" SID "13848" Position [790, 223, 820, 237] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "y" SID "13849" Position [790, 293, 820, 307] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "y_vout" SID "13850" Position [785, 448, 815, 462] Port "4" IconDisplay "Port number" } Line { SrcBlock "From2" SrcPort 1 Points [145, 0] Branch { Points [90, 0] Branch { Points [0, -50] Branch { DstBlock "MAC" DstPort 3 } Branch { Points [0, -90; 160, 0] } } Branch { Points [0, 65] DstBlock "Delay" DstPort 1 } } Branch { Points [0, 260] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "ROM" SrcPort 1 Points [5, 0] Branch { Points [0, -35] DstBlock "MAC" DstPort 2 } Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "MAC" SrcPort 1 Points [0, -5; 15, 0] Branch { DstBlock "y" DstPort 1 } Branch { Points [0, 365] DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "ASR" SrcPort 1 Points [35, 0] Branch { DstBlock "MAC" DstPort 1 } Branch { Points [0, -105] DstBlock "x_dly" DstPort 1 } Branch { Points [0, 330] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "From1" SrcPort 1 Points [5, 0] Branch { DstBlock "ROM" DstPort 1 } Branch { Points [0, 330] DstBlock "Gateway Out5" DstPort 1 } } Line { SrcBlock "From" SrcPort 1 Points [90, 0] Branch { DstBlock "ASR" DstPort 2 } Branch { Points [0, 300] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "x" SrcPort 1 Points [100, 0] Branch { DstBlock "ASR" DstPort 1 } Branch { Points [0, 305] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "vin" SrcPort 1 Points [25, 0] Branch { DstBlock "ASR" DstPort 3 } Branch { Points [0, 100] Branch { Points [0, 195] DstBlock "Gateway Out8" DstPort 1 } Branch { Points [230, 0] DstBlock "MAC" DstPort 4 } } Branch { Points [0, -80] DstBlock "x_dly_vout" DstPort 1 } } Line { SrcBlock "Delay" SrcPort 1 DstBlock "y_vout" DstPort 1 } Line { Name "X Vin" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 Points [150, 0] } Line { Name "ASR Addr" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 Points [150, 0] } Line { Name "X In" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 Points [150, 0] } Line { Name "ASR Out" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 Points [150, 0] } Line { Name "ROM Out" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 Points [150, 0] } Line { Name "Corr Ld" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 Points [150, 0] } Line { Name "Corr Out" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 Points [150, 0] } Line { Name "ROM Addr" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 Points [150, 0] } } } Block { BlockType SubSystem Name "C6" SID "13851" Ports [4, 4] Position [845, 207, 915, 293] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskPromptString "Coefficients (all)|Sub-correlator Ind|Coef/correlator" MaskStyleString "edit,edit,edit" MaskVariables "h=@1;c_ind=@2;N=@3;" MaskTunableValueString "on,on,on" MaskCallbackString "||" MaskEnableString "on,on,on" MaskVisibilityString "on,on,on" MaskToolTipString "on,on,on" MaskInitialization "coef2 = h((c_ind*N+1) : (c_ind + 1)*N);" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "h|5|N" System { Name "C6" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "122" Block { BlockType Inport Name "x" SID "13852" Position [265, 263, 295, 277] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "vin" SID "13853" Position [270, 303, 300, 317] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "13854" Position [270, 458, 300, 472] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "13855" Position [270, 503, 300, 517] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "ASR" SID "13856" Ports [3, 1] Position [445, 260, 490, 320] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Addressable Shift Register" SourceType "Xilinx Addressable Shift Register Block" infoedit "Delay of configurable length. Any element in the delay line can be addressed and driven onto the" " output port.

Hardware notes: This block is implemented using SRL16s. If Virtex-4 or Spartan-3 device is " "used, multiple SRLC16s are cascaded together." infer_latency off depth "length(coef2)" initVector "[0]" en on dbl_ovrd off use_behavioral_HDL off Optimization "Resource" xl_use_area off xl_area "[1 0 0 2 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,401" block_type "addrsr" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,60,3,1,white,blue,0,f8ea6153,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 60 60 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 60 60 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[36.66 3" "6.66 42.66 36.66 42.66 42.66 42.66 36.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[30.66 30.66 36.66 " "36.66 30.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[24.66 24.66 30.66 30.66 24.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[18.66 18.66 24.66 18.66 24.66 24.66 18.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'addr');\ncolor('black');port_label('input',3," "'en');\ncolor('black');port_label('output',1,'q');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Delay" SID "13857" Ports [1, 1] Position [705, 441, 730, 469] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "25,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 " "17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33" " 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('blac" "k');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "13858" Position [210, 280, 300, 300] ZOrder -9 ShowName off GotoTag "ltsCorr_dAddr" TagVisibility "scoped" } Block { BlockType From Name "From1" SID "13859" Position [210, 340, 300, 360] ZOrder -9 ShowName off GotoTag "ltsCorr_cAddr" TagVisibility "scoped" } Block { BlockType From Name "From2" SID "13860" Position [210, 380, 300, 400] ZOrder -9 ShowName off GotoTag "ltsCorr_ld" TagVisibility "scoped" } Block { BlockType Reference Name "Gateway Out1" SID "13861" Ports [1, 1] Position [745, 615, 780, 625] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "13862" Ports [1, 1] Position [745, 630, 780, 640] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "13863" Ports [1, 1] Position [745, 645, 780, 655] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Ld" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "13864" Ports [1, 1] Position [745, 660, 780, 670] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "13865" Ports [1, 1] Position [745, 675, 780, 685] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "13866" Ports [1, 1] Position [745, 570, 780, 580] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X In" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "13867" Ports [1, 1] Position [745, 585, 780, 595] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "13868" Ports [1, 1] Position [745, 600, 780, 610] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X Vin" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType SubSystem Name "MAC" SID "13869" Ports [4, 2] Position [575, 279, 660, 376] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "MAC" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "a" SID "13870" Position [35, 143, 65, 157] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "coeff" SID "13871" Position [35, 108, 65, 122] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "ld" SID "13872" Position [35, 178, 65, 192] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "rst" SID "13873" Position [35, 233, 65, 247] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub" SID "13874" Ports [3, 1] Position [340, 113, 385, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition or Subtraction" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Signed (2's comp)" n_bits "long_cor_acc_n_bits" bin_pt "0" quantization "Truncate" overflow "Flag as error" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[2 0 0 4 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,344" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,3,1,white,blue,0,02f64c57,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('input',3,'su" "b');\ncolor('black');port_label('output',1,'\\bf{a \\pm b}','texmode','on');\nfprintf('','COMMENT: end icon text" "');\n" } Block { BlockType Reference Name "Gateway Out1" SID "13875" Ports [1, 1] Position [475, 450, 510, 460] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out2" SID "13876" Ports [1, 1] Position [475, 465, 510, 475] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out3" SID "13877" Ports [1, 1] Position [475, 480, 510, 490] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out6" SID "13878" Ports [1, 1] Position [475, 405, 510, 415] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out7" SID "13879" Ports [1, 1] Position [475, 420, 510, 430] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out8" SID "13880" Ports [1, 1] Position [475, 435, 510, 445] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "13881" Ports [2, 1] Position [345, 30, 385, 70] BlockMirror on NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,40,2,1,white,blue,0,140cc11c,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'" "q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "13882" Ports [2, 1] Position [465, 110, 495, 210] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,100,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 100 100 0 ],[0.77 0." "82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 100 100 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[54.44 " "54.44 58.44 54.44 58.44 58.44 58.44 54.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[50.44 50.44 54.44 54" ".44 50.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[46.44 46.44 50.44 50.44 46.44 ],[1 1 1 ])" ";\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[42.44 42.44 46.44 42.44 46.44 46.44 42.44 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\nco" "lor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc2" SID "13883" Ports [1, 1] Position [265, 143, 290, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc3" SID "13884" Ports [1, 1] Position [135, 178, 160, 192] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "yn" SID "13885" Position [545, 153, 575, 167] IconDisplay "Port number" } Block { BlockType Outport Name "accrm" SID "13886" Position [520, 288, 550, 302] Port "2" IconDisplay "Port number" } Line { SrcBlock "rst" SrcPort 1 Points [90, 0] Branch { Points [0, 215] DstBlock "Gateway Out1" DstPort 1 } Branch { Points [255, 0; 0, -180] DstBlock "Register1" DstPort 2 } } Line { SrcBlock "Gateway Out3" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out2" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out1" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out6" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out7" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out8" SrcPort 1 Points [50, 0] } Line { SrcBlock "a" SrcPort 1 Points [140, 0] Branch { Points [0, 275] DstBlock "Gateway Out7" DstPort 1 } Branch { DstBlock "bc2" DstPort 1 } } Line { SrcBlock "AddSub" SrcPort 1 Points [0, 0; 5, 0] Branch { Points [0, 305] DstBlock "Gateway Out8" DstPort 1 } Branch { Points [40, 0] Branch { Points [0, 160] DstBlock "accrm" DstPort 1 } Branch { Points [0, -95] DstBlock "Register1" DstPort 1 } Branch { DstBlock "Register2" DstPort 1 } } } Line { SrcBlock "Register2" SrcPort 1 Points [15, 0] Branch { Points [0, 50; 110, 0; 0, 385; -260, 0; 0, -110] DstBlock "Gateway Out3" DstPort 1 } Branch { DstBlock "yn" DstPort 1 } } Line { SrcBlock "Register1" SrcPort 1 Points [-15, 0] DstBlock "AddSub" DstPort 1 } Line { SrcBlock "ld" SrcPort 1 Points [45, 0] Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } Branch { DstBlock "bc3" DstPort 1 } } Line { SrcBlock "bc3" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "bc2" SrcPort 1 DstBlock "AddSub" DstPort 3 } Line { SrcBlock "coeff" SrcPort 1 Points [95, 0; 0, 20; 50, 0] Branch { Points [0, 275] DstBlock "Gateway Out6" DstPort 1 } Branch { DstBlock "AddSub" DstPort 2 } } } } Block { BlockType Reference Name "ROM" SID "13887" Ports [1, 1] Position [440, 328, 490, 372] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/ROM" SourceType "Xilinx Single Port Read-Only Memory Block" depth "length(coef2)" initVector "coef2" distributed_mem "Distributed memory" rst off init_reg "0" en off latency "1" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "longCorr_coef_nbits" bin_pt "longCorr_coef_bp" preci_type "Single" exp_width "8" frac_width "24" dbl_ovrd off optimize "Area" use_rpm off xl_use_area off xl_area "[1 1 0 1 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,308" block_type "sprom" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,44,1,1,white,blue,0,bbc23d60,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 44 44 0 ]);\npatch([11.65 20.32 26.32 32.32 38.32 26.32 17.65 11.65 ],[28.66" " 28.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([17.65 26.32 20.32 11.65 17.65 ],[22.66 22.66 28." "66 28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([11.65 20.32 26.32 17.65 11.65 ],[16.66 16.66 22.66 22.66 16.66 ]" ",[1 1 1 ]);\npatch([17.65 38.32 32.32 26.32 20.32 11.65 17.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'addr');\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end" " icon text');\n" } Block { BlockType Outport Name "x_dly" SID "13888" Position [790, 178, 820, 192] IconDisplay "Port number" } Block { BlockType Outport Name "x_dly_vout" SID "13889" Position [790, 223, 820, 237] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "y" SID "13890" Position [790, 293, 820, 307] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "y_vout" SID "13891" Position [785, 448, 815, 462] Port "4" IconDisplay "Port number" } Line { Name "ROM Addr" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 Points [150, 0] } Line { Name "Corr Out" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 Points [150, 0] } Line { Name "Corr Ld" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 Points [150, 0] } Line { Name "ROM Out" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 Points [150, 0] } Line { Name "ASR Out" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 Points [150, 0] } Line { Name "X In" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 Points [150, 0] } Line { Name "ASR Addr" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 Points [150, 0] } Line { Name "X Vin" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 Points [150, 0] } Line { SrcBlock "Delay" SrcPort 1 DstBlock "y_vout" DstPort 1 } Line { SrcBlock "vin" SrcPort 1 Points [25, 0] Branch { Points [0, -80] DstBlock "x_dly_vout" DstPort 1 } Branch { Points [0, 100] Branch { Points [230, 0] DstBlock "MAC" DstPort 4 } Branch { Points [0, 195] DstBlock "Gateway Out8" DstPort 1 } } Branch { DstBlock "ASR" DstPort 3 } } Line { SrcBlock "x" SrcPort 1 Points [100, 0] Branch { Points [0, 305] DstBlock "Gateway Out6" DstPort 1 } Branch { DstBlock "ASR" DstPort 1 } } Line { SrcBlock "From" SrcPort 1 Points [90, 0] Branch { Points [0, 300] DstBlock "Gateway Out7" DstPort 1 } Branch { DstBlock "ASR" DstPort 2 } } Line { SrcBlock "From1" SrcPort 1 Points [5, 0] Branch { Points [0, 330] DstBlock "Gateway Out5" DstPort 1 } Branch { DstBlock "ROM" DstPort 1 } } Line { SrcBlock "ASR" SrcPort 1 Points [35, 0] Branch { Points [0, 330] DstBlock "Gateway Out1" DstPort 1 } Branch { Points [0, -105] DstBlock "x_dly" DstPort 1 } Branch { DstBlock "MAC" DstPort 1 } } Line { SrcBlock "MAC" SrcPort 1 Points [0, -5; 15, 0] Branch { Points [0, 365] DstBlock "Gateway Out4" DstPort 1 } Branch { DstBlock "y" DstPort 1 } } Line { SrcBlock "ROM" SrcPort 1 Points [5, 0] Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } Branch { Points [0, -35] DstBlock "MAC" DstPort 2 } } Line { SrcBlock "From2" SrcPort 1 Points [145, 0] Branch { Points [0, 260] DstBlock "Gateway Out3" DstPort 1 } Branch { Points [90, 0] Branch { Points [0, 65] DstBlock "Delay" DstPort 1 } Branch { Points [0, -50] Branch { Points [0, -90; 160, 0] } Branch { DstBlock "MAC" DstPort 3 } } } } } } Block { BlockType SubSystem Name "C7" SID "13892" Ports [4, 4] Position [950, 207, 1020, 293] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskPromptString "Coefficients (all)|Sub-correlator Ind|Coef/correlator" MaskStyleString "edit,edit,edit" MaskVariables "h=@1;c_ind=@2;N=@3;" MaskTunableValueString "on,on,on" MaskCallbackString "||" MaskEnableString "on,on,on" MaskVisibilityString "on,on,on" MaskToolTipString "on,on,on" MaskInitialization "coef2 = h((c_ind*N+1) : (c_ind + 1)*N);" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "h|6|N" System { Name "C7" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "122" Block { BlockType Inport Name "x" SID "13893" Position [265, 263, 295, 277] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "vin" SID "13894" Position [270, 303, 300, 317] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "13895" Position [270, 458, 300, 472] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "13896" Position [270, 503, 300, 517] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "ASR" SID "13897" Ports [3, 1] Position [445, 260, 490, 320] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Addressable Shift Register" SourceType "Xilinx Addressable Shift Register Block" infoedit "Delay of configurable length. Any element in the delay line can be addressed and driven onto the" " output port.

Hardware notes: This block is implemented using SRL16s. If Virtex-4 or Spartan-3 device is " "used, multiple SRLC16s are cascaded together." infer_latency off depth "length(coef2)" initVector "[0]" en on dbl_ovrd off use_behavioral_HDL off Optimization "Resource" xl_use_area off xl_area "[1 0 0 2 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,401" block_type "addrsr" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,60,3,1,white,blue,0,f8ea6153,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 60 60 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 60 60 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[36.66 3" "6.66 42.66 36.66 42.66 42.66 42.66 36.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[30.66 30.66 36.66 " "36.66 30.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[24.66 24.66 30.66 30.66 24.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[18.66 18.66 24.66 18.66 24.66 24.66 18.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'addr');\ncolor('black');port_label('input',3," "'en');\ncolor('black');port_label('output',1,'q');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Delay" SID "13898" Ports [1, 1] Position [705, 441, 730, 469] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "25,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 " "17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33" " 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('blac" "k');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "13899" Position [210, 280, 300, 300] ZOrder -9 ShowName off GotoTag "ltsCorr_dAddr" TagVisibility "scoped" } Block { BlockType From Name "From1" SID "13900" Position [210, 340, 300, 360] ZOrder -9 ShowName off GotoTag "ltsCorr_cAddr" TagVisibility "scoped" } Block { BlockType From Name "From2" SID "13901" Position [210, 380, 300, 400] ZOrder -9 ShowName off GotoTag "ltsCorr_ld" TagVisibility "scoped" } Block { BlockType Reference Name "Gateway Out1" SID "13902" Ports [1, 1] Position [745, 615, 780, 625] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "13903" Ports [1, 1] Position [745, 630, 780, 640] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "13904" Ports [1, 1] Position [745, 645, 780, 655] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Ld" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "13905" Ports [1, 1] Position [745, 660, 780, 670] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "13906" Ports [1, 1] Position [745, 675, 780, 685] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "13907" Ports [1, 1] Position [745, 570, 780, 580] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X In" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "13908" Ports [1, 1] Position [745, 585, 780, 595] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "13909" Ports [1, 1] Position [745, 600, 780, 610] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X Vin" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType SubSystem Name "MAC" SID "13910" Ports [4, 2] Position [575, 279, 660, 376] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "MAC" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "a" SID "13911" Position [35, 143, 65, 157] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "coeff" SID "13912" Position [35, 108, 65, 122] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "ld" SID "13913" Position [35, 178, 65, 192] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "rst" SID "13914" Position [35, 233, 65, 247] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub" SID "13915" Ports [3, 1] Position [340, 113, 385, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition or Subtraction" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Signed (2's comp)" n_bits "long_cor_acc_n_bits" bin_pt "0" quantization "Truncate" overflow "Flag as error" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[2 0 0 4 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,344" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,3,1,white,blue,0,02f64c57,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('input',3,'su" "b');\ncolor('black');port_label('output',1,'\\bf{a \\pm b}','texmode','on');\nfprintf('','COMMENT: end icon text" "');\n" } Block { BlockType Reference Name "Gateway Out1" SID "13916" Ports [1, 1] Position [475, 450, 510, 460] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out2" SID "13917" Ports [1, 1] Position [475, 465, 510, 475] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out3" SID "13918" Ports [1, 1] Position [475, 480, 510, 490] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out6" SID "13919" Ports [1, 1] Position [475, 405, 510, 415] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out7" SID "13920" Ports [1, 1] Position [475, 420, 510, 430] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out8" SID "13921" Ports [1, 1] Position [475, 435, 510, 445] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "13922" Ports [2, 1] Position [345, 30, 385, 70] BlockMirror on NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,40,2,1,white,blue,0,140cc11c,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'" "q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "13923" Ports [2, 1] Position [465, 110, 495, 210] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,100,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 100 100 0 ],[0.77 0." "82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 100 100 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[54.44 " "54.44 58.44 54.44 58.44 58.44 58.44 54.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[50.44 50.44 54.44 54" ".44 50.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[46.44 46.44 50.44 50.44 46.44 ],[1 1 1 ])" ";\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[42.44 42.44 46.44 42.44 46.44 46.44 42.44 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\nco" "lor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc2" SID "13924" Ports [1, 1] Position [265, 143, 290, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc3" SID "13925" Ports [1, 1] Position [135, 178, 160, 192] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "yn" SID "13926" Position [545, 153, 575, 167] IconDisplay "Port number" } Block { BlockType Outport Name "accrm" SID "13927" Position [520, 288, 550, 302] Port "2" IconDisplay "Port number" } Line { SrcBlock "coeff" SrcPort 1 Points [95, 0; 0, 20; 50, 0] Branch { DstBlock "AddSub" DstPort 2 } Branch { Points [0, 275] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "bc2" SrcPort 1 DstBlock "AddSub" DstPort 3 } Line { SrcBlock "bc3" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "ld" SrcPort 1 Points [45, 0] Branch { DstBlock "bc3" DstPort 1 } Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "Register1" SrcPort 1 Points [-15, 0] DstBlock "AddSub" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 Points [15, 0] Branch { DstBlock "yn" DstPort 1 } Branch { Points [0, 50; 110, 0; 0, 385; -260, 0; 0, -110] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "AddSub" SrcPort 1 Points [0, 0; 5, 0] Branch { Points [40, 0] Branch { DstBlock "Register2" DstPort 1 } Branch { Points [0, -95] DstBlock "Register1" DstPort 1 } Branch { Points [0, 160] DstBlock "accrm" DstPort 1 } } Branch { Points [0, 305] DstBlock "Gateway Out8" DstPort 1 } } Line { SrcBlock "a" SrcPort 1 Points [140, 0] Branch { DstBlock "bc2" DstPort 1 } Branch { Points [0, 275] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "Gateway Out8" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out7" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out6" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out1" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out2" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out3" SrcPort 1 Points [50, 0] } Line { SrcBlock "rst" SrcPort 1 Points [90, 0] Branch { Points [255, 0; 0, -180] DstBlock "Register1" DstPort 2 } Branch { Points [0, 215] DstBlock "Gateway Out1" DstPort 1 } } } } Block { BlockType Reference Name "ROM" SID "13928" Ports [1, 1] Position [440, 328, 490, 372] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/ROM" SourceType "Xilinx Single Port Read-Only Memory Block" depth "length(coef2)" initVector "coef2" distributed_mem "Distributed memory" rst off init_reg "0" en off latency "1" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "longCorr_coef_nbits" bin_pt "longCorr_coef_bp" preci_type "Single" exp_width "8" frac_width "24" dbl_ovrd off optimize "Area" use_rpm off xl_use_area off xl_area "[1 1 0 1 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,308" block_type "sprom" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,44,1,1,white,blue,0,bbc23d60,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 44 44 0 ]);\npatch([11.65 20.32 26.32 32.32 38.32 26.32 17.65 11.65 ],[28.66" " 28.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([17.65 26.32 20.32 11.65 17.65 ],[22.66 22.66 28." "66 28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([11.65 20.32 26.32 17.65 11.65 ],[16.66 16.66 22.66 22.66 16.66 ]" ",[1 1 1 ]);\npatch([17.65 38.32 32.32 26.32 20.32 11.65 17.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'addr');\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end" " icon text');\n" } Block { BlockType Outport Name "x_dly" SID "13929" Position [790, 178, 820, 192] IconDisplay "Port number" } Block { BlockType Outport Name "x_dly_vout" SID "13930" Position [790, 223, 820, 237] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "y" SID "13931" Position [790, 293, 820, 307] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "y_vout" SID "13932" Position [785, 448, 815, 462] Port "4" IconDisplay "Port number" } Line { SrcBlock "From2" SrcPort 1 Points [145, 0] Branch { Points [90, 0] Branch { Points [0, -50] Branch { DstBlock "MAC" DstPort 3 } Branch { Points [0, -90; 160, 0] } } Branch { Points [0, 65] DstBlock "Delay" DstPort 1 } } Branch { Points [0, 260] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "ROM" SrcPort 1 Points [5, 0] Branch { Points [0, -35] DstBlock "MAC" DstPort 2 } Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "MAC" SrcPort 1 Points [0, -5; 15, 0] Branch { DstBlock "y" DstPort 1 } Branch { Points [0, 365] DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "ASR" SrcPort 1 Points [35, 0] Branch { DstBlock "MAC" DstPort 1 } Branch { Points [0, -105] DstBlock "x_dly" DstPort 1 } Branch { Points [0, 330] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "From1" SrcPort 1 Points [5, 0] Branch { DstBlock "ROM" DstPort 1 } Branch { Points [0, 330] DstBlock "Gateway Out5" DstPort 1 } } Line { SrcBlock "From" SrcPort 1 Points [90, 0] Branch { DstBlock "ASR" DstPort 2 } Branch { Points [0, 300] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "x" SrcPort 1 Points [100, 0] Branch { DstBlock "ASR" DstPort 1 } Branch { Points [0, 305] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "vin" SrcPort 1 Points [25, 0] Branch { DstBlock "ASR" DstPort 3 } Branch { Points [0, 100] Branch { Points [0, 195] DstBlock "Gateway Out8" DstPort 1 } Branch { Points [230, 0] DstBlock "MAC" DstPort 4 } } Branch { Points [0, -80] DstBlock "x_dly_vout" DstPort 1 } } Line { SrcBlock "Delay" SrcPort 1 DstBlock "y_vout" DstPort 1 } Line { Name "X Vin" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 Points [150, 0] } Line { Name "ASR Addr" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 Points [150, 0] } Line { Name "X In" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 Points [150, 0] } Line { Name "ASR Out" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 Points [150, 0] } Line { Name "ROM Out" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 Points [150, 0] } Line { Name "Corr Ld" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 Points [150, 0] } Line { Name "Corr Out" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 Points [150, 0] } Line { Name "ROM Addr" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 Points [150, 0] } } } Block { BlockType SubSystem Name "C8" SID "13933" Ports [4, 4] Position [1060, 207, 1130, 293] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskPromptString "Coefficients (all)|Sub-correlator Ind|Coef/correlator" MaskStyleString "edit,edit,edit" MaskVariables "h=@1;c_ind=@2;N=@3;" MaskTunableValueString "on,on,on" MaskCallbackString "||" MaskEnableString "on,on,on" MaskVisibilityString "on,on,on" MaskToolTipString "on,on,on" MaskInitialization "coef2 = h((c_ind*N+1) : (c_ind + 1)*N);" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "h|7|N" System { Name "C8" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "122" Block { BlockType Inport Name "x" SID "13934" Position [265, 263, 295, 277] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "vin" SID "13935" Position [270, 303, 300, 317] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "13936" Position [270, 458, 300, 472] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "13937" Position [270, 503, 300, 517] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "ASR" SID "13938" Ports [3, 1] Position [445, 260, 490, 320] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Addressable Shift Register" SourceType "Xilinx Addressable Shift Register Block" infoedit "Delay of configurable length. Any element in the delay line can be addressed and driven onto the" " output port.

Hardware notes: This block is implemented using SRL16s. If Virtex-4 or Spartan-3 device is " "used, multiple SRLC16s are cascaded together." infer_latency off depth "length(coef2)" initVector "[0]" en on dbl_ovrd off use_behavioral_HDL off Optimization "Resource" xl_use_area off xl_area "[1 0 0 2 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,401" block_type "addrsr" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,60,3,1,white,blue,0,f8ea6153,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 60 60 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 60 60 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[36.66 3" "6.66 42.66 36.66 42.66 42.66 42.66 36.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[30.66 30.66 36.66 " "36.66 30.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[24.66 24.66 30.66 30.66 24.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[18.66 18.66 24.66 18.66 24.66 24.66 18.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'addr');\ncolor('black');port_label('input',3," "'en');\ncolor('black');port_label('output',1,'q');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Delay" SID "13939" Ports [1, 1] Position [705, 441, 730, 469] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "25,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 " "17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33" " 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('blac" "k');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "13940" Position [210, 280, 300, 300] ZOrder -9 ShowName off GotoTag "ltsCorr_dAddr" TagVisibility "scoped" } Block { BlockType From Name "From1" SID "13941" Position [210, 340, 300, 360] ZOrder -9 ShowName off GotoTag "ltsCorr_cAddr" TagVisibility "scoped" } Block { BlockType From Name "From2" SID "13942" Position [210, 380, 300, 400] ZOrder -9 ShowName off GotoTag "ltsCorr_ld" TagVisibility "scoped" } Block { BlockType Reference Name "Gateway Out1" SID "13943" Ports [1, 1] Position [745, 615, 780, 625] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "13944" Ports [1, 1] Position [745, 630, 780, 640] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "13945" Ports [1, 1] Position [745, 645, 780, 655] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Ld" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "13946" Ports [1, 1] Position [745, 660, 780, 670] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "13947" Ports [1, 1] Position [745, 675, 780, 685] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "13948" Ports [1, 1] Position [745, 570, 780, 580] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X In" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "13949" Ports [1, 1] Position [745, 585, 780, 595] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "13950" Ports [1, 1] Position [745, 600, 780, 610] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X Vin" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType SubSystem Name "MAC" SID "13951" Ports [4, 2] Position [575, 279, 660, 376] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "MAC" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "a" SID "13952" Position [35, 143, 65, 157] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "coeff" SID "13953" Position [35, 108, 65, 122] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "ld" SID "13954" Position [35, 178, 65, 192] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "rst" SID "13955" Position [35, 233, 65, 247] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub" SID "13956" Ports [3, 1] Position [340, 113, 385, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition or Subtraction" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Signed (2's comp)" n_bits "long_cor_acc_n_bits" bin_pt "0" quantization "Truncate" overflow "Flag as error" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[2 0 0 4 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,344" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,3,1,white,blue,0,02f64c57,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('input',3,'su" "b');\ncolor('black');port_label('output',1,'\\bf{a \\pm b}','texmode','on');\nfprintf('','COMMENT: end icon text" "');\n" } Block { BlockType Reference Name "Gateway Out1" SID "13957" Ports [1, 1] Position [475, 450, 510, 460] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out2" SID "13958" Ports [1, 1] Position [475, 465, 510, 475] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out3" SID "13959" Ports [1, 1] Position [475, 480, 510, 490] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out6" SID "13960" Ports [1, 1] Position [475, 405, 510, 415] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out7" SID "13961" Ports [1, 1] Position [475, 420, 510, 430] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out8" SID "13962" Ports [1, 1] Position [475, 435, 510, 445] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "13963" Ports [2, 1] Position [345, 30, 385, 70] BlockMirror on NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,40,2,1,white,blue,0,140cc11c,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'" "q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "13964" Ports [2, 1] Position [465, 110, 495, 210] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,100,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 100 100 0 ],[0.77 0." "82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 100 100 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[54.44 " "54.44 58.44 54.44 58.44 58.44 58.44 54.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[50.44 50.44 54.44 54" ".44 50.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[46.44 46.44 50.44 50.44 46.44 ],[1 1 1 ])" ";\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[42.44 42.44 46.44 42.44 46.44 46.44 42.44 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\nco" "lor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc2" SID "13965" Ports [1, 1] Position [265, 143, 290, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc3" SID "13966" Ports [1, 1] Position [135, 178, 160, 192] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "yn" SID "13967" Position [545, 153, 575, 167] IconDisplay "Port number" } Block { BlockType Outport Name "accrm" SID "13968" Position [520, 288, 550, 302] Port "2" IconDisplay "Port number" } Line { SrcBlock "rst" SrcPort 1 Points [90, 0] Branch { Points [0, 215] DstBlock "Gateway Out1" DstPort 1 } Branch { Points [255, 0; 0, -180] DstBlock "Register1" DstPort 2 } } Line { SrcBlock "Gateway Out3" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out2" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out1" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out6" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out7" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out8" SrcPort 1 Points [50, 0] } Line { SrcBlock "a" SrcPort 1 Points [140, 0] Branch { Points [0, 275] DstBlock "Gateway Out7" DstPort 1 } Branch { DstBlock "bc2" DstPort 1 } } Line { SrcBlock "AddSub" SrcPort 1 Points [0, 0; 5, 0] Branch { Points [0, 305] DstBlock "Gateway Out8" DstPort 1 } Branch { Points [40, 0] Branch { Points [0, 160] DstBlock "accrm" DstPort 1 } Branch { Points [0, -95] DstBlock "Register1" DstPort 1 } Branch { DstBlock "Register2" DstPort 1 } } } Line { SrcBlock "Register2" SrcPort 1 Points [15, 0] Branch { Points [0, 50; 110, 0; 0, 385; -260, 0; 0, -110] DstBlock "Gateway Out3" DstPort 1 } Branch { DstBlock "yn" DstPort 1 } } Line { SrcBlock "Register1" SrcPort 1 Points [-15, 0] DstBlock "AddSub" DstPort 1 } Line { SrcBlock "ld" SrcPort 1 Points [45, 0] Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } Branch { DstBlock "bc3" DstPort 1 } } Line { SrcBlock "bc3" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "bc2" SrcPort 1 DstBlock "AddSub" DstPort 3 } Line { SrcBlock "coeff" SrcPort 1 Points [95, 0; 0, 20; 50, 0] Branch { Points [0, 275] DstBlock "Gateway Out6" DstPort 1 } Branch { DstBlock "AddSub" DstPort 2 } } } } Block { BlockType Reference Name "ROM" SID "13969" Ports [1, 1] Position [440, 328, 490, 372] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/ROM" SourceType "Xilinx Single Port Read-Only Memory Block" depth "length(coef2)" initVector "coef2" distributed_mem "Distributed memory" rst off init_reg "0" en off latency "1" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "longCorr_coef_nbits" bin_pt "longCorr_coef_bp" preci_type "Single" exp_width "8" frac_width "24" dbl_ovrd off optimize "Area" use_rpm off xl_use_area off xl_area "[1 1 0 1 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,308" block_type "sprom" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,44,1,1,white,blue,0,bbc23d60,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 44 44 0 ]);\npatch([11.65 20.32 26.32 32.32 38.32 26.32 17.65 11.65 ],[28.66" " 28.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([17.65 26.32 20.32 11.65 17.65 ],[22.66 22.66 28." "66 28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([11.65 20.32 26.32 17.65 11.65 ],[16.66 16.66 22.66 22.66 16.66 ]" ",[1 1 1 ]);\npatch([17.65 38.32 32.32 26.32 20.32 11.65 17.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'addr');\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end" " icon text');\n" } Block { BlockType Outport Name "x_dly" SID "13970" Position [790, 178, 820, 192] IconDisplay "Port number" } Block { BlockType Outport Name "x_dly_vout" SID "13971" Position [790, 223, 820, 237] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "y" SID "13972" Position [790, 293, 820, 307] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "y_vout" SID "13973" Position [785, 448, 815, 462] Port "4" IconDisplay "Port number" } Line { Name "ROM Addr" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 Points [150, 0] } Line { Name "Corr Out" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 Points [150, 0] } Line { Name "Corr Ld" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 Points [150, 0] } Line { Name "ROM Out" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 Points [150, 0] } Line { Name "ASR Out" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 Points [150, 0] } Line { Name "X In" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 Points [150, 0] } Line { Name "ASR Addr" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 Points [150, 0] } Line { Name "X Vin" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 Points [150, 0] } Line { SrcBlock "Delay" SrcPort 1 DstBlock "y_vout" DstPort 1 } Line { SrcBlock "vin" SrcPort 1 Points [25, 0] Branch { Points [0, -80] DstBlock "x_dly_vout" DstPort 1 } Branch { Points [0, 100] Branch { Points [230, 0] DstBlock "MAC" DstPort 4 } Branch { Points [0, 195] DstBlock "Gateway Out8" DstPort 1 } } Branch { DstBlock "ASR" DstPort 3 } } Line { SrcBlock "x" SrcPort 1 Points [100, 0] Branch { Points [0, 305] DstBlock "Gateway Out6" DstPort 1 } Branch { DstBlock "ASR" DstPort 1 } } Line { SrcBlock "From" SrcPort 1 Points [90, 0] Branch { Points [0, 300] DstBlock "Gateway Out7" DstPort 1 } Branch { DstBlock "ASR" DstPort 2 } } Line { SrcBlock "From1" SrcPort 1 Points [5, 0] Branch { Points [0, 330] DstBlock "Gateway Out5" DstPort 1 } Branch { DstBlock "ROM" DstPort 1 } } Line { SrcBlock "ASR" SrcPort 1 Points [35, 0] Branch { Points [0, 330] DstBlock "Gateway Out1" DstPort 1 } Branch { Points [0, -105] DstBlock "x_dly" DstPort 1 } Branch { DstBlock "MAC" DstPort 1 } } Line { SrcBlock "MAC" SrcPort 1 Points [0, -5; 15, 0] Branch { Points [0, 365] DstBlock "Gateway Out4" DstPort 1 } Branch { DstBlock "y" DstPort 1 } } Line { SrcBlock "ROM" SrcPort 1 Points [5, 0] Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } Branch { Points [0, -35] DstBlock "MAC" DstPort 2 } } Line { SrcBlock "From2" SrcPort 1 Points [145, 0] Branch { Points [0, 260] DstBlock "Gateway Out3" DstPort 1 } Branch { Points [90, 0] Branch { Points [0, 65] DstBlock "Delay" DstPort 1 } Branch { Points [0, -50] Branch { Points [0, -90; 160, 0] } Branch { DstBlock "MAC" DstPort 3 } } } } } } Block { BlockType Reference Name "Gateway Out1" SID "13974" Ports [1, 1] Position [1195, 75, 1230, 85] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out10" SID "13975" Ports [1, 1] Position [1195, 120, 1230, 130] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out11" SID "13976" Ports [1, 1] Position [1195, 135, 1230, 145] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out12" SID "13977" Ports [1, 1] Position [1195, 150, 1230, 160] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out13" SID "13978" Ports [1, 1] Position [1195, 165, 1230, 175] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out14" SID "13979" Ports [1, 1] Position [1225, 180, 1260, 190] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out2" SID "13980" Ports [1, 1] Position [740, 720, 775, 730] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out3" SID "13981" Ports [1, 1] Position [740, 690, 775, 700] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out4" SID "13982" Ports [1, 1] Position [740, 705, 775, 715] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out5" SID "13983" Ports [1, 1] Position [740, 735, 775, 745] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out6" SID "13984" Ports [1, 1] Position [1195, 45, 1230, 55] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out7" SID "13985" Ports [1, 1] Position [1195, 60, 1230, 70] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out8" SID "13986" Ports [1, 1] Position [1195, 90, 1230, 100] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out9" SID "13987" Ports [1, 1] Position [1195, 105, 1230, 115] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Outport Name "y" SID "13988" Position [1290, 568, 1320, 582] IconDisplay "Port number" } Block { BlockType Outport Name "y_vout" SID "13989" Position [1290, 523, 1320, 537] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "x_dly" SID "13990" Position [1260, 213, 1290, 227] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "x_dly_vout" SID "13991" Position [1260, 253, 1290, 267] Port "4" IconDisplay "Port number" } Line { SrcBlock "x" SrcPort 1 Points [210, 0] Branch { DstBlock "C1" DstPort 1 } Branch { Points [0, 475] DstBlock "Gateway Out3" DstPort 1 } Branch { Points [0, -170] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "AddSub12" SrcPort 1 DstBlock "AddSub13" DstPort 2 } Line { SrcBlock "AddSub5" SrcPort 1 Points [0, 35] DstBlock "AddSub13" DstPort 1 } Line { SrcBlock "Gateway Out4" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out3" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out5" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out2" SrcPort 1 Points [50, 0] } Line { Points [780, 755; 50, 0] } Line { SrcBlock "x_valid" SrcPort 1 Points [200, 0] Branch { Points [0, -20] DstBlock "C1" DstPort 2 } Branch { Points [0, 450] DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "C1" SrcPort 1 DstBlock "C2" DstPort 1 } Line { SrcBlock "C1" SrcPort 2 DstBlock "C2" DstPort 2 } Line { SrcBlock "C2" SrcPort 1 DstBlock "C3" DstPort 1 } Line { SrcBlock "C2" SrcPort 2 DstBlock "C3" DstPort 2 } Line { SrcBlock "C2" SrcPort 3 Points [20, 0] Branch { DstBlock "AddSub5" DstPort 2 } Branch { Points [0, -180] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "C1" SrcPort 3 Points [15, 0] Branch { Points [0, 55] Branch { Points [0, 5; 95, 0] DstBlock "AddSub5" DstPort 1 } Branch { Points [0, 410] DstBlock "Gateway Out2" DstPort 1 } } Branch { Points [0, -195] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "C3" SrcPort 1 DstBlock "C4" DstPort 1 } Line { SrcBlock "C3" SrcPort 2 DstBlock "C4" DstPort 2 } Line { SrcBlock "C3" SrcPort 3 Points [20, 0] Branch { Points [0, 65; 80, 0] DstBlock "AddSub12" DstPort 1 } Branch { Points [0, -165] DstBlock "Gateway Out8" DstPort 1 } } Line { SrcBlock "C4" SrcPort 1 DstBlock "C5" DstPort 1 } Line { SrcBlock "C4" SrcPort 2 DstBlock "C5" DstPort 2 } Line { SrcBlock "C4" SrcPort 3 Points [15, 0] Branch { DstBlock "AddSub12" DstPort 2 } Branch { Points [0, -150] DstBlock "Gateway Out9" DstPort 1 } } Line { SrcBlock "C5" SrcPort 1 DstBlock "C6" DstPort 1 } Line { SrcBlock "C5" SrcPort 2 DstBlock "C6" DstPort 2 } Line { SrcBlock "C6" SrcPort 1 DstBlock "C7" DstPort 1 } Line { SrcBlock "C6" SrcPort 2 DstBlock "C7" DstPort 2 } Line { SrcBlock "C7" SrcPort 1 DstBlock "C8" DstPort 1 } Line { SrcBlock "C7" SrcPort 2 DstBlock "C8" DstPort 2 } Line { SrcBlock "C6" SrcPort 3 Points [15, 0] Branch { DstBlock "AddSub6" DstPort 2 } Branch { Points [0, -120] DstBlock "Gateway Out11" DstPort 1 } } Line { SrcBlock "C5" SrcPort 3 Points [10, 0] Branch { Points [0, 70; 85, 0] DstBlock "AddSub6" DstPort 1 } Branch { Points [0, -135] DstBlock "Gateway Out10" DstPort 1 } } Line { SrcBlock "C8" SrcPort 3 Points [10, 0] Branch { DstBlock "AddSub7" DstPort 2 } Branch { Points [0, -90] DstBlock "Gateway Out13" DstPort 1 } } Line { SrcBlock "C7" SrcPort 3 Points [20, 0] Branch { Points [0, 65; 75, 0] DstBlock "AddSub7" DstPort 1 } Branch { Points [0, -105] DstBlock "Gateway Out12" DstPort 1 } } Line { SrcBlock "AddSub6" SrcPort 1 DstBlock "AddSub1" DstPort 1 } Line { SrcBlock "AddSub7" SrcPort 1 Points [0, 35] DstBlock "AddSub1" DstPort 2 } Line { SrcBlock "AddSub13" SrcPort 1 Points [0, 85] DstBlock "AddSub4" DstPort 2 } Line { SrcBlock "AddSub1" SrcPort 1 Points [0, 60] DstBlock "AddSub4" DstPort 1 } Line { SrcBlock "AddSub4" SrcPort 1 Points [45, 0] Branch { Points [0, 75; -400, 0; 0, 90] DstBlock "Gateway Out5" DstPort 1 } Branch { Points [155, 0] Branch { DstBlock "y" DstPort 1 } Branch { Points [0, -390] DstBlock "Gateway Out14" DstPort 1 } } } Line { SrcBlock "C8" SrcPort 4 Points [40, 0; 0, 250] DstBlock "y_vout" DstPort 1 } Line { SrcBlock "Gateway Out7" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out6" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out8" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out1" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out9" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out10" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out11" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out12" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out13" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out14" SrcPort 1 Points [20, 0] } Line { SrcBlock "C8" SrcPort 1 DstBlock "x_dly" DstPort 1 } Line { SrcBlock "C8" SrcPort 2 Points [110, 0] DstBlock "x_dly_vout" DstPort 1 } } } Block { BlockType SubSystem Name "C7" SID "13992" Ports [2, 4] Position [585, 363, 670, 432] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskPromptString "Coefficients/correlator|Coefficients|Input sample period" MaskStyleString "edit,edit,edit" MaskVariables "N=@1;h=@2;Ts_In=@3;" MaskTunableValueString "on,on,on" MaskCallbackString "||" MaskEnableString "on,on,on" MaskVisibilityString "on,on,on" MaskToolTipString "on,on,on" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "4|longCorr_coef_q(1:32)|4" System { Name "C7" Location [480, 85, 2304, 1455] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "156" Block { BlockType Inport Name "x" SID "13993" Position [35, 213, 65, 227] IconDisplay "Port number" } Block { BlockType Inport Name "x_valid" SID "13994" Position [35, 253, 65, 267] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub1" SID "13995" Ports [2, 1] Position [915, 455, 955, 495] BlockRotation 270 BlockMirror on NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "1" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[3 6 0 5 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,40,2,1,white,blue,0,e85d8a90,down,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bf{a + b}','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\ne" "wline\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub12" SID "13996" Ports [2, 1] Position [684, 360, 731, 400] BlockRotation 270 BlockMirror on NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "1" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[3 5 0 4 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "47,40,2,1,white,blue,0,e85d8a90,down,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 47 47 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 47 47 0 0 ],[0 0 40 40 0 ]);\npatch([11.875 19.1 24.1 29.1 34.1 24.1 16.875 11.875 ],[25.55 2" "5.55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([16.875 24.1 19.1 11.875 16.875 ],[20.55 20.55 25.5" "5 25.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([11.875 19.1 24.1 16.875 11.875 ],[15.55 15.55 20.55 20.55 15.55 ]" ",[1 1 1 ]);\npatch([16.875 34.1 29.1 24.1 19.1 11.875 16.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('b" "lack');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output'" ",1,'\\bf{a + b}','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(" "' \\newline\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub13" SID "13997" Ports [2, 1] Position [680, 455, 720, 495] BlockRotation 270 BlockMirror on NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "1" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[3 6 0 5 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,40,2,1,white,blue,0,e85d8a90,down,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bf{a + b}','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\ne" "wline\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub4" SID "13998" Ports [2, 1] Position [960, 549, 1000, 596] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "1" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[4 7 0 6 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,47,2,1,white,blue,0,e85d8a90,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 47 47 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 47 47 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[28.55 28." "55 33.55 28.55 33.55 33.55 33.55 28.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[23.55 23.55 28.55 2" "8.55 23.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[18.55 18.55 23.55 23.55 18.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[13.55 13.55 18.55 13.55 18.55 18.55 13.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bf{a + b}','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\ne" "wline\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub5" SID "13999" Ports [2, 1] Position [475, 360, 515, 400] BlockRotation 270 BlockMirror on NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "1" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[3 6 0 5 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,40,2,1,white,blue,0,e85d8a90,down,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bf{a + b}','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\ne" "wline\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub6" SID "14000" Ports [2, 1] Position [899, 360, 946, 400] BlockRotation 270 BlockMirror on NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "1" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[3 5 0 4 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "47,40,2,1,white,blue,0,e85d8a90,down,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 47 47 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 47 47 0 0 ],[0 0 40 40 0 ]);\npatch([11.875 19.1 24.1 29.1 34.1 24.1 16.875 11.875 ],[25.55 2" "5.55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([16.875 24.1 19.1 11.875 16.875 ],[20.55 20.55 25.5" "5 25.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([11.875 19.1 24.1 16.875 11.875 ],[15.55 15.55 20.55 20.55 15.55 ]" ",[1 1 1 ]);\npatch([16.875 34.1 29.1 24.1 19.1 11.875 16.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('b" "lack');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output'" ",1,'\\bf{a + b}','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(" "' \\newline\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub7" SID "14001" Ports [2, 1] Position [1109, 360, 1156, 400] BlockRotation 270 BlockMirror on NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "1" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[3 5 0 4 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "47,40,2,1,white,blue,0,e85d8a90,down,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 47 47 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 47 47 0 0 ],[0 0 40 40 0 ]);\npatch([11.875 19.1 24.1 29.1 34.1 24.1 16.875 11.875 ],[25.55 2" "5.55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([16.875 24.1 19.1 11.875 16.875 ],[20.55 20.55 25.5" "5 25.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([11.875 19.1 24.1 16.875 11.875 ],[15.55 15.55 20.55 20.55 15.55 ]" ",[1 1 1 ]);\npatch([16.875 34.1 29.1 24.1 19.1 11.875 16.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('b" "lack');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output'" ",1,'\\bf{a + b}','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(" "' \\newline\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "C1" SID "14002" Ports [4, 4] Position [300, 207, 370, 293] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskPromptString "Coefficients (all)|Sub-correlator Ind|Coef/correlator" MaskStyleString "edit,edit,edit" MaskVariables "h=@1;c_ind=@2;N=@3;" MaskTunableValueString "on,on,on" MaskCallbackString "||" MaskEnableString "on,on,on" MaskVisibilityString "on,on,on" MaskToolTipString "on,on,on" MaskInitialization "coef2 = h((c_ind*N+1) : (c_ind + 1)*N);" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "h|0|N" System { Name "C1" Location [480, 85, 2304, 1471] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "122" Block { BlockType Inport Name "x" SID "14003" Position [265, 263, 295, 277] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "vin" SID "14004" Position [270, 303, 300, 317] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "14005" Position [270, 458, 300, 472] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "14006" Position [270, 503, 300, 517] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "ASR" SID "14007" Ports [3, 1] Position [445, 260, 490, 320] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Addressable Shift Register" SourceType "Xilinx Addressable Shift Register Block" infoedit "Delay of configurable length. Any element in the delay line can be addressed and driven onto the" " output port.

Hardware notes: This block is implemented using SRL16s. If Virtex-4 or Spartan-3 device is " "used, multiple SRLC16s are cascaded together." infer_latency off depth "length(coef2)" initVector "[0]" en on dbl_ovrd off use_behavioral_HDL off Optimization "Resource" xl_use_area off xl_area "[1 0 0 2 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,401" block_type "addrsr" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,60,3,1,white,blue,0,f8ea6153,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 60 60 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 60 60 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[36.66 3" "6.66 42.66 36.66 42.66 42.66 42.66 36.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[30.66 30.66 36.66 " "36.66 30.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[24.66 24.66 30.66 30.66 24.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[18.66 18.66 24.66 18.66 24.66 24.66 18.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'addr');\ncolor('black');port_label('input',3," "'en');\ncolor('black');port_label('output',1,'q');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Delay" SID "14008" Ports [1, 1] Position [705, 441, 730, 469] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "25,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 " "17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33" " 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('blac" "k');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "14009" Position [210, 280, 300, 300] ZOrder -9 ShowName off GotoTag "ltsCorr_dAddr" TagVisibility "scoped" } Block { BlockType From Name "From1" SID "14010" Position [210, 340, 300, 360] ZOrder -9 ShowName off GotoTag "ltsCorr_cAddr" TagVisibility "scoped" } Block { BlockType From Name "From2" SID "14011" Position [210, 380, 300, 400] ZOrder -9 ShowName off GotoTag "ltsCorr_ld" TagVisibility "scoped" } Block { BlockType Reference Name "Gateway Out1" SID "14012" Ports [1, 1] Position [745, 615, 780, 625] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "14013" Ports [1, 1] Position [745, 630, 780, 640] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "14014" Ports [1, 1] Position [745, 645, 780, 655] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Ld" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "14015" Ports [1, 1] Position [745, 660, 780, 670] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "14016" Ports [1, 1] Position [745, 675, 780, 685] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "14017" Ports [1, 1] Position [745, 570, 780, 580] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X In" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "14018" Ports [1, 1] Position [745, 585, 780, 595] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "14019" Ports [1, 1] Position [745, 600, 780, 610] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X Vin" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType SubSystem Name "MAC" SID "14020" Ports [4, 2] Position [575, 279, 660, 376] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "MAC" Location [88, 301, 2330, 1301] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "a" SID "14021" Position [35, 143, 65, 157] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "coeff" SID "14022" Position [35, 108, 65, 122] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "ld" SID "14023" Position [35, 178, 65, 192] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "rst" SID "14024" Position [35, 233, 65, 247] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub" SID "14025" Ports [3, 1] Position [340, 113, 385, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition or Subtraction" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Signed (2's comp)" n_bits "long_cor_acc_n_bits" bin_pt "0" quantization "Truncate" overflow "Flag as error" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[2 0 0 4 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,344" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,3,1,white,blue,0,02f64c57,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('input',3,'su" "b');\ncolor('black');port_label('output',1,'\\bf{a \\pm b}','texmode','on');\nfprintf('','COMMENT: end icon text" "');\n" } Block { BlockType Reference Name "Gateway Out1" SID "14026" Ports [1, 1] Position [475, 450, 510, 460] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out2" SID "14027" Ports [1, 1] Position [475, 465, 510, 475] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out3" SID "14028" Ports [1, 1] Position [475, 480, 510, 490] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out6" SID "14029" Ports [1, 1] Position [475, 405, 510, 415] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out7" SID "14030" Ports [1, 1] Position [475, 420, 510, 430] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out8" SID "14031" Ports [1, 1] Position [475, 435, 510, 445] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "14032" Ports [2, 1] Position [345, 30, 385, 70] BlockMirror on NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,40,2,1,white,blue,0,140cc11c,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'" "q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "14033" Ports [2, 1] Position [465, 110, 495, 210] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,100,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 100 100 0 ],[0.77 0." "82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 100 100 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[54.44 " "54.44 58.44 54.44 58.44 58.44 58.44 54.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[50.44 50.44 54.44 54" ".44 50.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[46.44 46.44 50.44 50.44 46.44 ],[1 1 1 ])" ";\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[42.44 42.44 46.44 42.44 46.44 46.44 42.44 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\nco" "lor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc2" SID "14034" Ports [1, 1] Position [265, 143, 290, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc3" SID "14035" Ports [1, 1] Position [135, 178, 160, 192] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "yn" SID "14036" Position [545, 153, 575, 167] IconDisplay "Port number" } Block { BlockType Outport Name "accrm" SID "14037" Position [520, 288, 550, 302] Port "2" IconDisplay "Port number" } Line { SrcBlock "coeff" SrcPort 1 Points [95, 0; 0, 20; 50, 0] Branch { DstBlock "AddSub" DstPort 2 } Branch { Points [0, 275] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "bc2" SrcPort 1 DstBlock "AddSub" DstPort 3 } Line { SrcBlock "bc3" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "ld" SrcPort 1 Points [45, 0] Branch { DstBlock "bc3" DstPort 1 } Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "Register1" SrcPort 1 Points [-15, 0] DstBlock "AddSub" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 Points [15, 0] Branch { DstBlock "yn" DstPort 1 } Branch { Points [0, 50; 110, 0; 0, 385; -260, 0; 0, -110] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "AddSub" SrcPort 1 Points [0, 0; 5, 0] Branch { Points [40, 0] Branch { DstBlock "Register2" DstPort 1 } Branch { Points [0, -95] DstBlock "Register1" DstPort 1 } Branch { Points [0, 160] DstBlock "accrm" DstPort 1 } } Branch { Points [0, 305] DstBlock "Gateway Out8" DstPort 1 } } Line { SrcBlock "a" SrcPort 1 Points [140, 0] Branch { DstBlock "bc2" DstPort 1 } Branch { Points [0, 275] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "Gateway Out8" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out7" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out6" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out1" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out2" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out3" SrcPort 1 Points [50, 0] } Line { SrcBlock "rst" SrcPort 1 Points [90, 0] Branch { Points [255, 0; 0, -180] DstBlock "Register1" DstPort 2 } Branch { Points [0, 215] DstBlock "Gateway Out1" DstPort 1 } } } } Block { BlockType Reference Name "ROM" SID "14038" Ports [1, 1] Position [440, 328, 490, 372] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/ROM" SourceType "Xilinx Single Port Read-Only Memory Block" depth "length(coef2)" initVector "coef2" distributed_mem "Distributed memory" rst off init_reg "0" en off latency "1" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "longCorr_coef_nbits" bin_pt "longCorr_coef_bp" preci_type "Single" exp_width "8" frac_width "24" dbl_ovrd off optimize "Area" use_rpm off xl_use_area off xl_area "[1 1 0 1 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,308" block_type "sprom" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,44,1,1,white,blue,0,bbc23d60,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 44 44 0 ]);\npatch([11.65 20.32 26.32 32.32 38.32 26.32 17.65 11.65 ],[28.66" " 28.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([17.65 26.32 20.32 11.65 17.65 ],[22.66 22.66 28." "66 28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([11.65 20.32 26.32 17.65 11.65 ],[16.66 16.66 22.66 22.66 16.66 ]" ",[1 1 1 ]);\npatch([17.65 38.32 32.32 26.32 20.32 11.65 17.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'addr');\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end" " icon text');\n" } Block { BlockType Outport Name "x_dly" SID "14039" Position [790, 178, 820, 192] IconDisplay "Port number" } Block { BlockType Outport Name "x_dly_vout" SID "14040" Position [790, 223, 820, 237] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "y" SID "14041" Position [790, 293, 820, 307] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "y_vout" SID "14042" Position [785, 448, 815, 462] Port "4" IconDisplay "Port number" } Line { SrcBlock "From2" SrcPort 1 Points [145, 0] Branch { Points [90, 0] Branch { Points [0, -50] Branch { DstBlock "MAC" DstPort 3 } Branch { Points [0, -90; 160, 0] } } Branch { Points [0, 65] DstBlock "Delay" DstPort 1 } } Branch { Points [0, 260] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "ROM" SrcPort 1 Points [5, 0] Branch { Points [0, -35] DstBlock "MAC" DstPort 2 } Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "MAC" SrcPort 1 Points [0, -5; 15, 0] Branch { DstBlock "y" DstPort 1 } Branch { Points [0, 365] DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "ASR" SrcPort 1 Points [35, 0] Branch { DstBlock "MAC" DstPort 1 } Branch { Points [0, -105] DstBlock "x_dly" DstPort 1 } Branch { Points [0, 330] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "From1" SrcPort 1 Points [5, 0] Branch { DstBlock "ROM" DstPort 1 } Branch { Points [0, 330] DstBlock "Gateway Out5" DstPort 1 } } Line { SrcBlock "From" SrcPort 1 Points [90, 0] Branch { DstBlock "ASR" DstPort 2 } Branch { Points [0, 300] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "x" SrcPort 1 Points [100, 0] Branch { DstBlock "ASR" DstPort 1 } Branch { Points [0, 305] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "vin" SrcPort 1 Points [25, 0] Branch { DstBlock "ASR" DstPort 3 } Branch { Points [0, 100] Branch { Points [0, 195] DstBlock "Gateway Out8" DstPort 1 } Branch { Points [230, 0] DstBlock "MAC" DstPort 4 } } Branch { Points [0, -80] DstBlock "x_dly_vout" DstPort 1 } } Line { SrcBlock "Delay" SrcPort 1 DstBlock "y_vout" DstPort 1 } Line { Name "X Vin" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 Points [150, 0] } Line { Name "ASR Addr" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 Points [150, 0] } Line { Name "X In" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 Points [150, 0] } Line { Name "ASR Out" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 Points [150, 0] } Line { Name "ROM Out" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 Points [150, 0] } Line { Name "Corr Ld" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 Points [150, 0] } Line { Name "Corr Out" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 Points [150, 0] } Line { Name "ROM Addr" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 Points [150, 0] } } } Block { BlockType SubSystem Name "C2" SID "14043" Ports [4, 4] Position [410, 207, 480, 293] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskPromptString "Coefficients (all)|Sub-correlator Ind|Coef/correlator" MaskStyleString "edit,edit,edit" MaskVariables "h=@1;c_ind=@2;N=@3;" MaskTunableValueString "on,on,on" MaskCallbackString "||" MaskEnableString "on,on,on" MaskVisibilityString "on,on,on" MaskToolTipString "on,on,on" MaskInitialization "coef2 = h((c_ind*N+1) : (c_ind + 1)*N);" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "h|1|N" System { Name "C2" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "122" Block { BlockType Inport Name "x" SID "14044" Position [265, 263, 295, 277] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "vin" SID "14045" Position [270, 303, 300, 317] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "14046" Position [270, 458, 300, 472] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "14047" Position [270, 503, 300, 517] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "ASR" SID "14048" Ports [3, 1] Position [445, 260, 490, 320] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Addressable Shift Register" SourceType "Xilinx Addressable Shift Register Block" infoedit "Delay of configurable length. Any element in the delay line can be addressed and driven onto the" " output port.

Hardware notes: This block is implemented using SRL16s. If Virtex-4 or Spartan-3 device is " "used, multiple SRLC16s are cascaded together." infer_latency off depth "length(coef2)" initVector "[0]" en on dbl_ovrd off use_behavioral_HDL off Optimization "Resource" xl_use_area off xl_area "[1 0 0 2 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,401" block_type "addrsr" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,60,3,1,white,blue,0,f8ea6153,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 60 60 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 60 60 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[36.66 3" "6.66 42.66 36.66 42.66 42.66 42.66 36.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[30.66 30.66 36.66 " "36.66 30.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[24.66 24.66 30.66 30.66 24.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[18.66 18.66 24.66 18.66 24.66 24.66 18.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'addr');\ncolor('black');port_label('input',3," "'en');\ncolor('black');port_label('output',1,'q');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Delay" SID "14049" Ports [1, 1] Position [705, 441, 730, 469] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "25,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 " "17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33" " 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('blac" "k');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "14050" Position [210, 280, 300, 300] ZOrder -9 ShowName off GotoTag "ltsCorr_dAddr" TagVisibility "scoped" } Block { BlockType From Name "From1" SID "14051" Position [210, 340, 300, 360] ZOrder -9 ShowName off GotoTag "ltsCorr_cAddr" TagVisibility "scoped" } Block { BlockType From Name "From2" SID "14052" Position [210, 380, 300, 400] ZOrder -9 ShowName off GotoTag "ltsCorr_ld" TagVisibility "scoped" } Block { BlockType Reference Name "Gateway Out1" SID "14053" Ports [1, 1] Position [745, 615, 780, 625] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "14054" Ports [1, 1] Position [745, 630, 780, 640] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "14055" Ports [1, 1] Position [745, 645, 780, 655] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Ld" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "14056" Ports [1, 1] Position [745, 660, 780, 670] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "14057" Ports [1, 1] Position [745, 675, 780, 685] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "14058" Ports [1, 1] Position [745, 570, 780, 580] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X In" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "14059" Ports [1, 1] Position [745, 585, 780, 595] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "14060" Ports [1, 1] Position [745, 600, 780, 610] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X Vin" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType SubSystem Name "MAC" SID "14061" Ports [4, 2] Position [575, 279, 660, 376] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "MAC" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "a" SID "14062" Position [35, 143, 65, 157] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "coeff" SID "14063" Position [35, 108, 65, 122] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "ld" SID "14064" Position [35, 178, 65, 192] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "rst" SID "14065" Position [35, 233, 65, 247] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub" SID "14066" Ports [3, 1] Position [340, 113, 385, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition or Subtraction" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Signed (2's comp)" n_bits "long_cor_acc_n_bits" bin_pt "0" quantization "Truncate" overflow "Flag as error" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[2 0 0 4 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,344" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,3,1,white,blue,0,02f64c57,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('input',3,'su" "b');\ncolor('black');port_label('output',1,'\\bf{a \\pm b}','texmode','on');\nfprintf('','COMMENT: end icon text" "');\n" } Block { BlockType Reference Name "Gateway Out1" SID "14067" Ports [1, 1] Position [475, 450, 510, 460] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out2" SID "14068" Ports [1, 1] Position [475, 465, 510, 475] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out3" SID "14069" Ports [1, 1] Position [475, 480, 510, 490] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out6" SID "14070" Ports [1, 1] Position [475, 405, 510, 415] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out7" SID "14071" Ports [1, 1] Position [475, 420, 510, 430] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out8" SID "14072" Ports [1, 1] Position [475, 435, 510, 445] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "14073" Ports [2, 1] Position [345, 30, 385, 70] BlockMirror on NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,40,2,1,white,blue,0,140cc11c,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'" "q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "14074" Ports [2, 1] Position [465, 110, 495, 210] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,100,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 100 100 0 ],[0.77 0." "82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 100 100 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[54.44 " "54.44 58.44 54.44 58.44 58.44 58.44 54.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[50.44 50.44 54.44 54" ".44 50.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[46.44 46.44 50.44 50.44 46.44 ],[1 1 1 ])" ";\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[42.44 42.44 46.44 42.44 46.44 46.44 42.44 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\nco" "lor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc2" SID "14075" Ports [1, 1] Position [265, 143, 290, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc3" SID "14076" Ports [1, 1] Position [135, 178, 160, 192] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "yn" SID "14077" Position [545, 153, 575, 167] IconDisplay "Port number" } Block { BlockType Outport Name "accrm" SID "14078" Position [520, 288, 550, 302] Port "2" IconDisplay "Port number" } Line { SrcBlock "rst" SrcPort 1 Points [90, 0] Branch { Points [0, 215] DstBlock "Gateway Out1" DstPort 1 } Branch { Points [255, 0; 0, -180] DstBlock "Register1" DstPort 2 } } Line { SrcBlock "Gateway Out3" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out2" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out1" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out6" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out7" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out8" SrcPort 1 Points [50, 0] } Line { SrcBlock "a" SrcPort 1 Points [140, 0] Branch { Points [0, 275] DstBlock "Gateway Out7" DstPort 1 } Branch { DstBlock "bc2" DstPort 1 } } Line { SrcBlock "AddSub" SrcPort 1 Points [0, 0; 5, 0] Branch { Points [0, 305] DstBlock "Gateway Out8" DstPort 1 } Branch { Points [40, 0] Branch { Points [0, 160] DstBlock "accrm" DstPort 1 } Branch { Points [0, -95] DstBlock "Register1" DstPort 1 } Branch { DstBlock "Register2" DstPort 1 } } } Line { SrcBlock "Register2" SrcPort 1 Points [15, 0] Branch { Points [0, 50; 110, 0; 0, 385; -260, 0; 0, -110] DstBlock "Gateway Out3" DstPort 1 } Branch { DstBlock "yn" DstPort 1 } } Line { SrcBlock "Register1" SrcPort 1 Points [-15, 0] DstBlock "AddSub" DstPort 1 } Line { SrcBlock "ld" SrcPort 1 Points [45, 0] Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } Branch { DstBlock "bc3" DstPort 1 } } Line { SrcBlock "bc3" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "bc2" SrcPort 1 DstBlock "AddSub" DstPort 3 } Line { SrcBlock "coeff" SrcPort 1 Points [95, 0; 0, 20; 50, 0] Branch { Points [0, 275] DstBlock "Gateway Out6" DstPort 1 } Branch { DstBlock "AddSub" DstPort 2 } } } } Block { BlockType Reference Name "ROM" SID "14079" Ports [1, 1] Position [440, 328, 490, 372] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/ROM" SourceType "Xilinx Single Port Read-Only Memory Block" depth "length(coef2)" initVector "coef2" distributed_mem "Distributed memory" rst off init_reg "0" en off latency "1" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "longCorr_coef_nbits" bin_pt "longCorr_coef_bp" preci_type "Single" exp_width "8" frac_width "24" dbl_ovrd off optimize "Area" use_rpm off xl_use_area off xl_area "[1 1 0 1 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,308" block_type "sprom" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,44,1,1,white,blue,0,bbc23d60,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 44 44 0 ]);\npatch([11.65 20.32 26.32 32.32 38.32 26.32 17.65 11.65 ],[28.66" " 28.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([17.65 26.32 20.32 11.65 17.65 ],[22.66 22.66 28." "66 28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([11.65 20.32 26.32 17.65 11.65 ],[16.66 16.66 22.66 22.66 16.66 ]" ",[1 1 1 ]);\npatch([17.65 38.32 32.32 26.32 20.32 11.65 17.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'addr');\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end" " icon text');\n" } Block { BlockType Outport Name "x_dly" SID "14080" Position [790, 178, 820, 192] IconDisplay "Port number" } Block { BlockType Outport Name "x_dly_vout" SID "14081" Position [790, 223, 820, 237] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "y" SID "14082" Position [790, 293, 820, 307] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "y_vout" SID "14083" Position [785, 448, 815, 462] Port "4" IconDisplay "Port number" } Line { Name "ROM Addr" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 Points [150, 0] } Line { Name "Corr Out" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 Points [150, 0] } Line { Name "Corr Ld" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 Points [150, 0] } Line { Name "ROM Out" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 Points [150, 0] } Line { Name "ASR Out" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 Points [150, 0] } Line { Name "X In" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 Points [150, 0] } Line { Name "ASR Addr" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 Points [150, 0] } Line { Name "X Vin" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 Points [150, 0] } Line { SrcBlock "Delay" SrcPort 1 DstBlock "y_vout" DstPort 1 } Line { SrcBlock "vin" SrcPort 1 Points [25, 0] Branch { Points [0, -80] DstBlock "x_dly_vout" DstPort 1 } Branch { Points [0, 100] Branch { Points [230, 0] DstBlock "MAC" DstPort 4 } Branch { Points [0, 195] DstBlock "Gateway Out8" DstPort 1 } } Branch { DstBlock "ASR" DstPort 3 } } Line { SrcBlock "x" SrcPort 1 Points [100, 0] Branch { Points [0, 305] DstBlock "Gateway Out6" DstPort 1 } Branch { DstBlock "ASR" DstPort 1 } } Line { SrcBlock "From" SrcPort 1 Points [90, 0] Branch { Points [0, 300] DstBlock "Gateway Out7" DstPort 1 } Branch { DstBlock "ASR" DstPort 2 } } Line { SrcBlock "From1" SrcPort 1 Points [5, 0] Branch { Points [0, 330] DstBlock "Gateway Out5" DstPort 1 } Branch { DstBlock "ROM" DstPort 1 } } Line { SrcBlock "ASR" SrcPort 1 Points [35, 0] Branch { Points [0, 330] DstBlock "Gateway Out1" DstPort 1 } Branch { Points [0, -105] DstBlock "x_dly" DstPort 1 } Branch { DstBlock "MAC" DstPort 1 } } Line { SrcBlock "MAC" SrcPort 1 Points [0, -5; 15, 0] Branch { Points [0, 365] DstBlock "Gateway Out4" DstPort 1 } Branch { DstBlock "y" DstPort 1 } } Line { SrcBlock "ROM" SrcPort 1 Points [5, 0] Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } Branch { Points [0, -35] DstBlock "MAC" DstPort 2 } } Line { SrcBlock "From2" SrcPort 1 Points [145, 0] Branch { Points [0, 260] DstBlock "Gateway Out3" DstPort 1 } Branch { Points [90, 0] Branch { Points [0, 65] DstBlock "Delay" DstPort 1 } Branch { Points [0, -50] Branch { Points [0, -90; 160, 0] } Branch { DstBlock "MAC" DstPort 3 } } } } } } Block { BlockType SubSystem Name "C3" SID "14084" Ports [4, 4] Position [520, 207, 590, 293] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskPromptString "Coefficients (all)|Sub-correlator Ind|Coef/correlator" MaskStyleString "edit,edit,edit" MaskVariables "h=@1;c_ind=@2;N=@3;" MaskTunableValueString "on,on,on" MaskCallbackString "||" MaskEnableString "on,on,on" MaskVisibilityString "on,on,on" MaskToolTipString "on,on,on" MaskInitialization "coef2 = h((c_ind*N+1) : (c_ind + 1)*N);" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "h|2|N" System { Name "C3" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "122" Block { BlockType Inport Name "x" SID "14085" Position [265, 263, 295, 277] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "vin" SID "14086" Position [270, 303, 300, 317] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "14087" Position [270, 458, 300, 472] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "14088" Position [270, 503, 300, 517] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "ASR" SID "14089" Ports [3, 1] Position [445, 260, 490, 320] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Addressable Shift Register" SourceType "Xilinx Addressable Shift Register Block" infoedit "Delay of configurable length. Any element in the delay line can be addressed and driven onto the" " output port.

Hardware notes: This block is implemented using SRL16s. If Virtex-4 or Spartan-3 device is " "used, multiple SRLC16s are cascaded together." infer_latency off depth "length(coef2)" initVector "[0]" en on dbl_ovrd off use_behavioral_HDL off Optimization "Resource" xl_use_area off xl_area "[1 0 0 2 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,401" block_type "addrsr" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,60,3,1,white,blue,0,f8ea6153,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 60 60 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 60 60 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[36.66 3" "6.66 42.66 36.66 42.66 42.66 42.66 36.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[30.66 30.66 36.66 " "36.66 30.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[24.66 24.66 30.66 30.66 24.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[18.66 18.66 24.66 18.66 24.66 24.66 18.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'addr');\ncolor('black');port_label('input',3," "'en');\ncolor('black');port_label('output',1,'q');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Delay" SID "14090" Ports [1, 1] Position [705, 441, 730, 469] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "25,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 " "17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33" " 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('blac" "k');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "14091" Position [210, 280, 300, 300] ZOrder -9 ShowName off GotoTag "ltsCorr_dAddr" TagVisibility "scoped" } Block { BlockType From Name "From1" SID "14092" Position [210, 340, 300, 360] ZOrder -9 ShowName off GotoTag "ltsCorr_cAddr" TagVisibility "scoped" } Block { BlockType From Name "From2" SID "14093" Position [210, 380, 300, 400] ZOrder -9 ShowName off GotoTag "ltsCorr_ld" TagVisibility "scoped" } Block { BlockType Reference Name "Gateway Out1" SID "14094" Ports [1, 1] Position [745, 615, 780, 625] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "14095" Ports [1, 1] Position [745, 630, 780, 640] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "14096" Ports [1, 1] Position [745, 645, 780, 655] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Ld" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "14097" Ports [1, 1] Position [745, 660, 780, 670] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "14098" Ports [1, 1] Position [745, 675, 780, 685] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "14099" Ports [1, 1] Position [745, 570, 780, 580] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X In" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "14100" Ports [1, 1] Position [745, 585, 780, 595] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "14101" Ports [1, 1] Position [745, 600, 780, 610] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X Vin" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType SubSystem Name "MAC" SID "14102" Ports [4, 2] Position [575, 279, 660, 376] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "MAC" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "a" SID "14103" Position [35, 143, 65, 157] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "coeff" SID "14104" Position [35, 108, 65, 122] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "ld" SID "14105" Position [35, 178, 65, 192] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "rst" SID "14106" Position [35, 233, 65, 247] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub" SID "14107" Ports [3, 1] Position [340, 113, 385, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition or Subtraction" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Signed (2's comp)" n_bits "long_cor_acc_n_bits" bin_pt "0" quantization "Truncate" overflow "Flag as error" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[2 0 0 4 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,344" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,3,1,white,blue,0,02f64c57,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('input',3,'su" "b');\ncolor('black');port_label('output',1,'\\bf{a \\pm b}','texmode','on');\nfprintf('','COMMENT: end icon text" "');\n" } Block { BlockType Reference Name "Gateway Out1" SID "14108" Ports [1, 1] Position [475, 450, 510, 460] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out2" SID "14109" Ports [1, 1] Position [475, 465, 510, 475] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out3" SID "14110" Ports [1, 1] Position [475, 480, 510, 490] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out6" SID "14111" Ports [1, 1] Position [475, 405, 510, 415] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out7" SID "14112" Ports [1, 1] Position [475, 420, 510, 430] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out8" SID "14113" Ports [1, 1] Position [475, 435, 510, 445] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "14114" Ports [2, 1] Position [345, 30, 385, 70] BlockMirror on NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,40,2,1,white,blue,0,140cc11c,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'" "q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "14115" Ports [2, 1] Position [465, 110, 495, 210] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,100,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 100 100 0 ],[0.77 0." "82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 100 100 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[54.44 " "54.44 58.44 54.44 58.44 58.44 58.44 54.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[50.44 50.44 54.44 54" ".44 50.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[46.44 46.44 50.44 50.44 46.44 ],[1 1 1 ])" ";\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[42.44 42.44 46.44 42.44 46.44 46.44 42.44 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\nco" "lor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc2" SID "14116" Ports [1, 1] Position [265, 143, 290, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc3" SID "14117" Ports [1, 1] Position [135, 178, 160, 192] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "yn" SID "14118" Position [545, 153, 575, 167] IconDisplay "Port number" } Block { BlockType Outport Name "accrm" SID "14119" Position [520, 288, 550, 302] Port "2" IconDisplay "Port number" } Line { SrcBlock "coeff" SrcPort 1 Points [95, 0; 0, 20; 50, 0] Branch { DstBlock "AddSub" DstPort 2 } Branch { Points [0, 275] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "bc2" SrcPort 1 DstBlock "AddSub" DstPort 3 } Line { SrcBlock "bc3" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "ld" SrcPort 1 Points [45, 0] Branch { DstBlock "bc3" DstPort 1 } Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "Register1" SrcPort 1 Points [-15, 0] DstBlock "AddSub" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 Points [15, 0] Branch { DstBlock "yn" DstPort 1 } Branch { Points [0, 50; 110, 0; 0, 385; -260, 0; 0, -110] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "AddSub" SrcPort 1 Points [0, 0; 5, 0] Branch { Points [40, 0] Branch { DstBlock "Register2" DstPort 1 } Branch { Points [0, -95] DstBlock "Register1" DstPort 1 } Branch { Points [0, 160] DstBlock "accrm" DstPort 1 } } Branch { Points [0, 305] DstBlock "Gateway Out8" DstPort 1 } } Line { SrcBlock "a" SrcPort 1 Points [140, 0] Branch { DstBlock "bc2" DstPort 1 } Branch { Points [0, 275] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "Gateway Out8" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out7" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out6" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out1" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out2" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out3" SrcPort 1 Points [50, 0] } Line { SrcBlock "rst" SrcPort 1 Points [90, 0] Branch { Points [255, 0; 0, -180] DstBlock "Register1" DstPort 2 } Branch { Points [0, 215] DstBlock "Gateway Out1" DstPort 1 } } } } Block { BlockType Reference Name "ROM" SID "14120" Ports [1, 1] Position [440, 328, 490, 372] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/ROM" SourceType "Xilinx Single Port Read-Only Memory Block" depth "length(coef2)" initVector "coef2" distributed_mem "Distributed memory" rst off init_reg "0" en off latency "1" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "longCorr_coef_nbits" bin_pt "longCorr_coef_bp" preci_type "Single" exp_width "8" frac_width "24" dbl_ovrd off optimize "Area" use_rpm off xl_use_area off xl_area "[1 1 0 1 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,308" block_type "sprom" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,44,1,1,white,blue,0,bbc23d60,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 44 44 0 ]);\npatch([11.65 20.32 26.32 32.32 38.32 26.32 17.65 11.65 ],[28.66" " 28.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([17.65 26.32 20.32 11.65 17.65 ],[22.66 22.66 28." "66 28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([11.65 20.32 26.32 17.65 11.65 ],[16.66 16.66 22.66 22.66 16.66 ]" ",[1 1 1 ]);\npatch([17.65 38.32 32.32 26.32 20.32 11.65 17.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'addr');\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end" " icon text');\n" } Block { BlockType Outport Name "x_dly" SID "14121" Position [790, 178, 820, 192] IconDisplay "Port number" } Block { BlockType Outport Name "x_dly_vout" SID "14122" Position [790, 223, 820, 237] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "y" SID "14123" Position [790, 293, 820, 307] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "y_vout" SID "14124" Position [785, 448, 815, 462] Port "4" IconDisplay "Port number" } Line { SrcBlock "From2" SrcPort 1 Points [145, 0] Branch { Points [90, 0] Branch { Points [0, -50] Branch { DstBlock "MAC" DstPort 3 } Branch { Points [0, -90; 160, 0] } } Branch { Points [0, 65] DstBlock "Delay" DstPort 1 } } Branch { Points [0, 260] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "ROM" SrcPort 1 Points [5, 0] Branch { Points [0, -35] DstBlock "MAC" DstPort 2 } Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "MAC" SrcPort 1 Points [0, -5; 15, 0] Branch { DstBlock "y" DstPort 1 } Branch { Points [0, 365] DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "ASR" SrcPort 1 Points [35, 0] Branch { DstBlock "MAC" DstPort 1 } Branch { Points [0, -105] DstBlock "x_dly" DstPort 1 } Branch { Points [0, 330] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "From1" SrcPort 1 Points [5, 0] Branch { DstBlock "ROM" DstPort 1 } Branch { Points [0, 330] DstBlock "Gateway Out5" DstPort 1 } } Line { SrcBlock "From" SrcPort 1 Points [90, 0] Branch { DstBlock "ASR" DstPort 2 } Branch { Points [0, 300] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "x" SrcPort 1 Points [100, 0] Branch { DstBlock "ASR" DstPort 1 } Branch { Points [0, 305] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "vin" SrcPort 1 Points [25, 0] Branch { DstBlock "ASR" DstPort 3 } Branch { Points [0, 100] Branch { Points [0, 195] DstBlock "Gateway Out8" DstPort 1 } Branch { Points [230, 0] DstBlock "MAC" DstPort 4 } } Branch { Points [0, -80] DstBlock "x_dly_vout" DstPort 1 } } Line { SrcBlock "Delay" SrcPort 1 DstBlock "y_vout" DstPort 1 } Line { Name "X Vin" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 Points [150, 0] } Line { Name "ASR Addr" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 Points [150, 0] } Line { Name "X In" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 Points [150, 0] } Line { Name "ASR Out" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 Points [150, 0] } Line { Name "ROM Out" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 Points [150, 0] } Line { Name "Corr Ld" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 Points [150, 0] } Line { Name "Corr Out" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 Points [150, 0] } Line { Name "ROM Addr" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 Points [150, 0] } } } Block { BlockType SubSystem Name "C4" SID "14125" Ports [4, 4] Position [630, 207, 700, 293] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskPromptString "Coefficients (all)|Sub-correlator Ind|Coef/correlator" MaskStyleString "edit,edit,edit" MaskVariables "h=@1;c_ind=@2;N=@3;" MaskTunableValueString "on,on,on" MaskCallbackString "||" MaskEnableString "on,on,on" MaskVisibilityString "on,on,on" MaskToolTipString "on,on,on" MaskInitialization "coef2 = h((c_ind*N+1) : (c_ind + 1)*N);" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "h|3|N" System { Name "C4" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "122" Block { BlockType Inport Name "x" SID "14126" Position [265, 263, 295, 277] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "vin" SID "14127" Position [270, 303, 300, 317] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "14128" Position [270, 458, 300, 472] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "14129" Position [270, 503, 300, 517] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "ASR" SID "14130" Ports [3, 1] Position [445, 260, 490, 320] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Addressable Shift Register" SourceType "Xilinx Addressable Shift Register Block" infoedit "Delay of configurable length. Any element in the delay line can be addressed and driven onto the" " output port.

Hardware notes: This block is implemented using SRL16s. If Virtex-4 or Spartan-3 device is " "used, multiple SRLC16s are cascaded together." infer_latency off depth "length(coef2)" initVector "[0]" en on dbl_ovrd off use_behavioral_HDL off Optimization "Resource" xl_use_area off xl_area "[1 0 0 2 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,401" block_type "addrsr" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,60,3,1,white,blue,0,f8ea6153,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 60 60 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 60 60 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[36.66 3" "6.66 42.66 36.66 42.66 42.66 42.66 36.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[30.66 30.66 36.66 " "36.66 30.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[24.66 24.66 30.66 30.66 24.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[18.66 18.66 24.66 18.66 24.66 24.66 18.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'addr');\ncolor('black');port_label('input',3," "'en');\ncolor('black');port_label('output',1,'q');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Delay" SID "14131" Ports [1, 1] Position [705, 441, 730, 469] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "25,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 " "17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33" " 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('blac" "k');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "14132" Position [210, 280, 300, 300] ZOrder -9 ShowName off GotoTag "ltsCorr_dAddr" TagVisibility "scoped" } Block { BlockType From Name "From1" SID "14133" Position [210, 340, 300, 360] ZOrder -9 ShowName off GotoTag "ltsCorr_cAddr" TagVisibility "scoped" } Block { BlockType From Name "From2" SID "14134" Position [210, 380, 300, 400] ZOrder -9 ShowName off GotoTag "ltsCorr_ld" TagVisibility "scoped" } Block { BlockType Reference Name "Gateway Out1" SID "14135" Ports [1, 1] Position [745, 615, 780, 625] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "14136" Ports [1, 1] Position [745, 630, 780, 640] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "14137" Ports [1, 1] Position [745, 645, 780, 655] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Ld" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "14138" Ports [1, 1] Position [745, 660, 780, 670] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "14139" Ports [1, 1] Position [745, 675, 780, 685] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "14140" Ports [1, 1] Position [745, 570, 780, 580] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X In" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "14141" Ports [1, 1] Position [745, 585, 780, 595] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "14142" Ports [1, 1] Position [745, 600, 780, 610] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X Vin" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType SubSystem Name "MAC" SID "14143" Ports [4, 2] Position [575, 279, 660, 376] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "MAC" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "a" SID "14144" Position [35, 143, 65, 157] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "coeff" SID "14145" Position [35, 108, 65, 122] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "ld" SID "14146" Position [35, 178, 65, 192] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "rst" SID "14147" Position [35, 233, 65, 247] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub" SID "14148" Ports [3, 1] Position [340, 113, 385, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition or Subtraction" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Signed (2's comp)" n_bits "long_cor_acc_n_bits" bin_pt "0" quantization "Truncate" overflow "Flag as error" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[2 0 0 4 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,344" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,3,1,white,blue,0,02f64c57,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('input',3,'su" "b');\ncolor('black');port_label('output',1,'\\bf{a \\pm b}','texmode','on');\nfprintf('','COMMENT: end icon text" "');\n" } Block { BlockType Reference Name "Gateway Out1" SID "14149" Ports [1, 1] Position [475, 450, 510, 460] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out2" SID "14150" Ports [1, 1] Position [475, 465, 510, 475] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out3" SID "14151" Ports [1, 1] Position [475, 480, 510, 490] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out6" SID "14152" Ports [1, 1] Position [475, 405, 510, 415] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out7" SID "14153" Ports [1, 1] Position [475, 420, 510, 430] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out8" SID "14154" Ports [1, 1] Position [475, 435, 510, 445] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "14155" Ports [2, 1] Position [345, 30, 385, 70] BlockMirror on NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,40,2,1,white,blue,0,140cc11c,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'" "q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "14156" Ports [2, 1] Position [465, 110, 495, 210] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,100,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 100 100 0 ],[0.77 0." "82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 100 100 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[54.44 " "54.44 58.44 54.44 58.44 58.44 58.44 54.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[50.44 50.44 54.44 54" ".44 50.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[46.44 46.44 50.44 50.44 46.44 ],[1 1 1 ])" ";\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[42.44 42.44 46.44 42.44 46.44 46.44 42.44 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\nco" "lor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc2" SID "14157" Ports [1, 1] Position [265, 143, 290, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc3" SID "14158" Ports [1, 1] Position [135, 178, 160, 192] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "yn" SID "14159" Position [545, 153, 575, 167] IconDisplay "Port number" } Block { BlockType Outport Name "accrm" SID "14160" Position [520, 288, 550, 302] Port "2" IconDisplay "Port number" } Line { SrcBlock "rst" SrcPort 1 Points [90, 0] Branch { Points [0, 215] DstBlock "Gateway Out1" DstPort 1 } Branch { Points [255, 0; 0, -180] DstBlock "Register1" DstPort 2 } } Line { SrcBlock "Gateway Out3" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out2" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out1" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out6" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out7" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out8" SrcPort 1 Points [50, 0] } Line { SrcBlock "a" SrcPort 1 Points [140, 0] Branch { Points [0, 275] DstBlock "Gateway Out7" DstPort 1 } Branch { DstBlock "bc2" DstPort 1 } } Line { SrcBlock "AddSub" SrcPort 1 Points [0, 0; 5, 0] Branch { Points [0, 305] DstBlock "Gateway Out8" DstPort 1 } Branch { Points [40, 0] Branch { Points [0, 160] DstBlock "accrm" DstPort 1 } Branch { Points [0, -95] DstBlock "Register1" DstPort 1 } Branch { DstBlock "Register2" DstPort 1 } } } Line { SrcBlock "Register2" SrcPort 1 Points [15, 0] Branch { Points [0, 50; 110, 0; 0, 385; -260, 0; 0, -110] DstBlock "Gateway Out3" DstPort 1 } Branch { DstBlock "yn" DstPort 1 } } Line { SrcBlock "Register1" SrcPort 1 Points [-15, 0] DstBlock "AddSub" DstPort 1 } Line { SrcBlock "ld" SrcPort 1 Points [45, 0] Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } Branch { DstBlock "bc3" DstPort 1 } } Line { SrcBlock "bc3" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "bc2" SrcPort 1 DstBlock "AddSub" DstPort 3 } Line { SrcBlock "coeff" SrcPort 1 Points [95, 0; 0, 20; 50, 0] Branch { Points [0, 275] DstBlock "Gateway Out6" DstPort 1 } Branch { DstBlock "AddSub" DstPort 2 } } } } Block { BlockType Reference Name "ROM" SID "14161" Ports [1, 1] Position [440, 328, 490, 372] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/ROM" SourceType "Xilinx Single Port Read-Only Memory Block" depth "length(coef2)" initVector "coef2" distributed_mem "Distributed memory" rst off init_reg "0" en off latency "1" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "longCorr_coef_nbits" bin_pt "longCorr_coef_bp" preci_type "Single" exp_width "8" frac_width "24" dbl_ovrd off optimize "Area" use_rpm off xl_use_area off xl_area "[1 1 0 1 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,308" block_type "sprom" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,44,1,1,white,blue,0,bbc23d60,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 44 44 0 ]);\npatch([11.65 20.32 26.32 32.32 38.32 26.32 17.65 11.65 ],[28.66" " 28.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([17.65 26.32 20.32 11.65 17.65 ],[22.66 22.66 28." "66 28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([11.65 20.32 26.32 17.65 11.65 ],[16.66 16.66 22.66 22.66 16.66 ]" ",[1 1 1 ]);\npatch([17.65 38.32 32.32 26.32 20.32 11.65 17.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'addr');\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end" " icon text');\n" } Block { BlockType Outport Name "x_dly" SID "14162" Position [790, 178, 820, 192] IconDisplay "Port number" } Block { BlockType Outport Name "x_dly_vout" SID "14163" Position [790, 223, 820, 237] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "y" SID "14164" Position [790, 293, 820, 307] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "y_vout" SID "14165" Position [785, 448, 815, 462] Port "4" IconDisplay "Port number" } Line { Name "ROM Addr" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 Points [150, 0] } Line { Name "Corr Out" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 Points [150, 0] } Line { Name "Corr Ld" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 Points [150, 0] } Line { Name "ROM Out" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 Points [150, 0] } Line { Name "ASR Out" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 Points [150, 0] } Line { Name "X In" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 Points [150, 0] } Line { Name "ASR Addr" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 Points [150, 0] } Line { Name "X Vin" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 Points [150, 0] } Line { SrcBlock "Delay" SrcPort 1 DstBlock "y_vout" DstPort 1 } Line { SrcBlock "vin" SrcPort 1 Points [25, 0] Branch { Points [0, -80] DstBlock "x_dly_vout" DstPort 1 } Branch { Points [0, 100] Branch { Points [230, 0] DstBlock "MAC" DstPort 4 } Branch { Points [0, 195] DstBlock "Gateway Out8" DstPort 1 } } Branch { DstBlock "ASR" DstPort 3 } } Line { SrcBlock "x" SrcPort 1 Points [100, 0] Branch { Points [0, 305] DstBlock "Gateway Out6" DstPort 1 } Branch { DstBlock "ASR" DstPort 1 } } Line { SrcBlock "From" SrcPort 1 Points [90, 0] Branch { Points [0, 300] DstBlock "Gateway Out7" DstPort 1 } Branch { DstBlock "ASR" DstPort 2 } } Line { SrcBlock "From1" SrcPort 1 Points [5, 0] Branch { Points [0, 330] DstBlock "Gateway Out5" DstPort 1 } Branch { DstBlock "ROM" DstPort 1 } } Line { SrcBlock "ASR" SrcPort 1 Points [35, 0] Branch { Points [0, 330] DstBlock "Gateway Out1" DstPort 1 } Branch { Points [0, -105] DstBlock "x_dly" DstPort 1 } Branch { DstBlock "MAC" DstPort 1 } } Line { SrcBlock "MAC" SrcPort 1 Points [0, -5; 15, 0] Branch { Points [0, 365] DstBlock "Gateway Out4" DstPort 1 } Branch { DstBlock "y" DstPort 1 } } Line { SrcBlock "ROM" SrcPort 1 Points [5, 0] Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } Branch { Points [0, -35] DstBlock "MAC" DstPort 2 } } Line { SrcBlock "From2" SrcPort 1 Points [145, 0] Branch { Points [0, 260] DstBlock "Gateway Out3" DstPort 1 } Branch { Points [90, 0] Branch { Points [0, 65] DstBlock "Delay" DstPort 1 } Branch { Points [0, -50] Branch { Points [0, -90; 160, 0] } Branch { DstBlock "MAC" DstPort 3 } } } } } } Block { BlockType SubSystem Name "C5" SID "14166" Ports [4, 4] Position [740, 207, 810, 293] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskPromptString "Coefficients (all)|Sub-correlator Ind|Coef/correlator" MaskStyleString "edit,edit,edit" MaskVariables "h=@1;c_ind=@2;N=@3;" MaskTunableValueString "on,on,on" MaskCallbackString "||" MaskEnableString "on,on,on" MaskVisibilityString "on,on,on" MaskToolTipString "on,on,on" MaskInitialization "coef2 = h((c_ind*N+1) : (c_ind + 1)*N);" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "h|4|N" System { Name "C5" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "122" Block { BlockType Inport Name "x" SID "14167" Position [265, 263, 295, 277] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "vin" SID "14168" Position [270, 303, 300, 317] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "14169" Position [270, 458, 300, 472] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "14170" Position [270, 503, 300, 517] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "ASR" SID "14171" Ports [3, 1] Position [445, 260, 490, 320] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Addressable Shift Register" SourceType "Xilinx Addressable Shift Register Block" infoedit "Delay of configurable length. Any element in the delay line can be addressed and driven onto the" " output port.

Hardware notes: This block is implemented using SRL16s. If Virtex-4 or Spartan-3 device is " "used, multiple SRLC16s are cascaded together." infer_latency off depth "length(coef2)" initVector "[0]" en on dbl_ovrd off use_behavioral_HDL off Optimization "Resource" xl_use_area off xl_area "[1 0 0 2 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,401" block_type "addrsr" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,60,3,1,white,blue,0,f8ea6153,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 60 60 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 60 60 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[36.66 3" "6.66 42.66 36.66 42.66 42.66 42.66 36.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[30.66 30.66 36.66 " "36.66 30.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[24.66 24.66 30.66 30.66 24.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[18.66 18.66 24.66 18.66 24.66 24.66 18.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'addr');\ncolor('black');port_label('input',3," "'en');\ncolor('black');port_label('output',1,'q');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Delay" SID "14172" Ports [1, 1] Position [705, 441, 730, 469] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "25,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 " "17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33" " 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('blac" "k');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "14173" Position [210, 280, 300, 300] ZOrder -9 ShowName off GotoTag "ltsCorr_dAddr" TagVisibility "scoped" } Block { BlockType From Name "From1" SID "14174" Position [210, 340, 300, 360] ZOrder -9 ShowName off GotoTag "ltsCorr_cAddr" TagVisibility "scoped" } Block { BlockType From Name "From2" SID "14175" Position [210, 380, 300, 400] ZOrder -9 ShowName off GotoTag "ltsCorr_ld" TagVisibility "scoped" } Block { BlockType Reference Name "Gateway Out1" SID "14176" Ports [1, 1] Position [745, 615, 780, 625] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "14177" Ports [1, 1] Position [745, 630, 780, 640] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "14178" Ports [1, 1] Position [745, 645, 780, 655] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Ld" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "14179" Ports [1, 1] Position [745, 660, 780, 670] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "14180" Ports [1, 1] Position [745, 675, 780, 685] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "14181" Ports [1, 1] Position [745, 570, 780, 580] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X In" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "14182" Ports [1, 1] Position [745, 585, 780, 595] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "14183" Ports [1, 1] Position [745, 600, 780, 610] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X Vin" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType SubSystem Name "MAC" SID "14184" Ports [4, 2] Position [575, 279, 660, 376] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "MAC" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "a" SID "14185" Position [35, 143, 65, 157] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "coeff" SID "14186" Position [35, 108, 65, 122] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "ld" SID "14187" Position [35, 178, 65, 192] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "rst" SID "14188" Position [35, 233, 65, 247] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub" SID "14189" Ports [3, 1] Position [340, 113, 385, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition or Subtraction" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Signed (2's comp)" n_bits "long_cor_acc_n_bits" bin_pt "0" quantization "Truncate" overflow "Flag as error" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[2 0 0 4 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,344" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,3,1,white,blue,0,02f64c57,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('input',3,'su" "b');\ncolor('black');port_label('output',1,'\\bf{a \\pm b}','texmode','on');\nfprintf('','COMMENT: end icon text" "');\n" } Block { BlockType Reference Name "Gateway Out1" SID "14190" Ports [1, 1] Position [475, 450, 510, 460] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out2" SID "14191" Ports [1, 1] Position [475, 465, 510, 475] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out3" SID "14192" Ports [1, 1] Position [475, 480, 510, 490] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out6" SID "14193" Ports [1, 1] Position [475, 405, 510, 415] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out7" SID "14194" Ports [1, 1] Position [475, 420, 510, 430] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out8" SID "14195" Ports [1, 1] Position [475, 435, 510, 445] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "14196" Ports [2, 1] Position [345, 30, 385, 70] BlockMirror on NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,40,2,1,white,blue,0,140cc11c,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'" "q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "14197" Ports [2, 1] Position [465, 110, 495, 210] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,100,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 100 100 0 ],[0.77 0." "82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 100 100 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[54.44 " "54.44 58.44 54.44 58.44 58.44 58.44 54.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[50.44 50.44 54.44 54" ".44 50.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[46.44 46.44 50.44 50.44 46.44 ],[1 1 1 ])" ";\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[42.44 42.44 46.44 42.44 46.44 46.44 42.44 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\nco" "lor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc2" SID "14198" Ports [1, 1] Position [265, 143, 290, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc3" SID "14199" Ports [1, 1] Position [135, 178, 160, 192] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "yn" SID "14200" Position [545, 153, 575, 167] IconDisplay "Port number" } Block { BlockType Outport Name "accrm" SID "14201" Position [520, 288, 550, 302] Port "2" IconDisplay "Port number" } Line { SrcBlock "coeff" SrcPort 1 Points [95, 0; 0, 20; 50, 0] Branch { DstBlock "AddSub" DstPort 2 } Branch { Points [0, 275] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "bc2" SrcPort 1 DstBlock "AddSub" DstPort 3 } Line { SrcBlock "bc3" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "ld" SrcPort 1 Points [45, 0] Branch { DstBlock "bc3" DstPort 1 } Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "Register1" SrcPort 1 Points [-15, 0] DstBlock "AddSub" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 Points [15, 0] Branch { DstBlock "yn" DstPort 1 } Branch { Points [0, 50; 110, 0; 0, 385; -260, 0; 0, -110] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "AddSub" SrcPort 1 Points [0, 0; 5, 0] Branch { Points [40, 0] Branch { DstBlock "Register2" DstPort 1 } Branch { Points [0, -95] DstBlock "Register1" DstPort 1 } Branch { Points [0, 160] DstBlock "accrm" DstPort 1 } } Branch { Points [0, 305] DstBlock "Gateway Out8" DstPort 1 } } Line { SrcBlock "a" SrcPort 1 Points [140, 0] Branch { DstBlock "bc2" DstPort 1 } Branch { Points [0, 275] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "Gateway Out8" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out7" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out6" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out1" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out2" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out3" SrcPort 1 Points [50, 0] } Line { SrcBlock "rst" SrcPort 1 Points [90, 0] Branch { Points [255, 0; 0, -180] DstBlock "Register1" DstPort 2 } Branch { Points [0, 215] DstBlock "Gateway Out1" DstPort 1 } } } } Block { BlockType Reference Name "ROM" SID "14202" Ports [1, 1] Position [440, 328, 490, 372] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/ROM" SourceType "Xilinx Single Port Read-Only Memory Block" depth "length(coef2)" initVector "coef2" distributed_mem "Distributed memory" rst off init_reg "0" en off latency "1" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "longCorr_coef_nbits" bin_pt "longCorr_coef_bp" preci_type "Single" exp_width "8" frac_width "24" dbl_ovrd off optimize "Area" use_rpm off xl_use_area off xl_area "[1 1 0 1 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,308" block_type "sprom" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,44,1,1,white,blue,0,bbc23d60,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 44 44 0 ]);\npatch([11.65 20.32 26.32 32.32 38.32 26.32 17.65 11.65 ],[28.66" " 28.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([17.65 26.32 20.32 11.65 17.65 ],[22.66 22.66 28." "66 28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([11.65 20.32 26.32 17.65 11.65 ],[16.66 16.66 22.66 22.66 16.66 ]" ",[1 1 1 ]);\npatch([17.65 38.32 32.32 26.32 20.32 11.65 17.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'addr');\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end" " icon text');\n" } Block { BlockType Outport Name "x_dly" SID "14203" Position [790, 178, 820, 192] IconDisplay "Port number" } Block { BlockType Outport Name "x_dly_vout" SID "14204" Position [790, 223, 820, 237] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "y" SID "14205" Position [790, 293, 820, 307] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "y_vout" SID "14206" Position [785, 448, 815, 462] Port "4" IconDisplay "Port number" } Line { SrcBlock "From2" SrcPort 1 Points [145, 0] Branch { Points [90, 0] Branch { Points [0, -50] Branch { DstBlock "MAC" DstPort 3 } Branch { Points [0, -90; 160, 0] } } Branch { Points [0, 65] DstBlock "Delay" DstPort 1 } } Branch { Points [0, 260] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "ROM" SrcPort 1 Points [5, 0] Branch { Points [0, -35] DstBlock "MAC" DstPort 2 } Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "MAC" SrcPort 1 Points [0, -5; 15, 0] Branch { DstBlock "y" DstPort 1 } Branch { Points [0, 365] DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "ASR" SrcPort 1 Points [35, 0] Branch { DstBlock "MAC" DstPort 1 } Branch { Points [0, -105] DstBlock "x_dly" DstPort 1 } Branch { Points [0, 330] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "From1" SrcPort 1 Points [5, 0] Branch { DstBlock "ROM" DstPort 1 } Branch { Points [0, 330] DstBlock "Gateway Out5" DstPort 1 } } Line { SrcBlock "From" SrcPort 1 Points [90, 0] Branch { DstBlock "ASR" DstPort 2 } Branch { Points [0, 300] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "x" SrcPort 1 Points [100, 0] Branch { DstBlock "ASR" DstPort 1 } Branch { Points [0, 305] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "vin" SrcPort 1 Points [25, 0] Branch { DstBlock "ASR" DstPort 3 } Branch { Points [0, 100] Branch { Points [0, 195] DstBlock "Gateway Out8" DstPort 1 } Branch { Points [230, 0] DstBlock "MAC" DstPort 4 } } Branch { Points [0, -80] DstBlock "x_dly_vout" DstPort 1 } } Line { SrcBlock "Delay" SrcPort 1 DstBlock "y_vout" DstPort 1 } Line { Name "X Vin" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 Points [150, 0] } Line { Name "ASR Addr" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 Points [150, 0] } Line { Name "X In" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 Points [150, 0] } Line { Name "ASR Out" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 Points [150, 0] } Line { Name "ROM Out" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 Points [150, 0] } Line { Name "Corr Ld" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 Points [150, 0] } Line { Name "Corr Out" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 Points [150, 0] } Line { Name "ROM Addr" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 Points [150, 0] } } } Block { BlockType SubSystem Name "C6" SID "14207" Ports [4, 4] Position [845, 207, 915, 293] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskPromptString "Coefficients (all)|Sub-correlator Ind|Coef/correlator" MaskStyleString "edit,edit,edit" MaskVariables "h=@1;c_ind=@2;N=@3;" MaskTunableValueString "on,on,on" MaskCallbackString "||" MaskEnableString "on,on,on" MaskVisibilityString "on,on,on" MaskToolTipString "on,on,on" MaskInitialization "coef2 = h((c_ind*N+1) : (c_ind + 1)*N);" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "h|5|N" System { Name "C6" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "122" Block { BlockType Inport Name "x" SID "14208" Position [265, 263, 295, 277] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "vin" SID "14209" Position [270, 303, 300, 317] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "14210" Position [270, 458, 300, 472] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "14211" Position [270, 503, 300, 517] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "ASR" SID "14212" Ports [3, 1] Position [445, 260, 490, 320] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Addressable Shift Register" SourceType "Xilinx Addressable Shift Register Block" infoedit "Delay of configurable length. Any element in the delay line can be addressed and driven onto the" " output port.

Hardware notes: This block is implemented using SRL16s. If Virtex-4 or Spartan-3 device is " "used, multiple SRLC16s are cascaded together." infer_latency off depth "length(coef2)" initVector "[0]" en on dbl_ovrd off use_behavioral_HDL off Optimization "Resource" xl_use_area off xl_area "[1 0 0 2 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,401" block_type "addrsr" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,60,3,1,white,blue,0,f8ea6153,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 60 60 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 60 60 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[36.66 3" "6.66 42.66 36.66 42.66 42.66 42.66 36.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[30.66 30.66 36.66 " "36.66 30.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[24.66 24.66 30.66 30.66 24.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[18.66 18.66 24.66 18.66 24.66 24.66 18.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'addr');\ncolor('black');port_label('input',3," "'en');\ncolor('black');port_label('output',1,'q');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Delay" SID "14213" Ports [1, 1] Position [705, 441, 730, 469] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "25,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 " "17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33" " 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('blac" "k');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "14214" Position [210, 280, 300, 300] ZOrder -9 ShowName off GotoTag "ltsCorr_dAddr" TagVisibility "scoped" } Block { BlockType From Name "From1" SID "14215" Position [210, 340, 300, 360] ZOrder -9 ShowName off GotoTag "ltsCorr_cAddr" TagVisibility "scoped" } Block { BlockType From Name "From2" SID "14216" Position [210, 380, 300, 400] ZOrder -9 ShowName off GotoTag "ltsCorr_ld" TagVisibility "scoped" } Block { BlockType Reference Name "Gateway Out1" SID "14217" Ports [1, 1] Position [745, 615, 780, 625] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "14218" Ports [1, 1] Position [745, 630, 780, 640] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "14219" Ports [1, 1] Position [745, 645, 780, 655] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Ld" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "14220" Ports [1, 1] Position [745, 660, 780, 670] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "14221" Ports [1, 1] Position [745, 675, 780, 685] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "14222" Ports [1, 1] Position [745, 570, 780, 580] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X In" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "14223" Ports [1, 1] Position [745, 585, 780, 595] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "14224" Ports [1, 1] Position [745, 600, 780, 610] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X Vin" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType SubSystem Name "MAC" SID "14225" Ports [4, 2] Position [575, 279, 660, 376] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "MAC" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "a" SID "14226" Position [35, 143, 65, 157] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "coeff" SID "14227" Position [35, 108, 65, 122] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "ld" SID "14228" Position [35, 178, 65, 192] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "rst" SID "14229" Position [35, 233, 65, 247] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub" SID "14230" Ports [3, 1] Position [340, 113, 385, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition or Subtraction" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Signed (2's comp)" n_bits "long_cor_acc_n_bits" bin_pt "0" quantization "Truncate" overflow "Flag as error" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[2 0 0 4 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,344" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,3,1,white,blue,0,02f64c57,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('input',3,'su" "b');\ncolor('black');port_label('output',1,'\\bf{a \\pm b}','texmode','on');\nfprintf('','COMMENT: end icon text" "');\n" } Block { BlockType Reference Name "Gateway Out1" SID "14231" Ports [1, 1] Position [475, 450, 510, 460] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out2" SID "14232" Ports [1, 1] Position [475, 465, 510, 475] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out3" SID "14233" Ports [1, 1] Position [475, 480, 510, 490] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out6" SID "14234" Ports [1, 1] Position [475, 405, 510, 415] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out7" SID "14235" Ports [1, 1] Position [475, 420, 510, 430] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out8" SID "14236" Ports [1, 1] Position [475, 435, 510, 445] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "14237" Ports [2, 1] Position [345, 30, 385, 70] BlockMirror on NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,40,2,1,white,blue,0,140cc11c,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'" "q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "14238" Ports [2, 1] Position [465, 110, 495, 210] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,100,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 100 100 0 ],[0.77 0." "82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 100 100 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[54.44 " "54.44 58.44 54.44 58.44 58.44 58.44 54.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[50.44 50.44 54.44 54" ".44 50.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[46.44 46.44 50.44 50.44 46.44 ],[1 1 1 ])" ";\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[42.44 42.44 46.44 42.44 46.44 46.44 42.44 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\nco" "lor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc2" SID "14239" Ports [1, 1] Position [265, 143, 290, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc3" SID "14240" Ports [1, 1] Position [135, 178, 160, 192] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "yn" SID "14241" Position [545, 153, 575, 167] IconDisplay "Port number" } Block { BlockType Outport Name "accrm" SID "14242" Position [520, 288, 550, 302] Port "2" IconDisplay "Port number" } Line { SrcBlock "rst" SrcPort 1 Points [90, 0] Branch { Points [0, 215] DstBlock "Gateway Out1" DstPort 1 } Branch { Points [255, 0; 0, -180] DstBlock "Register1" DstPort 2 } } Line { SrcBlock "Gateway Out3" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out2" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out1" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out6" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out7" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out8" SrcPort 1 Points [50, 0] } Line { SrcBlock "a" SrcPort 1 Points [140, 0] Branch { Points [0, 275] DstBlock "Gateway Out7" DstPort 1 } Branch { DstBlock "bc2" DstPort 1 } } Line { SrcBlock "AddSub" SrcPort 1 Points [0, 0; 5, 0] Branch { Points [0, 305] DstBlock "Gateway Out8" DstPort 1 } Branch { Points [40, 0] Branch { Points [0, 160] DstBlock "accrm" DstPort 1 } Branch { Points [0, -95] DstBlock "Register1" DstPort 1 } Branch { DstBlock "Register2" DstPort 1 } } } Line { SrcBlock "Register2" SrcPort 1 Points [15, 0] Branch { Points [0, 50; 110, 0; 0, 385; -260, 0; 0, -110] DstBlock "Gateway Out3" DstPort 1 } Branch { DstBlock "yn" DstPort 1 } } Line { SrcBlock "Register1" SrcPort 1 Points [-15, 0] DstBlock "AddSub" DstPort 1 } Line { SrcBlock "ld" SrcPort 1 Points [45, 0] Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } Branch { DstBlock "bc3" DstPort 1 } } Line { SrcBlock "bc3" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "bc2" SrcPort 1 DstBlock "AddSub" DstPort 3 } Line { SrcBlock "coeff" SrcPort 1 Points [95, 0; 0, 20; 50, 0] Branch { Points [0, 275] DstBlock "Gateway Out6" DstPort 1 } Branch { DstBlock "AddSub" DstPort 2 } } } } Block { BlockType Reference Name "ROM" SID "14243" Ports [1, 1] Position [440, 328, 490, 372] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/ROM" SourceType "Xilinx Single Port Read-Only Memory Block" depth "length(coef2)" initVector "coef2" distributed_mem "Distributed memory" rst off init_reg "0" en off latency "1" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "longCorr_coef_nbits" bin_pt "longCorr_coef_bp" preci_type "Single" exp_width "8" frac_width "24" dbl_ovrd off optimize "Area" use_rpm off xl_use_area off xl_area "[1 1 0 1 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,308" block_type "sprom" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,44,1,1,white,blue,0,bbc23d60,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 44 44 0 ]);\npatch([11.65 20.32 26.32 32.32 38.32 26.32 17.65 11.65 ],[28.66" " 28.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([17.65 26.32 20.32 11.65 17.65 ],[22.66 22.66 28." "66 28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([11.65 20.32 26.32 17.65 11.65 ],[16.66 16.66 22.66 22.66 16.66 ]" ",[1 1 1 ]);\npatch([17.65 38.32 32.32 26.32 20.32 11.65 17.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'addr');\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end" " icon text');\n" } Block { BlockType Outport Name "x_dly" SID "14244" Position [790, 178, 820, 192] IconDisplay "Port number" } Block { BlockType Outport Name "x_dly_vout" SID "14245" Position [790, 223, 820, 237] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "y" SID "14246" Position [790, 293, 820, 307] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "y_vout" SID "14247" Position [785, 448, 815, 462] Port "4" IconDisplay "Port number" } Line { Name "ROM Addr" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 Points [150, 0] } Line { Name "Corr Out" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 Points [150, 0] } Line { Name "Corr Ld" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 Points [150, 0] } Line { Name "ROM Out" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 Points [150, 0] } Line { Name "ASR Out" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 Points [150, 0] } Line { Name "X In" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 Points [150, 0] } Line { Name "ASR Addr" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 Points [150, 0] } Line { Name "X Vin" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 Points [150, 0] } Line { SrcBlock "Delay" SrcPort 1 DstBlock "y_vout" DstPort 1 } Line { SrcBlock "vin" SrcPort 1 Points [25, 0] Branch { Points [0, -80] DstBlock "x_dly_vout" DstPort 1 } Branch { Points [0, 100] Branch { Points [230, 0] DstBlock "MAC" DstPort 4 } Branch { Points [0, 195] DstBlock "Gateway Out8" DstPort 1 } } Branch { DstBlock "ASR" DstPort 3 } } Line { SrcBlock "x" SrcPort 1 Points [100, 0] Branch { Points [0, 305] DstBlock "Gateway Out6" DstPort 1 } Branch { DstBlock "ASR" DstPort 1 } } Line { SrcBlock "From" SrcPort 1 Points [90, 0] Branch { Points [0, 300] DstBlock "Gateway Out7" DstPort 1 } Branch { DstBlock "ASR" DstPort 2 } } Line { SrcBlock "From1" SrcPort 1 Points [5, 0] Branch { Points [0, 330] DstBlock "Gateway Out5" DstPort 1 } Branch { DstBlock "ROM" DstPort 1 } } Line { SrcBlock "ASR" SrcPort 1 Points [35, 0] Branch { Points [0, 330] DstBlock "Gateway Out1" DstPort 1 } Branch { Points [0, -105] DstBlock "x_dly" DstPort 1 } Branch { DstBlock "MAC" DstPort 1 } } Line { SrcBlock "MAC" SrcPort 1 Points [0, -5; 15, 0] Branch { Points [0, 365] DstBlock "Gateway Out4" DstPort 1 } Branch { DstBlock "y" DstPort 1 } } Line { SrcBlock "ROM" SrcPort 1 Points [5, 0] Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } Branch { Points [0, -35] DstBlock "MAC" DstPort 2 } } Line { SrcBlock "From2" SrcPort 1 Points [145, 0] Branch { Points [0, 260] DstBlock "Gateway Out3" DstPort 1 } Branch { Points [90, 0] Branch { Points [0, 65] DstBlock "Delay" DstPort 1 } Branch { Points [0, -50] Branch { Points [0, -90; 160, 0] } Branch { DstBlock "MAC" DstPort 3 } } } } } } Block { BlockType SubSystem Name "C7" SID "14248" Ports [4, 4] Position [950, 207, 1020, 293] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskPromptString "Coefficients (all)|Sub-correlator Ind|Coef/correlator" MaskStyleString "edit,edit,edit" MaskVariables "h=@1;c_ind=@2;N=@3;" MaskTunableValueString "on,on,on" MaskCallbackString "||" MaskEnableString "on,on,on" MaskVisibilityString "on,on,on" MaskToolTipString "on,on,on" MaskInitialization "coef2 = h((c_ind*N+1) : (c_ind + 1)*N);" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "h|6|N" System { Name "C7" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "122" Block { BlockType Inport Name "x" SID "14249" Position [265, 263, 295, 277] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "vin" SID "14250" Position [270, 303, 300, 317] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "14251" Position [270, 458, 300, 472] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "14252" Position [270, 503, 300, 517] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "ASR" SID "14253" Ports [3, 1] Position [445, 260, 490, 320] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Addressable Shift Register" SourceType "Xilinx Addressable Shift Register Block" infoedit "Delay of configurable length. Any element in the delay line can be addressed and driven onto the" " output port.

Hardware notes: This block is implemented using SRL16s. If Virtex-4 or Spartan-3 device is " "used, multiple SRLC16s are cascaded together." infer_latency off depth "length(coef2)" initVector "[0]" en on dbl_ovrd off use_behavioral_HDL off Optimization "Resource" xl_use_area off xl_area "[1 0 0 2 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,401" block_type "addrsr" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,60,3,1,white,blue,0,f8ea6153,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 60 60 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 60 60 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[36.66 3" "6.66 42.66 36.66 42.66 42.66 42.66 36.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[30.66 30.66 36.66 " "36.66 30.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[24.66 24.66 30.66 30.66 24.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[18.66 18.66 24.66 18.66 24.66 24.66 18.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'addr');\ncolor('black');port_label('input',3," "'en');\ncolor('black');port_label('output',1,'q');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Delay" SID "14254" Ports [1, 1] Position [705, 441, 730, 469] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "25,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 " "17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33" " 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('blac" "k');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "14255" Position [210, 280, 300, 300] ZOrder -9 ShowName off GotoTag "ltsCorr_dAddr" TagVisibility "scoped" } Block { BlockType From Name "From1" SID "14256" Position [210, 340, 300, 360] ZOrder -9 ShowName off GotoTag "ltsCorr_cAddr" TagVisibility "scoped" } Block { BlockType From Name "From2" SID "14257" Position [210, 380, 300, 400] ZOrder -9 ShowName off GotoTag "ltsCorr_ld" TagVisibility "scoped" } Block { BlockType Reference Name "Gateway Out1" SID "14258" Ports [1, 1] Position [745, 615, 780, 625] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "14259" Ports [1, 1] Position [745, 630, 780, 640] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "14260" Ports [1, 1] Position [745, 645, 780, 655] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Ld" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "14261" Ports [1, 1] Position [745, 660, 780, 670] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "14262" Ports [1, 1] Position [745, 675, 780, 685] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "14263" Ports [1, 1] Position [745, 570, 780, 580] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X In" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "14264" Ports [1, 1] Position [745, 585, 780, 595] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "14265" Ports [1, 1] Position [745, 600, 780, 610] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X Vin" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType SubSystem Name "MAC" SID "14266" Ports [4, 2] Position [575, 279, 660, 376] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "MAC" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "a" SID "14267" Position [35, 143, 65, 157] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "coeff" SID "14268" Position [35, 108, 65, 122] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "ld" SID "14269" Position [35, 178, 65, 192] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "rst" SID "14270" Position [35, 233, 65, 247] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub" SID "14271" Ports [3, 1] Position [340, 113, 385, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition or Subtraction" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Signed (2's comp)" n_bits "long_cor_acc_n_bits" bin_pt "0" quantization "Truncate" overflow "Flag as error" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[2 0 0 4 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,344" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,3,1,white,blue,0,02f64c57,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('input',3,'su" "b');\ncolor('black');port_label('output',1,'\\bf{a \\pm b}','texmode','on');\nfprintf('','COMMENT: end icon text" "');\n" } Block { BlockType Reference Name "Gateway Out1" SID "14272" Ports [1, 1] Position [475, 450, 510, 460] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out2" SID "14273" Ports [1, 1] Position [475, 465, 510, 475] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out3" SID "14274" Ports [1, 1] Position [475, 480, 510, 490] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out6" SID "14275" Ports [1, 1] Position [475, 405, 510, 415] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out7" SID "14276" Ports [1, 1] Position [475, 420, 510, 430] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out8" SID "14277" Ports [1, 1] Position [475, 435, 510, 445] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "14278" Ports [2, 1] Position [345, 30, 385, 70] BlockMirror on NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,40,2,1,white,blue,0,140cc11c,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'" "q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "14279" Ports [2, 1] Position [465, 110, 495, 210] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,100,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 100 100 0 ],[0.77 0." "82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 100 100 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[54.44 " "54.44 58.44 54.44 58.44 58.44 58.44 54.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[50.44 50.44 54.44 54" ".44 50.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[46.44 46.44 50.44 50.44 46.44 ],[1 1 1 ])" ";\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[42.44 42.44 46.44 42.44 46.44 46.44 42.44 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\nco" "lor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc2" SID "14280" Ports [1, 1] Position [265, 143, 290, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc3" SID "14281" Ports [1, 1] Position [135, 178, 160, 192] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "yn" SID "14282" Position [545, 153, 575, 167] IconDisplay "Port number" } Block { BlockType Outport Name "accrm" SID "14283" Position [520, 288, 550, 302] Port "2" IconDisplay "Port number" } Line { SrcBlock "coeff" SrcPort 1 Points [95, 0; 0, 20; 50, 0] Branch { DstBlock "AddSub" DstPort 2 } Branch { Points [0, 275] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "bc2" SrcPort 1 DstBlock "AddSub" DstPort 3 } Line { SrcBlock "bc3" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "ld" SrcPort 1 Points [45, 0] Branch { DstBlock "bc3" DstPort 1 } Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "Register1" SrcPort 1 Points [-15, 0] DstBlock "AddSub" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 Points [15, 0] Branch { DstBlock "yn" DstPort 1 } Branch { Points [0, 50; 110, 0; 0, 385; -260, 0; 0, -110] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "AddSub" SrcPort 1 Points [0, 0; 5, 0] Branch { Points [40, 0] Branch { DstBlock "Register2" DstPort 1 } Branch { Points [0, -95] DstBlock "Register1" DstPort 1 } Branch { Points [0, 160] DstBlock "accrm" DstPort 1 } } Branch { Points [0, 305] DstBlock "Gateway Out8" DstPort 1 } } Line { SrcBlock "a" SrcPort 1 Points [140, 0] Branch { DstBlock "bc2" DstPort 1 } Branch { Points [0, 275] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "Gateway Out8" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out7" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out6" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out1" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out2" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out3" SrcPort 1 Points [50, 0] } Line { SrcBlock "rst" SrcPort 1 Points [90, 0] Branch { Points [255, 0; 0, -180] DstBlock "Register1" DstPort 2 } Branch { Points [0, 215] DstBlock "Gateway Out1" DstPort 1 } } } } Block { BlockType Reference Name "ROM" SID "14284" Ports [1, 1] Position [440, 328, 490, 372] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/ROM" SourceType "Xilinx Single Port Read-Only Memory Block" depth "length(coef2)" initVector "coef2" distributed_mem "Distributed memory" rst off init_reg "0" en off latency "1" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "longCorr_coef_nbits" bin_pt "longCorr_coef_bp" preci_type "Single" exp_width "8" frac_width "24" dbl_ovrd off optimize "Area" use_rpm off xl_use_area off xl_area "[1 1 0 1 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,308" block_type "sprom" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,44,1,1,white,blue,0,bbc23d60,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 44 44 0 ]);\npatch([11.65 20.32 26.32 32.32 38.32 26.32 17.65 11.65 ],[28.66" " 28.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([17.65 26.32 20.32 11.65 17.65 ],[22.66 22.66 28." "66 28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([11.65 20.32 26.32 17.65 11.65 ],[16.66 16.66 22.66 22.66 16.66 ]" ",[1 1 1 ]);\npatch([17.65 38.32 32.32 26.32 20.32 11.65 17.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'addr');\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end" " icon text');\n" } Block { BlockType Outport Name "x_dly" SID "14285" Position [790, 178, 820, 192] IconDisplay "Port number" } Block { BlockType Outport Name "x_dly_vout" SID "14286" Position [790, 223, 820, 237] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "y" SID "14287" Position [790, 293, 820, 307] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "y_vout" SID "14288" Position [785, 448, 815, 462] Port "4" IconDisplay "Port number" } Line { SrcBlock "From2" SrcPort 1 Points [145, 0] Branch { Points [90, 0] Branch { Points [0, -50] Branch { DstBlock "MAC" DstPort 3 } Branch { Points [0, -90; 160, 0] } } Branch { Points [0, 65] DstBlock "Delay" DstPort 1 } } Branch { Points [0, 260] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "ROM" SrcPort 1 Points [5, 0] Branch { Points [0, -35] DstBlock "MAC" DstPort 2 } Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "MAC" SrcPort 1 Points [0, -5; 15, 0] Branch { DstBlock "y" DstPort 1 } Branch { Points [0, 365] DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "ASR" SrcPort 1 Points [35, 0] Branch { DstBlock "MAC" DstPort 1 } Branch { Points [0, -105] DstBlock "x_dly" DstPort 1 } Branch { Points [0, 330] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "From1" SrcPort 1 Points [5, 0] Branch { DstBlock "ROM" DstPort 1 } Branch { Points [0, 330] DstBlock "Gateway Out5" DstPort 1 } } Line { SrcBlock "From" SrcPort 1 Points [90, 0] Branch { DstBlock "ASR" DstPort 2 } Branch { Points [0, 300] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "x" SrcPort 1 Points [100, 0] Branch { DstBlock "ASR" DstPort 1 } Branch { Points [0, 305] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "vin" SrcPort 1 Points [25, 0] Branch { DstBlock "ASR" DstPort 3 } Branch { Points [0, 100] Branch { Points [0, 195] DstBlock "Gateway Out8" DstPort 1 } Branch { Points [230, 0] DstBlock "MAC" DstPort 4 } } Branch { Points [0, -80] DstBlock "x_dly_vout" DstPort 1 } } Line { SrcBlock "Delay" SrcPort 1 DstBlock "y_vout" DstPort 1 } Line { Name "X Vin" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 Points [150, 0] } Line { Name "ASR Addr" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 Points [150, 0] } Line { Name "X In" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 Points [150, 0] } Line { Name "ASR Out" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 Points [150, 0] } Line { Name "ROM Out" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 Points [150, 0] } Line { Name "Corr Ld" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 Points [150, 0] } Line { Name "Corr Out" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 Points [150, 0] } Line { Name "ROM Addr" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 Points [150, 0] } } } Block { BlockType SubSystem Name "C8" SID "14289" Ports [4, 4] Position [1060, 207, 1130, 293] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskPromptString "Coefficients (all)|Sub-correlator Ind|Coef/correlator" MaskStyleString "edit,edit,edit" MaskVariables "h=@1;c_ind=@2;N=@3;" MaskTunableValueString "on,on,on" MaskCallbackString "||" MaskEnableString "on,on,on" MaskVisibilityString "on,on,on" MaskToolTipString "on,on,on" MaskInitialization "coef2 = h((c_ind*N+1) : (c_ind + 1)*N);" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "h|7|N" System { Name "C8" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "122" Block { BlockType Inport Name "x" SID "14290" Position [265, 263, 295, 277] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "vin" SID "14291" Position [270, 303, 300, 317] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "14292" Position [270, 458, 300, 472] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "14293" Position [270, 503, 300, 517] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "ASR" SID "14294" Ports [3, 1] Position [445, 260, 490, 320] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Addressable Shift Register" SourceType "Xilinx Addressable Shift Register Block" infoedit "Delay of configurable length. Any element in the delay line can be addressed and driven onto the" " output port.

Hardware notes: This block is implemented using SRL16s. If Virtex-4 or Spartan-3 device is " "used, multiple SRLC16s are cascaded together." infer_latency off depth "length(coef2)" initVector "[0]" en on dbl_ovrd off use_behavioral_HDL off Optimization "Resource" xl_use_area off xl_area "[1 0 0 2 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,401" block_type "addrsr" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,60,3,1,white,blue,0,f8ea6153,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 60 60 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 60 60 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[36.66 3" "6.66 42.66 36.66 42.66 42.66 42.66 36.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[30.66 30.66 36.66 " "36.66 30.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[24.66 24.66 30.66 30.66 24.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[18.66 18.66 24.66 18.66 24.66 24.66 18.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'addr');\ncolor('black');port_label('input',3," "'en');\ncolor('black');port_label('output',1,'q');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Delay" SID "14295" Ports [1, 1] Position [705, 441, 730, 469] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "25,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 " "17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33" " 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('blac" "k');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "14296" Position [210, 280, 300, 300] ZOrder -9 ShowName off GotoTag "ltsCorr_dAddr" TagVisibility "scoped" } Block { BlockType From Name "From1" SID "14297" Position [210, 340, 300, 360] ZOrder -9 ShowName off GotoTag "ltsCorr_cAddr" TagVisibility "scoped" } Block { BlockType From Name "From2" SID "14298" Position [210, 380, 300, 400] ZOrder -9 ShowName off GotoTag "ltsCorr_ld" TagVisibility "scoped" } Block { BlockType Reference Name "Gateway Out1" SID "14299" Ports [1, 1] Position [745, 615, 780, 625] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "14300" Ports [1, 1] Position [745, 630, 780, 640] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "14301" Ports [1, 1] Position [745, 645, 780, 655] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Ld" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "14302" Ports [1, 1] Position [745, 660, 780, 670] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "14303" Ports [1, 1] Position [745, 675, 780, 685] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "14304" Ports [1, 1] Position [745, 570, 780, 580] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X In" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "14305" Ports [1, 1] Position [745, 585, 780, 595] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "14306" Ports [1, 1] Position [745, 600, 780, 610] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X Vin" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType SubSystem Name "MAC" SID "14307" Ports [4, 2] Position [575, 279, 660, 376] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "MAC" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "a" SID "14308" Position [35, 143, 65, 157] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "coeff" SID "14309" Position [35, 108, 65, 122] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "ld" SID "14310" Position [35, 178, 65, 192] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "rst" SID "14311" Position [35, 233, 65, 247] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub" SID "14312" Ports [3, 1] Position [340, 113, 385, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition or Subtraction" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Signed (2's comp)" n_bits "long_cor_acc_n_bits" bin_pt "0" quantization "Truncate" overflow "Flag as error" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[2 0 0 4 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,344" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,3,1,white,blue,0,02f64c57,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('input',3,'su" "b');\ncolor('black');port_label('output',1,'\\bf{a \\pm b}','texmode','on');\nfprintf('','COMMENT: end icon text" "');\n" } Block { BlockType Reference Name "Gateway Out1" SID "14313" Ports [1, 1] Position [475, 450, 510, 460] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out2" SID "14314" Ports [1, 1] Position [475, 465, 510, 475] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out3" SID "14315" Ports [1, 1] Position [475, 480, 510, 490] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out6" SID "14316" Ports [1, 1] Position [475, 405, 510, 415] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out7" SID "14317" Ports [1, 1] Position [475, 420, 510, 430] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out8" SID "14318" Ports [1, 1] Position [475, 435, 510, 445] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "14319" Ports [2, 1] Position [345, 30, 385, 70] BlockMirror on NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,40,2,1,white,blue,0,140cc11c,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'" "q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "14320" Ports [2, 1] Position [465, 110, 495, 210] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,100,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 100 100 0 ],[0.77 0." "82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 100 100 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[54.44 " "54.44 58.44 54.44 58.44 58.44 58.44 54.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[50.44 50.44 54.44 54" ".44 50.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[46.44 46.44 50.44 50.44 46.44 ],[1 1 1 ])" ";\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[42.44 42.44 46.44 42.44 46.44 46.44 42.44 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\nco" "lor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc2" SID "14321" Ports [1, 1] Position [265, 143, 290, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc3" SID "14322" Ports [1, 1] Position [135, 178, 160, 192] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "yn" SID "14323" Position [545, 153, 575, 167] IconDisplay "Port number" } Block { BlockType Outport Name "accrm" SID "14324" Position [520, 288, 550, 302] Port "2" IconDisplay "Port number" } Line { SrcBlock "rst" SrcPort 1 Points [90, 0] Branch { Points [0, 215] DstBlock "Gateway Out1" DstPort 1 } Branch { Points [255, 0; 0, -180] DstBlock "Register1" DstPort 2 } } Line { SrcBlock "Gateway Out3" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out2" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out1" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out6" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out7" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out8" SrcPort 1 Points [50, 0] } Line { SrcBlock "a" SrcPort 1 Points [140, 0] Branch { Points [0, 275] DstBlock "Gateway Out7" DstPort 1 } Branch { DstBlock "bc2" DstPort 1 } } Line { SrcBlock "AddSub" SrcPort 1 Points [0, 0; 5, 0] Branch { Points [0, 305] DstBlock "Gateway Out8" DstPort 1 } Branch { Points [40, 0] Branch { Points [0, 160] DstBlock "accrm" DstPort 1 } Branch { Points [0, -95] DstBlock "Register1" DstPort 1 } Branch { DstBlock "Register2" DstPort 1 } } } Line { SrcBlock "Register2" SrcPort 1 Points [15, 0] Branch { Points [0, 50; 110, 0; 0, 385; -260, 0; 0, -110] DstBlock "Gateway Out3" DstPort 1 } Branch { DstBlock "yn" DstPort 1 } } Line { SrcBlock "Register1" SrcPort 1 Points [-15, 0] DstBlock "AddSub" DstPort 1 } Line { SrcBlock "ld" SrcPort 1 Points [45, 0] Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } Branch { DstBlock "bc3" DstPort 1 } } Line { SrcBlock "bc3" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "bc2" SrcPort 1 DstBlock "AddSub" DstPort 3 } Line { SrcBlock "coeff" SrcPort 1 Points [95, 0; 0, 20; 50, 0] Branch { Points [0, 275] DstBlock "Gateway Out6" DstPort 1 } Branch { DstBlock "AddSub" DstPort 2 } } } } Block { BlockType Reference Name "ROM" SID "14325" Ports [1, 1] Position [440, 328, 490, 372] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/ROM" SourceType "Xilinx Single Port Read-Only Memory Block" depth "length(coef2)" initVector "coef2" distributed_mem "Distributed memory" rst off init_reg "0" en off latency "1" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "longCorr_coef_nbits" bin_pt "longCorr_coef_bp" preci_type "Single" exp_width "8" frac_width "24" dbl_ovrd off optimize "Area" use_rpm off xl_use_area off xl_area "[1 1 0 1 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,308" block_type "sprom" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,44,1,1,white,blue,0,bbc23d60,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 44 44 0 ]);\npatch([11.65 20.32 26.32 32.32 38.32 26.32 17.65 11.65 ],[28.66" " 28.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([17.65 26.32 20.32 11.65 17.65 ],[22.66 22.66 28." "66 28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([11.65 20.32 26.32 17.65 11.65 ],[16.66 16.66 22.66 22.66 16.66 ]" ",[1 1 1 ]);\npatch([17.65 38.32 32.32 26.32 20.32 11.65 17.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'addr');\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end" " icon text');\n" } Block { BlockType Outport Name "x_dly" SID "14326" Position [790, 178, 820, 192] IconDisplay "Port number" } Block { BlockType Outport Name "x_dly_vout" SID "14327" Position [790, 223, 820, 237] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "y" SID "14328" Position [790, 293, 820, 307] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "y_vout" SID "14329" Position [785, 448, 815, 462] Port "4" IconDisplay "Port number" } Line { Name "ROM Addr" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 Points [150, 0] } Line { Name "Corr Out" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 Points [150, 0] } Line { Name "Corr Ld" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 Points [150, 0] } Line { Name "ROM Out" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 Points [150, 0] } Line { Name "ASR Out" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 Points [150, 0] } Line { Name "X In" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 Points [150, 0] } Line { Name "ASR Addr" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 Points [150, 0] } Line { Name "X Vin" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 Points [150, 0] } Line { SrcBlock "Delay" SrcPort 1 DstBlock "y_vout" DstPort 1 } Line { SrcBlock "vin" SrcPort 1 Points [25, 0] Branch { Points [0, -80] DstBlock "x_dly_vout" DstPort 1 } Branch { Points [0, 100] Branch { Points [230, 0] DstBlock "MAC" DstPort 4 } Branch { Points [0, 195] DstBlock "Gateway Out8" DstPort 1 } } Branch { DstBlock "ASR" DstPort 3 } } Line { SrcBlock "x" SrcPort 1 Points [100, 0] Branch { Points [0, 305] DstBlock "Gateway Out6" DstPort 1 } Branch { DstBlock "ASR" DstPort 1 } } Line { SrcBlock "From" SrcPort 1 Points [90, 0] Branch { Points [0, 300] DstBlock "Gateway Out7" DstPort 1 } Branch { DstBlock "ASR" DstPort 2 } } Line { SrcBlock "From1" SrcPort 1 Points [5, 0] Branch { Points [0, 330] DstBlock "Gateway Out5" DstPort 1 } Branch { DstBlock "ROM" DstPort 1 } } Line { SrcBlock "ASR" SrcPort 1 Points [35, 0] Branch { Points [0, 330] DstBlock "Gateway Out1" DstPort 1 } Branch { Points [0, -105] DstBlock "x_dly" DstPort 1 } Branch { DstBlock "MAC" DstPort 1 } } Line { SrcBlock "MAC" SrcPort 1 Points [0, -5; 15, 0] Branch { Points [0, 365] DstBlock "Gateway Out4" DstPort 1 } Branch { DstBlock "y" DstPort 1 } } Line { SrcBlock "ROM" SrcPort 1 Points [5, 0] Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } Branch { Points [0, -35] DstBlock "MAC" DstPort 2 } } Line { SrcBlock "From2" SrcPort 1 Points [145, 0] Branch { Points [0, 260] DstBlock "Gateway Out3" DstPort 1 } Branch { Points [90, 0] Branch { Points [0, 65] DstBlock "Delay" DstPort 1 } Branch { Points [0, -50] Branch { Points [0, -90; 160, 0] } Branch { DstBlock "MAC" DstPort 3 } } } } } } Block { BlockType Reference Name "Gateway Out1" SID "14330" Ports [1, 1] Position [1195, 75, 1230, 85] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out10" SID "14331" Ports [1, 1] Position [1195, 120, 1230, 130] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out11" SID "14332" Ports [1, 1] Position [1195, 135, 1230, 145] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out12" SID "14333" Ports [1, 1] Position [1195, 150, 1230, 160] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out13" SID "14334" Ports [1, 1] Position [1195, 165, 1230, 175] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out14" SID "14335" Ports [1, 1] Position [1225, 180, 1260, 190] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out2" SID "14336" Ports [1, 1] Position [740, 720, 775, 730] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out3" SID "14337" Ports [1, 1] Position [740, 690, 775, 700] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out4" SID "14338" Ports [1, 1] Position [740, 705, 775, 715] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out5" SID "14339" Ports [1, 1] Position [740, 735, 775, 745] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out6" SID "14340" Ports [1, 1] Position [1195, 45, 1230, 55] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out7" SID "14341" Ports [1, 1] Position [1195, 60, 1230, 70] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out8" SID "14342" Ports [1, 1] Position [1195, 90, 1230, 100] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out9" SID "14343" Ports [1, 1] Position [1195, 105, 1230, 115] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Outport Name "y" SID "14344" Position [1290, 568, 1320, 582] IconDisplay "Port number" } Block { BlockType Outport Name "y_vout" SID "14345" Position [1290, 523, 1320, 537] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "x_dly" SID "14346" Position [1260, 213, 1290, 227] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "x_dly_vout" SID "14347" Position [1260, 253, 1290, 267] Port "4" IconDisplay "Port number" } Line { SrcBlock "x" SrcPort 1 Points [210, 0] Branch { DstBlock "C1" DstPort 1 } Branch { Points [0, 475] DstBlock "Gateway Out3" DstPort 1 } Branch { Points [0, -170] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "AddSub12" SrcPort 1 DstBlock "AddSub13" DstPort 2 } Line { SrcBlock "AddSub5" SrcPort 1 Points [0, 35] DstBlock "AddSub13" DstPort 1 } Line { SrcBlock "Gateway Out4" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out3" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out5" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out2" SrcPort 1 Points [50, 0] } Line { Points [780, 755; 50, 0] } Line { SrcBlock "x_valid" SrcPort 1 Points [200, 0] Branch { Points [0, -20] DstBlock "C1" DstPort 2 } Branch { Points [0, 450] DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "C1" SrcPort 1 DstBlock "C2" DstPort 1 } Line { SrcBlock "C1" SrcPort 2 DstBlock "C2" DstPort 2 } Line { SrcBlock "C2" SrcPort 1 DstBlock "C3" DstPort 1 } Line { SrcBlock "C2" SrcPort 2 DstBlock "C3" DstPort 2 } Line { SrcBlock "C2" SrcPort 3 Points [20, 0] Branch { DstBlock "AddSub5" DstPort 2 } Branch { Points [0, -180] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "C1" SrcPort 3 Points [15, 0] Branch { Points [0, 55] Branch { Points [0, 5; 95, 0] DstBlock "AddSub5" DstPort 1 } Branch { Points [0, 410] DstBlock "Gateway Out2" DstPort 1 } } Branch { Points [0, -195] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "C3" SrcPort 1 DstBlock "C4" DstPort 1 } Line { SrcBlock "C3" SrcPort 2 DstBlock "C4" DstPort 2 } Line { SrcBlock "C3" SrcPort 3 Points [20, 0] Branch { Points [0, 65; 80, 0] DstBlock "AddSub12" DstPort 1 } Branch { Points [0, -165] DstBlock "Gateway Out8" DstPort 1 } } Line { SrcBlock "C4" SrcPort 1 DstBlock "C5" DstPort 1 } Line { SrcBlock "C4" SrcPort 2 DstBlock "C5" DstPort 2 } Line { SrcBlock "C4" SrcPort 3 Points [15, 0] Branch { DstBlock "AddSub12" DstPort 2 } Branch { Points [0, -150] DstBlock "Gateway Out9" DstPort 1 } } Line { SrcBlock "C5" SrcPort 1 DstBlock "C6" DstPort 1 } Line { SrcBlock "C5" SrcPort 2 DstBlock "C6" DstPort 2 } Line { SrcBlock "C6" SrcPort 1 DstBlock "C7" DstPort 1 } Line { SrcBlock "C6" SrcPort 2 DstBlock "C7" DstPort 2 } Line { SrcBlock "C7" SrcPort 1 DstBlock "C8" DstPort 1 } Line { SrcBlock "C7" SrcPort 2 DstBlock "C8" DstPort 2 } Line { SrcBlock "C6" SrcPort 3 Points [15, 0] Branch { DstBlock "AddSub6" DstPort 2 } Branch { Points [0, -120] DstBlock "Gateway Out11" DstPort 1 } } Line { SrcBlock "C5" SrcPort 3 Points [10, 0] Branch { Points [0, 70; 85, 0] DstBlock "AddSub6" DstPort 1 } Branch { Points [0, -135] DstBlock "Gateway Out10" DstPort 1 } } Line { SrcBlock "C8" SrcPort 3 Points [10, 0] Branch { DstBlock "AddSub7" DstPort 2 } Branch { Points [0, -90] DstBlock "Gateway Out13" DstPort 1 } } Line { SrcBlock "C7" SrcPort 3 Points [20, 0] Branch { Points [0, 65; 75, 0] DstBlock "AddSub7" DstPort 1 } Branch { Points [0, -105] DstBlock "Gateway Out12" DstPort 1 } } Line { SrcBlock "AddSub6" SrcPort 1 DstBlock "AddSub1" DstPort 1 } Line { SrcBlock "AddSub7" SrcPort 1 Points [0, 35] DstBlock "AddSub1" DstPort 2 } Line { SrcBlock "AddSub13" SrcPort 1 Points [0, 85] DstBlock "AddSub4" DstPort 2 } Line { SrcBlock "AddSub1" SrcPort 1 Points [0, 60] DstBlock "AddSub4" DstPort 1 } Line { SrcBlock "AddSub4" SrcPort 1 Points [45, 0] Branch { Points [0, 75; -400, 0; 0, 90] DstBlock "Gateway Out5" DstPort 1 } Branch { Points [155, 0] Branch { DstBlock "y" DstPort 1 } Branch { Points [0, -390] DstBlock "Gateway Out14" DstPort 1 } } } Line { SrcBlock "C8" SrcPort 4 Points [40, 0; 0, 250] DstBlock "y_vout" DstPort 1 } Line { SrcBlock "Gateway Out7" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out6" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out8" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out1" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out9" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out10" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out11" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out12" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out13" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out14" SrcPort 1 Points [20, 0] } Line { SrcBlock "C8" SrcPort 1 DstBlock "x_dly" DstPort 1 } Line { SrcBlock "C8" SrcPort 2 Points [110, 0] DstBlock "x_dly_vout" DstPort 1 } } } Block { BlockType SubSystem Name "C8" SID "14348" Ports [2, 4] Position [725, 368, 810, 437] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskPromptString "Coefficients/correlator|Coefficients|Input sample period" MaskStyleString "edit,edit,edit" MaskVariables "N=@1;h=@2;Ts_In=@3;" MaskTunableValueString "on,on,on" MaskCallbackString "||" MaskEnableString "on,on,on" MaskVisibilityString "on,on,on" MaskToolTipString "on,on,on" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "4|longCorr_coef_q(33:64)|4" System { Name "C8" Location [480, 85, 2304, 1455] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "156" Block { BlockType Inport Name "x" SID "14349" Position [35, 213, 65, 227] IconDisplay "Port number" } Block { BlockType Inport Name "x_valid" SID "14350" Position [35, 253, 65, 267] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub1" SID "14351" Ports [2, 1] Position [915, 455, 955, 495] BlockRotation 270 BlockMirror on NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "1" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[3 6 0 5 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,40,2,1,white,blue,0,e85d8a90,down,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bf{a + b}','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\ne" "wline\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub12" SID "14352" Ports [2, 1] Position [684, 360, 731, 400] BlockRotation 270 BlockMirror on NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "1" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[3 5 0 4 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "47,40,2,1,white,blue,0,e85d8a90,down,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 47 47 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 47 47 0 0 ],[0 0 40 40 0 ]);\npatch([11.875 19.1 24.1 29.1 34.1 24.1 16.875 11.875 ],[25.55 2" "5.55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([16.875 24.1 19.1 11.875 16.875 ],[20.55 20.55 25.5" "5 25.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([11.875 19.1 24.1 16.875 11.875 ],[15.55 15.55 20.55 20.55 15.55 ]" ",[1 1 1 ]);\npatch([16.875 34.1 29.1 24.1 19.1 11.875 16.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('b" "lack');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output'" ",1,'\\bf{a + b}','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(" "' \\newline\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub13" SID "14353" Ports [2, 1] Position [680, 455, 720, 495] BlockRotation 270 BlockMirror on NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "1" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[3 6 0 5 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,40,2,1,white,blue,0,e85d8a90,down,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bf{a + b}','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\ne" "wline\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub4" SID "14354" Ports [2, 1] Position [960, 549, 1000, 596] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "1" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[4 7 0 6 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,47,2,1,white,blue,0,e85d8a90,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 47 47 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 47 47 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[28.55 28." "55 33.55 28.55 33.55 33.55 33.55 28.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[23.55 23.55 28.55 2" "8.55 23.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[18.55 18.55 23.55 23.55 18.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[13.55 13.55 18.55 13.55 18.55 18.55 13.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bf{a + b}','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\ne" "wline\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub5" SID "14355" Ports [2, 1] Position [475, 360, 515, 400] BlockRotation 270 BlockMirror on NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "1" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[3 6 0 5 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,40,2,1,white,blue,0,e85d8a90,down,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bf{a + b}','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\ne" "wline\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub6" SID "14356" Ports [2, 1] Position [899, 360, 946, 400] BlockRotation 270 BlockMirror on NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "1" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[3 5 0 4 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "47,40,2,1,white,blue,0,e85d8a90,down,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 47 47 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 47 47 0 0 ],[0 0 40 40 0 ]);\npatch([11.875 19.1 24.1 29.1 34.1 24.1 16.875 11.875 ],[25.55 2" "5.55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([16.875 24.1 19.1 11.875 16.875 ],[20.55 20.55 25.5" "5 25.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([11.875 19.1 24.1 16.875 11.875 ],[15.55 15.55 20.55 20.55 15.55 ]" ",[1 1 1 ]);\npatch([16.875 34.1 29.1 24.1 19.1 11.875 16.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('b" "lack');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output'" ",1,'\\bf{a + b}','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(" "' \\newline\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub7" SID "14357" Ports [2, 1] Position [1109, 360, 1156, 400] BlockRotation 270 BlockMirror on NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "1" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[3 5 0 4 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "47,40,2,1,white,blue,0,e85d8a90,down,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 47 47 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 47 47 0 0 ],[0 0 40 40 0 ]);\npatch([11.875 19.1 24.1 29.1 34.1 24.1 16.875 11.875 ],[25.55 2" "5.55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([16.875 24.1 19.1 11.875 16.875 ],[20.55 20.55 25.5" "5 25.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([11.875 19.1 24.1 16.875 11.875 ],[15.55 15.55 20.55 20.55 15.55 ]" ",[1 1 1 ]);\npatch([16.875 34.1 29.1 24.1 19.1 11.875 16.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('b" "lack');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output'" ",1,'\\bf{a + b}','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(" "' \\newline\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "C1" SID "14358" Ports [4, 4] Position [300, 207, 370, 293] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskPromptString "Coefficients (all)|Sub-correlator Ind|Coef/correlator" MaskStyleString "edit,edit,edit" MaskVariables "h=@1;c_ind=@2;N=@3;" MaskTunableValueString "on,on,on" MaskCallbackString "||" MaskEnableString "on,on,on" MaskVisibilityString "on,on,on" MaskToolTipString "on,on,on" MaskInitialization "coef2 = h((c_ind*N+1) : (c_ind + 1)*N);" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "h|0|N" System { Name "C1" Location [480, 85, 2304, 1471] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "122" Block { BlockType Inport Name "x" SID "14359" Position [265, 263, 295, 277] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "vin" SID "14360" Position [270, 303, 300, 317] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "14361" Position [270, 458, 300, 472] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "14362" Position [270, 503, 300, 517] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "ASR" SID "14363" Ports [3, 1] Position [445, 260, 490, 320] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Addressable Shift Register" SourceType "Xilinx Addressable Shift Register Block" infoedit "Delay of configurable length. Any element in the delay line can be addressed and driven onto the" " output port.

Hardware notes: This block is implemented using SRL16s. If Virtex-4 or Spartan-3 device is " "used, multiple SRLC16s are cascaded together." infer_latency off depth "length(coef2)" initVector "[0]" en on dbl_ovrd off use_behavioral_HDL off Optimization "Resource" xl_use_area off xl_area "[1 0 0 2 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,401" block_type "addrsr" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,60,3,1,white,blue,0,f8ea6153,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 60 60 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 60 60 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[36.66 3" "6.66 42.66 36.66 42.66 42.66 42.66 36.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[30.66 30.66 36.66 " "36.66 30.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[24.66 24.66 30.66 30.66 24.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[18.66 18.66 24.66 18.66 24.66 24.66 18.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'addr');\ncolor('black');port_label('input',3," "'en');\ncolor('black');port_label('output',1,'q');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Delay" SID "14364" Ports [1, 1] Position [705, 441, 730, 469] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "25,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 " "17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33" " 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('blac" "k');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "14365" Position [210, 280, 300, 300] ZOrder -9 ShowName off GotoTag "ltsCorr_dAddr" TagVisibility "scoped" } Block { BlockType From Name "From1" SID "14366" Position [210, 340, 300, 360] ZOrder -9 ShowName off GotoTag "ltsCorr_cAddr" TagVisibility "scoped" } Block { BlockType From Name "From2" SID "14367" Position [210, 380, 300, 400] ZOrder -9 ShowName off GotoTag "ltsCorr_ld" TagVisibility "scoped" } Block { BlockType Reference Name "Gateway Out1" SID "14368" Ports [1, 1] Position [745, 615, 780, 625] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "14369" Ports [1, 1] Position [745, 630, 780, 640] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "14370" Ports [1, 1] Position [745, 645, 780, 655] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Ld" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "14371" Ports [1, 1] Position [745, 660, 780, 670] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "14372" Ports [1, 1] Position [745, 675, 780, 685] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "14373" Ports [1, 1] Position [745, 570, 780, 580] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X In" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "14374" Ports [1, 1] Position [745, 585, 780, 595] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "14375" Ports [1, 1] Position [745, 600, 780, 610] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X Vin" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType SubSystem Name "MAC" SID "14376" Ports [4, 2] Position [575, 279, 660, 376] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "MAC" Location [88, 301, 2330, 1301] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "a" SID "14377" Position [35, 143, 65, 157] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "coeff" SID "14378" Position [35, 108, 65, 122] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "ld" SID "14379" Position [35, 178, 65, 192] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "rst" SID "14380" Position [35, 233, 65, 247] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub" SID "14381" Ports [3, 1] Position [340, 113, 385, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition or Subtraction" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Signed (2's comp)" n_bits "long_cor_acc_n_bits" bin_pt "0" quantization "Truncate" overflow "Flag as error" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[2 0 0 4 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,344" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,3,1,white,blue,0,02f64c57,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('input',3,'su" "b');\ncolor('black');port_label('output',1,'\\bf{a \\pm b}','texmode','on');\nfprintf('','COMMENT: end icon text" "');\n" } Block { BlockType Reference Name "Gateway Out1" SID "14382" Ports [1, 1] Position [475, 450, 510, 460] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out2" SID "14383" Ports [1, 1] Position [475, 465, 510, 475] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out3" SID "14384" Ports [1, 1] Position [475, 480, 510, 490] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out6" SID "14385" Ports [1, 1] Position [475, 405, 510, 415] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out7" SID "14386" Ports [1, 1] Position [475, 420, 510, 430] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out8" SID "14387" Ports [1, 1] Position [475, 435, 510, 445] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "14388" Ports [2, 1] Position [345, 30, 385, 70] BlockMirror on NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,40,2,1,white,blue,0,140cc11c,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'" "q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "14389" Ports [2, 1] Position [465, 110, 495, 210] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,100,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 100 100 0 ],[0.77 0." "82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 100 100 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[54.44 " "54.44 58.44 54.44 58.44 58.44 58.44 54.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[50.44 50.44 54.44 54" ".44 50.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[46.44 46.44 50.44 50.44 46.44 ],[1 1 1 ])" ";\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[42.44 42.44 46.44 42.44 46.44 46.44 42.44 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\nco" "lor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc2" SID "14390" Ports [1, 1] Position [265, 143, 290, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc3" SID "14391" Ports [1, 1] Position [135, 178, 160, 192] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "yn" SID "14392" Position [545, 153, 575, 167] IconDisplay "Port number" } Block { BlockType Outport Name "accrm" SID "14393" Position [520, 288, 550, 302] Port "2" IconDisplay "Port number" } Line { SrcBlock "rst" SrcPort 1 Points [90, 0] Branch { Points [0, 215] DstBlock "Gateway Out1" DstPort 1 } Branch { Points [255, 0; 0, -180] DstBlock "Register1" DstPort 2 } } Line { SrcBlock "Gateway Out3" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out2" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out1" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out6" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out7" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out8" SrcPort 1 Points [50, 0] } Line { SrcBlock "a" SrcPort 1 Points [140, 0] Branch { Points [0, 275] DstBlock "Gateway Out7" DstPort 1 } Branch { DstBlock "bc2" DstPort 1 } } Line { SrcBlock "AddSub" SrcPort 1 Points [0, 0; 5, 0] Branch { Points [0, 305] DstBlock "Gateway Out8" DstPort 1 } Branch { Points [40, 0] Branch { Points [0, 160] DstBlock "accrm" DstPort 1 } Branch { Points [0, -95] DstBlock "Register1" DstPort 1 } Branch { DstBlock "Register2" DstPort 1 } } } Line { SrcBlock "Register2" SrcPort 1 Points [15, 0] Branch { Points [0, 50; 110, 0; 0, 385; -260, 0; 0, -110] DstBlock "Gateway Out3" DstPort 1 } Branch { DstBlock "yn" DstPort 1 } } Line { SrcBlock "Register1" SrcPort 1 Points [-15, 0] DstBlock "AddSub" DstPort 1 } Line { SrcBlock "ld" SrcPort 1 Points [45, 0] Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } Branch { DstBlock "bc3" DstPort 1 } } Line { SrcBlock "bc3" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "bc2" SrcPort 1 DstBlock "AddSub" DstPort 3 } Line { SrcBlock "coeff" SrcPort 1 Points [95, 0; 0, 20; 50, 0] Branch { Points [0, 275] DstBlock "Gateway Out6" DstPort 1 } Branch { DstBlock "AddSub" DstPort 2 } } } } Block { BlockType Reference Name "ROM" SID "14394" Ports [1, 1] Position [440, 328, 490, 372] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/ROM" SourceType "Xilinx Single Port Read-Only Memory Block" depth "length(coef2)" initVector "coef2" distributed_mem "Distributed memory" rst off init_reg "0" en off latency "1" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "longCorr_coef_nbits" bin_pt "longCorr_coef_bp" preci_type "Single" exp_width "8" frac_width "24" dbl_ovrd off optimize "Area" use_rpm off xl_use_area off xl_area "[1 1 0 1 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,308" block_type "sprom" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,44,1,1,white,blue,0,bbc23d60,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 44 44 0 ]);\npatch([11.65 20.32 26.32 32.32 38.32 26.32 17.65 11.65 ],[28.66" " 28.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([17.65 26.32 20.32 11.65 17.65 ],[22.66 22.66 28." "66 28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([11.65 20.32 26.32 17.65 11.65 ],[16.66 16.66 22.66 22.66 16.66 ]" ",[1 1 1 ]);\npatch([17.65 38.32 32.32 26.32 20.32 11.65 17.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'addr');\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end" " icon text');\n" } Block { BlockType Outport Name "x_dly" SID "14395" Position [790, 178, 820, 192] IconDisplay "Port number" } Block { BlockType Outport Name "x_dly_vout" SID "14396" Position [790, 223, 820, 237] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "y" SID "14397" Position [790, 293, 820, 307] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "y_vout" SID "14398" Position [785, 448, 815, 462] Port "4" IconDisplay "Port number" } Line { Name "ROM Addr" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 Points [150, 0] } Line { Name "Corr Out" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 Points [150, 0] } Line { Name "Corr Ld" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 Points [150, 0] } Line { Name "ROM Out" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 Points [150, 0] } Line { Name "ASR Out" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 Points [150, 0] } Line { Name "X In" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 Points [150, 0] } Line { Name "ASR Addr" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 Points [150, 0] } Line { Name "X Vin" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 Points [150, 0] } Line { SrcBlock "Delay" SrcPort 1 DstBlock "y_vout" DstPort 1 } Line { SrcBlock "vin" SrcPort 1 Points [25, 0] Branch { Points [0, -80] DstBlock "x_dly_vout" DstPort 1 } Branch { Points [0, 100] Branch { Points [230, 0] DstBlock "MAC" DstPort 4 } Branch { Points [0, 195] DstBlock "Gateway Out8" DstPort 1 } } Branch { DstBlock "ASR" DstPort 3 } } Line { SrcBlock "x" SrcPort 1 Points [100, 0] Branch { Points [0, 305] DstBlock "Gateway Out6" DstPort 1 } Branch { DstBlock "ASR" DstPort 1 } } Line { SrcBlock "From" SrcPort 1 Points [90, 0] Branch { Points [0, 300] DstBlock "Gateway Out7" DstPort 1 } Branch { DstBlock "ASR" DstPort 2 } } Line { SrcBlock "From1" SrcPort 1 Points [5, 0] Branch { Points [0, 330] DstBlock "Gateway Out5" DstPort 1 } Branch { DstBlock "ROM" DstPort 1 } } Line { SrcBlock "ASR" SrcPort 1 Points [35, 0] Branch { Points [0, 330] DstBlock "Gateway Out1" DstPort 1 } Branch { Points [0, -105] DstBlock "x_dly" DstPort 1 } Branch { DstBlock "MAC" DstPort 1 } } Line { SrcBlock "MAC" SrcPort 1 Points [0, -5; 15, 0] Branch { Points [0, 365] DstBlock "Gateway Out4" DstPort 1 } Branch { DstBlock "y" DstPort 1 } } Line { SrcBlock "ROM" SrcPort 1 Points [5, 0] Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } Branch { Points [0, -35] DstBlock "MAC" DstPort 2 } } Line { SrcBlock "From2" SrcPort 1 Points [145, 0] Branch { Points [0, 260] DstBlock "Gateway Out3" DstPort 1 } Branch { Points [90, 0] Branch { Points [0, 65] DstBlock "Delay" DstPort 1 } Branch { Points [0, -50] Branch { Points [0, -90; 160, 0] } Branch { DstBlock "MAC" DstPort 3 } } } } } } Block { BlockType SubSystem Name "C2" SID "14399" Ports [4, 4] Position [410, 207, 480, 293] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskPromptString "Coefficients (all)|Sub-correlator Ind|Coef/correlator" MaskStyleString "edit,edit,edit" MaskVariables "h=@1;c_ind=@2;N=@3;" MaskTunableValueString "on,on,on" MaskCallbackString "||" MaskEnableString "on,on,on" MaskVisibilityString "on,on,on" MaskToolTipString "on,on,on" MaskInitialization "coef2 = h((c_ind*N+1) : (c_ind + 1)*N);" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "h|1|N" System { Name "C2" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "122" Block { BlockType Inport Name "x" SID "14400" Position [265, 263, 295, 277] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "vin" SID "14401" Position [270, 303, 300, 317] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "14402" Position [270, 458, 300, 472] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "14403" Position [270, 503, 300, 517] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "ASR" SID "14404" Ports [3, 1] Position [445, 260, 490, 320] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Addressable Shift Register" SourceType "Xilinx Addressable Shift Register Block" infoedit "Delay of configurable length. Any element in the delay line can be addressed and driven onto the" " output port.

Hardware notes: This block is implemented using SRL16s. If Virtex-4 or Spartan-3 device is " "used, multiple SRLC16s are cascaded together." infer_latency off depth "length(coef2)" initVector "[0]" en on dbl_ovrd off use_behavioral_HDL off Optimization "Resource" xl_use_area off xl_area "[1 0 0 2 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,401" block_type "addrsr" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,60,3,1,white,blue,0,f8ea6153,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 60 60 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 60 60 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[36.66 3" "6.66 42.66 36.66 42.66 42.66 42.66 36.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[30.66 30.66 36.66 " "36.66 30.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[24.66 24.66 30.66 30.66 24.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[18.66 18.66 24.66 18.66 24.66 24.66 18.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'addr');\ncolor('black');port_label('input',3," "'en');\ncolor('black');port_label('output',1,'q');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Delay" SID "14405" Ports [1, 1] Position [705, 441, 730, 469] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "25,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 " "17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33" " 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('blac" "k');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "14406" Position [210, 280, 300, 300] ZOrder -9 ShowName off GotoTag "ltsCorr_dAddr" TagVisibility "scoped" } Block { BlockType From Name "From1" SID "14407" Position [210, 340, 300, 360] ZOrder -9 ShowName off GotoTag "ltsCorr_cAddr" TagVisibility "scoped" } Block { BlockType From Name "From2" SID "14408" Position [210, 380, 300, 400] ZOrder -9 ShowName off GotoTag "ltsCorr_ld" TagVisibility "scoped" } Block { BlockType Reference Name "Gateway Out1" SID "14409" Ports [1, 1] Position [745, 615, 780, 625] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "14410" Ports [1, 1] Position [745, 630, 780, 640] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "14411" Ports [1, 1] Position [745, 645, 780, 655] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Ld" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "14412" Ports [1, 1] Position [745, 660, 780, 670] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "14413" Ports [1, 1] Position [745, 675, 780, 685] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "14414" Ports [1, 1] Position [745, 570, 780, 580] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X In" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "14415" Ports [1, 1] Position [745, 585, 780, 595] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "14416" Ports [1, 1] Position [745, 600, 780, 610] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X Vin" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType SubSystem Name "MAC" SID "14417" Ports [4, 2] Position [575, 279, 660, 376] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "MAC" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "a" SID "14418" Position [35, 143, 65, 157] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "coeff" SID "14419" Position [35, 108, 65, 122] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "ld" SID "14420" Position [35, 178, 65, 192] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "rst" SID "14421" Position [35, 233, 65, 247] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub" SID "14422" Ports [3, 1] Position [340, 113, 385, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition or Subtraction" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Signed (2's comp)" n_bits "long_cor_acc_n_bits" bin_pt "0" quantization "Truncate" overflow "Flag as error" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[2 0 0 4 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,344" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,3,1,white,blue,0,02f64c57,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('input',3,'su" "b');\ncolor('black');port_label('output',1,'\\bf{a \\pm b}','texmode','on');\nfprintf('','COMMENT: end icon text" "');\n" } Block { BlockType Reference Name "Gateway Out1" SID "14423" Ports [1, 1] Position [475, 450, 510, 460] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out2" SID "14424" Ports [1, 1] Position [475, 465, 510, 475] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out3" SID "14425" Ports [1, 1] Position [475, 480, 510, 490] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out6" SID "14426" Ports [1, 1] Position [475, 405, 510, 415] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out7" SID "14427" Ports [1, 1] Position [475, 420, 510, 430] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out8" SID "14428" Ports [1, 1] Position [475, 435, 510, 445] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "14429" Ports [2, 1] Position [345, 30, 385, 70] BlockMirror on NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,40,2,1,white,blue,0,140cc11c,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'" "q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "14430" Ports [2, 1] Position [465, 110, 495, 210] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,100,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 100 100 0 ],[0.77 0." "82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 100 100 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[54.44 " "54.44 58.44 54.44 58.44 58.44 58.44 54.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[50.44 50.44 54.44 54" ".44 50.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[46.44 46.44 50.44 50.44 46.44 ],[1 1 1 ])" ";\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[42.44 42.44 46.44 42.44 46.44 46.44 42.44 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\nco" "lor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc2" SID "14431" Ports [1, 1] Position [265, 143, 290, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc3" SID "14432" Ports [1, 1] Position [135, 178, 160, 192] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "yn" SID "14433" Position [545, 153, 575, 167] IconDisplay "Port number" } Block { BlockType Outport Name "accrm" SID "14434" Position [520, 288, 550, 302] Port "2" IconDisplay "Port number" } Line { SrcBlock "coeff" SrcPort 1 Points [95, 0; 0, 20; 50, 0] Branch { DstBlock "AddSub" DstPort 2 } Branch { Points [0, 275] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "bc2" SrcPort 1 DstBlock "AddSub" DstPort 3 } Line { SrcBlock "bc3" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "ld" SrcPort 1 Points [45, 0] Branch { DstBlock "bc3" DstPort 1 } Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "Register1" SrcPort 1 Points [-15, 0] DstBlock "AddSub" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 Points [15, 0] Branch { DstBlock "yn" DstPort 1 } Branch { Points [0, 50; 110, 0; 0, 385; -260, 0; 0, -110] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "AddSub" SrcPort 1 Points [0, 0; 5, 0] Branch { Points [40, 0] Branch { DstBlock "Register2" DstPort 1 } Branch { Points [0, -95] DstBlock "Register1" DstPort 1 } Branch { Points [0, 160] DstBlock "accrm" DstPort 1 } } Branch { Points [0, 305] DstBlock "Gateway Out8" DstPort 1 } } Line { SrcBlock "a" SrcPort 1 Points [140, 0] Branch { DstBlock "bc2" DstPort 1 } Branch { Points [0, 275] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "Gateway Out8" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out7" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out6" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out1" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out2" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out3" SrcPort 1 Points [50, 0] } Line { SrcBlock "rst" SrcPort 1 Points [90, 0] Branch { Points [255, 0; 0, -180] DstBlock "Register1" DstPort 2 } Branch { Points [0, 215] DstBlock "Gateway Out1" DstPort 1 } } } } Block { BlockType Reference Name "ROM" SID "14435" Ports [1, 1] Position [440, 328, 490, 372] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/ROM" SourceType "Xilinx Single Port Read-Only Memory Block" depth "length(coef2)" initVector "coef2" distributed_mem "Distributed memory" rst off init_reg "0" en off latency "1" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "longCorr_coef_nbits" bin_pt "longCorr_coef_bp" preci_type "Single" exp_width "8" frac_width "24" dbl_ovrd off optimize "Area" use_rpm off xl_use_area off xl_area "[1 1 0 1 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,308" block_type "sprom" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,44,1,1,white,blue,0,bbc23d60,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 44 44 0 ]);\npatch([11.65 20.32 26.32 32.32 38.32 26.32 17.65 11.65 ],[28.66" " 28.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([17.65 26.32 20.32 11.65 17.65 ],[22.66 22.66 28." "66 28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([11.65 20.32 26.32 17.65 11.65 ],[16.66 16.66 22.66 22.66 16.66 ]" ",[1 1 1 ]);\npatch([17.65 38.32 32.32 26.32 20.32 11.65 17.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'addr');\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end" " icon text');\n" } Block { BlockType Outport Name "x_dly" SID "14436" Position [790, 178, 820, 192] IconDisplay "Port number" } Block { BlockType Outport Name "x_dly_vout" SID "14437" Position [790, 223, 820, 237] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "y" SID "14438" Position [790, 293, 820, 307] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "y_vout" SID "14439" Position [785, 448, 815, 462] Port "4" IconDisplay "Port number" } Line { SrcBlock "From2" SrcPort 1 Points [145, 0] Branch { Points [90, 0] Branch { Points [0, -50] Branch { DstBlock "MAC" DstPort 3 } Branch { Points [0, -90; 160, 0] } } Branch { Points [0, 65] DstBlock "Delay" DstPort 1 } } Branch { Points [0, 260] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "ROM" SrcPort 1 Points [5, 0] Branch { Points [0, -35] DstBlock "MAC" DstPort 2 } Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "MAC" SrcPort 1 Points [0, -5; 15, 0] Branch { DstBlock "y" DstPort 1 } Branch { Points [0, 365] DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "ASR" SrcPort 1 Points [35, 0] Branch { DstBlock "MAC" DstPort 1 } Branch { Points [0, -105] DstBlock "x_dly" DstPort 1 } Branch { Points [0, 330] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "From1" SrcPort 1 Points [5, 0] Branch { DstBlock "ROM" DstPort 1 } Branch { Points [0, 330] DstBlock "Gateway Out5" DstPort 1 } } Line { SrcBlock "From" SrcPort 1 Points [90, 0] Branch { DstBlock "ASR" DstPort 2 } Branch { Points [0, 300] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "x" SrcPort 1 Points [100, 0] Branch { DstBlock "ASR" DstPort 1 } Branch { Points [0, 305] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "vin" SrcPort 1 Points [25, 0] Branch { DstBlock "ASR" DstPort 3 } Branch { Points [0, 100] Branch { Points [0, 195] DstBlock "Gateway Out8" DstPort 1 } Branch { Points [230, 0] DstBlock "MAC" DstPort 4 } } Branch { Points [0, -80] DstBlock "x_dly_vout" DstPort 1 } } Line { SrcBlock "Delay" SrcPort 1 DstBlock "y_vout" DstPort 1 } Line { Name "X Vin" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 Points [150, 0] } Line { Name "ASR Addr" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 Points [150, 0] } Line { Name "X In" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 Points [150, 0] } Line { Name "ASR Out" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 Points [150, 0] } Line { Name "ROM Out" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 Points [150, 0] } Line { Name "Corr Ld" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 Points [150, 0] } Line { Name "Corr Out" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 Points [150, 0] } Line { Name "ROM Addr" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 Points [150, 0] } } } Block { BlockType SubSystem Name "C3" SID "14440" Ports [4, 4] Position [520, 207, 590, 293] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskPromptString "Coefficients (all)|Sub-correlator Ind|Coef/correlator" MaskStyleString "edit,edit,edit" MaskVariables "h=@1;c_ind=@2;N=@3;" MaskTunableValueString "on,on,on" MaskCallbackString "||" MaskEnableString "on,on,on" MaskVisibilityString "on,on,on" MaskToolTipString "on,on,on" MaskInitialization "coef2 = h((c_ind*N+1) : (c_ind + 1)*N);" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "h|2|N" System { Name "C3" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "122" Block { BlockType Inport Name "x" SID "14441" Position [265, 263, 295, 277] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "vin" SID "14442" Position [270, 303, 300, 317] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "14443" Position [270, 458, 300, 472] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "14444" Position [270, 503, 300, 517] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "ASR" SID "14445" Ports [3, 1] Position [445, 260, 490, 320] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Addressable Shift Register" SourceType "Xilinx Addressable Shift Register Block" infoedit "Delay of configurable length. Any element in the delay line can be addressed and driven onto the" " output port.

Hardware notes: This block is implemented using SRL16s. If Virtex-4 or Spartan-3 device is " "used, multiple SRLC16s are cascaded together." infer_latency off depth "length(coef2)" initVector "[0]" en on dbl_ovrd off use_behavioral_HDL off Optimization "Resource" xl_use_area off xl_area "[1 0 0 2 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,401" block_type "addrsr" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,60,3,1,white,blue,0,f8ea6153,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 60 60 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 60 60 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[36.66 3" "6.66 42.66 36.66 42.66 42.66 42.66 36.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[30.66 30.66 36.66 " "36.66 30.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[24.66 24.66 30.66 30.66 24.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[18.66 18.66 24.66 18.66 24.66 24.66 18.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'addr');\ncolor('black');port_label('input',3," "'en');\ncolor('black');port_label('output',1,'q');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Delay" SID "14446" Ports [1, 1] Position [705, 441, 730, 469] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "25,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 " "17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33" " 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('blac" "k');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "14447" Position [210, 280, 300, 300] ZOrder -9 ShowName off GotoTag "ltsCorr_dAddr" TagVisibility "scoped" } Block { BlockType From Name "From1" SID "14448" Position [210, 340, 300, 360] ZOrder -9 ShowName off GotoTag "ltsCorr_cAddr" TagVisibility "scoped" } Block { BlockType From Name "From2" SID "14449" Position [210, 380, 300, 400] ZOrder -9 ShowName off GotoTag "ltsCorr_ld" TagVisibility "scoped" } Block { BlockType Reference Name "Gateway Out1" SID "14450" Ports [1, 1] Position [745, 615, 780, 625] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "14451" Ports [1, 1] Position [745, 630, 780, 640] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "14452" Ports [1, 1] Position [745, 645, 780, 655] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Ld" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "14453" Ports [1, 1] Position [745, 660, 780, 670] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "14454" Ports [1, 1] Position [745, 675, 780, 685] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "14455" Ports [1, 1] Position [745, 570, 780, 580] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X In" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "14456" Ports [1, 1] Position [745, 585, 780, 595] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "14457" Ports [1, 1] Position [745, 600, 780, 610] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X Vin" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType SubSystem Name "MAC" SID "14458" Ports [4, 2] Position [575, 279, 660, 376] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "MAC" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "a" SID "14459" Position [35, 143, 65, 157] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "coeff" SID "14460" Position [35, 108, 65, 122] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "ld" SID "14461" Position [35, 178, 65, 192] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "rst" SID "14462" Position [35, 233, 65, 247] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub" SID "14463" Ports [3, 1] Position [340, 113, 385, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition or Subtraction" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Signed (2's comp)" n_bits "long_cor_acc_n_bits" bin_pt "0" quantization "Truncate" overflow "Flag as error" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[2 0 0 4 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,344" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,3,1,white,blue,0,02f64c57,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('input',3,'su" "b');\ncolor('black');port_label('output',1,'\\bf{a \\pm b}','texmode','on');\nfprintf('','COMMENT: end icon text" "');\n" } Block { BlockType Reference Name "Gateway Out1" SID "14464" Ports [1, 1] Position [475, 450, 510, 460] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out2" SID "14465" Ports [1, 1] Position [475, 465, 510, 475] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out3" SID "14466" Ports [1, 1] Position [475, 480, 510, 490] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out6" SID "14467" Ports [1, 1] Position [475, 405, 510, 415] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out7" SID "14468" Ports [1, 1] Position [475, 420, 510, 430] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out8" SID "14469" Ports [1, 1] Position [475, 435, 510, 445] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "14470" Ports [2, 1] Position [345, 30, 385, 70] BlockMirror on NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,40,2,1,white,blue,0,140cc11c,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'" "q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "14471" Ports [2, 1] Position [465, 110, 495, 210] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,100,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 100 100 0 ],[0.77 0." "82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 100 100 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[54.44 " "54.44 58.44 54.44 58.44 58.44 58.44 54.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[50.44 50.44 54.44 54" ".44 50.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[46.44 46.44 50.44 50.44 46.44 ],[1 1 1 ])" ";\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[42.44 42.44 46.44 42.44 46.44 46.44 42.44 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\nco" "lor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc2" SID "14472" Ports [1, 1] Position [265, 143, 290, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc3" SID "14473" Ports [1, 1] Position [135, 178, 160, 192] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "yn" SID "14474" Position [545, 153, 575, 167] IconDisplay "Port number" } Block { BlockType Outport Name "accrm" SID "14475" Position [520, 288, 550, 302] Port "2" IconDisplay "Port number" } Line { SrcBlock "rst" SrcPort 1 Points [90, 0] Branch { Points [0, 215] DstBlock "Gateway Out1" DstPort 1 } Branch { Points [255, 0; 0, -180] DstBlock "Register1" DstPort 2 } } Line { SrcBlock "Gateway Out3" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out2" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out1" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out6" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out7" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out8" SrcPort 1 Points [50, 0] } Line { SrcBlock "a" SrcPort 1 Points [140, 0] Branch { Points [0, 275] DstBlock "Gateway Out7" DstPort 1 } Branch { DstBlock "bc2" DstPort 1 } } Line { SrcBlock "AddSub" SrcPort 1 Points [0, 0; 5, 0] Branch { Points [0, 305] DstBlock "Gateway Out8" DstPort 1 } Branch { Points [40, 0] Branch { Points [0, 160] DstBlock "accrm" DstPort 1 } Branch { Points [0, -95] DstBlock "Register1" DstPort 1 } Branch { DstBlock "Register2" DstPort 1 } } } Line { SrcBlock "Register2" SrcPort 1 Points [15, 0] Branch { Points [0, 50; 110, 0; 0, 385; -260, 0; 0, -110] DstBlock "Gateway Out3" DstPort 1 } Branch { DstBlock "yn" DstPort 1 } } Line { SrcBlock "Register1" SrcPort 1 Points [-15, 0] DstBlock "AddSub" DstPort 1 } Line { SrcBlock "ld" SrcPort 1 Points [45, 0] Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } Branch { DstBlock "bc3" DstPort 1 } } Line { SrcBlock "bc3" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "bc2" SrcPort 1 DstBlock "AddSub" DstPort 3 } Line { SrcBlock "coeff" SrcPort 1 Points [95, 0; 0, 20; 50, 0] Branch { Points [0, 275] DstBlock "Gateway Out6" DstPort 1 } Branch { DstBlock "AddSub" DstPort 2 } } } } Block { BlockType Reference Name "ROM" SID "14476" Ports [1, 1] Position [440, 328, 490, 372] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/ROM" SourceType "Xilinx Single Port Read-Only Memory Block" depth "length(coef2)" initVector "coef2" distributed_mem "Distributed memory" rst off init_reg "0" en off latency "1" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "longCorr_coef_nbits" bin_pt "longCorr_coef_bp" preci_type "Single" exp_width "8" frac_width "24" dbl_ovrd off optimize "Area" use_rpm off xl_use_area off xl_area "[1 1 0 1 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,308" block_type "sprom" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,44,1,1,white,blue,0,bbc23d60,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 44 44 0 ]);\npatch([11.65 20.32 26.32 32.32 38.32 26.32 17.65 11.65 ],[28.66" " 28.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([17.65 26.32 20.32 11.65 17.65 ],[22.66 22.66 28." "66 28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([11.65 20.32 26.32 17.65 11.65 ],[16.66 16.66 22.66 22.66 16.66 ]" ",[1 1 1 ]);\npatch([17.65 38.32 32.32 26.32 20.32 11.65 17.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'addr');\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end" " icon text');\n" } Block { BlockType Outport Name "x_dly" SID "14477" Position [790, 178, 820, 192] IconDisplay "Port number" } Block { BlockType Outport Name "x_dly_vout" SID "14478" Position [790, 223, 820, 237] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "y" SID "14479" Position [790, 293, 820, 307] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "y_vout" SID "14480" Position [785, 448, 815, 462] Port "4" IconDisplay "Port number" } Line { Name "ROM Addr" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 Points [150, 0] } Line { Name "Corr Out" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 Points [150, 0] } Line { Name "Corr Ld" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 Points [150, 0] } Line { Name "ROM Out" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 Points [150, 0] } Line { Name "ASR Out" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 Points [150, 0] } Line { Name "X In" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 Points [150, 0] } Line { Name "ASR Addr" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 Points [150, 0] } Line { Name "X Vin" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 Points [150, 0] } Line { SrcBlock "Delay" SrcPort 1 DstBlock "y_vout" DstPort 1 } Line { SrcBlock "vin" SrcPort 1 Points [25, 0] Branch { Points [0, -80] DstBlock "x_dly_vout" DstPort 1 } Branch { Points [0, 100] Branch { Points [230, 0] DstBlock "MAC" DstPort 4 } Branch { Points [0, 195] DstBlock "Gateway Out8" DstPort 1 } } Branch { DstBlock "ASR" DstPort 3 } } Line { SrcBlock "x" SrcPort 1 Points [100, 0] Branch { Points [0, 305] DstBlock "Gateway Out6" DstPort 1 } Branch { DstBlock "ASR" DstPort 1 } } Line { SrcBlock "From" SrcPort 1 Points [90, 0] Branch { Points [0, 300] DstBlock "Gateway Out7" DstPort 1 } Branch { DstBlock "ASR" DstPort 2 } } Line { SrcBlock "From1" SrcPort 1 Points [5, 0] Branch { Points [0, 330] DstBlock "Gateway Out5" DstPort 1 } Branch { DstBlock "ROM" DstPort 1 } } Line { SrcBlock "ASR" SrcPort 1 Points [35, 0] Branch { Points [0, 330] DstBlock "Gateway Out1" DstPort 1 } Branch { Points [0, -105] DstBlock "x_dly" DstPort 1 } Branch { DstBlock "MAC" DstPort 1 } } Line { SrcBlock "MAC" SrcPort 1 Points [0, -5; 15, 0] Branch { Points [0, 365] DstBlock "Gateway Out4" DstPort 1 } Branch { DstBlock "y" DstPort 1 } } Line { SrcBlock "ROM" SrcPort 1 Points [5, 0] Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } Branch { Points [0, -35] DstBlock "MAC" DstPort 2 } } Line { SrcBlock "From2" SrcPort 1 Points [145, 0] Branch { Points [0, 260] DstBlock "Gateway Out3" DstPort 1 } Branch { Points [90, 0] Branch { Points [0, 65] DstBlock "Delay" DstPort 1 } Branch { Points [0, -50] Branch { Points [0, -90; 160, 0] } Branch { DstBlock "MAC" DstPort 3 } } } } } } Block { BlockType SubSystem Name "C4" SID "14481" Ports [4, 4] Position [630, 207, 700, 293] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskPromptString "Coefficients (all)|Sub-correlator Ind|Coef/correlator" MaskStyleString "edit,edit,edit" MaskVariables "h=@1;c_ind=@2;N=@3;" MaskTunableValueString "on,on,on" MaskCallbackString "||" MaskEnableString "on,on,on" MaskVisibilityString "on,on,on" MaskToolTipString "on,on,on" MaskInitialization "coef2 = h((c_ind*N+1) : (c_ind + 1)*N);" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "h|3|N" System { Name "C4" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "122" Block { BlockType Inport Name "x" SID "14482" Position [265, 263, 295, 277] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "vin" SID "14483" Position [270, 303, 300, 317] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "14484" Position [270, 458, 300, 472] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "14485" Position [270, 503, 300, 517] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "ASR" SID "14486" Ports [3, 1] Position [445, 260, 490, 320] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Addressable Shift Register" SourceType "Xilinx Addressable Shift Register Block" infoedit "Delay of configurable length. Any element in the delay line can be addressed and driven onto the" " output port.

Hardware notes: This block is implemented using SRL16s. If Virtex-4 or Spartan-3 device is " "used, multiple SRLC16s are cascaded together." infer_latency off depth "length(coef2)" initVector "[0]" en on dbl_ovrd off use_behavioral_HDL off Optimization "Resource" xl_use_area off xl_area "[1 0 0 2 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,401" block_type "addrsr" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,60,3,1,white,blue,0,f8ea6153,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 60 60 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 60 60 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[36.66 3" "6.66 42.66 36.66 42.66 42.66 42.66 36.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[30.66 30.66 36.66 " "36.66 30.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[24.66 24.66 30.66 30.66 24.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[18.66 18.66 24.66 18.66 24.66 24.66 18.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'addr');\ncolor('black');port_label('input',3," "'en');\ncolor('black');port_label('output',1,'q');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Delay" SID "14487" Ports [1, 1] Position [705, 441, 730, 469] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "25,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 " "17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33" " 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('blac" "k');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "14488" Position [210, 280, 300, 300] ZOrder -9 ShowName off GotoTag "ltsCorr_dAddr" TagVisibility "scoped" } Block { BlockType From Name "From1" SID "14489" Position [210, 340, 300, 360] ZOrder -9 ShowName off GotoTag "ltsCorr_cAddr" TagVisibility "scoped" } Block { BlockType From Name "From2" SID "14490" Position [210, 380, 300, 400] ZOrder -9 ShowName off GotoTag "ltsCorr_ld" TagVisibility "scoped" } Block { BlockType Reference Name "Gateway Out1" SID "14491" Ports [1, 1] Position [745, 615, 780, 625] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "14492" Ports [1, 1] Position [745, 630, 780, 640] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "14493" Ports [1, 1] Position [745, 645, 780, 655] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Ld" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "14494" Ports [1, 1] Position [745, 660, 780, 670] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "14495" Ports [1, 1] Position [745, 675, 780, 685] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "14496" Ports [1, 1] Position [745, 570, 780, 580] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X In" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "14497" Ports [1, 1] Position [745, 585, 780, 595] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "14498" Ports [1, 1] Position [745, 600, 780, 610] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X Vin" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType SubSystem Name "MAC" SID "14499" Ports [4, 2] Position [575, 279, 660, 376] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "MAC" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "a" SID "14500" Position [35, 143, 65, 157] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "coeff" SID "14501" Position [35, 108, 65, 122] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "ld" SID "14502" Position [35, 178, 65, 192] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "rst" SID "14503" Position [35, 233, 65, 247] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub" SID "14504" Ports [3, 1] Position [340, 113, 385, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition or Subtraction" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Signed (2's comp)" n_bits "long_cor_acc_n_bits" bin_pt "0" quantization "Truncate" overflow "Flag as error" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[2 0 0 4 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,344" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,3,1,white,blue,0,02f64c57,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('input',3,'su" "b');\ncolor('black');port_label('output',1,'\\bf{a \\pm b}','texmode','on');\nfprintf('','COMMENT: end icon text" "');\n" } Block { BlockType Reference Name "Gateway Out1" SID "14505" Ports [1, 1] Position [475, 450, 510, 460] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out2" SID "14506" Ports [1, 1] Position [475, 465, 510, 475] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out3" SID "14507" Ports [1, 1] Position [475, 480, 510, 490] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out6" SID "14508" Ports [1, 1] Position [475, 405, 510, 415] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out7" SID "14509" Ports [1, 1] Position [475, 420, 510, 430] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out8" SID "14510" Ports [1, 1] Position [475, 435, 510, 445] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "14511" Ports [2, 1] Position [345, 30, 385, 70] BlockMirror on NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,40,2,1,white,blue,0,140cc11c,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'" "q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "14512" Ports [2, 1] Position [465, 110, 495, 210] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,100,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 100 100 0 ],[0.77 0." "82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 100 100 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[54.44 " "54.44 58.44 54.44 58.44 58.44 58.44 54.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[50.44 50.44 54.44 54" ".44 50.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[46.44 46.44 50.44 50.44 46.44 ],[1 1 1 ])" ";\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[42.44 42.44 46.44 42.44 46.44 46.44 42.44 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\nco" "lor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc2" SID "14513" Ports [1, 1] Position [265, 143, 290, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc3" SID "14514" Ports [1, 1] Position [135, 178, 160, 192] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "yn" SID "14515" Position [545, 153, 575, 167] IconDisplay "Port number" } Block { BlockType Outport Name "accrm" SID "14516" Position [520, 288, 550, 302] Port "2" IconDisplay "Port number" } Line { SrcBlock "coeff" SrcPort 1 Points [95, 0; 0, 20; 50, 0] Branch { DstBlock "AddSub" DstPort 2 } Branch { Points [0, 275] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "bc2" SrcPort 1 DstBlock "AddSub" DstPort 3 } Line { SrcBlock "bc3" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "ld" SrcPort 1 Points [45, 0] Branch { DstBlock "bc3" DstPort 1 } Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "Register1" SrcPort 1 Points [-15, 0] DstBlock "AddSub" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 Points [15, 0] Branch { DstBlock "yn" DstPort 1 } Branch { Points [0, 50; 110, 0; 0, 385; -260, 0; 0, -110] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "AddSub" SrcPort 1 Points [0, 0; 5, 0] Branch { Points [40, 0] Branch { DstBlock "Register2" DstPort 1 } Branch { Points [0, -95] DstBlock "Register1" DstPort 1 } Branch { Points [0, 160] DstBlock "accrm" DstPort 1 } } Branch { Points [0, 305] DstBlock "Gateway Out8" DstPort 1 } } Line { SrcBlock "a" SrcPort 1 Points [140, 0] Branch { DstBlock "bc2" DstPort 1 } Branch { Points [0, 275] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "Gateway Out8" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out7" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out6" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out1" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out2" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out3" SrcPort 1 Points [50, 0] } Line { SrcBlock "rst" SrcPort 1 Points [90, 0] Branch { Points [255, 0; 0, -180] DstBlock "Register1" DstPort 2 } Branch { Points [0, 215] DstBlock "Gateway Out1" DstPort 1 } } } } Block { BlockType Reference Name "ROM" SID "14517" Ports [1, 1] Position [440, 328, 490, 372] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/ROM" SourceType "Xilinx Single Port Read-Only Memory Block" depth "length(coef2)" initVector "coef2" distributed_mem "Distributed memory" rst off init_reg "0" en off latency "1" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "longCorr_coef_nbits" bin_pt "longCorr_coef_bp" preci_type "Single" exp_width "8" frac_width "24" dbl_ovrd off optimize "Area" use_rpm off xl_use_area off xl_area "[1 1 0 1 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,308" block_type "sprom" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,44,1,1,white,blue,0,bbc23d60,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 44 44 0 ]);\npatch([11.65 20.32 26.32 32.32 38.32 26.32 17.65 11.65 ],[28.66" " 28.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([17.65 26.32 20.32 11.65 17.65 ],[22.66 22.66 28." "66 28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([11.65 20.32 26.32 17.65 11.65 ],[16.66 16.66 22.66 22.66 16.66 ]" ",[1 1 1 ]);\npatch([17.65 38.32 32.32 26.32 20.32 11.65 17.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'addr');\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end" " icon text');\n" } Block { BlockType Outport Name "x_dly" SID "14518" Position [790, 178, 820, 192] IconDisplay "Port number" } Block { BlockType Outport Name "x_dly_vout" SID "14519" Position [790, 223, 820, 237] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "y" SID "14520" Position [790, 293, 820, 307] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "y_vout" SID "14521" Position [785, 448, 815, 462] Port "4" IconDisplay "Port number" } Line { SrcBlock "From2" SrcPort 1 Points [145, 0] Branch { Points [90, 0] Branch { Points [0, -50] Branch { DstBlock "MAC" DstPort 3 } Branch { Points [0, -90; 160, 0] } } Branch { Points [0, 65] DstBlock "Delay" DstPort 1 } } Branch { Points [0, 260] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "ROM" SrcPort 1 Points [5, 0] Branch { Points [0, -35] DstBlock "MAC" DstPort 2 } Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "MAC" SrcPort 1 Points [0, -5; 15, 0] Branch { DstBlock "y" DstPort 1 } Branch { Points [0, 365] DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "ASR" SrcPort 1 Points [35, 0] Branch { DstBlock "MAC" DstPort 1 } Branch { Points [0, -105] DstBlock "x_dly" DstPort 1 } Branch { Points [0, 330] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "From1" SrcPort 1 Points [5, 0] Branch { DstBlock "ROM" DstPort 1 } Branch { Points [0, 330] DstBlock "Gateway Out5" DstPort 1 } } Line { SrcBlock "From" SrcPort 1 Points [90, 0] Branch { DstBlock "ASR" DstPort 2 } Branch { Points [0, 300] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "x" SrcPort 1 Points [100, 0] Branch { DstBlock "ASR" DstPort 1 } Branch { Points [0, 305] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "vin" SrcPort 1 Points [25, 0] Branch { DstBlock "ASR" DstPort 3 } Branch { Points [0, 100] Branch { Points [0, 195] DstBlock "Gateway Out8" DstPort 1 } Branch { Points [230, 0] DstBlock "MAC" DstPort 4 } } Branch { Points [0, -80] DstBlock "x_dly_vout" DstPort 1 } } Line { SrcBlock "Delay" SrcPort 1 DstBlock "y_vout" DstPort 1 } Line { Name "X Vin" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 Points [150, 0] } Line { Name "ASR Addr" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 Points [150, 0] } Line { Name "X In" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 Points [150, 0] } Line { Name "ASR Out" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 Points [150, 0] } Line { Name "ROM Out" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 Points [150, 0] } Line { Name "Corr Ld" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 Points [150, 0] } Line { Name "Corr Out" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 Points [150, 0] } Line { Name "ROM Addr" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 Points [150, 0] } } } Block { BlockType SubSystem Name "C5" SID "14522" Ports [4, 4] Position [740, 207, 810, 293] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskPromptString "Coefficients (all)|Sub-correlator Ind|Coef/correlator" MaskStyleString "edit,edit,edit" MaskVariables "h=@1;c_ind=@2;N=@3;" MaskTunableValueString "on,on,on" MaskCallbackString "||" MaskEnableString "on,on,on" MaskVisibilityString "on,on,on" MaskToolTipString "on,on,on" MaskInitialization "coef2 = h((c_ind*N+1) : (c_ind + 1)*N);" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "h|4|N" System { Name "C5" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "122" Block { BlockType Inport Name "x" SID "14523" Position [265, 263, 295, 277] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "vin" SID "14524" Position [270, 303, 300, 317] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "14525" Position [270, 458, 300, 472] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "14526" Position [270, 503, 300, 517] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "ASR" SID "14527" Ports [3, 1] Position [445, 260, 490, 320] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Addressable Shift Register" SourceType "Xilinx Addressable Shift Register Block" infoedit "Delay of configurable length. Any element in the delay line can be addressed and driven onto the" " output port.

Hardware notes: This block is implemented using SRL16s. If Virtex-4 or Spartan-3 device is " "used, multiple SRLC16s are cascaded together." infer_latency off depth "length(coef2)" initVector "[0]" en on dbl_ovrd off use_behavioral_HDL off Optimization "Resource" xl_use_area off xl_area "[1 0 0 2 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,401" block_type "addrsr" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,60,3,1,white,blue,0,f8ea6153,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 60 60 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 60 60 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[36.66 3" "6.66 42.66 36.66 42.66 42.66 42.66 36.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[30.66 30.66 36.66 " "36.66 30.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[24.66 24.66 30.66 30.66 24.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[18.66 18.66 24.66 18.66 24.66 24.66 18.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'addr');\ncolor('black');port_label('input',3," "'en');\ncolor('black');port_label('output',1,'q');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Delay" SID "14528" Ports [1, 1] Position [705, 441, 730, 469] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "25,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 " "17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33" " 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('blac" "k');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "14529" Position [210, 280, 300, 300] ZOrder -9 ShowName off GotoTag "ltsCorr_dAddr" TagVisibility "scoped" } Block { BlockType From Name "From1" SID "14530" Position [210, 340, 300, 360] ZOrder -9 ShowName off GotoTag "ltsCorr_cAddr" TagVisibility "scoped" } Block { BlockType From Name "From2" SID "14531" Position [210, 380, 300, 400] ZOrder -9 ShowName off GotoTag "ltsCorr_ld" TagVisibility "scoped" } Block { BlockType Reference Name "Gateway Out1" SID "14532" Ports [1, 1] Position [745, 615, 780, 625] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "14533" Ports [1, 1] Position [745, 630, 780, 640] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "14534" Ports [1, 1] Position [745, 645, 780, 655] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Ld" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "14535" Ports [1, 1] Position [745, 660, 780, 670] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "14536" Ports [1, 1] Position [745, 675, 780, 685] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "14537" Ports [1, 1] Position [745, 570, 780, 580] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X In" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "14538" Ports [1, 1] Position [745, 585, 780, 595] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "14539" Ports [1, 1] Position [745, 600, 780, 610] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X Vin" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType SubSystem Name "MAC" SID "14540" Ports [4, 2] Position [575, 279, 660, 376] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "MAC" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "a" SID "14541" Position [35, 143, 65, 157] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "coeff" SID "14542" Position [35, 108, 65, 122] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "ld" SID "14543" Position [35, 178, 65, 192] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "rst" SID "14544" Position [35, 233, 65, 247] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub" SID "14545" Ports [3, 1] Position [340, 113, 385, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition or Subtraction" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Signed (2's comp)" n_bits "long_cor_acc_n_bits" bin_pt "0" quantization "Truncate" overflow "Flag as error" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[2 0 0 4 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,344" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,3,1,white,blue,0,02f64c57,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('input',3,'su" "b');\ncolor('black');port_label('output',1,'\\bf{a \\pm b}','texmode','on');\nfprintf('','COMMENT: end icon text" "');\n" } Block { BlockType Reference Name "Gateway Out1" SID "14546" Ports [1, 1] Position [475, 450, 510, 460] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out2" SID "14547" Ports [1, 1] Position [475, 465, 510, 475] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out3" SID "14548" Ports [1, 1] Position [475, 480, 510, 490] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out6" SID "14549" Ports [1, 1] Position [475, 405, 510, 415] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out7" SID "14550" Ports [1, 1] Position [475, 420, 510, 430] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out8" SID "14551" Ports [1, 1] Position [475, 435, 510, 445] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "14552" Ports [2, 1] Position [345, 30, 385, 70] BlockMirror on NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,40,2,1,white,blue,0,140cc11c,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'" "q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "14553" Ports [2, 1] Position [465, 110, 495, 210] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,100,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 100 100 0 ],[0.77 0." "82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 100 100 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[54.44 " "54.44 58.44 54.44 58.44 58.44 58.44 54.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[50.44 50.44 54.44 54" ".44 50.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[46.44 46.44 50.44 50.44 46.44 ],[1 1 1 ])" ";\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[42.44 42.44 46.44 42.44 46.44 46.44 42.44 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\nco" "lor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc2" SID "14554" Ports [1, 1] Position [265, 143, 290, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc3" SID "14555" Ports [1, 1] Position [135, 178, 160, 192] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "yn" SID "14556" Position [545, 153, 575, 167] IconDisplay "Port number" } Block { BlockType Outport Name "accrm" SID "14557" Position [520, 288, 550, 302] Port "2" IconDisplay "Port number" } Line { SrcBlock "rst" SrcPort 1 Points [90, 0] Branch { Points [0, 215] DstBlock "Gateway Out1" DstPort 1 } Branch { Points [255, 0; 0, -180] DstBlock "Register1" DstPort 2 } } Line { SrcBlock "Gateway Out3" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out2" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out1" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out6" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out7" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out8" SrcPort 1 Points [50, 0] } Line { SrcBlock "a" SrcPort 1 Points [140, 0] Branch { Points [0, 275] DstBlock "Gateway Out7" DstPort 1 } Branch { DstBlock "bc2" DstPort 1 } } Line { SrcBlock "AddSub" SrcPort 1 Points [0, 0; 5, 0] Branch { Points [0, 305] DstBlock "Gateway Out8" DstPort 1 } Branch { Points [40, 0] Branch { Points [0, 160] DstBlock "accrm" DstPort 1 } Branch { Points [0, -95] DstBlock "Register1" DstPort 1 } Branch { DstBlock "Register2" DstPort 1 } } } Line { SrcBlock "Register2" SrcPort 1 Points [15, 0] Branch { Points [0, 50; 110, 0; 0, 385; -260, 0; 0, -110] DstBlock "Gateway Out3" DstPort 1 } Branch { DstBlock "yn" DstPort 1 } } Line { SrcBlock "Register1" SrcPort 1 Points [-15, 0] DstBlock "AddSub" DstPort 1 } Line { SrcBlock "ld" SrcPort 1 Points [45, 0] Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } Branch { DstBlock "bc3" DstPort 1 } } Line { SrcBlock "bc3" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "bc2" SrcPort 1 DstBlock "AddSub" DstPort 3 } Line { SrcBlock "coeff" SrcPort 1 Points [95, 0; 0, 20; 50, 0] Branch { Points [0, 275] DstBlock "Gateway Out6" DstPort 1 } Branch { DstBlock "AddSub" DstPort 2 } } } } Block { BlockType Reference Name "ROM" SID "14558" Ports [1, 1] Position [440, 328, 490, 372] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/ROM" SourceType "Xilinx Single Port Read-Only Memory Block" depth "length(coef2)" initVector "coef2" distributed_mem "Distributed memory" rst off init_reg "0" en off latency "1" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "longCorr_coef_nbits" bin_pt "longCorr_coef_bp" preci_type "Single" exp_width "8" frac_width "24" dbl_ovrd off optimize "Area" use_rpm off xl_use_area off xl_area "[1 1 0 1 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,308" block_type "sprom" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,44,1,1,white,blue,0,bbc23d60,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 44 44 0 ]);\npatch([11.65 20.32 26.32 32.32 38.32 26.32 17.65 11.65 ],[28.66" " 28.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([17.65 26.32 20.32 11.65 17.65 ],[22.66 22.66 28." "66 28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([11.65 20.32 26.32 17.65 11.65 ],[16.66 16.66 22.66 22.66 16.66 ]" ",[1 1 1 ]);\npatch([17.65 38.32 32.32 26.32 20.32 11.65 17.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'addr');\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end" " icon text');\n" } Block { BlockType Outport Name "x_dly" SID "14559" Position [790, 178, 820, 192] IconDisplay "Port number" } Block { BlockType Outport Name "x_dly_vout" SID "14560" Position [790, 223, 820, 237] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "y" SID "14561" Position [790, 293, 820, 307] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "y_vout" SID "14562" Position [785, 448, 815, 462] Port "4" IconDisplay "Port number" } Line { Name "ROM Addr" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 Points [150, 0] } Line { Name "Corr Out" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 Points [150, 0] } Line { Name "Corr Ld" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 Points [150, 0] } Line { Name "ROM Out" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 Points [150, 0] } Line { Name "ASR Out" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 Points [150, 0] } Line { Name "X In" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 Points [150, 0] } Line { Name "ASR Addr" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 Points [150, 0] } Line { Name "X Vin" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 Points [150, 0] } Line { SrcBlock "Delay" SrcPort 1 DstBlock "y_vout" DstPort 1 } Line { SrcBlock "vin" SrcPort 1 Points [25, 0] Branch { Points [0, -80] DstBlock "x_dly_vout" DstPort 1 } Branch { Points [0, 100] Branch { Points [230, 0] DstBlock "MAC" DstPort 4 } Branch { Points [0, 195] DstBlock "Gateway Out8" DstPort 1 } } Branch { DstBlock "ASR" DstPort 3 } } Line { SrcBlock "x" SrcPort 1 Points [100, 0] Branch { Points [0, 305] DstBlock "Gateway Out6" DstPort 1 } Branch { DstBlock "ASR" DstPort 1 } } Line { SrcBlock "From" SrcPort 1 Points [90, 0] Branch { Points [0, 300] DstBlock "Gateway Out7" DstPort 1 } Branch { DstBlock "ASR" DstPort 2 } } Line { SrcBlock "From1" SrcPort 1 Points [5, 0] Branch { Points [0, 330] DstBlock "Gateway Out5" DstPort 1 } Branch { DstBlock "ROM" DstPort 1 } } Line { SrcBlock "ASR" SrcPort 1 Points [35, 0] Branch { Points [0, 330] DstBlock "Gateway Out1" DstPort 1 } Branch { Points [0, -105] DstBlock "x_dly" DstPort 1 } Branch { DstBlock "MAC" DstPort 1 } } Line { SrcBlock "MAC" SrcPort 1 Points [0, -5; 15, 0] Branch { Points [0, 365] DstBlock "Gateway Out4" DstPort 1 } Branch { DstBlock "y" DstPort 1 } } Line { SrcBlock "ROM" SrcPort 1 Points [5, 0] Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } Branch { Points [0, -35] DstBlock "MAC" DstPort 2 } } Line { SrcBlock "From2" SrcPort 1 Points [145, 0] Branch { Points [0, 260] DstBlock "Gateway Out3" DstPort 1 } Branch { Points [90, 0] Branch { Points [0, 65] DstBlock "Delay" DstPort 1 } Branch { Points [0, -50] Branch { Points [0, -90; 160, 0] } Branch { DstBlock "MAC" DstPort 3 } } } } } } Block { BlockType SubSystem Name "C6" SID "14563" Ports [4, 4] Position [845, 207, 915, 293] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskPromptString "Coefficients (all)|Sub-correlator Ind|Coef/correlator" MaskStyleString "edit,edit,edit" MaskVariables "h=@1;c_ind=@2;N=@3;" MaskTunableValueString "on,on,on" MaskCallbackString "||" MaskEnableString "on,on,on" MaskVisibilityString "on,on,on" MaskToolTipString "on,on,on" MaskInitialization "coef2 = h((c_ind*N+1) : (c_ind + 1)*N);" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "h|5|N" System { Name "C6" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "122" Block { BlockType Inport Name "x" SID "14564" Position [265, 263, 295, 277] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "vin" SID "14565" Position [270, 303, 300, 317] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "14566" Position [270, 458, 300, 472] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "14567" Position [270, 503, 300, 517] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "ASR" SID "14568" Ports [3, 1] Position [445, 260, 490, 320] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Addressable Shift Register" SourceType "Xilinx Addressable Shift Register Block" infoedit "Delay of configurable length. Any element in the delay line can be addressed and driven onto the" " output port.

Hardware notes: This block is implemented using SRL16s. If Virtex-4 or Spartan-3 device is " "used, multiple SRLC16s are cascaded together." infer_latency off depth "length(coef2)" initVector "[0]" en on dbl_ovrd off use_behavioral_HDL off Optimization "Resource" xl_use_area off xl_area "[1 0 0 2 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,401" block_type "addrsr" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,60,3,1,white,blue,0,f8ea6153,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 60 60 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 60 60 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[36.66 3" "6.66 42.66 36.66 42.66 42.66 42.66 36.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[30.66 30.66 36.66 " "36.66 30.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[24.66 24.66 30.66 30.66 24.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[18.66 18.66 24.66 18.66 24.66 24.66 18.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'addr');\ncolor('black');port_label('input',3," "'en');\ncolor('black');port_label('output',1,'q');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Delay" SID "14569" Ports [1, 1] Position [705, 441, 730, 469] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "25,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 " "17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33" " 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('blac" "k');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "14570" Position [210, 280, 300, 300] ZOrder -9 ShowName off GotoTag "ltsCorr_dAddr" TagVisibility "scoped" } Block { BlockType From Name "From1" SID "14571" Position [210, 340, 300, 360] ZOrder -9 ShowName off GotoTag "ltsCorr_cAddr" TagVisibility "scoped" } Block { BlockType From Name "From2" SID "14572" Position [210, 380, 300, 400] ZOrder -9 ShowName off GotoTag "ltsCorr_ld" TagVisibility "scoped" } Block { BlockType Reference Name "Gateway Out1" SID "14573" Ports [1, 1] Position [745, 615, 780, 625] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "14574" Ports [1, 1] Position [745, 630, 780, 640] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "14575" Ports [1, 1] Position [745, 645, 780, 655] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Ld" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "14576" Ports [1, 1] Position [745, 660, 780, 670] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "14577" Ports [1, 1] Position [745, 675, 780, 685] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "14578" Ports [1, 1] Position [745, 570, 780, 580] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X In" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "14579" Ports [1, 1] Position [745, 585, 780, 595] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "14580" Ports [1, 1] Position [745, 600, 780, 610] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X Vin" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType SubSystem Name "MAC" SID "14581" Ports [4, 2] Position [575, 279, 660, 376] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "MAC" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "a" SID "14582" Position [35, 143, 65, 157] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "coeff" SID "14583" Position [35, 108, 65, 122] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "ld" SID "14584" Position [35, 178, 65, 192] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "rst" SID "14585" Position [35, 233, 65, 247] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub" SID "14586" Ports [3, 1] Position [340, 113, 385, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition or Subtraction" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Signed (2's comp)" n_bits "long_cor_acc_n_bits" bin_pt "0" quantization "Truncate" overflow "Flag as error" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[2 0 0 4 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,344" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,3,1,white,blue,0,02f64c57,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('input',3,'su" "b');\ncolor('black');port_label('output',1,'\\bf{a \\pm b}','texmode','on');\nfprintf('','COMMENT: end icon text" "');\n" } Block { BlockType Reference Name "Gateway Out1" SID "14587" Ports [1, 1] Position [475, 450, 510, 460] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out2" SID "14588" Ports [1, 1] Position [475, 465, 510, 475] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out3" SID "14589" Ports [1, 1] Position [475, 480, 510, 490] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out6" SID "14590" Ports [1, 1] Position [475, 405, 510, 415] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out7" SID "14591" Ports [1, 1] Position [475, 420, 510, 430] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out8" SID "14592" Ports [1, 1] Position [475, 435, 510, 445] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "14593" Ports [2, 1] Position [345, 30, 385, 70] BlockMirror on NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,40,2,1,white,blue,0,140cc11c,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'" "q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "14594" Ports [2, 1] Position [465, 110, 495, 210] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,100,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 100 100 0 ],[0.77 0." "82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 100 100 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[54.44 " "54.44 58.44 54.44 58.44 58.44 58.44 54.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[50.44 50.44 54.44 54" ".44 50.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[46.44 46.44 50.44 50.44 46.44 ],[1 1 1 ])" ";\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[42.44 42.44 46.44 42.44 46.44 46.44 42.44 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\nco" "lor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc2" SID "14595" Ports [1, 1] Position [265, 143, 290, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc3" SID "14596" Ports [1, 1] Position [135, 178, 160, 192] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "yn" SID "14597" Position [545, 153, 575, 167] IconDisplay "Port number" } Block { BlockType Outport Name "accrm" SID "14598" Position [520, 288, 550, 302] Port "2" IconDisplay "Port number" } Line { SrcBlock "coeff" SrcPort 1 Points [95, 0; 0, 20; 50, 0] Branch { DstBlock "AddSub" DstPort 2 } Branch { Points [0, 275] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "bc2" SrcPort 1 DstBlock "AddSub" DstPort 3 } Line { SrcBlock "bc3" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "ld" SrcPort 1 Points [45, 0] Branch { DstBlock "bc3" DstPort 1 } Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "Register1" SrcPort 1 Points [-15, 0] DstBlock "AddSub" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 Points [15, 0] Branch { DstBlock "yn" DstPort 1 } Branch { Points [0, 50; 110, 0; 0, 385; -260, 0; 0, -110] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "AddSub" SrcPort 1 Points [0, 0; 5, 0] Branch { Points [40, 0] Branch { DstBlock "Register2" DstPort 1 } Branch { Points [0, -95] DstBlock "Register1" DstPort 1 } Branch { Points [0, 160] DstBlock "accrm" DstPort 1 } } Branch { Points [0, 305] DstBlock "Gateway Out8" DstPort 1 } } Line { SrcBlock "a" SrcPort 1 Points [140, 0] Branch { DstBlock "bc2" DstPort 1 } Branch { Points [0, 275] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "Gateway Out8" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out7" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out6" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out1" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out2" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out3" SrcPort 1 Points [50, 0] } Line { SrcBlock "rst" SrcPort 1 Points [90, 0] Branch { Points [255, 0; 0, -180] DstBlock "Register1" DstPort 2 } Branch { Points [0, 215] DstBlock "Gateway Out1" DstPort 1 } } } } Block { BlockType Reference Name "ROM" SID "14599" Ports [1, 1] Position [440, 328, 490, 372] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/ROM" SourceType "Xilinx Single Port Read-Only Memory Block" depth "length(coef2)" initVector "coef2" distributed_mem "Distributed memory" rst off init_reg "0" en off latency "1" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "longCorr_coef_nbits" bin_pt "longCorr_coef_bp" preci_type "Single" exp_width "8" frac_width "24" dbl_ovrd off optimize "Area" use_rpm off xl_use_area off xl_area "[1 1 0 1 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,308" block_type "sprom" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,44,1,1,white,blue,0,bbc23d60,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 44 44 0 ]);\npatch([11.65 20.32 26.32 32.32 38.32 26.32 17.65 11.65 ],[28.66" " 28.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([17.65 26.32 20.32 11.65 17.65 ],[22.66 22.66 28." "66 28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([11.65 20.32 26.32 17.65 11.65 ],[16.66 16.66 22.66 22.66 16.66 ]" ",[1 1 1 ]);\npatch([17.65 38.32 32.32 26.32 20.32 11.65 17.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'addr');\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end" " icon text');\n" } Block { BlockType Outport Name "x_dly" SID "14600" Position [790, 178, 820, 192] IconDisplay "Port number" } Block { BlockType Outport Name "x_dly_vout" SID "14601" Position [790, 223, 820, 237] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "y" SID "14602" Position [790, 293, 820, 307] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "y_vout" SID "14603" Position [785, 448, 815, 462] Port "4" IconDisplay "Port number" } Line { SrcBlock "From2" SrcPort 1 Points [145, 0] Branch { Points [90, 0] Branch { Points [0, -50] Branch { DstBlock "MAC" DstPort 3 } Branch { Points [0, -90; 160, 0] } } Branch { Points [0, 65] DstBlock "Delay" DstPort 1 } } Branch { Points [0, 260] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "ROM" SrcPort 1 Points [5, 0] Branch { Points [0, -35] DstBlock "MAC" DstPort 2 } Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "MAC" SrcPort 1 Points [0, -5; 15, 0] Branch { DstBlock "y" DstPort 1 } Branch { Points [0, 365] DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "ASR" SrcPort 1 Points [35, 0] Branch { DstBlock "MAC" DstPort 1 } Branch { Points [0, -105] DstBlock "x_dly" DstPort 1 } Branch { Points [0, 330] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "From1" SrcPort 1 Points [5, 0] Branch { DstBlock "ROM" DstPort 1 } Branch { Points [0, 330] DstBlock "Gateway Out5" DstPort 1 } } Line { SrcBlock "From" SrcPort 1 Points [90, 0] Branch { DstBlock "ASR" DstPort 2 } Branch { Points [0, 300] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "x" SrcPort 1 Points [100, 0] Branch { DstBlock "ASR" DstPort 1 } Branch { Points [0, 305] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "vin" SrcPort 1 Points [25, 0] Branch { DstBlock "ASR" DstPort 3 } Branch { Points [0, 100] Branch { Points [0, 195] DstBlock "Gateway Out8" DstPort 1 } Branch { Points [230, 0] DstBlock "MAC" DstPort 4 } } Branch { Points [0, -80] DstBlock "x_dly_vout" DstPort 1 } } Line { SrcBlock "Delay" SrcPort 1 DstBlock "y_vout" DstPort 1 } Line { Name "X Vin" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 Points [150, 0] } Line { Name "ASR Addr" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 Points [150, 0] } Line { Name "X In" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 Points [150, 0] } Line { Name "ASR Out" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 Points [150, 0] } Line { Name "ROM Out" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 Points [150, 0] } Line { Name "Corr Ld" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 Points [150, 0] } Line { Name "Corr Out" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 Points [150, 0] } Line { Name "ROM Addr" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 Points [150, 0] } } } Block { BlockType SubSystem Name "C7" SID "14604" Ports [4, 4] Position [950, 207, 1020, 293] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskPromptString "Coefficients (all)|Sub-correlator Ind|Coef/correlator" MaskStyleString "edit,edit,edit" MaskVariables "h=@1;c_ind=@2;N=@3;" MaskTunableValueString "on,on,on" MaskCallbackString "||" MaskEnableString "on,on,on" MaskVisibilityString "on,on,on" MaskToolTipString "on,on,on" MaskInitialization "coef2 = h((c_ind*N+1) : (c_ind + 1)*N);" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "h|6|N" System { Name "C7" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "122" Block { BlockType Inport Name "x" SID "14605" Position [265, 263, 295, 277] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "vin" SID "14606" Position [270, 303, 300, 317] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "14607" Position [270, 458, 300, 472] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "14608" Position [270, 503, 300, 517] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "ASR" SID "14609" Ports [3, 1] Position [445, 260, 490, 320] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Addressable Shift Register" SourceType "Xilinx Addressable Shift Register Block" infoedit "Delay of configurable length. Any element in the delay line can be addressed and driven onto the" " output port.

Hardware notes: This block is implemented using SRL16s. If Virtex-4 or Spartan-3 device is " "used, multiple SRLC16s are cascaded together." infer_latency off depth "length(coef2)" initVector "[0]" en on dbl_ovrd off use_behavioral_HDL off Optimization "Resource" xl_use_area off xl_area "[1 0 0 2 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,401" block_type "addrsr" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,60,3,1,white,blue,0,f8ea6153,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 60 60 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 60 60 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[36.66 3" "6.66 42.66 36.66 42.66 42.66 42.66 36.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[30.66 30.66 36.66 " "36.66 30.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[24.66 24.66 30.66 30.66 24.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[18.66 18.66 24.66 18.66 24.66 24.66 18.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'addr');\ncolor('black');port_label('input',3," "'en');\ncolor('black');port_label('output',1,'q');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Delay" SID "14610" Ports [1, 1] Position [705, 441, 730, 469] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "25,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 " "17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33" " 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('blac" "k');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "14611" Position [210, 280, 300, 300] ZOrder -9 ShowName off GotoTag "ltsCorr_dAddr" TagVisibility "scoped" } Block { BlockType From Name "From1" SID "14612" Position [210, 340, 300, 360] ZOrder -9 ShowName off GotoTag "ltsCorr_cAddr" TagVisibility "scoped" } Block { BlockType From Name "From2" SID "14613" Position [210, 380, 300, 400] ZOrder -9 ShowName off GotoTag "ltsCorr_ld" TagVisibility "scoped" } Block { BlockType Reference Name "Gateway Out1" SID "14614" Ports [1, 1] Position [745, 615, 780, 625] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "14615" Ports [1, 1] Position [745, 630, 780, 640] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "14616" Ports [1, 1] Position [745, 645, 780, 655] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Ld" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "14617" Ports [1, 1] Position [745, 660, 780, 670] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "14618" Ports [1, 1] Position [745, 675, 780, 685] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "14619" Ports [1, 1] Position [745, 570, 780, 580] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X In" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "14620" Ports [1, 1] Position [745, 585, 780, 595] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "14621" Ports [1, 1] Position [745, 600, 780, 610] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X Vin" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType SubSystem Name "MAC" SID "14622" Ports [4, 2] Position [575, 279, 660, 376] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "MAC" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "a" SID "14623" Position [35, 143, 65, 157] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "coeff" SID "14624" Position [35, 108, 65, 122] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "ld" SID "14625" Position [35, 178, 65, 192] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "rst" SID "14626" Position [35, 233, 65, 247] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub" SID "14627" Ports [3, 1] Position [340, 113, 385, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition or Subtraction" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Signed (2's comp)" n_bits "long_cor_acc_n_bits" bin_pt "0" quantization "Truncate" overflow "Flag as error" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[2 0 0 4 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,344" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,3,1,white,blue,0,02f64c57,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('input',3,'su" "b');\ncolor('black');port_label('output',1,'\\bf{a \\pm b}','texmode','on');\nfprintf('','COMMENT: end icon text" "');\n" } Block { BlockType Reference Name "Gateway Out1" SID "14628" Ports [1, 1] Position [475, 450, 510, 460] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out2" SID "14629" Ports [1, 1] Position [475, 465, 510, 475] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out3" SID "14630" Ports [1, 1] Position [475, 480, 510, 490] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out6" SID "14631" Ports [1, 1] Position [475, 405, 510, 415] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out7" SID "14632" Ports [1, 1] Position [475, 420, 510, 430] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out8" SID "14633" Ports [1, 1] Position [475, 435, 510, 445] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "14634" Ports [2, 1] Position [345, 30, 385, 70] BlockMirror on NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,40,2,1,white,blue,0,140cc11c,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'" "q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "14635" Ports [2, 1] Position [465, 110, 495, 210] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,100,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 100 100 0 ],[0.77 0." "82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 100 100 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[54.44 " "54.44 58.44 54.44 58.44 58.44 58.44 54.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[50.44 50.44 54.44 54" ".44 50.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[46.44 46.44 50.44 50.44 46.44 ],[1 1 1 ])" ";\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[42.44 42.44 46.44 42.44 46.44 46.44 42.44 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\nco" "lor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc2" SID "14636" Ports [1, 1] Position [265, 143, 290, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc3" SID "14637" Ports [1, 1] Position [135, 178, 160, 192] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "yn" SID "14638" Position [545, 153, 575, 167] IconDisplay "Port number" } Block { BlockType Outport Name "accrm" SID "14639" Position [520, 288, 550, 302] Port "2" IconDisplay "Port number" } Line { SrcBlock "rst" SrcPort 1 Points [90, 0] Branch { Points [0, 215] DstBlock "Gateway Out1" DstPort 1 } Branch { Points [255, 0; 0, -180] DstBlock "Register1" DstPort 2 } } Line { SrcBlock "Gateway Out3" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out2" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out1" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out6" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out7" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out8" SrcPort 1 Points [50, 0] } Line { SrcBlock "a" SrcPort 1 Points [140, 0] Branch { Points [0, 275] DstBlock "Gateway Out7" DstPort 1 } Branch { DstBlock "bc2" DstPort 1 } } Line { SrcBlock "AddSub" SrcPort 1 Points [0, 0; 5, 0] Branch { Points [0, 305] DstBlock "Gateway Out8" DstPort 1 } Branch { Points [40, 0] Branch { Points [0, 160] DstBlock "accrm" DstPort 1 } Branch { Points [0, -95] DstBlock "Register1" DstPort 1 } Branch { DstBlock "Register2" DstPort 1 } } } Line { SrcBlock "Register2" SrcPort 1 Points [15, 0] Branch { Points [0, 50; 110, 0; 0, 385; -260, 0; 0, -110] DstBlock "Gateway Out3" DstPort 1 } Branch { DstBlock "yn" DstPort 1 } } Line { SrcBlock "Register1" SrcPort 1 Points [-15, 0] DstBlock "AddSub" DstPort 1 } Line { SrcBlock "ld" SrcPort 1 Points [45, 0] Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } Branch { DstBlock "bc3" DstPort 1 } } Line { SrcBlock "bc3" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "bc2" SrcPort 1 DstBlock "AddSub" DstPort 3 } Line { SrcBlock "coeff" SrcPort 1 Points [95, 0; 0, 20; 50, 0] Branch { Points [0, 275] DstBlock "Gateway Out6" DstPort 1 } Branch { DstBlock "AddSub" DstPort 2 } } } } Block { BlockType Reference Name "ROM" SID "14640" Ports [1, 1] Position [440, 328, 490, 372] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/ROM" SourceType "Xilinx Single Port Read-Only Memory Block" depth "length(coef2)" initVector "coef2" distributed_mem "Distributed memory" rst off init_reg "0" en off latency "1" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "longCorr_coef_nbits" bin_pt "longCorr_coef_bp" preci_type "Single" exp_width "8" frac_width "24" dbl_ovrd off optimize "Area" use_rpm off xl_use_area off xl_area "[1 1 0 1 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,308" block_type "sprom" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,44,1,1,white,blue,0,bbc23d60,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 44 44 0 ]);\npatch([11.65 20.32 26.32 32.32 38.32 26.32 17.65 11.65 ],[28.66" " 28.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([17.65 26.32 20.32 11.65 17.65 ],[22.66 22.66 28." "66 28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([11.65 20.32 26.32 17.65 11.65 ],[16.66 16.66 22.66 22.66 16.66 ]" ",[1 1 1 ]);\npatch([17.65 38.32 32.32 26.32 20.32 11.65 17.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'addr');\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end" " icon text');\n" } Block { BlockType Outport Name "x_dly" SID "14641" Position [790, 178, 820, 192] IconDisplay "Port number" } Block { BlockType Outport Name "x_dly_vout" SID "14642" Position [790, 223, 820, 237] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "y" SID "14643" Position [790, 293, 820, 307] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "y_vout" SID "14644" Position [785, 448, 815, 462] Port "4" IconDisplay "Port number" } Line { Name "ROM Addr" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 Points [150, 0] } Line { Name "Corr Out" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 Points [150, 0] } Line { Name "Corr Ld" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 Points [150, 0] } Line { Name "ROM Out" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 Points [150, 0] } Line { Name "ASR Out" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 Points [150, 0] } Line { Name "X In" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 Points [150, 0] } Line { Name "ASR Addr" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 Points [150, 0] } Line { Name "X Vin" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 Points [150, 0] } Line { SrcBlock "Delay" SrcPort 1 DstBlock "y_vout" DstPort 1 } Line { SrcBlock "vin" SrcPort 1 Points [25, 0] Branch { Points [0, -80] DstBlock "x_dly_vout" DstPort 1 } Branch { Points [0, 100] Branch { Points [230, 0] DstBlock "MAC" DstPort 4 } Branch { Points [0, 195] DstBlock "Gateway Out8" DstPort 1 } } Branch { DstBlock "ASR" DstPort 3 } } Line { SrcBlock "x" SrcPort 1 Points [100, 0] Branch { Points [0, 305] DstBlock "Gateway Out6" DstPort 1 } Branch { DstBlock "ASR" DstPort 1 } } Line { SrcBlock "From" SrcPort 1 Points [90, 0] Branch { Points [0, 300] DstBlock "Gateway Out7" DstPort 1 } Branch { DstBlock "ASR" DstPort 2 } } Line { SrcBlock "From1" SrcPort 1 Points [5, 0] Branch { Points [0, 330] DstBlock "Gateway Out5" DstPort 1 } Branch { DstBlock "ROM" DstPort 1 } } Line { SrcBlock "ASR" SrcPort 1 Points [35, 0] Branch { Points [0, 330] DstBlock "Gateway Out1" DstPort 1 } Branch { Points [0, -105] DstBlock "x_dly" DstPort 1 } Branch { DstBlock "MAC" DstPort 1 } } Line { SrcBlock "MAC" SrcPort 1 Points [0, -5; 15, 0] Branch { Points [0, 365] DstBlock "Gateway Out4" DstPort 1 } Branch { DstBlock "y" DstPort 1 } } Line { SrcBlock "ROM" SrcPort 1 Points [5, 0] Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } Branch { Points [0, -35] DstBlock "MAC" DstPort 2 } } Line { SrcBlock "From2" SrcPort 1 Points [145, 0] Branch { Points [0, 260] DstBlock "Gateway Out3" DstPort 1 } Branch { Points [90, 0] Branch { Points [0, 65] DstBlock "Delay" DstPort 1 } Branch { Points [0, -50] Branch { Points [0, -90; 160, 0] } Branch { DstBlock "MAC" DstPort 3 } } } } } } Block { BlockType SubSystem Name "C8" SID "14645" Ports [4, 4] Position [1060, 207, 1130, 293] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskPromptString "Coefficients (all)|Sub-correlator Ind|Coef/correlator" MaskStyleString "edit,edit,edit" MaskVariables "h=@1;c_ind=@2;N=@3;" MaskTunableValueString "on,on,on" MaskCallbackString "||" MaskEnableString "on,on,on" MaskVisibilityString "on,on,on" MaskToolTipString "on,on,on" MaskInitialization "coef2 = h((c_ind*N+1) : (c_ind + 1)*N);" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "h|7|N" System { Name "C8" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "122" Block { BlockType Inport Name "x" SID "14646" Position [265, 263, 295, 277] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "vin" SID "14647" Position [270, 303, 300, 317] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "14648" Position [270, 458, 300, 472] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name " " SID "14649" Position [270, 503, 300, 517] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "ASR" SID "14650" Ports [3, 1] Position [445, 260, 490, 320] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Addressable Shift Register" SourceType "Xilinx Addressable Shift Register Block" infoedit "Delay of configurable length. Any element in the delay line can be addressed and driven onto the" " output port.

Hardware notes: This block is implemented using SRL16s. If Virtex-4 or Spartan-3 device is " "used, multiple SRLC16s are cascaded together." infer_latency off depth "length(coef2)" initVector "[0]" en on dbl_ovrd off use_behavioral_HDL off Optimization "Resource" xl_use_area off xl_area "[1 0 0 2 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,401" block_type "addrsr" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,60,3,1,white,blue,0,f8ea6153,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 60 60 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 60 60 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[36.66 3" "6.66 42.66 36.66 42.66 42.66 42.66 36.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[30.66 30.66 36.66 " "36.66 30.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[24.66 24.66 30.66 30.66 24.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[18.66 18.66 24.66 18.66 24.66 24.66 18.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'addr');\ncolor('black');port_label('input',3," "'en');\ncolor('black');port_label('output',1,'q');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Delay" SID "14651" Ports [1, 1] Position [705, 441, 730, 469] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "25,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 " "17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33" " 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('blac" "k');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "14652" Position [210, 280, 300, 300] ZOrder -9 ShowName off GotoTag "ltsCorr_dAddr" TagVisibility "scoped" } Block { BlockType From Name "From1" SID "14653" Position [210, 340, 300, 360] ZOrder -9 ShowName off GotoTag "ltsCorr_cAddr" TagVisibility "scoped" } Block { BlockType From Name "From2" SID "14654" Position [210, 380, 300, 400] ZOrder -9 ShowName off GotoTag "ltsCorr_ld" TagVisibility "scoped" } Block { BlockType Reference Name "Gateway Out1" SID "14655" Ports [1, 1] Position [745, 615, 780, 625] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "14656" Ports [1, 1] Position [745, 630, 780, 640] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "14657" Ports [1, 1] Position [745, 645, 780, 655] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Ld" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "14658" Ports [1, 1] Position [745, 660, 780, 670] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "14659" Ports [1, 1] Position [745, 675, 780, 685] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ROM Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "14660" Ports [1, 1] Position [745, 570, 780, 580] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X In" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "14661" Ports [1, 1] Position [745, 585, 780, 595] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ASR Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "14662" Ports [1, 1] Position [745, 600, 780, 610] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "X Vin" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType SubSystem Name "MAC" SID "14663" Ports [4, 2] Position [575, 279, 660, 376] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "MAC" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "a" SID "14664" Position [35, 143, 65, 157] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "coeff" SID "14665" Position [35, 108, 65, 122] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "ld" SID "14666" Position [35, 178, 65, 192] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "rst" SID "14667" Position [35, 233, 65, 247] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub" SID "14668" Ports [3, 1] Position [340, 113, 385, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition or Subtraction" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Signed (2's comp)" n_bits "long_cor_acc_n_bits" bin_pt "0" quantization "Truncate" overflow "Flag as error" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[2 0 0 4 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,344" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,3,1,white,blue,0,02f64c57,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('input',3,'su" "b');\ncolor('black');port_label('output',1,'\\bf{a \\pm b}','texmode','on');\nfprintf('','COMMENT: end icon text" "');\n" } Block { BlockType Reference Name "Gateway Out1" SID "14669" Ports [1, 1] Position [475, 450, 510, 460] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out2" SID "14670" Ports [1, 1] Position [475, 465, 510, 475] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out3" SID "14671" Ports [1, 1] Position [475, 480, 510, 490] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out6" SID "14672" Ports [1, 1] Position [475, 405, 510, 415] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out7" SID "14673" Ports [1, 1] Position [475, 420, 510, 430] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out8" SID "14674" Ports [1, 1] Position [475, 435, 510, 445] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "14675" Ports [2, 1] Position [345, 30, 385, 70] BlockMirror on NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,40,2,1,white,blue,0,140cc11c,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'" "q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "14676" Ports [2, 1] Position [465, 110, 495, 210] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[2 4 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,100,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 100 100 0 ],[0.77 0." "82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 100 100 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[54.44 " "54.44 58.44 54.44 58.44 58.44 58.44 54.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[50.44 50.44 54.44 54" ".44 50.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[46.44 46.44 50.44 50.44 46.44 ],[1 1 1 ])" ";\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[42.44 42.44 46.44 42.44 46.44 46.44 42.44 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\nco" "lor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc2" SID "14677" Ports [1, 1] Position [265, 143, 290, 157] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "bc3" SID "14678" Ports [1, 1] Position [135, 178, 160, 192] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "yn" SID "14679" Position [545, 153, 575, 167] IconDisplay "Port number" } Block { BlockType Outport Name "accrm" SID "14680" Position [520, 288, 550, 302] Port "2" IconDisplay "Port number" } Line { SrcBlock "coeff" SrcPort 1 Points [95, 0; 0, 20; 50, 0] Branch { DstBlock "AddSub" DstPort 2 } Branch { Points [0, 275] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "bc2" SrcPort 1 DstBlock "AddSub" DstPort 3 } Line { SrcBlock "bc3" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "ld" SrcPort 1 Points [45, 0] Branch { DstBlock "bc3" DstPort 1 } Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "Register1" SrcPort 1 Points [-15, 0] DstBlock "AddSub" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 Points [15, 0] Branch { DstBlock "yn" DstPort 1 } Branch { Points [0, 50; 110, 0; 0, 385; -260, 0; 0, -110] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "AddSub" SrcPort 1 Points [0, 0; 5, 0] Branch { Points [40, 0] Branch { DstBlock "Register2" DstPort 1 } Branch { Points [0, -95] DstBlock "Register1" DstPort 1 } Branch { Points [0, 160] DstBlock "accrm" DstPort 1 } } Branch { Points [0, 305] DstBlock "Gateway Out8" DstPort 1 } } Line { SrcBlock "a" SrcPort 1 Points [140, 0] Branch { DstBlock "bc2" DstPort 1 } Branch { Points [0, 275] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "Gateway Out8" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out7" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out6" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out1" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out2" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out3" SrcPort 1 Points [50, 0] } Line { SrcBlock "rst" SrcPort 1 Points [90, 0] Branch { Points [255, 0; 0, -180] DstBlock "Register1" DstPort 2 } Branch { Points [0, 215] DstBlock "Gateway Out1" DstPort 1 } } } } Block { BlockType Reference Name "ROM" SID "14681" Ports [1, 1] Position [440, 328, 490, 372] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/ROM" SourceType "Xilinx Single Port Read-Only Memory Block" depth "length(coef2)" initVector "coef2" distributed_mem "Distributed memory" rst off init_reg "0" en off latency "1" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "longCorr_coef_nbits" bin_pt "longCorr_coef_bp" preci_type "Single" exp_width "8" frac_width "24" dbl_ovrd off optimize "Area" use_rpm off xl_use_area off xl_area "[1 1 0 1 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,308" block_type "sprom" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,44,1,1,white,blue,0,bbc23d60,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 44 44 0 ]);\npatch([11.65 20.32 26.32 32.32 38.32 26.32 17.65 11.65 ],[28.66" " 28.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([17.65 26.32 20.32 11.65 17.65 ],[22.66 22.66 28." "66 28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([11.65 20.32 26.32 17.65 11.65 ],[16.66 16.66 22.66 22.66 16.66 ]" ",[1 1 1 ]);\npatch([17.65 38.32 32.32 26.32 20.32 11.65 17.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'addr');\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end" " icon text');\n" } Block { BlockType Outport Name "x_dly" SID "14682" Position [790, 178, 820, 192] IconDisplay "Port number" } Block { BlockType Outport Name "x_dly_vout" SID "14683" Position [790, 223, 820, 237] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "y" SID "14684" Position [790, 293, 820, 307] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "y_vout" SID "14685" Position [785, 448, 815, 462] Port "4" IconDisplay "Port number" } Line { SrcBlock "From2" SrcPort 1 Points [145, 0] Branch { Points [90, 0] Branch { Points [0, -50] Branch { DstBlock "MAC" DstPort 3 } Branch { Points [0, -90; 160, 0] } } Branch { Points [0, 65] DstBlock "Delay" DstPort 1 } } Branch { Points [0, 260] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "ROM" SrcPort 1 Points [5, 0] Branch { Points [0, -35] DstBlock "MAC" DstPort 2 } Branch { Points [0, 285] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "MAC" SrcPort 1 Points [0, -5; 15, 0] Branch { DstBlock "y" DstPort 1 } Branch { Points [0, 365] DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "ASR" SrcPort 1 Points [35, 0] Branch { DstBlock "MAC" DstPort 1 } Branch { Points [0, -105] DstBlock "x_dly" DstPort 1 } Branch { Points [0, 330] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "From1" SrcPort 1 Points [5, 0] Branch { DstBlock "ROM" DstPort 1 } Branch { Points [0, 330] DstBlock "Gateway Out5" DstPort 1 } } Line { SrcBlock "From" SrcPort 1 Points [90, 0] Branch { DstBlock "ASR" DstPort 2 } Branch { Points [0, 300] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "x" SrcPort 1 Points [100, 0] Branch { DstBlock "ASR" DstPort 1 } Branch { Points [0, 305] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "vin" SrcPort 1 Points [25, 0] Branch { DstBlock "ASR" DstPort 3 } Branch { Points [0, 100] Branch { Points [0, 195] DstBlock "Gateway Out8" DstPort 1 } Branch { Points [230, 0] DstBlock "MAC" DstPort 4 } } Branch { Points [0, -80] DstBlock "x_dly_vout" DstPort 1 } } Line { SrcBlock "Delay" SrcPort 1 DstBlock "y_vout" DstPort 1 } Line { Name "X Vin" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 Points [150, 0] } Line { Name "ASR Addr" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 Points [150, 0] } Line { Name "X In" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 Points [150, 0] } Line { Name "ASR Out" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 Points [150, 0] } Line { Name "ROM Out" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 Points [150, 0] } Line { Name "Corr Ld" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 Points [150, 0] } Line { Name "Corr Out" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 Points [150, 0] } Line { Name "ROM Addr" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 Points [150, 0] } } } Block { BlockType Reference Name "Gateway Out1" SID "14686" Ports [1, 1] Position [1195, 75, 1230, 85] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out10" SID "14687" Ports [1, 1] Position [1195, 120, 1230, 130] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out11" SID "14688" Ports [1, 1] Position [1195, 135, 1230, 145] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out12" SID "14689" Ports [1, 1] Position [1195, 150, 1230, 160] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out13" SID "14690" Ports [1, 1] Position [1195, 165, 1230, 175] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out14" SID "14691" Ports [1, 1] Position [1225, 180, 1260, 190] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out2" SID "14692" Ports [1, 1] Position [740, 720, 775, 730] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out3" SID "14693" Ports [1, 1] Position [740, 690, 775, 700] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out4" SID "14694" Ports [1, 1] Position [740, 705, 775, 715] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out5" SID "14695" Ports [1, 1] Position [740, 735, 775, 745] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out6" SID "14696" Ports [1, 1] Position [1195, 45, 1230, 55] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out7" SID "14697" Ports [1, 1] Position [1195, 60, 1230, 70] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out8" SID "14698" Ports [1, 1] Position [1195, 90, 1230, 100] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out9" SID "14699" Ports [1, 1] Position [1195, 105, 1230, 115] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Outport Name "y" SID "14700" Position [1290, 568, 1320, 582] IconDisplay "Port number" } Block { BlockType Outport Name "y_vout" SID "14701" Position [1290, 523, 1320, 537] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "x_dly" SID "14702" Position [1260, 213, 1290, 227] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "x_dly_vout" SID "14703" Position [1260, 253, 1290, 267] Port "4" IconDisplay "Port number" } Line { SrcBlock "C8" SrcPort 2 Points [110, 0] DstBlock "x_dly_vout" DstPort 1 } Line { SrcBlock "C8" SrcPort 1 DstBlock "x_dly" DstPort 1 } Line { SrcBlock "Gateway Out14" SrcPort 1 Points [20, 0] } Line { SrcBlock "Gateway Out13" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out12" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out11" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out10" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out9" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out1" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out8" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out6" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out7" SrcPort 1 Points [50, 0] } Line { SrcBlock "C8" SrcPort 4 Points [40, 0; 0, 250] DstBlock "y_vout" DstPort 1 } Line { SrcBlock "AddSub4" SrcPort 1 Points [45, 0] Branch { Points [155, 0] Branch { Points [0, -390] DstBlock "Gateway Out14" DstPort 1 } Branch { DstBlock "y" DstPort 1 } } Branch { Points [0, 75; -400, 0; 0, 90] DstBlock "Gateway Out5" DstPort 1 } } Line { SrcBlock "AddSub1" SrcPort 1 Points [0, 60] DstBlock "AddSub4" DstPort 1 } Line { SrcBlock "AddSub13" SrcPort 1 Points [0, 85] DstBlock "AddSub4" DstPort 2 } Line { SrcBlock "AddSub7" SrcPort 1 Points [0, 35] DstBlock "AddSub1" DstPort 2 } Line { SrcBlock "AddSub6" SrcPort 1 DstBlock "AddSub1" DstPort 1 } Line { SrcBlock "C7" SrcPort 3 Points [20, 0] Branch { Points [0, -105] DstBlock "Gateway Out12" DstPort 1 } Branch { Points [0, 65; 75, 0] DstBlock "AddSub7" DstPort 1 } } Line { SrcBlock "C8" SrcPort 3 Points [10, 0] Branch { Points [0, -90] DstBlock "Gateway Out13" DstPort 1 } Branch { DstBlock "AddSub7" DstPort 2 } } Line { SrcBlock "C5" SrcPort 3 Points [10, 0] Branch { Points [0, -135] DstBlock "Gateway Out10" DstPort 1 } Branch { Points [0, 70; 85, 0] DstBlock "AddSub6" DstPort 1 } } Line { SrcBlock "C6" SrcPort 3 Points [15, 0] Branch { Points [0, -120] DstBlock "Gateway Out11" DstPort 1 } Branch { DstBlock "AddSub6" DstPort 2 } } Line { SrcBlock "C7" SrcPort 2 DstBlock "C8" DstPort 2 } Line { SrcBlock "C7" SrcPort 1 DstBlock "C8" DstPort 1 } Line { SrcBlock "C6" SrcPort 2 DstBlock "C7" DstPort 2 } Line { SrcBlock "C6" SrcPort 1 DstBlock "C7" DstPort 1 } Line { SrcBlock "C5" SrcPort 2 DstBlock "C6" DstPort 2 } Line { SrcBlock "C5" SrcPort 1 DstBlock "C6" DstPort 1 } Line { SrcBlock "C4" SrcPort 3 Points [15, 0] Branch { Points [0, -150] DstBlock "Gateway Out9" DstPort 1 } Branch { DstBlock "AddSub12" DstPort 2 } } Line { SrcBlock "C4" SrcPort 2 DstBlock "C5" DstPort 2 } Line { SrcBlock "C4" SrcPort 1 DstBlock "C5" DstPort 1 } Line { SrcBlock "C3" SrcPort 3 Points [20, 0] Branch { Points [0, -165] DstBlock "Gateway Out8" DstPort 1 } Branch { Points [0, 65; 80, 0] DstBlock "AddSub12" DstPort 1 } } Line { SrcBlock "C3" SrcPort 2 DstBlock "C4" DstPort 2 } Line { SrcBlock "C3" SrcPort 1 DstBlock "C4" DstPort 1 } Line { SrcBlock "C1" SrcPort 3 Points [15, 0] Branch { Points [0, -195] DstBlock "Gateway Out7" DstPort 1 } Branch { Points [0, 55] Branch { Points [0, 410] DstBlock "Gateway Out2" DstPort 1 } Branch { Points [0, 5; 95, 0] DstBlock "AddSub5" DstPort 1 } } } Line { SrcBlock "C2" SrcPort 3 Points [20, 0] Branch { Points [0, -180] DstBlock "Gateway Out1" DstPort 1 } Branch { DstBlock "AddSub5" DstPort 2 } } Line { SrcBlock "C2" SrcPort 2 DstBlock "C3" DstPort 2 } Line { SrcBlock "C2" SrcPort 1 DstBlock "C3" DstPort 1 } Line { SrcBlock "C1" SrcPort 2 DstBlock "C2" DstPort 2 } Line { SrcBlock "C1" SrcPort 1 DstBlock "C2" DstPort 1 } Line { SrcBlock "x_valid" SrcPort 1 Points [200, 0] Branch { Points [0, 450] DstBlock "Gateway Out4" DstPort 1 } Branch { Points [0, -20] DstBlock "C1" DstPort 2 } } Line { Points [780, 755; 50, 0] } Line { SrcBlock "Gateway Out2" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out5" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out3" SrcPort 1 Points [50, 0] } Line { SrcBlock "Gateway Out4" SrcPort 1 Points [50, 0] } Line { SrcBlock "AddSub5" SrcPort 1 Points [0, 35] DstBlock "AddSub13" DstPort 1 } Line { SrcBlock "AddSub12" SrcPort 1 DstBlock "AddSub13" DstPort 2 } Line { SrcBlock "x" SrcPort 1 Points [210, 0] Branch { Points [0, -170] DstBlock "Gateway Out6" DstPort 1 } Branch { Points [0, 475] DstBlock "Gateway Out3" DstPort 1 } Branch { DstBlock "C1" DstPort 1 } } } } Block { BlockType SubSystem Name "Combine" SID "14704" Ports [4, 1] Position [1130, 162, 1170, 223] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Combine" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Re*Re" SID "14705" Position [235, 323, 265, 337] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "Im*Im" SID "14706" Position [235, 343, 265, 357] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "Re*Im" SID "14707" Position [235, 508, 265, 522] NamePlacement "alternate" Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "Im*Re" SID "14708" Position [235, 528, 265, 542] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub" SID "14709" Ports [2, 1] Position [340, 318, 385, 362] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Subtraction" use_carryin off use_carryout off en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[5 0 0 8 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,2,1,white,blue,0,32e1f85f,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bf{a - b}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub1" SID "14710" Ports [2, 1] Position [340, 503, 385, 547] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[5 0 0 8 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,2,1,white,blue,0,e139daf6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bf{a + b}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub2" SID "14711" Ports [2, 1] Position [580, 338, 625, 382] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "1" precision "User Defined" arith_type "Unsigned" n_bits "32" bin_pt "0" quantization "Truncate" overflow "Flag as error" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[10 0 0 18 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,2,1,white,blue,0,e85d8a90,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bf{a + b}','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\ne" "wline\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType BusCreator Name "Bus\nCreator" SID "14712" Ports [2, 1] Position [935, 246, 940, 284] ZOrder -2 ShowName off Inputs "2" DisplayOption "bar" } Block { BlockType Reference Name "Gateway Out1" SID "14713" Ports [1, 1] Position [665, 134, 700, 146] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out2" SID "14714" Ports [1, 1] Position [700, 159, 735, 171] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out3" SID "14715" Ports [1, 1] Position [700, 184, 735, 196] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out4" SID "14716" Ports [1, 1] Position [665, 109, 700, 121] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out5" SID "14717" Ports [1, 1] Position [700, 209, 735, 221] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out6" SID "14718" Ports [1, 1] Position [700, 234, 735, 246] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out7" SID "14719" Ports [1, 1] Position [700, 284, 735, 296] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Scope Name "LTS Sum" SID "14720" Ports [8] Position [1030, 110, 1065, 295] ZOrder -3 Floating off Location [6, 45, 1686, 1049] Open off NumInputPorts "8" ZoomMode "yonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" } TimeRange "5000" YMin "-50~-100~-40~-20~0~0~0~0" YMax "100~50~40~30~25000~2500~25000~25000" SaveName "ScopeData39" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType Reference Name "Mult" SID "14721" Ports [2, 1] Position [470, 328, 515, 372] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mult" SourceType "Xilinx Multiplier Block" infoedit "Hardware notes: To check for the optimum internal pipeline stages of the dedicated multiplier you" " must select 'Test for optimum pipelining'.

Optimization Goal: For implementation into device fabric (LUT" "s), the Speed or Area optimization will take effect only if it's supported by IP for the particular device famil" "y. Otherwise, the results will be identical regardless of the selection." precision "User Defined" arith_type "Unsigned" n_bits "32" bin_pt "0" quantization "Truncate" overflow "Flag as error" en off latency "1" dbl_ovrd off use_behavioral_HDL off opt "Speed" use_embedded on optimum_pipeline off xl_use_area off xl_area "[60 18 0 106 0 0 0]" pipeline "on" use_rpm "off" placement_style "Rectangular shape" has_advanced_control "0" sggui_pos "20,20,356,448" block_type "mult" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,2,1,white,blue,0,82c891c1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bfa \\times b','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' " "\\n ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mult1" SID "14722" Ports [2, 1] Position [470, 513, 515, 557] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mult" SourceType "Xilinx Multiplier Block" infoedit "Hardware notes: To check for the optimum internal pipeline stages of the dedicated multiplier you" " must select 'Test for optimum pipelining'.

Optimization Goal: For implementation into device fabric (LUT" "s), the Speed or Area optimization will take effect only if it's supported by IP for the particular device famil" "y. Otherwise, the results will be identical regardless of the selection." precision "User Defined" arith_type "Unsigned" n_bits "32" bin_pt "0" quantization "Truncate" overflow "Flag as error" en off latency "1" dbl_ovrd off use_behavioral_HDL off opt "Speed" use_embedded on optimum_pipeline off xl_use_area off xl_area "[60 18 0 106 0 0 0]" pipeline "on" use_rpm "off" placement_style "Rectangular shape" has_advanced_control "0" sggui_pos "20,20,356,448" block_type "mult" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,2,1,white,blue,0,82c891c1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bfa \\times b','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' " "\\n ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "R" SID "14723" Position [705, 353, 735, 367] IconDisplay "Port number" } Line { SrcBlock "AddSub" SrcPort 1 Points [40, 0] Branch { DstBlock "Mult" DstPort 1 } Branch { Points [0, 20] DstBlock "Mult" DstPort 2 } } Line { SrcBlock "AddSub1" SrcPort 1 Points [55, 0] Branch { DstBlock "Mult1" DstPort 1 } Branch { Points [0, 20] DstBlock "Mult1" DstPort 2 } } Line { SrcBlock "Mult" SrcPort 1 Points [20, 0] Branch { DstBlock "AddSub2" DstPort 1 } Branch { Points [0, -135] DstBlock "Gateway Out5" DstPort 1 } } Line { SrcBlock "Mult1" SrcPort 1 Points [30, 0; 0, -165] Branch { DstBlock "AddSub2" DstPort 2 } Branch { Points [0, -130] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "Re*Re" SrcPort 1 Points [10, 0] Branch { DstBlock "AddSub" DstPort 1 } Branch { Points [0, -215] DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "Im*Im" SrcPort 1 Points [15, 0] Branch { DstBlock "AddSub" DstPort 2 } Branch { Points [0, -210] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "AddSub2" SrcPort 1 Points [50, 0] Branch { DstBlock "R" DstPort 1 } Branch { Points [0, -70] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "Re*Im" SrcPort 1 Points [30, 0] Branch { DstBlock "AddSub1" DstPort 1 } Branch { Points [0, -350] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "Im*Re" SrcPort 1 Points [35, 0] Branch { DstBlock "AddSub1" DstPort 2 } Branch { Points [0, -345] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "Gateway Out4" SrcPort 1 DstBlock "LTS Sum" DstPort 1 } Line { SrcBlock "Gateway Out1" SrcPort 1 DstBlock "LTS Sum" DstPort 2 } Line { SrcBlock "Gateway Out2" SrcPort 1 DstBlock "LTS Sum" DstPort 3 } Line { SrcBlock "Gateway Out3" SrcPort 1 DstBlock "LTS Sum" DstPort 4 } Line { SrcBlock "Gateway Out5" SrcPort 1 DstBlock "LTS Sum" DstPort 5 } Line { SrcBlock "Gateway Out6" SrcPort 1 DstBlock "LTS Sum" DstPort 6 } Line { SrcBlock "Gateway Out7" SrcPort 1 Points [75, 0] Branch { DstBlock "LTS Sum" DstPort 8 } Branch { Points [0, -15] Branch { Points [0, -20] DstBlock "Bus\nCreator" DstPort 1 } Branch { DstBlock "Bus\nCreator" DstPort 2 } } } Line { SrcBlock "Bus\nCreator" SrcPort 1 DstBlock "LTS Sum" DstPort 7 } } } Block { BlockType Reference Name "Delay1" SID "14724" Ports [2, 1] Position [300, 166, 335, 204] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en on latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,38,2,1,white,blue,0,7c0ac154,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 38 38 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 38 38 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[24.55 24.55 29." "55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[19.55 19.55 24.55 24.55 19." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('inp" "ut',2,'en');\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay2" SID "14725" Ports [2, 1] Position [300, 256, 335, 294] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en on latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,38,2,1,white,blue,0,7c0ac154,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 38 38 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 38 38 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[24.55 24.55 29." "55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[19.55 19.55 24.55 24.55 19." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('inp" "ut',2,'en');\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay3" SID "14726" Ports [1, 1] Position [300, 576, 335, 614] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,38,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 38 38 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 38 38 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[24.55 24.55 29." "55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[19.55 19.55 24.55 24.55 19." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-1}'" ",'texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay4" SID "14727" Ports [1, 1] Position [300, 291, 335, 329] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,38,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 38 38 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 38 38 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[24.55 24.55 29." "55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[19.55 19.55 24.55 24.55 19." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-1}'" ",'texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "FSM" SID "14728" Ports [1, 3] Position [415, 558, 515, 632] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskPromptString "Coefficients/correlator" MaskStyleString "edit" MaskVariables "N=@1;" MaskTunableValueString "on" MaskEnableString "on" MaskVisibilityString "on" MaskToolTipString "on" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "4" System { Name "FSM" Location [480, 85, 2052, 1259] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "125" Block { BlockType Inport Name "IQ_Valid" SID "14729" Position [195, 338, 225, 352] IconDisplay "Port number" } Block { BlockType Reference Name "Coef Addr Gen" SID "14730" Ports [1, 1] Position [610, 623, 660, 667] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited count" "er is implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "N-1" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "ceil(log2(N))" bin_pt "0" load_pin off rst off en on explicit_period "off" period "1" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[3 3 0 4 0 0 0]" use_rpm "on" has_advanced_control "0" sggui_pos "20,20,356,524" block_type "counter" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,44,1,1,white,blue,0,b089e9c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 44 44 0 ]);\npatch([11.65 20.32 26.32 32.32 38.32 26.32 17.65 11.65 ],[28.66" " 28.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([17.65 26.32 20.32 11.65 17.65 ],[22.66 22.66 28." "66 28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([11.65 20.32 26.32 17.65 11.65 ],[16.66 16.66 22.66 22.66 16.66 ]" ",[1 1 1 ]);\npatch([17.65 38.32 32.32 26.32 20.32 11.65 17.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'en');\n\ncolor('black');disp('{\\fontsize{14}\\bf++}','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');\n" } Block { BlockType Reference Name "Constant" SID "14731" Ports [0, 1] Position [430, 490, 455, 510] BlockMirror on NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "N-2" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "ceil(log2(N))" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,20,0,1,white,blue,0,fca86624,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 20 20 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 20 20 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[12.22 12" ".22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[10.22 10.22 12.22 12." "22 10.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\n" "patch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('out" "put',1,'2');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Data Addr Gen" SID "14732" Ports [1, 1] Position [610, 558, 660, 602] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited count" "er is implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "N-1" operation "Up" start_count "7" cnt_by_val "1" arith_type "Unsigned" n_bits "ceil(log2(N))" bin_pt "0" load_pin off rst off en on explicit_period "off" period "1" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[3 3 0 4 0 0 0]" use_rpm "on" has_advanced_control "0" sggui_pos "20,20,356,524" block_type "counter" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,44,1,1,white,blue,0,b089e9c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 44 44 0 ]);\npatch([11.65 20.32 26.32 32.32 38.32 26.32 17.65 11.65 ],[28.66" " 28.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([17.65 26.32 20.32 11.65 17.65 ],[22.66 22.66 28." "66 28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([11.65 20.32 26.32 17.65 11.65 ],[16.66 16.66 22.66 22.66 16.66 ]" ",[1 1 1 ]);\npatch([17.65 38.32 32.32 26.32 20.32 11.65 17.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'en');\n\ncolor('black');disp('{\\fontsize{14}\\bf++}','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');\n" } Block { BlockType Reference Name "Delay1" SID "14733" Ports [1, 1] Position [625, 331, 650, 359] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "N" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "25,28,1,1,white,blue,0,d390c2d8,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 " "17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33" " 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('blac" "k');disp('z^{-4}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out" SID "14734" Ports [1, 1] Position [760, 745, 795, 755] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Data Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out1" SID "14735" Ports [1, 1] Position [760, 760, 795, 770] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Coef Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "14736" Ports [1, 1] Position [760, 790, 795, 800] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "IQ Valid" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "14737" Ports [1, 1] Position [760, 775, 795, 785] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr Load" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "14738" Ports [1, 1] Position [760, 805, 795, 815] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Counters en" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Inverter" SID "14739" Ports [1, 1] Position [305, 418, 330, 432] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "25,14,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfprintf" "('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical" SID "14740" Ports [2, 1] Position [515, 372, 545, 403] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "30,31,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 31 31 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 31 31 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 19.4" "4 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 19.44 " "15.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\np" "atch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('or" "');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "14741" Ports [2, 1] Position [355, 417, 385, 448] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "30,31,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 31 31 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 31 31 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 19.4" "4 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 19.44 " "15.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\np" "atch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('an" "d');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Scope Name "Long Corr\nScope" SID "14742" Ports [5] Position [905, 745, 940, 815] Floating off Location [990, 267, 2453, 947] Open off NumInputPorts "5" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" } YMin "-1~-1~-35~-5~-5" YMax "1~1~25~5~5" SaveName "ScopeData4" DataFormat "StructureWithTime" SampleTime "0" } Block { BlockType Reference Name "Relational" SID "14743" Ports [2, 1] Position [350, 468, 390, 512] BlockMirror on NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "40,44,2,1,white,blue,0,2a81ff49,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 44 44 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[27.55 27." "55 32.55 27.55 32.55 32.55 32.55 27.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[22.55 22.55 27.55 2" "7.55 22.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[17.55 17.55 22.55 22.55 17.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[12.55 12.55 17.55 12.55 17.55 17.55 12.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bfa = b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "S-R Latch" SID "14744" Ports [2, 1] Position [410, 392, 455, 448] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "S-R Latch" Location [351, 366, 2001, 1172] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "14745" Position [140, 103, 170, 117] IconDisplay "Port number" } Block { BlockType Inport Name "R" SID "14746" Position [140, 88, 170, 102] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "14747" Ports [0, 1] Position [195, 71, 210, 89] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "15,18,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11.22 " "13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 9.22 " "],[0.931 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([4.55 " "11.44 9.44 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "14748" Ports [1, 1] Position [230, 86, 255, 104] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('outpu" "t',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "14749" Ports [1, 1] Position [230, 101, 255, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('outpu" "t',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "14750" Ports [3, 1] Position [300, 71, 345, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "14751" Position [370, 88, 400, 102] IconDisplay "Port number" } Line { SrcBlock "Convert2" SrcPort 1 DstBlock "Register2" DstPort 3 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "S" SrcPort 1 DstBlock "Convert2" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Register2" DstPort 1 } } } Block { BlockType Outport Name "Data Addr" SID "14752" Position [810, 573, 840, 587] IconDisplay "Port number" } Block { BlockType Outport Name "Coef Addr" SID "14753" Position [810, 638, 840, 652] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "load" SID "14754" Position [810, 338, 840, 352] Port "3" IconDisplay "Port number" } Line { Name "Corr Load" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 DstBlock "Long Corr\nScope" DstPort 3 } Line { SrcBlock "IQ_Valid" SrcPort 1 Points [55, 0] Branch { DstBlock "Delay1" DstPort 1 } Branch { Points [0, 35] Branch { Points [0, 25] Branch { DstBlock "S-R Latch" DstPort 1 } Branch { Points [0, 20] Branch { DstBlock "Inverter" DstPort 1 } Branch { Points [0, 370] DstBlock "Gateway Out2" DstPort 1 } } } Branch { DstBlock "Logical" DstPort 1 } } } Line { Name "IQ Valid" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 DstBlock "Long Corr\nScope" DstPort 4 } Line { SrcBlock "Delay1" SrcPort 1 Points [25, 0] Branch { DstBlock "load" DstPort 1 } Branch { Points [0, 435] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "S-R Latch" SrcPort 1 Points [25, 0; 0, -25] DstBlock "Logical" DstPort 2 } Line { SrcBlock "Logical" SrcPort 1 Points [30, 0; 0, 190] Branch { DstBlock "Data Addr Gen" DstPort 1 } Branch { Points [0, 65] Branch { DstBlock "Coef Addr Gen" DstPort 1 } Branch { Points [0, 165] DstBlock "Gateway Out4" DstPort 1 } } } Line { SrcBlock "Constant" SrcPort 1 DstBlock "Relational" DstPort 2 } Line { SrcBlock "Relational" SrcPort 1 Points [-45, 0; 0, -50] DstBlock "Logical1" DstPort 2 } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "S-R Latch" DstPort 2 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { Name "Counters en" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 DstBlock "Long Corr\nScope" DstPort 5 } Line { SrcBlock "Data Addr Gen" SrcPort 1 Points [55, 0] Branch { Points [0, -100] DstBlock "Relational" DstPort 1 } Branch { DstBlock "Data Addr" DstPort 1 } Branch { Points [0, 170] DstBlock "Gateway Out" DstPort 1 } } Line { SrcBlock "Coef Addr Gen" SrcPort 1 Points [45, 0] Branch { DstBlock "Coef Addr" DstPort 1 } Branch { Points [0, 120] DstBlock "Gateway Out1" DstPort 1 } } Line { Name "Data Addr" Labels [0, 0] SrcBlock "Gateway Out" SrcPort 1 DstBlock "Long Corr\nScope" DstPort 1 } Line { Name "Coef Addr" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 DstBlock "Long Corr\nScope" DstPort 2 } Annotation { Name "The correlator archiecture divides the 64-point dot product\ninto 8 parallel 8-point proudct/sum oper" "ations. For every sample\neach sub block computes an 8-point dot product, the results of which\nare then summed." " For a sample rate = sys_clk/8 the correaltor runs\nnon-stop. For slower sample rates the correlator runs for 8 " "cycles\nafter each input sample, then pauses until the next sample is valid." Position [418, 255] } } } Block { BlockType Goto Name "Goto" SID "14755" Position [565, 560, 640, 580] ZOrder -10 ShowName off GotoTag "ltsCorr_dAddr" TagVisibility "scoped" } Block { BlockType GotoTagVisibility Name "Goto Tag\nVisibility" SID "14756" Position [660, 572, 744, 599] ZOrder -11 GotoTag "ltsCorr_dAddr" } Block { BlockType GotoTagVisibility Name "Goto Tag\nVisibility1" SID "14757" Position [755, 572, 840, 600] ZOrder -11 GotoTag "ltsCorr_cAddr" } Block { BlockType GotoTagVisibility Name "Goto Tag\nVisibility2" SID "14758" Position [850, 572, 935, 600] ZOrder -11 GotoTag "ltsCorr_ld" } Block { BlockType Goto Name "Goto1" SID "14759" Position [565, 585, 640, 605] ZOrder -10 ShowName off GotoTag "ltsCorr_cAddr" TagVisibility "scoped" } Block { BlockType Goto Name "Goto2" SID "14760" Position [560, 610, 640, 630] ZOrder -10 ShowName off GotoTag "ltsCorr_ld" TagVisibility "scoped" } Block { BlockType Goto Name "Goto3" SID "14761" Position [1270, 255, 1345, 275] ZOrder -10 ShowName off GotoTag "CS_LTS_Corr" TagVisibility "global" } Block { BlockType Outport Name "R" SID "14762" Position [1235, 188, 1265, 202] IconDisplay "Port number" } Line { SrcBlock "rx_IQ_valid" SrcPort 1 Points [85, 0] Branch { Points [0, -25] Branch { Points [0, -90] DstBlock "Delay1" DstPort 2 } Branch { DstBlock "Delay2" DstPort 2 } } Branch { DstBlock "Delay4" DstPort 1 } Branch { Points [0, 285] DstBlock "Delay3" DstPort 1 } } Line { SrcBlock "FSM" SrcPort 3 DstBlock "Goto2" DstPort 1 } Line { SrcBlock "FSM" SrcPort 2 DstBlock "Goto1" DstPort 1 } Line { SrcBlock "FSM" SrcPort 1 DstBlock "Goto" DstPort 1 } Line { SrcBlock "Delay2" SrcPort 1 Points [170, 0] Branch { Points [0, 190] DstBlock "C2" DstPort 1 } Branch { DstBlock "C5" DstPort 1 } } Line { SrcBlock "Delay1" SrcPort 1 Points [180, 0] Branch { DstBlock "C1" DstPort 1 } Branch { Points [0, 195] DstBlock "C7" DstPort 1 } } Line { SrcBlock "Combine" SrcPort 1 Points [25, 0] Branch { DstBlock "R" DstPort 1 } Branch { Points [0, 70] DstBlock "Goto3" DstPort 1 } } Line { SrcBlock "Rx I" SrcPort 1 DstBlock "Delay1" DstPort 1 } Line { SrcBlock "Rx Q" SrcPort 1 DstBlock "Delay2" DstPort 1 } Line { SrcBlock "Delay3" SrcPort 1 DstBlock "FSM" DstPort 1 } Line { SrcBlock "Delay4" SrcPort 1 Points [125, 0] Branch { Points [0, 0] Branch { Points [0, -90] DstBlock "C1" DstPort 2 } Branch { DstBlock "C5" DstPort 2 } } Branch { Points [0, 105] Branch { Points [0, 85] DstBlock "C2" DstPort 2 } Branch { DstBlock "C7" DstPort 2 } } } Line { SrcBlock "C3" SrcPort 1 DstBlock "AddSub4" DstPort 2 } Line { SrcBlock "C1" SrcPort 1 Points [15, 0; 0, -20] DstBlock "AddSub4" DstPort 1 } Line { SrcBlock "C1" SrcPort 3 Points [20, 0; 0, -20] DstBlock "C3" DstPort 1 } Line { SrcBlock "C1" SrcPort 4 DstBlock "C3" DstPort 2 } Line { SrcBlock "C5" SrcPort 1 Points [40, 0; 0, -20] DstBlock "AddSub1" DstPort 1 } Line { SrcBlock "C6" SrcPort 1 DstBlock "AddSub1" DstPort 2 } Line { SrcBlock "C5" SrcPort 3 Points [20, 0; 0, -20] DstBlock "C6" DstPort 1 } Line { SrcBlock "C5" SrcPort 4 DstBlock "C6" DstPort 2 } Line { SrcBlock "C7" SrcPort 1 Points [25, 0; 0, -20] DstBlock "AddSub2" DstPort 1 } Line { SrcBlock "C8" SrcPort 1 DstBlock "AddSub2" DstPort 2 } Line { SrcBlock "C7" SrcPort 3 Points [20, 0; 0, -20] DstBlock "C8" DstPort 1 } Line { SrcBlock "C7" SrcPort 4 DstBlock "C8" DstPort 2 } Line { SrcBlock "C2" SrcPort 1 Points [10, 0; 0, -20] DstBlock "AddSub3" DstPort 1 } Line { SrcBlock "C4" SrcPort 1 DstBlock "AddSub3" DstPort 2 } Line { SrcBlock "C2" SrcPort 3 Points [20, 0; 0, -20] DstBlock "C4" DstPort 1 } Line { SrcBlock "C2" SrcPort 4 DstBlock "C4" DstPort 2 } Line { SrcBlock "AddSub4" SrcPort 1 DstBlock "Combine" DstPort 1 } Line { SrcBlock "AddSub1" SrcPort 1 Points [75, 0; 0, -80] DstBlock "Combine" DstPort 2 } Line { SrcBlock "AddSub2" SrcPort 1 Points [115, 0; 0, -170] DstBlock "Combine" DstPort 3 } Line { SrcBlock "AddSub3" SrcPort 1 Points [155, 0; 0, -240] DstBlock "Combine" DstPort 4 } Annotation { Name "The architecture for this correlator is based on one developed by Dr. Chris Dick (Cheif DSP Scientist at" " Xilinx).\nThe version here has been modified in a few ways:\n-The inner correlators run at 8x the input sample ra" "te (vs 5 in the original)\n-The \"multiplications\" are 3-bit by 1-bit (vs 1x1 in the original), which improves\nc" "orrelation performance with interference or overlapping preambles" Position [606, 740] } Annotation { Name "i\nq\nq\ni" Position [288, 78] } } } Block { BlockType Reference Name "Delay" SID "18080" Ports [1, 1] Position [1195, 198, 1220, 222] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "25,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 24 24 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 24 24 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[15" ".33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[12.33 12.33 " "15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[9.33 9.33 12.33 12.33 9.33 ]" ",[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('bl" "ack');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From1" SID "18081" Position [140, 205, 340, 225] ShowName off CloseFcn "tagdialog Close" GotoTag "regRx_OFDM_Rx_Req_Pkt_Det" TagVisibility "global" } Block { BlockType Reference Name "Gateway Out1" SID "14763" Ports [1, 1] Position [1425, 674, 1460, 686] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Correlation " RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "14764" Ports [1, 1] Position [1425, 659, 1460, 671] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Rx Q" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "14765" Ports [1, 1] Position [1425, 689, 1460, 701] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Detection" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "14766" Ports [1, 1] Position [1425, 644, 1460, 656] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Rx I" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "14767" Ports [1, 1] Position [1425, 629, 1460, 641] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "En" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "18084" Ports [1, 1] Position [1425, 704, 1460, 716] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "OFDM Pkt Det In" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "14768" Ports [1, 1] Position [1425, 734, 1460, 746] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Timeout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Inverter1" SID "18082" Ports [1, 1] Position [590, 206, 615, 224] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.2" "2 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 " "11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);" "\npatch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('no" "t');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Scope Name "LTS Corr" SID "14770" Ports [8] Position [1560, 631, 1600, 744] ZOrder -3 Floating off Location [1921, 45, 3841, 1199] Open off NumInputPorts "8" ZoomMode "yonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" } List { ListType ScopeGraphics FigureColor "[0.5 0.5 0.5]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "14000" YMin "0~-1~-1~0~-1~-1~-1~0" YMax "1~1~1~20000~1~1~1~1" SaveName "ScopeData55" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType SubSystem Name "LTS Corr Timeout" SID "14771" Ports [3, 1] Position [1245, 136, 1335, 224] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "LTS Corr Timeout" Location [280, 193, 2120, 1196] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "89" Block { BlockType Inport Name "Pkt Det" SID "14772" Position [245, 473, 275, 487] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "IQ Valid" SID "14773" Position [245, 493, 275, 507] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "Det" SID "14774" Position [245, 308, 275, 322] NamePlacement "alternate" Port "3" IconDisplay "Port number" } Block { BlockType Reference Name "Counter" SID "14775" Ports [2, 1] Position [495, 445, 555, 505] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited counter i" "s implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "Inf" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "10" bin_pt "0" load_pin off rst on en on explicit_period "off" period "1" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "counter" sg_icon_stat "60,60,2,1,white,blue,0,ae3608d6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 60 60 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[38.88 38.88 46" ".88 38.88 46.88 46.88 46.88 38.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[30.88 30.88 38.88 38.88 30.88" " ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[22.88 22.88 30.88 30.88 22.88 ],[1 1 1 ]);\npatch(" "[20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[14.88 14.88 22.88 14.88 22.88 22.88 14.88 ],[0.931 0.946 0.973 ]);\nfpr" "intf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'" ",1,'rst');\ncolor('black');port_label('input',2,'en');\n\ncolor('black');disp('{\\fontsize{14}\\bf++}','texmode','" "on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Display Name "Display" SID "14776" Ports [1] Position [795, 611, 880, 639] ShowName off Decimation "1" Lockdown off } Block { BlockType From Name "From2" SID "14777" Position [440, 529, 610, 551] ShowName off CloseFcn "tagdialog Close" GotoTag "regRx_PktDet_Timout" TagVisibility "global" } Block { BlockType Reference Name "Gateway Out2" SID "14778" Ports [1, 1] Position [1065, 174, 1100, 186] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Corr 1 Latch" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "14779" Ports [1, 1] Position [1065, 154, 1100, 166] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Corr 1" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "14780" Ports [1, 1] Position [1065, 234, 1100, 246] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Pkt Det" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "14781" Ports [1, 1] Position [1065, 254, 1100, 266] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Timeout counter" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "14782" Ports [1, 1] Position [1065, 334, 1100, 346] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Timeout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "14783" Ports [1, 1] Position [1065, 274, 1100, 286] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "No Det" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out9" SID "14784" Ports [1, 1] Position [1065, 294, 1100, 306] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Counter at limit" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Inverter" SID "14785" Ports [1, 1] Position [365, 434, 400, 466] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "35,32,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 32 32 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 32 32 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[20.44 20.44 24.4" "4 20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[16.44 16.44 20.44 20.44 16.44 ]," "[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1 1 1 ]);\npatch([12.1" " 25.88 21.88 17.88 13.88 8.1 12.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter1" SID "14786" Ports [1, 1] Position [605, 309, 640, 341] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "35,32,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 32 32 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 32 32 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[20.44 20.44 24.4" "4 20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[16.44 16.44 20.44 20.44 16.44 ]," "[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1 1 1 ]);\npatch([12.1" " 25.88 21.88 17.88 13.88 8.1 12.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Scope Name "LTS Timeout" SID "14787" Ports [10] Position [1245, 140, 1295, 360] ZOrder -3 Floating off Location [26, 90, 1826, 1248] Open off NumInputPorts "10" ZoomMode "yonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" axes9 "%" axes10 "%" } List { ListType ScopeGraphics FigureColor "[0.5 0.5 0.5]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "18000" YMin "0~0~0~0~0~0~0~0~-1~-1" YMax "1~1~1~1~1~600~1~1~1~1" SaveName "ScopeData17" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType Reference Name "Logical" SID "14788" Ports [2, 1] Position [365, 471, 400, 509] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,38,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 38 38 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 38 38 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[24.55 24.55 29." "55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[19.55 19.55 24.55 24.55 19." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('and')" ";\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "14789" Ports [2, 1] Position [785, 301, 820, 394] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,93,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 93 93 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 93 93 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[51.55 51.55 56." "55 51.55 56.55 56.55 56.55 51.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[46.55 46.55 51.55 51.55 46." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[41.55 41.55 46.55 46.55 41.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[36.55 36.55 41.55 36.55 41.55 41.55 36.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('a" "nd');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational" SID "14790" Ports [2, 1] Position [675, 462, 730, 518] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a>b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "55,56,2,1,white,blue,0,b5131c97,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 55 55 0 0 ],[0 0 56 56 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ],[35.77 35" ".77 42.77 35.77 42.77 42.77 42.77 35.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[28.77 28.77 35.77" " 35.77 28.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[21.77 21.77 28.77 28.77 21.77 ]," "[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[14.77 14.77 21.77 14.77 21.77 21.77 14.77 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1," "'\\bfa > b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "S-R Latch" SID "14791" Ports [2, 1] Position [520, 308, 555, 337] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "S-R Latch" Location [384, 416, 2217, 1476] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "14792" Position [140, 103, 170, 117] IconDisplay "Port number" } Block { BlockType Inport Name "R" SID "14793" Position [140, 88, 170, 102] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "14794" Ports [0, 1] Position [195, 71, 210, 89] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "15,18,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11.22 " "13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 9.22 " "],[0.931 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([4.55 " "11.44 9.44 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "14795" Ports [1, 1] Position [210, 86, 235, 104] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('outpu" "t',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "14796" Ports [1, 1] Position [210, 101, 235, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('outpu" "t',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "14797" Ports [3, 1] Position [255, 71, 300, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "14798" Position [325, 88, 355, 102] IconDisplay "Port number" } Line { SrcBlock "S" SrcPort 1 DstBlock "Convert2" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "Convert2" SrcPort 1 DstBlock "Register2" DstPort 3 } } } Block { BlockType Reference Name "done14" SID "14799" Ports [1, 1] Position [705, 620, 740, 630] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, " "or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarded, dep" "ending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6.11 6.1" "1 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6.11 5.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Outport Name "Timeout" SID "14800" Position [935, 342, 965, 358] IconDisplay "Port number" } Line { SrcBlock "Logical" SrcPort 1 DstBlock "Counter" DstPort 2 } Line { SrcBlock "Pkt Det" SrcPort 1 Points [45, 0] Branch { DstBlock "Logical" DstPort 1 } Branch { Points [0, -30] Branch { DstBlock "Inverter" DstPort 1 } Branch { Points [0, -210] DstBlock "Gateway Out5" DstPort 1 } } } Line { SrcBlock "IQ Valid" SrcPort 1 DstBlock "Logical" DstPort 2 } Line { SrcBlock "Inverter" SrcPort 1 Points [50, 0] Branch { Points [0, 10] DstBlock "Counter" DstPort 1 } Branch { Points [0, -120] DstBlock "S-R Latch" DstPort 2 } } Line { SrcBlock "Det" SrcPort 1 Points [75, 0] Branch { DstBlock "S-R Latch" DstPort 1 } Branch { Points [0, -155] DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "S-R Latch" SrcPort 1 Points [25, 0] Branch { Points [0, -145] DstBlock "Gateway Out2" DstPort 1 } Branch { DstBlock "Inverter1" DstPort 1 } } Line { SrcBlock "Relational" SrcPort 1 Points [20, 0; 0, -120] Branch { DstBlock "Logical2" DstPort 2 } Branch { Points [0, -70] DstBlock "Gateway Out9" DstPort 1 } } Line { SrcBlock "Logical2" SrcPort 1 Points [65, 0] Branch { DstBlock "Timeout" DstPort 1 } Branch { Points [0, -10] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "Counter" SrcPort 1 Points [90, 0] Branch { DstBlock "Relational" DstPort 1 } Branch { Points [0, -215] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "From2" SrcPort 1 Points [20, 0] Branch { Points [0, -35] DstBlock "Relational" DstPort 2 } Branch { Points [0, 85] DstBlock "done14" DstPort 1 } } Line { SrcBlock "done14" SrcPort 1 DstBlock "Display" DstPort 1 } Line { Name "Corr 1" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 DstBlock "LTS Timeout" DstPort 1 } Line { Name "Corr 1 Latch" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 DstBlock "LTS Timeout" DstPort 2 } Line { Name "Pkt Det" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 DstBlock "LTS Timeout" DstPort 5 } Line { Name "Timeout counter" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 DstBlock "LTS Timeout" DstPort 6 } Line { Name "Timeout" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 DstBlock "LTS Timeout" DstPort 10 } Line { Name "No Det" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 DstBlock "LTS Timeout" DstPort 7 } Line { Name "Counter at limit" Labels [0, 0] SrcBlock "Gateway Out9" SrcPort 1 DstBlock "LTS Timeout" DstPort 8 } Line { SrcBlock "Inverter1" SrcPort 1 Points [100, 0] Branch { DstBlock "Logical2" DstPort 1 } Branch { Points [0, -45] DstBlock "Gateway Out8" DstPort 1 } } Annotation { Name "LTS corr asserts when timeout counter is around 290, for\na perfect Rx waveform with no AGC and auto-cor" "r pkt det." Position [466, 624] } } } Block { BlockType Reference Name "Logical1" SID "18083" Ports [2, 1] Position [685, 201, 720, 259] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,58,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 58 58 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 58 58 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[34.55" " 34.55 39.55 34.55 39.55 39.55 39.55 34.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[29.55 29.55 34" ".55 34.55 29.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[24.55 24.55 29.55 29.55 24.55 " "],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[19.55 19.55 24.55 19.55 24.55 24.55 19.55 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n" "color('black');disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Posedge" SID "14801" Ports [1, 1] Position [1110, 348, 1145, 362] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Posedge" Location [88, 301, 2330, 1301] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "14802" Position [200, 253, 230, 267] IconDisplay "Port number" } Block { BlockType Reference Name "Delay" SID "14803" Ports [1, 1] Position [425, 153, 460, 177] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. If r" "egister retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[15.33 15" ".33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.33 12.33 15.33" " 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 " "1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');" "disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "14804" Ports [1, 1] Position [490, 156, 515, 174] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "14805" Ports [2, 1] Position [540, 151, 585, 204] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,53,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 53 53 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 53 53 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[32.66 32.66 3" "8.66 32.66 38.66 38.66 38.66 32.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[26.66 26.66 32.66 32.66 26" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[20.66 20.66 26.66 26.66 20.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[14.66 14.66 20.66 14.66 20.66 20.66 14.66 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('" "and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "14806" Position [610, 173, 640, 187] IconDisplay "Port number" } Line { SrcBlock "D" SrcPort 1 Points [150, 0; 0, -70] Branch { DstBlock "Logical1" DstPort 2 } Branch { Points [0, -25] DstBlock "Delay" DstPort 1 } } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Delay" SrcPort 1 DstBlock "Inverter" DstPort 1 } Annotation { Name "Rising Edge Detection" Position [500, 112] } } } Block { BlockType SubSystem Name "S-R Latch2" SID "14807" Ports [2, 1] Position [1025, 338, 1060, 367] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "S-R Latch2" Location [351, 366, 2001, 1172] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "14808" Position [140, 103, 170, 117] IconDisplay "Port number" } Block { BlockType Inport Name "R" SID "14809" Position [140, 88, 170, 102] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "14810" Ports [0, 1] Position [195, 71, 210, 89] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "15,18,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11.22 13.22 " "11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 9.22 ],[0.931" " 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([4.55 11.44 9.44" " 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon" " graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "14811" Ports [1, 1] Position [230, 86, 255, 104] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cast');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "14812" Ports [1, 1] Position [230, 101, 255, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cast');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "14813" Ports [3, 1] Position [300, 71, 345, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 30.66 3" "6.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 30.66 24" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('" "input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'en');\ncolor('bl" "ack');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon te" "xt');" } Block { BlockType Outport Name "Q" SID "14814" Position [370, 88, 400, 102] IconDisplay "Port number" } Line { SrcBlock "Convert2" SrcPort 1 DstBlock "Register2" DstPort 3 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "S" SrcPort 1 DstBlock "Convert2" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Register2" DstPort 1 } } } Block { BlockType Reference Name "Slice" SID "14815" Ports [1, 1] Position [350, 288, 380, 302] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

" "

Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Upper Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,376" block_type "slice" block_version "10.1.3" sg_icon_stat "30,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 14 14 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 14 14 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[9" ".22 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[7.22 7.22 9.22" " 9.22 7.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 " "]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');por" "t_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Slice1" SID "14816" Ports [1, 1] Position [350, 323, 380, 337] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

" "

Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Upper Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,376" block_type "slice" block_version "10.1.3" sg_icon_stat "30,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 14 14 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 14 14 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[9" ".22 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[7.22 7.22 9.22" " 9.22 7.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 " "]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');por" "t_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Threshold Select" SID "14817" Ports [2, 2] Position [390, 483, 525, 527] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Threshold Select" Location [202, 70, 2473, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Pkt Det" SID "14818" Position [455, 273, 485, 287] IconDisplay "Port number" } Block { BlockType Inport Name "RSSI" SID "14819" Position [455, 248, 485, 262] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType From Name "From1" SID "14820" Position [355, 365, 610, 385] ShowName off CloseFcn "tagdialog Close" GotoTag "regRx_LongCorr_Thresh_lowSNR" TagVisibility "global" } Block { BlockType From Name "From2" SID "14821" Position [355, 400, 610, 420] ShowName off CloseFcn "tagdialog Close" GotoTag "regRx_LongCorr_Thresh_highSNR" TagVisibility "global" } Block { BlockType From Name "From3" SID "14822" Position [345, 315, 600, 335] ShowName off CloseFcn "tagdialog Close" GotoTag "regRx_LongCorr_RSSI_Thresh" TagVisibility "global" } Block { BlockType From Name "From4" SID "14823" Position [355, 535, 610, 555] ShowName off CloseFcn "tagdialog Close" GotoTag "regRx_LongCorr_PeakType_Thresh_lowSNR" TagVisibility "global" } Block { BlockType From Name "From5" SID "14824" Position [355, 600, 610, 620] ShowName off CloseFcn "tagdialog Close" GotoTag "regRx_LongCorr_PeakType_Thresh_highSNR" TagVisibility "global" } Block { BlockType Reference Name "Mux" SID "14825" Ports [3, 1] Position [810, 247, 835, 443] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "25,196,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 28 168 196 0 ],[0.77 0.82 " "0.91 ]);\nplot([0 25 25 0 0 ],[0 28 168 196 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[101.33" " 101.33 104.33 101.33 104.33 104.33 104.33 101.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[98.33 98.33" " 101.33 101.33 98.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[95.33 95.33 98.33 98.33 95.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[92.33 92.33 95.33 92.33 95.33 95.33 92.33 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input'," "3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux1" SID "14826" Ports [3, 1] Position [810, 447, 835, 643] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "25,196,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 28 168 196 0 ],[0.77 0.82 " "0.91 ]);\nplot([0 25 25 0 0 ],[0 28 168 196 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[101.33" " 101.33 104.33 101.33 104.33 104.33 104.33 101.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[98.33 98.33" " 101.33 101.33 98.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[95.33 95.33 98.33 98.33 95.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[92.33 92.33 95.33 92.33 95.33 95.33 92.33 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input'," "3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "14827" Ports [2, 1] Position [625, 242, 675, 293] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "50,51,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 51 51 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 50 50 0 0 ],[0 0 51 51 0 ]);\npatch([9.425 19.54 26.54 33.54 40.54 26.54 16.425 9.425 ],[32.77 32.7" "7 39.77 32.77 39.77 39.77 39.77 32.77 ],[1 1 1 ]);\npatch([16.425 26.54 19.54 9.425 16.425 ],[25.77 25.77 32.77 32" ".77 25.77 ],[0.931 0.946 0.973 ]);\npatch([9.425 19.54 26.54 16.425 9.425 ],[18.77 18.77 25.77 25.77 18.77 ],[1 1 " "1 ]);\npatch([16.425 40.54 33.54 26.54 19.54 9.425 16.425 ],[11.77 11.77 18.77 11.77 18.77 18.77 11.77 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');" "\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational1" SID "14828" Ports [2, 1] Position [725, 258, 765, 302] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a>b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[10 0 0 19 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,44,2,1,white,blue,0,b5131c97,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 44 44 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 44 44 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[27.55 27.55 32." "55 27.55 32.55 32.55 32.55 27.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[22.55 22.55 27.55 27.55 22." "55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[17.55 17.55 22.55 22.55 17.55 ],[1 1 1 ]);\npa" "tch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[12.55 12.55 17.55 12.55 17.55 17.55 12.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i" "nput',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa > b','texmod" "e','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "posedge" SID "14829" Ports [1, 1] Position [530, 271, 575, 289] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "posedge" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "14830" Position [275, 183, 305, 197] IconDisplay "Port number" } Block { BlockType Reference Name "Delay" SID "14831" Ports [1, 1] Position [425, 153, 460, 177] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. " "If register retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[15" ".33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.33 12." "33 15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 12.33 " "9.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\nc" "olor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "14832" Ports [1, 1] Position [495, 156, 520, 174] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "14833" Ports [2, 1] Position [540, 151, 585, 204] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,53,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 53 53 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 53 53 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[32.66 3" "2.66 38.66 32.66 38.66 38.66 38.66 32.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[26.66 26.66 32.66 " "32.66 26.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[20.66 20.66 26.66 26.66 20.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[14.66 14.66 20.66 14.66 20.66 20.66 14.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('" "black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "14834" Position [610, 173, 640, 187] IconDisplay "Port number" } Line { SrcBlock "Delay" SrcPort 1 DstBlock "Inverter" DstPort 1 } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "D" SrcPort 1 Points [75, 0] Branch { Points [0, -25] DstBlock "Delay" DstPort 1 } Branch { DstBlock "Logical1" DstPort 2 } } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical1" DstPort 1 } } } Block { BlockType Outport Name "Corr Thresh" SID "14835" Position [935, 338, 965, 352] IconDisplay "Port number" } Block { BlockType Outport Name "Peak Type Thresh" SID "14836" Position [935, 538, 965, 552] Port "2" IconDisplay "Port number" } Line { SrcBlock "Relational1" SrcPort 1 Points [15, 0] Branch { DstBlock "Mux" DstPort 1 } Branch { Points [0, 200] DstBlock "Mux1" DstPort 1 } } Line { SrcBlock "RSSI" SrcPort 1 DstBlock "Register1" DstPort 1 } Line { SrcBlock "posedge" SrcPort 1 DstBlock "Register1" DstPort 2 } Line { SrcBlock "Register1" SrcPort 1 DstBlock "Relational1" DstPort 1 } Line { SrcBlock "From3" SrcPort 1 Points [105, 0] DstBlock "Relational1" DstPort 2 } Line { SrcBlock "From2" SrcPort 1 DstBlock "Mux" DstPort 3 } Line { SrcBlock "From1" SrcPort 1 Points [135, 0; 0, -30] DstBlock "Mux" DstPort 2 } Line { SrcBlock "Pkt Det" SrcPort 1 DstBlock "posedge" DstPort 1 } Line { SrcBlock "Mux" SrcPort 1 DstBlock "Corr Thresh" DstPort 1 } Line { SrcBlock "Mux1" SrcPort 1 DstBlock "Peak Type Thresh" DstPort 1 } Line { SrcBlock "From4" SrcPort 1 DstBlock "Mux1" DstPort 2 } Line { SrcBlock "From5" SrcPort 1 DstBlock "Mux1" DstPort 3 } } } Block { BlockType SubSystem Name "negedge" SID "18085" Ports [1, 1] Position [870, 273, 905, 287] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "negedge" Location [88, 301, 2330, 1301] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "18086" Position [200, 253, 230, 267] IconDisplay "Port number" } Block { BlockType Reference Name "Delay" SID "18087" Ports [1, 1] Position [425, 153, 460, 177] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. If r" "egister retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[15.33 15" ".33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.33 12.33 15.33" " 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 " "1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');" "disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "18088" Ports [1, 1] Position [490, 181, 515, 199] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "18089" Ports [2, 1] Position [540, 151, 585, 204] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,53,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 53 53 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 53 53 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[32.66 32.66 3" "8.66 32.66 38.66 38.66 38.66 32.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[26.66 26.66 32.66 32.66 26" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[20.66 20.66 26.66 26.66 20.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[14.66 14.66 20.66 14.66 20.66 20.66 14.66 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('" "and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "18090" Position [610, 173, 640, 187] IconDisplay "Port number" } Line { SrcBlock "Delay" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "D" SrcPort 1 Points [150, 0; 0, -70] Branch { Points [0, -25] DstBlock "Delay" DstPort 1 } Branch { DstBlock "Inverter" DstPort 1 } } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical1" DstPort 2 } } } Block { BlockType Outport Name "Det" SID "14837" Position [1245, 348, 1275, 362] IconDisplay "Port number" } Block { BlockType Outport Name "Timeout" SID "14838" Position [1425, 173, 1455, 187] Port "2" IconDisplay "Port number" } Line { SrcBlock "rx_I" SrcPort 1 Points [55, 0] Branch { DstBlock "Slice" DstPort 1 } Branch { Points [0, 355] DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "rx_Q" SrcPort 1 Points [50, 0] Branch { DstBlock "Slice1" DstPort 1 } Branch { Points [0, 335] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "Correlator" SrcPort 1 Points [95, 0] Branch { DstBlock "Corr Event Logic" DstPort 2 } Branch { Points [0, 350] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "OFDM Pkt Det" SrcPort 1 Points [80, 0] Branch { Points [0, -95] DstBlock "LTS Corr Timeout" DstPort 1 } Branch { Labels [0, 0] Points [0, 250] Branch { DstBlock "Threshold Select" DstPort 1 } Branch { Points [0, 215] DstBlock "Gateway Out6" DstPort 1 } } Branch { Points [370, 0] Branch { DstBlock "Logical1" DstPort 2 } Branch { Points [0, 35] DstBlock "negedge" DstPort 1 } } } Line { Labels [0, 0] SrcBlock "Slice" SrcPort 1 DstBlock "Correlator" DstPort 1 } Line { Labels [0, 0] SrcBlock "Slice1" SrcPort 1 DstBlock "Correlator" DstPort 2 } Line { SrcBlock "rx_IQ_valid" SrcPort 1 Points [195, 0] Branch { DstBlock "Correlator" DstPort 3 } Branch { Points [0, 45; 145, 0; 0, -65] DstBlock "Corr Event Logic" DstPort 3 } Branch { Points [0, -185] DstBlock "LTS Corr Timeout" DstPort 2 } } Line { SrcBlock "RSSI" SrcPort 1 DstBlock "Threshold Select" DstPort 2 } Line { SrcBlock "Threshold Select" SrcPort 1 Points [105, 0; 0, -135] DstBlock "Corr Event Logic" DstPort 4 } Line { SrcBlock "Threshold Select" SrcPort 2 Points [125, 0; 0, -140] DstBlock "Corr Event Logic" DstPort 5 } Line { SrcBlock "S-R Latch2" SrcPort 1 DstBlock "Posedge" DstPort 1 } Line { SrcBlock "Posedge" SrcPort 1 Points [25, 0] Branch { DstBlock "Det" DstPort 1 } Branch { Points [0, 340] DstBlock "Gateway Out3" DstPort 1 } Branch { Points [0, -145] DstBlock "Delay" DstPort 1 } } Line { SrcBlock "Corr Event Logic" SrcPort 1 DstBlock "S-R Latch2" DstPort 1 } Line { SrcBlock "LTS Corr Timeout" SrcPort 1 Points [45, 0] Branch { DstBlock "Timeout" DstPort 1 } Branch { Points [0, 560] DstBlock "Gateway Out7" DstPort 1 } } Line { Name "Rx Q" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 DstBlock "LTS Corr" DstPort 3 } Line { Name "Rx I" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 DstBlock "LTS Corr" DstPort 2 } Line { Name "Correlation " Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 DstBlock "LTS Corr" DstPort 4 } Line { Name "Detection" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 DstBlock "LTS Corr" DstPort 5 } Line { Name "Timeout" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 DstBlock "LTS Corr" DstPort 8 } Line { Name "En" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 DstBlock "LTS Corr" DstPort 1 } Line { SrcBlock "Delay" SrcPort 1 DstBlock "LTS Corr Timeout" DstPort 3 } Line { SrcBlock "Logical1" SrcPort 1 Points [10, 0; 0, 85] Branch { Points [0, 0] DstBlock "Corr Event Logic" DstPort 1 } Branch { Points [0, 320] DstBlock "Gateway Out5" DstPort 1 } } Line { SrcBlock "From1" SrcPort 1 DstBlock "Inverter1" DstPort 1 } Line { SrcBlock "Inverter1" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { Name "OFDM Pkt Det In" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 DstBlock "LTS Corr" DstPort 6 } Line { SrcBlock "negedge" SrcPort 1 Points [35, 0; 0, 80] DstBlock "S-R Latch2" DstPort 2 } Annotation { Name "Delay LTS pulse so it occurs after pkt det\nin case LTF correlation is src of pkt det" Position [1281, 254] } } } Block { BlockType SubSystem Name "PHY CCA" SID "7382" Ports [8] Position [1050, 656, 1135, 779] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "PHY CCA" Location [24, 118, 2486, 1460] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "106" Block { BlockType Inport Name "LTS Sync" SID "7383" Position [290, 318, 320, 332] IconDisplay "Port number" } Block { BlockType Inport Name "LTS Timeout" SID "7384" Position [145, 428, 175, 442] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "IQ Valid" SID "7385" Position [290, 298, 320, 312] NamePlacement "alternate" Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "Det OFDM" SID "7386" Position [145, 383, 175, 397] NamePlacement "alternate" Port "4" IconDisplay "Port number" } Block { BlockType Inport Name "Avg RSSI Vec" SID "7387" Position [245, 628, 275, 642] NamePlacement "alternate" Port "5" IconDisplay "Port number" } Block { BlockType Inport Name "Reset OFDM" SID "7388" Position [145, 413, 175, 427] NamePlacement "alternate" Port "6" IconDisplay "Port number" } Block { BlockType Inport Name "Det DSSS" SID "7389" Position [145, 943, 175, 957] NamePlacement "alternate" Port "7" IconDisplay "Port number" } Block { BlockType Inport Name "Reset DSSS" SID "7390" Position [145, 983, 175, 997] NamePlacement "alternate" Port "8" IconDisplay "Port number" } Block { BlockType BusSelector Name "Bus\nSelector1" SID "7391" Ports [1, 4] Position [355, 540, 360, 725] ZOrder -3 ShowName off OutputSignals "RFA_RSSI,RFB_RSSI,RFC_RSSI,RFD_RSSI" Port { PortNumber 1 Name "" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 2 Name "" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 3 Name "" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 4 Name "" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Delay" SID "18096" Ports [1, 1] Position [355, 313, 380, 337] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "25,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 24 24 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 24 24 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[15" ".33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[12.33 12.33 " "15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[9.33 9.33 12.33 12.33 9.33 ]" ",[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('bl" "ack');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From1" SID "7392" Position [470, 930, 665, 950] ShowName off CloseFcn "tagdialog Close" GotoTag "regRx_DSSS_asserts_CCA_busy" TagVisibility "global" } Block { BlockType From Name "From2" SID "7393" Position [485, 575, 680, 595] ShowName off CloseFcn "tagdialog Close" GotoTag "regRx_RSSI_CS_THRESH" TagVisibility "global" } Block { BlockType From Name "From3" SID "7394" Position [645, 390, 840, 410] ShowName off CloseFcn "tagdialog Close" GotoTag "OFDM_RX_SIGNAL_VALID" TagVisibility "global" } Block { BlockType From Name "From4" SID "9502" Position [600, 425, 795, 445] ShowName off CloseFcn "tagdialog Close" GotoTag "RX_GLOBAL_RESET" TagVisibility "global" } Block { BlockType From Name "From5" SID "18142" Position [45, 895, 240, 915] ShowName off CloseFcn "tagdialog Close" GotoTag "DSSS_RX_RUNNING" TagVisibility "global" } Block { BlockType Reference Name "Gateway Out1" SID "7395" Ports [1, 1] Position [1300, 134, 1335, 146] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "RL Active" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "7396" Ports [1, 1] Position [1300, 159, 1335, 171] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "CCA Busy" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "7397" Ports [1, 1] Position [1300, 109, 1335, 121] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Start" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Goto Name "Goto" SID "7398" Position [1265, 574, 1410, 596] ZOrder -10 ShowName off GotoTag "RX_CCA_BUSY" TagVisibility "global" } Block { BlockType Goto Name "Goto1" SID "7399" Position [880, 309, 1090, 331] ZOrder -10 ShowName off GotoTag "RX_END_OFDM_LAST_SAMP" TagVisibility "global" } Block { BlockType Goto Name "Goto2" SID "7400" Position [1245, 404, 1470, 426] ZOrder -10 ShowName off GotoTag "RX_PHY_RATE_LENGTH_ACTIVE" TagVisibility "global" } Block { BlockType Reference Name "Logical1" SID "7401" Ports [2, 1] Position [250, 410, 275, 445] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "25,35,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 35 35 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 35 35 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[20" ".33 20.33 23.33 20.33 23.33 23.33 23.33 20.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[17.33 17.33 " "20.33 20.33 17.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[14.33 14.33 17.33 17.33 14.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[11.33 11.33 14.33 11.33 14.33 14.33 11.33 ]," "[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n" "\ncolor('black');disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "7402" Ports [4, 1] Position [1115, 524, 1150, 646] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "4" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,122,4,1,white,blue,0,4f3eee2e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 122 122 0 ],[0.77" " 0.82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 122 122 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[6" "6.55 66.55 71.55 66.55 71.55 71.55 71.55 66.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[61.55 61.5" "5 66.55 66.55 61.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[56.55 56.55 61.55 61.55 56" ".55 ],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[51.55 51.55 56.55 51.55 56.55 56.55 51.55 ]" ",[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n" "\n\n\n\ncolor('black');disp('or');\nfprintf('','COMMENT: end icon text');" Port { PortNumber 1 Name "CCA_BUSY" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Logical3" SID "7403" Ports [2, 1] Position [525, 315, 550, 350] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "25,35,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 35 35 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 35 35 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[20" ".33 20.33 23.33 20.33 23.33 23.33 23.33 20.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[17.33 17.33 " "20.33 20.33 17.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[14.33 14.33 17.33 17.33 14.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[11.33 11.33 14.33 11.33 14.33 14.33 11.33 ]," "[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n" "\ncolor('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical4" SID "7404" Ports [2, 1] Position [735, 960, 760, 995] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "25,35,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 35 35 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 35 35 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[20" ".33 20.33 23.33 20.33 23.33 23.33 23.33 20.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[17.33 17.33 " "20.33 20.33 17.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[14.33 14.33 17.33 17.33 14.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[11.33 11.33 14.33 11.33 14.33 14.33 11.33 ]," "[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n" "\ncolor('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical5" SID "9501" Ports [2, 1] Position [885, 410, 910, 445] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "25,35,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 35 35 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 35 35 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[20" ".33 20.33 23.33 20.33 23.33 23.33 23.33 20.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[17.33 17.33 " "20.33 20.33 17.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[14.33 14.33 17.33 17.33 14.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[11.33 11.33 14.33 11.33 14.33 14.33 11.33 ]," "[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n" "\ncolor('black');disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical6" SID "18129" Ports [2, 1] Position [420, 925, 445, 960] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "25,35,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 35 35 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 35 35 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[20" ".33 20.33 23.33 20.33 23.33 23.33 23.33 20.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[17.33 17.33 " "20.33 20.33 17.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[14.33 14.33 17.33 17.33 14.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[11.33 11.33 14.33 11.33 14.33 14.33 11.33 ]," "[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n" "\ncolor('black');disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Scope Name "PHY CCA" SID "7405" Ports [7] Position [1420, 97, 1465, 283] ZOrder -3 Floating off Location [838, 66, 1829, 1134] Open off NumInputPorts "7" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" } List { ListType ScopeGraphics FigureColor "[0.5 0.5 0.5]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "10000" YMin "-1~-1~0.95~-70~0~0~-0.25" YMax "1~1~1.05~80~1~60000~0.3" SaveName "ScopeData31" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType SubSystem Name "PHY CCA Logic" SID "7406" Ports [4, 1] Position [870, 566, 930, 629] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "PHY CCA Logic" Location [-1678, 70, -2, 1030] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "125" Block { BlockType Inport Name "Det A" SID "7407" Position [370, 353, 400, 367] IconDisplay "Port number" } Block { BlockType Inport Name "Det B" SID "7408" Position [370, 418, 400, 432] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "Det C" SID "7409" Position [370, 483, 400, 497] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "Det D" SID "7410" Position [370, 548, 400, 562] Port "4" IconDisplay "Port number" } Block { BlockType From Name "From1" SID "7411" Position [445, 385, 645, 405] ShowName off CloseFcn "tagdialog Close" GotoTag "regRx_pktDetEn_RFB" TagVisibility "global" } Block { BlockType From Name "From2" SID "7412" Position [445, 450, 645, 470] ShowName off CloseFcn "tagdialog Close" GotoTag "regRx_pktDetEn_RFC" TagVisibility "global" } Block { BlockType From Name "From3" SID "7413" Position [445, 515, 645, 535] ShowName off CloseFcn "tagdialog Close" GotoTag "regRx_pktDetEn_RFD" TagVisibility "global" } Block { BlockType From Name "From4" SID "7414" Position [385, 635, 585, 655] ShowName off CloseFcn "tagdialog Close" GotoTag "regRx_pktDetEn_RFA" TagVisibility "global" } Block { BlockType From Name "From5" SID "7415" Position [385, 665, 585, 685] ShowName off CloseFcn "tagdialog Close" GotoTag "regRx_pktDetEn_RFB" TagVisibility "global" } Block { BlockType From Name "From6" SID "7416" Position [445, 320, 645, 340] ShowName off CloseFcn "tagdialog Close" GotoTag "regRx_pktDetEn_RFA" TagVisibility "global" } Block { BlockType From Name "From7" SID "7417" Position [385, 695, 585, 715] ShowName off CloseFcn "tagdialog Close" GotoTag "regRx_pktDetEn_RFC" TagVisibility "global" } Block { BlockType From Name "From8" SID "7418" Position [385, 725, 585, 745] ShowName off CloseFcn "tagdialog Close" GotoTag "regRx_pktDetEn_RFD" TagVisibility "global" } Block { BlockType From Name "From9" SID "7419" Position [445, 265, 645, 285] ShowName off CloseFcn "tagdialog Close" GotoTag "regRx_phyCCA_Mode_Sel" TagVisibility "global" } Block { BlockType Reference Name "Inverter" SID "7420" Ports [1, 1] Position [660, 636, 695, 654] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "35,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 18 18 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[11.22 11.22" " 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[9.22 9.22 11.22 11.22 9" ".22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch" "([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfpr" "intf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter1" SID "7421" Ports [1, 1] Position [660, 666, 695, 684] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "35,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 18 18 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[11.22 11.22" " 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[9.22 9.22 11.22 11.22 9" ".22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch" "([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfpr" "intf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter2" SID "7422" Ports [1, 1] Position [660, 696, 695, 714] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "35,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 18 18 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[11.22 11.22" " 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[9.22 9.22 11.22 11.22 9" ".22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch" "([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfpr" "intf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter3" SID "7423" Ports [1, 1] Position [660, 726, 695, 744] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "35,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 18 18 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[11.22 11.22" " 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[9.22 9.22 11.22 11.22 9" ".22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch" "([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfpr" "intf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical" SID "7424" Ports [2, 1] Position [680, 316, 715, 374] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,58,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 58 58 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 58 58 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[34.55 34.55 39." "55 34.55 39.55 39.55 39.55 34.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[29.55 29.55 34.55 34.55 29." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[24.55 24.55 29.55 29.55 24.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[19.55 19.55 24.55 19.55 24.55 24.55 19.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('a" "nd');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "7425" Ports [4, 1] Position [925, 332, 960, 448] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "4" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,116,4,1,white,blue,0,4f3eee2e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 116 116 0 ],[0.77 0.82 0" ".91 ]);\nplot([0 35 35 0 0 ],[0 0 116 116 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[63.55 63.55" " 68.55 63.55 68.55 68.55 68.55 63.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[58.55 58.55 63.55 63.55" " 58.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[53.55 53.55 58.55 58.55 53.55 ],[1 1 1 ]);" "\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[48.55 48.55 53.55 48.55 53.55 53.55 48.55 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\n\ncolor('black')" ";disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical10" SID "7426" Ports [4, 1] Position [820, 745, 855, 795] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "4" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,50,4,1,white,blue,0,4f3eee2e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 50 50 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 50 50 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[30.55 30.55 35." "55 30.55 35.55 35.55 35.55 30.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[25.55 25.55 30.55 30.55 25." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[20.55 20.55 25.55 25.55 20.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[15.55 15.55 20.55 15.55 20.55 20.55 15.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\n\ncolor('black');dis" "p('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "7427" Ports [2, 1] Position [680, 381, 715, 439] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,58,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 58 58 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 58 58 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[34.55 34.55 39." "55 34.55 39.55 39.55 39.55 34.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[29.55 29.55 34.55 34.55 29." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[24.55 24.55 29.55 29.55 24.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[19.55 19.55 24.55 19.55 24.55 24.55 19.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('a" "nd');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical3" SID "7428" Ports [2, 1] Position [680, 446, 715, 504] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,58,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 58 58 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 58 58 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[34.55 34.55 39." "55 34.55 39.55 39.55 39.55 34.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[29.55 29.55 34.55 34.55 29." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[24.55 24.55 29.55 29.55 24.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[19.55 19.55 24.55 19.55 24.55 24.55 19.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('a" "nd');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical4" SID "7429" Ports [2, 1] Position [680, 511, 715, 569] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,58,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 58 58 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 58 58 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[34.55 34.55 39." "55 34.55 39.55 39.55 39.55 34.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[29.55 29.55 34.55 34.55 29." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[24.55 24.55 29.55 29.55 24.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[19.55 19.55 24.55 19.55 24.55 24.55 19.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('a" "nd');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical5" SID "7430" Ports [5, 1] Position [925, 619, 960, 781] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "5" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,162,5,1,white,blue,0,2904cdfe,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 162 162 0 ],[0.77 0.82 0" ".91 ]);\nplot([0 35 35 0 0 ],[0 0 162 162 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[86.55 86.55" " 91.55 86.55 91.55 91.55 91.55 86.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[81.55 81.55 86.55 86.55" " 81.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[76.55 76.55 81.55 81.55 76.55 ],[1 1 1 ]);" "\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[71.55 71.55 76.55 71.55 76.55 76.55 71.55 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\n\n\ncolor('black" "');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical6" SID "7431" Ports [2, 1] Position [820, 622, 855, 653] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,31,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 31 31 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 31 31 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[19.44 19.44 23.4" "4 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[15.44 15.44 19.44 19.44 15.44 ]," "[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([12.1" " 25.88 21.88 17.88 13.88 8.1 12.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('or');\nfprintf('" "','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical7" SID "7432" Ports [2, 1] Position [820, 652, 855, 683] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,31,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 31 31 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 31 31 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[19.44 19.44 23.4" "4 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[15.44 15.44 19.44 19.44 15.44 ]," "[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([12.1" " 25.88 21.88 17.88 13.88 8.1 12.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('or');\nfprintf('" "','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical8" SID "7433" Ports [2, 1] Position [820, 682, 855, 713] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,31,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 31 31 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 31 31 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[19.44 19.44 23.4" "4 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[15.44 15.44 19.44 19.44 15.44 ]," "[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([12.1" " 25.88 21.88 17.88 13.88 8.1 12.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('or');\nfprintf('" "','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical9" SID "7434" Ports [2, 1] Position [820, 712, 855, 743] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,31,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 31 31 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 31 31 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[19.44 19.44 23.4" "4 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[15.44 15.44 19.44 19.44 15.44 ]," "[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([12.1" " 25.88 21.88 17.88 13.88 8.1 12.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('or');\nfprintf('" "','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux" SID "7435" Ports [3, 1] Position [1020, 302, 1055, 478] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "35,176,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 25.1429 150.857 176 0 ],[0" ".77 0.82 0.91 ]);\nplot([0 35 35 0 0 ],[0 25.1429 150.857 176 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 " "5.875 ],[93.55 93.55 98.55 93.55 98.55 98.55 98.55 93.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[88." "55 88.55 93.55 93.55 88.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[83.55 83.55 88.55 88.5" "5 83.55 ],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[78.55 78.55 83.55 78.55 83.55 83.55 78.55 " "],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolo" "r('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('in" "put',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "BUSY" SID "7436" Position [1105, 382, 1135, 398] NamePlacement "alternate" IconDisplay "Port number" } Line { SrcBlock "From6" SrcPort 1 DstBlock "Logical" DstPort 1 } Line { SrcBlock "Logical" SrcPort 1 Points [50, 0] Branch { DstBlock "Logical1" DstPort 1 } Branch { Points [0, 285] DstBlock "Logical6" DstPort 1 } } Line { SrcBlock "Logical2" SrcPort 1 Points [45, 0] Branch { Points [25, 0; 0, -35] DstBlock "Logical1" DstPort 2 } Branch { Points [0, 250] DstBlock "Logical7" DstPort 1 } } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Mux" DstPort 2 } Line { SrcBlock "Det A" SrcPort 1 DstBlock "Logical" DstPort 2 } Line { SrcBlock "Det B" SrcPort 1 DstBlock "Logical2" DstPort 2 } Line { SrcBlock "From1" SrcPort 1 DstBlock "Logical2" DstPort 1 } Line { SrcBlock "Det C" SrcPort 1 DstBlock "Logical3" DstPort 2 } Line { SrcBlock "Det D" SrcPort 1 DstBlock "Logical4" DstPort 2 } Line { SrcBlock "From2" SrcPort 1 DstBlock "Logical3" DstPort 1 } Line { SrcBlock "From3" SrcPort 1 DstBlock "Logical4" DstPort 1 } Line { SrcBlock "Logical3" SrcPort 1 Points [40, 0] Branch { Points [40, 0; 0, -70] DstBlock "Logical1" DstPort 3 } Branch { Points [0, 215] DstBlock "Logical8" DstPort 1 } } Line { SrcBlock "Logical4" SrcPort 1 Points [35, 0] Branch { Points [50, 0; 0, -105] DstBlock "Logical1" DstPort 4 } Branch { Points [0, 180] DstBlock "Logical9" DstPort 1 } } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical6" DstPort 2 } Line { SrcBlock "From4" SrcPort 1 Points [50, 0] Branch { DstBlock "Inverter" DstPort 1 } Branch { Points [0, 110] DstBlock "Logical10" DstPort 1 } } Line { SrcBlock "Logical6" SrcPort 1 DstBlock "Logical5" DstPort 1 } Line { SrcBlock "Logical7" SrcPort 1 DstBlock "Logical5" DstPort 2 } Line { SrcBlock "From5" SrcPort 1 Points [45, 0] Branch { DstBlock "Inverter1" DstPort 1 } Branch { Points [0, 90] DstBlock "Logical10" DstPort 2 } } Line { SrcBlock "Inverter1" SrcPort 1 DstBlock "Logical7" DstPort 2 } Line { SrcBlock "Logical8" SrcPort 1 DstBlock "Logical5" DstPort 3 } Line { SrcBlock "From7" SrcPort 1 Points [40, 0] Branch { DstBlock "Inverter2" DstPort 1 } Branch { Points [0, 70] DstBlock "Logical10" DstPort 3 } } Line { SrcBlock "Inverter2" SrcPort 1 DstBlock "Logical8" DstPort 2 } Line { SrcBlock "From8" SrcPort 1 Points [35, 0] Branch { DstBlock "Inverter3" DstPort 1 } Branch { Points [0, 50] DstBlock "Logical10" DstPort 4 } } Line { SrcBlock "Inverter3" SrcPort 1 DstBlock "Logical9" DstPort 2 } Line { SrcBlock "Logical9" SrcPort 1 DstBlock "Logical5" DstPort 4 } Line { SrcBlock "Logical10" SrcPort 1 Points [0, -10] DstBlock "Logical5" DstPort 5 } Line { SrcBlock "Logical5" SrcPort 1 Points [15, 0; 0, -250] DstBlock "Mux" DstPort 3 } Line { SrcBlock "Mux" SrcPort 1 DstBlock "BUSY" DstPort 1 } Line { SrcBlock "From9" SrcPort 1 Points [325, 0; 0, 55] DstBlock "Mux" DstPort 1 } Annotation { Name "Two modes for physical carrier sensing:\nMode 0: Any enabled antenna can assert BUSY if its RSSI exceeds" " the threshold\nMode 1: BUSY only if *all* enabled antennas exceed the threshold" Position [1033, 526] HorizontalAlignment "left" } Annotation { Name "This 4-in OR deasserts BUSY\nif all antennas are disabled." Position [837, 816] } } } Block { BlockType SubSystem Name "Posedge" SID "18130" Ports [1, 1] Position [320, 942, 360, 958] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Posedge" Location [88, 301, 2330, 1301] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "18131" Position [200, 253, 230, 267] IconDisplay "Port number" } Block { BlockType Reference Name "Delay" SID "18132" Ports [1, 1] Position [425, 153, 460, 177] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. If r" "egister retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[15.33 15" ".33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.33 12.33 15.33" " 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 " "1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');" "disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "18133" Ports [1, 1] Position [490, 156, 515, 174] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "18134" Ports [2, 1] Position [540, 151, 585, 204] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,53,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 53 53 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 53 53 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[32.66 32.66 3" "8.66 32.66 38.66 38.66 38.66 32.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[26.66 26.66 32.66 32.66 26" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[20.66 20.66 26.66 26.66 20.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[14.66 14.66 20.66 14.66 20.66 20.66 14.66 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('" "and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "18135" Position [610, 173, 640, 187] IconDisplay "Port number" } Line { SrcBlock "D" SrcPort 1 Points [150, 0; 0, -70] Branch { DstBlock "Logical1" DstPort 2 } Branch { Points [0, -25] DstBlock "Delay" DstPort 1 } } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Delay" SrcPort 1 DstBlock "Inverter" DstPort 1 } Annotation { Name "Rising Edge Detection" Position [500, 112] } } } Block { BlockType SubSystem Name "Posedge1" SID "18136" Ports [1, 1] Position [320, 897, 360, 913] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Posedge1" Location [88, 301, 2330, 1301] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "18137" Position [200, 253, 230, 267] IconDisplay "Port number" } Block { BlockType Reference Name "Delay" SID "18138" Ports [1, 1] Position [425, 153, 460, 177] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. If r" "egister retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[15.33 15" ".33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.33 12.33 15.33" " 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 " "1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');" "disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "18139" Ports [1, 1] Position [490, 156, 515, 174] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "18140" Ports [2, 1] Position [540, 151, 585, 204] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,53,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 53 53 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 53 53 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[32.66 32.66 3" "8.66 32.66 38.66 38.66 38.66 32.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[26.66 26.66 32.66 32.66 26" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[20.66 20.66 26.66 26.66 20.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[14.66 14.66 20.66 14.66 20.66 20.66 14.66 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('" "and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "18141" Position [610, 173, 640, 187] IconDisplay "Port number" } Line { SrcBlock "Delay" SrcPort 1 DstBlock "Inverter" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "D" SrcPort 1 Points [150, 0; 0, -70] Branch { Points [0, -25] DstBlock "Delay" DstPort 1 } Branch { DstBlock "Logical1" DstPort 2 } } Annotation { Name "Rising Edge Detection" Position [500, 112] } } } Block { BlockType SubSystem Name "Rate-Length\nBUSY" SID "10779" Ports [2, 1] Position [645, 289, 755, 351] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Rate-Length\nBUSY" Location [-1678, 227, -18, 1171] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "124" Block { BlockType Inport Name "IQ Valid" SID "10780" Position [195, 258, 225, 272] IconDisplay "Port number" } Block { BlockType Inport Name "Start" SID "10781" Position [195, 243, 225, 257] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType SubSystem Name "Bits" SID "10782" Ports [2, 1] Position [485, 322, 575, 373] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Bits" Location [242, 606, 1407, 930] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Sym Inc" SID "10783" Position [345, 478, 375, 492] IconDisplay "Port number" } Block { BlockType Inport Name "Rst" SID "10784" Position [350, 522, 380, 538] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Accumulator" SID "10785" Ports [3, 1] Position [900, 371, 960, 459] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Accumulator" SourceType "Xilinx Accumulator Block" infoedit "Adder or subtracter-based accumulator. Output type and binary point position match the input.
Hardware notes: When \"Reinitialize with input 'b' on reset\" is selected, the accumulator is forced to ru" "n at the system rate even if the input 'b' is running at a slower rate." operation "Add" n_bits "ceil(log2(MAX_NUM_BYTES*8))" overflow "Wrap" scale "1" rst on infoeditControl "reset for floating point data type must be asserted for a minimum of 2 cycles" hasbypass on en on latency "0" dbl_ovrd off msb_inp "100" msb "100" lsb "-100" use_behavioral_HDL on implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "accum" sg_icon_stat "60,88,3,1,white,blue,0,ee9eb47a,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 88 88 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 88 88 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[52.88 52" ".88 60.88 52.88 60.88 60.88 60.88 52.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[44.88 44.88 52.88 52." "88 44.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[36.88 36.88 44.88 44.88 36.88 ],[1 1 1 ]" ");\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 28.88 36.88 36.88 28.88 ],[0.931 0.946 0." "973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port" "_label('input',1,'b');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'en');\n" "color('black');port_label('output',1,'\\bf+=b','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From1" SID "10822" Position [60, 390, 260, 410] ShowName off CloseFcn "tagdialog Close" GotoTag "OFDM_RX_SIGNAL_VALID" TagVisibility "global" } Block { BlockType From Name "From2" SID "10918" Position [215, 295, 415, 315] ShowName off CloseFcn "tagdialog Close" GotoTag "OFDM_RX_SIGNAL_LENGTH" TagVisibility "global" } Block { BlockType From Name "From5" SID "10792" Position [215, 360, 415, 380] ShowName off CloseFcn "tagdialog Close" GotoTag "OFDM_RX_DATA_N_DBPS_1" TagVisibility "global" } Block { BlockType Reference Name "Gateway Out1" SID "10794" Ports [1, 1] Position [1305, 109, 1340, 121] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Length (Bytes)" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "10795" Ports [1, 1] Position [1305, 134, 1340, 146] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "N_DBPS" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "10796" Ports [1, 1] Position [1305, 184, 1340, 196] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Bit Accum" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "10797" Ports [1, 1] Position [1305, 209, 1340, 221] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Done" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "10798" Ports [1, 1] Position [1305, 234, 1340, 246] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Accum Inc En" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "10799" Ports [1, 1] Position [1305, 159, 1340, 171] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "SIGNAL Valid" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "10800" Ports [1, 1] Position [1305, 259, 1340, 271] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Reset" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Logical4" SID "10802" Ports [2, 1] Position [825, 427, 860, 458] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,31,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 31 31 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 31 31 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[19.44 19.4" "4 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[15.44 15.44 19.44 19.44 " "15.44 ],[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\np" "atch([12.1 25.88 21.88 17.88 13.88 8.1 12.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('an" "d');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical5" SID "10803" Ports [2, 1] Position [490, 522, 525, 553] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,31,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 31 31 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 31 31 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[19.44 19.4" "4 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[15.44 15.44 19.44 19.44 " "15.44 ],[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\np" "atch([12.1 25.88 21.88 17.88 13.88 8.1 12.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('or" "');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Scope Name "PHY Rx Busy - Bits" SID "10806" Ports [7] Position [1460, 97, 1505, 283] ZOrder -3 Floating off Location [85, 827, 1577, 1583] Open off NumInputPorts "7" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" } List { ListType ScopeGraphics FigureColor "[0.5 0.5 0.5]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "20000" YMin "0~20~0~0~0~0~0" YMax "120~50~1~1000~1~1~1" SaveName "ScopeData23" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType SubSystem Name "Posedge" SID "10827" Ports [1, 1] Position [325, 392, 365, 408] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Posedge" Location [88, 301, 2330, 1301] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "10828" Position [200, 253, 230, 267] IconDisplay "Port number" } Block { BlockType Reference Name "Delay" SID "10829" Ports [1, 1] Position [425, 153, 460, 177] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. " "If register retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[15" ".33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.33 12." "33 15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 12.33 " "9.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\nc" "olor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "10830" Ports [1, 1] Position [490, 156, 515, 174] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "10831" Ports [2, 1] Position [540, 151, 585, 204] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,53,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 53 53 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 53 53 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[32.66 3" "2.66 38.66 32.66 38.66 38.66 38.66 32.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[26.66 26.66 32.66 " "32.66 26.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[20.66 20.66 26.66 26.66 20.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[14.66 14.66 20.66 14.66 20.66 20.66 14.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('" "black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "10832" Position [610, 173, 640, 187] IconDisplay "Port number" } Line { SrcBlock "D" SrcPort 1 Points [150, 0; 0, -70] Branch { DstBlock "Logical1" DstPort 2 } Branch { Points [0, -25] DstBlock "Delay" DstPort 1 } } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Delay" SrcPort 1 DstBlock "Inverter" DstPort 1 } Annotation { Name "Rising Edge Detection" Position [500, 112] } } } Block { BlockType Reference Name "Register" SID "10807" Ports [3, 1] Position [480, 361, 535, 409] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "24" rst on en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "55,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 48 48 0 ]);\npatch([13.65 22.32 28.32 34.32 40.32 28.32 19.65 13.65 ],[30.66" " 30.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([19.65 28.32 22.32 13.65 19.65 ],[24.66 24.66 30." "66 30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([13.65 22.32 28.32 19.65 13.65 ],[18.66 18.66 24.66 24.66 18.66 ]" ",[1 1 1 ]);\npatch([19.65 40.32 34.32 28.32 22.32 13.65 19.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('inpu" "t',3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf(" "'','COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "10808" Ports [3, 1] Position [480, 296, 535, 344] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "9" rst on en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "55,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 48 48 0 ]);\npatch([13.65 22.32 28.32 34.32 40.32 28.32 19.65 13.65 ],[30.66" " 30.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([19.65 28.32 22.32 13.65 19.65 ],[24.66 24.66 30." "66 30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([13.65 22.32 28.32 19.65 13.65 ],[18.66 18.66 24.66 24.66 18.66 ]" ",[1 1 1 ]);\npatch([19.65 40.32 34.32 28.32 22.32 13.65 19.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('inpu" "t',3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf(" "'','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational2" SID "10810" Ports [2, 1] Position [1070, 305, 1105, 365] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "15,18,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11.22 " "13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 9.22 " "],[0.931 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([4.55 " "11.44 9.44 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "10815" Ports [1, 1] Position [230, 86, 255, 104] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('outpu" "t',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "10816" Ports [1, 1] Position [230, 101, 255, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('outpu" "t',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "10817" Ports [3, 1] Position [300, 71, 345, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "10818" Position [370, 88, 400, 102] IconDisplay "Port number" } Line { SrcBlock "Convert2" SrcPort 1 DstBlock "Register2" DstPort 3 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "S" SrcPort 1 DstBlock "Convert2" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Register2" DstPort 1 } } } Block { BlockType SubSystem Name "Target Num Bits" SID "10921" Ports [1, 1] Position [625, 300, 745, 340] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Target Num Bits" Location [767, 298, 1277, 439] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "SIG.LENGTH" SID "10923" Position [245, 288, 275, 302] IconDisplay "Port number" } Block { BlockType Reference Name "AddSub" SID "10786" Ports [2, 1] Position [625, 251, 685, 309] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Unsigned" n_bits "3+ceil(log2(MAX_NUM_BYTES))" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL off hw_selection "Fabric" pipelined off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" sg_icon_stat "60,58,2,1,white,blue,0,e139daf6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 58 58 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 58 58 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[37.88 37" ".88 45.88 37.88 45.88 45.88 45.88 37.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[29.88 29.88 37.88 37." "88 29.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[21.88 21.88 29.88 29.88 21.88 ],[1 1 1 ]" ");\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[13.88 13.88 21.88 13.88 21.88 21.88 13.88 ],[0.931 0.946 0." "973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port" "_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bf{a " "+ b}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant1" SID "10787" Ports [0, 1] Position [525, 255, 565, 275] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "24+16+6" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "6" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "40,20,0,1,white,blue,0,96aa3a5d,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 20 20 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 20 20 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[12.22" " 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[10.22 10.22 12." "22 12.22 10.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1" " 1 1 ]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');po" "rt_label('output',1,'46');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert" SID "10788" Ports [1, 1] Position [345, 286, 380, 304] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3+ceil(log2(MAX_NUM_BYTES))" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "35,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 18 18 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Shift" SID "10819" Ports [1, 1] Position [450, 278, 505, 312] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Shift" SourceType "Xilinx Binary Shift Operator Block" infoedit "Hardware notes: In hardware this block costs nothing if full output precision is used." shift_dir "Left" shift_bits "3" en off latency "0" precision "Full" arith_type "Signed (2's comp)" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "shift" sg_icon_stat "55,34,1,1,white,blue,0,2cc77cbe,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 34 34 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 34 34 0 ]);\npatch([18.1 23.88 27.88 31.88 35.88 27.88 22.1 18.1 ],[21.44 21" ".44 25.44 21.44 25.44 25.44 25.44 21.44 ],[1 1 1 ]);\npatch([22.1 27.88 23.88 18.1 22.1 ],[17.44 17.44 21.44 21." "44 17.44 ],[0.931 0.946 0.973 ]);\npatch([18.1 23.88 27.88 22.1 18.1 ],[13.44 13.44 17.44 17.44 13.44 ],[1 1 1 ]" ");\npatch([22.1 35.88 31.88 27.88 23.88 18.1 22.1 ],[9.44 9.44 13.44 9.44 13.44 13.44 9.44 ],[0.931 0.946 0.973 " "]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp" "('\\bf{X << 3}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Total Bits" SID "10922" Position [775, 273, 805, 287] IconDisplay "Port number" } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "AddSub" DstPort 1 } Line { SrcBlock "Shift" SrcPort 1 DstBlock "AddSub" DstPort 2 } Line { SrcBlock "Convert" SrcPort 1 DstBlock "Shift" DstPort 1 } Line { SrcBlock "SIG.LENGTH" SrcPort 1 DstBlock "Convert" DstPort 1 } Line { SrcBlock "AddSub" SrcPort 1 DstBlock "Total Bits" DstPort 1 } Annotation { Name "24: SIGNAL/L-SIG\n16:SERVICE bits\n6: TAIL bits" Position [530, 223] HorizontalAlignment "left" } } } Block { BlockType Outport Name "Done" SID "10837" Position [1175, 328, 1205, 342] IconDisplay "Port number" } Line { SrcBlock "From5" SrcPort 1 DstBlock "Register" DstPort 1 } Line { SrcBlock "S-R Latch3" SrcPort 1 DstBlock "Logical4" DstPort 1 } Line { SrcBlock "Register" SrcPort 1 Points [65, 0] Branch { DstBlock "Accumulator" DstPort 1 } Branch { Points [0, -245] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "Logical4" SrcPort 1 DstBlock "Accumulator" DstPort 3 } Line { SrcBlock "Accumulator" SrcPort 1 Points [60, 0; 0, -65] Branch { DstBlock "Relational2" DstPort 2 } Branch { Points [0, -160] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "Register1" SrcPort 1 Points [60, 0] Branch { Points [0, -205] DstBlock "Gateway Out1" DstPort 1 } Branch { Labels [0, 0] DstBlock "Target Num Bits" DstPort 1 } } Line { SrcBlock "Target Num Bits" SrcPort 1 DstBlock "Relational2" DstPort 1 } Line { SrcBlock "Logical5" SrcPort 1 Points [35, 0; 0, -100] Branch { Points [0, -25] DstBlock "Accumulator" DstPort 2 } Branch { DstBlock "S-R Latch3" DstPort 2 } Branch { Points [-120, 0; 0, -55] Branch { DstBlock "Register" DstPort 2 } Branch { Points [0, -65] DstBlock "Register1" DstPort 2 } } } Line { SrcBlock "Rst" SrcPort 1 Points [30, 0] Branch { DstBlock "Logical5" DstPort 1 } Branch { Points [0, 55; 840, 0; 0, -320] DstBlock "Gateway Out8" DstPort 1 } } Line { SrcBlock "Relational2" SrcPort 1 Points [40, 0] Branch { DstBlock "Done" DstPort 1 } Branch { Points [0, 245; -690, 0; 0, -35] DstBlock "Logical5" DstPort 2 } Branch { Points [0, -120] DstBlock "Gateway Out4" DstPort 1 } } Line { Name "Reset" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 DstBlock "PHY Rx Busy - Bits" DstPort 7 } Line { Name "Length (Bytes)" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 DstBlock "PHY Rx Busy - Bits" DstPort 1 } Line { Name "N_DBPS" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 DstBlock "PHY Rx Busy - Bits" DstPort 2 } Line { Name "Bit Accum" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 DstBlock "PHY Rx Busy - Bits" DstPort 4 } Line { Name "Done" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 DstBlock "PHY Rx Busy - Bits" DstPort 5 } Line { Name "Accum Inc En" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 DstBlock "PHY Rx Busy - Bits" DstPort 6 } Line { SrcBlock "From2" SrcPort 1 DstBlock "Register1" DstPort 1 } Line { SrcBlock "Posedge" SrcPort 1 Points [85, 0] Branch { Points [0, 0] Branch { DstBlock "Register" DstPort 3 } Branch { Points [0, 25] DstBlock "S-R Latch3" DstPort 1 } } Branch { Points [0, -65] Branch { DstBlock "Register1" DstPort 3 } Branch { Points [0, -170] DstBlock "Gateway Out6" DstPort 1 } } } Line { SrcBlock "Sym Inc" SrcPort 1 Points [400, 0; 0, -35] Branch { DstBlock "Logical4" DstPort 2 } Branch { Points [0, -210] DstBlock "Gateway Out5" DstPort 1 } } Line { Name "SIGNAL Valid" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 DstBlock "PHY Rx Busy - Bits" DstPort 3 } Line { SrcBlock "From1" SrcPort 1 DstBlock "Posedge" DstPort 1 } } } Block { BlockType BusCreator Name "Bus Creator" SID "10916" Ports [2, 1] Position [1165, 28, 1170, 57] ZOrder -2 ShowName off Inputs "2" DisplayOption "bar" } Block { BlockType Reference Name "Delay" SID "11299" Ports [1, 1] Position [305, 240, 325, 260] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "20,20,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 20 20 0 0 ],[0 0 20 20 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[12.22 12.22 14." "22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[10.22 10.22 12.22 12.22 10.22 ]" ",[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatch([7.55 " "14.44 12.44 10.44 8.44 5.55 7.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-1}','texmode','on'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Extension" SID "10838" Ports [3, 1] Position [485, 404, 575, 456] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Extension" Location [1067, 1033, 1747, 1237] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "124" Block { BlockType Inport Name "Bits Done" SID "10839" Position [400, 358, 430, 372] IconDisplay "Port number" } Block { BlockType Inport Name "IQ Valid" SID "10840" Position [400, 393, 430, 407] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "Rst" SID "10841" Position [400, 323, 430, 337] Port "3" IconDisplay "Port number" } Block { BlockType Reference Name "Counter1" SID "10848" Ports [2, 1] Position [790, 306, 850, 384] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited count" "er is implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "Inf" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "11" bin_pt "0" load_pin off rst on en on explicit_period "off" period "1" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "counter" sg_icon_stat "60,78,2,1,white,blue,0,ae3608d6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 78 78 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 78 78 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[47.88 47" ".88 55.88 47.88 55.88 55.88 55.88 47.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[39.88 39.88 47.88 47." "88 39.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[31.88 31.88 39.88 39.88 31.88 ],[1 1 1 ]" ");\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[23.88 23.88 31.88 23.88 31.88 31.88 23.88 ],[0.931 0.946 0." "973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port" "_label('input',1,'rst');\ncolor('black');port_label('input',2,'en');\n\ncolor('black');disp('{\\fontsize{14}\\bf" "++}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Display Name "Display" SID "10849" Ports [1] Position [970, 454, 1065, 476] ZOrder -1 ShowName off Decimation "1" Lockdown off } Block { BlockType From Name "From2" SID "10851" Position [585, 430, 780, 450] ShowName off CloseFcn "tagdialog Close" GotoTag "regRx_CCA_PostRx_Extension" TagVisibility "global" } Block { BlockType Reference Name "Gateway Out1" SID "10854" Ports [1, 1] Position [1245, 69, 1280, 81] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out2" SID "10855" Ports [1, 1] Position [1245, 94, 1280, 106] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out3" SID "10856" Ports [1, 1] Position [1245, 119, 1280, 131] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out4" SID "10857" Ports [1, 1] Position [1245, 44, 1280, 56] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out5" SID "10858" Ports [1, 1] Position [1245, 144, 1280, 156] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out6" SID "10859" Ports [1, 1] Position [875, 459, 910, 471] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "10860" Ports [2, 1] Position [690, 364, 720, 411] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "30,47,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 47 47 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 47 47 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[27.44 27.4" "4 31.44 27.44 31.44 31.44 31.44 27.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[23.44 23.44 27.44 27.44 " "23.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[19.44 19.44 23.44 23.44 19.44 ],[1 1 1 ]);\np" "atch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 15.44 19.44 19.44 15.44 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp" "('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "10861" Ports [2, 1] Position [530, 307, 565, 338] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,31,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 31 31 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 31 31 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[19.44 19.4" "4 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[15.44 15.44 19.44 19.44 " "15.44 ],[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\np" "atch([12.1 25.88 21.88 17.88 13.88 8.1 12.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('or" "');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical3" SID "10862" Ports [2, 1] Position [1095, 244, 1125, 291] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "30,47,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 47 47 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 47 47 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[27.44 27.4" "4 31.44 27.44 31.44 31.44 31.44 27.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[23.44 23.44 27.44 27.44 " "23.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[19.44 19.44 23.44 23.44 19.44 ],[1 1 1 ]);\np" "atch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 15.44 19.44 19.44 15.44 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp" "('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Scope Name "PHY Rx Busy - Extension" SID "10865" Ports [7] Position [1330, 32, 1375, 218] ZOrder -3 Floating off Location [6, 45, 1686, 1049] Open off NumInputPorts "7" ZoomMode "yonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" } List { ListType ScopeGraphics FigureColor "[0.5 0.5 0.5]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "10000" YMin "0~-100~-100~-70~0~0~-0.25" YMax "80~75~75~80~1~60000~0.3" SaveName "ScopeData33" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType Reference Name "Relational3" SID "10867" Ports [2, 1] Position [980, 330, 1015, 390] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a>=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,60,2,1,white,blue,0,6218dc92,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 60 60 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 60 60 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[35.55 35." "55 40.55 35.55 40.55 40.55 40.55 35.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[30.55 30.55 35.55 3" "5.55 30.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[25.55 25.55 30.55 30.55 25.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[20.55 20.55 25.55 20.55 25.55 25.55 20.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bfa \\geq b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "S-R Latch1" SID "10868" Ports [2, 1] Position [605, 358, 640, 387] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "S-R Latch1" Location [351, 366, 2001, 1172] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "10869" Position [140, 103, 170, 117] IconDisplay "Port number" } Block { BlockType Inport Name "R" SID "10870" Position [140, 88, 170, 102] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "10871" Ports [0, 1] Position [195, 71, 210, 89] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "15,18,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11.22 " "13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 9.22 " "],[0.931 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([4.55 " "11.44 9.44 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "10872" Ports [1, 1] Position [230, 86, 255, 104] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('outpu" "t',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "10873" Ports [1, 1] Position [230, 101, 255, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('outpu" "t',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "10874" Ports [3, 1] Position [300, 71, 345, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "10875" Position [370, 88, 400, 102] IconDisplay "Port number" } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "S" SrcPort 1 DstBlock "Convert2" DstPort 1 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "Convert2" SrcPort 1 DstBlock "Register2" DstPort 3 } } } Block { BlockType Outport Name "Pkt Done" SID "10876" Position [1215, 263, 1245, 277] IconDisplay "Port number" } Line { SrcBlock "Relational3" SrcPort 1 Points [25, 0; 0, -80] Branch { Points [-535, 0; 0, 35] DstBlock "Logical2" DstPort 1 } Branch { DstBlock "Logical3" DstPort 2 } } Line { SrcBlock "Counter1" SrcPort 1 Points [90, 0] Branch { DstBlock "Relational3" DstPort 1 } Branch { Points [0, -195] DstBlock "Gateway Out5" DstPort 1 } } Line { SrcBlock "Logical2" SrcPort 1 Points [10, 0] Branch { DstBlock "Counter1" DstPort 1 } Branch { Points [0, 55] DstBlock "S-R Latch1" DstPort 2 } } Line { SrcBlock "Rst" SrcPort 1 DstBlock "Logical2" DstPort 2 } Line { SrcBlock "Bits Done" SrcPort 1 Points [25, 0] Branch { Points [0, -315] DstBlock "Gateway Out4" DstPort 1 } Branch { DstBlock "S-R Latch1" DstPort 1 } } Line { SrcBlock "S-R Latch1" SrcPort 1 Points [15, 0] Branch { DstBlock "Logical1" DstPort 1 } Branch { Points [0, -120] DstBlock "Logical3" DstPort 1 } } Line { SrcBlock "IQ Valid" SrcPort 1 DstBlock "Logical1" DstPort 2 } Line { SrcBlock "Logical3" SrcPort 1 Points [30, 0] Branch { DstBlock "Pkt Done" DstPort 1 } Branch { Points [0, -145] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "Gateway Out4" SrcPort 1 DstBlock "PHY Rx Busy - Extension" DstPort 1 } Line { SrcBlock "Gateway Out1" SrcPort 1 DstBlock "PHY Rx Busy - Extension" DstPort 2 } Line { SrcBlock "Gateway Out2" SrcPort 1 DstBlock "PHY Rx Busy - Extension" DstPort 3 } Line { SrcBlock "Gateway Out3" SrcPort 1 DstBlock "PHY Rx Busy - Extension" DstPort 4 } Line { SrcBlock "From2" SrcPort 1 Points [55, 0] Branch { Points [0, 25] DstBlock "Gateway Out6" DstPort 1 } Branch { Points [85, 0; 0, -65] Branch { DstBlock "Relational3" DstPort 2 } Branch { Points [0, -275] DstBlock "Gateway Out2" DstPort 1 } } } Line { SrcBlock "Logical1" SrcPort 1 Points [25, 0; 0, -25] Branch { DstBlock "Counter1" DstPort 2 } Branch { Points [0, -290] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "Gateway Out5" SrcPort 1 DstBlock "PHY Rx Busy - Extension" DstPort 5 } Line { SrcBlock "Gateway Out6" SrcPort 1 DstBlock "Display" DstPort 1 } } } Block { BlockType From Name "From1" SID "10877" Position [30, 340, 225, 360] ShowName off CloseFcn "tagdialog Close" GotoTag "OFDM_RX_SIGNAL_INVALID" TagVisibility "global" } Block { BlockType From Name "From2" SID "10878" Position [755, 25, 950, 45] ShowName off CloseFcn "tagdialog Close" GotoTag "CS_ADC_I" TagVisibility "global" } Block { BlockType From Name "From3" SID "10879" Position [30, 360, 225, 380] ShowName off CloseFcn "tagdialog Close" GotoTag "HT_SIG_ERROR" TagVisibility "global" } Block { BlockType From Name "From4" SID "10880" Position [30, 380, 225, 400] ShowName off CloseFcn "tagdialog Close" GotoTag "RX_GLOBAL_RESET" TagVisibility "global" } Block { BlockType Reference Name "Gateway Out1" SID "10881" Ports [1, 1] Position [1015, 89, 1050, 101] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Sym Inc" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "10882" Ports [1, 1] Position [1015, 114, 1050, 126] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Bits Done" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "10883" Ports [1, 1] Position [1015, 29, 1050, 41] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "ADC I" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "10884" Ports [1, 1] Position [1015, 64, 1050, 76] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Start" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "10885" Ports [1, 1] Position [1015, 164, 1050, 176] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Reset" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "10924" Ports [1, 1] Position [1015, 189, 1050, 201] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "HTSIG Error" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "10886" Ports [1, 1] Position [1015, 139, 1050, 151] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Pkt Done" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Logical1" SID "10887" Ports [2, 1] Position [400, 276, 435, 309] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,33,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 33 33 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 33 33 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[20.44 20.44 24.4" "4 20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[16.44 16.44 20.44 20.44 16.44 ]," "[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1 1 1 ]);\npatch([12.1" " 25.88 21.88 17.88 13.88 8.1 12.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('or');\nfprintf('" "','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "11307" Ports [2, 1] Position [755, 421, 790, 454] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,33,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 33 33 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 33 33 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[20.44 20.44 24.4" "4 20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[16.44 16.44 20.44 20.44 16.44 ]," "[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1 1 1 ]);\npatch([12.1" " 25.88 21.88 17.88 13.88 8.1 12.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('or');\nfprintf('" "','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical3" SID "10888" Ports [4, 1] Position [300, 320, 335, 400] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "4" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,80,4,1,white,blue,0,4f3eee2e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 80 80 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 80 80 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[45.55 45.55 50." "55 45.55 50.55 50.55 50.55 45.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[40.55 40.55 45.55 45.55 40." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[35.55 35.55 40.55 40.55 35.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[30.55 30.55 35.55 30.55 35.55 35.55 30.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\n\ncolor('black');dis" "p('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "OFDM Syms" SID "10889" Ports [3, 1] Position [485, 239, 575, 291] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "OFDM Syms" Location [987, 828, 1312, 1006] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Start" SID "10890" Position [235, 658, 265, 672] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "IQ valid" SID "10891" Position [230, 598, 260, 612] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "Rst" SID "10892" Position [215, 683, 245, 697] Port "3" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub" SID "10893" Ports [2, 1] Position [740, 451, 800, 509] BlockMirror on NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL off hw_selection "Fabric" pipelined off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" sg_icon_stat "60,58,2,1,white,blue,0,e139daf6,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 58 58 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 58 58 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[37.88 37" ".88 45.88 37.88 45.88 45.88 45.88 37.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[29.88 29.88 37.88 37." "88 29.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[21.88 21.88 29.88 29.88 21.88 ],[1 1 1 ]" ");\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[13.88 13.88 21.88 13.88 21.88 21.88 13.88 ],[0.931 0.946 0." "973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port" "_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bf{a " "+ b}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Counter" SID "10894" Ports [2, 1] Position [615, 556, 675, 634] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited count" "er is implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "Inf" operation "Up" start_count "1" cnt_by_val "1" arith_type "Unsigned" n_bits "ceil(log2(MAX_CP_LEN)) + ceil(log2(MAX_NUM_SC))" bin_pt "0" load_pin off rst on en on explicit_period "off" period "1" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "counter" sg_icon_stat "60,78,2,1,white,blue,0,ae3608d6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 78 78 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 78 78 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[47.88 47" ".88 55.88 47.88 55.88 55.88 55.88 47.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[39.88 39.88 47.88 47." "88 39.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[31.88 31.88 39.88 39.88 31.88 ],[1 1 1 ]" ");\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[23.88 23.88 31.88 23.88 31.88 31.88 23.88 ],[0.931 0.946 0." "973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port" "_label('input',1,'rst');\ncolor('black');port_label('input',2,'en');\n\ncolor('black');disp('{\\fontsize{14}\\bf" "++}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Display Name "Display" SID "10895" Ports [1] Position [900, 371, 985, 399] ZOrder -1 ShowName off Decimation "1" Lockdown off } Block { BlockType From Name "From1" SID "10896" Position [865, 455, 1060, 475] BlockMirror on NamePlacement "alternate" ShowName off CloseFcn "tagdialog Close" GotoTag "regRx_NUM_SC" TagVisibility "global" } Block { BlockType From Name "From2" SID "10897" Position [865, 485, 1060, 505] BlockMirror on NamePlacement "alternate" ShowName off CloseFcn "tagdialog Close" GotoTag "regRx_CP_LEN" TagVisibility "global" } Block { BlockType Reference Name "Gateway Out9" SID "10898" Ports [1, 1] Position [750, 379, 785, 391] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "10899" Ports [1, 1] Position [440, 576, 465, 594] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "10900" Ports [2, 1] Position [340, 517, 375, 548] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,31,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 31 31 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 31 31 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[19.44 19.4" "4 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[15.44 15.44 19.44 19.44 " "15.44 ],[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\np" "atch([12.1 25.88 21.88 17.88 13.88 8.1 12.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('an" "d');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "10901" Ports [2, 1] Position [520, 597, 555, 628] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,31,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 31 31 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 31 31 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[19.44 19.4" "4 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[15.44 15.44 19.44 19.44 " "15.44 ],[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\np" "atch([12.1 25.88 21.88 17.88 13.88 8.1 12.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('an" "d');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical3" SID "10902" Ports [2, 1] Position [535, 557, 570, 588] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,31,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 31 31 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 31 31 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[19.44 19.4" "4 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[15.44 15.44 19.44 19.44 " "15.44 ],[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\np" "atch([12.1 25.88 21.88 17.88 13.88 8.1 12.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('or" "');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational1" SID "10903" Ports [2, 1] Position [630, 470, 665, 510] BlockMirror on NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a<=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,40,2,1,white,blue,0,52e4b236,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 40 40 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bfa \\leq b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "S-R Latch1" SID "10904" Ports [2, 1] Position [300, 658, 335, 687] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "S-R Latch1" Location [351, 366, 2001, 1172] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "10905" Position [140, 103, 170, 117] IconDisplay "Port number" } Block { BlockType Inport Name "R" SID "10906" Position [140, 88, 170, 102] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "10907" Ports [0, 1] Position [195, 71, 210, 89] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "15,18,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11.22 " "13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 9.22 " "],[0.931 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([4.55 " "11.44 9.44 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "10908" Ports [1, 1] Position [230, 86, 255, 104] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('outpu" "t',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "10909" Ports [1, 1] Position [230, 101, 255, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('outpu" "t',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "10910" Ports [3, 1] Position [300, 71, 345, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "10911" Position [370, 88, 400, 102] IconDisplay "Port number" } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "S" SrcPort 1 DstBlock "Convert2" DstPort 1 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "Convert2" SrcPort 1 DstBlock "Register2" DstPort 3 } } } Block { BlockType Outport Name "Sym" SID "10912" Position [540, 528, 570, 542] IconDisplay "Port number" } Line { SrcBlock "AddSub" SrcPort 1 Points [-30, 0] Branch { DstBlock "Relational1" DstPort 1 } Branch { Points [0, -95] DstBlock "Gateway Out9" DstPort 1 } } Line { SrcBlock "Logical3" SrcPort 1 DstBlock "Counter" DstPort 1 } Line { SrcBlock "Counter" SrcPort 1 Points [10, 0; 0, -95] DstBlock "Relational1" DstPort 2 } Line { SrcBlock "IQ valid" SrcPort 1 Points [45, 0] Branch { Points [0, -65] DstBlock "Logical1" DstPort 2 } Branch { DstBlock "Logical2" DstPort 1 } } Line { SrcBlock "From1" SrcPort 1 DstBlock "AddSub" DstPort 1 } Line { SrcBlock "From2" SrcPort 1 DstBlock "AddSub" DstPort 2 } Line { SrcBlock "Gateway Out9" SrcPort 1 DstBlock "Display" DstPort 1 } Line { SrcBlock "Relational1" SrcPort 1 Points [-315, 0; 0, 35] DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Logical1" SrcPort 1 Points [20, 0] Branch { DstBlock "Sym" DstPort 1 } Branch { Points [0, 30] DstBlock "Logical3" DstPort 1 } } Line { SrcBlock "Start" SrcPort 1 DstBlock "S-R Latch1" DstPort 1 } Line { SrcBlock "Logical2" SrcPort 1 DstBlock "Counter" DstPort 2 } Line { SrcBlock "S-R Latch1" SrcPort 1 Points [10, 0; 0, -55] Branch { DstBlock "Logical2" DstPort 2 } Branch { Points [0, -35] DstBlock "Inverter" DstPort 1 } } Line { SrcBlock "Rst" SrcPort 1 Points [25, 0; 0, -10] DstBlock "S-R Latch1" DstPort 2 } Line { SrcBlock "Inverter" SrcPort 1 Points [50, 0] DstBlock "Logical3" DstPort 2 } } } Block { BlockType Scope Name "PHY Rx Busy" SID "10913" Ports [7] Position [1215, 27, 1260, 213] ZOrder -3 Floating off Location [1921, 45, 3841, 1199] Open off NumInputPorts "7" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" } List { ListType ScopeGraphics FigureColor "[0.5 0.5 0.5]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "11300 " YMin "-0.2~-1~-1~-1~-1~-1~-1" YMax "0.25~1~1~1~1~1~1" SaveName "ScopeData30" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType Outport Name "Pkt Done" SID "10914" Position [835, 433, 865, 447] IconDisplay "Port number" } Line { Name "Start" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 DstBlock "PHY Rx Busy" DstPort 2 } Line { Name "Sym Inc" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 DstBlock "PHY Rx Busy" DstPort 3 } Line { Name "Bits Done" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 DstBlock "PHY Rx Busy" DstPort 4 } Line { SrcBlock "IQ Valid" SrcPort 1 Points [130, 0] Branch { DstBlock "OFDM Syms" DstPort 2 } Branch { Labels [0, 0] Points [0, 165] DstBlock "Extension" DstPort 2 } } Line { Name "Pkt Done" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 Points [40, 0] Branch { DstBlock "PHY Rx Busy" DstPort 5 } Branch { Points [0, -95] DstBlock "Bus Creator" DstPort 2 } } Line { SrcBlock "Start" SrcPort 1 Points [40, 0] Branch { Points [0, 0] Branch { Points [0, 0; 0, -180] DstBlock "Gateway Out4" DstPort 1 } Branch { Labels [0, 0] DstBlock "Delay" DstPort 1 } } Branch { Points [0, 80] DstBlock "Logical3" DstPort 1 } } Line { SrcBlock "OFDM Syms" SrcPort 1 Points [15, 0] Branch { Points [0, 45; -125, 0] DstBlock "Bits" DstPort 1 } Branch { Points [0, -170] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "Extension" SrcPort 1 Points [135, 0] Branch { Points [0, -285] DstBlock "Gateway Out8" DstPort 1 } Branch { Points [0, 65; -330, 0] DstBlock "Logical1" DstPort 2 } Branch { DstBlock "Logical2" DstPort 1 } } Line { SrcBlock "Bits" SrcPort 1 Points [15, 0] Branch { Points [0, 40; -125, 0] DstBlock "Extension" DstPort 1 } Branch { Points [90, 0; 0, -230] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "From2" SrcPort 1 DstBlock "Gateway Out3" DstPort 1 } Line { Name "ADC I" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 DstBlock "Bus Creator" DstPort 1 } Line { SrcBlock "Logical3" SrcPort 1 Points [35, 0] Branch { Points [-20, 0] Branch { DstBlock "Bits" DstPort 2 } Branch { Points [0, 0] Branch { Points [0, -190] DstBlock "Gateway Out5" DstPort 1 } Branch { Points [0, 85] Branch { DstBlock "Extension" DstPort 3 } Branch { Points [0, 65; 385, 0] DstBlock "Logical2" DstPort 2 } } } } Branch { Points [0, -75] DstBlock "Logical1" DstPort 1 } } Line { SrcBlock "From1" SrcPort 1 DstBlock "Logical3" DstPort 2 } Line { Name "Reset" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 DstBlock "PHY Rx Busy" DstPort 6 } Line { SrcBlock "Logical1" SrcPort 1 Points [15, 0; 0, -15] DstBlock "OFDM Syms" DstPort 3 } Line { SrcBlock "From3" SrcPort 1 Points [20, 0] Branch { DstBlock "Logical3" DstPort 3 } Branch { Points [0, -175] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "From4" SrcPort 1 DstBlock "Logical3" DstPort 4 } Line { SrcBlock "Bus Creator" SrcPort 1 DstBlock "PHY Rx Busy" DstPort 1 } Line { Name "HTSIG Error" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 DstBlock "PHY Rx Busy" DstPort 7 } Line { Labels [0, 0] SrcBlock "Delay" SrcPort 1 DstBlock "OFDM Syms" DstPort 1 } Line { SrcBlock "Logical2" SrcPort 1 DstBlock "Pkt Done" DstPort 1 } Annotation { Name "CCA_BUSY for any Rx pkt with valid SIGNAL field\nRx Active drops after last data-bearing sample plus\npr" "ogrammable extension. This block doesn't care about\nactual decoding latency or supported rates.\n\nThis block sta" "rts counting before the SIGNAL field is\ndecoded. If the SIGNAL field is invalid, the default rate/length\n(24 bit" "s @ 6Mbps) will be used. This will de-assert busy after\nthe symbols containing the undecodable SIGNAL field." Position [480, 671] HorizontalAlignment "left" } Annotation { Name "Force reset if SIGNAL or HT-SIG is invalid, indicating\nPHY header could not be intepretted for waveform" "\nduration.\n\nAny other Rx event will keep this block running for\nthe duration of the Rx waveform, indepedent of" " the\nRx PHY pipeline's attempt to decode the waveform.\nThis keeps the MAC in sync with the medium by\naligning R" "X_END to the end of the waveform, even\nfor waveforms recevied below the physical CS\nthreshold." Position [36, 479] HorizontalAlignment "left" } } } Block { BlockType Reference Name "Register" SID "18144" Ports [1, 1] Position [260, 893, 285, 917] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,24,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 24 24 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 24 24 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[15" ".33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[12.33 12.33 " "15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[9.33 9.33 12.33 12.33 9.33 ]" ",[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode" "','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "18145" Ports [1, 1] Position [260, 938, 285, 962] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,24,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 24 24 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 24 24 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[15" ".33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[12.33 12.33 " "15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[9.33 9.33 12.33 12.33 9.33 ]" ",[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode" "','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational" SID "7569" Ports [2, 1] Position [740, 555, 780, 595] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a>b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "40,40,2,1,white,blue,0,b5131c97,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55" " 25.55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25" ".55 25.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 " "],[1 1 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor(" "'black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('outp" "ut',1,'\\bfa > b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational1" SID "7570" Ports [2, 1] Position [740, 600, 780, 640] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a>b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "40,40,2,1,white,blue,0,b5131c97,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55" " 25.55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25" ".55 25.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 " "],[1 1 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor(" "'black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('outp" "ut',1,'\\bfa > b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational2" SID "7571" Ports [2, 1] Position [740, 645, 780, 685] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a>b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "40,40,2,1,white,blue,0,b5131c97,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55" " 25.55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25" ".55 25.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 " "],[1 1 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor(" "'black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('outp" "ut',1,'\\bfa > b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational3" SID "7572" Ports [2, 1] Position [740, 690, 780, 730] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a>b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "40,40,2,1,white,blue,0,b5131c97,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55" " 25.55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25" ".55 25.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 " "],[1 1 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor(" "'black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('outp" "ut',1,'\\bfa > b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "S-R Latch1" SID "7573" Ports [2, 1] Position [960, 384, 995, 446] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "S-R Latch1" Location [351, 366, 2001, 1172] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "7574" Position [140, 103, 170, 117] IconDisplay "Port number" } Block { BlockType Inport Name "R" SID "7575" Position [140, 88, 170, 102] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "7576" Ports [0, 1] Position [195, 71, 210, 89] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "15,18,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11.22 13.22 " "11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 9.22 ],[0.931" " 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([4.55 11.44 9.44" " 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon" " graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "7577" Ports [1, 1] Position [230, 86, 255, 104] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cast');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "7578" Ports [1, 1] Position [230, 101, 255, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cast');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "7579" Ports [3, 1] Position [300, 71, 345, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 30.66 3" "6.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 30.66 24" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('" "input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'en');\ncolor('bl" "ack');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon te" "xt');" } Block { BlockType Outport Name "Q" SID "7580" Position [370, 88, 400, 102] IconDisplay "Port number" } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "S" SrcPort 1 DstBlock "Convert2" DstPort 1 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "Convert2" SrcPort 1 DstBlock "Register2" DstPort 3 } } } Block { BlockType SubSystem Name "S-R Latch2" SID "7581" Ports [2, 1] Position [350, 408, 385, 437] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "S-R Latch2" Location [351, 366, 2001, 1172] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "7582" Position [140, 103, 170, 117] IconDisplay "Port number" } Block { BlockType Inport Name "R" SID "7583" Position [140, 88, 170, 102] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "7584" Ports [0, 1] Position [195, 71, 210, 89] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "15,18,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11.22 13.22 " "11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 9.22 ],[0.931" " 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([4.55 11.44 9.44" " 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon" " graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "7585" Ports [1, 1] Position [230, 86, 255, 104] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cast');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "7586" Ports [1, 1] Position [230, 101, 255, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cast');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "7587" Ports [3, 1] Position [300, 71, 345, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 30.66 3" "6.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 30.66 24" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('" "input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'en');\ncolor('bl" "ack');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon te" "xt');" } Block { BlockType Outport Name "Q" SID "7588" Position [370, 88, 400, 102] IconDisplay "Port number" } Line { SrcBlock "Convert2" SrcPort 1 DstBlock "Register2" DstPort 3 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "S" SrcPort 1 DstBlock "Convert2" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Register2" DstPort 1 } } } Block { BlockType SubSystem Name "S-R Latch3" SID "7589" Ports [2, 1] Position [540, 968, 575, 997] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "S-R Latch3" Location [351, 366, 2001, 1172] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "7590" Position [140, 103, 170, 117] IconDisplay "Port number" } Block { BlockType Inport Name "R" SID "7591" Position [140, 88, 170, 102] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "7592" Ports [0, 1] Position [195, 71, 210, 89] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "15,18,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11.22 13.22 " "11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 9.22 ],[0.931" " 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([4.55 11.44 9.44" " 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon" " graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "7593" Ports [1, 1] Position [230, 86, 255, 104] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cast');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "7594" Ports [1, 1] Position [230, 101, 255, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cast');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "7595" Ports [3, 1] Position [300, 71, 345, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 30.66 3" "6.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 30.66 24" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('" "input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'en');\ncolor('bl" "ack');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon te" "xt');" } Block { BlockType Outport Name "Q" SID "7596" Position [370, 88, 400, 102] IconDisplay "Port number" } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "S" SrcPort 1 DstBlock "Convert2" DstPort 1 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "Convert2" SrcPort 1 DstBlock "Register2" DstPort 3 } } } Block { BlockType Reference Name "Slice2" SID "7597" Ports [1, 1] Position [415, 318, 450, 332] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Upper Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "35,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 14 14 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 14 14 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[9" ".22 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[7.22 7.22 9.22" " 9.22 7.22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 " "]);\npatch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');por" "t_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Line { SrcBlock "From2" SrcPort 1 Points [20, 0] Branch { DstBlock "Relational" DstPort 2 } Branch { Points [0, 45] Branch { DstBlock "Relational1" DstPort 2 } Branch { Points [0, 45] Branch { DstBlock "Relational2" DstPort 2 } Branch { Points [0, 45] DstBlock "Relational3" DstPort 2 } } } } Line { Name "" Labels [0, 0] SrcBlock "Bus\nSelector1" SrcPort 1 DstBlock "Relational" DstPort 1 } Line { Name "CCA_BUSY" Labels [0, 0] SrcBlock "Logical2" SrcPort 1 Points [50, 0] Branch { DstBlock "Goto" DstPort 1 } Branch { Points [0, -420] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "Det OFDM" SrcPort 1 Points [110, 0; 0, 25] DstBlock "S-R Latch2" DstPort 1 } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "S-R Latch2" DstPort 2 } Line { SrcBlock "Reset OFDM" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "LTS Timeout" SrcPort 1 DstBlock "Logical1" DstPort 2 } Line { SrcBlock "S-R Latch2" SrcPort 1 Points [85, 0] Branch { Points [0, -85] DstBlock "Logical3" DstPort 2 } Branch { Points [0, 90; 490, 0; 0, 55] DstBlock "Logical2" DstPort 2 } } Line { SrcBlock "IQ Valid" SrcPort 1 DstBlock "Rate-Length\nBUSY" DstPort 1 } Line { SrcBlock "Logical3" SrcPort 1 Points [45, 0] Branch { Points [0, -220] DstBlock "Gateway Out4" DstPort 1 } Branch { DstBlock "Rate-Length\nBUSY" DstPort 2 } } Line { SrcBlock "LTS Sync" SrcPort 1 DstBlock "Delay" DstPort 1 } Line { SrcBlock "Avg RSSI Vec" SrcPort 1 DstBlock "Bus\nSelector1" DstPort 1 } Line { SrcBlock "Slice2" SrcPort 1 DstBlock "Logical3" DstPort 1 } Line { SrcBlock "Relational" SrcPort 1 DstBlock "PHY CCA Logic" DstPort 1 } Line { SrcBlock "Relational1" SrcPort 1 Points [0, -30] DstBlock "PHY CCA Logic" DstPort 2 } Line { Name "" Labels [0, 0] SrcBlock "Bus\nSelector1" SrcPort 2 DstBlock "Relational1" DstPort 1 } Line { SrcBlock "PHY CCA Logic" SrcPort 1 DstBlock "Logical2" DstPort 3 } Line { Name "" Labels [0, 0] SrcBlock "Bus\nSelector1" SrcPort 3 DstBlock "Relational2" DstPort 1 } Line { Name "" Labels [0, 0] SrcBlock "Bus\nSelector1" SrcPort 4 DstBlock "Relational3" DstPort 1 } Line { SrcBlock "Relational2" SrcPort 1 Points [10, 0; 0, -60] DstBlock "PHY CCA Logic" DstPort 3 } Line { SrcBlock "Relational3" SrcPort 1 Points [20, 0; 0, -90] DstBlock "PHY CCA Logic" DstPort 4 } Line { Name "Start" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 DstBlock "PHY CCA" DstPort 1 } Line { Name "RL Active" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 DstBlock "PHY CCA" DstPort 2 } Line { Name "CCA Busy" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 DstBlock "PHY CCA" DstPort 3 } Line { SrcBlock "From3" SrcPort 1 DstBlock "S-R Latch1" DstPort 1 } Line { SrcBlock "S-R Latch1" SrcPort 1 Points [45, 0] Branch { DstBlock "Goto2" DstPort 1 } Branch { Points [0, -275] DstBlock "Gateway Out1" DstPort 1 } Branch { Points [0, 125] DstBlock "Logical2" DstPort 1 } } Line { SrcBlock "Rate-Length\nBUSY" SrcPort 1 Points [80, 0] Branch { DstBlock "Goto1" DstPort 1 } Branch { Points [0, 100] DstBlock "Logical5" DstPort 1 } } Line { SrcBlock "Det DSSS" SrcPort 1 DstBlock "Register1" DstPort 1 } Line { SrcBlock "Reset DSSS" SrcPort 1 DstBlock "S-R Latch3" DstPort 2 } Line { SrcBlock "From1" SrcPort 1 Points [25, 0; 0, 30] DstBlock "Logical4" DstPort 1 } Line { SrcBlock "S-R Latch3" SrcPort 1 DstBlock "Logical4" DstPort 2 } Line { SrcBlock "Logical4" SrcPort 1 Points [275, 0; 0, -350] DstBlock "Logical2" DstPort 4 } Line { SrcBlock "Logical5" SrcPort 1 DstBlock "S-R Latch1" DstPort 2 } Line { SrcBlock "From4" SrcPort 1 DstBlock "Logical5" DstPort 2 } Line { SrcBlock "Delay" SrcPort 1 DstBlock "Slice2" DstPort 1 } Line { SrcBlock "Posedge" SrcPort 1 DstBlock "Logical6" DstPort 2 } Line { SrcBlock "Logical6" SrcPort 1 Points [15, 0; 0, 30] DstBlock "S-R Latch3" DstPort 1 } Line { SrcBlock "Posedge1" SrcPort 1 Points [40, 0] DstBlock "Logical6" DstPort 1 } Line { SrcBlock "From5" SrcPort 1 DstBlock "Register" DstPort 1 } Line { SrcBlock "Register" SrcPort 1 DstBlock "Posedge1" DstPort 1 } Line { SrcBlock "Register1" SrcPort 1 DstBlock "Posedge" DstPort 1 } Annotation { Position [1418, 254] } } } Block { BlockType SubSystem Name "Pkt Det" SID "7598" Ports [7, 3] Position [490, 220, 630, 420] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Pkt Det" Location [592, 525, 1087, 730] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "112" Block { BlockType Inport Name "Reset OFDM" SID "7599" Position [105, 298, 135, 312] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "Reset DSSS" SID "7600" Position [105, 338, 135, 352] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "Rx I Vec" SID "7601" Position [85, 423, 115, 437] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "Rx Q Vec" SID "7602" Position [85, 518, 115, 532] Port "4" IconDisplay "Port number" } Block { BlockType Inport Name "IQ Valid" SID "7603" Position [85, 608, 115, 622] Port "5" IconDisplay "Port number" } Block { BlockType Inport Name "RSSI Vec" SID "7604" Position [85, 728, 115, 742] Port "6" IconDisplay "Port number" } Block { BlockType Inport Name "LTF Det" SID "18073" Position [105, 263, 135, 277] NamePlacement "alternate" Port "7" IconDisplay "Port number" } Block { BlockType BusSelector Name "Bus\nSelector" SID "7605" Ports [1, 4] Position [160, 395, 165, 460] ZOrder -3 ShowName off OutputSignals "RFA_I,RFB_I,RFC_I,RFD_I" Port { PortNumber 1 Name "" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 2 Name "" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 3 Name "" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 4 Name "" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType BusSelector Name "Bus\nSelector1" SID "7606" Ports [1, 4] Position [160, 490, 165, 555] ZOrder -3 ShowName off OutputSignals "RFA_Q,RFB_Q,RFC_Q,RFD_Q" Port { PortNumber 1 Name "" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 2 Name "" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 3 Name "" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 4 Name "" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType BusSelector Name "Bus\nSelector2" SID "7607" Ports [1, 4] Position [160, 700, 165, 765] ZOrder -3 ShowName off OutputSignals "RFA_RSSI,RFB_RSSI,RFC_RSSI,RFD_RSSI" Port { PortNumber 1 Name "" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 2 Name "" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 3 Name "" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 4 Name "" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType BusSelector Name "Bus\nSelector3" SID "7608" Ports [1, 4] Position [160, 580, 165, 645] ZOrder -3 ShowName off OutputSignals "signal1,signal2,signal3,signal4" Port { PortNumber 1 Name "" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 2 Name "" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 3 Name "" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 4 Name "" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Constant2" SID "7609" Ports [0, 1] Position [555, 706, 570, 724] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "15,18,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 " "9.22 ],[0.931 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch(" "[4.55 11.44 9.44 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf(''" ",'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1," "'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant3" SID "7610" Ports [0, 1] Position [555, 791, 570, 809] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "15,18,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 " "9.22 ],[0.931 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch(" "[4.55 11.44 9.44 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf(''" ",'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1," "'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Counter" SID "17457" Ports [2, 1] Position [1115, 585, 1175, 645] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited co" "unter is implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "Inf" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "32" bin_pt "0" load_pin off rst on en on explicit_period "off" period "1" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "counter" sg_icon_stat "60,60,2,1,white,blue,0,ae3608d6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 60 60 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[38.8" "8 38.88 46.88 38.88 46.88 46.88 46.88 38.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[30.88 30.88 38.8" "8 38.88 30.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[22.88 22.88 30.88 30.88 22.88 ],[1" " 1 1 ]);\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[14.88 14.88 22.88 14.88 22.88 22.88 14.88 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('blac" "k');port_label('input',1,'rst');\ncolor('black');port_label('input',2,'en');\n\ncolor('black');disp('{\\fontsiz" "e{14}\\bf++}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Counter1" SID "17464" Ports [2, 1] Position [1115, 670, 1175, 730] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited co" "unter is implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "Inf" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "32" bin_pt "0" load_pin off rst on en on explicit_period "off" period "1" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "counter" sg_icon_stat "60,60,2,1,white,blue,0,ae3608d6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 60 60 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[38.8" "8 38.88 46.88 38.88 46.88 46.88 46.88 38.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[30.88 30.88 38.8" "8 38.88 30.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[22.88 22.88 30.88 30.88 22.88 ],[1" " 1 1 ]);\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[14.88 14.88 22.88 14.88 22.88 22.88 14.88 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('blac" "k');port_label('input',1,'rst');\ncolor('black');port_label('input',2,'en');\n\ncolor('black');disp('{\\fontsiz" "e{14}\\bf++}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "DSSS Ant Sel Logic" SID "7611" Ports [4, 1] Position [725, 470, 795, 535] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "DSSS Ant Sel Logic" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "124" Block { BlockType Inport Name "Det A" SID "7612" Position [370, 353, 400, 367] IconDisplay "Port number" } Block { BlockType Inport Name "Det B" SID "7613" Position [370, 418, 400, 432] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "Det C" SID "7614" Position [370, 483, 400, 497] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "Det D" SID "7615" Position [370, 548, 400, 562] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "Concat" SID "7616" Ports [4, 1] Position [905, 235, 950, 325] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point at z" "ero." num_inputs "4" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "45,90,4,1,white,blue,0,47d3d416,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 90 90 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 90 90 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[51.66 51.66 5" "7.66 51.66 57.66 57.66 57.66 51.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[45.66 45.66 51.66 51.66 45" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[39.66 39.66 45.66 45.66 39.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[33.66 33.66 39.66 33.66 39.66 39.66 33.66 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('" "input',1,'hi');\n\n\ncolor('black');port_label('input',4,'lo');\n\ncolor('black');disp('\\fontsize{20}\\}','texmod" "e','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From1" SID "7617" Position [445, 385, 645, 405] ShowName off CloseFcn "tagdialog Close" GotoTag "regRx_pktDetEn_RFB" TagVisibility "global" } Block { BlockType From Name "From2" SID "7618" Position [445, 450, 645, 470] ShowName off CloseFcn "tagdialog Close" GotoTag "regRx_pktDetEn_RFC" TagVisibility "global" } Block { BlockType From Name "From3" SID "7619" Position [445, 515, 645, 535] ShowName off CloseFcn "tagdialog Close" GotoTag "regRx_pktDetEn_RFD" TagVisibility "global" } Block { BlockType From Name "From6" SID "7620" Position [445, 320, 645, 340] ShowName off CloseFcn "tagdialog Close" GotoTag "regRx_pktDetEn_RFA" TagVisibility "global" } Block { BlockType Goto Name "Goto" SID "7621" Position [1030, 269, 1165, 291] ZOrder -10 ShowName off GotoTag "PKTDET_STATUS_DSSS" TagVisibility "global" } Block { BlockType Reference Name "Logical" SID "7622" Ports [2, 1] Position [680, 316, 715, 374] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,58,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 58 58 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 58 58 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[34.55 34.55 39." "55 34.55 39.55 39.55 39.55 34.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[29.55 29.55 34.55 34.55 29." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[24.55 24.55 29.55 29.55 24.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[19.55 19.55 24.55 19.55 24.55 24.55 19.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('a" "nd');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "7623" Ports [4, 1] Position [905, 338, 940, 397] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "4" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,59,4,1,white,blue,0,4f3eee2e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 59 59 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 59 59 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[34.55 34.55 39." "55 34.55 39.55 39.55 39.55 34.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[29.55 29.55 34.55 34.55 29." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[24.55 24.55 29.55 29.55 24.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[19.55 19.55 24.55 19.55 24.55 24.55 19.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\n\ncolor('black');dis" "p('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "7624" Ports [2, 1] Position [680, 381, 715, 439] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,58,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 58 58 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 58 58 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[34.55 34.55 39." "55 34.55 39.55 39.55 39.55 34.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[29.55 29.55 34.55 34.55 29." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[24.55 24.55 29.55 29.55 24.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[19.55 19.55 24.55 19.55 24.55 24.55 19.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('a" "nd');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical3" SID "7625" Ports [2, 1] Position [680, 446, 715, 504] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,58,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 58 58 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 58 58 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[34.55 34.55 39." "55 34.55 39.55 39.55 39.55 34.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[29.55 29.55 34.55 34.55 29." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[24.55 24.55 29.55 29.55 24.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[19.55 19.55 24.55 19.55 24.55 24.55 19.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('a" "nd');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical4" SID "7626" Ports [2, 1] Position [680, 511, 715, 569] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,58,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 58 58 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 58 58 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[34.55 34.55 39." "55 34.55 39.55 39.55 39.55 34.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[29.55 29.55 34.55 34.55 29." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[24.55 24.55 29.55 29.55 24.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[19.55 19.55 24.55 19.55 24.55 24.55 19.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('a" "nd');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Pkt Det" SID "7627" Position [995, 362, 1025, 378] NamePlacement "alternate" IconDisplay "Port number" } Line { SrcBlock "Logical4" SrcPort 1 Points [40, 0; 0, -150; 100, 0] Branch { DstBlock "Logical1" DstPort 4 } Branch { Points [0, -140] DstBlock "Concat" DstPort 1 } } Line { SrcBlock "Logical3" SrcPort 1 Points [25, 0; 0, -100; 120, 0] Branch { DstBlock "Logical1" DstPort 3 } Branch { Points [0, -105] DstBlock "Concat" DstPort 2 } } Line { SrcBlock "Det D" SrcPort 1 DstBlock "Logical4" DstPort 2 } Line { SrcBlock "Det C" SrcPort 1 DstBlock "Logical3" DstPort 2 } Line { SrcBlock "From3" SrcPort 1 DstBlock "Logical4" DstPort 1 } Line { SrcBlock "From2" SrcPort 1 DstBlock "Logical3" DstPort 1 } Line { SrcBlock "From1" SrcPort 1 DstBlock "Logical2" DstPort 1 } Line { SrcBlock "Det B" SrcPort 1 DstBlock "Logical2" DstPort 2 } Line { SrcBlock "Det A" SrcPort 1 DstBlock "Logical" DstPort 2 } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Pkt Det" DstPort 1 } Line { SrcBlock "Logical2" SrcPort 1 Points [15, 0; 0, -50; 135, 0] Branch { DstBlock "Logical1" DstPort 2 } Branch { Points [0, -70] DstBlock "Concat" DstPort 3 } } Line { SrcBlock "Logical" SrcPort 1 Points [155, 0] Branch { DstBlock "Logical1" DstPort 1 } Branch { Points [0, -35] DstBlock "Concat" DstPort 4 } } Line { SrcBlock "From6" SrcPort 1 DstBlock "Logical" DstPort 1 } Line { SrcBlock "Concat" SrcPort 1 DstBlock "Goto" DstPort 1 } } } Block { BlockType SubSystem Name "Ext Pkt Det" SID "7628" Ports [1, 1] Position [505, 326, 580, 354] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Ext Pkt Det" Location [641, 146, 992, 259] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Reset" SID "7629" Position [425, 218, 455, 232] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Constant Name "Constant" SID "7630" Position [270, 253, 285, 267] ShowName off Value "0" } Block { BlockType Reference Name "Convert" SID "7631" Ports [1, 1] Position [965, 236, 990, 254] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "16" bin_pt "14" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cast');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "7632" Ports [1, 1] Position [965, 266, 990, 284] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "16" bin_pt "14" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cast');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "7633" Ports [1, 1] Position [1260, 231, 1285, 249] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "16" bin_pt "14" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cast');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Debouce" SID "7634" Ports [2, 1] Position [750, 248, 790, 297] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Debouce" Location [88, 301, 2330, 1301] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "7635" Position [165, 128, 195, 142] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "R" SID "7636" Position [165, 148, 195, 162] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Logical1" SID "7637" Ports [4, 1] Position [540, 141, 585, 194] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "4" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,53,4,1,white,blue,0,50b60d37,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 53 53 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 53 53 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[32.66 3" "2.66 38.66 32.66 38.66 38.66 38.66 32.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[26.66 26.66 32.66 " "32.66 26.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[20.66 20.66 26.66 26.66 20.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[14.66 14.66 20.66 14.66 20.66 20.66 14.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\n\ncol" "or('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register" SID "7638" Ports [2, 1] Position [325, 125, 365, 165] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "40,40,2,1,white,blue,0,140cc11c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'" "q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "7639" Ports [2, 1] Position [325, 180, 365, 220] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "40,40,2,1,white,blue,0,140cc11c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'" "q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "7640" Ports [2, 1] Position [325, 235, 365, 275] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "40,40,2,1,white,blue,0,140cc11c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'" "q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register3" SID "7641" Ports [2, 1] Position [325, 290, 365, 330] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "40,40,2,1,white,blue,0,140cc11c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'" "q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "7642" Position [640, 163, 670, 177] IconDisplay "Port number" } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "Register" SrcPort 1 Points [0, 0] Branch { Points [0, 25; -60, 0] DstBlock "Register1" DstPort 1 } Branch { DstBlock "Logical1" DstPort 1 } } Line { SrcBlock "Register1" SrcPort 1 Points [0, 0] Branch { Points [0, 25; -60, 0] DstBlock "Register2" DstPort 1 } Branch { Points [65, 0; 0, -40] DstBlock "Logical1" DstPort 2 } } Line { SrcBlock "Register2" SrcPort 1 Points [0, 0] Branch { Points [0, 25; -60, 0] DstBlock "Register3" DstPort 1 } Branch { Points [70, 0; 0, -80] DstBlock "Logical1" DstPort 3 } } Line { SrcBlock "Register3" SrcPort 1 Points [75, 0; 0, -120] DstBlock "Logical1" DstPort 4 } Line { SrcBlock "D" SrcPort 1 DstBlock "Register" DstPort 1 } Line { SrcBlock "R" SrcPort 1 Points [85, 0] Branch { DstBlock "Register" DstPort 2 } Branch { Points [0, 55] Branch { DstBlock "Register1" DstPort 2 } Branch { Points [0, 55] Branch { DstBlock "Register2" DstPort 2 } Branch { Points [0, 55] DstBlock "Register3" DstPort 2 } } } } } } Block { BlockType From Name "From6" SID "7643" Position [835, 145, 1035, 165] ShowName off CloseFcn "tagdialog Close" GotoTag "regRx_pktDetEn_Ext" TagVisibility "global" } Block { BlockType From Name "From9" SID "11288" Position [595, 329, 810, 351] ShowName off CloseFcn "tagdialog Close" GotoTag "MAC_PHY_BLOCK_PKT_DET" TagVisibility "global" } Block { BlockType Reference Name "Inverter" SID "11289" Ports [1, 1] Position [855, 331, 880, 349] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "7644" Ports [2, 1] Position [1315, 226, 1350, 284] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,58,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 58 58 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 58 58 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[34.55 34.55 39." "55 34.55 39.55 39.55 39.55 34.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[29.55 29.55 34.55 34.55 29." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[24.55 24.55 29.55 29.55 24.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[19.55 19.55 24.55 19.55 24.55 24.55 19.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('a" "nd');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "11291" Ports [2, 1] Position [1055, 261, 1090, 319] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,58,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 58 58 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 58 58 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[34.55 34.55 39." "55 34.55 39.55 39.55 39.55 34.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[29.55 29.55 34.55 34.55 29." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[24.55 24.55 29.55 29.55 24.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[19.55 19.55 24.55 19.55 24.55 24.55 19.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('a" "nd');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Posedge1" SID "7645" Ports [1, 1] Position [865, 266, 910, 284] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Posedge1" Location [88, 301, 2330, 1301] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "7646" Position [200, 253, 230, 267] IconDisplay "Port number" } Block { BlockType Reference Name "Delay" SID "7647" Ports [1, 1] Position [425, 153, 460, 177] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. " "If register retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[15" ".33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.33 12." "33 15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 12.33 " "9.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\nc" "olor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "7648" Ports [1, 1] Position [490, 156, 515, 174] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "7649" Ports [2, 1] Position [540, 151, 585, 204] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,53,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 53 53 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 53 53 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[32.66 3" "2.66 38.66 32.66 38.66 38.66 38.66 32.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[26.66 26.66 32.66 " "32.66 26.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[20.66 20.66 26.66 26.66 20.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[14.66 14.66 20.66 14.66 20.66 20.66 14.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('" "black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "7650" Position [610, 173, 640, 187] IconDisplay "Port number" } Line { SrcBlock "Delay" SrcPort 1 DstBlock "Inverter" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "D" SrcPort 1 Points [150, 0; 0, -70] Branch { Points [0, -25] DstBlock "Delay" DstPort 1 } Branch { DstBlock "Logical1" DstPort 2 } } Annotation { Name "Rising Edge Detection" Position [500, 112] } } } Block { BlockType Reference Name "Register1" SID "7651" Ports [1, 1] Position [520, 244, 550, 276] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,32,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 32 32 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 32 32 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[20.44 20.44 24.4" "4 20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[16.44 16.44 20.44 20.44 16.44 ]," "[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1 1 1 ]);\npatch([10.1" " 23.88 19.88 15.88 11.88 6.1 10.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\n" "color('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: en" "d icon text');" } Block { BlockType Reference Name "Register2" SID "7652" Ports [1, 1] Position [585, 244, 615, 276] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,32,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 32 32 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 32 32 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[20.44 20.44 24.4" "4 20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[16.44 16.44 20.44 20.44 16.44 ]," "[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1 1 1 ]);\npatch([10.1" " 23.88 19.88 15.88 11.88 6.1 10.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\n" "color('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: en" "d icon text');" } Block { BlockType Reference Name "Register3" SID "7653" Ports [1, 1] Position [585, 209, 615, 241] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,32,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 32 32 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 32 32 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[20.44 20.44 24.4" "4 20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[16.44 16.44 20.44 20.44 16.44 ]," "[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1 1 1 ]);\npatch([10.1" " 23.88 19.88 15.88 11.88 6.1 10.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\n" "color('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: en" "d icon text');" } Block { BlockType Reference Name "Register4" SID "7654" Ports [1, 1] Position [450, 244, 480, 276] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,32,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 32 32 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 32 32 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[20.44 20.44 24.4" "4 20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[16.44 16.44 20.44 20.44 16.44 ]," "[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1 1 1 ]);\npatch([10.1" " 23.88 19.88 15.88 11.88 6.1 10.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\n" "color('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: en" "d icon text');" } Block { BlockType Reference Name "Register5" SID "7655" Ports [1, 1] Position [520, 209, 550, 241] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,32,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 32 32 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 32 32 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[20.44 20.44 24.4" "4 20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[16.44 16.44 20.44 20.44 16.44 ]," "[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1 1 1 ]);\npatch([10.1" " 23.88 19.88 15.88 11.88 6.1 10.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\n" "color('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: en" "d icon text');" } Block { BlockType Reference Name "Register6" SID "11292" Ports [1, 1] Position [920, 324, 950, 356] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,32,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 32 32 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 32 32 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[20.44 20.44 24.4" "4 20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[16.44 16.44 20.44 20.44 16.44 ]," "[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1 1 1 ]);\npatch([10.1" " 23.88 19.88 15.88 11.88 6.1 10.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\n" "color('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: en" "d icon text');" } Block { BlockType SubSystem Name "S-R Latch" SID "7656" Ports [2, 1] Position [1155, 222, 1190, 313] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "S-R Latch" Location [160, 70, 1918, 1152] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "R" SID "7657" Position [140, 88, 170, 102] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "S" SID "7658" Position [140, 103, 170, 117] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "7659" Ports [0, 1] Position [195, 71, 210, 89] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "15,18,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11.22 " "13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 9.22 " "],[0.931 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([4.55 " "11.44 9.44 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "7660" Ports [3, 1] Position [255, 71, 300, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "7661" Position [325, 88, 355, 102] IconDisplay "Port number" } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "S" SrcPort 1 DstBlock "Register2" DstPort 3 } } } Block { BlockType Reference Name "pkt_det_in" SID "7662" Ports [1, 1] Position [330, 250, 395, 270] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to Xilin" "x fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top level input" " ports." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.6" "5 ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12.22 12.22" " 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 12.22 12.22" " 10.22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\n" "patch([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('inpu" "t',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT:" " end icon text');" } Block { BlockType Outport Name "Det" SID "7663" Position [1435, 248, 1465, 262] IconDisplay "Port number" } Line { SrcBlock "Constant" SrcPort 1 DstBlock "pkt_det_in" DstPort 1 } Line { SrcBlock "S-R Latch" SrcPort 1 DstBlock "Logical1" DstPort 2 } Line { SrcBlock "Posedge1" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Reset" SrcPort 1 DstBlock "Register5" DstPort 1 } Line { SrcBlock "Debouce" SrcPort 1 DstBlock "Posedge1" DstPort 1 } Line { SrcBlock "pkt_det_in" SrcPort 1 DstBlock "Register4" DstPort 1 } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Det" DstPort 1 } Line { SrcBlock "From6" SrcPort 1 Points [155, 0; 0, 85] DstBlock "Convert2" DstPort 1 } Line { SrcBlock "Convert" SrcPort 1 DstBlock "S-R Latch" DstPort 1 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Logical2" DstPort 1 } Line { SrcBlock "Convert2" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Register4" SrcPort 1 DstBlock "Register1" DstPort 1 } Line { SrcBlock "Register1" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Debouce" DstPort 1 } Line { SrcBlock "Register3" SrcPort 1 Points [85, 0] Branch { Points [0, 60] DstBlock "Debouce" DstPort 2 } Branch { Points [230, 0; 0, 20] DstBlock "Convert" DstPort 1 } } Line { SrcBlock "Register5" SrcPort 1 DstBlock "Register3" DstPort 1 } Line { SrcBlock "From9" SrcPort 1 DstBlock "Inverter" DstPort 1 } Line { SrcBlock "Logical2" SrcPort 1 DstBlock "S-R Latch" DstPort 2 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Register6" DstPort 1 } Line { SrcBlock "Register6" SrcPort 1 Points [5, 0; 0, -35] DstBlock "Logical2" DstPort 2 } } } Block { BlockType From Name "From" SID "7664" Position [380, 412, 440, 428] ZOrder -9 ShowName off GotoTag "RFA_I" } Block { BlockType From Name "From1" SID "7665" Position [380, 427, 440, 443] ZOrder -9 ShowName off GotoTag "RFA_Q" } Block { BlockType From Name "From10" SID "7666" Position [380, 722, 440, 738] ZOrder -9 ShowName off GotoTag "RFC_IQ_V" } Block { BlockType From Name "From11" SID "7667" Position [380, 737, 440, 753] ZOrder -9 ShowName off GotoTag "RFC_RSSI" } Block { BlockType From Name "From12" SID "7668" Position [380, 807, 440, 823] ZOrder -9 ShowName off GotoTag "RFD_IQ_V" } Block { BlockType From Name "From13" SID "7669" Position [380, 822, 440, 838] ZOrder -9 ShowName off GotoTag "RFD_RSSI" } Block { BlockType From Name "From14" SID "7670" Position [380, 777, 440, 793] ZOrder -9 ShowName off GotoTag "RFD_I" } Block { BlockType From Name "From15" SID "7671" Position [380, 792, 440, 808] ZOrder -9 ShowName off GotoTag "RFD_Q" } Block { BlockType From Name "From16" SID "7672" Position [165, 17, 380, 33] ShowName off CloseFcn "tagdialog Close" GotoTag "regRx_pktDet_requireBoth_OFDM" TagVisibility "global" } Block { BlockType From Name "From17" SID "15797" Position [165, 92, 380, 108] ShowName off CloseFcn "tagdialog Close" GotoTag "regRx_pktDet_requireBoth_DSSS" TagVisibility "global" } Block { BlockType From Name "From18" SID "17471" Position [785, 592, 1000, 608] ShowName off CloseFcn "tagdialog Close" GotoTag "regRx_Reset_PktDetCounts" TagVisibility "global" } Block { BlockType From Name "From2" SID "7673" Position [380, 442, 440, 458] ZOrder -9 ShowName off GotoTag "RFA_IQ_V" } Block { BlockType From Name "From3" SID "7674" Position [380, 457, 440, 473] ZOrder -9 ShowName off GotoTag "RFA_RSSI" } Block { BlockType From Name "From4" SID "7675" Position [380, 562, 440, 578] ZOrder -9 ShowName off GotoTag "RFB_I" } Block { BlockType From Name "From5" SID "7676" Position [380, 577, 440, 593] ZOrder -9 ShowName off GotoTag "RFB_Q" } Block { BlockType From Name "From6" SID "7677" Position [380, 592, 440, 608] ZOrder -9 ShowName off GotoTag "RFB_IQ_V" } Block { BlockType From Name "From7" SID "7678" Position [380, 607, 440, 623] ZOrder -9 ShowName off GotoTag "RFB_RSSI" } Block { BlockType From Name "From8" SID "7679" Position [380, 692, 440, 708] ZOrder -9 ShowName off GotoTag "RFC_I" } Block { BlockType From Name "From9" SID "7680" Position [380, 707, 440, 723] ZOrder -9 ShowName off GotoTag "RFC_Q" } Block { BlockType Goto Name "Goto" SID "7681" Position [245, 397, 305, 413] ZOrder -10 ShowName off GotoTag "RFA_I" TagVisibility "local" } Block { BlockType Goto Name "Goto1" SID "7682" Position [245, 412, 305, 428] ZOrder -10 ShowName off GotoTag "RFB_I" TagVisibility "local" } Block { BlockType Goto Name "Goto10" SID "7683" Position [245, 612, 305, 628] ZOrder -10 ShowName off GotoTag "RFC_IQ_V" TagVisibility "local" } Block { BlockType Goto Name "Goto11" SID "7684" Position [245, 627, 305, 643] ZOrder -10 ShowName off GotoTag "RFD_IQ_V" TagVisibility "local" } Block { BlockType Goto Name "Goto12" SID "7685" Position [245, 702, 305, 718] ZOrder -10 ShowName off GotoTag "RFA_RSSI" TagVisibility "local" } Block { BlockType Goto Name "Goto13" SID "7686" Position [245, 717, 305, 733] ZOrder -10 ShowName off GotoTag "RFB_RSSI" TagVisibility "local" } Block { BlockType Goto Name "Goto14" SID "7687" Position [245, 732, 305, 748] ZOrder -10 ShowName off GotoTag "RFC_RSSI" TagVisibility "local" } Block { BlockType Goto Name "Goto15" SID "7688" Position [245, 747, 305, 763] ZOrder -10 ShowName off GotoTag "RFD_RSSI" TagVisibility "local" } Block { BlockType Goto Name "Goto16" SID "7689" Position [650, 45, 835, 65] ShowName off GotoTag "regRx_pktDet_requireBothB_OFDM" TagVisibility "global" } Block { BlockType Goto Name "Goto17" SID "15798" Position [650, 120, 835, 140] ShowName off GotoTag "regRx_pktDet_requireBothB_DSSS" TagVisibility "global" } Block { BlockType Goto Name "Goto18" SID "15799" Position [650, 90, 835, 110] ShowName off GotoTag "regRx_pktDet_requireBothA_DSSS" TagVisibility "global" } Block { BlockType Goto Name "Goto19" SID "17472" Position [1315, 605, 1500, 625] ShowName off GotoTag "regRx_PktDetCount_OFDM" TagVisibility "global" } Block { BlockType Goto Name "Goto2" SID "7690" Position [245, 427, 305, 443] ZOrder -10 ShowName off GotoTag "RFC_I" TagVisibility "local" } Block { BlockType Goto Name "Goto20" SID "17473" Position [1315, 690, 1500, 710] ShowName off GotoTag "regRx_PktDetCount_DSSS" TagVisibility "global" } Block { BlockType Goto Name "Goto22" SID "7691" Position [650, 15, 835, 35] ShowName off GotoTag "regRx_pktDet_requireBothA_OFDM" TagVisibility "global" } Block { BlockType Goto Name "Goto3" SID "7692" Position [245, 442, 305, 458] ZOrder -10 ShowName off GotoTag "RFD_I" TagVisibility "local" } Block { BlockType Goto Name "Goto4" SID "7693" Position [245, 492, 305, 508] ZOrder -10 ShowName off GotoTag "RFA_Q" TagVisibility "local" } Block { BlockType Goto Name "Goto5" SID "7694" Position [245, 507, 305, 523] ZOrder -10 ShowName off GotoTag "RFB_Q" TagVisibility "local" } Block { BlockType Goto Name "Goto6" SID "7695" Position [245, 522, 305, 538] ZOrder -10 ShowName off GotoTag "RFC_Q" TagVisibility "local" } Block { BlockType Goto Name "Goto7" SID "7696" Position [245, 537, 305, 553] ZOrder -10 ShowName off GotoTag "RFD_Q" TagVisibility "local" } Block { BlockType Goto Name "Goto8" SID "7697" Position [245, 582, 305, 598] ZOrder -10 ShowName off GotoTag "RFA_IQ_V" TagVisibility "local" } Block { BlockType Goto Name "Goto9" SID "7698" Position [245, 597, 305, 613] ZOrder -10 ShowName off GotoTag "RFB_IQ_V" TagVisibility "local" } Block { BlockType Reference Name "Inverter2" SID "18156" Ports [1, 1] Position [415, 211, 440, 229] BlockMirror on ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.2" "2 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 " "11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);" "\npatch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('no" "t');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "LTF Only Det" SID "18033" Ports [2, 1] Position [505, 278, 580, 307] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "LTF Only Det" Location [202, 70, 1833, 1180] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "LTF Det" SID "18074" Position [280, 273, 310, 287] IconDisplay "Port number" } Block { BlockType Inport Name "Reset" SID "18034" Position [280, 243, 310, 257] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Convert" SID "18036" Ports [1, 1] Position [595, 241, 620, 259] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "16" bin_pt "14" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cast');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "18037" Ports [1, 1] Position [595, 271, 620, 289] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "16" bin_pt "14" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cast');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From1" SID "18077" Position [240, 200, 440, 220] ShowName off CloseFcn "tagdialog Close" GotoTag "regRx_OFDM_Rx_Req_Pkt_Det" TagVisibility "global" } Block { BlockType From Name "From9" SID "18049" Position [225, 329, 440, 351] ShowName off CloseFcn "tagdialog Close" GotoTag "MAC_PHY_BLOCK_PKT_DET" TagVisibility "global" } Block { BlockType Reference Name "Inverter" SID "18050" Ports [1, 1] Position [485, 331, 510, 349] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Inverter1" SID "18095" Ports [1, 1] Position [755, 151, 780, 169] BlockMirror on ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "18078" Ports [2, 1] Position [685, 206, 720, 264] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,58,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 58 58 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 58 58 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[34.55 34.55 39." "55 34.55 39.55 39.55 39.55 34.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[29.55 29.55 34.55 34.55 29." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[24.55 24.55 29.55 29.55 24.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[19.55 19.55 24.55 19.55 24.55 24.55 19.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('o" "r');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "18052" Ports [2, 1] Position [685, 266, 720, 324] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,58,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 58 58 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 58 58 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[34.55 34.55 39." "55 34.55 39.55 39.55 39.55 34.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[29.55 29.55 34.55 34.55 29." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[24.55 24.55 29.55 29.55 24.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[19.55 19.55 24.55 19.55 24.55 24.55 19.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('a" "nd');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical3" SID "18094" Ports [2, 1] Position [625, 166, 660, 224] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,58,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 58 58 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 58 58 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[34.55 34.55 39." "55 34.55 39.55 39.55 39.55 34.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[29.55 29.55 34.55 34.55 29." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[24.55 24.55 29.55 29.55 24.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[19.55 19.55 24.55 19.55 24.55 24.55 19.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('a" "nd');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Posedge1" SID "18053" Ports [1, 1] Position [495, 271, 540, 289] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Posedge1" Location [88, 301, 2330, 1301] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "18054" Position [200, 253, 230, 267] IconDisplay "Port number" } Block { BlockType Reference Name "Delay" SID "18055" Ports [1, 1] Position [425, 153, 460, 177] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. " "If register retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[15" ".33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.33 12." "33 15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 12.33 " "9.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\nc" "olor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "18056" Ports [1, 1] Position [490, 156, 515, 174] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "18057" Ports [2, 1] Position [540, 151, 585, 204] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,53,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 53 53 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 53 53 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[32.66 3" "2.66 38.66 32.66 38.66 38.66 38.66 32.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[26.66 26.66 32.66 " "32.66 26.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[20.66 20.66 26.66 26.66 20.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[14.66 14.66 20.66 14.66 20.66 20.66 14.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('" "black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "18058" Position [610, 173, 640, 187] IconDisplay "Port number" } Line { SrcBlock "D" SrcPort 1 Points [150, 0; 0, -70] Branch { DstBlock "Logical1" DstPort 2 } Branch { Points [0, -25] DstBlock "Delay" DstPort 1 } } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Delay" SrcPort 1 DstBlock "Inverter" DstPort 1 } Annotation { Name "Rising Edge Detection" Position [500, 112] } } } Block { BlockType Reference Name "Register6" SID "18064" Ports [1, 1] Position [550, 324, 580, 356] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,32,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 32 32 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 32 32 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[20.44 20.44 24.4" "4 20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[16.44 16.44 20.44 20.44 16.44 ]," "[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1 1 1 ]);\npatch([10.1" " 23.88 19.88 15.88 11.88 6.1 10.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\n" "color('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: en" "d icon text');" } Block { BlockType SubSystem Name "S-R Latch" SID "18065" Ports [2, 1] Position [785, 227, 820, 318] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "S-R Latch" Location [160, 70, 1918, 1152] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "R" SID "18066" Position [140, 88, 170, 102] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "S" SID "18067" Position [140, 103, 170, 117] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "18068" Ports [0, 1] Position [195, 71, 210, 89] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "15,18,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11.22 " "13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 9.22 " "],[0.931 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([4.55 " "11.44 9.44 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "18069" Ports [3, 1] Position [255, 71, 300, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "18070" Position [325, 88, 355, 102] IconDisplay "Port number" } Line { SrcBlock "S" SrcPort 1 DstBlock "Register2" DstPort 3 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Register2" DstPort 1 } } } Block { BlockType Outport Name "Det" SID "18072" Position [905, 268, 935, 282] IconDisplay "Port number" } Line { SrcBlock "Register6" SrcPort 1 Points [5, 0; 0, -30] DstBlock "Logical2" DstPort 2 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Register6" DstPort 1 } Line { SrcBlock "Logical2" SrcPort 1 DstBlock "S-R Latch" DstPort 2 } Line { SrcBlock "From9" SrcPort 1 DstBlock "Inverter" DstPort 1 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Logical2" DstPort 1 } Line { SrcBlock "Convert" SrcPort 1 DstBlock "Logical1" DstPort 2 } Line { SrcBlock "LTF Det" SrcPort 1 DstBlock "Posedge1" DstPort 1 } Line { SrcBlock "Reset" SrcPort 1 DstBlock "Convert" DstPort 1 } Line { SrcBlock "Posedge1" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "S-R Latch" SrcPort 1 Points [45, 0] Branch { DstBlock "Det" DstPort 1 } Branch { Points [0, -115] DstBlock "Inverter1" DstPort 1 } } Line { SrcBlock "From1" SrcPort 1 DstBlock "Logical3" DstPort 2 } Line { SrcBlock "Logical1" SrcPort 1 Points [20, 0; 0, 15] DstBlock "S-R Latch" DstPort 1 } Line { SrcBlock "Inverter1" SrcPort 1 Points [-140, 0] DstBlock "Logical3" DstPort 1 } Line { SrcBlock "Logical3" SrcPort 1 Points [0, 25] DstBlock "Logical1" DstPort 1 } Annotation { Name "Ignore config bit until current Rx is done" Position [740, 139] } } } Block { BlockType Reference Name "Logical1" SID "7699" Ports [3, 1] Position [875, 361, 910, 419] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,58,3,1,white,blue,0,a2abe52d,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 58 58 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 58 58 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[34.55" " 34.55 39.55 34.55 39.55 39.55 39.55 34.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[29.55 29.55 34" ".55 34.55 29.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[24.55 24.55 29.55 29.55 24.55 " "],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[19.55 19.55 24.55 19.55 24.55 24.55 19.55 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n" "\ncolor('black');disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "18092" Ports [2, 1] Position [875, 296, 910, 354] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,58,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 58 58 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 58 58 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[34.55" " 34.55 39.55 34.55 39.55 39.55 39.55 34.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[29.55 29.55 34" ".55 34.55 29.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[24.55 24.55 29.55 29.55 24.55 " "],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[19.55 19.55 24.55 19.55 24.55 24.55 19.55 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n" "color('black');disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical4" SID "18157" Ports [2, 1] Position [410, 241, 445, 299] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,58,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 58 58 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 58 58 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[34.55" " 34.55 39.55 34.55 39.55 39.55 39.55 34.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[29.55 29.55 34" ".55 34.55 29.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[24.55 24.55 29.55 29.55 24.55 " "],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[19.55 19.55 24.55 19.55 24.55 24.55 19.55 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n" "color('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "OFDM Ant Sel Logic" SID "7700" Ports [6, 1] Position [725, 378, 795, 442] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "OFDM Ant Sel Logic" Location [537, 726, 1202, 901] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "LTF Det" SID "18075" Position [370, 183, 400, 197] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "Ext Det" SID "7701" Position [370, 203, 400, 217] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "Det A" SID "7702" Position [370, 353, 400, 367] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "Det B" SID "7703" Position [370, 418, 400, 432] Port "4" IconDisplay "Port number" } Block { BlockType Inport Name "Det C" SID "7704" Position [370, 483, 400, 497] Port "5" IconDisplay "Port number" } Block { BlockType Inport Name "Det D" SID "7705" Position [370, 548, 400, 562] Port "6" IconDisplay "Port number" } Block { BlockType Reference Name "Concat" SID "7706" Ports [6, 1] Position [900, 180, 945, 300] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point at z" "ero." num_inputs "6" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "45,120,6,1,white,blue,0,c44eeefa,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 120 120 0 ],[0.77 0.82 0" ".91 ]);\nplot([0 45 45 0 0 ],[0 0 120 120 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[66.66 66." "66 72.66 66.66 72.66 72.66 72.66 66.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[60.66 60.66 66.66 66.6" "6 60.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[54.66 54.66 60.66 60.66 54.66 ],[1 1 1 ]);" "\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[48.66 48.66 54.66 48.66 54.66 54.66 48.66 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_lab" "el('input',1,'hi');\n\n\n\n\ncolor('black');port_label('input',6,'lo');\n\ncolor('black');disp('\\fontsize{20}\\}'" ",'texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From1" SID "7707" Position [445, 385, 645, 405] ShowName off CloseFcn "tagdialog Close" GotoTag "regRx_pktDetEn_RFB" TagVisibility "global" } Block { BlockType From Name "From2" SID "7708" Position [445, 450, 645, 470] ShowName off CloseFcn "tagdialog Close" GotoTag "regRx_pktDetEn_RFC" TagVisibility "global" } Block { BlockType From Name "From3" SID "7709" Position [445, 515, 645, 535] ShowName off CloseFcn "tagdialog Close" GotoTag "regRx_pktDetEn_RFD" TagVisibility "global" } Block { BlockType From Name "From6" SID "7710" Position [445, 320, 645, 340] ShowName off CloseFcn "tagdialog Close" GotoTag "regRx_pktDetEn_RFA" TagVisibility "global" } Block { BlockType Goto Name "Goto" SID "7711" Position [1040, 229, 1175, 251] ZOrder -10 ShowName off GotoTag "PKTDET_STATUS_OFDM" TagVisibility "global" } Block { BlockType Reference Name "Logical" SID "7712" Ports [2, 1] Position [680, 316, 715, 374] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,58,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 58 58 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 58 58 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[34.55 34.55 39." "55 34.55 39.55 39.55 39.55 34.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[29.55 29.55 34.55 34.55 29." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[24.55 24.55 29.55 29.55 24.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[19.55 19.55 24.55 19.55 24.55 24.55 19.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('a" "nd');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "7713" Ports [4, 1] Position [905, 338, 940, 397] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "4" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,59,4,1,white,blue,0,4f3eee2e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 59 59 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 59 59 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[34.55 34.55 39." "55 34.55 39.55 39.55 39.55 34.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[29.55 29.55 34.55 34.55 29." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[24.55 24.55 29.55 29.55 24.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[19.55 19.55 24.55 19.55 24.55 24.55 19.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\n\ncolor('black');dis" "p('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "7714" Ports [2, 1] Position [680, 381, 715, 439] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,58,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 58 58 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 58 58 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[34.55 34.55 39." "55 34.55 39.55 39.55 39.55 34.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[29.55 29.55 34.55 34.55 29." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[24.55 24.55 29.55 29.55 24.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[19.55 19.55 24.55 19.55 24.55 24.55 19.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('a" "nd');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical3" SID "7715" Ports [2, 1] Position [680, 446, 715, 504] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,58,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 58 58 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 58 58 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[34.55 34.55 39." "55 34.55 39.55 39.55 39.55 34.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[29.55 29.55 34.55 34.55 29." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[24.55 24.55 29.55 29.55 24.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[19.55 19.55 24.55 19.55 24.55 24.55 19.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('a" "nd');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical4" SID "7716" Ports [2, 1] Position [680, 511, 715, 569] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,58,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 58 58 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 58 58 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[34.55 34.55 39." "55 34.55 39.55 39.55 39.55 34.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[29.55 29.55 34.55 34.55 29." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[24.55 24.55 29.55 29.55 24.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[19.55 19.55 24.55 19.55 24.55 24.55 19.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('a" "nd');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Pkt Det" SID "7717" Position [995, 362, 1025, 378] NamePlacement "alternate" IconDisplay "Port number" } Line { SrcBlock "From6" SrcPort 1 DstBlock "Logical" DstPort 1 } Line { SrcBlock "Logical" SrcPort 1 Points [115, 0] Branch { DstBlock "Logical1" DstPort 1 } Branch { Points [0, -55] DstBlock "Concat" DstPort 6 } } Line { SrcBlock "Logical2" SrcPort 1 Points [15, 0; 0, -50; 95, 0] Branch { DstBlock "Logical1" DstPort 2 } Branch { Points [0, -90] DstBlock "Concat" DstPort 5 } } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Pkt Det" DstPort 1 } Line { SrcBlock "Det A" SrcPort 1 DstBlock "Logical" DstPort 2 } Line { SrcBlock "Det B" SrcPort 1 DstBlock "Logical2" DstPort 2 } Line { SrcBlock "From1" SrcPort 1 DstBlock "Logical2" DstPort 1 } Line { SrcBlock "From2" SrcPort 1 DstBlock "Logical3" DstPort 1 } Line { SrcBlock "From3" SrcPort 1 DstBlock "Logical4" DstPort 1 } Line { SrcBlock "Det C" SrcPort 1 DstBlock "Logical3" DstPort 2 } Line { SrcBlock "Det D" SrcPort 1 DstBlock "Logical4" DstPort 2 } Line { SrcBlock "Logical3" SrcPort 1 Points [25, 0; 0, -100; 80, 0] Branch { DstBlock "Logical1" DstPort 3 } Branch { Points [0, -125] DstBlock "Concat" DstPort 4 } } Line { SrcBlock "Logical4" SrcPort 1 Points [40, 0; 0, -150; 60, 0] Branch { DstBlock "Logical1" DstPort 4 } Branch { Points [0, -160] DstBlock "Concat" DstPort 3 } } Line { SrcBlock "Concat" SrcPort 1 DstBlock "Goto" DstPort 1 } Line { SrcBlock "Ext Det" SrcPort 1 DstBlock "Concat" DstPort 2 } Line { SrcBlock "LTF Det" SrcPort 1 DstBlock "Concat" DstPort 1 } } } Block { BlockType SubSystem Name "Posedge1" SID "17458" Ports [1, 1] Position [1035, 621, 1080, 639] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Posedge1" Location [88, 301, 2330, 1301] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "17459" Position [200, 253, 230, 267] IconDisplay "Port number" } Block { BlockType Reference Name "Delay" SID "17460" Ports [1, 1] Position [425, 153, 460, 177] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. If r" "egister retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[15.33 15" ".33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.33 12.33 15.33" " 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 " "1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');" "disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "17461" Ports [1, 1] Position [490, 156, 515, 174] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "17462" Ports [2, 1] Position [540, 151, 585, 204] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,53,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 53 53 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 53 53 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[32.66 32.66 3" "8.66 32.66 38.66 38.66 38.66 32.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[26.66 26.66 32.66 32.66 26" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[20.66 20.66 26.66 26.66 20.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[14.66 14.66 20.66 14.66 20.66 20.66 14.66 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('" "and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "17463" Position [610, 173, 640, 187] IconDisplay "Port number" } Line { SrcBlock "Delay" SrcPort 1 DstBlock "Inverter" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "D" SrcPort 1 Points [150, 0; 0, -70] Branch { Points [0, -25] DstBlock "Delay" DstPort 1 } Branch { DstBlock "Logical1" DstPort 2 } } Annotation { Name "Rising Edge Detection" Position [500, 112] } } } Block { BlockType SubSystem Name "Posedge2" SID "17465" Ports [1, 1] Position [1035, 706, 1080, 724] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Posedge2" Location [88, 301, 2330, 1301] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "17466" Position [200, 253, 230, 267] IconDisplay "Port number" } Block { BlockType Reference Name "Delay" SID "17467" Ports [1, 1] Position [425, 153, 460, 177] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. If r" "egister retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[15.33 15" ".33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.33 12.33 15.33" " 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 " "1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');" "disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "17468" Ports [1, 1] Position [490, 156, 515, 174] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "17469" Ports [2, 1] Position [540, 151, 585, 204] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,53,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 53 53 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 53 53 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[32.66 32.66 3" "8.66 32.66 38.66 38.66 38.66 32.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[26.66 26.66 32.66 32.66 26" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[20.66 20.66 26.66 26.66 20.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[14.66 14.66 20.66 14.66 20.66 20.66 14.66 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('" "and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "17470" Position [610, 173, 640, 187] IconDisplay "Port number" } Line { SrcBlock "D" SrcPort 1 Points [150, 0; 0, -70] Branch { DstBlock "Logical1" DstPort 2 } Branch { Points [0, -25] DstBlock "Delay" DstPort 1 } } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Delay" SrcPort 1 DstBlock "Inverter" DstPort 1 } Annotation { Name "Rising Edge Detection" Position [500, 112] } } } Block { BlockType SubSystem Name "RF A Det" SID "7718" Ports [6, 2] Position [495, 381, 595, 474] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "RF A Det" Location [432, 425, 1027, 612] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Reset OFDM" SID "7719" Position [340, 263, 370, 277] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "Reset DSSS" SID "7720" Position [340, 303, 370, 317] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "Rx I" SID "7721" Position [275, 358, 305, 372] NamePlacement "alternate" Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "Rx Q" SID "7722" Position [275, 373, 305, 387] Port "4" IconDisplay "Port number" } Block { BlockType Inport Name "IQ Valid" SID "7723" Position [340, 388, 370, 402] Port "5" IconDisplay "Port number" } Block { BlockType Inport Name "RSSI" SID "7724" Position [340, 458, 370, 472] Port "6" IconDisplay "Port number" } Block { BlockType SubSystem Name "Auto-Corr Pkt Det" SID "7725" Ports [5, 2] Position [535, 321, 665, 409] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Auto-Corr Pkt Det" Location [227, 108, 1983, 1242] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "121" Block { BlockType Inport Name "Reset OFDM" SID "7726" Position [490, 93, 520, 107] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "Reset DSSS" SID "7727" Position [490, 133, 520, 147] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "rx_I" SID "7728" Position [85, 233, 115, 247] NamePlacement "alternate" Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "rx_Q" SID "7729" Position [85, 258, 115, 272] Port "4" IconDisplay "Port number" } Block { BlockType Inport Name "rx_valid" SID "7730" Position [125, 208, 155, 222] NamePlacement "alternate" Port "5" IconDisplay "Port number" Port { PortNumber 1 ShowPropagatedSignals "on" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType SubSystem Name "Auto Corr" SID "7731" Ports [3, 2] Position [635, 199, 705, 281] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Auto Corr" Location [227, 108, 1983, 1242] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "156" Block { BlockType Inport Name "Valid" SID "7732" Position [225, 258, 255, 272] IconDisplay "Port number" } Block { BlockType Inport Name "I" SID "7733" Position [225, 323, 255, 337] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "Q" SID "7734" Position [225, 358, 255, 372] Port "3" IconDisplay "Port number" } Block { BlockType SubSystem Name "Avg Mag" SID "7735" Ports [2, 1] Position [680, 304, 720, 386] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Avg Mag" Location [227, 108, 1983, 1242] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "151" Block { BlockType Inport Name "Valid" SID "7736" Position [225, 298, 255, 312] IconDisplay "Port number" } Block { BlockType Inport Name "I" SID "7737" Position [230, 348, 260, 362] Port "2" IconDisplay "Port number" } Block { BlockType Scope Name "Auto Corr Calc" SID "15909" Ports [9] Position [760, 500, 805, 650] Floating off Location [1, 45, 1836, 1199] Open off NumInputPorts "9" ZoomMode "yonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" axes9 "%" } List { ListType ScopeGraphics FigureColor "[0.5 0.5 0.5]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "17540 " YMin "-0.04~-0.05~0.002~0~-1~-1~-1~-1~-1" YMax "0.05~0.05~0.01~0.007~1~1~1~1~1" SaveName "ScopeData56" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType Reference Name "Register" SID "7745" Ports [2, 1] Position [470, 338, 495, 362] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,24,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 24 24 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 24 24 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[15.33 " "15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[12.33 12.33 15.33" " 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 1 " "1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\nco" "lor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Running Sum" SID "7747" Ports [2, 2] Position [365, 338, 430, 362] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Running Sum" Location [227, 108, 1983, 1242] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "En" SID "7748" Position [195, 183, 225, 197] IconDisplay "Port number" } Block { BlockType Inport Name "D" SID "7749" Position [195, 123, 225, 137] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Accum1" SID "7750" Ports [2, 1] Position [485, 131, 535, 184] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Accumulator" SourceType "Xilinx Accumulator Block" infoedit "Adder or subtracter-based accumulator. Output type and binary point position match the input.
Hardware notes: When \"Reinitialize with input 'b' on reset\" is selected, the accumulator is forced to ru" "n at the system rate even if the input 'b' is running at a slower rate." operation "Add" n_bits "27" overflow "Flag as error" scale "1" rst off infoeditControl "reset for floating point data type must be asserted for a minimum of 2 cycles" hasbypass off en on latency "0" dbl_ovrd off msb_inp "100" msb "100" lsb "-100" use_behavioral_HDL on implementation "Fabric" xl_use_area off xl_area "[12 23 0 22 0 0 0]" has_advanced_control "0" sggui_pos "20,20,367,457" block_type "accum" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,53,2,1,white,blue,0,debef366,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 53 53 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 53 53 0 ]);\npatch([9.425 19.54 26.54 33.54 40.54 26.54 16.425 9.425 ],[33.7" "7 33.77 40.77 33.77 40.77 40.77 40.77 33.77 ],[1 1 1 ]);\npatch([16.425 26.54 19.54 9.425 16.425 ],[26.77 26.77 " "33.77 33.77 26.77 ],[0.931 0.946 0.973 ]);\npatch([9.425 19.54 26.54 16.425 9.425 ],[19.77 19.77 26.77 26.77 19." "77 ],[1 1 1 ]);\npatch([16.425 40.54 33.54 26.54 19.54 9.425 16.425 ],[12.77 12.77 19.77 12.77 19.77 19.77 12.77" " ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nc" "olor('black');port_label('input',1,'b');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label(" "'output',1,'\\bf+=b','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "AddSub1" SID "7751" Ports [2, 1] Position [360, 117, 410, 168] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Subtraction" use_carryin off use_carryout off en off latency "1" precision "Full" arith_type "Signed (2's comp)" n_bits "36" bin_pt "28" quantization "Truncate" overflow "Saturate" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[9 18 0 17 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,344" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,51,2,1,white,blue,0,8a00a986,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 51 51 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 51 51 0 ]);\npatch([9.425 19.54 26.54 33.54 40.54 26.54 16.425 9.425 ],[32.7" "7 32.77 39.77 32.77 39.77 39.77 39.77 32.77 ],[1 1 1 ]);\npatch([16.425 26.54 19.54 9.425 16.425 ],[25.77 25.77 " "32.77 32.77 25.77 ],[0.931 0.946 0.973 ]);\npatch([9.425 19.54 26.54 16.425 9.425 ],[18.77 18.77 25.77 25.77 18." "77 ],[1 1 1 ]);\npatch([16.425 40.54 33.54 26.54 19.54 9.425 16.425 ],[11.77 11.77 18.77 11.77 18.77 18.77 11.77" " ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nc" "olor('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('" "output',1,'\\bf{a - b}','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black'" ");disp(' \\newline\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay" SID "7752" Ports [1, 1] Position [375, 178, 400, 202] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[7 14 0 14 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 24 24 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 24 24 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[15.33 " "15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[12.33 12.33 15.33" " 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 1 " "1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');di" "sp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay1" SID "7753" Ports [1, 1] Position [495, 198, 520, 222] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[7 14 0 14 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 24 24 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 24 24 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[15.33 " "15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[12.33 12.33 15.33" " 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 1 " "1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');di" "sp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay2" SID "7754" Ports [1, 1] Position [605, 198, 630, 222] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[7 14 0 14 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 24 24 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 24 24 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[15.33 " "15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[12.33 12.33 15.33" " 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 1 " "1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');di" "sp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay6" SID "7755" Ports [2, 1] Position [265, 143, 300, 167] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en on latency "16" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[9 17 0 17 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,24,2,1,white,blue,0,68dbc054,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[15" ".33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.33 12." "33 15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 12.33 " "9.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncol" "or('black');port_label('input',2,'en');\n\ncolor('black');disp('z^{-16}','texmode','on');\nfprintf('','COMMENT: " "end icon text');" } Block { BlockType Reference Name "Register" SID "7756" Ports [1, 1] Position [600, 142, 635, 178] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,36,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 36 36 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 36 36 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[23.55 23." "55 28.55 23.55 28.55 28.55 28.55 23.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[18.55 18.55 23.55 2" "3.55 18.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[13.55 13.55 18.55 18.55 13.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[8.55 8.55 13.55 8.55 13.55 13.55 8.55 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');por" "t_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Sum" SID "7758" Position [710, 153, 740, 167] IconDisplay "Port number" } Block { BlockType Outport Name "Valid" SID "7757" Position [710, 203, 740, 217] Port "2" IconDisplay "Port number" } Line { SrcBlock "Delay6" SrcPort 1 DstBlock "AddSub1" DstPort 2 } Line { SrcBlock "AddSub1" SrcPort 1 DstBlock "Accum1" DstPort 1 } Line { SrcBlock "D" SrcPort 1 Points [0, 0; 15, 0] Branch { DstBlock "AddSub1" DstPort 1 } Branch { Points [0, 20] DstBlock "Delay6" DstPort 1 } } Line { SrcBlock "Accum1" SrcPort 1 DstBlock "Register" DstPort 1 } Line { SrcBlock "Register" SrcPort 1 DstBlock "Sum" DstPort 1 } Line { SrcBlock "En" SrcPort 1 Points [10, 0] Branch { Points [0, -30] DstBlock "Delay6" DstPort 2 } Branch { DstBlock "Delay" DstPort 1 } } Line { SrcBlock "Delay" SrcPort 1 Points [50, 0] Branch { Points [0, -20] DstBlock "Accum1" DstPort 2 } Branch { Points [0, 20] DstBlock "Delay1" DstPort 1 } } Line { SrcBlock "Delay1" SrcPort 1 DstBlock "Delay2" DstPort 1 } Line { SrcBlock "Delay2" SrcPort 1 DstBlock "Valid" DstPort 1 } } } Block { BlockType Reference Name "done1" SID "15912" Ports [1, 1] Position [550, 540, 585, 550] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Running Sum I" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "done4" SID "15911" Ports [1, 1] Position [550, 510, 585, 520] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Conj Mult I" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Outport Name "M" SID "7771" Position [565, 343, 595, 357] IconDisplay "Port number" } Line { SrcBlock "Running Sum" SrcPort 1 Points [10, 0] Branch { DstBlock "Register" DstPort 1 } Branch { Points [0, 200] DstBlock "done1" DstPort 1 } } Line { SrcBlock "I" SrcPort 1 Points [50, 0] Branch { DstBlock "Running Sum" DstPort 2 } Branch { Points [0, 160] DstBlock "done4" DstPort 1 } } Line { SrcBlock "Valid" SrcPort 1 Points [90, 0] DstBlock "Running Sum" DstPort 1 } Line { Name "Conj Mult I" Labels [0, 0] SrcBlock "done4" SrcPort 1 DstBlock "Auto Corr Calc" DstPort 1 } Line { Name "Running Sum I" Labels [0, 0] SrcBlock "done1" SrcPort 1 DstBlock "Auto Corr Calc" DstPort 3 } Line { SrcBlock "Running Sum" SrcPort 2 DstBlock "Register" DstPort 2 } Line { SrcBlock "Register" SrcPort 1 DstBlock "M" DstPort 1 } } } Block { BlockType SubSystem Name "Avg Mag1" SID "15932" Ports [2, 1] Position [680, 489, 720, 571] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Avg Mag1" Location [202, 70, 1833, 1180] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "151" Block { BlockType Inport Name "Valid" SID "15933" Position [225, 298, 255, 312] IconDisplay "Port number" } Block { BlockType Inport Name "I" SID "15934" Position [230, 348, 260, 362] Port "2" IconDisplay "Port number" } Block { BlockType Scope Name "Auto Corr Calc" SID "15935" Ports [9] Position [760, 500, 805, 650] Floating off Location [1, 45, 1836, 1199] Open off NumInputPorts "9" ZoomMode "yonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" axes9 "%" } List { ListType ScopeGraphics FigureColor "[0.5 0.5 0.5]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "17540 " YMin "-0.04~-0.05~0.002~0~-1~-1~-1~-1~-1" YMax "0.05~0.05~0.01~0.007~1~1~1~1~1" SaveName "ScopeData56" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType Reference Name "Register" SID "15936" Ports [2, 1] Position [470, 338, 495, 362] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,24,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 24 24 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 24 24 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[15.33 " "15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[12.33 12.33 15.33" " 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 1 " "1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\nco" "lor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Running Sum" SID "15937" Ports [2, 2] Position [365, 338, 430, 362] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Running Sum" Location [202, 70, 1833, 1180] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "En" SID "15938" Position [195, 183, 225, 197] IconDisplay "Port number" } Block { BlockType Inport Name "D" SID "15939" Position [195, 123, 225, 137] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Accum1" SID "15940" Ports [2, 1] Position [485, 131, 535, 184] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Accumulator" SourceType "Xilinx Accumulator Block" infoedit "Adder or subtracter-based accumulator. Output type and binary point position match the input.
Hardware notes: When \"Reinitialize with input 'b' on reset\" is selected, the accumulator is forced to ru" "n at the system rate even if the input 'b' is running at a slower rate." operation "Add" n_bits "27" overflow "Flag as error" scale "1" rst off infoeditControl "reset for floating point data type must be asserted for a minimum of 2 cycles" hasbypass off en on latency "0" dbl_ovrd off msb_inp "100" msb "100" lsb "-100" use_behavioral_HDL on implementation "Fabric" xl_use_area off xl_area "[12 23 0 22 0 0 0]" has_advanced_control "0" sggui_pos "20,20,367,457" block_type "accum" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,53,2,1,white,blue,0,debef366,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 53 53 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 53 53 0 ]);\npatch([9.425 19.54 26.54 33.54 40.54 26.54 16.425 9.425 ],[33.7" "7 33.77 40.77 33.77 40.77 40.77 40.77 33.77 ],[1 1 1 ]);\npatch([16.425 26.54 19.54 9.425 16.425 ],[26.77 26.77 " "33.77 33.77 26.77 ],[0.931 0.946 0.973 ]);\npatch([9.425 19.54 26.54 16.425 9.425 ],[19.77 19.77 26.77 26.77 19." "77 ],[1 1 1 ]);\npatch([16.425 40.54 33.54 26.54 19.54 9.425 16.425 ],[12.77 12.77 19.77 12.77 19.77 19.77 12.77" " ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nc" "olor('black');port_label('input',1,'b');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label(" "'output',1,'\\bf+=b','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "AddSub1" SID "15941" Ports [2, 1] Position [360, 117, 410, 168] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Subtraction" use_carryin off use_carryout off en off latency "1" precision "Full" arith_type "Signed (2's comp)" n_bits "36" bin_pt "28" quantization "Truncate" overflow "Saturate" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[9 18 0 17 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,344" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,51,2,1,white,blue,0,8a00a986,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 51 51 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 51 51 0 ]);\npatch([9.425 19.54 26.54 33.54 40.54 26.54 16.425 9.425 ],[32.7" "7 32.77 39.77 32.77 39.77 39.77 39.77 32.77 ],[1 1 1 ]);\npatch([16.425 26.54 19.54 9.425 16.425 ],[25.77 25.77 " "32.77 32.77 25.77 ],[0.931 0.946 0.973 ]);\npatch([9.425 19.54 26.54 16.425 9.425 ],[18.77 18.77 25.77 25.77 18." "77 ],[1 1 1 ]);\npatch([16.425 40.54 33.54 26.54 19.54 9.425 16.425 ],[11.77 11.77 18.77 11.77 18.77 18.77 11.77" " ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nc" "olor('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('" "output',1,'\\bf{a - b}','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black'" ");disp(' \\newline\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay" SID "15942" Ports [1, 1] Position [375, 178, 400, 202] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[7 14 0 14 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 24 24 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 24 24 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[15.33 " "15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[12.33 12.33 15.33" " 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 1 " "1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');di" "sp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay1" SID "15943" Ports [1, 1] Position [495, 198, 520, 222] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[7 14 0 14 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 24 24 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 24 24 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[15.33 " "15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[12.33 12.33 15.33" " 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 1 " "1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');di" "sp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay2" SID "15944" Ports [1, 1] Position [605, 198, 630, 222] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[7 14 0 14 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 24 24 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 24 24 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[15.33 " "15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[12.33 12.33 15.33" " 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 1 " "1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');di" "sp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay6" SID "15945" Ports [2, 1] Position [265, 143, 300, 167] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en on latency "20" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[9 17 0 17 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,24,2,1,white,blue,0,bbd9dacd,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[15" ".33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.33 12." "33 15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 12.33 " "9.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncol" "or('black');port_label('input',2,'en');\n\ncolor('black');disp('z^{-20}','texmode','on');\nfprintf('','COMMENT: " "end icon text');" } Block { BlockType Reference Name "Register" SID "15946" Ports [1, 1] Position [600, 142, 635, 178] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,36,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 36 36 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 36 36 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[23.55 23." "55 28.55 23.55 28.55 28.55 28.55 23.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[18.55 18.55 23.55 2" "3.55 18.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[13.55 13.55 18.55 18.55 13.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[8.55 8.55 13.55 8.55 13.55 13.55 8.55 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');por" "t_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Sum" SID "15947" Position [710, 153, 740, 167] IconDisplay "Port number" } Block { BlockType Outport Name "Valid" SID "15948" Position [710, 203, 740, 217] Port "2" IconDisplay "Port number" } Line { SrcBlock "Delay2" SrcPort 1 DstBlock "Valid" DstPort 1 } Line { SrcBlock "Delay1" SrcPort 1 DstBlock "Delay2" DstPort 1 } Line { SrcBlock "Delay" SrcPort 1 Points [50, 0] Branch { Points [0, 20] DstBlock "Delay1" DstPort 1 } Branch { Points [0, -20] DstBlock "Accum1" DstPort 2 } } Line { SrcBlock "En" SrcPort 1 Points [10, 0] Branch { DstBlock "Delay" DstPort 1 } Branch { Points [0, -30] DstBlock "Delay6" DstPort 2 } } Line { SrcBlock "Register" SrcPort 1 DstBlock "Sum" DstPort 1 } Line { SrcBlock "Accum1" SrcPort 1 DstBlock "Register" DstPort 1 } Line { SrcBlock "D" SrcPort 1 Points [0, 0; 15, 0] Branch { Points [0, 20] DstBlock "Delay6" DstPort 1 } Branch { DstBlock "AddSub1" DstPort 1 } } Line { SrcBlock "AddSub1" SrcPort 1 DstBlock "Accum1" DstPort 1 } Line { SrcBlock "Delay6" SrcPort 1 DstBlock "AddSub1" DstPort 2 } } } Block { BlockType Reference Name "done1" SID "15949" Ports [1, 1] Position [550, 540, 585, 550] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Running Sum I" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "done4" SID "15950" Ports [1, 1] Position [550, 510, 585, 520] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Conj Mult I" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Outport Name "M" SID "15951" Position [565, 343, 595, 357] IconDisplay "Port number" } Line { SrcBlock "Register" SrcPort 1 DstBlock "M" DstPort 1 } Line { SrcBlock "Running Sum" SrcPort 2 DstBlock "Register" DstPort 2 } Line { Name "Running Sum I" Labels [0, 0] SrcBlock "done1" SrcPort 1 DstBlock "Auto Corr Calc" DstPort 3 } Line { Name "Conj Mult I" Labels [0, 0] SrcBlock "done4" SrcPort 1 DstBlock "Auto Corr Calc" DstPort 1 } Line { SrcBlock "Valid" SrcPort 1 Points [90, 0] DstBlock "Running Sum" DstPort 1 } Line { SrcBlock "I" SrcPort 1 Points [50, 0] Branch { Points [0, 160] DstBlock "done4" DstPort 1 } Branch { DstBlock "Running Sum" DstPort 2 } } Line { SrcBlock "Running Sum" SrcPort 1 Points [10, 0] Branch { Points [0, 200] DstBlock "done1" DstPort 1 } Branch { DstBlock "Register" DstPort 1 } } } } Block { BlockType SubSystem Name "Conj Mult" SID "7809" Ports [5, 2] Position [540, 303, 605, 387] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Conj Mult" Location [227, 108, 1983, 1242] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Valid" SID "7810" Position [180, 293, 210, 307] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "A I" SID "7811" Position [180, 343, 210, 357] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "A Q" SID "7812" Position [180, 428, 210, 442] NamePlacement "alternate" Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "B I" SID "7813" Position [180, 373, 210, 387] NamePlacement "alternate" Port "4" IconDisplay "Port number" } Block { BlockType Inport Name "B Q" SID "7814" Position [180, 458, 210, 472] NamePlacement "alternate" Port "5" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub" SID "7815" Ports [2, 1] Position [490, 351, 520, 409] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "1" precision "User Defined" arith_type "Signed (2's comp)" n_bits "23" bin_pt "20" quantization "Truncate" overflow "Flag as error" dbl_ovrd off use_behavioral_HDL off hw_selection "Fabric" pipelined off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" sg_icon_stat "30,58,2,1,white,blue,0,e85d8a90,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 58 58 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 58 58 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[33.44 33.4" "4 37.44 33.44 37.44 37.44 37.44 33.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[29.44 29.44 33.44 33.44 " "29.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[25.44 25.44 29.44 29.44 25.44 ],[1 1 1 ]);\np" "atch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[21.44 21.44 25.44 21.44 25.44 25.44 21.44 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label" "('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bf{a + b}'," "'texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\newline\\bf{}" "','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay" SID "7817" Ports [1, 1] Position [430, 286, 465, 314] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "4" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,28,1,1,white,blue,0,d390c2d8,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 28 28 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[18.44 18.4" "4 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[14.44 14.44 18.44 18.44 " "14.44 ],[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\np" "atch([12.1 25.88 21.88 17.88 13.88 8.1 12.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-" "4}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mult" SID "7818" Ports [2, 1] Position [360, 334, 395, 396] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mult" SourceType "Xilinx Multiplier Block" infoedit "Hardware notes: To check for the optimum internal pipeline stages of the dedicated multiplier you" " must select 'Test for optimum pipelining'.

Optimization Goal: For implementation into device fabric (LUT" "s), the Speed or Area optimization will take effect only if it's supported by IP for the particular device famil" "y. Otherwise, the results will be identical regardless of the selection." precision "User Defined" arith_type "Signed (2's comp)" n_bits "22" bin_pt "20" quantization "Truncate" overflow "Flag as error" en off latency "3" dbl_ovrd off use_behavioral_HDL off opt "Speed" use_embedded on optimum_pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" pipeline "on" use_rpm "on" placement_style "Triangular" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mult" sg_icon_stat "35,62,2,1,white,blue,0,7028354c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 62 62 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 62 62 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[36.55 36." "55 41.55 36.55 41.55 41.55 41.55 36.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[31.55 31.55 36.55 3" "6.55 31.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[26.55 26.55 31.55 31.55 26.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[21.55 21.55 26.55 21.55 26.55 26.55 21.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bfa \\times b','texmode','on');\ncolor('black');disp('z^{-3}\\newline ','texmode','on');\ncolor('black');disp(' " "\\n ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mult1" SID "15918" Ports [2, 1] Position [360, 419, 395, 481] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mult" SourceType "Xilinx Multiplier Block" infoedit "Hardware notes: To check for the optimum internal pipeline stages of the dedicated multiplier you" " must select 'Test for optimum pipelining'.

Optimization Goal: For implementation into device fabric (LUT" "s), the Speed or Area optimization will take effect only if it's supported by IP for the particular device famil" "y. Otherwise, the results will be identical regardless of the selection." precision "User Defined" arith_type "Signed (2's comp)" n_bits "22" bin_pt "20" quantization "Truncate" overflow "Flag as error" en off latency "3" dbl_ovrd off use_behavioral_HDL off opt "Speed" use_embedded on optimum_pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" pipeline "on" use_rpm "on" placement_style "Triangular" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mult" sg_icon_stat "35,62,2,1,white,blue,0,7028354c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 62 62 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 62 62 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[36.55 36." "55 41.55 36.55 41.55 41.55 41.55 36.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[31.55 31.55 36.55 3" "6.55 31.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[26.55 26.55 31.55 31.55 26.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[21.55 21.55 26.55 21.55 26.55 26.55 21.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bfa \\times b','texmode','on');\ncolor('black');disp('z^{-3}\\newline ','texmode','on');\ncolor('black');disp(' " "\\n ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name " Valid" SID "7822" Position [815, 293, 845, 307] IconDisplay "Port number" } Block { BlockType Outport Name " I" SID "7823" Position [630, 373, 660, 387] Port "2" IconDisplay "Port number" } Line { SrcBlock "B Q" SrcPort 1 DstBlock "Mult1" DstPort 2 } Line { SrcBlock "Valid" SrcPort 1 DstBlock "Delay" DstPort 1 } Line { SrcBlock "A I" SrcPort 1 DstBlock "Mult" DstPort 1 } Line { SrcBlock "B I" SrcPort 1 DstBlock "Mult" DstPort 2 } Line { SrcBlock "A Q" SrcPort 1 DstBlock "Mult1" DstPort 1 } Line { SrcBlock "Mult" SrcPort 1 DstBlock "AddSub" DstPort 1 } Line { SrcBlock "Mult1" SrcPort 1 Points [15, 0; 0, -55] DstBlock "AddSub" DstPort 2 } Line { SrcBlock "AddSub" SrcPort 1 DstBlock " I" DstPort 1 } Line { SrcBlock "Delay" SrcPort 1 DstBlock " Valid" DstPort 1 } } } Block { BlockType SubSystem Name "Conj Mult1" SID "15920" Ports [5, 2] Position [540, 488, 605, 572] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Conj Mult1" Location [202, 70, 1833, 1180] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Valid" SID "15921" Position [180, 293, 210, 307] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "A I" SID "15922" Position [180, 343, 210, 357] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "A Q" SID "15923" Position [180, 428, 210, 442] NamePlacement "alternate" Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "B I" SID "15924" Position [180, 373, 210, 387] NamePlacement "alternate" Port "4" IconDisplay "Port number" } Block { BlockType Inport Name "B Q" SID "15925" Position [180, 458, 210, 472] NamePlacement "alternate" Port "5" IconDisplay "Port number" } Block { BlockType Reference Name "Absolute" SID "15953" Ports [1, 1] Position [595, 363, 625, 397] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Absolute" SourceType "Xilinx Absolute Block Block" precision "User Defined" arith_type "Unsigned" n_bits "23" bin_pt "20" quantization "Truncate" overflow "Flag as error" en off latency "1" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "abs" sg_icon_stat "30,34,1,1,white,blue,0,6c6606ff,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 34 34 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 34 34 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[21.44 21.4" "4 25.44 21.44 25.44 25.44 25.44 21.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[17.44 17.44 21.44 21.44 " "17.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[13.44 13.44 17.44 17.44 13.44 ],[1 1 1 ]);\np" "atch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[9.44 9.44 13.44 9.44 13.44 13.44 9.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('in" "put',1,'a');\ncolor('black');port_label('output',1,'|a|');\ncolor('black');disp('z^{-1}\\newline ','texmode','on" "');\ncolor('black');disp(' \\newline\\bf{|x|}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub" SID "15926" Ports [2, 1] Position [490, 351, 520, 409] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "1" precision "User Defined" arith_type "Signed (2's comp)" n_bits "23" bin_pt "20" quantization "Truncate" overflow "Flag as error" dbl_ovrd off use_behavioral_HDL off hw_selection "Fabric" pipelined off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" sg_icon_stat "30,58,2,1,white,blue,0,e85d8a90,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 58 58 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 58 58 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[33.44 33.4" "4 37.44 33.44 37.44 37.44 37.44 33.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[29.44 29.44 33.44 33.44 " "29.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[25.44 25.44 29.44 29.44 25.44 ],[1 1 1 ]);\np" "atch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[21.44 21.44 25.44 21.44 25.44 25.44 21.44 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label" "('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bf{a + b}'," "'texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\newline\\bf{}" "','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay" SID "15927" Ports [1, 1] Position [430, 286, 465, 314] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "5" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,28,1,1,white,blue,0,ec356abf,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 28 28 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[18.44 18.4" "4 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[14.44 14.44 18.44 18.44 " "14.44 ],[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\np" "atch([12.1 25.88 21.88 17.88 13.88 8.1 12.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-" "5}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mult" SID "15928" Ports [2, 1] Position [360, 334, 395, 396] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mult" SourceType "Xilinx Multiplier Block" infoedit "Hardware notes: To check for the optimum internal pipeline stages of the dedicated multiplier you" " must select 'Test for optimum pipelining'.

Optimization Goal: For implementation into device fabric (LUT" "s), the Speed or Area optimization will take effect only if it's supported by IP for the particular device famil" "y. Otherwise, the results will be identical regardless of the selection." precision "User Defined" arith_type "Signed (2's comp)" n_bits "22" bin_pt "20" quantization "Truncate" overflow "Flag as error" en off latency "3" dbl_ovrd off use_behavioral_HDL off opt "Speed" use_embedded on optimum_pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" pipeline "on" use_rpm "on" placement_style "Triangular" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mult" sg_icon_stat "35,62,2,1,white,blue,0,7028354c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 62 62 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 62 62 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[36.55 36." "55 41.55 36.55 41.55 41.55 41.55 36.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[31.55 31.55 36.55 3" "6.55 31.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[26.55 26.55 31.55 31.55 26.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[21.55 21.55 26.55 21.55 26.55 26.55 21.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bfa \\times b','texmode','on');\ncolor('black');disp('z^{-3}\\newline ','texmode','on');\ncolor('black');disp(' " "\\n ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mult1" SID "15929" Ports [2, 1] Position [360, 419, 395, 481] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mult" SourceType "Xilinx Multiplier Block" infoedit "Hardware notes: To check for the optimum internal pipeline stages of the dedicated multiplier you" " must select 'Test for optimum pipelining'.

Optimization Goal: For implementation into device fabric (LUT" "s), the Speed or Area optimization will take effect only if it's supported by IP for the particular device famil" "y. Otherwise, the results will be identical regardless of the selection." precision "User Defined" arith_type "Signed (2's comp)" n_bits "22" bin_pt "20" quantization "Truncate" overflow "Flag as error" en off latency "3" dbl_ovrd off use_behavioral_HDL off opt "Speed" use_embedded on optimum_pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" pipeline "on" use_rpm "on" placement_style "Triangular" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mult" sg_icon_stat "35,62,2,1,white,blue,0,7028354c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 62 62 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 62 62 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[36.55 36." "55 41.55 36.55 41.55 41.55 41.55 36.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[31.55 31.55 36.55 3" "6.55 31.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[26.55 26.55 31.55 31.55 26.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[21.55 21.55 26.55 21.55 26.55 26.55 21.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bfa \\times b','texmode','on');\ncolor('black');disp('z^{-3}\\newline ','texmode','on');\ncolor('black');disp(' " "\\n ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name " Valid" SID "15930" Position [815, 293, 845, 307] IconDisplay "Port number" } Block { BlockType Outport Name " I" SID "15931" Position [700, 373, 730, 387] Port "2" IconDisplay "Port number" } Line { SrcBlock "Delay" SrcPort 1 DstBlock " Valid" DstPort 1 } Line { SrcBlock "AddSub" SrcPort 1 DstBlock "Absolute" DstPort 1 } Line { SrcBlock "Mult1" SrcPort 1 Points [15, 0; 0, -55] DstBlock "AddSub" DstPort 2 } Line { SrcBlock "Mult" SrcPort 1 DstBlock "AddSub" DstPort 1 } Line { SrcBlock "A Q" SrcPort 1 DstBlock "Mult1" DstPort 1 } Line { SrcBlock "B I" SrcPort 1 DstBlock "Mult" DstPort 2 } Line { SrcBlock "A I" SrcPort 1 DstBlock "Mult" DstPort 1 } Line { SrcBlock "Valid" SrcPort 1 DstBlock "Delay" DstPort 1 } Line { SrcBlock "B Q" SrcPort 1 DstBlock "Mult1" DstPort 2 } Line { SrcBlock "Absolute" SrcPort 1 DstBlock " I" DstPort 1 } } } Block { BlockType Reference Name "Delay" SID "7841" Ports [2, 1] Position [310, 350, 345, 370] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en on latency "16" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[7 14 0 14 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,20,2,1,white,blue,0,68dbc054,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 20 20 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 20 20 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[12.22" " 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[10.22 10.22 12." "22 12.22 10.22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1" " 1 1 ]);\npatch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');" "port_label('input',2,'en');\n\ncolor('black');disp('z^{-16}','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" } Block { BlockType Reference Name "Delay1" SID "7842" Ports [2, 1] Position [310, 365, 345, 385] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en on latency "16" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[7 14 0 14 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,20,2,1,white,blue,0,68dbc054,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 20 20 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 20 20 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[12.22" " 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[10.22 10.22 12." "22 12.22 10.22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1" " 1 1 ]);\npatch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');" "port_label('input',2,'en');\n\ncolor('black');disp('z^{-16}','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" } Block { BlockType Reference Name "Delay2" SID "7843" Ports [2, 1] Position [390, 535, 425, 555] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en on latency "4" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[7 14 0 14 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,20,2,1,white,blue,0,bb519d05,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 20 20 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 20 20 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[12.22" " 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[10.22 10.22 12." "22 12.22 10.22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1" " 1 1 ]);\npatch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');" "port_label('input',2,'en');\n\ncolor('black');disp('z^{-4}','texmode','on');\nfprintf('','COMMENT: end icon text" "');" } Block { BlockType Reference Name "Delay3" SID "7844" Ports [2, 1] Position [390, 550, 425, 570] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en on latency "4" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[7 14 0 14 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,20,2,1,white,blue,0,bb519d05,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 20 20 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 20 20 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[12.22" " 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[10.22 10.22 12." "22 12.22 10.22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1" " 1 1 ]);\npatch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');" "port_label('input',2,'en');\n\ncolor('black');disp('z^{-4}','texmode','on');\nfprintf('','COMMENT: end icon text" "');" } Block { BlockType Reference Name "Register" SID "7845" Ports [1, 1] Position [455, 301, 485, 329] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,28,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 18.4" "4 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 18.44 " "14.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\np" "atch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('in" "put',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf" "('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "7846" Ports [1, 1] Position [455, 316, 485, 344] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,28,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 18.4" "4 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 18.44 " "14.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\np" "atch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('in" "put',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf" "('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "7847" Ports [1, 1] Position [455, 331, 485, 359] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,28,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 18.4" "4 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 18.44 " "14.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\np" "atch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('in" "put',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf" "('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register3" SID "7848" Ports [1, 1] Position [455, 346, 485, 374] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,28,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 18.4" "4 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 18.44 " "14.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\np" "atch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('in" "put',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf" "('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register4" SID "7849" Ports [1, 1] Position [455, 361, 485, 389] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,28,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 18.4" "4 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 18.44 " "14.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\np" "atch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('in" "put',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf" "('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register5" SID "7850" Ports [1, 1] Position [455, 486, 485, 514] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,28,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 18.4" "4 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 18.44 " "14.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\np" "atch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('in" "put',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf" "('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register6" SID "7851" Ports [1, 1] Position [455, 501, 485, 529] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,28,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 18.4" "4 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 18.44 " "14.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\np" "atch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('in" "put',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf" "('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register7" SID "7852" Ports [1, 1] Position [455, 516, 485, 544] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,28,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 18.4" "4 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 18.44 " "14.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\np" "atch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('in" "put',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf" "('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register8" SID "7853" Ports [1, 1] Position [455, 531, 485, 559] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,28,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 18.4" "4 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 18.44 " "14.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\np" "atch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('in" "put',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf" "('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register9" SID "7854" Ports [1, 1] Position [455, 546, 485, 574] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,28,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 18.4" "4 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 18.44 " "14.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\np" "atch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('in" "put',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf" "('','COMMENT: end icon text');" } Block { BlockType Outport Name "Corr_16" SID "7855" Position [780, 338, 810, 352] IconDisplay "Port number" } Block { BlockType Outport Name "Corr_20" SID "7856" Position [780, 523, 810, 537] Port "2" IconDisplay "Port number" } Line { SrcBlock "I" SrcPort 1 Points [35, 0] Branch { DstBlock "Delay" DstPort 1 } Branch { Points [115, 0] Branch { DstBlock "Register1" DstPort 1 } Branch { Points [0, 185] DstBlock "Register6" DstPort 1 } } } Line { SrcBlock "Q" SrcPort 1 Points [15, 0] Branch { Points [0, 5] DstBlock "Delay1" DstPort 1 } Branch { Points [0, -20; 130, 0] Branch { DstBlock "Register2" DstPort 1 } Branch { Points [0, 185] DstBlock "Register7" DstPort 1 } } } Line { SrcBlock "Delay" SrcPort 1 Points [15, 0] Branch { DstBlock "Register3" DstPort 1 } Branch { Points [0, 180] DstBlock "Delay2" DstPort 1 } } Line { SrcBlock "Delay1" SrcPort 1 Points [10, 0] Branch { DstBlock "Register4" DstPort 1 } Branch { Points [0, 180] DstBlock "Delay3" DstPort 1 } } Line { SrcBlock "Valid" SrcPort 1 Points [25, 0] Branch { Points [0, 100] Branch { DstBlock "Delay" DstPort 2 } Branch { Points [0, 15] Branch { DstBlock "Delay1" DstPort 2 } Branch { Points [0, 170] Branch { DstBlock "Delay2" DstPort 2 } Branch { Points [0, 15] DstBlock "Delay3" DstPort 2 } } } } Branch { Points [130, 0; 0, 50] Branch { DstBlock "Register" DstPort 1 } Branch { Points [0, 185] DstBlock "Register5" DstPort 1 } } } Line { SrcBlock "Conj Mult" SrcPort 2 DstBlock "Avg Mag" DstPort 2 } Line { Labels [0, 0] SrcBlock "Conj Mult" SrcPort 1 DstBlock "Avg Mag" DstPort 1 } Line { SrcBlock "Avg Mag" SrcPort 1 DstBlock "Corr_16" DstPort 1 } Line { SrcBlock "Register" SrcPort 1 DstBlock "Conj Mult" DstPort 1 } Line { SrcBlock "Register1" SrcPort 1 DstBlock "Conj Mult" DstPort 2 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Conj Mult" DstPort 3 } Line { SrcBlock "Register3" SrcPort 1 DstBlock "Conj Mult" DstPort 4 } Line { SrcBlock "Register4" SrcPort 1 DstBlock "Conj Mult" DstPort 5 } Line { SrcBlock "Avg Mag1" SrcPort 1 DstBlock "Corr_20" DstPort 1 } Line { SrcBlock "Register5" SrcPort 1 DstBlock "Conj Mult1" DstPort 1 } Line { SrcBlock "Register6" SrcPort 1 DstBlock "Conj Mult1" DstPort 2 } Line { SrcBlock "Register7" SrcPort 1 DstBlock "Conj Mult1" DstPort 3 } Line { SrcBlock "Delay2" SrcPort 1 DstBlock "Register8" DstPort 1 } Line { SrcBlock "Register8" SrcPort 1 DstBlock "Conj Mult1" DstPort 4 } Line { SrcBlock "Register9" SrcPort 1 DstBlock "Conj Mult1" DstPort 5 } Line { SrcBlock "Delay3" SrcPort 1 DstBlock "Register9" DstPort 1 } Line { SrcBlock "Conj Mult1" SrcPort 1 DstBlock "Avg Mag1" DstPort 1 } Line { SrcBlock "Conj Mult1" SrcPort 2 DstBlock "Avg Mag1" DstPort 2 } } } Block { BlockType Scope Name "Auto Corr Pkt Det" SID "7857" Ports [9] Position [1270, 415, 1315, 565] Floating off Location [6, 40, 1848, 1194] Open off NumInputPorts "9" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" axes9 "%" } List { ListType ScopeGraphics FigureColor "[0.5 0.5 0.5]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "17540" YMin "-0.5~-0.5~0~-0.3~0~-1~-1~-1~0" YMax "0.5~0.5~2~0.7~0.7~1~1~1~1" SaveName "ScopeData28" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType SubSystem Name "Decision" SID "7858" Ports [7, 2] Position [810, 80, 935, 360] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Decision" Location [202, 70, 1833, 1180] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Reset OFDM" SID "7859" Position [810, 403, 840, 417] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "Reset DSSS" SID "7860" Position [835, 613, 865, 627] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "iq_vld" SID "14949" Position [25, 768, 55, 782] NamePlacement "alternate" Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "Corr_16" SID "7861" Position [25, 333, 55, 347] NamePlacement "alternate" Port "4" IconDisplay "Port number" } Block { BlockType Inport Name "Corr_20" SID "7862" Position [25, 593, 55, 607] NamePlacement "alternate" Port "5" IconDisplay "Port number" } Block { BlockType Inport Name "Mag 16" SID "7863" Position [25, 403, 55, 417] Port "6" IconDisplay "Port number" } Block { BlockType Inport Name "Mag 20" SID "17485" Position [25, 533, 55, 547] Port "7" IconDisplay "Port number" } Block { BlockType Scope Name "Auto Corr Decision" SID "7864" Ports [10] Position [1520, 48, 1565, 197] Floating off Location [1921, 45, 3841, 1199] Open off NumInputPorts "10" ZoomMode "yonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" axes9 "%" axes10 "%" } List { ListType ScopeGraphics FigureColor "[0.501960784313725 0.501960784313725 0.501960784313725]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[1 1 1 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "17540" YMin "-0.5~1.025~1.275~1.125~-1~0.95~-1~-1~1.09~-0.4" YMax "0.4~1.25~1.5~1.3~1~1.05~1~1~1.17~0.4" SaveName "ScopeData43" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType Reference Name "Delay" SID "17489" Ports [1, 1] Position [465, 338, 495, 362] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "30,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 24 24 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 24 24 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[15.3" "3 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[12.33 12.33 " "15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[9.33 9.33 12.33 12.33 9.33 " "],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('" "black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay1" SID "17490" Ports [1, 1] Position [465, 598, 495, 622] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "30,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 24 24 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 24 24 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[15.3" "3 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[12.33 12.33 " "15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[9.33 9.33 12.33 12.33 9.33 " "],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('" "black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay2" SID "17493" Ports [1, 1] Position [465, 538, 495, 562] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "30,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 24 24 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 24 24 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[15.3" "3 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[12.33 12.33 " "15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[9.33 9.33 12.33 12.33 9.33 " "],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('" "black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay3" SID "17494" Ports [1, 1] Position [465, 478, 495, 502] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "30,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 24 24 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 24 24 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[15.3" "3 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[12.33 12.33 " "15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[9.33 9.33 12.33 12.33 9.33 " "],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('" "black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Display Name "Display" SID "7865" Ports [1] Position [540, 1091, 625, 1119] ShowName off Decimation "1" Lockdown off } Block { BlockType Display Name "Display1" SID "7866" Ports [1] Position [540, 1156, 625, 1184] ShowName off Decimation "1" Lockdown off } Block { BlockType Display Name "Display2" SID "7867" Ports [1] Position [540, 1116, 625, 1144] ShowName off Decimation "1" Lockdown off } Block { BlockType Display Name "Display3" SID "7868" Ports [1] Position [540, 1181, 625, 1209] ShowName off Decimation "1" Lockdown off } Block { BlockType Display Name "Display4" SID "7869" Ports [1] Position [1115, 1091, 1200, 1119] ShowName off Decimation "1" Lockdown off } Block { BlockType Display Name "Display5" SID "7870" Ports [1] Position [1115, 1116, 1200, 1144] ShowName off Decimation "1" Lockdown off } Block { BlockType Display Name "Display6" SID "7871" Ports [1] Position [1095, 1156, 1180, 1184] ShowName off Decimation "1" Lockdown off } Block { BlockType Display Name "Display7" SID "7872" Ports [1] Position [1095, 1181, 1180, 1209] ShowName off Decimation "1" Lockdown off } Block { BlockType Product Name "Divide" SID "17432" Ports [2, 1] Position [1275, 157, 1305, 188] ZOrder -8 Inputs "*/" InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" RndMeth "Floor" SaturateOnIntegerOverflow off Port { PortNumber 1 Name "DSSS Ratio" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Product Name "Divide1" SID "17433" Ports [2, 1] Position [1275, 222, 1305, 253] ZOrder -8 Inputs "*/" InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" RndMeth "Floor" SaturateOnIntegerOverflow off Port { PortNumber 1 Name "OFDM Ratio" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType From Name "From1" SID "7873" Position [195, 379, 365, 401] ShowName off CloseFcn "tagdialog Close" GotoTag "regRx_PktDet_CorrThresh_A" TagVisibility "global" } Block { BlockType From Name "From2" SID "7874" Position [165, 1159, 335, 1181] ShowName off CloseFcn "tagdialog Close" GotoTag "regRx_PktDet_EnergyThresh_A" TagVisibility "global" } Block { BlockType From Name "From3" SID "7875" Position [175, 1094, 345, 1116] ShowName off CloseFcn "tagdialog Close" GotoTag "regRx_PktDet_CorrThresh_A" TagVisibility "global" } Block { BlockType From Name "From4" SID "7876" Position [195, 499, 365, 521] ShowName off CloseFcn "tagdialog Close" GotoTag "regRx_PktDet_EnergyThresh_A" TagVisibility "global" } Block { BlockType From Name "From5" SID "7877" Position [160, 664, 375, 686] ShowName off CloseFcn "tagdialog Close" GotoTag "regRx_PktDet_CorrThresh_DSSS_A" TagVisibility "global" } Block { BlockType From Name "From6" SID "7878" Position [705, 1094, 920, 1116] ShowName off CloseFcn "tagdialog Close" GotoTag "regRx_PktDet_CorrThresh_DSSS_A" TagVisibility "global" } Block { BlockType From Name "From7" SID "7879" Position [150, 561, 365, 579] ShowName off CloseFcn "tagdialog Close" GotoTag "regRx_PktDet_EnergyThresh_DSSS_A" TagVisibility "global" } Block { BlockType From Name "From8" SID "7880" Position [685, 1161, 890, 1179] ShowName off CloseFcn "tagdialog Close" GotoTag "regRx_PktDet_EnergyThresh_DSSS_A" TagVisibility "global" } Block { BlockType From Name "From9" SID "10932" Position [700, 719, 915, 741] ShowName off CloseFcn "tagdialog Close" GotoTag "MAC_PHY_BLOCK_PKT_DET" TagVisibility "global" } Block { BlockType Reference Name "Inverter" SID "10937" Ports [1, 1] Position [960, 721, 985, 739] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical" SID "7881" Ports [2, 1] Position [710, 408, 755, 452] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('" "black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "7882" Ports [2, 1] Position [710, 618, 755, 662] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('" "black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "10931" Ports [2, 1] Position [1100, 418, 1145, 462] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('" "black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical3" SID "10938" Ports [2, 1] Position [1100, 628, 1145, 672] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('" "black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Min Dur" SID "7883" Ports [3, 1] Position [905, 400, 995, 460] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Min Dur" Location [227, 108, 1983, 1242] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Reset " SID "7884" Position [355, 143, 385, 157] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "Det " SID "7885" Position [355, 233, 385, 247] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "iq_vld" SID "14947" Position [330, 298, 360, 312] Port "3" IconDisplay "Port number" } Block { BlockType Reference Name "Counter1" SID "7886" Ports [2, 1] Position [695, 189, 725, 271] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited count" "er is implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "Inf" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "5" bin_pt "0" load_pin off rst on en on explicit_period "off" period "4" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,619" block_type "counter" block_version "10.1.3" sg_icon_stat "30,82,2,1,white,blue,0,ae3608d6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 82 82 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 82 82 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[45.44 45.4" "4 49.44 45.44 49.44 49.44 49.44 45.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[41.44 41.44 45.44 45.44 " "41.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[37.44 37.44 41.44 41.44 37.44 ],[1 1 1 ]);\np" "atch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[33.44 33.44 37.44 33.44 37.44 37.44 33.44 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label" "('input',1,'rst');\ncolor('black');port_label('input',2,'en');\n\ncolor('black');disp('{\\fontsize{14}\\bf++}','" "texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Display Name "Display" SID "7887" Ports [1] Position [675, 561, 760, 589] ShowName off Decimation "1" Lockdown off } Block { BlockType From Name "From1" SID "7888" Position [295, 566, 535, 584] ShowName off CloseFcn "tagdialog Close" GotoTag "regPktDet_pktDetMinDuration_autoCorr_A" TagVisibility "global" } Block { BlockType From Name "From4" SID "7889" Position [485, 271, 725, 289] ShowName off CloseFcn "tagdialog Close" GotoTag "regPktDet_pktDetMinDuration_autoCorr_A" TagVisibility "global" } Block { BlockType Reference Name "Inverter1" SID "7890" Ports [1, 1] Position [530, 208, 555, 222] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "8.2" sg_icon_stat "25,14,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfprintf" "('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter2" SID "7891" Ports [1, 1] Position [635, 328, 660, 342] BlockMirror on ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "8.2" sg_icon_stat "25,14,1,1,white,blue,0,267846e5,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfprintf" "('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "7892" Ports [2, 1] Position [615, 194, 645, 221] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,261" block_type "logical" block_version "10.1.3" sg_icon_stat "30,27,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 27 27 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 27 27 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[16.3" "3 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 13.33 " "16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13.33 10." "33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n" "color('black');disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "7893" Ports [3, 1] Position [590, 231, 620, 269] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,261" block_type "logical" block_version "10.1.3" sg_icon_stat "30,38,3,1,white,blue,0,98d76266,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 38 38 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 38 38 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[23.44 23.4" "4 27.44 23.44 27.44 27.44 27.44 23.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[19.44 19.44 23.44 23.44 " "19.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[15.44 15.44 19.44 19.44 15.44 ],[1 1 1 ]);\np" "atch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[11.44 11.44 15.44 11.44 15.44 15.44 11.44 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\ncolor('black');di" "sp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Scope Name "Pkt Det Ctrl Min Dur" SID "7894" Ports [7] Position [1270, 360, 1315, 470] Floating off Location [1, 45, 1833, 1199] Open off NumInputPorts "7" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" } List { ListType ScopeGraphics FigureColor "[0.5 0.5 0.5]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "10000" YMin "0~0~0~0~-1~-1~-1" YMax "1~1~1~1~1~1~1" SaveName "ScopeData6" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType SubSystem Name "Posedge1" SID "7895" Ports [1, 1] Position [870, 231, 915, 249] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Posedge1" Location [88, 301, 2330, 1301] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "7896" Position [200, 253, 230, 267] IconDisplay "Port number" } Block { BlockType Reference Name "Delay" SID "7897" Ports [1, 1] Position [425, 153, 460, 177] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. " "If register retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[15" ".33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.33 12." "33 15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 12.33 " "9.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\nc" "olor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "7898" Ports [1, 1] Position [490, 156, 515, 174] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "7899" Ports [2, 1] Position [540, 151, 585, 204] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,53,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 53 53 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 53 53 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[32.66 3" "2.66 38.66 32.66 38.66 38.66 38.66 32.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[26.66 26.66 32.66 " "32.66 26.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[20.66 20.66 26.66 26.66 20.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[14.66 14.66 20.66 14.66 20.66 20.66 14.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('" "black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "7900" Position [610, 173, 640, 187] IconDisplay "Port number" } Line { SrcBlock "Delay" SrcPort 1 DstBlock "Inverter" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "D" SrcPort 1 Points [150, 0; 0, -70] Branch { Points [0, -25] DstBlock "Delay" DstPort 1 } Branch { DstBlock "Logical1" DstPort 2 } } Annotation { Name "Rising Edge Detection" Position [500, 112] } } } Block { BlockType Reference Name "Relational3" SID "7901" Ports [2, 1] Position [770, 218, 815, 262] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a>b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "500,165,356,193" block_type "relational" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,2,1,white,blue,0,b5131c97,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bfa > b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "done1" SID "7908" Ports [1, 1] Position [1125, 410, 1160, 420] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Det Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "done14" SID "7909" Ports [1, 1] Position [600, 570, 635, 580] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "done2" SID "7910" Ports [1, 1] Position [1125, 380, 1160, 390] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Min Dur Met" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "done3" SID "14946" Ports [1, 1] Position [1125, 425, 1160, 435] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Min dur counter" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "done5" SID "7911" Ports [1, 1] Position [1125, 395, 1160, 405] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Reset" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "done6" SID "7912" Ports [1, 1] Position [1125, 365, 1160, 375] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Det In" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Outport Name "Pkt Det " SID "7913" Position [1050, 233, 1080, 247] IconDisplay "Port number" } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Counter1" DstPort 1 } Line { SrcBlock "Inverter1" SrcPort 1 DstBlock "Logical1" DstPort 2 } Line { SrcBlock "Counter1" SrcPort 1 Points [5, 0] Branch { DstBlock "Relational3" DstPort 1 } Branch { Points [0, 200] DstBlock "done3" DstPort 1 } } Line { SrcBlock "From4" SrcPort 1 Points [25, 0] DstBlock "Relational3" DstPort 2 } Line { SrcBlock "Relational3" SrcPort 1 Points [20, 0] Branch { DstBlock "Posedge1" DstPort 1 } Branch { Points [0, 95] Branch { DstBlock "Inverter2" DstPort 1 } Branch { Points [0, 50] DstBlock "done2" DstPort 1 } } } Line { SrcBlock "done14" SrcPort 1 DstBlock "Display" DstPort 1 } Line { Name "Min Dur Met" Labels [0, 0] SrcBlock "done2" SrcPort 1 DstBlock "Pkt Det Ctrl Min Dur" DstPort 2 } Line { Name "Reset" Labels [0, 0] SrcBlock "done5" SrcPort 1 DstBlock "Pkt Det Ctrl Min Dur" DstPort 3 } Line { Name "Det Out" Labels [0, 0] SrcBlock "done1" SrcPort 1 DstBlock "Pkt Det Ctrl Min Dur" DstPort 4 } Line { SrcBlock "Logical2" SrcPort 1 DstBlock "Counter1" DstPort 2 } Line { SrcBlock "Inverter2" SrcPort 1 Points [-160, 0; 0, -85] DstBlock "Logical2" DstPort 2 } Line { SrcBlock "Posedge1" SrcPort 1 Points [85, 0] Branch { DstBlock "Pkt Det " DstPort 1 } Branch { Points [0, 175] DstBlock "done1" DstPort 1 } } Line { SrcBlock "From1" SrcPort 1 DstBlock "done14" DstPort 1 } Line { Name "Det In" Labels [0, 0] SrcBlock "done6" SrcPort 1 DstBlock "Pkt Det Ctrl Min Dur" DstPort 1 } Line { SrcBlock "Reset " SrcPort 1 Points [35, 0; 0, 50] Branch { DstBlock "Logical1" DstPort 1 } Branch { Points [0, 200] DstBlock "done5" DstPort 1 } } Line { SrcBlock "Det " SrcPort 1 Points [55, 0] Branch { DstBlock "Logical2" DstPort 1 } Branch { Points [0, 0] Branch { Points [0, -25] DstBlock "Inverter1" DstPort 1 } Branch { Points [0, 130] DstBlock "done6" DstPort 1 } } } Line { Name "Min dur counter" Labels [0, 0] SrcBlock "done3" SrcPort 1 DstBlock "Pkt Det Ctrl Min Dur" DstPort 5 } Line { SrcBlock "iq_vld" SrcPort 1 Points [40, 0; 0, -45] DstBlock "Logical2" DstPort 3 } Annotation { Position [1152, 227] } } } Block { BlockType SubSystem Name "Min Dur1" SID "14950" Ports [3, 1] Position [905, 610, 995, 670] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Min Dur1" Location [202, 70, 1830, 1180] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Reset " SID "14951" Position [355, 143, 385, 157] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "Det " SID "14952" Position [355, 233, 385, 247] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "iq_vld" SID "14953" Position [330, 298, 360, 312] Port "3" IconDisplay "Port number" } Block { BlockType Reference Name "Counter1" SID "14954" Ports [2, 1] Position [695, 189, 725, 271] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited count" "er is implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "Inf" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "5" bin_pt "0" load_pin off rst on en on explicit_period "off" period "4" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,619" block_type "counter" block_version "10.1.3" sg_icon_stat "30,82,2,1,white,blue,0,ae3608d6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 82 82 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 82 82 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[45.44 45.4" "4 49.44 45.44 49.44 49.44 49.44 45.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[41.44 41.44 45.44 45.44 " "41.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[37.44 37.44 41.44 41.44 37.44 ],[1 1 1 ]);\np" "atch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[33.44 33.44 37.44 33.44 37.44 37.44 33.44 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label" "('input',1,'rst');\ncolor('black');port_label('input',2,'en');\n\ncolor('black');disp('{\\fontsize{14}\\bf++}','" "texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Display Name "Display" SID "14955" Ports [1] Position [675, 561, 760, 589] ShowName off Decimation "1" Lockdown off } Block { BlockType From Name "From1" SID "14956" Position [295, 566, 535, 584] ShowName off CloseFcn "tagdialog Close" GotoTag "regPktDet_pktDetMinDuration_autoCorr_A" TagVisibility "global" } Block { BlockType From Name "From4" SID "14957" Position [485, 271, 725, 289] ShowName off CloseFcn "tagdialog Close" GotoTag "regPktDet_pktDetMinDuration_autoCorr_A" TagVisibility "global" } Block { BlockType Reference Name "Inverter1" SID "14958" Ports [1, 1] Position [530, 208, 555, 222] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "8.2" sg_icon_stat "25,14,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfprintf" "('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter2" SID "14959" Ports [1, 1] Position [635, 328, 660, 342] BlockMirror on ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "8.2" sg_icon_stat "25,14,1,1,white,blue,0,267846e5,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfprintf" "('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "14960" Ports [2, 1] Position [615, 194, 645, 221] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,261" block_type "logical" block_version "10.1.3" sg_icon_stat "30,27,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 27 27 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 27 27 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[16.3" "3 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 13.33 " "16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13.33 10." "33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n" "color('black');disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "14961" Ports [3, 1] Position [590, 231, 620, 269] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,261" block_type "logical" block_version "10.1.3" sg_icon_stat "30,38,3,1,white,blue,0,98d76266,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 38 38 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 38 38 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[23.44 23.4" "4 27.44 23.44 27.44 27.44 27.44 23.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[19.44 19.44 23.44 23.44 " "19.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[15.44 15.44 19.44 19.44 15.44 ],[1 1 1 ]);\np" "atch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[11.44 11.44 15.44 11.44 15.44 15.44 11.44 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\ncolor('black');di" "sp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Scope Name "Pkt Det Ctrl Min Dur" SID "14962" Ports [7] Position [1270, 360, 1315, 470] Floating off Location [-18, 112, 1814, 1266] Open off NumInputPorts "7" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" } List { ListType ScopeGraphics FigureColor "[0.5 0.5 0.5]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "10000" YMin "0~0~0~0~-1~-1~-1" YMax "1~1~1~1~1~1~1" SaveName "ScopeData6" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType SubSystem Name "Posedge1" SID "14963" Ports [1, 1] Position [870, 231, 915, 249] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Posedge1" Location [88, 301, 2330, 1301] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "14964" Position [200, 253, 230, 267] IconDisplay "Port number" } Block { BlockType Reference Name "Delay" SID "14965" Ports [1, 1] Position [425, 153, 460, 177] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. " "If register retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[15" ".33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.33 12." "33 15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 12.33 " "9.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\nc" "olor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "14966" Ports [1, 1] Position [490, 156, 515, 174] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "14967" Ports [2, 1] Position [540, 151, 585, 204] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,53,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 53 53 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 53 53 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[32.66 3" "2.66 38.66 32.66 38.66 38.66 38.66 32.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[26.66 26.66 32.66 " "32.66 26.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[20.66 20.66 26.66 26.66 20.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[14.66 14.66 20.66 14.66 20.66 20.66 14.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('" "black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "14968" Position [610, 173, 640, 187] IconDisplay "Port number" } Line { SrcBlock "D" SrcPort 1 Points [150, 0; 0, -70] Branch { DstBlock "Logical1" DstPort 2 } Branch { Points [0, -25] DstBlock "Delay" DstPort 1 } } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Delay" SrcPort 1 DstBlock "Inverter" DstPort 1 } Annotation { Name "Rising Edge Detection" Position [500, 112] } } } Block { BlockType Reference Name "Relational3" SID "14969" Ports [2, 1] Position [770, 218, 815, 262] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a>b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "500,165,356,193" block_type "relational" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,2,1,white,blue,0,b5131c97,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bfa > b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "done1" SID "14970" Ports [1, 1] Position [1125, 410, 1160, 420] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Det Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "done14" SID "14971" Ports [1, 1] Position [600, 570, 635, 580] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "done2" SID "14972" Ports [1, 1] Position [1125, 380, 1160, 390] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Min Dur Met" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "done3" SID "14973" Ports [1, 1] Position [1125, 425, 1160, 435] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Min dur counter" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "done5" SID "14974" Ports [1, 1] Position [1125, 395, 1160, 405] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Reset" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "done6" SID "14975" Ports [1, 1] Position [1125, 365, 1160, 375] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Det In" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Outport Name "Pkt Det " SID "14976" Position [1050, 233, 1080, 247] IconDisplay "Port number" } Line { SrcBlock "iq_vld" SrcPort 1 Points [40, 0; 0, -45] DstBlock "Logical2" DstPort 3 } Line { Name "Min dur counter" Labels [0, 0] SrcBlock "done3" SrcPort 1 DstBlock "Pkt Det Ctrl Min Dur" DstPort 5 } Line { SrcBlock "Det " SrcPort 1 Points [55, 0] Branch { Points [0, 0] Branch { Points [0, 130] DstBlock "done6" DstPort 1 } Branch { Points [0, -25] DstBlock "Inverter1" DstPort 1 } } Branch { DstBlock "Logical2" DstPort 1 } } Line { SrcBlock "Reset " SrcPort 1 Points [35, 0; 0, 50] Branch { Points [0, 200] DstBlock "done5" DstPort 1 } Branch { DstBlock "Logical1" DstPort 1 } } Line { Name "Det In" Labels [0, 0] SrcBlock "done6" SrcPort 1 DstBlock "Pkt Det Ctrl Min Dur" DstPort 1 } Line { SrcBlock "From1" SrcPort 1 DstBlock "done14" DstPort 1 } Line { SrcBlock "Posedge1" SrcPort 1 Points [85, 0] Branch { Points [0, 175] DstBlock "done1" DstPort 1 } Branch { DstBlock "Pkt Det " DstPort 1 } } Line { SrcBlock "Inverter2" SrcPort 1 Points [-160, 0; 0, -85] DstBlock "Logical2" DstPort 2 } Line { SrcBlock "Logical2" SrcPort 1 DstBlock "Counter1" DstPort 2 } Line { Name "Det Out" Labels [0, 0] SrcBlock "done1" SrcPort 1 DstBlock "Pkt Det Ctrl Min Dur" DstPort 4 } Line { Name "Reset" Labels [0, 0] SrcBlock "done5" SrcPort 1 DstBlock "Pkt Det Ctrl Min Dur" DstPort 3 } Line { Name "Min Dur Met" Labels [0, 0] SrcBlock "done2" SrcPort 1 DstBlock "Pkt Det Ctrl Min Dur" DstPort 2 } Line { SrcBlock "done14" SrcPort 1 DstBlock "Display" DstPort 1 } Line { SrcBlock "Relational3" SrcPort 1 Points [20, 0] Branch { Points [0, 95] Branch { Points [0, 50] DstBlock "done2" DstPort 1 } Branch { DstBlock "Inverter2" DstPort 1 } } Branch { DstBlock "Posedge1" DstPort 1 } } Line { SrcBlock "From4" SrcPort 1 Points [25, 0] DstBlock "Relational3" DstPort 2 } Line { SrcBlock "Counter1" SrcPort 1 Points [5, 0] Branch { Points [0, 200] DstBlock "done3" DstPort 1 } Branch { DstBlock "Relational3" DstPort 1 } } Line { SrcBlock "Inverter1" SrcPort 1 DstBlock "Logical1" DstPort 2 } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Counter1" DstPort 1 } Annotation { Position [1152, 227] } } } Block { BlockType Reference Name "Mult1" SID "7945" Ports [2, 1] Position [455, 377, 505, 433] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mult" SourceType "Xilinx Multiplier Block" infoedit "Hardware notes: To check for the optimum internal pipeline stages of the dedicated multiplier you" " must select 'Test for optimum pipelining'.

Optimization Goal: For implementation into device fabric (LUT" "s), the Speed or Area optimization will take effect only if it's supported by IP for the particular device famil" "y. Otherwise, the results will be identical regardless of the selection." precision "User Defined" arith_type "Unsigned" n_bits "28" bin_pt "20" quantization "Truncate" overflow "Flag as error" en off latency "1" dbl_ovrd off use_behavioral_HDL off opt "Speed" use_embedded on optimum_pipeline off xl_use_area off xl_area "[63 105 0 106 0 4 0]" pipeline "on" use_rpm "off" placement_style "Rectangular shape" has_advanced_control "0" sggui_pos "1126,548,356,577" block_type "mult" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,56,2,1,white,blue,0,82c891c1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 56 56 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 56 56 0 ]);\npatch([9.425 19.54 26.54 33.54 40.54 26.54 16.425 9.425 ],[35.7" "7 35.77 42.77 35.77 42.77 42.77 42.77 35.77 ],[1 1 1 ]);\npatch([16.425 26.54 19.54 9.425 16.425 ],[28.77 28.77 " "35.77 35.77 28.77 ],[0.931 0.946 0.973 ]);\npatch([9.425 19.54 26.54 16.425 9.425 ],[21.77 21.77 28.77 28.77 21." "77 ],[1 1 1 ]);\npatch([16.425 40.54 33.54 26.54 19.54 9.425 16.425 ],[14.77 14.77 21.77 14.77 21.77 21.77 14.77" " ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nc" "olor('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('" "output',1,'\\bfa \\times b','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('bl" "ack');disp(' \\n ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mult2" SID "7946" Ports [2, 1] Position [455, 632, 505, 688] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mult" SourceType "Xilinx Multiplier Block" infoedit "Hardware notes: To check for the optimum internal pipeline stages of the dedicated multiplier you" " must select 'Test for optimum pipelining'.

Optimization Goal: For implementation into device fabric (LUT" "s), the Speed or Area optimization will take effect only if it's supported by IP for the particular device famil" "y. Otherwise, the results will be identical regardless of the selection." precision "User Defined" arith_type "Unsigned" n_bits "27" bin_pt "20" quantization "Truncate" overflow "Flag as error" en off latency "1" dbl_ovrd off use_behavioral_HDL off opt "Speed" use_embedded on optimum_pipeline off xl_use_area off xl_area "[63 105 0 106 0 4 0]" pipeline "on" use_rpm "off" placement_style "Rectangular shape" has_advanced_control "0" sggui_pos "675,561,356,577" block_type "mult" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,56,2,1,white,blue,0,82c891c1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 56 56 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 56 56 0 ]);\npatch([9.425 19.54 26.54 33.54 40.54 26.54 16.425 9.425 ],[35.7" "7 35.77 42.77 35.77 42.77 42.77 42.77 35.77 ],[1 1 1 ]);\npatch([16.425 26.54 19.54 9.425 16.425 ],[28.77 28.77 " "35.77 35.77 28.77 ],[0.931 0.946 0.973 ]);\npatch([9.425 19.54 26.54 16.425 9.425 ],[21.77 21.77 28.77 28.77 21." "77 ],[1 1 1 ]);\npatch([16.425 40.54 33.54 26.54 19.54 9.425 16.425 ],[14.77 14.77 21.77 14.77 21.77 21.77 14.77" " ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nc" "olor('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('" "output',1,'\\bfa \\times b','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('bl" "ack');disp(' \\n ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "7947" Ports [2, 1] Position [140, 404, 165, 431] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,27,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 27 27 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 27 27 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 " "16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33" " 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q'" ");\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "7948" Ports [2, 1] Position [150, 594, 175, 621] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,27,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 27 27 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 27 27 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 " "16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33" " 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q'" ");\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register3" SID "7949" Ports [2, 1] Position [140, 334, 165, 361] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,27,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 27 27 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 27 27 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 " "16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33" " 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q'" ");\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register4" SID "17486" Ports [2, 1] Position [150, 534, 175, 561] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,27,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 27 27 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 27 27 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 " "16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33" " 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q'" ");\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register6" SID "11293" Ports [1, 1] Position [1005, 714, 1035, 746] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,32,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 32 32 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 32 32 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[20.44 20.4" "4 24.44 20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[16.44 16.44 20.44 20.44 " "16.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1 1 1 ]);\np" "atch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('in" "put',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf" "('','COMMENT: end icon text');" } Block { BlockType Reference Name "Reinterpret" SID "7950" Ports [1, 1] Position [420, 1123, 445, 1137] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can change the signal betwe" "en signed and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothi" "ng.

Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced " "to unsigned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output " "of 56 (111000 in binary)." force_arith_type on arith_type "Unsigned" force_bin_pt on bin_pt "0" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "reinterpret" sg_icon_stat "25,14,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('reinterpret');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Reinterpret1" SID "7951" Ports [1, 1] Position [420, 1188, 445, 1202] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can change the signal betwe" "en signed and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothi" "ng.

Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced " "to unsigned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output " "of 56 (111000 in binary)." force_arith_type on arith_type "Unsigned" force_bin_pt on bin_pt "0" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "reinterpret" sg_icon_stat "25,14,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('reinterpret');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Reinterpret2" SID "7952" Ports [1, 1] Position [995, 1123, 1020, 1137] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can change the signal betwe" "en signed and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothi" "ng.

Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced " "to unsigned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output " "of 56 (111000 in binary)." force_arith_type on arith_type "Unsigned" force_bin_pt on bin_pt "0" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "reinterpret" sg_icon_stat "25,14,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('reinterpret');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Reinterpret3" SID "7953" Ports [1, 1] Position [975, 1188, 1000, 1202] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can change the signal betwe" "en signed and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothi" "ng.

Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced " "to unsigned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output " "of 56 (111000 in binary)." force_arith_type on arith_type "Unsigned" force_bin_pt on bin_pt "0" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "reinterpret" sg_icon_stat "25,14,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('reinterpret');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational" SID "7954" Ports [2, 1] Position [565, 338, 610, 382] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a>b" en off latency "1" dbl_ovrd off xl_use_area off xl_area "[11 1 0 22 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,2,1,white,blue,0,3049caaa,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bfa > b','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\n ')" ";\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational1" SID "7955" Ports [2, 1] Position [565, 478, 610, 522] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a>b" en off latency "1" dbl_ovrd off xl_use_area off xl_area "[11 1 0 22 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "relational" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,2,1,white,blue,0,3049caaa,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bfa > b','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\n ')" ";\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational2" SID "7956" Ports [2, 1] Position [565, 628, 610, 672] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a>b" en off latency "1" dbl_ovrd off xl_use_area off xl_area "[11 1 0 22 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,2,1,white,blue,0,3049caaa,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bfa > b','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\n ')" ";\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational3" SID "7957" Ports [2, 1] Position [565, 538, 610, 582] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a>b" en off latency "1" dbl_ovrd off xl_use_area off xl_area "[11 1 0 22 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "relational" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,2,1,white,blue,0,3049caaa,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bfa > b','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\n ')" ";\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "S-R Latch" SID "7902" Ports [2, 1] Position [1230, 366, 1260, 464] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "S-R Latch" Location [160, 70, 1918, 1152] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "R" SID "7903" Position [140, 88, 170, 102] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "S" SID "7904" Position [140, 103, 170, 117] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "7905" Ports [0, 1] Position [195, 71, 210, 89] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "15,18,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11.22 " "13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 9.22 " "],[0.931 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([4.55 " "11.44 9.44 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "7906" Ports [3, 1] Position [255, 71, 300, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "7907" Position [325, 88, 355, 102] IconDisplay "Port number" } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "S" SrcPort 1 DstBlock "Register2" DstPort 3 } } } Block { BlockType SubSystem Name "S-R Latch1" SID "10925" Ports [2, 1] Position [1230, 577, 1265, 673] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "S-R Latch1" Location [160, 70, 1918, 1152] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "R" SID "10926" Position [140, 88, 170, 102] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "S" SID "10927" Position [140, 103, 170, 117] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "10928" Ports [0, 1] Position [195, 71, 210, 89] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "15,18,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11.22 " "13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 9.22 " "],[0.931 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([4.55 " "11.44 9.44 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "10929" Ports [3, 1] Position [255, 71, 300, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "10930" Position [325, 88, 355, 102] IconDisplay "Port number" } Line { SrcBlock "S" SrcPort 1 DstBlock "Register2" DstPort 3 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Register2" DstPort 1 } } } Block { BlockType Reference Name "done1" SID "7958" Ports [1, 1] Position [990, 1100, 1025, 1110] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "done10" SID "7959" Ports [1, 1] Position [970, 1165, 1005, 1175] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "done11" SID "7960" Ports [1, 1] Position [1030, 1190, 1065, 1200] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "done12" SID "7961" Ports [1, 1] Position [1350, 155, 1385, 165] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Det DSSS" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "done13" SID "15916" Ports [1, 1] Position [1195, 240, 1230, 250] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "done14" SID "7962" Ports [1, 1] Position [415, 1100, 450, 1110] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "done15" SID "7963" Ports [1, 1] Position [415, 1165, 450, 1175] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "done16" SID "15917" Ports [1, 1] Position [1195, 160, 1230, 170] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "done17" SID "7964" Ports [1, 1] Position [475, 1125, 510, 1135] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "done18" SID "7965" Ports [1, 1] Position [475, 1190, 510, 1200] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "done19" SID "17434" Ports [1, 1] Position [1195, 225, 1230, 235] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "done2" SID "7966" Ports [1, 1] Position [1050, 1125, 1085, 1135] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "done20" SID "17487" Ports [1, 1] Position [1195, 175, 1230, 185] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "done3" SID "7967" Ports [1, 1] Position [1350, 65, 1385, 75] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Scaled Mag 16" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "done4" SID "7968" Ports [1, 1] Position [1350, 50, 1385, 60] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr 16" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "done5" SID "7969" Ports [1, 1] Position [1350, 80, 1385, 90] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr 20" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "done6" SID "7970" Ports [1, 1] Position [1350, 95, 1385, 105] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Scaled Mag 20" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "done7" SID "7971" Ports [1, 1] Position [1350, 110, 1385, 120] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Det 16" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "done8" SID "7972" Ports [1, 1] Position [1350, 125, 1385, 135] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Det 20" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "done9" SID "7973" Ports [1, 1] Position [1350, 140, 1385, 150] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Det OFDM" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Outport Name "Det OFDM" SID "7974" Position [1330, 407, 1360, 423] IconDisplay "Port number" } Block { BlockType Outport Name "Det DSSS" SID "7975" Position [1330, 617, 1360, 633] Port "2" IconDisplay "Port number" } Line { SrcBlock "done18" SrcPort 1 DstBlock "Display3" DstPort 1 } Line { SrcBlock "Reinterpret1" SrcPort 1 DstBlock "done18" DstPort 1 } Line { SrcBlock "done17" SrcPort 1 DstBlock "Display2" DstPort 1 } Line { SrcBlock "Reinterpret" SrcPort 1 DstBlock "done17" DstPort 1 } Line { SrcBlock "done15" SrcPort 1 DstBlock "Display1" DstPort 1 } Line { SrcBlock "done14" SrcPort 1 DstBlock "Display" DstPort 1 } Line { SrcBlock "From3" SrcPort 1 Points [25, 0] Branch { Points [0, 25] DstBlock "Reinterpret" DstPort 1 } Branch { DstBlock "done14" DstPort 1 } } Line { SrcBlock "From2" SrcPort 1 Points [35, 0] Branch { Points [0, 25] DstBlock "Reinterpret1" DstPort 1 } Branch { DstBlock "done15" DstPort 1 } } Line { SrcBlock "Corr_16" SrcPort 1 DstBlock "Register3" DstPort 1 } Line { SrcBlock "Mag 16" SrcPort 1 DstBlock "Register1" DstPort 1 } Line { SrcBlock "From1" SrcPort 1 DstBlock "Mult1" DstPort 1 } Line { SrcBlock "Mult1" SrcPort 1 Points [20, 0; 0, -35] Branch { DstBlock "Relational" DstPort 2 } Branch { Points [0, -300; 600, 0] Branch { DstBlock "done3" DstPort 1 } Branch { Points [0, 175] DstBlock "done13" DstPort 1 } } } Line { SrcBlock "From4" SrcPort 1 DstBlock "Relational1" DstPort 2 } Line { SrcBlock "Relational" SrcPort 1 Points [50, 0; 0, 60] DstBlock "Logical" DstPort 1 } Line { SrcBlock "Relational1" SrcPort 1 Points [50, 0; 0, -60] DstBlock "Logical" DstPort 2 } Line { SrcBlock "Relational2" SrcPort 1 DstBlock "Logical1" DstPort 2 } Line { SrcBlock "Logical" SrcPort 1 Points [10, 0] Branch { Points [0, -315] DstBlock "done7" DstPort 1 } Branch { DstBlock "Min Dur" DstPort 2 } } Line { SrcBlock "Logical1" SrcPort 1 Points [25, 0] Branch { Points [0, -510] DstBlock "done8" DstPort 1 } Branch { DstBlock "Min Dur1" DstPort 2 } } Line { SrcBlock "From5" SrcPort 1 DstBlock "Mult2" DstPort 2 } Line { SrcBlock "Mult2" SrcPort 1 Points [30, 0] Branch { DstBlock "Relational2" DstPort 2 } Branch { Points [0, -560; 615, 0] Branch { DstBlock "done6" DstPort 1 } Branch { Points [0, 80] DstBlock "done20" DstPort 1 } } } Line { SrcBlock "Corr_20" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "done2" SrcPort 1 DstBlock "Display5" DstPort 1 } Line { SrcBlock "Reinterpret2" SrcPort 1 DstBlock "done2" DstPort 1 } Line { SrcBlock "done1" SrcPort 1 DstBlock "Display4" DstPort 1 } Line { SrcBlock "From6" SrcPort 1 Points [25, 0] Branch { DstBlock "done1" DstPort 1 } Branch { Points [0, 25] DstBlock "Reinterpret2" DstPort 1 } } Line { Name "Corr 16" Labels [0, 0] SrcBlock "done4" SrcPort 1 DstBlock "Auto Corr Decision" DstPort 1 } Line { Name "Scaled Mag 16" Labels [0, 0] SrcBlock "done3" SrcPort 1 DstBlock "Auto Corr Decision" DstPort 2 } Line { Name "Corr 20" Labels [0, 0] SrcBlock "done5" SrcPort 1 DstBlock "Auto Corr Decision" DstPort 3 } Line { Name "Scaled Mag 20" Labels [0, 0] SrcBlock "done6" SrcPort 1 DstBlock "Auto Corr Decision" DstPort 4 } Line { Name "Det 16" Labels [0, 0] SrcBlock "done7" SrcPort 1 DstBlock "Auto Corr Decision" DstPort 5 } Line { Name "Det 20" Labels [0, 0] SrcBlock "done8" SrcPort 1 DstBlock "Auto Corr Decision" DstPort 6 } Line { Name "Det OFDM" Labels [0, 0] SrcBlock "done9" SrcPort 1 DstBlock "Auto Corr Decision" DstPort 7 } Line { SrcBlock "From7" SrcPort 1 DstBlock "Relational3" DstPort 2 } Line { SrcBlock "Relational3" SrcPort 1 Points [25, 0; 0, 70] DstBlock "Logical1" DstPort 1 } Line { SrcBlock "done11" SrcPort 1 DstBlock "Display7" DstPort 1 } Line { SrcBlock "Reinterpret3" SrcPort 1 DstBlock "done11" DstPort 1 } Line { SrcBlock "done10" SrcPort 1 DstBlock "Display6" DstPort 1 } Line { SrcBlock "From8" SrcPort 1 Points [35, 0] Branch { DstBlock "done10" DstPort 1 } Branch { Points [0, 25] DstBlock "Reinterpret3" DstPort 1 } } Line { Name "Det DSSS" Labels [0, 0] SrcBlock "done12" SrcPort 1 DstBlock "Auto Corr Decision" DstPort 8 } Line { SrcBlock "Reset OFDM" SrcPort 1 Points [30, 0] Branch { DstBlock "Min Dur" DstPort 1 } Branch { Points [0, -20] DstBlock "S-R Latch" DstPort 1 } } Line { SrcBlock "Reset DSSS" SrcPort 1 Points [15, 0] Branch { Points [0, -20] DstBlock "S-R Latch1" DstPort 1 } Branch { DstBlock "Min Dur1" DstPort 1 } } Line { SrcBlock "Min Dur" SrcPort 1 Points [10, 0] Branch { Points [0, -285] DstBlock "done9" DstPort 1 } Branch { DstBlock "Logical2" DstPort 1 } } Line { SrcBlock "Min Dur1" SrcPort 1 Points [15, 0] Branch { Points [0, -480] DstBlock "done12" DstPort 1 } Branch { DstBlock "Logical3" DstPort 1 } } Line { SrcBlock "Register3" SrcPort 1 DstBlock "Delay" DstPort 1 } Line { SrcBlock "Register1" SrcPort 1 Points [260, 0] Branch { DstBlock "Mult1" DstPort 2 } Branch { Points [0, 70] DstBlock "Delay3" DstPort 1 } } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Delay1" DstPort 1 } Line { SrcBlock "S-R Latch1" SrcPort 1 DstBlock "Det DSSS" DstPort 1 } Line { SrcBlock "S-R Latch" SrcPort 1 DstBlock "Det OFDM" DstPort 1 } Line { SrcBlock "Logical2" SrcPort 1 DstBlock "S-R Latch" DstPort 2 } Line { SrcBlock "From9" SrcPort 1 DstBlock "Inverter" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Register6" DstPort 1 } Line { SrcBlock "Logical3" SrcPort 1 DstBlock "S-R Latch1" DstPort 2 } Line { SrcBlock "Register6" SrcPort 1 Points [15, 0; 0, -70] Branch { Points [0, -210] DstBlock "Logical2" DstPort 2 } Branch { DstBlock "Logical3" DstPort 2 } } Line { SrcBlock "iq_vld" SrcPort 1 Points [50, 0] Branch { Points [575, 0; 0, -245; 125, 0] Branch { Points [0, -80] DstBlock "Min Dur" DstPort 3 } Branch { Points [0, 130] DstBlock "Min Dur1" DstPort 3 } } Branch { Points [0, -160] Branch { DstBlock "Register2" DstPort 2 } Branch { Points [0, -60] Branch { DstBlock "Register4" DstPort 2 } Branch { Points [0, -130] Branch { Points [0, -70] DstBlock "Register3" DstPort 2 } Branch { DstBlock "Register1" DstPort 2 } } } } } Line { Name "OFDM Ratio" Labels [3, 1] SrcBlock "Divide1" SrcPort 1 Points [30, 0; 0, -50] DstBlock "Auto Corr Decision" DstPort 10 } Line { SrcBlock "done16" SrcPort 1 DstBlock "Divide" DstPort 1 } Line { SrcBlock "done13" SrcPort 1 DstBlock "Divide1" DstPort 2 } Line { Name "DSSS Ratio" Labels [1, 1] SrcBlock "Divide" SrcPort 1 DstBlock "Auto Corr Decision" DstPort 9 } Line { SrcBlock "done19" SrcPort 1 DstBlock "Divide1" DstPort 1 } Line { SrcBlock "Mag 20" SrcPort 1 DstBlock "Register4" DstPort 1 } Line { SrcBlock "Register4" SrcPort 1 Points [240, 0] Branch { Points [0, 95] DstBlock "Mult2" DstPort 1 } Branch { DstBlock "Delay2" DstPort 1 } } Line { SrcBlock "done20" SrcPort 1 DstBlock "Divide" DstPort 2 } Line { SrcBlock "Delay" SrcPort 1 Points [15, 0] Branch { DstBlock "Relational" DstPort 1 } Branch { Points [0, -295; 620, 0] Branch { DstBlock "done4" DstPort 1 } Branch { Points [0, 175] DstBlock "done19" DstPort 1 } } } Line { SrcBlock "Delay1" SrcPort 1 Points [25, 0] Branch { Points [0, 30] DstBlock "Relational2" DstPort 1 } Branch { Points [0, -525; 635, 0] Branch { DstBlock "done5" DstPort 1 } Branch { Points [0, 80] DstBlock "done16" DstPort 1 } } } Line { SrcBlock "Delay2" SrcPort 1 DstBlock "Relational3" DstPort 1 } Line { SrcBlock "Delay3" SrcPort 1 DstBlock "Relational1" DstPort 1 } } } Block { BlockType SubSystem Name "Mag" SID "7976" Ports [3, 2] Position [635, 298, 705, 392] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Mag" Location [227, 108, 1983, 1242] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "155" Block { BlockType Inport Name "Valid" SID "7977" Position [85, 173, 115, 187] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "I" SID "7978" Position [85, 223, 115, 237] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "Q" SID "7979" Position [85, 293, 115, 307] Port "3" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub" SID "7980" Ports [2, 1] Position [350, 231, 380, 289] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Signed (2's comp)" n_bits "23" bin_pt "20" quantization "Truncate" overflow "Flag as error" dbl_ovrd off use_behavioral_HDL off hw_selection "Fabric" pipelined off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" sg_icon_stat "30,58,2,1,white,blue,0,e139daf6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 58 58 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 58 58 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[33.44 33.4" "4 37.44 33.44 37.44 37.44 37.44 33.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[29.44 29.44 33.44 33.44 " "29.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[25.44 25.44 29.44 29.44 25.44 ],[1 1 1 ]);\np" "atch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[21.44 21.44 25.44 21.44 25.44 25.44 21.44 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label" "('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bf{a + b}'," "'texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Scope Name "Auto Corr Mag Calc" SID "15895" Ports [9] Position [865, 395, 910, 545] Floating off Location [1, 45, 1836, 1199] Open off NumInputPorts "9" ZoomMode "yonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" axes9 "%" } List { ListType ScopeGraphics FigureColor "[0.5 0.5 0.5]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "40000" YMin "-0.4~-1~0~0~0~-1~0.95~0.95~-1" YMax "0.4~1~0.45~0.04~0.6~1~1.05~1.05~1" SaveName "ScopeData41" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType Reference Name "Delay" SID "7981" Ports [1, 1] Position [265, 166, 300, 194] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "3" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,28,1,1,white,blue,0,83e6bb61,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 28 28 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[18.44 18.4" "4 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[14.44 14.44 18.44 18.44 " "14.44 ],[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\np" "atch([12.1 25.88 21.88 17.88 13.88 8.1 12.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-" "3}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Goto Name "Goto" SID "18158" Position [725, 137, 960, 153] ZOrder -10 ForegroundColor "red" ShowName off GotoTag "reg_RFA_RXIQ_MAG_SUM_40SAMP" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Mult" SID "7982" Ports [2, 1] Position [265, 214, 300, 276] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mult" SourceType "Xilinx Multiplier Block" infoedit "Hardware notes: To check for the optimum internal pipeline stages of the dedicated multiplier you" " must select 'Test for optimum pipelining'.

Optimization Goal: For implementation into device fabric (LUT" "s), the Speed or Area optimization will take effect only if it's supported by IP for the particular device famil" "y. Otherwise, the results will be identical regardless of the selection." precision "User Defined" arith_type "Signed (2's comp)" n_bits "22" bin_pt "20" quantization "Truncate" overflow "Flag as error" en off latency "3" dbl_ovrd off use_behavioral_HDL off opt "Speed" use_embedded on optimum_pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" pipeline "on" use_rpm "on" placement_style "Triangular" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mult" sg_icon_stat "35,62,2,1,white,blue,0,7028354c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 62 62 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 62 62 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[36.55 36." "55 41.55 36.55 41.55 41.55 41.55 36.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[31.55 31.55 36.55 3" "6.55 31.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[26.55 26.55 31.55 31.55 26.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[21.55 21.55 26.55 21.55 26.55 26.55 21.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bfa \\times b','texmode','on');\ncolor('black');disp('z^{-3}\\newline ','texmode','on');\ncolor('black');disp(' " "\\n ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mult1" SID "15919" Ports [2, 1] Position [265, 284, 300, 346] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mult" SourceType "Xilinx Multiplier Block" infoedit "Hardware notes: To check for the optimum internal pipeline stages of the dedicated multiplier you" " must select 'Test for optimum pipelining'.

Optimization Goal: For implementation into device fabric (LUT" "s), the Speed or Area optimization will take effect only if it's supported by IP for the particular device famil" "y. Otherwise, the results will be identical regardless of the selection." precision "User Defined" arith_type "Signed (2's comp)" n_bits "22" bin_pt "20" quantization "Truncate" overflow "Flag as error" en off latency "3" dbl_ovrd off use_behavioral_HDL off opt "Speed" use_embedded on optimum_pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" pipeline "on" use_rpm "on" placement_style "Triangular" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mult" sg_icon_stat "35,62,2,1,white,blue,0,7028354c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 62 62 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 62 62 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[36.55 36." "55 41.55 36.55 41.55 41.55 41.55 36.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[31.55 31.55 36.55 3" "6.55 31.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[26.55 26.55 31.55 31.55 26.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[21.55 21.55 26.55 21.55 26.55 26.55 21.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bfa \\times b','texmode','on');\ncolor('black');disp('z^{-3}\\newline ','texmode','on');\ncolor('black');disp(' " "\\n ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Running Sum" SID "7985" Ports [2, 2] Position [465, 207, 530, 258] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Running Sum" Location [227, 108, 1983, 1242] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "En" SID "7986" Position [195, 183, 225, 197] IconDisplay "Port number" } Block { BlockType Inport Name "D" SID "7987" Position [195, 123, 225, 137] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Accum1" SID "7988" Ports [2, 1] Position [520, 131, 570, 184] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Accumulator" SourceType "Xilinx Accumulator Block" infoedit "Adder or subtracter-based accumulator. Output type and binary point position match the input.
Hardware notes: When \"Reinitialize with input 'b' on reset\" is selected, the accumulator is forced to ru" "n at the system rate even if the input 'b' is running at a slower rate." operation "Add" n_bits "28" overflow "Flag as error" scale "1" rst off infoeditControl "reset for floating point data type must be asserted for a minimum of 2 cycles" hasbypass off en on latency "0" dbl_ovrd off msb_inp "100" msb "100" lsb "-100" use_behavioral_HDL on implementation "Fabric" xl_use_area off xl_area "[12 23 0 22 0 0 0]" has_advanced_control "0" sggui_pos "20,20,367,457" block_type "accum" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,53,2,1,white,blue,0,debef366,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 53 53 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 53 53 0 ]);\npatch([9.425 19.54 26.54 33.54 40.54 26.54 16.425 9.425 ],[33.7" "7 33.77 40.77 33.77 40.77 40.77 40.77 33.77 ],[1 1 1 ]);\npatch([16.425 26.54 19.54 9.425 16.425 ],[26.77 26.77 " "33.77 33.77 26.77 ],[0.931 0.946 0.973 ]);\npatch([9.425 19.54 26.54 16.425 9.425 ],[19.77 19.77 26.77 26.77 19." "77 ],[1 1 1 ]);\npatch([16.425 40.54 33.54 26.54 19.54 9.425 16.425 ],[12.77 12.77 19.77 12.77 19.77 19.77 12.77" " ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nc" "olor('black');port_label('input',1,'b');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label(" "'output',1,'\\bf+=b','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Accum2" SID "17476" Ports [2, 1] Position [520, 266, 570, 319] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Accumulator" SourceType "Xilinx Accumulator Block" infoedit "Adder or subtracter-based accumulator. Output type and binary point position match the input.
Hardware notes: When \"Reinitialize with input 'b' on reset\" is selected, the accumulator is forced to ru" "n at the system rate even if the input 'b' is running at a slower rate." operation "Add" n_bits "28" overflow "Flag as error" scale "1" rst off infoeditControl "reset for floating point data type must be asserted for a minimum of 2 cycles" hasbypass off en on latency "0" dbl_ovrd off msb_inp "100" msb "100" lsb "-100" use_behavioral_HDL on implementation "Fabric" xl_use_area off xl_area "[12 23 0 22 0 0 0]" has_advanced_control "0" sggui_pos "20,20,367,457" block_type "accum" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,53,2,1,white,blue,0,debef366,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 53 53 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 53 53 0 ]);\npatch([9.425 19.54 26.54 33.54 40.54 26.54 16.425 9.425 ],[33.7" "7 33.77 40.77 33.77 40.77 40.77 40.77 33.77 ],[1 1 1 ]);\npatch([16.425 26.54 19.54 9.425 16.425 ],[26.77 26.77 " "33.77 33.77 26.77 ],[0.931 0.946 0.973 ]);\npatch([9.425 19.54 26.54 16.425 9.425 ],[19.77 19.77 26.77 26.77 19." "77 ],[1 1 1 ]);\npatch([16.425 40.54 33.54 26.54 19.54 9.425 16.425 ],[12.77 12.77 19.77 12.77 19.77 19.77 12.77" " ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nc" "olor('black');port_label('input',1,'b');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label(" "'output',1,'\\bf+=b','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "AddSub1" SID "7989" Ports [2, 1] Position [410, 117, 460, 168] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Subtraction" use_carryin off use_carryout off en off latency "1" precision "Full" arith_type "Signed (2's comp)" n_bits "36" bin_pt "28" quantization "Truncate" overflow "Saturate" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[9 18 0 17 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,344" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,51,2,1,white,blue,0,8a00a986,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 51 51 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 51 51 0 ]);\npatch([9.425 19.54 26.54 33.54 40.54 26.54 16.425 9.425 ],[32.7" "7 32.77 39.77 32.77 39.77 39.77 39.77 32.77 ],[1 1 1 ]);\npatch([16.425 26.54 19.54 9.425 16.425 ],[25.77 25.77 " "32.77 32.77 25.77 ],[0.931 0.946 0.973 ]);\npatch([9.425 19.54 26.54 16.425 9.425 ],[18.77 18.77 25.77 25.77 18." "77 ],[1 1 1 ]);\npatch([16.425 40.54 33.54 26.54 19.54 9.425 16.425 ],[11.77 11.77 18.77 11.77 18.77 18.77 11.77" " ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nc" "olor('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('" "output',1,'\\bf{a - b}','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black'" ");disp(' \\newline\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub2" SID "17477" Ports [2, 1] Position [410, 252, 460, 303] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Subtraction" use_carryin off use_carryout off en off latency "1" precision "Full" arith_type "Signed (2's comp)" n_bits "36" bin_pt "28" quantization "Truncate" overflow "Saturate" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[9 18 0 17 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,344" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,51,2,1,white,blue,0,8a00a986,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 51 51 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 51 51 0 ]);\npatch([9.425 19.54 26.54 33.54 40.54 26.54 16.425 9.425 ],[32.7" "7 32.77 39.77 32.77 39.77 39.77 39.77 32.77 ],[1 1 1 ]);\npatch([16.425 26.54 19.54 9.425 16.425 ],[25.77 25.77 " "32.77 32.77 25.77 ],[0.931 0.946 0.973 ]);\npatch([9.425 19.54 26.54 16.425 9.425 ],[18.77 18.77 25.77 25.77 18." "77 ],[1 1 1 ]);\npatch([16.425 40.54 33.54 26.54 19.54 9.425 16.425 ],[11.77 11.77 18.77 11.77 18.77 18.77 11.77" " ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nc" "olor('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('" "output',1,'\\bf{a - b}','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black'" ");disp(' \\newline\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay" SID "7990" Ports [1, 1] Position [425, 178, 450, 202] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[7 14 0 14 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 24 24 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 24 24 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[15.33 " "15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[12.33 12.33 15.33" " 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 1 " "1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');di" "sp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay1" SID "7991" Ports [1, 1] Position [530, 198, 555, 222] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[7 14 0 14 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 24 24 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 24 24 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[15.33 " "15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[12.33 12.33 15.33" " 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 1 " "1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');di" "sp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay4" SID "17482" Ports [2, 1] Position [330, 278, 365, 302] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en on latency "8" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[9 17 0 17 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,24,2,1,white,blue,0,76050afe,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[15" ".33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.33 12." "33 15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 12.33 " "9.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncol" "or('black');port_label('input',2,'en');\n\ncolor('black');disp('z^{-8}','texmode','on');\nfprintf('','COMMENT: e" "nd icon text');" } Block { BlockType Reference Name "Delay6" SID "7993" Ports [2, 1] Position [265, 143, 300, 167] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en on latency "32" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[9 17 0 17 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,24,2,1,white,blue,0,8441554b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[15" ".33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.33 12." "33 15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 12.33 " "9.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncol" "or('black');port_label('input',2,'en');\n\ncolor('black');disp('z^{-32}','texmode','on');\nfprintf('','COMMENT: " "end icon text');" } Block { BlockType Reference Name "Register" SID "7994" Ports [2, 1] Position [690, 152, 725, 188] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,36,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 36 36 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 36 36 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[23.55 23." "55 28.55 23.55 28.55 28.55 28.55 23.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[18.55 18.55 23.55 2" "3.55 18.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[13.55 13.55 18.55 18.55 13.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[8.55 8.55 13.55 8.55 13.55 13.55 8.55 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');por" "t_label('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\n" "color('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "17480" Ports [2, 1] Position [700, 287, 735, 323] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,36,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 36 36 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 36 36 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[23.55 23." "55 28.55 23.55 28.55 28.55 28.55 23.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[18.55 18.55 23.55 2" "3.55 18.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[13.55 13.55 18.55 18.55 13.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[8.55 8.55 13.55 8.55 13.55 13.55 8.55 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');por" "t_label('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\n" "color('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "17491" Ports [2, 1] Position [785, 162, 820, 198] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,36,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 36 36 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 36 36 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[23.55 23." "55 28.55 23.55 28.55 28.55 28.55 23.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[18.55 18.55 23.55 2" "3.55 18.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[13.55 13.55 18.55 18.55 13.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[8.55 8.55 13.55 8.55 13.55 13.55 8.55 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');por" "t_label('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\n" "color('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register3" SID "17492" Ports [2, 1] Position [780, 297, 815, 333] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,36,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 36 36 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 36 36 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[23.55 23." "55 28.55 23.55 28.55 28.55 28.55 23.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[18.55 18.55 23.55 2" "3.55 18.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[13.55 13.55 18.55 18.55 13.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[8.55 8.55 13.55 8.55 13.55 13.55 8.55 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');por" "t_label('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\n" "color('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Sum 32" SID "7995" Position [910, 173, 940, 187] IconDisplay "Port number" } Block { BlockType Outport Name "Sum 40" SID "17481" Position [910, 308, 940, 322] Port "2" IconDisplay "Port number" } Line { SrcBlock "Delay6" SrcPort 1 Points [10, 0] Branch { DstBlock "AddSub1" DstPort 2 } Branch { DstBlock "Delay4" DstPort 1 } } Line { SrcBlock "AddSub1" SrcPort 1 DstBlock "Accum1" DstPort 1 } Line { SrcBlock "D" SrcPort 1 Points [0, 0; 15, 0] Branch { Points [0, 20] DstBlock "Delay6" DstPort 1 } Branch { Points [80, 0] Branch { DstBlock "AddSub1" DstPort 1 } Branch { Points [0, 135] DstBlock "AddSub2" DstPort 1 } } } Line { SrcBlock "Accum1" SrcPort 1 DstBlock "Register" DstPort 1 } Line { SrcBlock "En" SrcPort 1 Points [10, 0] Branch { Points [0, -30] DstBlock "Delay6" DstPort 2 } Branch { DstBlock "Delay" DstPort 1 } Branch { Points [0, 105] DstBlock "Delay4" DstPort 2 } } Line { SrcBlock "Delay" SrcPort 1 Points [50, 0] Branch { DstBlock "Accum1" DstPort 2 } Branch { Points [0, 20] Branch { DstBlock "Delay1" DstPort 1 } Branch { DstBlock "Accum2" DstPort 2 } } } Line { SrcBlock "Delay1" SrcPort 1 Points [55, 0] Branch { Points [0, 105] Branch { DstBlock "Register1" DstPort 2 } Branch { Points [0, 10] DstBlock "Register3" DstPort 2 } } Branch { Points [0, -20] Branch { Points [0, -10] DstBlock "Register" DstPort 2 } Branch { DstBlock "Register2" DstPort 2 } } } Line { SrcBlock "AddSub2" SrcPort 1 DstBlock "Accum2" DstPort 1 } Line { SrcBlock "Accum2" SrcPort 1 DstBlock "Register1" DstPort 1 } Line { SrcBlock "Delay4" SrcPort 1 DstBlock "AddSub2" DstPort 2 } Line { SrcBlock "Register" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Sum 32" DstPort 1 } Line { SrcBlock "Register1" SrcPort 1 DstBlock "Register3" DstPort 1 } Line { SrcBlock "Register3" SrcPort 1 DstBlock "Sum 40" DstPort 1 } Annotation { Name "Extra delay here to align with correlation calc" Position [762, 241] } } } Block { BlockType Reference Name "done1" SID "15897" Ports [1, 1] Position [760, 420, 795, 430] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ADCQ" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "done2" SID "15898" Ports [1, 1] Position [760, 435, 795, 445] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "I^2" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "done3" SID "15900" Ports [1, 1] Position [760, 450, 795, 460] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Q^2" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "done4" SID "15896" Ports [1, 1] Position [760, 405, 795, 415] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ADCI" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "done5" SID "15901" Ports [1, 1] Position [760, 465, 795, 475] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Sum" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "done6" SID "15902" Ports [1, 1] Position [760, 480, 795, 490] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Mag 16" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "done7" SID "17484" Ports [1, 1] Position [760, 495, 795, 505] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Mag 20" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Outport Name "Mag 16" SID "7997" Position [670, 213, 700, 227] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Outport Name "Mag 20" SID "17483" Position [670, 238, 700, 252] Port "2" IconDisplay "Port number" } Line { SrcBlock "Delay" SrcPort 1 Points [65, 0; 0, 40] DstBlock "Running Sum" DstPort 1 } Line { SrcBlock "I" SrcPort 1 Points [80, 0] Branch { Points [30, 0] Branch { DstBlock "Mult" DstPort 1 } Branch { Points [0, 30] DstBlock "Mult" DstPort 2 } } Branch { Points [0, 180] DstBlock "done4" DstPort 1 } } Line { SrcBlock "Valid" SrcPort 1 DstBlock "Delay" DstPort 1 } Line { SrcBlock "Running Sum" SrcPort 1 Points [50, 0] Branch { Points [0, 265] DstBlock "done6" DstPort 1 } Branch { DstBlock "Mag 16" DstPort 1 } } Line { SrcBlock "Q" SrcPort 1 Points [75, 0] Branch { Points [35, 0] Branch { Points [0, 30] DstBlock "Mult1" DstPort 2 } Branch { DstBlock "Mult1" DstPort 1 } } Branch { Points [0, 125] DstBlock "done1" DstPort 1 } } Line { SrcBlock "Mult" SrcPort 1 Points [20, 0] Branch { DstBlock "AddSub" DstPort 1 } Branch { Points [0, 195] DstBlock "done2" DstPort 1 } } Line { SrcBlock "Mult1" SrcPort 1 Points [15, 0] Branch { Points [0, -40] DstBlock "AddSub" DstPort 2 } Branch { Points [0, 140] DstBlock "done3" DstPort 1 } } Line { SrcBlock "AddSub" SrcPort 1 Points [45, 0] Branch { Points [0, -15] DstBlock "Running Sum" DstPort 2 } Branch { Points [0, 210] DstBlock "done5" DstPort 1 } } Line { Name "ADCI" Labels [0, 0] SrcBlock "done4" SrcPort 1 DstBlock "Auto Corr Mag Calc" DstPort 1 } Line { Name "ADCQ" Labels [0, 0] SrcBlock "done1" SrcPort 1 DstBlock "Auto Corr Mag Calc" DstPort 2 } Line { Name "I^2" Labels [0, 0] SrcBlock "done2" SrcPort 1 DstBlock "Auto Corr Mag Calc" DstPort 3 } Line { Name "Q^2" Labels [0, 0] SrcBlock "done3" SrcPort 1 DstBlock "Auto Corr Mag Calc" DstPort 4 } Line { Name "Sum" Labels [0, 0] SrcBlock "done5" SrcPort 1 DstBlock "Auto Corr Mag Calc" DstPort 5 } Line { Name "Mag 16" Labels [0, 0] SrcBlock "done6" SrcPort 1 DstBlock "Auto Corr Mag Calc" DstPort 6 } Line { SrcBlock "Running Sum" SrcPort 2 Points [45, 0] Branch { DstBlock "Mag 20" DstPort 1 } Branch { Points [0, 255] DstBlock "done7" DstPort 1 } Branch { Points [0, -100] DstBlock "Goto" DstPort 1 } } Line { Name "Mag 20" Labels [0, 0] SrcBlock "done7" SrcPort 1 DstBlock "Auto Corr Mag Calc" DstPort 7 } } } Block { BlockType Reference Name "Register1" SID "7998" Ports [1, 1] Position [420, 228, 450, 252] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,24,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 24 24 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 24 24 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[15.3" "3 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[12.33 12.33 " "15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[9.33 9.33 12.33 12.33 9.33 " "],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('blac" "k');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmod" "e','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "7999" Ports [1, 1] Position [420, 203, 450, 227] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,24,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 24 24 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 24 24 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[15.3" "3 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[12.33 12.33 " "15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[9.33 9.33 12.33 12.33 9.33 " "],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('blac" "k');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmod" "e','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register3" SID "8000" Ports [1, 1] Position [420, 253, 450, 277] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,24,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 24 24 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 24 24 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[15.3" "3 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[12.33 12.33 " "15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[9.33 9.33 12.33 12.33 9.33 " "],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('blac" "k');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmod" "e','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "done1" SID "8001" Ports [1, 1] Position [1060, 530, 1095, 540] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Det Reset OFDM" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "done2" SID "8002" Ports [1, 1] Position [1060, 440, 1095, 450] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ADCQ" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "done3" SID "8003" Ports [1, 1] Position [1060, 455, 1095, 465] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Mag" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "done4" SID "8004" Ports [1, 1] Position [1060, 425, 1095, 435] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ADCI" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "done5" SID "8005" Ports [1, 1] Position [1060, 470, 1095, 480] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr OFDM" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "done6" SID "8006" Ports [1, 1] Position [1060, 500, 1095, 510] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Det OFDM" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "done7" SID "8007" Ports [1, 1] Position [1060, 485, 1095, 495] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr DSSS" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "done8" SID "8008" Ports [1, 1] Position [1060, 515, 1095, 525] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Det DSSS" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "done9" SID "8009" Ports [1, 1] Position [1060, 545, 1095, 555] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Det Reset DSSS" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Outport Name "Det OFDM" SID "8010" Position [1045, 142, 1075, 158] IconDisplay "Port number" } Block { BlockType Outport Name "Det DSSS" SID "8011" Position [1045, 282, 1075, 298] Port "2" IconDisplay "Port number" } Line { SrcBlock "Decision" SrcPort 1 Points [35, 0] Branch { Points [0, 355] DstBlock "done6" DstPort 1 } Branch { DstBlock "Det OFDM" DstPort 1 } } Line { SrcBlock "Mag" SrcPort 1 Points [50, 0] Branch { Points [0, -25] DstBlock "Decision" DstPort 6 } Branch { Points [0, 135] DstBlock "done3" DstPort 1 } } Line { SrcBlock "Auto Corr" SrcPort 1 Points [25, 0] Branch { DstBlock "Decision" DstPort 4 } Branch { Points [0, 255] DstBlock "done5" DstPort 1 } } Line { Labels [0, 0] SrcBlock "Register2" SrcPort 1 Points [155, 0] Branch { DstBlock "Auto Corr" DstPort 1 } Branch { Points [0, 100] DstBlock "Mag" DstPort 1 } Branch { Labels [2, 0] Points [0, -35] DstBlock "Decision" DstPort 3 } } Line { Labels [0, 0] SrcBlock "Register3" SrcPort 1 Points [135, 0] Branch { Points [0, 110] Branch { DstBlock "Mag" DstPort 3 } Branch { Points [0, 70] DstBlock "done2" DstPort 1 } } Branch { DstBlock "Auto Corr" DstPort 3 } } Line { Labels [0, 0] SrcBlock "Register1" SrcPort 1 Points [145, 0] Branch { DstBlock "Auto Corr" DstPort 2 } Branch { Points [0, 105] Branch { DstBlock "Mag" DstPort 2 } Branch { Points [0, 85] DstBlock "done4" DstPort 1 } } } Line { Labels [0, 1] SrcBlock "rx_valid" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "rx_I" SrcPort 1 DstBlock "Register1" DstPort 1 } Line { SrcBlock "rx_Q" SrcPort 1 DstBlock "Register3" DstPort 1 } Line { SrcBlock "Auto Corr" SrcPort 2 Points [15, 0] Branch { DstBlock "Decision" DstPort 5 } Branch { Points [0, 230] DstBlock "done7" DstPort 1 } } Line { Name "ADCI" Labels [0, 0] SrcBlock "done4" SrcPort 1 DstBlock "Auto Corr Pkt Det" DstPort 1 } Line { Name "ADCQ" Labels [0, 0] SrcBlock "done2" SrcPort 1 DstBlock "Auto Corr Pkt Det" DstPort 2 } Line { Name "Mag" Labels [0, 0] SrcBlock "done3" SrcPort 1 DstBlock "Auto Corr Pkt Det" DstPort 3 } Line { Name "Corr OFDM" Labels [0, 0] SrcBlock "done5" SrcPort 1 DstBlock "Auto Corr Pkt Det" DstPort 4 } Line { Name "Corr DSSS" Labels [0, 0] SrcBlock "done7" SrcPort 1 DstBlock "Auto Corr Pkt Det" DstPort 5 } Line { Name "Det OFDM" Labels [0, 0] SrcBlock "done6" SrcPort 1 DstBlock "Auto Corr Pkt Det" DstPort 6 } Line { Name "Det DSSS" Labels [0, 0] SrcBlock "done8" SrcPort 1 DstBlock "Auto Corr Pkt Det" DstPort 7 } Line { Name "Det Reset OFDM" Labels [0, 0] SrcBlock "done1" SrcPort 1 DstBlock "Auto Corr Pkt Det" DstPort 8 } Line { Name "Det Reset DSSS" Labels [0, 0] SrcBlock "done9" SrcPort 1 DstBlock "Auto Corr Pkt Det" DstPort 9 } Line { SrcBlock "Decision" SrcPort 2 Points [30, 0] Branch { Points [0, 230] DstBlock "done8" DstPort 1 } Branch { DstBlock "Det DSSS" DstPort 1 } } Line { SrcBlock "Reset OFDM" SrcPort 1 Points [255, 0] Branch { DstBlock "Decision" DstPort 1 } Branch { Points [0, 435] DstBlock "done1" DstPort 1 } } Line { SrcBlock "Reset DSSS" SrcPort 1 Points [245, 0] Branch { DstBlock "Decision" DstPort 2 } Branch { Points [0, 410] DstBlock "done9" DstPort 1 } } Line { SrcBlock "Mag" SrcPort 2 Points [85, 0] DstBlock "Decision" DstPort 7 } } } Block { BlockType From Name "From1" SID "8012" Position [510, 192, 725, 208] ShowName off CloseFcn "tagdialog Close" GotoTag "regRx_pktDet_requireBothA_OFDM" TagVisibility "global" } Block { BlockType From Name "From2" SID "15806" Position [510, 212, 725, 228] ShowName off CloseFcn "tagdialog Close" GotoTag "regRx_pktDet_requireBothA_DSSS" TagVisibility "global" } Block { BlockType Reference Name "Logical" SID "8013" Ports [2, 1] Position [775, 336, 810, 369] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,33,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 33 33 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 33 33 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[20.44 20.44 24.4" "4 20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[16.44 16.44 20.44 20.44 16.44 ]," "[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1 1 1 ]);\npatch([12.1" " 25.88 21.88 17.88 13.88 8.1 12.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('or');\nfprintf('" "','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "8014" Ports [2, 1] Position [775, 436, 810, 469] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,33,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 33 33 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 33 33 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[20.44 20.44 24.4" "4 20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[16.44 16.44 20.44 20.44 16.44 ]," "[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1 1 1 ]);\npatch([12.1" " 25.88 21.88 17.88 13.88 8.1 12.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('or');\nfprintf('" "','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "8015" Ports [2, 1] Position [775, 466, 810, 499] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,33,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 33 33 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 33 33 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[20.44 20.44 24.4" "4 20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[16.44 16.44 20.44 20.44 16.44 ]," "[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1 1 1 ]);\npatch([12.1" " 25.88 21.88 17.88 13.88 8.1 12.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('and');\nfprintf(" "'','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical3" SID "8016" Ports [2, 1] Position [775, 366, 810, 399] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,33,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 33 33 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 33 33 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[20.44 20.44 24.4" "4 20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[16.44 16.44 20.44 20.44 16.44 ]," "[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1 1 1 ]);\npatch([12.1" " 25.88 21.88 17.88 13.88 8.1 12.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('and');\nfprintf(" "'','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux" SID "8017" Ports [3, 1] Position [880, 312, 915, 398] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "35,86,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 12.2857 73.7143 86 0 ],[0." "77 0.82 0.91 ]);\nplot([0 35 35 0 0 ],[0 12.2857 73.7143 86 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5." "875 ],[48.55 48.55 53.55 48.55 53.55 53.55 53.55 48.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[43.55" " 43.55 48.55 48.55 43.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[38.55 38.55 43.55 43.55 " "38.55 ],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[33.55 33.55 38.55 33.55 38.55 38.55 33.55 ]," "[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor(" "'black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('inpu" "t',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux1" SID "8018" Ports [3, 1] Position [880, 412, 915, 498] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "35,86,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 12.2857 73.7143 86 0 ],[0." "77 0.82 0.91 ]);\nplot([0 35 35 0 0 ],[0 12.2857 73.7143 86 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5." "875 ],[48.55 48.55 53.55 48.55 53.55 53.55 53.55 48.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[43.55" " 43.55 48.55 48.55 43.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[38.55 38.55 43.55 43.55 " "38.55 ],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[33.55 33.55 38.55 33.55 38.55 38.55 33.55 ]," "[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor(" "'black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('inpu" "t',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "RSSI Pkt Det" SID "8019" Ports [3, 2] Position [535, 414, 665, 476] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "RSSI Pkt Det" Location [58, 156, 383, 269] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "143" Block { BlockType Inport Name "Reset OFDM" SID "8020" Position [360, 273, 390, 287] IconDisplay "Port number" } Block { BlockType Inport Name "Reset DSSS" SID "8021" Position [360, 378, 390, 392] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "Avg RSSI" SID "8022" Position [245, 248, 275, 262] NamePlacement "alternate" Port "3" IconDisplay "Port number" Port { PortNumber 1 PropagatedSignals "RFA_RSSI" ShowPropagatedSignals "on" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType SubSystem Name "Detection Decision" SID "8023" Ports [1, 1] Position [455, 235, 540, 275] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Detection Decision" Location [572, 342, 1525, 506] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "135" Block { BlockType Inport Name "Avg RSSI" SID "8024" Position [240, 223, 270, 237] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Reference Name "Concat" SID "8025" Ports [2, 1] Position [695, 268, 720, 317] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point " "at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "25,49,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 49 49 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 49 49 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[27.33 " "27.33 30.33 27.33 30.33 30.33 30.33 27.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[24.33 24.33 27.33" " 27.33 24.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[21.33 21.33 24.33 24.33 21.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[18.33 18.33 21.33 18.33 21.33 21.33 18.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('blac" "k');port_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fontsize{2" "0}\\}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant" SID "8026" Ports [0, 1] Position [625, 295, 645, 315] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "4" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "20,20,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 20 20 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 20 20 0 0 ],[0 0 20 20 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[12.22 12." "22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[10.22 10.22 12.22 12.22" " 10.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npa" "tch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfprin" "tf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output" "',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Counter1" SID "8027" Ports [2, 1] Position [695, 194, 730, 256] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited count" "er is implemented by combining a counter with a comparator." cnt_type "Count Limited" cnt_to "1023" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "10" bin_pt "0" load_pin off rst on en on explicit_period "off" period "4" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,619" block_type "counter" block_version "10.1.3" sg_icon_stat "35,62,2,1,white,blue,0,131a2a7a,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 62 62 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 62 62 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[36.55 36." "55 41.55 36.55 41.55 41.55 41.55 36.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[31.55 31.55 36.55 3" "6.55 31.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[26.55 26.55 31.55 31.55 26.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[21.55 21.55 26.55 21.55 26.55 26.55 21.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'rst');\ncolor('black');port_label('input',2,'en');\n\ncolor('black');disp('{\\fontsize{14" "}\\bf\\lceil++\\rceil}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From3" SID "8028" Position [95, 242, 310, 258] ShowName off CloseFcn "tagdialog Close" GotoTag "regRx_PKTDET_RSSI_THRESH_A" TagVisibility "global" } Block { BlockType From Name "From4" SID "8029" Position [230, 272, 450, 288] ShowName off CloseFcn "tagdialog Close" GotoTag "regRx_PKTDET_RSSI_MIN_DUR_A" TagVisibility "global" } Block { BlockType Reference Name "Inverter1" SID "8030" Ports [1, 1] Position [560, 203, 585, 217] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "8.2" sg_icon_stat "25,14,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfprintf" "('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register" SID "8031" Ports [1, 1] Position [575, 265, 605, 295] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 30 30 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 30 30 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 19.4" "4 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 19.44 " "15.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\np" "atch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('in" "put',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf" "('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational2" SID "8032" Ports [2, 1] Position [365, 218, 410, 262] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a>b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "500,165,356,193" block_type "relational" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,2,1,white,blue,0,b5131c97,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bfa > b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational3" SID "8033" Ports [2, 1] Position [795, 213, 840, 257] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a>b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "500,165,356,193" block_type "relational" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,2,1,white,blue,0,b5131c97,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bfa > b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Pkt Det" SID "8034" Position [920, 228, 950, 242] IconDisplay "Port number" } Line { SrcBlock "From3" SrcPort 1 DstBlock "Relational2" DstPort 2 } Line { SrcBlock "Counter1" SrcPort 1 DstBlock "Relational3" DstPort 1 } Line { SrcBlock "From4" SrcPort 1 DstBlock "Register" DstPort 1 } Line { SrcBlock "Relational3" SrcPort 1 DstBlock "Pkt Det" DstPort 1 } Line { SrcBlock "Avg RSSI" SrcPort 1 DstBlock "Relational2" DstPort 1 } Line { SrcBlock "Constant" SrcPort 1 DstBlock "Concat" DstPort 2 } Line { SrcBlock "Register" SrcPort 1 DstBlock "Concat" DstPort 1 } Line { SrcBlock "Concat" SrcPort 1 Points [55, 0] DstBlock "Relational3" DstPort 2 } Line { SrcBlock "Inverter1" SrcPort 1 DstBlock "Counter1" DstPort 1 } Line { SrcBlock "Relational2" SrcPort 1 Points [90, 0] Branch { Points [0, -30] DstBlock "Inverter1" DstPort 1 } Branch { DstBlock "Counter1" DstPort 2 } } Annotation { Position [1012, 242] } Annotation { Name "Require avg(RSSI) > thresh for a minimum number of\nsample periods. This coutner stops at its max val" "ue and\nis reset any time the avg(RSSI) falls below the threshold." Position [386, 361] } } } Block { BlockType From Name "From9" SID "10939" Position [220, 189, 435, 211] ShowName off CloseFcn "tagdialog Close" GotoTag "MAC_PHY_BLOCK_PKT_DET" TagVisibility "global" } Block { BlockType Reference Name "Inverter" SID "10940" Ports [1, 1] Position [480, 191, 505, 209] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical3" SID "10941" Ports [2, 1] Position [715, 223, 760, 267] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('" "black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Posedge1" SID "8035" Ports [1, 1] Position [590, 246, 635, 264] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Posedge1" Location [88, 301, 2330, 1301] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "8036" Position [200, 253, 230, 267] IconDisplay "Port number" } Block { BlockType Reference Name "Delay" SID "8037" Ports [1, 1] Position [425, 153, 460, 177] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. " "If register retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[15" ".33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.33 12." "33 15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 12.33 " "9.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\nc" "olor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "8038" Ports [1, 1] Position [490, 156, 515, 174] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "8039" Ports [2, 1] Position [540, 151, 585, 204] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,53,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 53 53 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 53 53 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[32.66 3" "2.66 38.66 32.66 38.66 38.66 38.66 32.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[26.66 26.66 32.66 " "32.66 26.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[20.66 20.66 26.66 26.66 20.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[14.66 14.66 20.66 14.66 20.66 20.66 14.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('" "black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "8040" Position [610, 173, 640, 187] IconDisplay "Port number" } Line { SrcBlock "Delay" SrcPort 1 DstBlock "Inverter" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "D" SrcPort 1 Points [150, 0; 0, -70] Branch { Points [0, -25] DstBlock "Delay" DstPort 1 } Branch { DstBlock "Logical1" DstPort 2 } } Annotation { Name "Rising Edge Detection" Position [500, 112] } } } Block { BlockType Reference Name "Register6" SID "11294" Ports [1, 1] Position [570, 184, 600, 216] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,32,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 32 32 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 32 32 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[20.44 20.4" "4 24.44 20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[16.44 16.44 20.44 20.44 " "16.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1 1 1 ]);\np" "atch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('in" "put',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf" "('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "S-R Latch1" SID "8041" Ports [2, 1] Position [805, 229, 835, 296] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "S-R Latch1" Location [160, 70, 1918, 1152] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "8042" Position [140, 103, 170, 117] IconDisplay "Port number" } Block { BlockType Inport Name "R" SID "8043" Position [140, 88, 170, 102] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "8044" Ports [0, 1] Position [195, 71, 210, 89] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "15,18,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11.22 " "13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 9.22 " "],[0.931 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([4.55 " "11.44 9.44 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "8045" Ports [3, 1] Position [255, 71, 300, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "8046" Position [325, 88, 355, 102] IconDisplay "Port number" } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "S" SrcPort 1 DstBlock "Register2" DstPort 3 } } } Block { BlockType SubSystem Name "S-R Latch2" SID "8047" Ports [2, 1] Position [805, 334, 835, 401] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "S-R Latch2" Location [160, 70, 1918, 1152] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "8048" Position [140, 103, 170, 117] IconDisplay "Port number" } Block { BlockType Inport Name "R" SID "8049" Position [140, 88, 170, 102] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "8050" Ports [0, 1] Position [195, 71, 210, 89] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "15,18,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11.22 " "13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 9.22 " "],[0.931 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([4.55 " "11.44 9.44 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "8051" Ports [3, 1] Position [255, 71, 300, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "8052" Position [325, 88, 355, 102] IconDisplay "Port number" } Line { SrcBlock "S" SrcPort 1 DstBlock "Register2" DstPort 3 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Register2" DstPort 1 } } } Block { BlockType Outport Name "PktDet OFDM" SID "8053" Position [900, 258, 930, 272] IconDisplay "Port number" } Block { BlockType Outport Name "PktDet DSSS" SID "8054" Position [900, 363, 930, 377] Port "2" IconDisplay "Port number" } Line { Labels [1, 0] SrcBlock "Avg RSSI" SrcPort 1 DstBlock "Detection Decision" DstPort 1 } Line { SrcBlock "Posedge1" SrcPort 1 DstBlock "Logical3" DstPort 2 } Line { SrcBlock "S-R Latch1" SrcPort 1 DstBlock "PktDet OFDM" DstPort 1 } Line { SrcBlock "Reset OFDM" SrcPort 1 DstBlock "S-R Latch1" DstPort 2 } Line { SrcBlock "Detection Decision" SrcPort 1 DstBlock "Posedge1" DstPort 1 } Line { SrcBlock "S-R Latch2" SrcPort 1 DstBlock "PktDet DSSS" DstPort 1 } Line { SrcBlock "Reset DSSS" SrcPort 1 DstBlock "S-R Latch2" DstPort 2 } Line { SrcBlock "From9" SrcPort 1 DstBlock "Inverter" DstPort 1 } Line { SrcBlock "Logical3" SrcPort 1 Points [10, 0] Branch { DstBlock "S-R Latch1" DstPort 1 } Branch { Points [0, 105] DstBlock "S-R Latch2" DstPort 1 } } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Register6" DstPort 1 } Line { SrcBlock "Register6" SrcPort 1 Points [50, 0; 0, 35] DstBlock "Logical3" DstPort 1 } Annotation { Name "The DSSS and OFDM pipelines operate independently. Both require\ntheir pktDet inputs to assert at the" " beginning of a reception\nand stay asserted until the pipeline is finished. But each pipeline\ncan reset the ot" "her (valid OFDM implies DSSS not valid), so\nthe pkt det state bits must be kept separate here." Position [479, 125] } } } Block { BlockType Outport Name "Det OFDM" SID "8055" Position [960, 348, 990, 362] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Outport Name "Det DSSS" SID "8056" Position [960, 448, 990, 462] Port "2" IconDisplay "Port number" } Line { SrcBlock "Logical" SrcPort 1 DstBlock "Mux" DstPort 2 } Line { SrcBlock "IQ Valid" SrcPort 1 DstBlock "Auto-Corr Pkt Det" DstPort 5 } Line { SrcBlock "Rx Q" SrcPort 1 DstBlock "Auto-Corr Pkt Det" DstPort 4 } Line { SrcBlock "Rx I" SrcPort 1 DstBlock "Auto-Corr Pkt Det" DstPort 3 } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Mux1" DstPort 2 } Line { SrcBlock "Reset OFDM" SrcPort 1 Points [65, 0; 0, 65] Branch { DstBlock "Auto-Corr Pkt Det" DstPort 1 } Branch { Points [0, 90] DstBlock "RSSI Pkt Det" DstPort 1 } } Line { SrcBlock "Reset DSSS" SrcPort 1 Points [55, 0; 0, 40] Branch { DstBlock "Auto-Corr Pkt Det" DstPort 2 } Branch { Points [0, 95] DstBlock "RSSI Pkt Det" DstPort 2 } } Line { SrcBlock "From1" SrcPort 1 Points [125, 0; 0, 125] DstBlock "Mux" DstPort 1 } Line { SrcBlock "Logical3" SrcPort 1 DstBlock "Mux" DstPort 3 } Line { SrcBlock "Mux" SrcPort 1 DstBlock "Det OFDM" DstPort 1 } Line { SrcBlock "RSSI" SrcPort 1 DstBlock "RSSI Pkt Det" DstPort 3 } Line { SrcBlock "Auto-Corr Pkt Det" SrcPort 2 Points [15, 0; 0, 55; 65, 0] Branch { DstBlock "Logical1" DstPort 1 } Branch { Points [0, 30] DstBlock "Logical2" DstPort 1 } } Line { SrcBlock "RSSI Pkt Det" SrcPort 2 Points [70, 0] Branch { DstBlock "Logical1" DstPort 2 } Branch { Points [0, 30] DstBlock "Logical2" DstPort 2 } } Line { SrcBlock "Auto-Corr Pkt Det" SrcPort 1 Points [80, 0] Branch { DstBlock "Logical" DstPort 1 } Branch { Points [0, 30] DstBlock "Logical3" DstPort 1 } } Line { SrcBlock "RSSI Pkt Det" SrcPort 1 Points [35, 0; 0, -70; 40, 0] Branch { DstBlock "Logical" DstPort 2 } Branch { Points [0, 30] DstBlock "Logical3" DstPort 2 } } Line { SrcBlock "Logical2" SrcPort 1 DstBlock "Mux1" DstPort 3 } Line { SrcBlock "Mux1" SrcPort 1 DstBlock "Det DSSS" DstPort 1 } Line { SrcBlock "From2" SrcPort 1 Points [110, 0; 0, 205] DstBlock "Mux1" DstPort 1 } } } Block { BlockType SubSystem Name "RF B Det" SID "17495" Ports [6, 2] Position [495, 531, 595, 624] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "RF B Det" Location [202, 70, 1833, 1180] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Reset OFDM" SID "17496" Position [340, 263, 370, 277] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "Reset DSSS" SID "17497" Position [340, 303, 370, 317] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "Rx I" SID "17498" Position [275, 358, 305, 372] NamePlacement "alternate" Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "Rx Q" SID "17499" Position [275, 373, 305, 387] Port "4" IconDisplay "Port number" } Block { BlockType Inport Name "IQ Valid" SID "17500" Position [340, 388, 370, 402] Port "5" IconDisplay "Port number" } Block { BlockType Inport Name "RSSI" SID "17501" Position [340, 458, 370, 472] Port "6" IconDisplay "Port number" } Block { BlockType SubSystem Name "Auto-Corr Pkt Det" SID "17502" Ports [5, 2] Position [535, 321, 665, 409] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Auto-Corr Pkt Det" Location [202, 70, 1833, 1180] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "121" Block { BlockType Inport Name "Reset OFDM" SID "17503" Position [490, 93, 520, 107] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "Reset DSSS" SID "17504" Position [490, 133, 520, 147] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "rx_I" SID "17505" Position [85, 233, 115, 247] NamePlacement "alternate" Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "rx_Q" SID "17506" Position [85, 258, 115, 272] Port "4" IconDisplay "Port number" } Block { BlockType Inport Name "rx_valid" SID "17507" Position [125, 208, 155, 222] NamePlacement "alternate" Port "5" IconDisplay "Port number" Port { PortNumber 1 ShowPropagatedSignals "on" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType SubSystem Name "Auto Corr" SID "17508" Ports [3, 2] Position [635, 199, 705, 281] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Auto Corr" Location [202, 70, 1833, 1180] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "156" Block { BlockType Inport Name "Valid" SID "17509" Position [225, 258, 255, 272] IconDisplay "Port number" } Block { BlockType Inport Name "I" SID "17510" Position [225, 323, 255, 337] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "Q" SID "17511" Position [225, 358, 255, 372] Port "3" IconDisplay "Port number" } Block { BlockType SubSystem Name "Avg Mag" SID "17512" Ports [2, 1] Position [680, 304, 720, 386] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Avg Mag" Location [202, 70, 1833, 1180] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "151" Block { BlockType Inport Name "Valid" SID "17513" Position [225, 298, 255, 312] IconDisplay "Port number" } Block { BlockType Inport Name "I" SID "17514" Position [230, 348, 260, 362] Port "2" IconDisplay "Port number" } Block { BlockType Scope Name "Auto Corr Calc" SID "17515" Ports [9] Position [760, 500, 805, 650] Floating off Location [1, 45, 1836, 1199] Open off NumInputPorts "9" ZoomMode "yonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" axes9 "%" } List { ListType ScopeGraphics FigureColor "[0.5 0.5 0.5]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "17540 " YMin "-0.04~-0.05~0.002~0~-1~-1~-1~-1~-1" YMax "0.05~0.05~0.01~0.007~1~1~1~1~1" SaveName "ScopeData56" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType Reference Name "Register" SID "17516" Ports [2, 1] Position [470, 338, 495, 362] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,24,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 24 24 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 24 24 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[15.33 " "15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[12.33 12.33 15.33" " 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 1 " "1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\nco" "lor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Running Sum" SID "17517" Ports [2, 2] Position [365, 338, 430, 362] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Running Sum" Location [202, 70, 1833, 1180] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "En" SID "17518" Position [195, 183, 225, 197] IconDisplay "Port number" } Block { BlockType Inport Name "D" SID "17519" Position [195, 123, 225, 137] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Accum1" SID "17520" Ports [2, 1] Position [485, 131, 535, 184] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Accumulator" SourceType "Xilinx Accumulator Block" infoedit "Adder or subtracter-based accumulator. Output type and binary point position match the input.
Hardware notes: When \"Reinitialize with input 'b' on reset\" is selected, the accumulator is forced to ru" "n at the system rate even if the input 'b' is running at a slower rate." operation "Add" n_bits "27" overflow "Flag as error" scale "1" rst off infoeditControl "reset for floating point data type must be asserted for a minimum of 2 cycles" hasbypass off en on latency "0" dbl_ovrd off msb_inp "100" msb "100" lsb "-100" use_behavioral_HDL on implementation "Fabric" xl_use_area off xl_area "[12 23 0 22 0 0 0]" has_advanced_control "0" sggui_pos "20,20,367,457" block_type "accum" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,53,2,1,white,blue,0,debef366,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 53 53 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 53 53 0 ]);\npatch([9.425 19.54 26.54 33.54 40.54 26.54 16.425 9.425 ],[33.7" "7 33.77 40.77 33.77 40.77 40.77 40.77 33.77 ],[1 1 1 ]);\npatch([16.425 26.54 19.54 9.425 16.425 ],[26.77 26.77 " "33.77 33.77 26.77 ],[0.931 0.946 0.973 ]);\npatch([9.425 19.54 26.54 16.425 9.425 ],[19.77 19.77 26.77 26.77 19." "77 ],[1 1 1 ]);\npatch([16.425 40.54 33.54 26.54 19.54 9.425 16.425 ],[12.77 12.77 19.77 12.77 19.77 19.77 12.77" " ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nc" "olor('black');port_label('input',1,'b');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label(" "'output',1,'\\bf+=b','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "AddSub1" SID "17521" Ports [2, 1] Position [360, 117, 410, 168] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Subtraction" use_carryin off use_carryout off en off latency "1" precision "Full" arith_type "Signed (2's comp)" n_bits "36" bin_pt "28" quantization "Truncate" overflow "Saturate" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[9 18 0 17 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,344" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,51,2,1,white,blue,0,8a00a986,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 51 51 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 51 51 0 ]);\npatch([9.425 19.54 26.54 33.54 40.54 26.54 16.425 9.425 ],[32.7" "7 32.77 39.77 32.77 39.77 39.77 39.77 32.77 ],[1 1 1 ]);\npatch([16.425 26.54 19.54 9.425 16.425 ],[25.77 25.77 " "32.77 32.77 25.77 ],[0.931 0.946 0.973 ]);\npatch([9.425 19.54 26.54 16.425 9.425 ],[18.77 18.77 25.77 25.77 18." "77 ],[1 1 1 ]);\npatch([16.425 40.54 33.54 26.54 19.54 9.425 16.425 ],[11.77 11.77 18.77 11.77 18.77 18.77 11.77" " ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nc" "olor('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('" "output',1,'\\bf{a - b}','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black'" ");disp(' \\newline\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay" SID "17522" Ports [1, 1] Position [375, 178, 400, 202] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[7 14 0 14 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 24 24 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 24 24 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[15.33 " "15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[12.33 12.33 15.33" " 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 1 " "1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');di" "sp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay1" SID "17523" Ports [1, 1] Position [495, 198, 520, 222] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[7 14 0 14 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 24 24 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 24 24 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[15.33 " "15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[12.33 12.33 15.33" " 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 1 " "1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');di" "sp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay2" SID "17524" Ports [1, 1] Position [605, 198, 630, 222] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[7 14 0 14 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 24 24 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 24 24 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[15.33 " "15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[12.33 12.33 15.33" " 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 1 " "1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');di" "sp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay6" SID "17525" Ports [2, 1] Position [265, 143, 300, 167] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en on latency "16" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[9 17 0 17 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,24,2,1,white,blue,0,68dbc054,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[15" ".33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.33 12." "33 15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 12.33 " "9.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncol" "or('black');port_label('input',2,'en');\n\ncolor('black');disp('z^{-16}','texmode','on');\nfprintf('','COMMENT: " "end icon text');" } Block { BlockType Reference Name "Register" SID "17526" Ports [1, 1] Position [600, 142, 635, 178] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,36,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 36 36 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 36 36 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[23.55 23." "55 28.55 23.55 28.55 28.55 28.55 23.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[18.55 18.55 23.55 2" "3.55 18.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[13.55 13.55 18.55 18.55 13.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[8.55 8.55 13.55 8.55 13.55 13.55 8.55 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');por" "t_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Sum" SID "17527" Position [710, 153, 740, 167] IconDisplay "Port number" } Block { BlockType Outport Name "Valid" SID "17528" Position [710, 203, 740, 217] Port "2" IconDisplay "Port number" } Line { SrcBlock "Delay2" SrcPort 1 DstBlock "Valid" DstPort 1 } Line { SrcBlock "Delay1" SrcPort 1 DstBlock "Delay2" DstPort 1 } Line { SrcBlock "Delay" SrcPort 1 Points [50, 0] Branch { Points [0, 20] DstBlock "Delay1" DstPort 1 } Branch { Points [0, -20] DstBlock "Accum1" DstPort 2 } } Line { SrcBlock "En" SrcPort 1 Points [10, 0] Branch { DstBlock "Delay" DstPort 1 } Branch { Points [0, -30] DstBlock "Delay6" DstPort 2 } } Line { SrcBlock "Register" SrcPort 1 DstBlock "Sum" DstPort 1 } Line { SrcBlock "Accum1" SrcPort 1 DstBlock "Register" DstPort 1 } Line { SrcBlock "D" SrcPort 1 Points [0, 0; 15, 0] Branch { Points [0, 20] DstBlock "Delay6" DstPort 1 } Branch { DstBlock "AddSub1" DstPort 1 } } Line { SrcBlock "AddSub1" SrcPort 1 DstBlock "Accum1" DstPort 1 } Line { SrcBlock "Delay6" SrcPort 1 DstBlock "AddSub1" DstPort 2 } } } Block { BlockType Reference Name "done1" SID "17529" Ports [1, 1] Position [550, 540, 585, 550] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Running Sum I" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "done4" SID "17530" Ports [1, 1] Position [550, 510, 585, 520] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Conj Mult I" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Outport Name "M" SID "17531" Position [565, 343, 595, 357] IconDisplay "Port number" } Line { SrcBlock "Register" SrcPort 1 DstBlock "M" DstPort 1 } Line { SrcBlock "Running Sum" SrcPort 2 DstBlock "Register" DstPort 2 } Line { Name "Running Sum I" Labels [0, 0] SrcBlock "done1" SrcPort 1 DstBlock "Auto Corr Calc" DstPort 3 } Line { Name "Conj Mult I" Labels [0, 0] SrcBlock "done4" SrcPort 1 DstBlock "Auto Corr Calc" DstPort 1 } Line { SrcBlock "Valid" SrcPort 1 Points [90, 0] DstBlock "Running Sum" DstPort 1 } Line { SrcBlock "I" SrcPort 1 Points [50, 0] Branch { Points [0, 160] DstBlock "done4" DstPort 1 } Branch { DstBlock "Running Sum" DstPort 2 } } Line { SrcBlock "Running Sum" SrcPort 1 Points [10, 0] Branch { Points [0, 200] DstBlock "done1" DstPort 1 } Branch { DstBlock "Register" DstPort 1 } } } } Block { BlockType SubSystem Name "Avg Mag1" SID "17532" Ports [2, 1] Position [680, 489, 720, 571] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Avg Mag1" Location [202, 70, 1833, 1180] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "151" Block { BlockType Inport Name "Valid" SID "17533" Position [225, 298, 255, 312] IconDisplay "Port number" } Block { BlockType Inport Name "I" SID "17534" Position [230, 348, 260, 362] Port "2" IconDisplay "Port number" } Block { BlockType Scope Name "Auto Corr Calc" SID "17535" Ports [9] Position [760, 500, 805, 650] Floating off Location [1, 45, 1836, 1199] Open off NumInputPorts "9" ZoomMode "yonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" axes9 "%" } List { ListType ScopeGraphics FigureColor "[0.5 0.5 0.5]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "17540 " YMin "-0.04~-0.05~0.002~0~-1~-1~-1~-1~-1" YMax "0.05~0.05~0.01~0.007~1~1~1~1~1" SaveName "ScopeData56" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType Reference Name "Register" SID "17536" Ports [2, 1] Position [470, 338, 495, 362] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,24,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 24 24 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 24 24 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[15.33 " "15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[12.33 12.33 15.33" " 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 1 " "1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\nco" "lor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Running Sum" SID "17537" Ports [2, 2] Position [365, 338, 430, 362] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Running Sum" Location [202, 70, 1833, 1180] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "En" SID "17538" Position [195, 183, 225, 197] IconDisplay "Port number" } Block { BlockType Inport Name "D" SID "17539" Position [195, 123, 225, 137] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Accum1" SID "17540" Ports [2, 1] Position [485, 131, 535, 184] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Accumulator" SourceType "Xilinx Accumulator Block" infoedit "Adder or subtracter-based accumulator. Output type and binary point position match the input.
Hardware notes: When \"Reinitialize with input 'b' on reset\" is selected, the accumulator is forced to ru" "n at the system rate even if the input 'b' is running at a slower rate." operation "Add" n_bits "27" overflow "Flag as error" scale "1" rst off infoeditControl "reset for floating point data type must be asserted for a minimum of 2 cycles" hasbypass off en on latency "0" dbl_ovrd off msb_inp "100" msb "100" lsb "-100" use_behavioral_HDL on implementation "Fabric" xl_use_area off xl_area "[12 23 0 22 0 0 0]" has_advanced_control "0" sggui_pos "20,20,367,457" block_type "accum" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,53,2,1,white,blue,0,debef366,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 53 53 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 53 53 0 ]);\npatch([9.425 19.54 26.54 33.54 40.54 26.54 16.425 9.425 ],[33.7" "7 33.77 40.77 33.77 40.77 40.77 40.77 33.77 ],[1 1 1 ]);\npatch([16.425 26.54 19.54 9.425 16.425 ],[26.77 26.77 " "33.77 33.77 26.77 ],[0.931 0.946 0.973 ]);\npatch([9.425 19.54 26.54 16.425 9.425 ],[19.77 19.77 26.77 26.77 19." "77 ],[1 1 1 ]);\npatch([16.425 40.54 33.54 26.54 19.54 9.425 16.425 ],[12.77 12.77 19.77 12.77 19.77 19.77 12.77" " ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nc" "olor('black');port_label('input',1,'b');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label(" "'output',1,'\\bf+=b','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "AddSub1" SID "17541" Ports [2, 1] Position [360, 117, 410, 168] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Subtraction" use_carryin off use_carryout off en off latency "1" precision "Full" arith_type "Signed (2's comp)" n_bits "36" bin_pt "28" quantization "Truncate" overflow "Saturate" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[9 18 0 17 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,344" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,51,2,1,white,blue,0,8a00a986,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 51 51 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 51 51 0 ]);\npatch([9.425 19.54 26.54 33.54 40.54 26.54 16.425 9.425 ],[32.7" "7 32.77 39.77 32.77 39.77 39.77 39.77 32.77 ],[1 1 1 ]);\npatch([16.425 26.54 19.54 9.425 16.425 ],[25.77 25.77 " "32.77 32.77 25.77 ],[0.931 0.946 0.973 ]);\npatch([9.425 19.54 26.54 16.425 9.425 ],[18.77 18.77 25.77 25.77 18." "77 ],[1 1 1 ]);\npatch([16.425 40.54 33.54 26.54 19.54 9.425 16.425 ],[11.77 11.77 18.77 11.77 18.77 18.77 11.77" " ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nc" "olor('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('" "output',1,'\\bf{a - b}','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black'" ");disp(' \\newline\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay" SID "17542" Ports [1, 1] Position [375, 178, 400, 202] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[7 14 0 14 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 24 24 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 24 24 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[15.33 " "15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[12.33 12.33 15.33" " 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 1 " "1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');di" "sp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay1" SID "17543" Ports [1, 1] Position [495, 198, 520, 222] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[7 14 0 14 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 24 24 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 24 24 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[15.33 " "15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[12.33 12.33 15.33" " 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 1 " "1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');di" "sp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay2" SID "17544" Ports [1, 1] Position [605, 198, 630, 222] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[7 14 0 14 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 24 24 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 24 24 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[15.33 " "15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[12.33 12.33 15.33" " 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 1 " "1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');di" "sp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay6" SID "17545" Ports [2, 1] Position [265, 143, 300, 167] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en on latency "20" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[9 17 0 17 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,24,2,1,white,blue,0,bbd9dacd,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[15" ".33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.33 12." "33 15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 12.33 " "9.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncol" "or('black');port_label('input',2,'en');\n\ncolor('black');disp('z^{-20}','texmode','on');\nfprintf('','COMMENT: " "end icon text');" } Block { BlockType Reference Name "Register" SID "17546" Ports [1, 1] Position [600, 142, 635, 178] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,36,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 36 36 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 36 36 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[23.55 23." "55 28.55 23.55 28.55 28.55 28.55 23.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[18.55 18.55 23.55 2" "3.55 18.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[13.55 13.55 18.55 18.55 13.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[8.55 8.55 13.55 8.55 13.55 13.55 8.55 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');por" "t_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Sum" SID "17547" Position [710, 153, 740, 167] IconDisplay "Port number" } Block { BlockType Outport Name "Valid" SID "17548" Position [710, 203, 740, 217] Port "2" IconDisplay "Port number" } Line { SrcBlock "Delay6" SrcPort 1 DstBlock "AddSub1" DstPort 2 } Line { SrcBlock "AddSub1" SrcPort 1 DstBlock "Accum1" DstPort 1 } Line { SrcBlock "D" SrcPort 1 Points [0, 0; 15, 0] Branch { DstBlock "AddSub1" DstPort 1 } Branch { Points [0, 20] DstBlock "Delay6" DstPort 1 } } Line { SrcBlock "Accum1" SrcPort 1 DstBlock "Register" DstPort 1 } Line { SrcBlock "Register" SrcPort 1 DstBlock "Sum" DstPort 1 } Line { SrcBlock "En" SrcPort 1 Points [10, 0] Branch { Points [0, -30] DstBlock "Delay6" DstPort 2 } Branch { DstBlock "Delay" DstPort 1 } } Line { SrcBlock "Delay" SrcPort 1 Points [50, 0] Branch { Points [0, -20] DstBlock "Accum1" DstPort 2 } Branch { Points [0, 20] DstBlock "Delay1" DstPort 1 } } Line { SrcBlock "Delay1" SrcPort 1 DstBlock "Delay2" DstPort 1 } Line { SrcBlock "Delay2" SrcPort 1 DstBlock "Valid" DstPort 1 } } } Block { BlockType Reference Name "done1" SID "17549" Ports [1, 1] Position [550, 540, 585, 550] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Running Sum I" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "done4" SID "17550" Ports [1, 1] Position [550, 510, 585, 520] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Conj Mult I" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Outport Name "M" SID "17551" Position [565, 343, 595, 357] IconDisplay "Port number" } Line { SrcBlock "Running Sum" SrcPort 1 Points [10, 0] Branch { DstBlock "Register" DstPort 1 } Branch { Points [0, 200] DstBlock "done1" DstPort 1 } } Line { SrcBlock "I" SrcPort 1 Points [50, 0] Branch { DstBlock "Running Sum" DstPort 2 } Branch { Points [0, 160] DstBlock "done4" DstPort 1 } } Line { SrcBlock "Valid" SrcPort 1 Points [90, 0] DstBlock "Running Sum" DstPort 1 } Line { Name "Conj Mult I" Labels [0, 0] SrcBlock "done4" SrcPort 1 DstBlock "Auto Corr Calc" DstPort 1 } Line { Name "Running Sum I" Labels [0, 0] SrcBlock "done1" SrcPort 1 DstBlock "Auto Corr Calc" DstPort 3 } Line { SrcBlock "Running Sum" SrcPort 2 DstBlock "Register" DstPort 2 } Line { SrcBlock "Register" SrcPort 1 DstBlock "M" DstPort 1 } } } Block { BlockType SubSystem Name "Conj Mult" SID "17552" Ports [5, 2] Position [540, 303, 605, 387] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Conj Mult" Location [202, 70, 1833, 1180] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Valid" SID "17553" Position [180, 293, 210, 307] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "A I" SID "17554" Position [180, 343, 210, 357] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "A Q" SID "17555" Position [180, 428, 210, 442] NamePlacement "alternate" Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "B I" SID "17556" Position [180, 373, 210, 387] NamePlacement "alternate" Port "4" IconDisplay "Port number" } Block { BlockType Inport Name "B Q" SID "17557" Position [180, 458, 210, 472] NamePlacement "alternate" Port "5" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub" SID "17558" Ports [2, 1] Position [490, 351, 520, 409] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "1" precision "User Defined" arith_type "Signed (2's comp)" n_bits "23" bin_pt "20" quantization "Truncate" overflow "Flag as error" dbl_ovrd off use_behavioral_HDL off hw_selection "Fabric" pipelined off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" sg_icon_stat "30,58,2,1,white,blue,0,e85d8a90,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 58 58 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 58 58 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[33.44 33.4" "4 37.44 33.44 37.44 37.44 37.44 33.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[29.44 29.44 33.44 33.44 " "29.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[25.44 25.44 29.44 29.44 25.44 ],[1 1 1 ]);\np" "atch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[21.44 21.44 25.44 21.44 25.44 25.44 21.44 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label" "('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bf{a + b}'," "'texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\newline\\bf{}" "','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay" SID "17559" Ports [1, 1] Position [430, 286, 465, 314] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "4" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,28,1,1,white,blue,0,d390c2d8,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 28 28 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[18.44 18.4" "4 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[14.44 14.44 18.44 18.44 " "14.44 ],[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\np" "atch([12.1 25.88 21.88 17.88 13.88 8.1 12.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-" "4}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mult" SID "17560" Ports [2, 1] Position [360, 334, 395, 396] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mult" SourceType "Xilinx Multiplier Block" infoedit "Hardware notes: To check for the optimum internal pipeline stages of the dedicated multiplier you" " must select 'Test for optimum pipelining'.

Optimization Goal: For implementation into device fabric (LUT" "s), the Speed or Area optimization will take effect only if it's supported by IP for the particular device famil" "y. Otherwise, the results will be identical regardless of the selection." precision "User Defined" arith_type "Signed (2's comp)" n_bits "22" bin_pt "20" quantization "Truncate" overflow "Flag as error" en off latency "3" dbl_ovrd off use_behavioral_HDL off opt "Speed" use_embedded on optimum_pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" pipeline "on" use_rpm "on" placement_style "Triangular" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mult" sg_icon_stat "35,62,2,1,white,blue,0,7028354c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 62 62 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 62 62 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[36.55 36." "55 41.55 36.55 41.55 41.55 41.55 36.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[31.55 31.55 36.55 3" "6.55 31.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[26.55 26.55 31.55 31.55 26.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[21.55 21.55 26.55 21.55 26.55 26.55 21.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bfa \\times b','texmode','on');\ncolor('black');disp('z^{-3}\\newline ','texmode','on');\ncolor('black');disp(' " "\\n ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mult1" SID "17561" Ports [2, 1] Position [360, 419, 395, 481] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mult" SourceType "Xilinx Multiplier Block" infoedit "Hardware notes: To check for the optimum internal pipeline stages of the dedicated multiplier you" " must select 'Test for optimum pipelining'.

Optimization Goal: For implementation into device fabric (LUT" "s), the Speed or Area optimization will take effect only if it's supported by IP for the particular device famil" "y. Otherwise, the results will be identical regardless of the selection." precision "User Defined" arith_type "Signed (2's comp)" n_bits "22" bin_pt "20" quantization "Truncate" overflow "Flag as error" en off latency "3" dbl_ovrd off use_behavioral_HDL off opt "Speed" use_embedded on optimum_pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" pipeline "on" use_rpm "on" placement_style "Triangular" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mult" sg_icon_stat "35,62,2,1,white,blue,0,7028354c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 62 62 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 62 62 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[36.55 36." "55 41.55 36.55 41.55 41.55 41.55 36.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[31.55 31.55 36.55 3" "6.55 31.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[26.55 26.55 31.55 31.55 26.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[21.55 21.55 26.55 21.55 26.55 26.55 21.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bfa \\times b','texmode','on');\ncolor('black');disp('z^{-3}\\newline ','texmode','on');\ncolor('black');disp(' " "\\n ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name " Valid" SID "17562" Position [815, 293, 845, 307] IconDisplay "Port number" } Block { BlockType Outport Name " I" SID "17563" Position [630, 373, 660, 387] Port "2" IconDisplay "Port number" } Line { SrcBlock "Delay" SrcPort 1 DstBlock " Valid" DstPort 1 } Line { SrcBlock "AddSub" SrcPort 1 DstBlock " I" DstPort 1 } Line { SrcBlock "Mult1" SrcPort 1 Points [15, 0; 0, -55] DstBlock "AddSub" DstPort 2 } Line { SrcBlock "Mult" SrcPort 1 DstBlock "AddSub" DstPort 1 } Line { SrcBlock "A Q" SrcPort 1 DstBlock "Mult1" DstPort 1 } Line { SrcBlock "B I" SrcPort 1 DstBlock "Mult" DstPort 2 } Line { SrcBlock "A I" SrcPort 1 DstBlock "Mult" DstPort 1 } Line { SrcBlock "Valid" SrcPort 1 DstBlock "Delay" DstPort 1 } Line { SrcBlock "B Q" SrcPort 1 DstBlock "Mult1" DstPort 2 } } } Block { BlockType SubSystem Name "Conj Mult1" SID "17564" Ports [5, 2] Position [540, 488, 605, 572] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Conj Mult1" Location [202, 70, 1833, 1180] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Valid" SID "17565" Position [180, 293, 210, 307] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "A I" SID "17566" Position [180, 343, 210, 357] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "A Q" SID "17567" Position [180, 428, 210, 442] NamePlacement "alternate" Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "B I" SID "17568" Position [180, 373, 210, 387] NamePlacement "alternate" Port "4" IconDisplay "Port number" } Block { BlockType Inport Name "B Q" SID "17569" Position [180, 458, 210, 472] NamePlacement "alternate" Port "5" IconDisplay "Port number" } Block { BlockType Reference Name "Absolute" SID "17570" Ports [1, 1] Position [595, 363, 625, 397] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Absolute" SourceType "Xilinx Absolute Block Block" precision "User Defined" arith_type "Unsigned" n_bits "23" bin_pt "20" quantization "Truncate" overflow "Flag as error" en off latency "1" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "abs" sg_icon_stat "30,34,1,1,white,blue,0,6c6606ff,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 34 34 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 34 34 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[21.44 21.4" "4 25.44 21.44 25.44 25.44 25.44 21.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[17.44 17.44 21.44 21.44 " "17.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[13.44 13.44 17.44 17.44 13.44 ],[1 1 1 ]);\np" "atch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[9.44 9.44 13.44 9.44 13.44 13.44 9.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('in" "put',1,'a');\ncolor('black');port_label('output',1,'|a|');\ncolor('black');disp('z^{-1}\\newline ','texmode','on" "');\ncolor('black');disp(' \\newline\\bf{|x|}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub" SID "17571" Ports [2, 1] Position [490, 351, 520, 409] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "1" precision "User Defined" arith_type "Signed (2's comp)" n_bits "23" bin_pt "20" quantization "Truncate" overflow "Flag as error" dbl_ovrd off use_behavioral_HDL off hw_selection "Fabric" pipelined off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" sg_icon_stat "30,58,2,1,white,blue,0,e85d8a90,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 58 58 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 58 58 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[33.44 33.4" "4 37.44 33.44 37.44 37.44 37.44 33.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[29.44 29.44 33.44 33.44 " "29.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[25.44 25.44 29.44 29.44 25.44 ],[1 1 1 ]);\np" "atch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[21.44 21.44 25.44 21.44 25.44 25.44 21.44 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label" "('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bf{a + b}'," "'texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\newline\\bf{}" "','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay" SID "17572" Ports [1, 1] Position [430, 286, 465, 314] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "5" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,28,1,1,white,blue,0,ec356abf,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 28 28 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[18.44 18.4" "4 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[14.44 14.44 18.44 18.44 " "14.44 ],[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\np" "atch([12.1 25.88 21.88 17.88 13.88 8.1 12.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-" "5}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mult" SID "17573" Ports [2, 1] Position [360, 334, 395, 396] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mult" SourceType "Xilinx Multiplier Block" infoedit "Hardware notes: To check for the optimum internal pipeline stages of the dedicated multiplier you" " must select 'Test for optimum pipelining'.

Optimization Goal: For implementation into device fabric (LUT" "s), the Speed or Area optimization will take effect only if it's supported by IP for the particular device famil" "y. Otherwise, the results will be identical regardless of the selection." precision "User Defined" arith_type "Signed (2's comp)" n_bits "22" bin_pt "20" quantization "Truncate" overflow "Flag as error" en off latency "3" dbl_ovrd off use_behavioral_HDL off opt "Speed" use_embedded on optimum_pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" pipeline "on" use_rpm "on" placement_style "Triangular" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mult" sg_icon_stat "35,62,2,1,white,blue,0,7028354c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 62 62 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 62 62 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[36.55 36." "55 41.55 36.55 41.55 41.55 41.55 36.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[31.55 31.55 36.55 3" "6.55 31.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[26.55 26.55 31.55 31.55 26.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[21.55 21.55 26.55 21.55 26.55 26.55 21.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bfa \\times b','texmode','on');\ncolor('black');disp('z^{-3}\\newline ','texmode','on');\ncolor('black');disp(' " "\\n ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mult1" SID "17574" Ports [2, 1] Position [360, 419, 395, 481] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mult" SourceType "Xilinx Multiplier Block" infoedit "Hardware notes: To check for the optimum internal pipeline stages of the dedicated multiplier you" " must select 'Test for optimum pipelining'.

Optimization Goal: For implementation into device fabric (LUT" "s), the Speed or Area optimization will take effect only if it's supported by IP for the particular device famil" "y. Otherwise, the results will be identical regardless of the selection." precision "User Defined" arith_type "Signed (2's comp)" n_bits "22" bin_pt "20" quantization "Truncate" overflow "Flag as error" en off latency "3" dbl_ovrd off use_behavioral_HDL off opt "Speed" use_embedded on optimum_pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" pipeline "on" use_rpm "on" placement_style "Triangular" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mult" sg_icon_stat "35,62,2,1,white,blue,0,7028354c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 62 62 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 62 62 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[36.55 36." "55 41.55 36.55 41.55 41.55 41.55 36.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[31.55 31.55 36.55 3" "6.55 31.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[26.55 26.55 31.55 31.55 26.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[21.55 21.55 26.55 21.55 26.55 26.55 21.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bfa \\times b','texmode','on');\ncolor('black');disp('z^{-3}\\newline ','texmode','on');\ncolor('black');disp(' " "\\n ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name " Valid" SID "17575" Position [815, 293, 845, 307] IconDisplay "Port number" } Block { BlockType Outport Name " I" SID "17576" Position [700, 373, 730, 387] Port "2" IconDisplay "Port number" } Line { SrcBlock "Absolute" SrcPort 1 DstBlock " I" DstPort 1 } Line { SrcBlock "B Q" SrcPort 1 DstBlock "Mult1" DstPort 2 } Line { SrcBlock "Valid" SrcPort 1 DstBlock "Delay" DstPort 1 } Line { SrcBlock "A I" SrcPort 1 DstBlock "Mult" DstPort 1 } Line { SrcBlock "B I" SrcPort 1 DstBlock "Mult" DstPort 2 } Line { SrcBlock "A Q" SrcPort 1 DstBlock "Mult1" DstPort 1 } Line { SrcBlock "Mult" SrcPort 1 DstBlock "AddSub" DstPort 1 } Line { SrcBlock "Mult1" SrcPort 1 Points [15, 0; 0, -55] DstBlock "AddSub" DstPort 2 } Line { SrcBlock "AddSub" SrcPort 1 DstBlock "Absolute" DstPort 1 } Line { SrcBlock "Delay" SrcPort 1 DstBlock " Valid" DstPort 1 } } } Block { BlockType Reference Name "Delay" SID "17577" Ports [2, 1] Position [310, 350, 345, 370] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en on latency "16" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[7 14 0 14 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,20,2,1,white,blue,0,68dbc054,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 20 20 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 20 20 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[12.22" " 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[10.22 10.22 12." "22 12.22 10.22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1" " 1 1 ]);\npatch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');" "port_label('input',2,'en');\n\ncolor('black');disp('z^{-16}','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" } Block { BlockType Reference Name "Delay1" SID "17578" Ports [2, 1] Position [310, 365, 345, 385] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en on latency "16" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[7 14 0 14 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,20,2,1,white,blue,0,68dbc054,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 20 20 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 20 20 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[12.22" " 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[10.22 10.22 12." "22 12.22 10.22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1" " 1 1 ]);\npatch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');" "port_label('input',2,'en');\n\ncolor('black');disp('z^{-16}','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" } Block { BlockType Reference Name "Delay2" SID "17579" Ports [2, 1] Position [390, 535, 425, 555] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en on latency "4" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[7 14 0 14 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,20,2,1,white,blue,0,bb519d05,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 20 20 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 20 20 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[12.22" " 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[10.22 10.22 12." "22 12.22 10.22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1" " 1 1 ]);\npatch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');" "port_label('input',2,'en');\n\ncolor('black');disp('z^{-4}','texmode','on');\nfprintf('','COMMENT: end icon text" "');" } Block { BlockType Reference Name "Delay3" SID "17580" Ports [2, 1] Position [390, 550, 425, 570] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en on latency "4" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[7 14 0 14 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,20,2,1,white,blue,0,bb519d05,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 20 20 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 20 20 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[12.22" " 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[10.22 10.22 12." "22 12.22 10.22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1" " 1 1 ]);\npatch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');" "port_label('input',2,'en');\n\ncolor('black');disp('z^{-4}','texmode','on');\nfprintf('','COMMENT: end icon text" "');" } Block { BlockType Reference Name "Register" SID "17581" Ports [1, 1] Position [455, 301, 485, 329] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,28,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 18.4" "4 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 18.44 " "14.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\np" "atch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('in" "put',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf" "('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "17582" Ports [1, 1] Position [455, 316, 485, 344] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,28,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 18.4" "4 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 18.44 " "14.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\np" "atch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('in" "put',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf" "('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "17583" Ports [1, 1] Position [455, 331, 485, 359] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,28,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 18.4" "4 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 18.44 " "14.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\np" "atch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('in" "put',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf" "('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register3" SID "17584" Ports [1, 1] Position [455, 346, 485, 374] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,28,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 18.4" "4 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 18.44 " "14.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\np" "atch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('in" "put',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf" "('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register4" SID "17585" Ports [1, 1] Position [455, 361, 485, 389] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,28,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 18.4" "4 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 18.44 " "14.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\np" "atch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('in" "put',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf" "('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register5" SID "17586" Ports [1, 1] Position [455, 486, 485, 514] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,28,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 18.4" "4 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 18.44 " "14.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\np" "atch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('in" "put',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf" "('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register6" SID "17587" Ports [1, 1] Position [455, 501, 485, 529] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,28,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 18.4" "4 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 18.44 " "14.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\np" "atch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('in" "put',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf" "('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register7" SID "17588" Ports [1, 1] Position [455, 516, 485, 544] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,28,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 18.4" "4 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 18.44 " "14.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\np" "atch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('in" "put',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf" "('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register8" SID "17589" Ports [1, 1] Position [455, 531, 485, 559] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,28,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 18.4" "4 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 18.44 " "14.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\np" "atch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('in" "put',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf" "('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register9" SID "17590" Ports [1, 1] Position [455, 546, 485, 574] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,28,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 18.4" "4 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 18.44 " "14.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\np" "atch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('in" "put',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf" "('','COMMENT: end icon text');" } Block { BlockType Outport Name "Corr_16" SID "17591" Position [780, 338, 810, 352] IconDisplay "Port number" } Block { BlockType Outport Name "Corr_20" SID "17592" Position [780, 523, 810, 537] Port "2" IconDisplay "Port number" } Line { SrcBlock "Conj Mult1" SrcPort 2 DstBlock "Avg Mag1" DstPort 2 } Line { SrcBlock "Conj Mult1" SrcPort 1 DstBlock "Avg Mag1" DstPort 1 } Line { SrcBlock "Delay3" SrcPort 1 DstBlock "Register9" DstPort 1 } Line { SrcBlock "Register9" SrcPort 1 DstBlock "Conj Mult1" DstPort 5 } Line { SrcBlock "Register8" SrcPort 1 DstBlock "Conj Mult1" DstPort 4 } Line { SrcBlock "Delay2" SrcPort 1 DstBlock "Register8" DstPort 1 } Line { SrcBlock "Register7" SrcPort 1 DstBlock "Conj Mult1" DstPort 3 } Line { SrcBlock "Register6" SrcPort 1 DstBlock "Conj Mult1" DstPort 2 } Line { SrcBlock "Register5" SrcPort 1 DstBlock "Conj Mult1" DstPort 1 } Line { SrcBlock "Avg Mag1" SrcPort 1 DstBlock "Corr_20" DstPort 1 } Line { SrcBlock "Register4" SrcPort 1 DstBlock "Conj Mult" DstPort 5 } Line { SrcBlock "Register3" SrcPort 1 DstBlock "Conj Mult" DstPort 4 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Conj Mult" DstPort 3 } Line { SrcBlock "Register1" SrcPort 1 DstBlock "Conj Mult" DstPort 2 } Line { SrcBlock "Register" SrcPort 1 DstBlock "Conj Mult" DstPort 1 } Line { SrcBlock "Avg Mag" SrcPort 1 DstBlock "Corr_16" DstPort 1 } Line { Labels [0, 0] SrcBlock "Conj Mult" SrcPort 1 DstBlock "Avg Mag" DstPort 1 } Line { SrcBlock "Conj Mult" SrcPort 2 DstBlock "Avg Mag" DstPort 2 } Line { SrcBlock "Valid" SrcPort 1 Points [25, 0] Branch { Points [130, 0; 0, 50] Branch { Points [0, 185] DstBlock "Register5" DstPort 1 } Branch { DstBlock "Register" DstPort 1 } } Branch { Points [0, 100] Branch { Points [0, 15] Branch { Points [0, 170] Branch { Points [0, 15] DstBlock "Delay3" DstPort 2 } Branch { DstBlock "Delay2" DstPort 2 } } Branch { DstBlock "Delay1" DstPort 2 } } Branch { DstBlock "Delay" DstPort 2 } } } Line { SrcBlock "Delay1" SrcPort 1 Points [10, 0] Branch { Points [0, 180] DstBlock "Delay3" DstPort 1 } Branch { DstBlock "Register4" DstPort 1 } } Line { SrcBlock "Delay" SrcPort 1 Points [15, 0] Branch { Points [0, 180] DstBlock "Delay2" DstPort 1 } Branch { DstBlock "Register3" DstPort 1 } } Line { SrcBlock "Q" SrcPort 1 Points [15, 0] Branch { Points [0, -20; 130, 0] Branch { Points [0, 185] DstBlock "Register7" DstPort 1 } Branch { DstBlock "Register2" DstPort 1 } } Branch { Points [0, 5] DstBlock "Delay1" DstPort 1 } } Line { SrcBlock "I" SrcPort 1 Points [35, 0] Branch { Points [115, 0] Branch { Points [0, 185] DstBlock "Register6" DstPort 1 } Branch { DstBlock "Register1" DstPort 1 } } Branch { DstBlock "Delay" DstPort 1 } } } } Block { BlockType Scope Name "Auto Corr Pkt Det" SID "17593" Ports [9] Position [1270, 415, 1315, 565] Floating off Location [1, 45, 1836, 1199] Open off NumInputPorts "9" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" axes9 "%" } List { ListType ScopeGraphics FigureColor "[0.5 0.5 0.5]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "17540" YMin "-0.75~-0.04~0~-0.5~0~-1~0.95~-1~-1" YMax "0.75~0.04~3~0.4~1.5~1~1.05~1~1" SaveName "ScopeData28" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType SubSystem Name "Decision" SID "17594" Ports [7, 2] Position [810, 80, 935, 360] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Decision" Location [202, 70, 1817, 1180] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Reset OFDM" SID "17595" Position [810, 403, 840, 417] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "Reset DSSS" SID "17596" Position [835, 613, 865, 627] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "iq_vld" SID "17597" Position [25, 768, 55, 782] NamePlacement "alternate" Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "Corr_16" SID "17598" Position [25, 333, 55, 347] NamePlacement "alternate" Port "4" IconDisplay "Port number" } Block { BlockType Inport Name "Corr_20" SID "17599" Position [25, 593, 55, 607] NamePlacement "alternate" Port "5" IconDisplay "Port number" } Block { BlockType Inport Name "Mag 16" SID "17600" Position [25, 403, 55, 417] Port "6" IconDisplay "Port number" } Block { BlockType Inport Name "Mag 20" SID "17601" Position [25, 533, 55, 547] Port "7" IconDisplay "Port number" } Block { BlockType Scope Name "Auto Corr Decision" SID "17602" Ports [10] Position [1520, 48, 1565, 197] Floating off Location [1, 45, 1836, 1199] Open off NumInputPorts "10" ZoomMode "yonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" axes9 "%" axes10 "%" } List { ListType ScopeGraphics FigureColor "[0.501960784313725 0.501960784313725 0.501960784313725]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[1 1 1 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "17540" YMin "-0.5~1.025~1.275~1.125~-1~1~-1~-1~1.09~-0.4" YMax "0.4~1.25~1.5~1.3~1~1~1~1~1.17~0.4" SaveName "ScopeData43" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType Reference Name "Delay" SID "17603" Ports [1, 1] Position [465, 338, 495, 362] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "30,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 24 24 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 24 24 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[15.3" "3 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[12.33 12.33 " "15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[9.33 9.33 12.33 12.33 9.33 " "],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('" "black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay1" SID "17604" Ports [1, 1] Position [465, 598, 495, 622] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "30,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 24 24 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 24 24 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[15.3" "3 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[12.33 12.33 " "15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[9.33 9.33 12.33 12.33 9.33 " "],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('" "black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay2" SID "17605" Ports [1, 1] Position [465, 538, 495, 562] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "30,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 24 24 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 24 24 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[15.3" "3 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[12.33 12.33 " "15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[9.33 9.33 12.33 12.33 9.33 " "],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('" "black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay3" SID "17606" Ports [1, 1] Position [465, 478, 495, 502] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "30,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 24 24 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 24 24 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[15.3" "3 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[12.33 12.33 " "15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[9.33 9.33 12.33 12.33 9.33 " "],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('" "black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Product Name "Divide" SID "17615" Ports [2, 1] Position [1275, 157, 1305, 188] ZOrder -8 Inputs "*/" InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" RndMeth "Floor" SaturateOnIntegerOverflow off Port { PortNumber 1 Name "DSSS Ratio" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Product Name "Divide1" SID "17616" Ports [2, 1] Position [1275, 222, 1305, 253] ZOrder -8 Inputs "*/" InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" RndMeth "Floor" SaturateOnIntegerOverflow off Port { PortNumber 1 Name "OFDM Ratio" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType From Name "From1" SID "17617" Position [195, 379, 365, 401] ShowName off CloseFcn "tagdialog Close" GotoTag "regRx_PktDet_CorrThresh_B" TagVisibility "global" } Block { BlockType From Name "From4" SID "17620" Position [195, 499, 365, 521] ShowName off CloseFcn "tagdialog Close" GotoTag "regRx_PktDet_EnergyThresh_B" TagVisibility "global" } Block { BlockType From Name "From5" SID "17621" Position [160, 664, 375, 686] ShowName off CloseFcn "tagdialog Close" GotoTag "regRx_PktDet_CorrThresh_DSSS_B" TagVisibility "global" } Block { BlockType From Name "From7" SID "17623" Position [150, 561, 365, 579] ShowName off CloseFcn "tagdialog Close" GotoTag "regRx_PktDet_EnergyThresh_DSSS_B" TagVisibility "global" } Block { BlockType From Name "From9" SID "17625" Position [700, 719, 915, 741] ShowName off CloseFcn "tagdialog Close" GotoTag "MAC_PHY_BLOCK_PKT_DET" TagVisibility "global" } Block { BlockType Reference Name "Inverter" SID "17626" Ports [1, 1] Position [960, 721, 985, 739] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical" SID "17627" Ports [2, 1] Position [710, 408, 755, 452] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('" "black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "17628" Ports [2, 1] Position [710, 618, 755, 662] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('" "black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "17629" Ports [2, 1] Position [1100, 418, 1145, 462] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('" "black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical3" SID "17630" Ports [2, 1] Position [1100, 628, 1145, 672] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('" "black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Min Dur" SID "17631" Ports [3, 1] Position [905, 400, 995, 460] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Min Dur" Location [202, 70, 1833, 1180] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Reset " SID "17632" Position [355, 143, 385, 157] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "Det " SID "17633" Position [355, 233, 385, 247] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "iq_vld" SID "17634" Position [330, 298, 360, 312] Port "3" IconDisplay "Port number" } Block { BlockType Reference Name "Counter1" SID "17635" Ports [2, 1] Position [695, 189, 725, 271] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited count" "er is implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "Inf" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "5" bin_pt "0" load_pin off rst on en on explicit_period "off" period "4" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,619" block_type "counter" block_version "10.1.3" sg_icon_stat "30,82,2,1,white,blue,0,ae3608d6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 82 82 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 82 82 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[45.44 45.4" "4 49.44 45.44 49.44 49.44 49.44 45.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[41.44 41.44 45.44 45.44 " "41.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[37.44 37.44 41.44 41.44 37.44 ],[1 1 1 ]);\np" "atch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[33.44 33.44 37.44 33.44 37.44 37.44 33.44 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label" "('input',1,'rst');\ncolor('black');port_label('input',2,'en');\n\ncolor('black');disp('{\\fontsize{14}\\bf++}','" "texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From4" SID "17638" Position [485, 271, 725, 289] ShowName off CloseFcn "tagdialog Close" GotoTag "regPktDet_pktDetMinDuration_autoCorr_B" TagVisibility "global" } Block { BlockType Reference Name "Inverter1" SID "17639" Ports [1, 1] Position [530, 208, 555, 222] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "8.2" sg_icon_stat "25,14,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfprintf" "('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter2" SID "17640" Ports [1, 1] Position [635, 328, 660, 342] BlockMirror on ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "8.2" sg_icon_stat "25,14,1,1,white,blue,0,267846e5,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfprintf" "('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "17641" Ports [2, 1] Position [615, 194, 645, 221] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,261" block_type "logical" block_version "10.1.3" sg_icon_stat "30,27,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 27 27 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 27 27 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[16.3" "3 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 13.33 " "16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13.33 10." "33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n" "color('black');disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "17642" Ports [3, 1] Position [590, 231, 620, 269] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,261" block_type "logical" block_version "10.1.3" sg_icon_stat "30,38,3,1,white,blue,0,98d76266,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 38 38 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 38 38 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[23.44 23.4" "4 27.44 23.44 27.44 27.44 27.44 23.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[19.44 19.44 23.44 23.44 " "19.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[15.44 15.44 19.44 19.44 15.44 ],[1 1 1 ]);\np" "atch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[11.44 11.44 15.44 11.44 15.44 15.44 11.44 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\ncolor('black');di" "sp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Scope Name "Pkt Det Ctrl Min Dur" SID "17643" Ports [7] Position [1270, 360, 1315, 470] Floating off Location [1, 45, 1833, 1199] Open off NumInputPorts "7" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" } List { ListType ScopeGraphics FigureColor "[0.5 0.5 0.5]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "10000" YMin "0~0~0~0~-1~-1~-1" YMax "1~1~1~1~1~1~1" SaveName "ScopeData6" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType SubSystem Name "Posedge1" SID "17644" Ports [1, 1] Position [870, 231, 915, 249] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Posedge1" Location [88, 301, 2330, 1301] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "17645" Position [200, 253, 230, 267] IconDisplay "Port number" } Block { BlockType Reference Name "Delay" SID "17646" Ports [1, 1] Position [425, 153, 460, 177] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. " "If register retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[15" ".33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.33 12." "33 15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 12.33 " "9.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\nc" "olor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "17647" Ports [1, 1] Position [490, 156, 515, 174] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "17648" Ports [2, 1] Position [540, 151, 585, 204] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,53,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 53 53 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 53 53 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[32.66 3" "2.66 38.66 32.66 38.66 38.66 38.66 32.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[26.66 26.66 32.66 " "32.66 26.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[20.66 20.66 26.66 26.66 20.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[14.66 14.66 20.66 14.66 20.66 20.66 14.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('" "black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "17649" Position [610, 173, 640, 187] IconDisplay "Port number" } Line { SrcBlock "D" SrcPort 1 Points [150, 0; 0, -70] Branch { DstBlock "Logical1" DstPort 2 } Branch { Points [0, -25] DstBlock "Delay" DstPort 1 } } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Delay" SrcPort 1 DstBlock "Inverter" DstPort 1 } Annotation { Name "Rising Edge Detection" Position [500, 112] } } } Block { BlockType Reference Name "Relational3" SID "17650" Ports [2, 1] Position [770, 218, 815, 262] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a>b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "500,165,356,193" block_type "relational" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,2,1,white,blue,0,b5131c97,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bfa > b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "done1" SID "17651" Ports [1, 1] Position [1125, 410, 1160, 420] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Det Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "done2" SID "17653" Ports [1, 1] Position [1125, 380, 1160, 390] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Min Dur Met" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "done3" SID "17654" Ports [1, 1] Position [1125, 425, 1160, 435] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Min dur counter" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "done5" SID "17655" Ports [1, 1] Position [1125, 395, 1160, 405] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Reset" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "done6" SID "17656" Ports [1, 1] Position [1125, 365, 1160, 375] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Det In" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Outport Name "Pkt Det " SID "17657" Position [1050, 233, 1080, 247] IconDisplay "Port number" } Line { SrcBlock "iq_vld" SrcPort 1 Points [40, 0; 0, -45] DstBlock "Logical2" DstPort 3 } Line { Name "Min dur counter" Labels [0, 0] SrcBlock "done3" SrcPort 1 DstBlock "Pkt Det Ctrl Min Dur" DstPort 5 } Line { SrcBlock "Det " SrcPort 1 Points [55, 0] Branch { Points [0, 0] Branch { Points [0, 130] DstBlock "done6" DstPort 1 } Branch { Points [0, -25] DstBlock "Inverter1" DstPort 1 } } Branch { DstBlock "Logical2" DstPort 1 } } Line { SrcBlock "Reset " SrcPort 1 Points [35, 0; 0, 50] Branch { Points [0, 200] DstBlock "done5" DstPort 1 } Branch { DstBlock "Logical1" DstPort 1 } } Line { Name "Det In" Labels [0, 0] SrcBlock "done6" SrcPort 1 DstBlock "Pkt Det Ctrl Min Dur" DstPort 1 } Line { SrcBlock "Posedge1" SrcPort 1 Points [85, 0] Branch { Points [0, 175] DstBlock "done1" DstPort 1 } Branch { DstBlock "Pkt Det " DstPort 1 } } Line { SrcBlock "Inverter2" SrcPort 1 Points [-160, 0; 0, -85] DstBlock "Logical2" DstPort 2 } Line { SrcBlock "Logical2" SrcPort 1 DstBlock "Counter1" DstPort 2 } Line { Name "Det Out" Labels [0, 0] SrcBlock "done1" SrcPort 1 DstBlock "Pkt Det Ctrl Min Dur" DstPort 4 } Line { Name "Reset" Labels [0, 0] SrcBlock "done5" SrcPort 1 DstBlock "Pkt Det Ctrl Min Dur" DstPort 3 } Line { Name "Min Dur Met" Labels [0, 0] SrcBlock "done2" SrcPort 1 DstBlock "Pkt Det Ctrl Min Dur" DstPort 2 } Line { SrcBlock "Relational3" SrcPort 1 Points [20, 0] Branch { Points [0, 95] Branch { Points [0, 50] DstBlock "done2" DstPort 1 } Branch { DstBlock "Inverter2" DstPort 1 } } Branch { DstBlock "Posedge1" DstPort 1 } } Line { SrcBlock "From4" SrcPort 1 Points [25, 0] DstBlock "Relational3" DstPort 2 } Line { SrcBlock "Counter1" SrcPort 1 Points [5, 0] Branch { Points [0, 200] DstBlock "done3" DstPort 1 } Branch { DstBlock "Relational3" DstPort 1 } } Line { SrcBlock "Inverter1" SrcPort 1 DstBlock "Logical1" DstPort 2 } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Counter1" DstPort 1 } Annotation { Position [1152, 227] } } } Block { BlockType SubSystem Name "Min Dur1" SID "17658" Ports [3, 1] Position [905, 610, 995, 670] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Min Dur1" Location [202, 70, 1833, 1180] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Reset " SID "17659" Position [355, 143, 385, 157] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "Det " SID "17660" Position [355, 233, 385, 247] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "iq_vld" SID "17661" Position [330, 298, 360, 312] Port "3" IconDisplay "Port number" } Block { BlockType Reference Name "Counter1" SID "17662" Ports [2, 1] Position [695, 189, 725, 271] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited count" "er is implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "Inf" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "5" bin_pt "0" load_pin off rst on en on explicit_period "off" period "4" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,619" block_type "counter" block_version "10.1.3" sg_icon_stat "30,82,2,1,white,blue,0,ae3608d6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 82 82 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 82 82 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[45.44 45.4" "4 49.44 45.44 49.44 49.44 49.44 45.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[41.44 41.44 45.44 45.44 " "41.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[37.44 37.44 41.44 41.44 37.44 ],[1 1 1 ]);\np" "atch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[33.44 33.44 37.44 33.44 37.44 37.44 33.44 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label" "('input',1,'rst');\ncolor('black');port_label('input',2,'en');\n\ncolor('black');disp('{\\fontsize{14}\\bf++}','" "texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From4" SID "17665" Position [485, 271, 725, 289] ShowName off CloseFcn "tagdialog Close" GotoTag "regPktDet_pktDetMinDuration_autoCorr_B" TagVisibility "global" } Block { BlockType Reference Name "Inverter1" SID "17666" Ports [1, 1] Position [530, 208, 555, 222] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "8.2" sg_icon_stat "25,14,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfprintf" "('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter2" SID "17667" Ports [1, 1] Position [635, 328, 660, 342] BlockMirror on ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "8.2" sg_icon_stat "25,14,1,1,white,blue,0,267846e5,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfprintf" "('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "17668" Ports [2, 1] Position [615, 194, 645, 221] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,261" block_type "logical" block_version "10.1.3" sg_icon_stat "30,27,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 27 27 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 27 27 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[16.3" "3 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 13.33 " "16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13.33 10." "33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n" "color('black');disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "17669" Ports [3, 1] Position [590, 231, 620, 269] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,261" block_type "logical" block_version "10.1.3" sg_icon_stat "30,38,3,1,white,blue,0,98d76266,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 38 38 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 38 38 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[23.44 23.4" "4 27.44 23.44 27.44 27.44 27.44 23.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[19.44 19.44 23.44 23.44 " "19.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[15.44 15.44 19.44 19.44 15.44 ],[1 1 1 ]);\np" "atch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[11.44 11.44 15.44 11.44 15.44 15.44 11.44 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\ncolor('black');di" "sp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Scope Name "Pkt Det Ctrl Min Dur" SID "17670" Ports [7] Position [1270, 360, 1315, 470] Floating off Location [-18, 112, 1814, 1266] Open off NumInputPorts "7" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" } List { ListType ScopeGraphics FigureColor "[0.5 0.5 0.5]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "10000" YMin "0~0~0~0~-1~-1~-1" YMax "1~1~1~1~1~1~1" SaveName "ScopeData6" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType SubSystem Name "Posedge1" SID "17671" Ports [1, 1] Position [870, 231, 915, 249] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Posedge1" Location [88, 301, 2330, 1301] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "17672" Position [200, 253, 230, 267] IconDisplay "Port number" } Block { BlockType Reference Name "Delay" SID "17673" Ports [1, 1] Position [425, 153, 460, 177] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. " "If register retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[15" ".33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.33 12." "33 15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 12.33 " "9.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\nc" "olor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "17674" Ports [1, 1] Position [490, 156, 515, 174] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "17675" Ports [2, 1] Position [540, 151, 585, 204] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,53,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 53 53 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 53 53 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[32.66 3" "2.66 38.66 32.66 38.66 38.66 38.66 32.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[26.66 26.66 32.66 " "32.66 26.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[20.66 20.66 26.66 26.66 20.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[14.66 14.66 20.66 14.66 20.66 20.66 14.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('" "black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "17676" Position [610, 173, 640, 187] IconDisplay "Port number" } Line { SrcBlock "Delay" SrcPort 1 DstBlock "Inverter" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "D" SrcPort 1 Points [150, 0; 0, -70] Branch { Points [0, -25] DstBlock "Delay" DstPort 1 } Branch { DstBlock "Logical1" DstPort 2 } } Annotation { Name "Rising Edge Detection" Position [500, 112] } } } Block { BlockType Reference Name "Relational3" SID "17677" Ports [2, 1] Position [770, 218, 815, 262] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a>b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "500,165,356,193" block_type "relational" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,2,1,white,blue,0,b5131c97,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bfa > b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "done1" SID "17678" Ports [1, 1] Position [1125, 410, 1160, 420] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Det Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "done2" SID "17680" Ports [1, 1] Position [1125, 380, 1160, 390] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Min Dur Met" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "done3" SID "17681" Ports [1, 1] Position [1125, 425, 1160, 435] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Min dur counter" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "done5" SID "17682" Ports [1, 1] Position [1125, 395, 1160, 405] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Reset" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "done6" SID "17683" Ports [1, 1] Position [1125, 365, 1160, 375] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Det In" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Outport Name "Pkt Det " SID "17684" Position [1050, 233, 1080, 247] IconDisplay "Port number" } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Counter1" DstPort 1 } Line { SrcBlock "Inverter1" SrcPort 1 DstBlock "Logical1" DstPort 2 } Line { SrcBlock "Counter1" SrcPort 1 Points [5, 0] Branch { DstBlock "Relational3" DstPort 1 } Branch { Points [0, 200] DstBlock "done3" DstPort 1 } } Line { SrcBlock "From4" SrcPort 1 Points [25, 0] DstBlock "Relational3" DstPort 2 } Line { SrcBlock "Relational3" SrcPort 1 Points [20, 0] Branch { DstBlock "Posedge1" DstPort 1 } Branch { Points [0, 95] Branch { DstBlock "Inverter2" DstPort 1 } Branch { Points [0, 50] DstBlock "done2" DstPort 1 } } } Line { Name "Min Dur Met" Labels [0, 0] SrcBlock "done2" SrcPort 1 DstBlock "Pkt Det Ctrl Min Dur" DstPort 2 } Line { Name "Reset" Labels [0, 0] SrcBlock "done5" SrcPort 1 DstBlock "Pkt Det Ctrl Min Dur" DstPort 3 } Line { Name "Det Out" Labels [0, 0] SrcBlock "done1" SrcPort 1 DstBlock "Pkt Det Ctrl Min Dur" DstPort 4 } Line { SrcBlock "Logical2" SrcPort 1 DstBlock "Counter1" DstPort 2 } Line { SrcBlock "Inverter2" SrcPort 1 Points [-160, 0; 0, -85] DstBlock "Logical2" DstPort 2 } Line { SrcBlock "Posedge1" SrcPort 1 Points [85, 0] Branch { DstBlock "Pkt Det " DstPort 1 } Branch { Points [0, 175] DstBlock "done1" DstPort 1 } } Line { Name "Det In" Labels [0, 0] SrcBlock "done6" SrcPort 1 DstBlock "Pkt Det Ctrl Min Dur" DstPort 1 } Line { SrcBlock "Reset " SrcPort 1 Points [35, 0; 0, 50] Branch { DstBlock "Logical1" DstPort 1 } Branch { Points [0, 200] DstBlock "done5" DstPort 1 } } Line { SrcBlock "Det " SrcPort 1 Points [55, 0] Branch { DstBlock "Logical2" DstPort 1 } Branch { Points [0, 0] Branch { Points [0, -25] DstBlock "Inverter1" DstPort 1 } Branch { Points [0, 130] DstBlock "done6" DstPort 1 } } } Line { Name "Min dur counter" Labels [0, 0] SrcBlock "done3" SrcPort 1 DstBlock "Pkt Det Ctrl Min Dur" DstPort 5 } Line { SrcBlock "iq_vld" SrcPort 1 Points [40, 0; 0, -45] DstBlock "Logical2" DstPort 3 } Annotation { Position [1152, 227] } } } Block { BlockType Reference Name "Mult1" SID "17685" Ports [2, 1] Position [455, 377, 505, 433] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mult" SourceType "Xilinx Multiplier Block" infoedit "Hardware notes: To check for the optimum internal pipeline stages of the dedicated multiplier you" " must select 'Test for optimum pipelining'.

Optimization Goal: For implementation into device fabric (LUT" "s), the Speed or Area optimization will take effect only if it's supported by IP for the particular device famil" "y. Otherwise, the results will be identical regardless of the selection." precision "User Defined" arith_type "Unsigned" n_bits "28" bin_pt "20" quantization "Truncate" overflow "Flag as error" en off latency "1" dbl_ovrd off use_behavioral_HDL off opt "Speed" use_embedded on optimum_pipeline off xl_use_area off xl_area "[63 105 0 106 0 4 0]" pipeline "on" use_rpm "off" placement_style "Rectangular shape" has_advanced_control "0" sggui_pos "1126,548,356,577" block_type "mult" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,56,2,1,white,blue,0,82c891c1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 56 56 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 56 56 0 ]);\npatch([9.425 19.54 26.54 33.54 40.54 26.54 16.425 9.425 ],[35.7" "7 35.77 42.77 35.77 42.77 42.77 42.77 35.77 ],[1 1 1 ]);\npatch([16.425 26.54 19.54 9.425 16.425 ],[28.77 28.77 " "35.77 35.77 28.77 ],[0.931 0.946 0.973 ]);\npatch([9.425 19.54 26.54 16.425 9.425 ],[21.77 21.77 28.77 28.77 21." "77 ],[1 1 1 ]);\npatch([16.425 40.54 33.54 26.54 19.54 9.425 16.425 ],[14.77 14.77 21.77 14.77 21.77 21.77 14.77" " ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nc" "olor('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('" "output',1,'\\bfa \\times b','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('bl" "ack');disp(' \\n ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mult2" SID "17686" Ports [2, 1] Position [455, 632, 505, 688] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mult" SourceType "Xilinx Multiplier Block" infoedit "Hardware notes: To check for the optimum internal pipeline stages of the dedicated multiplier you" " must select 'Test for optimum pipelining'.

Optimization Goal: For implementation into device fabric (LUT" "s), the Speed or Area optimization will take effect only if it's supported by IP for the particular device famil" "y. Otherwise, the results will be identical regardless of the selection." precision "User Defined" arith_type "Unsigned" n_bits "27" bin_pt "20" quantization "Truncate" overflow "Flag as error" en off latency "1" dbl_ovrd off use_behavioral_HDL off opt "Speed" use_embedded on optimum_pipeline off xl_use_area off xl_area "[63 105 0 106 0 4 0]" pipeline "on" use_rpm "off" placement_style "Rectangular shape" has_advanced_control "0" sggui_pos "675,561,356,577" block_type "mult" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,56,2,1,white,blue,0,82c891c1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 56 56 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 56 56 0 ]);\npatch([9.425 19.54 26.54 33.54 40.54 26.54 16.425 9.425 ],[35.7" "7 35.77 42.77 35.77 42.77 42.77 42.77 35.77 ],[1 1 1 ]);\npatch([16.425 26.54 19.54 9.425 16.425 ],[28.77 28.77 " "35.77 35.77 28.77 ],[0.931 0.946 0.973 ]);\npatch([9.425 19.54 26.54 16.425 9.425 ],[21.77 21.77 28.77 28.77 21." "77 ],[1 1 1 ]);\npatch([16.425 40.54 33.54 26.54 19.54 9.425 16.425 ],[14.77 14.77 21.77 14.77 21.77 21.77 14.77" " ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nc" "olor('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('" "output',1,'\\bfa \\times b','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('bl" "ack');disp(' \\n ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "17687" Ports [2, 1] Position [140, 404, 165, 431] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,27,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 27 27 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 27 27 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 " "16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33" " 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q'" ");\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "17688" Ports [2, 1] Position [150, 594, 175, 621] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,27,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 27 27 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 27 27 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 " "16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33" " 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q'" ");\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register3" SID "17689" Ports [2, 1] Position [140, 334, 165, 361] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,27,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 27 27 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 27 27 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 " "16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33" " 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q'" ");\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register4" SID "17690" Ports [2, 1] Position [150, 534, 175, 561] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,27,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 27 27 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 27 27 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 " "16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33" " 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q'" ");\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register6" SID "17691" Ports [1, 1] Position [1005, 714, 1035, 746] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,32,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 32 32 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 32 32 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[20.44 20.4" "4 24.44 20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[16.44 16.44 20.44 20.44 " "16.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1 1 1 ]);\np" "atch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('in" "put',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf" "('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational" SID "17696" Ports [2, 1] Position [565, 338, 610, 382] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a>b" en off latency "1" dbl_ovrd off xl_use_area off xl_area "[11 1 0 22 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,2,1,white,blue,0,3049caaa,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bfa > b','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\n ')" ";\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational1" SID "17697" Ports [2, 1] Position [565, 478, 610, 522] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a>b" en off latency "1" dbl_ovrd off xl_use_area off xl_area "[11 1 0 22 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "relational" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,2,1,white,blue,0,3049caaa,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bfa > b','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\n ')" ";\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational2" SID "17698" Ports [2, 1] Position [565, 628, 610, 672] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a>b" en off latency "1" dbl_ovrd off xl_use_area off xl_area "[11 1 0 22 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,2,1,white,blue,0,3049caaa,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bfa > b','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\n ')" ";\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational3" SID "17699" Ports [2, 1] Position [565, 538, 610, 582] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a>b" en off latency "1" dbl_ovrd off xl_use_area off xl_area "[11 1 0 22 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "relational" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,2,1,white,blue,0,3049caaa,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bfa > b','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\n ')" ";\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "S-R Latch" SID "17700" Ports [2, 1] Position [1230, 366, 1260, 464] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "S-R Latch" Location [160, 70, 1918, 1152] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "R" SID "17701" Position [140, 88, 170, 102] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "S" SID "17702" Position [140, 103, 170, 117] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "17703" Ports [0, 1] Position [195, 71, 210, 89] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "15,18,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11.22 " "13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 9.22 " "],[0.931 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([4.55 " "11.44 9.44 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "17704" Ports [3, 1] Position [255, 71, 300, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "17705" Position [325, 88, 355, 102] IconDisplay "Port number" } Line { SrcBlock "S" SrcPort 1 DstBlock "Register2" DstPort 3 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Register2" DstPort 1 } } } Block { BlockType SubSystem Name "S-R Latch1" SID "17706" Ports [2, 1] Position [1230, 577, 1265, 673] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "S-R Latch1" Location [160, 70, 1918, 1152] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "R" SID "17707" Position [140, 88, 170, 102] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "S" SID "17708" Position [140, 103, 170, 117] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "17709" Ports [0, 1] Position [195, 71, 210, 89] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "15,18,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11.22 " "13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 9.22 " "],[0.931 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([4.55 " "11.44 9.44 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "17710" Ports [3, 1] Position [255, 71, 300, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "17711" Position [325, 88, 355, 102] IconDisplay "Port number" } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "S" SrcPort 1 DstBlock "Register2" DstPort 3 } } } Block { BlockType Reference Name "done12" SID "17715" Ports [1, 1] Position [1350, 155, 1385, 165] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Det DSSS" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "done13" SID "17716" Ports [1, 1] Position [1195, 240, 1230, 250] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "done16" SID "17719" Ports [1, 1] Position [1195, 160, 1230, 170] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "done19" SID "17722" Ports [1, 1] Position [1195, 225, 1230, 235] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "done20" SID "17724" Ports [1, 1] Position [1195, 175, 1230, 185] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "done3" SID "17725" Ports [1, 1] Position [1350, 65, 1385, 75] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Scaled Mag 16" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "done4" SID "17726" Ports [1, 1] Position [1350, 50, 1385, 60] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr 16" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "done5" SID "17727" Ports [1, 1] Position [1350, 80, 1385, 90] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr 20" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "done6" SID "17728" Ports [1, 1] Position [1350, 95, 1385, 105] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Scaled Mag 20" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "done7" SID "17729" Ports [1, 1] Position [1350, 110, 1385, 120] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Det 16" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "done8" SID "17730" Ports [1, 1] Position [1350, 125, 1385, 135] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Det 20" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "done9" SID "17731" Ports [1, 1] Position [1350, 140, 1385, 150] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Det OFDM" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Outport Name "Det OFDM" SID "17732" Position [1330, 407, 1360, 423] IconDisplay "Port number" } Block { BlockType Outport Name "Det DSSS" SID "17733" Position [1330, 617, 1360, 633] Port "2" IconDisplay "Port number" } Line { SrcBlock "Delay3" SrcPort 1 DstBlock "Relational1" DstPort 1 } Line { SrcBlock "Delay2" SrcPort 1 DstBlock "Relational3" DstPort 1 } Line { SrcBlock "Delay1" SrcPort 1 Points [25, 0] Branch { Points [0, -525; 635, 0] Branch { Points [0, 80] DstBlock "done16" DstPort 1 } Branch { DstBlock "done5" DstPort 1 } } Branch { Points [0, 30] DstBlock "Relational2" DstPort 1 } } Line { SrcBlock "Delay" SrcPort 1 Points [15, 0] Branch { Points [0, -295; 620, 0] Branch { Points [0, 175] DstBlock "done19" DstPort 1 } Branch { DstBlock "done4" DstPort 1 } } Branch { DstBlock "Relational" DstPort 1 } } Line { SrcBlock "done20" SrcPort 1 DstBlock "Divide" DstPort 2 } Line { SrcBlock "Register4" SrcPort 1 Points [240, 0] Branch { DstBlock "Delay2" DstPort 1 } Branch { Points [0, 95] DstBlock "Mult2" DstPort 1 } } Line { SrcBlock "Mag 20" SrcPort 1 DstBlock "Register4" DstPort 1 } Line { SrcBlock "done19" SrcPort 1 DstBlock "Divide1" DstPort 1 } Line { Name "DSSS Ratio" Labels [1, 1] SrcBlock "Divide" SrcPort 1 DstBlock "Auto Corr Decision" DstPort 9 } Line { SrcBlock "done13" SrcPort 1 DstBlock "Divide1" DstPort 2 } Line { SrcBlock "done16" SrcPort 1 DstBlock "Divide" DstPort 1 } Line { Name "OFDM Ratio" Labels [3, 1] SrcBlock "Divide1" SrcPort 1 Points [30, 0; 0, -50] DstBlock "Auto Corr Decision" DstPort 10 } Line { SrcBlock "iq_vld" SrcPort 1 Points [50, 0] Branch { Points [0, -160] Branch { Points [0, -60] Branch { Points [0, -130] Branch { DstBlock "Register1" DstPort 2 } Branch { Points [0, -70] DstBlock "Register3" DstPort 2 } } Branch { DstBlock "Register4" DstPort 2 } } Branch { DstBlock "Register2" DstPort 2 } } Branch { Points [575, 0; 0, -245; 125, 0] Branch { Points [0, 130] DstBlock "Min Dur1" DstPort 3 } Branch { Points [0, -80] DstBlock "Min Dur" DstPort 3 } } } Line { SrcBlock "Register6" SrcPort 1 Points [15, 0; 0, -70] Branch { DstBlock "Logical3" DstPort 2 } Branch { Points [0, -210] DstBlock "Logical2" DstPort 2 } } Line { SrcBlock "Logical3" SrcPort 1 DstBlock "S-R Latch1" DstPort 2 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Register6" DstPort 1 } Line { SrcBlock "From9" SrcPort 1 DstBlock "Inverter" DstPort 1 } Line { SrcBlock "Logical2" SrcPort 1 DstBlock "S-R Latch" DstPort 2 } Line { SrcBlock "S-R Latch" SrcPort 1 DstBlock "Det OFDM" DstPort 1 } Line { SrcBlock "S-R Latch1" SrcPort 1 DstBlock "Det DSSS" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Delay1" DstPort 1 } Line { SrcBlock "Register1" SrcPort 1 Points [260, 0] Branch { Points [0, 70] DstBlock "Delay3" DstPort 1 } Branch { DstBlock "Mult1" DstPort 2 } } Line { SrcBlock "Register3" SrcPort 1 DstBlock "Delay" DstPort 1 } Line { SrcBlock "Min Dur1" SrcPort 1 Points [15, 0] Branch { DstBlock "Logical3" DstPort 1 } Branch { Points [0, -480] DstBlock "done12" DstPort 1 } } Line { SrcBlock "Min Dur" SrcPort 1 Points [10, 0] Branch { DstBlock "Logical2" DstPort 1 } Branch { Points [0, -285] DstBlock "done9" DstPort 1 } } Line { SrcBlock "Reset DSSS" SrcPort 1 Points [15, 0] Branch { DstBlock "Min Dur1" DstPort 1 } Branch { Points [0, -20] DstBlock "S-R Latch1" DstPort 1 } } Line { SrcBlock "Reset OFDM" SrcPort 1 Points [30, 0] Branch { Points [0, -20] DstBlock "S-R Latch" DstPort 1 } Branch { DstBlock "Min Dur" DstPort 1 } } Line { Name "Det DSSS" Labels [0, 0] SrcBlock "done12" SrcPort 1 DstBlock "Auto Corr Decision" DstPort 8 } Line { Points [1005, 1195; 20, 0] } Line { Points [1070, 1195; 20, 0] } Line { SrcBlock "Relational3" SrcPort 1 Points [25, 0; 0, 70] DstBlock "Logical1" DstPort 1 } Line { SrcBlock "From7" SrcPort 1 DstBlock "Relational3" DstPort 2 } Line { Name "Det OFDM" Labels [0, 0] SrcBlock "done9" SrcPort 1 DstBlock "Auto Corr Decision" DstPort 7 } Line { Name "Det 20" Labels [0, 0] SrcBlock "done8" SrcPort 1 DstBlock "Auto Corr Decision" DstPort 6 } Line { Name "Det 16" Labels [0, 0] SrcBlock "done7" SrcPort 1 DstBlock "Auto Corr Decision" DstPort 5 } Line { Name "Scaled Mag 20" Labels [0, 0] SrcBlock "done6" SrcPort 1 DstBlock "Auto Corr Decision" DstPort 4 } Line { Name "Corr 20" Labels [0, 0] SrcBlock "done5" SrcPort 1 DstBlock "Auto Corr Decision" DstPort 3 } Line { Name "Scaled Mag 16" Labels [0, 0] SrcBlock "done3" SrcPort 1 DstBlock "Auto Corr Decision" DstPort 2 } Line { Name "Corr 16" Labels [0, 0] SrcBlock "done4" SrcPort 1 DstBlock "Auto Corr Decision" DstPort 1 } Line { SrcBlock "Corr_20" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "Mult2" SrcPort 1 Points [30, 0] Branch { Points [0, -560; 615, 0] Branch { Points [0, 80] DstBlock "done20" DstPort 1 } Branch { DstBlock "done6" DstPort 1 } } Branch { DstBlock "Relational2" DstPort 2 } } Line { SrcBlock "From5" SrcPort 1 DstBlock "Mult2" DstPort 2 } Line { SrcBlock "Logical1" SrcPort 1 Points [25, 0] Branch { DstBlock "Min Dur1" DstPort 2 } Branch { Points [0, -510] DstBlock "done8" DstPort 1 } } Line { SrcBlock "Logical" SrcPort 1 Points [10, 0] Branch { DstBlock "Min Dur" DstPort 2 } Branch { Points [0, -315] DstBlock "done7" DstPort 1 } } Line { SrcBlock "Relational2" SrcPort 1 DstBlock "Logical1" DstPort 2 } Line { SrcBlock "Relational1" SrcPort 1 Points [50, 0; 0, -60] DstBlock "Logical" DstPort 2 } Line { SrcBlock "Relational" SrcPort 1 Points [50, 0; 0, 60] DstBlock "Logical" DstPort 1 } Line { SrcBlock "From4" SrcPort 1 DstBlock "Relational1" DstPort 2 } Line { SrcBlock "Mult1" SrcPort 1 Points [20, 0; 0, -35] Branch { Points [0, -300; 600, 0] Branch { Points [0, 175] DstBlock "done13" DstPort 1 } Branch { DstBlock "done3" DstPort 1 } } Branch { DstBlock "Relational" DstPort 2 } } Line { SrcBlock "From1" SrcPort 1 DstBlock "Mult1" DstPort 1 } Line { SrcBlock "Mag 16" SrcPort 1 DstBlock "Register1" DstPort 1 } Line { SrcBlock "Corr_16" SrcPort 1 DstBlock "Register3" DstPort 1 } Line { Points [450, 1195; 20, 0] } Line { Points [515, 1195; 20, 0] } } } Block { BlockType SubSystem Name "Mag" SID "17734" Ports [3, 2] Position [635, 298, 705, 392] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Mag" Location [202, 70, 1833, 1180] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "155" Block { BlockType Inport Name "Valid" SID "17735" Position [85, 173, 115, 187] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "I" SID "17736" Position [85, 223, 115, 237] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "Q" SID "17737" Position [85, 293, 115, 307] Port "3" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub" SID "17738" Ports [2, 1] Position [350, 231, 380, 289] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Signed (2's comp)" n_bits "23" bin_pt "20" quantization "Truncate" overflow "Flag as error" dbl_ovrd off use_behavioral_HDL off hw_selection "Fabric" pipelined off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" sg_icon_stat "30,58,2,1,white,blue,0,e139daf6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 58 58 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 58 58 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[33.44 33.4" "4 37.44 33.44 37.44 37.44 37.44 33.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[29.44 29.44 33.44 33.44 " "29.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[25.44 25.44 29.44 29.44 25.44 ],[1 1 1 ]);\np" "atch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[21.44 21.44 25.44 21.44 25.44 25.44 21.44 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label" "('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bf{a + b}'," "'texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Scope Name "Auto Corr Mag Calc" SID "17739" Ports [9] Position [865, 395, 910, 545] Floating off Location [1, 45, 1836, 1199] Open off NumInputPorts "9" ZoomMode "yonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" axes9 "%" } List { ListType ScopeGraphics FigureColor "[0.5 0.5 0.5]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "40000" YMin "-0.4~-1~0~0~0~-1~0.95~0.95~-1" YMax "0.4~1~0.45~0.04~0.6~1~1.05~1.05~1" SaveName "ScopeData41" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType Reference Name "Delay" SID "17740" Ports [1, 1] Position [265, 166, 300, 194] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "3" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,28,1,1,white,blue,0,83e6bb61,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 28 28 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[18.44 18.4" "4 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[14.44 14.44 18.44 18.44 " "14.44 ],[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\np" "atch([12.1 25.88 21.88 17.88 13.88 8.1 12.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-" "3}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mult" SID "17741" Ports [2, 1] Position [265, 214, 300, 276] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mult" SourceType "Xilinx Multiplier Block" infoedit "Hardware notes: To check for the optimum internal pipeline stages of the dedicated multiplier you" " must select 'Test for optimum pipelining'.

Optimization Goal: For implementation into device fabric (LUT" "s), the Speed or Area optimization will take effect only if it's supported by IP for the particular device famil" "y. Otherwise, the results will be identical regardless of the selection." precision "User Defined" arith_type "Signed (2's comp)" n_bits "22" bin_pt "20" quantization "Truncate" overflow "Flag as error" en off latency "3" dbl_ovrd off use_behavioral_HDL off opt "Speed" use_embedded on optimum_pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" pipeline "on" use_rpm "on" placement_style "Triangular" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mult" sg_icon_stat "35,62,2,1,white,blue,0,7028354c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 62 62 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 62 62 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[36.55 36." "55 41.55 36.55 41.55 41.55 41.55 36.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[31.55 31.55 36.55 3" "6.55 31.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[26.55 26.55 31.55 31.55 26.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[21.55 21.55 26.55 21.55 26.55 26.55 21.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bfa \\times b','texmode','on');\ncolor('black');disp('z^{-3}\\newline ','texmode','on');\ncolor('black');disp(' " "\\n ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mult1" SID "17742" Ports [2, 1] Position [265, 284, 300, 346] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mult" SourceType "Xilinx Multiplier Block" infoedit "Hardware notes: To check for the optimum internal pipeline stages of the dedicated multiplier you" " must select 'Test for optimum pipelining'.

Optimization Goal: For implementation into device fabric (LUT" "s), the Speed or Area optimization will take effect only if it's supported by IP for the particular device famil" "y. Otherwise, the results will be identical regardless of the selection." precision "User Defined" arith_type "Signed (2's comp)" n_bits "22" bin_pt "20" quantization "Truncate" overflow "Flag as error" en off latency "3" dbl_ovrd off use_behavioral_HDL off opt "Speed" use_embedded on optimum_pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" pipeline "on" use_rpm "on" placement_style "Triangular" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mult" sg_icon_stat "35,62,2,1,white,blue,0,7028354c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 62 62 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 62 62 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[36.55 36." "55 41.55 36.55 41.55 41.55 41.55 36.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[31.55 31.55 36.55 3" "6.55 31.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[26.55 26.55 31.55 31.55 26.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[21.55 21.55 26.55 21.55 26.55 26.55 21.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bfa \\times b','texmode','on');\ncolor('black');disp('z^{-3}\\newline ','texmode','on');\ncolor('black');disp(' " "\\n ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Running Sum" SID "17743" Ports [2, 2] Position [465, 207, 530, 258] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Running Sum" Location [202, 70, 1833, 1180] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "En" SID "17744" Position [195, 183, 225, 197] IconDisplay "Port number" } Block { BlockType Inport Name "D" SID "17745" Position [195, 123, 225, 137] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Accum1" SID "17746" Ports [2, 1] Position [520, 131, 570, 184] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Accumulator" SourceType "Xilinx Accumulator Block" infoedit "Adder or subtracter-based accumulator. Output type and binary point position match the input.
Hardware notes: When \"Reinitialize with input 'b' on reset\" is selected, the accumulator is forced to ru" "n at the system rate even if the input 'b' is running at a slower rate." operation "Add" n_bits "28" overflow "Flag as error" scale "1" rst off infoeditControl "reset for floating point data type must be asserted for a minimum of 2 cycles" hasbypass off en on latency "0" dbl_ovrd off msb_inp "100" msb "100" lsb "-100" use_behavioral_HDL on implementation "Fabric" xl_use_area off xl_area "[12 23 0 22 0 0 0]" has_advanced_control "0" sggui_pos "20,20,367,457" block_type "accum" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,53,2,1,white,blue,0,debef366,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 53 53 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 53 53 0 ]);\npatch([9.425 19.54 26.54 33.54 40.54 26.54 16.425 9.425 ],[33.7" "7 33.77 40.77 33.77 40.77 40.77 40.77 33.77 ],[1 1 1 ]);\npatch([16.425 26.54 19.54 9.425 16.425 ],[26.77 26.77 " "33.77 33.77 26.77 ],[0.931 0.946 0.973 ]);\npatch([9.425 19.54 26.54 16.425 9.425 ],[19.77 19.77 26.77 26.77 19." "77 ],[1 1 1 ]);\npatch([16.425 40.54 33.54 26.54 19.54 9.425 16.425 ],[12.77 12.77 19.77 12.77 19.77 19.77 12.77" " ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nc" "olor('black');port_label('input',1,'b');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label(" "'output',1,'\\bf+=b','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Accum2" SID "17747" Ports [2, 1] Position [520, 266, 570, 319] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Accumulator" SourceType "Xilinx Accumulator Block" infoedit "Adder or subtracter-based accumulator. Output type and binary point position match the input.
Hardware notes: When \"Reinitialize with input 'b' on reset\" is selected, the accumulator is forced to ru" "n at the system rate even if the input 'b' is running at a slower rate." operation "Add" n_bits "28" overflow "Flag as error" scale "1" rst off infoeditControl "reset for floating point data type must be asserted for a minimum of 2 cycles" hasbypass off en on latency "0" dbl_ovrd off msb_inp "100" msb "100" lsb "-100" use_behavioral_HDL on implementation "Fabric" xl_use_area off xl_area "[12 23 0 22 0 0 0]" has_advanced_control "0" sggui_pos "20,20,367,457" block_type "accum" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,53,2,1,white,blue,0,debef366,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 53 53 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 53 53 0 ]);\npatch([9.425 19.54 26.54 33.54 40.54 26.54 16.425 9.425 ],[33.7" "7 33.77 40.77 33.77 40.77 40.77 40.77 33.77 ],[1 1 1 ]);\npatch([16.425 26.54 19.54 9.425 16.425 ],[26.77 26.77 " "33.77 33.77 26.77 ],[0.931 0.946 0.973 ]);\npatch([9.425 19.54 26.54 16.425 9.425 ],[19.77 19.77 26.77 26.77 19." "77 ],[1 1 1 ]);\npatch([16.425 40.54 33.54 26.54 19.54 9.425 16.425 ],[12.77 12.77 19.77 12.77 19.77 19.77 12.77" " ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nc" "olor('black');port_label('input',1,'b');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label(" "'output',1,'\\bf+=b','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "AddSub1" SID "17748" Ports [2, 1] Position [410, 117, 460, 168] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Subtraction" use_carryin off use_carryout off en off latency "1" precision "Full" arith_type "Signed (2's comp)" n_bits "36" bin_pt "28" quantization "Truncate" overflow "Saturate" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[9 18 0 17 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,344" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,51,2,1,white,blue,0,8a00a986,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 51 51 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 51 51 0 ]);\npatch([9.425 19.54 26.54 33.54 40.54 26.54 16.425 9.425 ],[32.7" "7 32.77 39.77 32.77 39.77 39.77 39.77 32.77 ],[1 1 1 ]);\npatch([16.425 26.54 19.54 9.425 16.425 ],[25.77 25.77 " "32.77 32.77 25.77 ],[0.931 0.946 0.973 ]);\npatch([9.425 19.54 26.54 16.425 9.425 ],[18.77 18.77 25.77 25.77 18." "77 ],[1 1 1 ]);\npatch([16.425 40.54 33.54 26.54 19.54 9.425 16.425 ],[11.77 11.77 18.77 11.77 18.77 18.77 11.77" " ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nc" "olor('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('" "output',1,'\\bf{a - b}','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black'" ");disp(' \\newline\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub2" SID "17749" Ports [2, 1] Position [410, 252, 460, 303] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Subtraction" use_carryin off use_carryout off en off latency "1" precision "Full" arith_type "Signed (2's comp)" n_bits "36" bin_pt "28" quantization "Truncate" overflow "Saturate" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[9 18 0 17 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,344" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,51,2,1,white,blue,0,8a00a986,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 51 51 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 51 51 0 ]);\npatch([9.425 19.54 26.54 33.54 40.54 26.54 16.425 9.425 ],[32.7" "7 32.77 39.77 32.77 39.77 39.77 39.77 32.77 ],[1 1 1 ]);\npatch([16.425 26.54 19.54 9.425 16.425 ],[25.77 25.77 " "32.77 32.77 25.77 ],[0.931 0.946 0.973 ]);\npatch([9.425 19.54 26.54 16.425 9.425 ],[18.77 18.77 25.77 25.77 18." "77 ],[1 1 1 ]);\npatch([16.425 40.54 33.54 26.54 19.54 9.425 16.425 ],[11.77 11.77 18.77 11.77 18.77 18.77 11.77" " ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nc" "olor('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('" "output',1,'\\bf{a - b}','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black'" ");disp(' \\newline\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay" SID "17750" Ports [1, 1] Position [425, 178, 450, 202] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[7 14 0 14 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 24 24 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 24 24 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[15.33 " "15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[12.33 12.33 15.33" " 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 1 " "1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');di" "sp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay1" SID "17751" Ports [1, 1] Position [530, 198, 555, 222] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[7 14 0 14 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 24 24 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 24 24 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[15.33 " "15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[12.33 12.33 15.33" " 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 1 " "1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');di" "sp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay4" SID "17752" Ports [2, 1] Position [330, 278, 365, 302] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en on latency "8" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[9 17 0 17 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,24,2,1,white,blue,0,76050afe,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[15" ".33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.33 12." "33 15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 12.33 " "9.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncol" "or('black');port_label('input',2,'en');\n\ncolor('black');disp('z^{-8}','texmode','on');\nfprintf('','COMMENT: e" "nd icon text');" } Block { BlockType Reference Name "Delay6" SID "17753" Ports [2, 1] Position [265, 143, 300, 167] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en on latency "32" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[9 17 0 17 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,24,2,1,white,blue,0,8441554b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[15" ".33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.33 12." "33 15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 12.33 " "9.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncol" "or('black');port_label('input',2,'en');\n\ncolor('black');disp('z^{-32}','texmode','on');\nfprintf('','COMMENT: " "end icon text');" } Block { BlockType Reference Name "Register" SID "17754" Ports [2, 1] Position [690, 152, 725, 188] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,36,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 36 36 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 36 36 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[23.55 23." "55 28.55 23.55 28.55 28.55 28.55 23.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[18.55 18.55 23.55 2" "3.55 18.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[13.55 13.55 18.55 18.55 13.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[8.55 8.55 13.55 8.55 13.55 13.55 8.55 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');por" "t_label('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\n" "color('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "17755" Ports [2, 1] Position [700, 287, 735, 323] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,36,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 36 36 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 36 36 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[23.55 23." "55 28.55 23.55 28.55 28.55 28.55 23.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[18.55 18.55 23.55 2" "3.55 18.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[13.55 13.55 18.55 18.55 13.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[8.55 8.55 13.55 8.55 13.55 13.55 8.55 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');por" "t_label('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\n" "color('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "17756" Ports [2, 1] Position [785, 162, 820, 198] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,36,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 36 36 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 36 36 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[23.55 23." "55 28.55 23.55 28.55 28.55 28.55 23.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[18.55 18.55 23.55 2" "3.55 18.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[13.55 13.55 18.55 18.55 13.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[8.55 8.55 13.55 8.55 13.55 13.55 8.55 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');por" "t_label('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\n" "color('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register3" SID "17757" Ports [2, 1] Position [780, 297, 815, 333] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,36,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 36 36 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 36 36 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[23.55 23." "55 28.55 23.55 28.55 28.55 28.55 23.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[18.55 18.55 23.55 2" "3.55 18.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[13.55 13.55 18.55 18.55 13.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[8.55 8.55 13.55 8.55 13.55 13.55 8.55 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');por" "t_label('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\n" "color('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Sum 32" SID "17758" Position [910, 173, 940, 187] IconDisplay "Port number" } Block { BlockType Outport Name "Sum 40" SID "17759" Position [910, 308, 940, 322] Port "2" IconDisplay "Port number" } Line { SrcBlock "Register3" SrcPort 1 DstBlock "Sum 40" DstPort 1 } Line { SrcBlock "Register1" SrcPort 1 DstBlock "Register3" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Sum 32" DstPort 1 } Line { SrcBlock "Register" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "Delay4" SrcPort 1 DstBlock "AddSub2" DstPort 2 } Line { SrcBlock "Accum2" SrcPort 1 DstBlock "Register1" DstPort 1 } Line { SrcBlock "AddSub2" SrcPort 1 DstBlock "Accum2" DstPort 1 } Line { SrcBlock "Delay1" SrcPort 1 Points [55, 0] Branch { Points [0, -20] Branch { DstBlock "Register2" DstPort 2 } Branch { Points [0, -10] DstBlock "Register" DstPort 2 } } Branch { Points [0, 105] Branch { Points [0, 10] DstBlock "Register3" DstPort 2 } Branch { DstBlock "Register1" DstPort 2 } } } Line { SrcBlock "Delay" SrcPort 1 Points [50, -5; 0, 0] Branch { Points [0, 20] Branch { DstBlock "Accum2" DstPort 2 } Branch { DstBlock "Delay1" DstPort 1 } } Branch { DstBlock "Accum1" DstPort 2 } } Line { SrcBlock "En" SrcPort 1 Points [10, 0] Branch { Points [0, 105] DstBlock "Delay4" DstPort 2 } Branch { DstBlock "Delay" DstPort 1 } Branch { Points [0, -30] DstBlock "Delay6" DstPort 2 } } Line { SrcBlock "Accum1" SrcPort 1 DstBlock "Register" DstPort 1 } Line { SrcBlock "D" SrcPort 1 Points [0, 0; 15, 0] Branch { Points [80, 0] Branch { Points [0, 135] DstBlock "AddSub2" DstPort 1 } Branch { DstBlock "AddSub1" DstPort 1 } } Branch { Points [0, 20] DstBlock "Delay6" DstPort 1 } } Line { SrcBlock "AddSub1" SrcPort 1 DstBlock "Accum1" DstPort 1 } Line { SrcBlock "Delay6" SrcPort 1 Points [10, 0] Branch { DstBlock "Delay4" DstPort 1 } Branch { DstBlock "AddSub1" DstPort 2 } } Annotation { Name "Extra delay here to align with correlation calc" Position [762, 241] } } } Block { BlockType Reference Name "done1" SID "17760" Ports [1, 1] Position [760, 420, 795, 430] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ADCQ" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "done2" SID "17761" Ports [1, 1] Position [760, 435, 795, 445] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "I^2" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "done3" SID "17762" Ports [1, 1] Position [760, 450, 795, 460] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Q^2" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "done4" SID "17763" Ports [1, 1] Position [760, 405, 795, 415] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ADCI" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "done5" SID "17764" Ports [1, 1] Position [760, 465, 795, 475] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Sum" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "done6" SID "17765" Ports [1, 1] Position [760, 480, 795, 490] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Mag 16" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "done7" SID "17766" Ports [1, 1] Position [760, 495, 795, 505] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Mag 20" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Outport Name "Mag 16" SID "17767" Position [670, 213, 700, 227] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Outport Name "Mag 20" SID "17768" Position [670, 238, 700, 252] Port "2" IconDisplay "Port number" } Line { Name "Mag 20" Labels [0, 0] SrcBlock "done7" SrcPort 1 DstBlock "Auto Corr Mag Calc" DstPort 7 } Line { SrcBlock "Running Sum" SrcPort 2 Points [45, 0] Branch { Points [0, 255] DstBlock "done7" DstPort 1 } Branch { DstBlock "Mag 20" DstPort 1 } } Line { Name "Mag 16" Labels [0, 0] SrcBlock "done6" SrcPort 1 DstBlock "Auto Corr Mag Calc" DstPort 6 } Line { Name "Sum" Labels [0, 0] SrcBlock "done5" SrcPort 1 DstBlock "Auto Corr Mag Calc" DstPort 5 } Line { Name "Q^2" Labels [0, 0] SrcBlock "done3" SrcPort 1 DstBlock "Auto Corr Mag Calc" DstPort 4 } Line { Name "I^2" Labels [0, 0] SrcBlock "done2" SrcPort 1 DstBlock "Auto Corr Mag Calc" DstPort 3 } Line { Name "ADCQ" Labels [0, 0] SrcBlock "done1" SrcPort 1 DstBlock "Auto Corr Mag Calc" DstPort 2 } Line { Name "ADCI" Labels [0, 0] SrcBlock "done4" SrcPort 1 DstBlock "Auto Corr Mag Calc" DstPort 1 } Line { SrcBlock "AddSub" SrcPort 1 Points [45, 0] Branch { Points [0, 210] DstBlock "done5" DstPort 1 } Branch { Points [0, -15] DstBlock "Running Sum" DstPort 2 } } Line { SrcBlock "Mult1" SrcPort 1 Points [15, 0] Branch { Points [0, 140] DstBlock "done3" DstPort 1 } Branch { Points [0, -40] DstBlock "AddSub" DstPort 2 } } Line { SrcBlock "Mult" SrcPort 1 Points [20, 0] Branch { Points [0, 195] DstBlock "done2" DstPort 1 } Branch { DstBlock "AddSub" DstPort 1 } } Line { SrcBlock "Q" SrcPort 1 Points [75, 0] Branch { Points [0, 125] DstBlock "done1" DstPort 1 } Branch { Points [35, 0] Branch { DstBlock "Mult1" DstPort 1 } Branch { Points [0, 30] DstBlock "Mult1" DstPort 2 } } } Line { SrcBlock "Running Sum" SrcPort 1 Points [50, 0] Branch { DstBlock "Mag 16" DstPort 1 } Branch { Points [0, 265] DstBlock "done6" DstPort 1 } } Line { SrcBlock "Valid" SrcPort 1 DstBlock "Delay" DstPort 1 } Line { SrcBlock "I" SrcPort 1 Points [80, 0] Branch { Points [0, 180] DstBlock "done4" DstPort 1 } Branch { Points [30, 0] Branch { Points [0, 30] DstBlock "Mult" DstPort 2 } Branch { DstBlock "Mult" DstPort 1 } } } Line { SrcBlock "Delay" SrcPort 1 Points [65, 0; 0, 40] DstBlock "Running Sum" DstPort 1 } } } Block { BlockType Reference Name "Register1" SID "17769" Ports [1, 1] Position [420, 228, 450, 252] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,24,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 24 24 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 24 24 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[15.3" "3 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[12.33 12.33 " "15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[9.33 9.33 12.33 12.33 9.33 " "],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('blac" "k');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmod" "e','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "17770" Ports [1, 1] Position [420, 203, 450, 227] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,24,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 24 24 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 24 24 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[15.3" "3 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[12.33 12.33 " "15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[9.33 9.33 12.33 12.33 9.33 " "],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('blac" "k');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmod" "e','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register3" SID "17771" Ports [1, 1] Position [420, 253, 450, 277] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,24,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 24 24 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 24 24 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[15.3" "3 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[12.33 12.33 " "15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[9.33 9.33 12.33 12.33 9.33 " "],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('blac" "k');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmod" "e','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "done1" SID "17772" Ports [1, 1] Position [1060, 530, 1095, 540] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Det Reset OFDM" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "done2" SID "17773" Ports [1, 1] Position [1060, 440, 1095, 450] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ADCQ" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "done3" SID "17774" Ports [1, 1] Position [1060, 455, 1095, 465] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Mag" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "done4" SID "17775" Ports [1, 1] Position [1060, 425, 1095, 435] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "ADCI" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "done5" SID "17776" Ports [1, 1] Position [1060, 470, 1095, 480] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr OFDM" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "done6" SID "17777" Ports [1, 1] Position [1060, 500, 1095, 510] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Det OFDM" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "done7" SID "17778" Ports [1, 1] Position [1060, 485, 1095, 495] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Corr DSSS" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "done8" SID "17779" Ports [1, 1] Position [1060, 515, 1095, 525] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Det DSSS" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "done9" SID "17780" Ports [1, 1] Position [1060, 545, 1095, 555] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0 0 0 0 1 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 10 10 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 10 10 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[6." "11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[5.11 5.11 6.11 6." "11 5.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Det Reset DSSS" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Outport Name "Det OFDM" SID "17781" Position [1045, 142, 1075, 158] IconDisplay "Port number" } Block { BlockType Outport Name "Det DSSS" SID "17782" Position [1045, 282, 1075, 298] Port "2" IconDisplay "Port number" } Line { SrcBlock "Mag" SrcPort 2 Points [85, 0] DstBlock "Decision" DstPort 7 } Line { SrcBlock "Reset DSSS" SrcPort 1 Points [245, 0] Branch { Points [0, 410] DstBlock "done9" DstPort 1 } Branch { DstBlock "Decision" DstPort 2 } } Line { SrcBlock "Reset OFDM" SrcPort 1 Points [255, 0] Branch { Points [0, 435] DstBlock "done1" DstPort 1 } Branch { DstBlock "Decision" DstPort 1 } } Line { SrcBlock "Decision" SrcPort 2 Points [30, 0] Branch { DstBlock "Det DSSS" DstPort 1 } Branch { Points [0, 230] DstBlock "done8" DstPort 1 } } Line { Name "Det Reset DSSS" Labels [0, 0] SrcBlock "done9" SrcPort 1 DstBlock "Auto Corr Pkt Det" DstPort 9 } Line { Name "Det Reset OFDM" Labels [0, 0] SrcBlock "done1" SrcPort 1 DstBlock "Auto Corr Pkt Det" DstPort 8 } Line { Name "Det DSSS" Labels [0, 0] SrcBlock "done8" SrcPort 1 DstBlock "Auto Corr Pkt Det" DstPort 7 } Line { Name "Det OFDM" Labels [0, 0] SrcBlock "done6" SrcPort 1 DstBlock "Auto Corr Pkt Det" DstPort 6 } Line { Name "Corr DSSS" Labels [0, 0] SrcBlock "done7" SrcPort 1 DstBlock "Auto Corr Pkt Det" DstPort 5 } Line { Name "Corr OFDM" Labels [0, 0] SrcBlock "done5" SrcPort 1 DstBlock "Auto Corr Pkt Det" DstPort 4 } Line { Name "Mag" Labels [0, 0] SrcBlock "done3" SrcPort 1 DstBlock "Auto Corr Pkt Det" DstPort 3 } Line { Name "ADCQ" Labels [0, 0] SrcBlock "done2" SrcPort 1 DstBlock "Auto Corr Pkt Det" DstPort 2 } Line { Name "ADCI" Labels [0, 0] SrcBlock "done4" SrcPort 1 DstBlock "Auto Corr Pkt Det" DstPort 1 } Line { SrcBlock "Auto Corr" SrcPort 2 Points [15, 0] Branch { Points [0, 230] DstBlock "done7" DstPort 1 } Branch { DstBlock "Decision" DstPort 5 } } Line { SrcBlock "rx_Q" SrcPort 1 DstBlock "Register3" DstPort 1 } Line { SrcBlock "rx_I" SrcPort 1 DstBlock "Register1" DstPort 1 } Line { Labels [0, 1] SrcBlock "rx_valid" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { Labels [0, 0] SrcBlock "Register1" SrcPort 1 Points [145, 0] Branch { Points [0, 105] Branch { Points [0, 85] DstBlock "done4" DstPort 1 } Branch { DstBlock "Mag" DstPort 2 } } Branch { DstBlock "Auto Corr" DstPort 2 } } Line { Labels [0, 0] SrcBlock "Register3" SrcPort 1 Points [135, 0] Branch { DstBlock "Auto Corr" DstPort 3 } Branch { Points [0, 110] Branch { Points [0, 70] DstBlock "done2" DstPort 1 } Branch { DstBlock "Mag" DstPort 3 } } } Line { Labels [0, 0] SrcBlock "Register2" SrcPort 1 Points [155, 0] Branch { Labels [2, 0] Points [0, -35] DstBlock "Decision" DstPort 3 } Branch { Points [0, 100] DstBlock "Mag" DstPort 1 } Branch { DstBlock "Auto Corr" DstPort 1 } } Line { SrcBlock "Auto Corr" SrcPort 1 Points [25, 0] Branch { Points [0, 255] DstBlock "done5" DstPort 1 } Branch { DstBlock "Decision" DstPort 4 } } Line { SrcBlock "Mag" SrcPort 1 Points [50, 20; 0, 0] Branch { Points [0, 135] DstBlock "done3" DstPort 1 } Branch { Points [0, -25] DstBlock "Decision" DstPort 6 } } Line { SrcBlock "Decision" SrcPort 1 Points [35, 0] Branch { DstBlock "Det OFDM" DstPort 1 } Branch { Points [0, 355] DstBlock "done6" DstPort 1 } } } } Block { BlockType From Name "From1" SID "17783" Position [510, 192, 725, 208] ShowName off CloseFcn "tagdialog Close" GotoTag "regRx_pktDet_requireBothB_OFDM" TagVisibility "global" } Block { BlockType From Name "From2" SID "17784" Position [510, 212, 725, 228] ShowName off CloseFcn "tagdialog Close" GotoTag "regRx_pktDet_requireBothB_DSSS" TagVisibility "global" } Block { BlockType Reference Name "Logical" SID "17785" Ports [2, 1] Position [775, 336, 810, 369] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,33,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 33 33 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 33 33 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[20.44 20.44 24.4" "4 20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[16.44 16.44 20.44 20.44 16.44 ]," "[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1 1 1 ]);\npatch([12.1" " 25.88 21.88 17.88 13.88 8.1 12.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('or');\nfprintf('" "','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "17786" Ports [2, 1] Position [775, 436, 810, 469] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,33,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 33 33 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 33 33 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[20.44 20.44 24.4" "4 20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[16.44 16.44 20.44 20.44 16.44 ]," "[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1 1 1 ]);\npatch([12.1" " 25.88 21.88 17.88 13.88 8.1 12.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('or');\nfprintf('" "','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "17787" Ports [2, 1] Position [775, 466, 810, 499] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,33,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 33 33 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 33 33 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[20.44 20.44 24.4" "4 20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[16.44 16.44 20.44 20.44 16.44 ]," "[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1 1 1 ]);\npatch([12.1" " 25.88 21.88 17.88 13.88 8.1 12.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('and');\nfprintf(" "'','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical3" SID "17788" Ports [2, 1] Position [775, 366, 810, 399] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,33,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 33 33 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 33 33 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[20.44 20.44 24.4" "4 20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[16.44 16.44 20.44 20.44 16.44 ]," "[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1 1 1 ]);\npatch([12.1" " 25.88 21.88 17.88 13.88 8.1 12.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('and');\nfprintf(" "'','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux" SID "17789" Ports [3, 1] Position [880, 312, 915, 398] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "35,86,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 12.2857 73.7143 86 0 ],[0." "77 0.82 0.91 ]);\nplot([0 35 35 0 0 ],[0 12.2857 73.7143 86 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5." "875 ],[48.55 48.55 53.55 48.55 53.55 53.55 53.55 48.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[43.55" " 43.55 48.55 48.55 43.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[38.55 38.55 43.55 43.55 " "38.55 ],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[33.55 33.55 38.55 33.55 38.55 38.55 33.55 ]," "[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor(" "'black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('inpu" "t',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux1" SID "17790" Ports [3, 1] Position [880, 412, 915, 498] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "35,86,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 12.2857 73.7143 86 0 ],[0." "77 0.82 0.91 ]);\nplot([0 35 35 0 0 ],[0 12.2857 73.7143 86 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5." "875 ],[48.55 48.55 53.55 48.55 53.55 53.55 53.55 48.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[43.55" " 43.55 48.55 48.55 43.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[38.55 38.55 43.55 43.55 " "38.55 ],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[33.55 33.55 38.55 33.55 38.55 38.55 33.55 ]," "[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor(" "'black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('inpu" "t',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "RSSI Pkt Det" SID "17791" Ports [3, 2] Position [535, 414, 665, 476] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "RSSI Pkt Det" Location [58, 156, 383, 269] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "143" Block { BlockType Inport Name "Reset OFDM" SID "17792" Position [360, 273, 390, 287] IconDisplay "Port number" } Block { BlockType Inport Name "Reset DSSS" SID "17793" Position [360, 378, 390, 392] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "Avg RSSI" SID "17794" Position [245, 248, 275, 262] NamePlacement "alternate" Port "3" IconDisplay "Port number" Port { PortNumber 1 PropagatedSignals "RFB_RSSI" ShowPropagatedSignals "on" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType SubSystem Name "Detection Decision" SID "17795" Ports [1, 1] Position [455, 235, 540, 275] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Detection Decision" Location [572, 342, 1525, 506] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "135" Block { BlockType Inport Name "Avg RSSI" SID "17796" Position [240, 223, 270, 237] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Reference Name "Concat" SID "17797" Ports [2, 1] Position [695, 268, 720, 317] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point " "at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "25,49,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 49 49 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 49 49 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[27.33 " "27.33 30.33 27.33 30.33 30.33 30.33 27.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[24.33 24.33 27.33" " 27.33 24.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[21.33 21.33 24.33 24.33 21.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[18.33 18.33 21.33 18.33 21.33 21.33 18.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('blac" "k');port_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fontsize{2" "0}\\}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant" SID "17798" Ports [0, 1] Position [625, 295, 645, 315] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "4" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "20,20,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 20 20 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 20 20 0 0 ],[0 0 20 20 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[12.22 12." "22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[10.22 10.22 12.22 12.22" " 10.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npa" "tch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfprin" "tf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output" "',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Counter1" SID "17799" Ports [2, 1] Position [695, 194, 730, 256] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited count" "er is implemented by combining a counter with a comparator." cnt_type "Count Limited" cnt_to "1023" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "10" bin_pt "0" load_pin off rst on en on explicit_period "off" period "4" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,619" block_type "counter" block_version "10.1.3" sg_icon_stat "35,62,2,1,white,blue,0,131a2a7a,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 62 62 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 62 62 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[36.55 36." "55 41.55 36.55 41.55 41.55 41.55 36.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[31.55 31.55 36.55 3" "6.55 31.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[26.55 26.55 31.55 31.55 26.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[21.55 21.55 26.55 21.55 26.55 26.55 21.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'rst');\ncolor('black');port_label('input',2,'en');\n\ncolor('black');disp('{\\fontsize{14" "}\\bf\\lceil++\\rceil}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From3" SID "17800" Position [95, 242, 310, 258] ShowName off CloseFcn "tagdialog Close" GotoTag "regRx_PKTDET_RSSI_THRESH_B" TagVisibility "global" } Block { BlockType From Name "From4" SID "17801" Position [230, 272, 450, 288] ShowName off CloseFcn "tagdialog Close" GotoTag "regRx_PKTDET_RSSI_MIN_DUR_B" TagVisibility "global" } Block { BlockType Reference Name "Inverter1" SID "17802" Ports [1, 1] Position [560, 203, 585, 217] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "8.2" sg_icon_stat "25,14,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.2" "2 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 " "],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.5" "5 16.44 14.44 12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfprintf" "('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register" SID "17803" Ports [1, 1] Position [575, 265, 605, 295] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 30 30 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 30 30 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 19.4" "4 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 19.44 " "15.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\np" "atch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('in" "put',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf" "('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational2" SID "17804" Ports [2, 1] Position [365, 218, 410, 262] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a>b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "500,165,356,193" block_type "relational" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,2,1,white,blue,0,b5131c97,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bfa > b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational3" SID "17805" Ports [2, 1] Position [795, 213, 840, 257] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a>b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "500,165,356,193" block_type "relational" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,2,1,white,blue,0,b5131c97,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bfa > b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Pkt Det" SID "17806" Position [920, 228, 950, 242] IconDisplay "Port number" } Line { SrcBlock "Relational2" SrcPort 1 Points [90, 0] Branch { DstBlock "Counter1" DstPort 2 } Branch { Points [0, -30] DstBlock "Inverter1" DstPort 1 } } Line { SrcBlock "Inverter1" SrcPort 1 DstBlock "Counter1" DstPort 1 } Line { SrcBlock "Concat" SrcPort 1 Points [55, 0] DstBlock "Relational3" DstPort 2 } Line { SrcBlock "Register" SrcPort 1 DstBlock "Concat" DstPort 1 } Line { SrcBlock "Constant" SrcPort 1 DstBlock "Concat" DstPort 2 } Line { SrcBlock "Avg RSSI" SrcPort 1 DstBlock "Relational2" DstPort 1 } Line { SrcBlock "Relational3" SrcPort 1 DstBlock "Pkt Det" DstPort 1 } Line { SrcBlock "From4" SrcPort 1 DstBlock "Register" DstPort 1 } Line { SrcBlock "Counter1" SrcPort 1 DstBlock "Relational3" DstPort 1 } Line { SrcBlock "From3" SrcPort 1 DstBlock "Relational2" DstPort 2 } Annotation { Name "Require avg(RSSI) > thresh for a minimum number of\nsample periods. This coutner stops at its max val" "ue and\nis reset any time the avg(RSSI) falls below the threshold." Position [386, 361] } Annotation { Position [1012, 242] } } } Block { BlockType From Name "From9" SID "17807" Position [220, 189, 435, 211] ShowName off CloseFcn "tagdialog Close" GotoTag "MAC_PHY_BLOCK_PKT_DET" TagVisibility "global" } Block { BlockType Reference Name "Inverter" SID "17808" Ports [1, 1] Position [480, 191, 505, 209] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical3" SID "17809" Ports [2, 1] Position [715, 223, 760, 267] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('" "black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Posedge1" SID "17810" Ports [1, 1] Position [590, 246, 635, 264] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Posedge1" Location [88, 301, 2330, 1301] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "17811" Position [200, 253, 230, 267] IconDisplay "Port number" } Block { BlockType Reference Name "Delay" SID "17812" Ports [1, 1] Position [425, 153, 460, 177] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. " "If register retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[15" ".33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.33 12." "33 15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 12.33 " "9.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\nc" "olor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "17813" Ports [1, 1] Position [490, 156, 515, 174] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "17814" Ports [2, 1] Position [540, 151, 585, 204] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,53,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 53 53 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 53 53 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[32.66 3" "2.66 38.66 32.66 38.66 38.66 38.66 32.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[26.66 26.66 32.66 " "32.66 26.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[20.66 20.66 26.66 26.66 20.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[14.66 14.66 20.66 14.66 20.66 20.66 14.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('" "black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "17815" Position [610, 173, 640, 187] IconDisplay "Port number" } Line { SrcBlock "D" SrcPort 1 Points [150, 0; 0, -70] Branch { DstBlock "Logical1" DstPort 2 } Branch { Points [0, -25] DstBlock "Delay" DstPort 1 } } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Delay" SrcPort 1 DstBlock "Inverter" DstPort 1 } Annotation { Name "Rising Edge Detection" Position [500, 112] } } } Block { BlockType Reference Name "Register6" SID "17816" Ports [1, 1] Position [570, 184, 600, 216] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,32,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 32 32 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 32 32 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[20.44 20.4" "4 24.44 20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[16.44 16.44 20.44 20.44 " "16.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1 1 1 ]);\np" "atch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('in" "put',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf" "('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "S-R Latch1" SID "17817" Ports [2, 1] Position [805, 229, 835, 296] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "S-R Latch1" Location [160, 70, 1918, 1152] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "17818" Position [140, 103, 170, 117] IconDisplay "Port number" } Block { BlockType Inport Name "R" SID "17819" Position [140, 88, 170, 102] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "17820" Ports [0, 1] Position [195, 71, 210, 89] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "15,18,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11.22 " "13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 9.22 " "],[0.931 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([4.55 " "11.44 9.44 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "17821" Ports [3, 1] Position [255, 71, 300, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "17822" Position [325, 88, 355, 102] IconDisplay "Port number" } Line { SrcBlock "S" SrcPort 1 DstBlock "Register2" DstPort 3 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Register2" DstPort 1 } } } Block { BlockType SubSystem Name "S-R Latch2" SID "17823" Ports [2, 1] Position [805, 334, 835, 401] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "S-R Latch2" Location [160, 70, 1918, 1152] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "17824" Position [140, 103, 170, 117] IconDisplay "Port number" } Block { BlockType Inport Name "R" SID "17825" Position [140, 88, 170, 102] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "17826" Ports [0, 1] Position [195, 71, 210, 89] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "15,18,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11.22 " "13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 9.22 " "],[0.931 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([4.55 " "11.44 9.44 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "17827" Ports [3, 1] Position [255, 71, 300, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "17828" Position [325, 88, 355, 102] IconDisplay "Port number" } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "S" SrcPort 1 DstBlock "Register2" DstPort 3 } } } Block { BlockType Outport Name "PktDet OFDM" SID "17829" Position [900, 258, 930, 272] IconDisplay "Port number" } Block { BlockType Outport Name "PktDet DSSS" SID "17830" Position [900, 363, 930, 377] Port "2" IconDisplay "Port number" } Line { SrcBlock "Register6" SrcPort 1 Points [50, 0; 0, 35] DstBlock "Logical3" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Register6" DstPort 1 } Line { SrcBlock "Logical3" SrcPort 1 Points [10, 0] Branch { Points [0, 105] DstBlock "S-R Latch2" DstPort 1 } Branch { DstBlock "S-R Latch1" DstPort 1 } } Line { SrcBlock "From9" SrcPort 1 DstBlock "Inverter" DstPort 1 } Line { SrcBlock "Reset DSSS" SrcPort 1 DstBlock "S-R Latch2" DstPort 2 } Line { SrcBlock "S-R Latch2" SrcPort 1 DstBlock "PktDet DSSS" DstPort 1 } Line { SrcBlock "Detection Decision" SrcPort 1 DstBlock "Posedge1" DstPort 1 } Line { SrcBlock "Reset OFDM" SrcPort 1 DstBlock "S-R Latch1" DstPort 2 } Line { SrcBlock "S-R Latch1" SrcPort 1 DstBlock "PktDet OFDM" DstPort 1 } Line { SrcBlock "Posedge1" SrcPort 1 DstBlock "Logical3" DstPort 2 } Line { Labels [1, 0] SrcBlock "Avg RSSI" SrcPort 1 DstBlock "Detection Decision" DstPort 1 } Annotation { Name "The DSSS and OFDM pipelines operate independently. Both require\ntheir pktDet inputs to assert at the" " beginning of a reception\nand stay asserted until the pipeline is finished. But each pipeline\ncan reset the ot" "her (valid OFDM implies DSSS not valid), so\nthe pkt det state bits must be kept separate here." Position [479, 125] } } } Block { BlockType Outport Name "Det OFDM" SID "17831" Position [960, 348, 990, 362] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Outport Name "Det DSSS" SID "17832" Position [960, 448, 990, 462] Port "2" IconDisplay "Port number" } Line { SrcBlock "From2" SrcPort 1 Points [110, 0; 0, 205] DstBlock "Mux1" DstPort 1 } Line { SrcBlock "Mux1" SrcPort 1 DstBlock "Det DSSS" DstPort 1 } Line { SrcBlock "Logical2" SrcPort 1 DstBlock "Mux1" DstPort 3 } Line { SrcBlock "RSSI Pkt Det" SrcPort 1 Points [35, 0; 0, -70; 40, 0] Branch { Points [0, 30] DstBlock "Logical3" DstPort 2 } Branch { DstBlock "Logical" DstPort 2 } } Line { SrcBlock "Auto-Corr Pkt Det" SrcPort 1 Points [80, 0] Branch { Points [0, 30] DstBlock "Logical3" DstPort 1 } Branch { DstBlock "Logical" DstPort 1 } } Line { SrcBlock "RSSI Pkt Det" SrcPort 2 Points [70, 0] Branch { Points [0, 30] DstBlock "Logical2" DstPort 2 } Branch { DstBlock "Logical1" DstPort 2 } } Line { SrcBlock "Auto-Corr Pkt Det" SrcPort 2 Points [15, 0; 0, 55; 65, 0] Branch { Points [0, 30] DstBlock "Logical2" DstPort 1 } Branch { DstBlock "Logical1" DstPort 1 } } Line { SrcBlock "RSSI" SrcPort 1 DstBlock "RSSI Pkt Det" DstPort 3 } Line { SrcBlock "Mux" SrcPort 1 DstBlock "Det OFDM" DstPort 1 } Line { SrcBlock "Logical3" SrcPort 1 DstBlock "Mux" DstPort 3 } Line { SrcBlock "From1" SrcPort 1 Points [125, 0; 0, 125] DstBlock "Mux" DstPort 1 } Line { SrcBlock "Reset DSSS" SrcPort 1 Points [55, 0; 0, 40] Branch { Points [0, 95] DstBlock "RSSI Pkt Det" DstPort 2 } Branch { DstBlock "Auto-Corr Pkt Det" DstPort 2 } } Line { SrcBlock "Reset OFDM" SrcPort 1 Points [65, 0; 0, 65] Branch { Points [0, 90] DstBlock "RSSI Pkt Det" DstPort 1 } Branch { DstBlock "Auto-Corr Pkt Det" DstPort 1 } } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Mux1" DstPort 2 } Line { SrcBlock "Rx I" SrcPort 1 DstBlock "Auto-Corr Pkt Det" DstPort 3 } Line { SrcBlock "Rx Q" SrcPort 1 DstBlock "Auto-Corr Pkt Det" DstPort 4 } Line { SrcBlock "IQ Valid" SrcPort 1 DstBlock "Auto-Corr Pkt Det" DstPort 5 } Line { SrcBlock "Logical" SrcPort 1 DstBlock "Mux" DstPort 2 } } } Block { BlockType Reference Name "Register1" SID "8372" Ports [1, 1] Position [550, 12, 575, 38] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 " "16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "8373" Ports [1, 1] Position [465, 42, 490, 68] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 " "16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register3" SID "8374" Ports [1, 1] Position [465, 12, 490, 38] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 " "16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register4" SID "8375" Ports [1, 1] Position [550, 42, 575, 68] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 " "16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register5" SID "15800" Ports [1, 1] Position [550, 87, 575, 113] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 " "16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register6" SID "15801" Ports [1, 1] Position [465, 117, 490, 143] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 " "16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register7" SID "15802" Ports [1, 1] Position [465, 87, 490, 113] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 " "16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register8" SID "15803" Ports [1, 1] Position [550, 117, 575, 143] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 " "16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Det OFDM" SID "8376" Position [1100, 383, 1130, 397] IconDisplay "Port number" } Block { BlockType Outport Name "Det OFDM AGC Trig" SID "18091" Position [1100, 318, 1130, 332] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "Det DSSS" SID "8377" Position [1045, 498, 1075, 512] Port "3" IconDisplay "Port number" } Line { SrcBlock "Rx Q Vec" SrcPort 1 DstBlock "Bus\nSelector1" DstPort 1 } Line { SrcBlock "IQ Valid" SrcPort 1 DstBlock "Bus\nSelector3" DstPort 1 } Line { SrcBlock "RSSI Vec" SrcPort 1 DstBlock "Bus\nSelector2" DstPort 1 } Line { SrcBlock "RF A Det" SrcPort 1 DstBlock "OFDM Ant Sel Logic" DstPort 3 } Line { SrcBlock "OFDM Ant Sel Logic" SrcPort 1 Points [30, 0] Branch { DstBlock "Logical1" DstPort 3 } Branch { Points [0, -70] Branch { DstBlock "Logical2" DstPort 2 } Branch { Points [0, -120] DstBlock "Inverter2" DstPort 1 } } } Line { SrcBlock "Rx I Vec" SrcPort 1 DstBlock "Bus\nSelector" DstPort 1 } Line { SrcBlock "Logical1" SrcPort 1 Points [75, 0] Branch { DstBlock "Det OFDM" DstPort 1 } Branch { Points [0, 240] DstBlock "Posedge1" DstPort 1 } } Line { SrcBlock "Ext Pkt Det" SrcPort 1 Points [60, 0] Branch { Points [0, 55] DstBlock "OFDM Ant Sel Logic" DstPort 2 } Branch { Points [165, 0] Branch { Points [0, 50] DstBlock "Logical1" DstPort 2 } Branch { Points [0, -30] DstBlock "Logical2" DstPort 1 } } } Line { Name "" Labels [0, 0] SrcBlock "Bus\nSelector" SrcPort 1 DstBlock "Goto" DstPort 1 } Line { Name "" Labels [0, 0] SrcBlock "Bus\nSelector" SrcPort 2 DstBlock "Goto1" DstPort 1 } Line { Name "" Labels [0, 0] SrcBlock "Bus\nSelector" SrcPort 3 DstBlock "Goto2" DstPort 1 } Line { Name "" Labels [0, 0] SrcBlock "Bus\nSelector" SrcPort 4 DstBlock "Goto3" DstPort 1 } Line { Name "" Labels [0, 0] SrcBlock "Bus\nSelector1" SrcPort 1 DstBlock "Goto4" DstPort 1 } Line { Name "" Labels [0, 0] SrcBlock "Bus\nSelector1" SrcPort 2 DstBlock "Goto5" DstPort 1 } Line { Name "" Labels [0, 0] SrcBlock "Bus\nSelector1" SrcPort 3 DstBlock "Goto6" DstPort 1 } Line { Name "" Labels [0, 0] SrcBlock "Bus\nSelector1" SrcPort 4 DstBlock "Goto7" DstPort 1 } Line { Name "" Labels [0, 0] SrcBlock "Bus\nSelector3" SrcPort 1 DstBlock "Goto8" DstPort 1 } Line { Name "" Labels [0, 0] SrcBlock "Bus\nSelector3" SrcPort 2 DstBlock "Goto9" DstPort 1 } Line { Name "" Labels [0, 0] SrcBlock "Bus\nSelector3" SrcPort 3 DstBlock "Goto10" DstPort 1 } Line { Name "" Labels [0, 0] SrcBlock "Bus\nSelector3" SrcPort 4 DstBlock "Goto11" DstPort 1 } Line { Name "" Labels [0, 0] SrcBlock "Bus\nSelector2" SrcPort 1 DstBlock "Goto12" DstPort 1 } Line { Name "" Labels [0, 0] SrcBlock "Bus\nSelector2" SrcPort 2 DstBlock "Goto13" DstPort 1 } Line { Name "" Labels [0, 0] SrcBlock "Bus\nSelector2" SrcPort 3 DstBlock "Goto14" DstPort 1 } Line { Name "" Labels [0, 0] SrcBlock "Bus\nSelector2" SrcPort 4 DstBlock "Goto15" DstPort 1 } Line { SrcBlock "From" SrcPort 1 DstBlock "RF A Det" DstPort 3 } Line { SrcBlock "From1" SrcPort 1 DstBlock "RF A Det" DstPort 4 } Line { SrcBlock "From2" SrcPort 1 DstBlock "RF A Det" DstPort 5 } Line { SrcBlock "From3" SrcPort 1 DstBlock "RF A Det" DstPort 6 } Line { SrcBlock "From4" SrcPort 1 DstBlock "RF B Det" DstPort 3 } Line { SrcBlock "From5" SrcPort 1 DstBlock "RF B Det" DstPort 4 } Line { SrcBlock "From6" SrcPort 1 DstBlock "RF B Det" DstPort 5 } Line { SrcBlock "From7" SrcPort 1 DstBlock "RF B Det" DstPort 6 } Line { SrcBlock "From8" SrcPort 1 Points [45, 0] } Line { SrcBlock "From9" SrcPort 1 Points [45, 0] } Line { SrcBlock "From10" SrcPort 1 Points [45, 0] } Line { SrcBlock "From11" SrcPort 1 Points [45, 0] } Line { SrcBlock "From14" SrcPort 1 Points [45, 0] } Line { SrcBlock "From15" SrcPort 1 Points [45, 0] } Line { SrcBlock "From12" SrcPort 1 Points [45, 0] } Line { SrcBlock "From13" SrcPort 1 Points [45, 0] } Line { SrcBlock "RF A Det" SrcPort 2 Points [10, 0; 0, 30] DstBlock "DSSS Ant Sel Logic" DstPort 1 } Line { SrcBlock "DSSS Ant Sel Logic" SrcPort 1 Points [180, 0] Branch { Points [0, 210] DstBlock "Posedge2" DstPort 1 } Branch { DstBlock "Det DSSS" DstPort 1 } } Line { SrcBlock "Reset OFDM" SrcPort 1 Points [325, 0] Branch { Points [0, 35] Branch { DstBlock "Ext Pkt Det" DstPort 1 } Branch { Points [0, 50] Branch { DstBlock "RF A Det" DstPort 1 } Branch { Points [0, 150] DstBlock "RF B Det" DstPort 1 } } } Branch { Points [0, -5] DstBlock "LTF Only Det" DstPort 2 } } Line { SrcBlock "Reset DSSS" SrcPort 1 Points [315, 0; 0, 60] Branch { DstBlock "RF A Det" DstPort 2 } Branch { Points [0, 150] DstBlock "RF B Det" DstPort 2 } } Line { SrcBlock "Constant2" SrcPort 1 Points [90, 0; 0, -205] Branch { Points [0, -85] DstBlock "OFDM Ant Sel Logic" DstPort 5 } Branch { DstBlock "DSSS Ant Sel Logic" DstPort 3 } } Line { SrcBlock "Constant3" SrcPort 1 Points [100, 0; 0, -275] Branch { Points [0, -90] DstBlock "OFDM Ant Sel Logic" DstPort 6 } Branch { DstBlock "DSSS Ant Sel Logic" DstPort 4 } } Line { SrcBlock "RF B Det" SrcPort 1 Points [20, 0; 0, -140] DstBlock "OFDM Ant Sel Logic" DstPort 4 } Line { SrcBlock "RF B Det" SrcPort 2 Points [30, 0; 0, -105] DstBlock "DSSS Ant Sel Logic" DstPort 2 } Line { SrcBlock "Register3" SrcPort 1 DstBlock "Register1" DstPort 1 } Line { SrcBlock "From16" SrcPort 1 Points [50, 0] Branch { DstBlock "Register3" DstPort 1 } Branch { Points [0, 30] DstBlock "Register2" DstPort 1 } } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Register4" DstPort 1 } Line { SrcBlock "Register1" SrcPort 1 DstBlock "Goto22" DstPort 1 } Line { SrcBlock "Register4" SrcPort 1 DstBlock "Goto16" DstPort 1 } Line { SrcBlock "Register7" SrcPort 1 DstBlock "Register5" DstPort 1 } Line { SrcBlock "From17" SrcPort 1 Points [50, 0] Branch { Points [0, 30] DstBlock "Register6" DstPort 1 } Branch { DstBlock "Register7" DstPort 1 } } Line { SrcBlock "Register6" SrcPort 1 DstBlock "Register8" DstPort 1 } Line { SrcBlock "Register5" SrcPort 1 DstBlock "Goto18" DstPort 1 } Line { SrcBlock "Register8" SrcPort 1 DstBlock "Goto17" DstPort 1 } Line { SrcBlock "Posedge1" SrcPort 1 DstBlock "Counter" DstPort 2 } Line { SrcBlock "Posedge2" SrcPort 1 DstBlock "Counter1" DstPort 2 } Line { SrcBlock "From18" SrcPort 1 Points [85, 0] Branch { DstBlock "Counter" DstPort 1 } Branch { Points [0, 85] DstBlock "Counter1" DstPort 1 } } Line { SrcBlock "Counter" SrcPort 1 DstBlock "Goto19" DstPort 1 } Line { SrcBlock "Counter1" SrcPort 1 DstBlock "Goto20" DstPort 1 } Line { SrcBlock "LTF Det" SrcPort 1 Points [175, 0; 0, 15] DstBlock "Logical4" DstPort 2 } Line { SrcBlock "LTF Only Det" SrcPort 1 Points [70, 0] Branch { Points [0, 90] DstBlock "OFDM Ant Sel Logic" DstPort 1 } Branch { Points [160, 0; 0, 75] DstBlock "Logical1" DstPort 1 } } Line { SrcBlock "Logical2" SrcPort 1 DstBlock "Det OFDM AGC Trig" DstPort 1 } Line { SrcBlock "Logical4" SrcPort 1 Points [20, 0; 0, 15] DstBlock "LTF Only Det" DstPort 1 } Line { SrcBlock "Inverter2" SrcPort 1 Points [-25, 0; 0, 35] DstBlock "Logical4" DstPort 1 } Annotation { Name "Only assert LTF Det if normal pkt det is not asserted\nThis avoids a race between mid-Rx pkt det a" "nd LTF \ndet for asserting/holding AGC enable" Position [414, 178] } } } Block { BlockType SubSystem Name "Pkt Det AGC Ctrl" SID "8378" Ports [2] Position [1080, 289, 1140, 331] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Pkt Det AGC Ctrl" Location [280, 193, 2120, 1196] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Det OFDM" SID "8379" Position [760, 418, 790, 432] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "Det DSSS" SID "8380" Position [760, 438, 790, 452] Port "2" IconDisplay "Port number" } Block { BlockType Scope Name "AGC Ctrl" SID "8381" Ports [4] Position [1190, 193, 1235, 302] ZOrder -3 Floating off Location [46, 36, 670, 1194] Open off NumInputPorts "4" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" } List { ListType ScopeGraphics FigureColor "[0.5 0.5 0.5]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } YMin "-5~-5~-5~-5" YMax "5~5~5~5" SaveName "ScopeData24" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType Reference Name "Gateway Out" SID "8382" Ports [1, 1] Position [1100, 203, 1130, 217] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,14,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 14 14 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 30 30 0 0 ],[0 0 14 14 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[9" ".22 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[7.22 7.22 9.22" " 9.22 7.22 ],[0.964 0.964 0.964 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 " "]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.964 0.964 0.96" "4 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('" "','COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out1" SID "8383" Ports [1, 1] Position [1100, 228, 1130, 242] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,14,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 14 14 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 30 30 0 0 ],[0 0 14 14 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[9" ".22 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[7.22 7.22 9.22" " 9.22 7.22 ],[0.964 0.964 0.964 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 " "]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.964 0.964 0.96" "4 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('" "','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical" SID "8384" Ports [2, 1] Position [905, 415, 945, 455] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,40,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55" " 25.55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25" ".55 25.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 " "],[1 1 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n" "color('black');disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "8385" Ports [1, 1] Position [1010, 422, 1045, 448] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 26 26 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ]" ",[16.33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[13.3" "3 13.33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[10.33 10.33 13.3" "3 13.33 10.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[7.33 7.33 10.33 7.33 10.33 1" "0.33 7.33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon " "text');\ncolor('black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');" "disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "pkt_det_o" SID "8386" Ports [1, 1] Position [1100, 428, 1140, 442] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "40,14,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9" ".22 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22" " 9.22 7.22 ],[0.985 0.979 0.895 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.985 0.979 0.89" "5 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprin" "tf('','COMMENT: end icon text');" } Line { SrcBlock "Register1" SrcPort 1 DstBlock "pkt_det_o" DstPort 1 } Line { SrcBlock "Logical" SrcPort 1 DstBlock "Register1" DstPort 1 } Line { SrcBlock "Det OFDM" SrcPort 1 Points [85, 0] Branch { DstBlock "Logical" DstPort 1 } Branch { Points [0, -215] DstBlock "Gateway Out" DstPort 1 } } Line { SrcBlock "Gateway Out" SrcPort 1 DstBlock "AGC Ctrl" DstPort 1 } Line { SrcBlock "Gateway Out1" SrcPort 1 DstBlock "AGC Ctrl" DstPort 2 } Line { SrcBlock "Det DSSS" SrcPort 1 Points [80, 0] Branch { DstBlock "Logical" DstPort 2 } Branch { Points [0, -210] DstBlock "Gateway Out1" DstPort 1 } } Annotation { Name "Pkt det output to start/reset AGC" Position [1160, 408] } } } Block { BlockType SubSystem Name "RSSI & Gain\nCapture" SID "4251" Ports [2] Position [670, 554, 765, 596] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "RSSI & Gain\nCapture" Location [202, 70, 1833, 1180] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "RSSI Vec" SID "4252" Position [575, 298, 605, 312] IconDisplay "Port number" } Block { BlockType Inport Name "LTS Corr Event" SID "18106" Position [425, 408, 455, 422] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "16MSB" SID "4253" Ports [1, 1] Position [805, 241, 835, 259] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "16" boolean_output off mode "Upper Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "30,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 18 18 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[1" "1.22 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[9.22 9.22 " "11.22 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[7.22 7.22 9.22 9.22 7.22 ],[" "1 1 1 ]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black" "');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "16MSB1" SID "4254" Ports [1, 1] Position [805, 276, 835, 294] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "16" boolean_output off mode "Upper Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "30,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 18 18 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[1" "1.22 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[9.22 9.22 " "11.22 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[7.22 7.22 9.22 9.22 7.22 ],[" "1 1 1 ]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black" "');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "16MSB2" SID "4255" Ports [1, 1] Position [805, 311, 835, 329] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "16" boolean_output off mode "Upper Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "30,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 18 18 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[1" "1.22 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[9.22 9.22 " "11.22 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[7.22 7.22 9.22 9.22 7.22 ],[" "1 1 1 ]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black" "');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "16MSB3" SID "4256" Ports [1, 1] Position [805, 346, 835, 364] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "16" boolean_output off mode "Upper Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "30,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 18 18 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[1" "1.22 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[9.22 9.22 " "11.22 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[7.22 7.22 9.22 9.22 7.22 ],[" "1 1 1 ]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black" "');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType BusSelector Name "Bus\nSelector3" SID "4257" Ports [1, 4] Position [685, 230, 690, 375] ZOrder -3 ShowName off OutputSignals "RFB_RSSI,RFA_RSSI,RFD_RSSI,RFC_RSSI" Port { PortNumber 1 Name "" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 2 Name "" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 3 Name "" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 4 Name "" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Concat" SID "4258" Ports [2, 1] Position [660, 631, 710, 669] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary poi" "nt at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "50,38,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 38 38 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 38 38 0 ]);\npatch([13.875 21.1 26.1 31.1 36.1 26.1 18.875 13.875 ],[24." "55 24.55 29.55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([18.875 26.1 21.1 13.875 18.875 ],[19.55 19.55" " 24.55 24.55 19.55 ],[0.931 0.946 0.973 ]);\npatch([13.875 21.1 26.1 18.875 13.875 ],[14.55 14.55 19.55 19.55 1" "4.55 ],[1 1 1 ]);\npatch([18.875 36.1 31.1 26.1 21.1 13.875 18.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolo" "r('black');port_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fo" "ntsize{20}\\}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Concat1" SID "4259" Ports [8, 1] Position [940, 505, 990, 655] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary poi" "nt at zero." num_inputs "8" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "50,150,8,1,white,blue,0,6fe74153,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 150 150 0 ],[0.77" " 0.82 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 150 150 0 ]);\npatch([9.425 19.54 26.54 33.54 40.54 26.54 16.425 9.425" " ],[82.77 82.77 89.77 82.77 89.77 89.77 89.77 82.77 ],[1 1 1 ]);\npatch([16.425 26.54 19.54 9.425 16.425 ],[75." "77 75.77 82.77 82.77 75.77 ],[0.931 0.946 0.973 ]);\npatch([9.425 19.54 26.54 16.425 9.425 ],[68.77 68.77 75.77" " 75.77 68.77 ],[1 1 1 ]);\npatch([16.425 40.54 33.54 26.54 19.54 9.425 16.425 ],[61.77 61.77 68.77 61.77 68.77 " "68.77 61.77 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin ico" "n text');\ncolor('black');port_label('input',1,'hi');\n\n\n\n\n\n\ncolor('black');port_label('input',8,'lo');\n" "\ncolor('black');disp('\\fontsize{20}\\}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Concat2" SID "4260" Ports [2, 1] Position [945, 233, 980, 302] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary poi" "nt at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "35,69,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 69 69 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 69 69 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[39.55" " 39.55 44.55 39.55 44.55 44.55 44.55 39.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[34.55 34.55 39" ".55 39.55 34.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[29.55 29.55 34.55 34.55 29.55 " "],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[24.55 24.55 29.55 24.55 29.55 29.55 24.55 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor(" "'black');port_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\font" "size{20}\\}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Concat3" SID "4261" Ports [2, 1] Position [660, 591, 710, 629] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary poi" "nt at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "50,38,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 38 38 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 38 38 0 ]);\npatch([13.875 21.1 26.1 31.1 36.1 26.1 18.875 13.875 ],[24." "55 24.55 29.55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([18.875 26.1 21.1 13.875 18.875 ],[19.55 19.55" " 24.55 24.55 19.55 ],[0.931 0.946 0.973 ]);\npatch([13.875 21.1 26.1 18.875 13.875 ],[14.55 14.55 19.55 19.55 1" "4.55 ],[1 1 1 ]);\npatch([18.875 36.1 31.1 26.1 21.1 13.875 18.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolo" "r('black');port_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fo" "ntsize{20}\\}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Concat4" SID "4262" Ports [2, 1] Position [945, 303, 980, 372] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary poi" "nt at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "35,69,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 69 69 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 69 69 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[39.55" " 39.55 44.55 39.55 44.55 44.55 44.55 39.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[34.55 34.55 39" ".55 39.55 34.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[29.55 29.55 34.55 34.55 29.55 " "],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[24.55 24.55 29.55 24.55 29.55 29.55 24.55 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor(" "'black');port_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\font" "size{20}\\}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Concat6" SID "4263" Ports [2, 1] Position [660, 551, 710, 589] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary poi" "nt at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "50,38,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 38 38 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 38 38 0 ]);\npatch([13.875 21.1 26.1 31.1 36.1 26.1 18.875 13.875 ],[24." "55 24.55 29.55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([18.875 26.1 21.1 13.875 18.875 ],[19.55 19.55" " 24.55 24.55 19.55 ],[0.931 0.946 0.973 ]);\npatch([13.875 21.1 26.1 18.875 13.875 ],[14.55 14.55 19.55 19.55 1" "4.55 ],[1 1 1 ]);\npatch([18.875 36.1 31.1 26.1 21.1 13.875 18.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolo" "r('black');port_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fo" "ntsize{20}\\}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Concat7" SID "4264" Ports [2, 1] Position [660, 511, 710, 549] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary poi" "nt at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "50,38,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 38 38 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 38 38 0 ]);\npatch([13.875 21.1 26.1 31.1 36.1 26.1 18.875 13.875 ],[24." "55 24.55 29.55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([18.875 26.1 21.1 13.875 18.875 ],[19.55 19.55" " 24.55 24.55 19.55 ],[0.931 0.946 0.973 ]);\npatch([13.875 21.1 26.1 18.875 13.875 ],[14.55 14.55 19.55 19.55 1" "4.55 ],[1 1 1 ]);\npatch([18.875 36.1 31.1 26.1 21.1 13.875 18.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolo" "r('black');port_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fo" "ntsize{20}\\}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant1" SID "4265" Ports [0, 1] Position [875, 621, 890, 639] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "15,18,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 " "9.22 ],[0.931 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch(" "[4.55 11.44 9.44 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf(''" ",'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1," "'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "4267" Position [460, 630, 575, 650] ZOrder -9 ShowName off GotoTag "RFA_AGC_G_RF" TagVisibility "global" } Block { BlockType From Name "From1" SID "4268" Position [460, 486, 590, 504] ShowName off CloseFcn "tagdialog Close" GotoTag "AGC_DONE" TagVisibility "global" } Block { BlockType From Name "From2" SID "4269" Position [460, 650, 575, 670] ZOrder -9 ShowName off GotoTag "RFA_AGC_G_BB" TagVisibility "global" } Block { BlockType From Name "From3" SID "4270" Position [460, 590, 575, 610] ZOrder -9 ShowName off GotoTag "RFB_AGC_G_RF" TagVisibility "global" } Block { BlockType From Name "From4" SID "4271" Position [460, 610, 575, 630] ZOrder -9 ShowName off GotoTag "RFB_AGC_G_BB" TagVisibility "global" } Block { BlockType From Name "From5" SID "18108" Position [270, 425, 470, 445] ShowName off CloseFcn "tagdialog Close" GotoTag "RX_START_DSSS_SIGNAL_VALID" TagVisibility "global" } Block { BlockType From Name "From6" SID "4272" Position [460, 510, 575, 530] ZOrder -9 ShowName off GotoTag "RFD_AGC_G_RF" TagVisibility "global" } Block { BlockType From Name "From7" SID "4273" Position [460, 530, 575, 550] ZOrder -9 ShowName off GotoTag "RFD_AGC_G_BB" TagVisibility "global" } Block { BlockType From Name "From8" SID "4274" Position [460, 550, 575, 570] ZOrder -9 ShowName off GotoTag "RFC_AGC_G_RF" TagVisibility "global" } Block { BlockType From Name "From9" SID "4275" Position [460, 570, 575, 590] ZOrder -9 ShowName off GotoTag "RFC_AGC_G_BB" TagVisibility "global" } Block { BlockType Goto Name "Goto2" SID "4276" Position [1400, 343, 1540, 367] ZOrder -10 ShowName off GotoTag "RSSI_POST_AGC_CD" TagVisibility "global" } Block { BlockType Goto Name "Goto4" SID "4277" Position [1400, 273, 1540, 297] ZOrder -10 ShowName off GotoTag "RSSI_POST_AGC_AB" TagVisibility "global" } Block { BlockType Goto Name "Goto5" SID "4278" Position [1410, 583, 1550, 607] ZOrder -10 ShowName off GotoTag "GAINS_POST_AGC" TagVisibility "global" } Block { BlockType Reference Name "Logical" SID "18109" Ports [2, 1] Position [630, 404, 670, 451] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,47,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 47 47 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 47 47 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[28.55" " 28.55 33.55 28.55 33.55 33.55 33.55 28.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[23.55 23.55 28" ".55 28.55 23.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[18.55 18.55 23.55 23.55 18.55 " "],[1 1 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[13.55 13.55 18.55 13.55 18.55 18.55 13.55 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n" "color('black');disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Posedge1" SID "4279" Ports [1, 1] Position [825, 423, 860, 437] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Posedge1" Location [202, 70, 1833, 1180] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "4280" Position [200, 253, 230, 267] IconDisplay "Port number" } Block { BlockType Reference Name "Delay" SID "4281" Ports [1, 1] Position [425, 153, 460, 177] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. If r" "egister retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[15.33 15" ".33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.33 12.33 15.33" " 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 " "1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');" "disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "4282" Ports [1, 1] Position [490, 156, 515, 174] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "4283" Ports [2, 1] Position [540, 151, 585, 204] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,53,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 53 53 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 53 53 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[32.66 32.66 3" "8.66 32.66 38.66 38.66 38.66 32.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[26.66 26.66 32.66 32.66 26" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[20.66 20.66 26.66 26.66 20.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[14.66 14.66 20.66 14.66 20.66 20.66 14.66 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('" "and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "4284" Position [610, 173, 640, 187] IconDisplay "Port number" } Line { SrcBlock "Delay" SrcPort 1 DstBlock "Inverter" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "D" SrcPort 1 Points [150, 0; 0, -70] Branch { Points [0, -25] DstBlock "Delay" DstPort 1 } Branch { DstBlock "Logical1" DstPort 2 } } Annotation { Name "Rising Edge Detection" Position [500, 112] } } } Block { BlockType Reference Name "Register1" SID "4285" Ports [2, 1] Position [1155, 257, 1205, 308] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "50,51,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 51 51 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 51 51 0 ]);\npatch([9.425 19.54 26.54 33.54 40.54 26.54 16.425 9.425 ],[" "32.77 32.77 39.77 32.77 39.77 39.77 39.77 32.77 ],[1 1 1 ]);\npatch([16.425 26.54 19.54 9.425 16.425 ],[25.77 2" "5.77 32.77 32.77 25.77 ],[0.931 0.946 0.973 ]);\npatch([9.425 19.54 26.54 16.425 9.425 ],[18.77 18.77 25.77 25." "77 18.77 ],[1 1 1 ]);\npatch([16.425 40.54 33.54 26.54 19.54 9.425 16.425 ],[11.77 11.77 18.77 11.77 18.77 18.7" "7 11.77 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon te" "xt');\ncolor('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');po" "rt_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register10" SID "18111" Ports [1, 1] Position [540, 400, 570, 430] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 30 30 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 30 30 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 " "19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 1" "9.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register11" SID "18112" Ports [1, 1] Position [540, 420, 570, 450] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 30 30 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 30 30 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 " "19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 1" "9.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "4286" Ports [2, 1] Position [1160, 567, 1210, 618] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "50,51,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 51 51 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 51 51 0 ]);\npatch([9.425 19.54 26.54 33.54 40.54 26.54 16.425 9.425 ],[" "32.77 32.77 39.77 32.77 39.77 39.77 39.77 32.77 ],[1 1 1 ]);\npatch([16.425 26.54 19.54 9.425 16.425 ],[25.77 2" "5.77 32.77 32.77 25.77 ],[0.931 0.946 0.973 ]);\npatch([9.425 19.54 26.54 16.425 9.425 ],[18.77 18.77 25.77 25." "77 18.77 ],[1 1 1 ]);\npatch([16.425 40.54 33.54 26.54 19.54 9.425 16.425 ],[11.77 11.77 18.77 11.77 18.77 18.7" "7 11.77 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon te" "xt');\ncolor('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');po" "rt_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register3" SID "4287" Ports [1, 1] Position [1265, 270, 1295, 300] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 30 30 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 30 30 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 " "19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 1" "9.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register4" SID "4288" Ports [2, 1] Position [1155, 327, 1205, 378] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "50,51,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 51 51 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 51 51 0 ]);\npatch([9.425 19.54 26.54 33.54 40.54 26.54 16.425 9.425 ],[" "32.77 32.77 39.77 32.77 39.77 39.77 39.77 32.77 ],[1 1 1 ]);\npatch([16.425 26.54 19.54 9.425 16.425 ],[25.77 2" "5.77 32.77 32.77 25.77 ],[0.931 0.946 0.973 ]);\npatch([9.425 19.54 26.54 16.425 9.425 ],[18.77 18.77 25.77 25." "77 18.77 ],[1 1 1 ]);\npatch([16.425 40.54 33.54 26.54 19.54 9.425 16.425 ],[11.77 11.77 18.77 11.77 18.77 18.7" "7 11.77 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon te" "xt');\ncolor('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');po" "rt_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register5" SID "4289" Ports [1, 1] Position [1265, 340, 1295, 370] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 30 30 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 30 30 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 " "19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 1" "9.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register6" SID "4290" Ports [1, 1] Position [1255, 580, 1285, 610] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 30 30 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 30 30 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 " "19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 1" "9.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register7" SID "4291" Ports [1, 1] Position [1325, 580, 1355, 610] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 30 30 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 30 30 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 " "19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 1" "9.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register8" SID "4292" Ports [1, 1] Position [1330, 340, 1360, 370] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 30 30 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 30 30 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 " "19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 1" "9.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register9" SID "4293" Ports [1, 1] Position [1325, 270, 1355, 300] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 30 30 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 30 30 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 " "19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 1" "9.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Up Sample" SID "4294" Ports [1, 1] Position [1040, 258, 1070, 282] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Up Sample" SourceType "Xilinx Up Sampler Block" infoedit "Up samples input data. Inserted values can be zeros or copies of the most recent input sampl" "e.

Hardware notes: No hardware is needed if inserted values are copies of the input sample; otherwise, a" " mux and single bit flip-flop are used." sample_ratio "16" copy_samples on en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "usamp" sg_icon_stat "30,24,1,1,white,blue,0,2d01a39a,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 24 24 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 24 24 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[" "15.33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[12.33 1" "2.33 15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[9.33 9.33 12.33 12.33" " 9.33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ]," "[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n" "color('black');disp('{\\fontsize{14pt}\\bf\\uparrow}16','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Up Sample1" SID "4295" Ports [1, 1] Position [1040, 328, 1070, 352] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Up Sample" SourceType "Xilinx Up Sampler Block" infoedit "Up samples input data. Inserted values can be zeros or copies of the most recent input sampl" "e.

Hardware notes: No hardware is needed if inserted values are copies of the input sample; otherwise, a" " mux and single bit flip-flop are used." sample_ratio "16" copy_samples on en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "usamp" sg_icon_stat "30,24,1,1,white,blue,0,2d01a39a,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 24 24 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 24 24 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[" "15.33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[12.33 1" "2.33 15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[9.33 9.33 12.33 12.33" " 9.33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ]," "[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n" "color('black');disp('{\\fontsize{14pt}\\bf\\uparrow}16','texmode','on');\nfprintf('','COMMENT: end icon text');" } Line { SrcBlock "From2" SrcPort 1 DstBlock "Concat" DstPort 2 } Line { SrcBlock "Register4" SrcPort 1 DstBlock "Register5" DstPort 1 } Line { SrcBlock "Up Sample1" SrcPort 1 DstBlock "Register4" DstPort 1 } Line { SrcBlock "Concat4" SrcPort 1 DstBlock "Up Sample1" DstPort 1 } Line { SrcBlock "Concat6" SrcPort 1 DstBlock "Concat1" DstPort 4 } Line { SrcBlock "Concat7" SrcPort 1 DstBlock "Concat1" DstPort 2 } Line { SrcBlock "From6" SrcPort 1 DstBlock "Concat7" DstPort 1 } Line { SrcBlock "From7" SrcPort 1 DstBlock "Concat7" DstPort 2 } Line { SrcBlock "From9" SrcPort 1 DstBlock "Concat6" DstPort 2 } Line { SrcBlock "From8" SrcPort 1 DstBlock "Concat6" DstPort 1 } Line { SrcBlock "Concat3" SrcPort 1 DstBlock "Concat1" DstPort 6 } Line { SrcBlock "Concat" SrcPort 1 DstBlock "Concat1" DstPort 8 } Line { SrcBlock "Constant1" SrcPort 1 Points [20, 0] Branch { Points [0, -40] Branch { Points [0, -40] DstBlock "Concat1" DstPort 3 } Branch { DstBlock "Concat1" DstPort 5 } } Branch { DstBlock "Concat1" DstPort 7 } } Line { SrcBlock "From3" SrcPort 1 DstBlock "Concat3" DstPort 1 } Line { SrcBlock "From4" SrcPort 1 DstBlock "Concat3" DstPort 2 } Line { SrcBlock "From" SrcPort 1 DstBlock "Concat" DstPort 1 } Line { SrcBlock "Posedge1" SrcPort 1 Points [255, 0] Branch { Points [0, -65] Branch { Points [0, -70] DstBlock "Register1" DstPort 2 } Branch { DstBlock "Register4" DstPort 2 } } Branch { Points [0, 175] DstBlock "Register2" DstPort 2 } } Line { SrcBlock "Logical" SrcPort 1 DstBlock "Posedge1" DstPort 1 } Line { SrcBlock "16MSB1" SrcPort 1 DstBlock "Concat2" DstPort 2 } Line { SrcBlock "16MSB" SrcPort 1 DstBlock "Concat2" DstPort 1 } Line { SrcBlock "Up Sample" SrcPort 1 DstBlock "Register1" DstPort 1 } Line { SrcBlock "Concat2" SrcPort 1 DstBlock "Up Sample" DstPort 1 } Line { SrcBlock "Register1" SrcPort 1 DstBlock "Register3" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Register6" DstPort 1 } Line { SrcBlock "Concat1" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "RSSI Vec" SrcPort 1 DstBlock "Bus\nSelector3" DstPort 1 } Line { SrcBlock "16MSB2" SrcPort 1 DstBlock "Concat4" DstPort 1 } Line { SrcBlock "16MSB3" SrcPort 1 DstBlock "Concat4" DstPort 2 } Line { Name "" Labels [0, 0] SrcBlock "Bus\nSelector3" SrcPort 1 DstBlock "16MSB" DstPort 1 } Line { Name "" Labels [0, 0] SrcBlock "Bus\nSelector3" SrcPort 2 DstBlock "16MSB1" DstPort 1 } Line { Name "" Labels [0, 0] SrcBlock "Bus\nSelector3" SrcPort 3 DstBlock "16MSB2" DstPort 1 } Line { Name "" Labels [0, 0] SrcBlock "Bus\nSelector3" SrcPort 4 DstBlock "16MSB3" DstPort 1 } Line { SrcBlock "Register3" SrcPort 1 DstBlock "Register9" DstPort 1 } Line { SrcBlock "Register5" SrcPort 1 DstBlock "Register8" DstPort 1 } Line { SrcBlock "Register6" SrcPort 1 DstBlock "Register7" DstPort 1 } Line { SrcBlock "Register7" SrcPort 1 DstBlock "Goto5" DstPort 1 } Line { SrcBlock "Register8" SrcPort 1 DstBlock "Goto2" DstPort 1 } Line { SrcBlock "Register9" SrcPort 1 DstBlock "Goto4" DstPort 1 } Line { SrcBlock "From1" SrcPort 1 Points [175, 0; 0, 15] DstBlock "Concat1" DstPort 1 } Line { SrcBlock "LTS Corr Event" SrcPort 1 DstBlock "Register10" DstPort 1 } Line { SrcBlock "From5" SrcPort 1 DstBlock "Register11" DstPort 1 } Line { SrcBlock "Register10" SrcPort 1 DstBlock "Logical" DstPort 1 } Line { SrcBlock "Register11" SrcPort 1 DstBlock "Logical" DstPort 2 } Annotation { Name "Capture RSSI after AGC has settled\n(avoids saturating RSSI when G_RF=3 and Rx power is high)\nSof" "tware must compensate for RF gain selection when\ninterpretting thse RSSI values." Position [1384, 215] } Annotation { Name "Capture gains for all antennas\nafter AGC has settled." Position [1499, 560] } } } Block { BlockType SubSystem Name "Resets" SID "8387" Ports [3, 2] Position [225, 213, 345, 277] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Resets" Location [97, 411, 797, 1188] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "OFDM Reset" SID "8388" Position [240, 273, 270, 287] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "DSSS Reset " SID "8389" Position [710, 113, 740, 127] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "LTS Timeout" SID "8390" Position [690, 348, 720, 362] NamePlacement "alternate" Port "3" IconDisplay "Port number" } Block { BlockType Constant Name "Constant1" SID "8391" Position [465, 414, 490, 436] ZOrder -5 ShowName off Value "0" } Block { BlockType From Name "From1" SID "8392" Position [565, 381, 695, 399] ShowName off CloseFcn "tagdialog Close" GotoTag "RX_GLOBAL_RESET" TagVisibility "global" } Block { BlockType From Name "From16" SID "8393" Position [265, 232, 480, 248] ShowName off CloseFcn "tagdialog Close" GotoTag "regRx_rateLength_holds_pktDet" TagVisibility "global" } Block { BlockType From Name "From2" SID "8394" Position [670, 688, 870, 702] ShowName off CloseFcn "tagdialog Close" GotoTag "RX_STARTED_TO_MAC" TagVisibility "global" } Block { BlockType From Name "From3" SID "8395" Position [75, 308, 275, 322] ZOrder -9 ShowName off GotoTag "RX_PHY_RATE_LENGTH_ACTIVE" TagVisibility "global" } Block { BlockType From Name "From4" SID "16609" Position [235, 473, 385, 497] ShowName off CloseFcn "tagdialog Close" GotoTag "regRx_DISABLE_OFDM" TagVisibility "global" } Block { BlockType From Name "From5" SID "18016" Position [580, 143, 730, 167] ShowName off CloseFcn "tagdialog Close" GotoTag "DSSS_SYNC_PktDet_Block" TagVisibility "global" } Block { BlockType From Name "From6" SID "18022" Position [465, 588, 615, 612] ShowName off CloseFcn "tagdialog Close" GotoTag "DSSS_SYNC_PktDet_Block" TagVisibility "global" } Block { BlockType From Name "From7" SID "18150" Position [235, 503, 435, 517] ShowName off CloseFcn "tagdialog Close" GotoTag "RX_STARTED_TO_MAC" TagVisibility "global" } Block { BlockType Goto Name "Goto3" SID "10298" Position [1015, 676, 1225, 694] ZOrder -10 ShowName off GotoTag "RX_RESET_WHILE_ACTIVE" TagVisibility "global" } Block { BlockType Reference Name "Inverter1" SID "18151" Ports [1, 1] Position [485, 501, 515, 519] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "30,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 18 18 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[1" "1.22 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[9.22 9.22 " "11.22 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[7.22 7.22 9.22 9.22 7.22 ],[" "1 1 1 ]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('bla" "ck');disp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter4" SID "8398" Ports [1, 1] Position [335, 306, 365, 324] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "30,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 18 18 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[1" "1.22 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[9.22 9.22 " "11.22 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[7.22 7.22 9.22 9.22 7.22 ],[" "1 1 1 ]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('bla" "ck');disp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "8399" Ports [2, 1] Position [915, 655, 955, 710] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,55,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 55 55 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 55 55 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[32.55" " 32.55 37.55 32.55 37.55 37.55 37.55 32.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[27.55 27.55 32" ".55 32.55 27.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[22.55 22.55 27.55 27.55 22.55 " "],[1 1 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[17.55 17.55 22.55 17.55 22.55 22.55 17.55 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n" "color('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "8400" Ports [6, 1] Position [810, 306, 860, 509] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "6" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "50,203,6,1,white,blue,0,31bf5775,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 203 203 0 ],[0.77" " 0.82 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 203 203 0 ]);\npatch([9.425 19.54 26.54 33.54 40.54 26.54 16.425 9.425" " ],[108.77 108.77 115.77 108.77 115.77 115.77 115.77 108.77 ],[1 1 1 ]);\npatch([16.425 26.54 19.54 9.425 16.42" "5 ],[101.77 101.77 108.77 108.77 101.77 ],[0.931 0.946 0.973 ]);\npatch([9.425 19.54 26.54 16.425 9.425 ],[94.7" "7 94.77 101.77 101.77 94.77 ],[1 1 1 ]);\npatch([16.425 40.54 33.54 26.54 19.54 9.425 16.425 ],[87.77 87.77 94." "77 87.77 94.77 94.77 87.77 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COM" "MENT: begin icon text');\n\n\n\n\n\n\n\ncolor('black');disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical3" SID "8401" Ports [2, 1] Position [800, 654, 840, 681] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,27,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 27 27 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 27 27 0 ]);\npatch([13.325 17.66 20.66 23.66 26.66 20.66 16.325 13.325 ]" ",[16.33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([16.325 20.66 17.66 13.325 16.325 ],[13.3" "3 13.33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([13.325 17.66 20.66 16.325 13.325 ],[10.33 10.33 13.3" "3 13.33 10.33 ],[1 1 1 ]);\npatch([16.325 26.66 23.66 20.66 17.66 13.325 16.325 ],[7.33 7.33 10.33 7.33 10.33 1" "0.33 7.33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon " "text');\n\n\n\ncolor('black');disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical4" SID "8402" Ports [4, 1] Position [810, 105, 855, 240] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "4" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "45,135,4,1,white,blue,0,4f3eee2e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 135 135 0 ],[0.77" " 0.82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 135 135 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ]," "[73.66 73.66 79.66 73.66 79.66 79.66 79.66 73.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[67.66 67." "66 73.66 73.66 67.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[61.66 61.66 67.66 67.66 61" ".66 ],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[55.66 55.66 61.66 55.66 61.66 61.66 55.66 " "],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n" "\n\n\n\ncolor('black');disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical5" SID "8403" Ports [2, 1] Position [500, 300, 535, 335] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,35,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 35 35 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 35 35 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[22.55" " 22.55 27.55 22.55 27.55 27.55 27.55 22.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[17.55 17.55 22" ".55 22.55 17.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[12.55 12.55 17.55 17.55 12.55 " "],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[7.55 7.55 12.55 7.55 12.55 12.55 7.55 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolo" "r('black');disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical6" SID "8404" Ports [2, 1] Position [410, 290, 445, 325] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,35,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 35 35 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 35 35 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[22.55" " 22.55 27.55 22.55 27.55 27.55 27.55 22.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[17.55 17.55 22" ".55 22.55 17.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[12.55 12.55 17.55 17.55 12.55 " "],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[7.55 7.55 12.55 7.55 12.55 12.55 7.55 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolo" "r('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical7" SID "18149" Ports [2, 1] Position [565, 470, 605, 525] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,55,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 55 55 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 55 55 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[32.55" " 32.55 37.55 32.55 37.55 37.55 37.55 32.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[27.55 27.55 32" ".55 32.55 27.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[22.55 22.55 27.55 27.55 22.55 " "],[1 1 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[17.55 17.55 22.55 17.55 22.55 22.55 17.55 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n" "color('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux" SID "8405" Ports [3, 1] Position [580, 218, 610, 342] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "30,124,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 17.7143 106.286 124" " 0 ],[0.77 0.82 0.91 ]);\nplot([0 30 30 0 0 ],[0 17.7143 106.286 124 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 " "15.88 10.1 6.1 ],[66.44 66.44 70.44 66.44 70.44 70.44 70.44 66.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10." "1 ],[62.44 62.44 66.44 66.44 62.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[58.44 58.44 62." "44 62.44 58.44 ],[1 1 1 ]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[54.44 54.44 58.44 54.44 58.44 58.4" "4 54.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon te" "xt');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');" "port_label('input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" } Block { BlockType SubSystem Name "Negedge" SID "8406" Ports [1, 1] Position [335, 337, 375, 353] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Negedge" Location [88, 301, 2330, 1301] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "8407" Position [200, 253, 230, 267] IconDisplay "Port number" } Block { BlockType Reference Name "Delay" SID "8408" Ports [1, 1] Position [425, 153, 460, 177] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. If r" "egister retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[15.33 15" ".33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.33 12.33 15.33" " 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 " "1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');" "disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "8409" Ports [1, 1] Position [490, 181, 515, 199] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "8410" Ports [2, 1] Position [540, 151, 585, 204] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,53,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 53 53 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 53 53 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[32.66 32.66 3" "8.66 32.66 38.66 38.66 38.66 32.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[26.66 26.66 32.66 32.66 26" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[20.66 20.66 26.66 26.66 20.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[14.66 14.66 20.66 14.66 20.66 20.66 14.66 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('" "and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "8411" Position [610, 173, 640, 187] IconDisplay "Port number" } Line { SrcBlock "D" SrcPort 1 Points [150, 0; 0, -70] Branch { Points [0, -25] DstBlock "Delay" DstPort 1 } Branch { DstBlock "Inverter" DstPort 1 } } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "Delay" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical1" DstPort 2 } } } Block { BlockType Reference Name "PHY_RX_RESET" SID "8412" Ports [1, 1] Position [555, 415, 620, 435] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to" " Xilinx fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top l" "evel input ports." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "16" bin_pt "14" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[1" "2.22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.2" "2 12.22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.2" "2 ],[1 1 1 ]);\npatch([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985" " 0.979 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' " "');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register3" SID "8413" Ports [1, 1] Position [660, 410, 685, 440] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 30 30 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 30 30 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[18" ".33 18.33 21.33 18.33 21.33 21.33 21.33 18.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[15.33 15.33 " "18.33 18.33 15.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[12.33 12.33 15.33 15.33 12.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[9.33 9.33 12.33 9.33 12.33 12.33 9.33 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Reset Gen" SID "8414" Ports [1, 1] Position [960, 393, 1025, 427] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Reset Gen" Location [280, 193, 2120, 1196] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "132" Block { BlockType Inport Name "Done" SID "8415" Position [265, 423, 295, 437] IconDisplay "Port number" } Block { BlockType Reference Name "Concat" SID "8416" Ports [2, 1] Position [575, 503, 600, 552] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point at z" "ero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "25,49,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 49 49 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 49 49 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[27.33 27.33 " "30.33 27.33 30.33 30.33 30.33 27.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[24.33 24.33 27.33 27.33 2" "4.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[21.33 21.33 24.33 24.33 21.33 ],[1 1 1 ]);\n" "patch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[18.33 18.33 21.33 18.33 21.33 21.33 18.33 ],[0.931 0.946 0.973 " "]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label" "('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fontsize{20}\\}','texmode'" ",'on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant" SID "8417" Ports [0, 1] Position [505, 530, 525, 550] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "4" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "20,20,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 20 20 0 0 ],[0 0 20 20 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[12.22 12.22 14." "22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[10.22 10.22 12.22 12.22 10.22 ]" ",[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatch([7.55 " "14.44 12.44 10.44 8.44 5.55 7.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'0');\nfpr" "intf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Counter1" SID "8418" Ports [2, 1] Position [630, 329, 665, 391] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited counter i" "s implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "Inf" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "10" bin_pt "0" load_pin off rst on en on explicit_period "off" period "4" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,619" block_type "counter" block_version "10.1.3" sg_icon_stat "35,62,2,1,white,blue,0,ae3608d6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 62 62 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 62 62 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[36.55 36.55 41." "55 36.55 41.55 41.55 41.55 36.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[31.55 31.55 36.55 36.55 31." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[26.55 26.55 31.55 31.55 26.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[21.55 21.55 26.55 21.55 26.55 26.55 21.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i" "nput',1,'rst');\ncolor('black');port_label('input',2,'en');\n\ncolor('black');disp('{\\fontsize{14}\\bf++}','texmo" "de','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From2" SID "8419" Position [145, 506, 355, 524] ShowName off CloseFcn "tagdialog Close" GotoTag "regRx_PKT_DET_RESET_EXT_DUR" TagVisibility "global" } Block { BlockType Reference Name "Inverter" SID "8420" Ports [1, 1] Position [575, 336, 600, 354] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "8421" Ports [3, 1] Position [870, 420, 910, 460] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,40,3,1,white,blue,0,a2abe52d,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25.55 30." "55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 25.55 20." "55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1 1 ]);\npa" "tch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\ncolor('black');disp(" "'or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register" SID "8422" Ports [1, 1] Position [425, 500, 455, 530] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 30 30 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 19.44 23.4" "4 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 19.44 15.44 ]," "[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([10.1" " 23.88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\n" "color('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: en" "d icon text');" } Block { BlockType Reference Name "Relational3" SID "8423" Ports [2, 1] Position [775, 348, 820, 392] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a>b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "500,165,356,193" block_type "relational" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,2,1,white,blue,0,b5131c97,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 28.66 3" "4.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 28.66 22" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('" "input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa > b','texmo" "de','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "S-R Latch2" SID "8424" Ports [2, 1] Position [500, 358, 535, 387] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "S-R Latch2" Location [426, 211, 2266, 1214] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "8425" Position [140, 103, 170, 117] IconDisplay "Port number" } Block { BlockType Inport Name "R" SID "8426" Position [140, 88, 170, 102] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "8427" Ports [0, 1] Position [195, 71, 210, 89] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "15,18,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11.22 " "13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 9.22 " "],[0.931 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([4.55 " "11.44 9.44 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "8428" Ports [1, 1] Position [210, 86, 235, 104] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('outpu" "t',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "8429" Ports [1, 1] Position [210, 101, 235, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('outpu" "t',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "8430" Ports [3, 1] Position [255, 71, 300, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "8431" Position [325, 88, 355, 102] IconDisplay "Port number" } Line { SrcBlock "Convert2" SrcPort 1 DstBlock "Register2" DstPort 3 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "S" SrcPort 1 DstBlock "Convert2" DstPort 1 } } } Block { BlockType SubSystem Name "negedge" SID "8432" Ports [1, 1] Position [395, 356, 440, 374] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "negedge" Location [88, 301, 2330, 1301] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "8433" Position [275, 183, 305, 197] IconDisplay "Port number" } Block { BlockType Reference Name "Delay" SID "8434" Ports [1, 1] Position [425, 153, 460, 177] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. " "If register retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[15" ".33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.33 12." "33 15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 12.33 " "9.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\nc" "olor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "8435" Ports [1, 1] Position [495, 181, 520, 199] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "8436" Ports [2, 1] Position [540, 151, 585, 204] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,53,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 53 53 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 53 53 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[32.66 3" "2.66 38.66 32.66 38.66 38.66 38.66 32.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[26.66 26.66 32.66 " "32.66 26.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[20.66 20.66 26.66 26.66 20.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[14.66 14.66 20.66 14.66 20.66 20.66 14.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('" "black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "8437" Position [610, 173, 640, 187] IconDisplay "Port number" } Line { SrcBlock "Delay" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "D" SrcPort 1 Points [75, 0] Branch { Points [0, -25] DstBlock "Delay" DstPort 1 } Branch { DstBlock "Inverter" DstPort 1 } } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical1" DstPort 2 } } } Block { BlockType Outport Name "Reset" SID "8438" Position [970, 433, 1000, 447] IconDisplay "Port number" } Line { SrcBlock "Done" SrcPort 1 Points [60, 0] Branch { Points [0, 10] DstBlock "Logical2" DstPort 2 } Branch { Points [0, -65] DstBlock "negedge" DstPort 1 } } Line { SrcBlock "negedge" SrcPort 1 Points [10, 0] Branch { DstBlock "S-R Latch2" DstPort 1 } Branch { Points [0, 90] DstBlock "Logical2" DstPort 3 } } Line { SrcBlock "S-R Latch2" SrcPort 1 Points [10, 0] Branch { Points [50, 0] Branch { DstBlock "Counter1" DstPort 2 } Branch { Points [0, 50] DstBlock "Logical2" DstPort 1 } } Branch { Points [0, -30] DstBlock "Inverter" DstPort 1 } } Line { SrcBlock "Counter1" SrcPort 1 DstBlock "Relational3" DstPort 1 } Line { SrcBlock "Relational3" SrcPort 1 Points [80, 0; 0, -70; -430, 0; 0, 80] DstBlock "S-R Latch2" DstPort 2 } Line { SrcBlock "Logical2" SrcPort 1 DstBlock "Reset" DstPort 1 } Line { SrcBlock "Concat" SrcPort 1 Points [145, 0; 0, -145] DstBlock "Relational3" DstPort 2 } Line { SrcBlock "Constant" SrcPort 1 DstBlock "Concat" DstPort 2 } Line { SrcBlock "From2" SrcPort 1 DstBlock "Register" DstPort 1 } Line { SrcBlock "Register" SrcPort 1 DstBlock "Concat" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Counter1" DstPort 1 } Annotation { Name "Extend pkt det reset by programmable\nduration, to avoid false positives after\nactual receptions due to" " Rx transients\nduring AGC reset" Position [354, 194] } } } Block { BlockType SubSystem Name "Reset Gen1" SID "8439" Ports [1, 1] Position [960, 158, 1025, 192] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Reset Gen1" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "132" Block { BlockType Inport Name "Done" SID "8440" Position [265, 423, 295, 437] IconDisplay "Port number" } Block { BlockType Reference Name "Concat" SID "8441" Ports [2, 1] Position [575, 503, 600, 552] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point at z" "ero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "25,49,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 49 49 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 49 49 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[27.33 27.33 " "30.33 27.33 30.33 30.33 30.33 27.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[24.33 24.33 27.33 27.33 2" "4.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[21.33 21.33 24.33 24.33 21.33 ],[1 1 1 ]);\n" "patch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[18.33 18.33 21.33 18.33 21.33 21.33 18.33 ],[0.931 0.946 0.973 " "]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label" "('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fontsize{20}\\}','texmode'" ",'on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant" SID "8442" Ports [0, 1] Position [505, 530, 525, 550] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "4" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "20,20,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 20 20 0 0 ],[0 0 20 20 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[12.22 12.22 14." "22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[10.22 10.22 12.22 12.22 10.22 ]" ",[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatch([7.55 " "14.44 12.44 10.44 8.44 5.55 7.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'0');\nfpr" "intf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Counter1" SID "8443" Ports [2, 1] Position [630, 329, 665, 391] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited counter i" "s implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "Inf" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "10" bin_pt "0" load_pin off rst on en on explicit_period "off" period "4" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,619" block_type "counter" block_version "10.1.3" sg_icon_stat "35,62,2,1,white,blue,0,ae3608d6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 62 62 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 62 62 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[36.55 36.55 41." "55 36.55 41.55 41.55 41.55 36.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[31.55 31.55 36.55 36.55 31." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[26.55 26.55 31.55 31.55 26.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[21.55 21.55 26.55 21.55 26.55 26.55 21.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i" "nput',1,'rst');\ncolor('black');port_label('input',2,'en');\n\ncolor('black');disp('{\\fontsize{14}\\bf++}','texmo" "de','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From2" SID "8444" Position [145, 506, 355, 524] ShowName off CloseFcn "tagdialog Close" GotoTag "regRx_PKT_DET_RESET_EXT_DUR" TagVisibility "global" } Block { BlockType Reference Name "Inverter" SID "8445" Ports [1, 1] Position [575, 336, 600, 354] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "8446" Ports [3, 1] Position [870, 420, 910, 460] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,40,3,1,white,blue,0,a2abe52d,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25.55 30." "55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 25.55 20." "55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1 1 ]);\npa" "tch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\ncolor('black');disp(" "'or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register" SID "8447" Ports [1, 1] Position [425, 500, 455, 530] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 30 30 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 19.44 23.4" "4 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 19.44 15.44 ]," "[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([10.1" " 23.88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\n" "color('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: en" "d icon text');" } Block { BlockType Reference Name "Relational3" SID "8448" Ports [2, 1] Position [775, 348, 820, 392] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a>b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "500,165,356,193" block_type "relational" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,2,1,white,blue,0,b5131c97,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 28.66 3" "4.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 28.66 22" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('" "input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa > b','texmo" "de','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "S-R Latch2" SID "8449" Ports [2, 1] Position [500, 358, 535, 387] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "S-R Latch2" Location [426, 211, 2266, 1214] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "8450" Position [140, 103, 170, 117] IconDisplay "Port number" } Block { BlockType Inport Name "R" SID "8451" Position [140, 88, 170, 102] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "8452" Ports [0, 1] Position [195, 71, 210, 89] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "15,18,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11.22 " "13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 9.22 " "],[0.931 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([4.55 " "11.44 9.44 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "8453" Ports [1, 1] Position [210, 86, 235, 104] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('outpu" "t',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "8454" Ports [1, 1] Position [210, 101, 235, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('outpu" "t',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "8455" Ports [3, 1] Position [255, 71, 300, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "8456" Position [325, 88, 355, 102] IconDisplay "Port number" } Line { SrcBlock "S" SrcPort 1 DstBlock "Convert2" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "Convert2" SrcPort 1 DstBlock "Register2" DstPort 3 } } } Block { BlockType SubSystem Name "negedge" SID "8457" Ports [1, 1] Position [395, 356, 440, 374] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "negedge" Location [88, 301, 2330, 1301] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "8458" Position [275, 183, 305, 197] IconDisplay "Port number" } Block { BlockType Reference Name "Delay" SID "8459" Ports [1, 1] Position [425, 153, 460, 177] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. " "If register retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[15" ".33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.33 12." "33 15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 12.33 " "9.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\nc" "olor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "8460" Ports [1, 1] Position [495, 181, 520, 199] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "8461" Ports [2, 1] Position [540, 151, 585, 204] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,53,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 53 53 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 53 53 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[32.66 3" "2.66 38.66 32.66 38.66 38.66 38.66 32.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[26.66 26.66 32.66 " "32.66 26.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[20.66 20.66 26.66 26.66 20.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[14.66 14.66 20.66 14.66 20.66 20.66 14.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('" "black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "8462" Position [610, 173, 640, 187] IconDisplay "Port number" } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical1" DstPort 2 } Line { SrcBlock "D" SrcPort 1 Points [75, 0] Branch { DstBlock "Inverter" DstPort 1 } Branch { Points [0, -25] DstBlock "Delay" DstPort 1 } } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "Delay" SrcPort 1 DstBlock "Logical1" DstPort 1 } } } Block { BlockType Outport Name "Reset" SID "8463" Position [970, 433, 1000, 447] IconDisplay "Port number" } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Counter1" DstPort 1 } Line { SrcBlock "Register" SrcPort 1 DstBlock "Concat" DstPort 1 } Line { SrcBlock "From2" SrcPort 1 DstBlock "Register" DstPort 1 } Line { SrcBlock "Constant" SrcPort 1 DstBlock "Concat" DstPort 2 } Line { SrcBlock "Concat" SrcPort 1 Points [145, 0; 0, -145] DstBlock "Relational3" DstPort 2 } Line { SrcBlock "Logical2" SrcPort 1 DstBlock "Reset" DstPort 1 } Line { SrcBlock "Relational3" SrcPort 1 Points [80, 0; 0, -70; -430, 0; 0, 80] DstBlock "S-R Latch2" DstPort 2 } Line { SrcBlock "Counter1" SrcPort 1 DstBlock "Relational3" DstPort 1 } Line { SrcBlock "S-R Latch2" SrcPort 1 Points [10, 0] Branch { Points [0, -30] DstBlock "Inverter" DstPort 1 } Branch { Points [50, 0] Branch { Points [0, 50] DstBlock "Logical2" DstPort 1 } Branch { DstBlock "Counter1" DstPort 2 } } } Line { SrcBlock "negedge" SrcPort 1 Points [10, 0] Branch { Points [0, 90] DstBlock "Logical2" DstPort 3 } Branch { DstBlock "S-R Latch2" DstPort 1 } } Line { SrcBlock "Done" SrcPort 1 Points [60, 0] Branch { Points [0, -65] DstBlock "negedge" DstPort 1 } Branch { Points [0, 10] DstBlock "Logical2" DstPort 2 } } Annotation { Name "Extend pkt det reset by programmable\nduration, to avoid false positives after\nactual receptions due to" " Rx transients\nduring AGC reset" Position [354, 194] } } } Block { BlockType Outport Name " OFDM Reset" SID "8464" Position [1095, 403, 1125, 417] IconDisplay "Port number" } Block { BlockType Outport Name "DSSS Reset" SID "8465" Position [1105, 168, 1135, 182] Port "2" IconDisplay "Port number" } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Goto3" DstPort 1 } Line { SrcBlock "Logical3" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "From2" SrcPort 1 DstBlock "Logical1" DstPort 2 } Line { SrcBlock "Register3" SrcPort 1 Points [80, 0] Branch { Points [0, 235] DstBlock "Logical3" DstPort 1 } Branch { Points [0, -200] DstBlock "Logical4" DstPort 4 } Branch { DstBlock "Logical2" DstPort 4 } } Line { SrcBlock "PHY_RX_RESET" SrcPort 1 DstBlock "Register3" DstPort 1 } Line { SrcBlock "From1" SrcPort 1 Points [65, 0] Branch { Points [0, 285] DstBlock "Logical3" DstPort 2 } Branch { Points [0, -200] DstBlock "Logical4" DstPort 3 } Branch { DstBlock "Logical2" DstPort 3 } } Line { SrcBlock "Logical2" SrcPort 1 DstBlock "Reset Gen" DstPort 1 } Line { SrcBlock "Reset Gen" SrcPort 1 DstBlock " OFDM Reset" DstPort 1 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "PHY_RX_RESET" DstPort 1 } Line { SrcBlock "LTS Timeout" SrcPort 1 DstBlock "Logical2" DstPort 2 } Line { SrcBlock "Reset Gen1" SrcPort 1 DstBlock "DSSS Reset" DstPort 1 } Line { SrcBlock "Logical4" SrcPort 1 DstBlock "Reset Gen1" DstPort 1 } Line { SrcBlock "DSSS Reset " SrcPort 1 DstBlock "Logical4" DstPort 1 } Line { SrcBlock "From3" SrcPort 1 Points [30, 0] Branch { DstBlock "Inverter4" DstPort 1 } Branch { Points [0, 30] DstBlock "Negedge" DstPort 1 } } Line { SrcBlock "Inverter4" SrcPort 1 DstBlock "Logical6" DstPort 2 } Line { SrcBlock "Logical6" SrcPort 1 DstBlock "Logical5" DstPort 1 } Line { SrcBlock "Negedge" SrcPort 1 Points [105, 0] DstBlock "Logical5" DstPort 2 } Line { SrcBlock "OFDM Reset" SrcPort 1 Points [100, 0] Branch { Points [0, 20] DstBlock "Logical6" DstPort 1 } Branch { DstBlock "Mux" DstPort 2 } } Line { SrcBlock "Logical5" SrcPort 1 DstBlock "Mux" DstPort 3 } Line { SrcBlock "Mux" SrcPort 1 Points [60, 0; 0, 40] DstBlock "Logical2" DstPort 1 } Line { SrcBlock "From16" SrcPort 1 DstBlock "Mux" DstPort 1 } Line { SrcBlock "Logical7" SrcPort 1 Points [70, 0; 0, -40] DstBlock "Logical2" DstPort 5 } Line { SrcBlock "From5" SrcPort 1 DstBlock "Logical4" DstPort 2 } Line { SrcBlock "From6" SrcPort 1 Points [85, 0; 0, -105] DstBlock "Logical2" DstPort 6 } Line { SrcBlock "From7" SrcPort 1 DstBlock "Inverter1" DstPort 1 } Line { SrcBlock "From4" SrcPort 1 DstBlock "Logical7" DstPort 1 } Line { SrcBlock "Inverter1" SrcPort 1 DstBlock "Logical7" DstPort 2 } Annotation { Name "Handle rare case of a valid SIGNAL being received, sending\nRX_START to MAC, then getting reset be" "fore the pkt is processed.\nRX_START must be followed by RX_END for sane MAC state." Position [930, 738] } Annotation { Name "Wait for current Rx to finish before\nasserting OFDM reset when software\ndisables OFDM pipeline" Position [348, 543] } } } Block { BlockType Outport Name " Pkt Det DSSS" SID "8466" Position [850, 362, 880, 378] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Outport Name " Rx I" SID "8467" Position [830, 408, 860, 422] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Outport Name " Rx Q" SID "8468" Position [830, 433, 860, 447] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name " IQ Valid" SID "8469" Position [875, 458, 905, 472] Port "4" IconDisplay "Port number" } Block { BlockType Outport Name " Pkt Det OFDM" SID "8470" Position [850, 247, 880, 263] NamePlacement "alternate" Port "5" IconDisplay "Port number" } Block { BlockType Outport Name "LTS Sync" SID "8471" Position [1095, 572, 1125, 588] NamePlacement "alternate" Port "6" IconDisplay "Port number" } Line { SrcBlock "LTS Correlation" SrcPort 1 Points [40, 0] Branch { Points [0, -45; -600, 0; 0, -125] DstBlock "Pkt Det" DstPort 7 } Branch { DstBlock "Delay" DstPort 1 } } Line { SrcBlock "LTS Correlation" SrcPort 2 Points [10, 0] Branch { Points [0, 55] Branch { DstBlock "PHY CCA" DstPort 2 } Branch { Points [-795, 0; 0, -415] DstBlock "Resets" DstPort 3 } Branch { Points [0, 155] DstBlock "Debug \nOutputs" DstPort 2 } } Branch { Points [0, -565] DstBlock "Gateway Out2" DstPort 1 } } Line { Name "LTS TO" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 DstBlock "ADC/Corr" DstPort 3 } Line { Name "Pkt Done" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 DstBlock "ADC/Corr" DstPort 2 } Line { Name "Pkt Det OFDM" Labels [0, 0] SrcBlock "Gateway Out" SrcPort 1 DstBlock "ADC/Corr" DstPort 1 } Line { SrcBlock "Pkt Det" SrcPort 1 Points [15, 0] Branch { Labels [1, 0] Points [0, 160] Branch { DstBlock "Antenna Selection" DstPort 1 } Branch { Points [0, 215] Branch { Points [0, 80] Branch { DstBlock "PHY CCA" DstPort 4 } Branch { Points [0, 140] DstBlock "Debug \nOutputs" DstPort 3 } } Branch { DstBlock "LTS Correlation" DstPort 5 } } } Branch { Points [0, -225] DstBlock "Gateway Out" DstPort 1 } Branch { DstBlock " Pkt Det OFDM" DstPort 1 } } Line { SrcBlock "Resets" SrcPort 1 Points [10, 0] Branch { Points [0, 260] Branch { DstBlock "Antenna Selection" DstPort 6 } Branch { Points [0, 250] DstBlock "PHY CCA" DstPort 6 } } Branch { Points [0, -185] DstBlock "Gateway Out1" DstPort 1 } Branch { DstBlock "Pkt Det" DstPort 1 } } Line { SrcBlock "IQ Valid" SrcPort 1 Points [50, 0] Branch { DstBlock "Pkt Det" DstPort 5 } Branch { Points [0, 110] DstBlock "Antenna Selection" DstPort 4 } } Line { SrcBlock "RSSI" SrcPort 1 Points [45, 0] Branch { DstBlock "Pkt Det" DstPort 6 } Branch { Points [0, 95] Branch { DstBlock "Antenna Selection" DstPort 5 } Branch { Points [0, 90] Branch { Points [0, 160] DstBlock "PHY CCA" DstPort 5 } Branch { DstBlock "RSSI & Gain\nCapture" DstPort 1 } } } } Line { SrcBlock "Rx I" SrcPort 1 Points [60, 0] Branch { DstBlock "Pkt Det" DstPort 3 } Branch { Points [0, 140] DstBlock "Antenna Selection" DstPort 2 } } Line { SrcBlock "Rx Q" SrcPort 1 Points [55, 0] Branch { DstBlock "Pkt Det" DstPort 4 } Branch { Points [0, 125] DstBlock "Antenna Selection" DstPort 3 } } Line { SrcBlock "Antenna Selection" SrcPort 1 Points [25, 0] Branch { DstBlock " Rx I" DstPort 1 } Branch { Points [0, 155] DstBlock "LTS Correlation" DstPort 1 } } Line { SrcBlock "Antenna Selection" SrcPort 2 Points [20, 0] Branch { DstBlock " Rx Q" DstPort 1 } Branch { Points [0, 145] DstBlock "LTS Correlation" DstPort 2 } } Line { SrcBlock "Antenna Selection" SrcPort 3 Points [15, 0] Branch { Points [0, 135] Branch { Points [0, 95] DstBlock "PHY CCA" DstPort 3 } Branch { DstBlock "LTS Correlation" DstPort 3 } } Branch { DstBlock " IQ Valid" DstPort 1 } } Line { Name "Avg RSSI" SrcBlock "Antenna Selection" SrcPort 4 Points [10, 0] Branch { Labels [2, 0] Points [0, -340] DstBlock "Gateway Out3" DstPort 1 } Branch { Points [0, 125] DstBlock "LTS Correlation" DstPort 4 } } Line { SrcBlock "Gateway Out3" SrcPort 1 DstBlock "ADC/Corr" DstPort 9 } Line { SrcBlock "Pkt Det" SrcPort 3 Points [0, -15; 25, 0] Branch { Points [0, -295] DstBlock "Gateway Out4" DstPort 1 } Branch { Points [145, 0] Branch { DstBlock " Pkt Det DSSS" DstPort 1 } Branch { Points [0, -50] DstBlock "Pkt Det AGC Ctrl" DstPort 2 } } Branch { Points [0, 385] Branch { Points [0, 110] DstBlock "Debug \nOutputs" DstPort 4 } Branch { DstBlock "PHY CCA" DstPort 7 } } } Line { Name "Pkt Det DSSS" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 DstBlock "ADC/Corr" DstPort 4 } Line { SrcBlock "Resets" SrcPort 2 Points [5, 0] Branch { DstBlock "Pkt Det" DstPort 2 } Branch { Points [0, 510] DstBlock "PHY CCA" DstPort 8 } } Line { SrcBlock "From11" SrcPort 1 DstBlock "Resets" DstPort 2 } Line { SrcBlock "Reset " SrcPort 1 DstBlock "Resets" DstPort 1 } Line { SrcBlock "Delay" SrcPort 1 Points [15, 0] Branch { DstBlock "LTS Sync" DstPort 1 } Branch { Points [0, 40; -35, 0; 0, 45] Branch { Points [0, 155] DstBlock "Debug \nOutputs" DstPort 1 } Branch { Points [0, 0] Branch { DstBlock "PHY CCA" DstPort 1 } Branch { Points [-405, 0; 0, -80] DstBlock "RSSI & Gain\nCapture" DstPort 2 } } } } Line { SrcBlock "Pkt Det" SrcPort 2 Points [55, 0; 0, -20] DstBlock "Pkt Det AGC Ctrl" DstPort 1 } Annotation { Name "Delay LTS pulse so it occurs after pkt det\nin case LTF correlation is src of pkt det" Position [1101, 539] } } } Line { SrcBlock "FFT" SrcPort 1 Points [10, 0; 0, -25; -370, 0; 0, 25] DstBlock "CFO & Samp Buffer" DstPort 1 } Line { SrcBlock "CFO & Samp Buffer" SrcPort 4 DstBlock "FFT" DstPort 4 } Line { SrcBlock "CFO & Samp Buffer" SrcPort 1 DstBlock "FFT" DstPort 1 } Line { Labels [0, 0] SrcBlock "CFO & Samp Buffer" SrcPort 2 DstBlock "FFT" DstPort 2 } Line { SrcBlock "CFO & Samp Buffer" SrcPort 3 DstBlock "FFT" DstPort 3 } Line { SrcBlock "Chan Est & EQ" SrcPort 1 DstBlock "Detect & Decode" DstPort 1 } Line { SrcBlock "Chan Est & EQ" SrcPort 2 DstBlock "Detect & Decode" DstPort 2 } Line { SrcBlock "Chan Est & EQ" SrcPort 5 DstBlock "Detect & Decode" DstPort 5 } Line { SrcBlock "FFT" SrcPort 2 DstBlock "Chan Est & EQ" DstPort 1 } Line { SrcBlock "FFT" SrcPort 3 DstBlock "Chan Est & EQ" DstPort 2 } Line { SrcBlock "FFT" SrcPort 6 DstBlock "Chan Est & EQ" DstPort 5 } Line { SrcBlock "DSSS Rx" SrcPort 1 DstBlock "FCS & Pkt Buf" DstPort 1 } Line { SrcBlock "Detect & Decode" SrcPort 1 DstBlock "FCS & Pkt Buf" DstPort 2 } Line { SrcBlock "Detect & Decode" SrcPort 2 Points [35, 0; 0, 45; -520, 0] Branch { Points [-175, 0] Branch { Points [0, -50] DstBlock "CFO & Samp Buffer" DstPort 7 } Branch { Points [-175, 0; 0, -65] DstBlock "Sync & Antenna Sel" DstPort 5 } } Branch { Points [0, -30] DstBlock "FFT" DstPort 5 } } Line { SrcBlock "Inputs" SrcPort 1 DstBlock "Sync & Antenna Sel" DstPort 1 } Line { SrcBlock "Inputs" SrcPort 2 DstBlock "Sync & Antenna Sel" DstPort 2 } Line { SrcBlock "Inputs" SrcPort 3 DstBlock "Sync & Antenna Sel" DstPort 3 } Line { SrcBlock "Inputs" SrcPort 4 DstBlock "Sync & Antenna Sel" DstPort 4 } Line { SrcBlock "Sync & Antenna Sel" SrcPort 2 Points [5, 0] Branch { DstBlock "CFO & Samp Buffer" DstPort 2 } Branch { Points [0, -60] DstBlock "DSSS Rx" DstPort 2 } } Line { SrcBlock "Sync & Antenna Sel" SrcPort 3 Points [10, 0] Branch { DstBlock "CFO & Samp Buffer" DstPort 3 } Branch { Points [0, -60] DstBlock "DSSS Rx" DstPort 3 } } Line { SrcBlock "Sync & Antenna Sel" SrcPort 4 Points [15, 0] Branch { DstBlock "CFO & Samp Buffer" DstPort 4 } Branch { Points [0, -60] DstBlock "DSSS Rx" DstPort 4 } } Line { SrcBlock "Sync & Antenna Sel" SrcPort 5 DstBlock "CFO & Samp Buffer" DstPort 5 } Line { SrcBlock "Sync & Antenna Sel" SrcPort 6 DstBlock "CFO & Samp Buffer" DstPort 6 } Line { SrcBlock "Sync & Antenna Sel" SrcPort 1 Points [0, -60] DstBlock "DSSS Rx" DstPort 1 } Line { SrcBlock "FFT" SrcPort 4 DstBlock "Chan Est & EQ" DstPort 3 } Line { SrcBlock "FFT" SrcPort 5 DstBlock "Chan Est & EQ" DstPort 4 } Line { SrcBlock "Chan Est & EQ" SrcPort 3 DstBlock "Detect & Decode" DstPort 3 } Line { SrcBlock "Chan Est & EQ" SrcPort 4 DstBlock "Detect & Decode" DstPort 4 } Annotation { Name "Copyright (c) 2020 Mango Communications, Inc. All rights reserved.\n\nDistributed under the Mango R" "eference Design License:\nhttp://mangocomm.com/802.11/license" Position [667, 401] DropShadow on } Annotation { Name "TODO:\n-HT-SIG.LENGTH=0 not supported (required for NDP sounding, not common), \n will be marked " "as bad FCS to MAC\n-Scale soft bits by abs(H)?" Position [59, 421] HorizontalAlignment "left" } } } MatData { NumRecords 1 DataRecord { Tag DataTag0 Data " %)30 . ^)T 8 ( @ % \" $ ! 0 % 0 !@ $ , 0 . . 8 ( ! " "% \" $ ' 0 0 !P '1A7, !V86QU97, . & $ 8 ( 0 % \" $ # 0 " ". 0 8 ( ! % \" $ + 0 0 \"P $A$3\"!.971L:7-T . 2 8 " " ( ! % \" $ 8 0 0 & $5X<&]R=\"!A7-I

7=H97)E(&EN(%-U8E-Y&EL:6YX9F%M:6QY <&%R= " " 7!E7W-G861V86YC960 <')" "O:E]T>7!E 4WEN=&A?9FEL95]S9V%D=F%N8V5D 4WEN=&A?9FEL90 " " 26UP;%]F:6QE7W-G861V86YC960 26UP;%]F:6QE =&5S=&)E;F-H7W-G861V86YC960 " " =&5S=&)E;F-H #8 #@ $ & \" 0 !0 @ ! \"@ $ $ H !X8S9V;'@" "R-#!T #@ # & \" 0 !0 @ ! @ $ $ \" \"TR . . 8 ( ! " " % \" $ & 0 0 !@ &9F,3$U-@ #@ # & \" 0 !0 @ " " $ $ . , 8 ( ! % \" $ # 0 0 , 6%-4 X P !@ " " @ $ 4 ( ! ! #@ $ & \" 0 !0 @ ! #0 " " $ $ T !#;&]C:R!%;F%B;&5S #@ $ & \" 0 !0 @ ! \"0 $ $ " " D N+VYE=&QI'0G*3L #@ # & \" 0 !0 @ $ $ . " " , 8 ( ! % \" 0 0 X P !@ @ $ 4 ( " " ! ! #@ # & \" 0 !0 @ ! P $ $ # &]F9@ . " " , 8 ( ! % \" $ $ 0 0 0 5DA$3 X ! !@ @ $ 4 ( " " 0 T ! ! - 6%-4($1E9F%U;'1S*@ X ! !@ @ $ 4 ( 0 T ! " " ! - 25-%($1E9F%U;'1S*@ X X !@ @ & 4 ( 0 $ ! D ( " " . . 8 ( !@ % \" $ ! 0 ) \" #@ ) @ & \" " " ( !0 @ ! 0 $ !0 $ !X ! O@4 &EN9F]E9&ET 'AI;&EN>" "&9A;6EL>0 '!A0 " " '!R;VI?='EP95]S9V%D=F%N8V5D '!R;VI?='EP90 %-Y;G1H7V9I;&5?0 " " '9E#8 #@ $ & \" 0 !0 @ ! \"@ $" " $ H !X8S9V;'@R-#!T #@ # & \" 0 !0 @ ! @ $ $ \" \"" "TR . . 8 ( ! % \" $ & 0 0 !@ &9F,3$U-@ #@ # & \" " "0 !0 @ $ $ . , 8 ( ! % \" $ # 0 " " 0 , 6%-4 X P !@ @ $ 4 ( ! ! #@ $ & \" 0 " " !0 @ ! #0 $ $ T !#;&]C:R!%;F%B;&5S #@ $ & \" 0 !0 @ " " ! $ $ $ ! N+W!C;W)E7W)X7W8T,#)A#@ # & \" 0 !0 @ $ " " $ . 2 8 ( ! % \" $ 1 0 0 $0 %!R;VIE8W0@3F%V:6=A=&]" "R X P !@ @ $ 4 ( ! ! #@ $ & \" 0 " " !0 @ ! # $ $ P !84U0@1&5F875L=', #@ # & \" 0 !0 @ " " $ $ . 0 8 ( ! % \" $ , 0 0 # $E312!$96" "9A=6QT

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