Changes between Version 11 and Version 12 of 802.11/Architecture

Timestamp:

Dec 2, 2013, 8:52:12 AM (10 years ago)

Author:

murphpo

Comment:

--

802.11/Architecture

@@ -13 +13 @@
 [[Image(wiki:802.11/files:wlan_ref_des_arch.png, width=500)]]
 
-== FPGA Cores ==
+== 802.11 FPGA Cores ==
 
  * '''CPU High:''' MicroBlaze CPU executing the top-level MAC code and other high-level functions. The code in CPU High is responsible for constructing all non-control packets for transmission and for implementing the various handshakes with nodes (probe request/response, association request/response, etc.). CPU High is also responsible for integrating with a wired network, implementing encapsulation and de-encapsulation of Ethernet frames according to the wired-wireless integration described in Annex P of the IEEE 802.11-2012 standard. CPU High is clocked at 160MHz.
@@ -25 +25 @@
  * '''Hardware Support''': These cores are drawn from the standard platform support cores for WARP v3 ([wiki:cores/w3_ad_controller w3_ad_controller], [wiki:cores/radio_controller radio_controller], etc.) and enable control of the various peripheral interfaces on WARP v3 from the code in CPU Low.
 
-== Inter-Processor Communication ==
-CPU High and CPU Low run independent executables, each generated by a distinct software application project in the Xilinx SDK. The two executables communicate via a mailbox (the Xilinx [http://www.xilinx.com/products/intellectual-property/mailbox.htm  axi_mailbox] core). The two CPUs also utilize a mutex to protect access to the Tx and Rx packet buffers in use by each processor. The mailbox and mutex are the only connection between the two applications.
+== Design Integration ==
+The 802.11 Reference Design is implemented as a Xilinx Platform Studio project. The XPS project integrates the CPUs, PHY cores, MAC core, hardware support cores and FPGA pin and timing constraints. The output of the XPS project is a fully-implemented FPGA design ready for use in the Xilinx SDK. The MAC code is compiled in the SDK and added to the FPGA design. The combined hardware+software design is used to configure the WARP v3 FPGA.
+
+If you are not familiar with the System Generator -> XPS -> SDK -> hardware design flow, please review our [GettingStarted/WARPv3 tutorials]. These tutorials introduce the same design tools used for the 802.11 Reference Design using a much simpler example design.