Changes between Version 2 and Version 3 of 802.11/Architecture


Ignore:
Timestamp:
Jul 26, 2013, 5:22:46 PM (11 years ago)
Author:
murphpo
Comment:

--

Legend:

Unmodified
Added
Removed
Modified

  • 802.11/Architecture

    v2 v3  
    33= 802.11 Reference Design: Architecture =
    44
    5 [[Image(wiki:802.11/files:wlan_ref_des_arch.png)]]
     5[[Image(wiki:802.11/files:wlan_ref_des_arch.png, width=500, right)]]
    66
    7 The 802.11 Reference Design consists of 4 key hardware components that, together, implement the 802.11 PHY, MAC and some of the networking layer.
     7The 802.11 Reference Design is implemented entirely in the FPGA of the WARP v3 node. PHY processing is divided across multiple cores (Tx, Rx, AGC, hardware control, etc.). The MAC is implemented primarily in software running in two MicroBlaze CPUs, with a support core in the FPGA to achieve accurate inter-packet timing. The overall design is integrated in Xilinx Platform Studio (XPS). The source code/models for all components are available in the repository: [browser:/ReferenceDesigns/802.11 /ReferenceDesigns/w3_802.11] and are distributed under the [wiki:../License Mango Reference Design License].
    88
    9 == Hardware Components ==
     9== FPGA Cores ==
    1010
    11 1.  '''CPU_HIGH (mb_high):''' a high-level processor for performing inter-packet tasks that are not time critical. For example, this processor handles 802.11 associations with stations and handles the periodic transmissions of beacon frames. Additionally, this processor handles Ethernet receptions and transmissions. The wlan_mac_ap software project implements a portal to integrate the WLAN with a Wired LAN as specified in Annex P of the 802.11-2012 standard.
     11 * '''CPU High:''' MicroBlaze CPU executing the top-level MAC code and other high-level functions. The code in CPU High is responsible for constructing all non-control packets for transmission and for implementing the various handshakes with nodes (probe request/response, association request/response, etc.). CPU High is also responsible for integrating with a wired network, implementing encapsulation and de-encapsulation of Ethernet frames according to the wired-wireless integration described in Annex P of the IEEE 802.11-2012 standard.
    1212
    13 2.  '''CPU_LOW (mb_low):''' a low-level processor for handling intra-packet behaviors that are time critical. For example, this processor runs code that is responsible for constructing outgoing ACK frames within a SIFS interval following the last byte of a reception on the wireless medium. It is also responsible for handling retransmissions and modifying the 802.11 contention window as appropriate. The wlan_mac_dcf software project is an implementation of Section 9.3.1 of the 802.11-2012 standard. Inter-processor communication between CPU_HIGH and CPU_LOW is handled by [http://www.xilinx.com/products/intellectual-property/mailbox.htm an AXI Mailbox] and mutual exclusion is handled by [http://www.xilinx.com/products/intellectual-property/mutex.htm an AXI Mutex].
     13 * '''CPU Low:''' MicroBlaze CPU executing low-level code for the MAC distributed coordination function (DCF). This code is responsible for all MAC-PHY interactions and for handling intra-packet state that is time critical. This includes transmission of ACKs, scheduling of backoffs, maintaining the contention window and initiating re-transmissions. The wlan_mac_dcf software project is an implementation of Section 9.3.1 of the 802.11-2012 standard.
    1414
    15 3.  '''MAC DCF (wlan_mac_dcf_hw):''' a hardware peripheral core that acts as the interface between the physical layer and any C code that runs in the processors. It also assists in managing the DCF transmit state machine by automatically beginning timeouts after unicast transmissions, beginning backoff intervals after DIFS intervals following medium idle indications, and other timing-critical functions. It also manages the virtual CS of the system, automatically interpreting the duration field of receptions and updating the NAV. Furthermore, this core is responsible for the automatic transmission of packets after valid-FCS receptions, provided the CPU_LOW enables that feature and constructs the outgoing frame prior to the time in which it should transmit (generally a SIFS).
     15 * '''MAC DCF Core (wlan_mac_dcf_hw):''' an FPGA core implemented in System Generator which acts as the interface between the MAC software design and the Tx/Rx PHY cores. This core implements the timers required for the DCF (timeout, backoff, DIFS, SIFS, etc.) and the various carrier sensing mechanisms. The MAC DCF core monitors the Tx and Rx PHY cores and sequences Tx and Rx events per the configuration provided by the MAC software.
    1616
    17 4.  '''PHY TX/RX''': These peripheral cores implement the physical layer behavior specified in Section 18 of the 802.11-2012 standard. Details are available in the [wiki:./FAQ FAQ].
     17 * '''PHY Tx/Rx''': These peripheral cores implement the OFDM physical layer transceiver specified in Section 18 of the 802.11-2012 standard. Details are available in the [wiki:./PHY PHY page].
    1818
    19 == Getting Started with the 802.11 Reference Design ==
     19 * '''Hardware Support''': These cores are drawn from the standard platform support cores for WARP v3 ([wiki:cores/w3_ad_controller w3_ad_controller], [wiki:cores/radio_controller radio_controller], etc.) and enable control of the various peripheral interfaces on WARP v3 from the code in CPU Low.
    2020
    21 1. Plug ETH A from a WARP v3 board into a router whose WAN port is connected to the Internet. The 802.11 Reference Design is not a router -- it does not have a DHCP server to issue IP addresses to associated stations. It will, however, pass DHCP requests and responses through its Ethernet portal, so connecting WARP v3 to a router will allow DHCP to occur on client stations.
    22 1. Download the 802.11 Reference Design and program a WARP v3 board with the provided bitstream.
    23 1. Use any 802.11 device (such as a computer or smartphone) to join the unsecured network with SSID of "WARP." At this point, the 802.11 device should be able to access the network.
     21== Inter-Processor Communication ==
     22CPU High and CPU Low run independent executables, each generated by a distinct software application project in the Xilinx SDK. The two executables communicate via a mailbox (the Xilinx [http://www.xilinx.com/products/intellectual-property/mailbox.htm an axi_mailbox] core). The two CPUs also utilize a mutex to protect access to the Tx and Rx packet buffers in use by each processor. The mailbox and mutex are the only connection between the two applications.
     23