| 5 | | The 802.11 Reference Design is implemented entirely in the FPGA of the WARP v3 node. PHY processing is divided across multiple cores (Tx, Rx, AGC, hardware control, etc.). The MAC is implemented primarily in software running in two MicroBlaze CPUs, with a support core in the FPGA to achieve accurate inter-packet timing. The overall design is integrated in Xilinx Platform Studio (XPS). The source code/models for all components are available in the repository: [browser:/ReferenceDesigns/w3_802.11 /ReferenceDesigns/w3_802.11] and are distributed under the [wiki:../License Mango Reference Design License]. |
| | 5 | The 802.11 Reference Design is implemented entirely in the FPGA of the WARP v3 node. PHY processing is divided across multiple cores (Tx, Rx, AGC, hardware control, etc.). The MAC is implemented primarily in software running in two MicroBlaze CPUs, with a support core in the FPGA to achieve accurate inter-packet timing. The overall design is integrated in Xilinx Platform Studio (XPS). The source code/models for all components are available in the repository ([browser:/ReferenceDesigns/w3_802.11 /ReferenceDesigns/w3_802.11]) and are distributed under the [wiki:../License Mango Reference Design License]. |
