Changes between Initial Version and Version 1 of 802.11/FPGAArchitecture/802_11_v1_3


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Timestamp:
Dec 7, 2015, 2:25:07 PM (8 years ago)
Author:
welsh
Comment:

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  • 802.11/FPGAArchitecture/802_11_v1_3

    v1 v1  
     1{{{#!comment
     2[[Include(wiki:802.11/beta-note)]]
     3}}}
     4
     5[[TracNav(802.11/TOC)]]
     6
     7= 802.11 Reference Design version 1.3.0 FPGA Architecture for WARP v3 Hardware =
     8
     9The 802.11 Reference Design version 1.3.0 for WARP v3 makes changes to the underlying FPGA architecture.  This includes:
     10
     11  * New clock_controller and EEPROM cores that mirror the connections in WARPLab 7.5.1
     12  * New radio_controller
     13  * See [wiki:802.11/Changelog#a1.3Release changelog] for other updates
     14
     15== Interconnect Architecture ==
     16
     17[[Image(802_11_v1_3_interconnect_architecture.png)]]
     18
     19
     20== Address Map ==
     21
     22  Please review the XPS project for the latest information. 
     23
     24
     25=== Microblaze Address Map ===
     26
     27'''NOTE:  All Address not explicitly defined are reserved.'''
     28
     29||= '''IP Instance''' =||= '''Base Address''' =||= '''High Address''' =||= '''Size''' =||
     30|| DLMB || 0x0000_0000 || 0x0001_FFFF || 128K ||
     31|| ILMB || 0x0000_0000 || 0x0001_FFFF || 128K ||
     32|| Interrupt Controller || 0x1000_0000 || 0x1000_FFFF || 64K ||
     33|| WARPLab Trigger Proc || 0x1010_0000 || 0x1010_FFFF || 64K ||
     34|| WARPLab AGC || 0x1020_0000 || 0x1020_FFFF || 64K ||
     35|| WARPLab Buffers || 0x1030_0000 || 0x1030_FFFF || 64K ||
     36|| ETH A MAC || 0x1100_0000 || 0x1103_FFFF || 256K ||
     37|| ETH B MAC || 0x1110_0000 || 0x1113_FFFF || 256K ||
     38|| AXI DMA (ETH A) || 0x1120_0000 || 0x1120_FFFF || 64K ||
     39|| AXI DMA (ETH B) || 0x1130_0000 || 0x1130_FFFF || 64K ||
     40|| CDMA || 0x1200_0000 || 0x1200_FFFF || 64K ||
     41|| W3 Clock Controller || 0x2010_0000 || 0x2010_FFFF || 64K ||
     42|| W3 User IO || 0x2020_0000 || 0x2020_FFFF || 64K ||
     43|| Radio Controller || 0x2030_0000 || 0x2030_FFFF || 64K ||
     44|| W3 AD Controller || 0x2040_0000 || 0x2040_FFFF || 64K ||
     45|| AXI GPIO || 0x2050_0000 || 0x2050_FFFF || 64K ||
     46|| AXI SYSMON ADC || 0x2060_0000 || 0x2060_FFFF || 64K ||
     47|| AXI Timer || 0x2070_0000 || 0x2070_FFFF || 64K ||
     48|| USB UART || 0x2080_0000 || 0x2080_FFFF || 64K ||
     49|| W3 I2C EEPROM On Board || 0x2090_0000 || 0x2090_FFFF || 64K ||
     50|| W3 I2C EEPROM FMC || 0x20A0_0000 || 0x20A0_FFFF || 64K ||
     51|| RFA RX CTL || 0x4100_0000 || 0x4101_FFFF || 128K ||
     52|| RFA RSSI CTL || 0x4102_0000 || 0x4102_3FFF || 16K ||
     53|| RFA TX CTL || 0x4104_0000 || 0x4105_FFFF || 128K ||
     54|| RFB RX CTL || 0x4108_0000 || 0x4109_FFFF || 128K ||
     55|| RFB RSSI CTL || 0x410A_0000 || 0x410A_3FFF || 16K ||
     56|| RFB TX CTL || 0x410C_0000 || 0x410D_FFFF || 128K ||
     57|| RFC RX CTL || 0x4110_0000 || 0x4111_FFFF || 128K ||
     58|| RFC RSSI CTL || 0x4112_0000 || 0x4112_3FFF || 16K ||
     59|| RFC TX CTL || 0x4114_0000 || 0x4115_FFFF || 128K ||
     60|| RFD RX CTL || 0x4118_0000 || 0x4119_FFFF || 128K ||
     61|| RFD RSSI CTL || 0x411A_0000 || 0x411A_3FFF || 16K ||
     62|| RFD TX CTL || 0x411C_0000 || 0x411D_FFFF || 128K ||
     63|| BRAM || 0x5000_0000 || 0x5001_FFFF || 128K ||
     64|| DDR ||  0x8000_0000 || 0xFFFF_FFFF || 2G ||
     65
     66
     67