Changes between Version 1 and Version 2 of 802.11/FPGAArchitecture/802_11_v1_3


Ignore:
Timestamp:
Dec 7, 2015, 2:46:13 PM (8 years ago)
Author:
welsh
Comment:

--

Legend:

Unmodified
Added
Removed
Modified

  • 802.11/FPGAArchitecture/802_11_v1_3

    v1 v2  
    2323
    2424
    25 === Microblaze Address Map ===
     25=== CPU High Microblaze Address Map ===
    2626
    2727'''NOTE:  All Address not explicitly defined are reserved.'''
    2828
    2929||= '''IP Instance''' =||= '''Base Address''' =||= '''High Address''' =||= '''Size''' =||
    30 || DLMB || 0x0000_0000 || 0x0001_FFFF || 128K ||
    31 || ILMB || 0x0000_0000 || 0x0001_FFFF || 128K ||
    32 || Interrupt Controller || 0x1000_0000 || 0x1000_FFFF || 64K ||
    33 || WARPLab Trigger Proc || 0x1010_0000 || 0x1010_FFFF || 64K ||
    34 || WARPLab AGC || 0x1020_0000 || 0x1020_FFFF || 64K ||
    35 || WARPLab Buffers || 0x1030_0000 || 0x1030_FFFF || 64K ||
    36 || ETH A MAC || 0x1100_0000 || 0x1103_FFFF || 256K ||
    37 || ETH B MAC || 0x1110_0000 || 0x1113_FFFF || 256K ||
    38 || AXI DMA (ETH A) || 0x1120_0000 || 0x1120_FFFF || 64K ||
    39 || AXI DMA (ETH B) || 0x1130_0000 || 0x1130_FFFF || 64K ||
    40 || CDMA || 0x1200_0000 || 0x1200_FFFF || 64K ||
    41 || W3 Clock Controller || 0x2010_0000 || 0x2010_FFFF || 64K ||
    42 || W3 User IO || 0x2020_0000 || 0x2020_FFFF || 64K ||
    43 || Radio Controller || 0x2030_0000 || 0x2030_FFFF || 64K ||
    44 || W3 AD Controller || 0x2040_0000 || 0x2040_FFFF || 64K ||
    45 || AXI GPIO || 0x2050_0000 || 0x2050_FFFF || 64K ||
    46 || AXI SYSMON ADC || 0x2060_0000 || 0x2060_FFFF || 64K ||
    47 || AXI Timer || 0x2070_0000 || 0x2070_FFFF || 64K ||
    48 || USB UART || 0x2080_0000 || 0x2080_FFFF || 64K ||
    49 || W3 I2C EEPROM On Board || 0x2090_0000 || 0x2090_FFFF || 64K ||
    50 || W3 I2C EEPROM FMC || 0x20A0_0000 || 0x20A0_FFFF || 64K ||
    51 || RFA RX CTL || 0x4100_0000 || 0x4101_FFFF || 128K ||
    52 || RFA RSSI CTL || 0x4102_0000 || 0x4102_3FFF || 16K ||
    53 || RFA TX CTL || 0x4104_0000 || 0x4105_FFFF || 128K ||
    54 || RFB RX CTL || 0x4108_0000 || 0x4109_FFFF || 128K ||
    55 || RFB RSSI CTL || 0x410A_0000 || 0x410A_3FFF || 16K ||
    56 || RFB TX CTL || 0x410C_0000 || 0x410D_FFFF || 128K ||
    57 || RFC RX CTL || 0x4110_0000 || 0x4111_FFFF || 128K ||
    58 || RFC RSSI CTL || 0x4112_0000 || 0x4112_3FFF || 16K ||
    59 || RFC TX CTL || 0x4114_0000 || 0x4115_FFFF || 128K ||
    60 || RFD RX CTL || 0x4118_0000 || 0x4119_FFFF || 128K ||
    61 || RFD RSSI CTL || 0x411A_0000 || 0x411A_3FFF || 16K ||
    62 || RFD TX CTL || 0x411C_0000 || 0x411D_FFFF || 128K ||
    63 || BRAM || 0x5000_0000 || 0x5001_FFFF || 128K ||
    64 || DDR ||  0x8000_0000 || 0xFFFF_FFFF || 2G ||
     30|| DLMB_0 || 0x0000_0000 || 0x0001_FFFF || 128K ||
     31|| ILMB_0 || 0x0000_0000 || 0x0001_FFFF || 128K ||
     32|| DLMB_1 || 0x0002_0000 || 0x0003_FFFF || 128K ||
     33|| ILMB_1 || 0x0002_0000 || 0x0003_FFFF || 128K ||
     34|| AXI GPIO (timestamp) || 0x4000_0000 || 0x4000_FFFF || 64K ||
     35|| AXI GPIO (software) || 0x4010_0000 || 0x4010_FFFF || 64K ||
     36|| USB UART || 0x4060_0000 || 0x4060_FFFF || 64K ||
     37|| Interrupt Controller || 0x4120_0000 || 0x4120_FFFF || 64K ||
     38|| AXI Timer || 0x41C0_0000 || 0x41C0_FFFF || 64K ||
     39|| AXI SYSMON ADC || 0x41D0_0000 || 0x41D0_FFFF || 64K ||
     40|| AXI DMA (ETH A) || 0x41E0_0000 || 0x41E0_FFFF || 64K ||
     41|| Mutex || 0x4340_0000 || 0x4340_FFFF || 64K ||
     42|| ETH A MAC || 0x4244_0000 || 0x4347_FFFF || 256K ||
     43|| ETH B MAC || 0x4348_0000 || 0x434B_FFFF || 256K ||
     44|| AXI FIFO (ETH B) || 0x434C_0000 || 0x434C_FFFF || 64K ||
     45|| Mailbox || 0x4360_0000 || 0x4360_FFFF || 64K ||
     46|| BRAM (init) || 0x5000_0000 || 0x5000_0FFF || 4K ||
     47|| CDMA || 0x7E20_0000 || 0x7E20_FFFF || 64K ||
     48|| W3 User IO || 0x8000_0000 || 0x8000_0FFF || 4K ||
     49|| BRAM (aux) || 0xBF54_0000 || 0xBF54_FFFF || 64K ||
     50|| BRAM (RX pkt buffer) || 0xBF56_0000 || 0xBF56_7FFF || 32K ||
     51|| BRAM (TX pkt buffer) || 0xBF57_0000 || 0xBF57_7FFF || 32K ||
     52|| DDR ||  0xC000_0000 || 0xFFFF_FFFF || 1G ||
     53
     54
     55=== CPU Low Microblaze Address Map ===
     56
     57'''NOTE:  All Address not explicitly defined are reserved.'''
     58
     59||= '''IP Instance''' =||= '''Base Address''' =||= '''High Address''' =||= '''Size''' =||
     60|| DLMB || 0x0000_0000 || 0x0000_FFFF || 64K ||
     61|| ILMB || 0x0000_0000 || 0x0000_FFFF || 64K ||
     62|| USB UART || 0x4060_0000 || 0x4060_FFFF || 64K ||
     63|| AXI Timer || 0x41C0_0000 || 0x41C0_FFFF || 64K ||
     64|| Mailbox || 0x4380_0000 || 0x4380_FFFF || 64K ||
     65|| W3 I2C EEPROM On Board || 0x7040_0000 || 0x7040_FFFF || 64K ||
     66|| W3 Clock Controller || 0x7042_0000 || 0x7042_FFFF || 64K ||
     67|| W3 AD Controller || 0x7600_0000 || 0x7600_FFFF || 64K ||
     68|| WLAN PHY TX || 0x78E0_0000 || 0x78E0_FFFF || 64K ||
     69|| WLAN PHY RX || 0x78E2_0000 || 0x78E2_FFFF || 64K ||
     70|| Radio Controller || 0x7AC0_0000 || 0x7AC0_FFFF || 64K ||
     71|| Mutex || 0x7B00_0000 || 0x7B00_FFFF || 64K ||
     72|| WLAN MAC HW || 0x7BE0_0000 || 0x7BE0_FFFF || 64K ||
     73|| WLAN AGC || 0x7EA0_0000 || 0x7EA0_FFFF || 64K ||
     74|| W3 User IO || 0x8000_0000 || 0x8000_0FFF || 4K ||
     75|| BRAM (RX pkt buffer) || 0xBF56_0000 || 0xBF56_7FFF || 32K ||
     76|| BRAM (TX pkt buffer) || 0xBF57_0000 || 0xBF57_7FFF || 32K ||
    6577
    6678
    6779
     80
     81