| 1 | {{{#!comment |
| 2 | [[Include(wiki:802.11/beta-note)]] |
| 3 | }}} |
| 4 | |
| 5 | [[TracNav(802.11/TOC)]] |
| 6 | |
| 7 | = 802.11 Reference Design version 1.4.0 FPGA Architecture for WARP v3 Hardware = |
| 8 | |
| 9 | The 802.11 Reference Design version 1.4.0 for WARP v3 makes changes to the underlying FPGA architecture. This includes: |
| 10 | |
| 11 | * New MAC time hardware core |
| 12 | * Updates to Ethernet controller B |
| 13 | * Updates to peripheral address map |
| 14 | * See [wiki:802.11/Changelog#a1.4Release changelog] for other updates |
| 15 | |
| 16 | == Interconnect Architecture == |
| 17 | |
| 18 | [[Image(802_11_v1_4_interconnect_architecture.png)]] |
| 19 | |
| 20 | |
| 21 | == Address Map == |
| 22 | |
| 23 | Please review the XPS project for the latest information. |
| 24 | |
| 25 | |
| 26 | === CPU High Microblaze Address Map === |
| 27 | |
| 28 | '''NOTE: All Address not explicitly defined are reserved.''' |
| 29 | |
| 30 | ||= '''IP Instance''' =||= '''Base Address''' =||= '''High Address''' =||= '''Size''' =|| |
| 31 | || DLMB_0 || 0x0000_0000 || 0x0001_FFFF || 128K || |
| 32 | || ILMB_0 || 0x0000_0000 || 0x0001_FFFF || 128K || |
| 33 | || DLMB_1 || 0x0002_0000 || 0x0003_FFFF || 128K || |
| 34 | || ILMB_1 || 0x0002_0000 || 0x0003_FFFF || 128K || |
| 35 | || AXI GPIO (timestamp) || 0x4000_0000 || 0x4000_FFFF || 64K || |
| 36 | || AXI GPIO (software) || 0x4010_0000 || 0x4010_FFFF || 64K || |
| 37 | || USB UART || 0x4060_0000 || 0x4060_FFFF || 64K || |
| 38 | || Interrupt Controller || 0x4120_0000 || 0x4120_FFFF || 64K || |
| 39 | || AXI Timer || 0x41C0_0000 || 0x41C0_FFFF || 64K || |
| 40 | || AXI SYSMON ADC || 0x41D0_0000 || 0x41D0_FFFF || 64K || |
| 41 | || AXI DMA (ETH A) || 0x41E0_0000 || 0x41E0_FFFF || 64K || |
| 42 | || Mutex || 0x4340_0000 || 0x4340_FFFF || 64K || |
| 43 | || ETH A MAC || 0x4244_0000 || 0x4347_FFFF || 256K || |
| 44 | || ETH B MAC || 0x4348_0000 || 0x434B_FFFF || 256K || |
| 45 | || AXI FIFO (ETH B) || 0x434C_0000 || 0x434C_FFFF || 64K || |
| 46 | || Mailbox || 0x4360_0000 || 0x4360_FFFF || 64K || |
| 47 | || BRAM (init) || 0x5000_0000 || 0x5000_0FFF || 4K || |
| 48 | || CDMA || 0x7E20_0000 || 0x7E20_FFFF || 64K || |
| 49 | || W3 User IO || 0x8000_0000 || 0x8000_0FFF || 4K || |
| 50 | || BRAM (aux) || 0xBF54_0000 || 0xBF54_FFFF || 64K || |
| 51 | || BRAM (RX pkt buffer) || 0xBF56_0000 || 0xBF56_7FFF || 32K || |
| 52 | || BRAM (TX pkt buffer) || 0xBF57_0000 || 0xBF57_7FFF || 32K || |
| 53 | || DDR || 0xC000_0000 || 0xFFFF_FFFF || 1G || |
| 54 | |
| 55 | |
| 56 | === CPU Low Microblaze Address Map === |
| 57 | |
| 58 | '''NOTE: All Address not explicitly defined are reserved.''' |
| 59 | |
| 60 | ||= '''IP Instance''' =||= '''Base Address''' =||= '''High Address''' =||= '''Size''' =|| |
| 61 | || DLMB || 0x0000_0000 || 0x0000_FFFF || 64K || |
| 62 | || ILMB || 0x0000_0000 || 0x0000_FFFF || 64K || |
| 63 | || USB UART || 0x4060_0000 || 0x4060_FFFF || 64K || |
| 64 | || AXI Timer || 0x41C0_0000 || 0x41C0_FFFF || 64K || |
| 65 | || Mailbox || 0x4380_0000 || 0x4380_FFFF || 64K || |
| 66 | || W3 I2C EEPROM On Board || 0x7040_0000 || 0x7040_FFFF || 64K || |
| 67 | || W3 Clock Controller || 0x7042_0000 || 0x7042_FFFF || 64K || |
| 68 | || W3 AD Controller || 0x7600_0000 || 0x7600_FFFF || 64K || |
| 69 | || WLAN PHY TX || 0x78E0_0000 || 0x78E0_FFFF || 64K || |
| 70 | || WLAN PHY RX || 0x78E2_0000 || 0x78E2_FFFF || 64K || |
| 71 | || Radio Controller || 0x7AC0_0000 || 0x7AC0_FFFF || 64K || |
| 72 | || Mutex || 0x7B00_0000 || 0x7B00_FFFF || 64K || |
| 73 | || WLAN MAC HW || 0x7BE0_0000 || 0x7BE0_FFFF || 64K || |
| 74 | || WLAN AGC || 0x7EA0_0000 || 0x7EA0_FFFF || 64K || |
| 75 | || W3 User IO || 0x8000_0000 || 0x8000_0FFF || 4K || |
| 76 | || BRAM (RX pkt buffer) || 0xBF56_0000 || 0xBF56_7FFF || 32K || |
| 77 | || BRAM (TX pkt buffer) || 0xBF57_0000 || 0xBF57_7FFF || 32K || |
| 78 | |
| 79 | |
| 80 | |
| 81 | |