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= 802.11 Reference Design version 1.4.0 FPGA Architecture for WARP v3 Hardware =

The 802.11 Reference Design version 1.4.0 for WARP v3 makes changes to the underlying FPGA architecture.  This includes:

  * New MAC time hardware core
  * Updates to Ethernet controller B
  * Updates to peripheral address map
  * See [wiki:802.11/Changelog#a1.4Release changelog] for other updates

== Interconnect Architecture ==

[[Image(802_11_v1_4_interconnect_architecture.png)]]


== Address Map ==

  Please review the XPS project for the latest information.  


=== CPU High Microblaze Address Map ===

'''NOTE:  All Address not explicitly defined are reserved.'''

||= '''IP Instance''' =||= '''Base Address''' =||= '''High Address''' =||= '''Size''' =||
|| DLMB_0 || 0x0000_0000 || 0x0001_FFFF || 128K ||
|| ILMB_0 || 0x0000_0000 || 0x0001_FFFF || 128K ||
|| DLMB_1 || 0x0002_0000 || 0x0003_FFFF || 128K ||
|| ILMB_1 || 0x0002_0000 || 0x0003_FFFF || 128K ||
|| AXI GPIO (timestamp) || 0x4000_0000 || 0x4000_FFFF || 64K ||
|| AXI GPIO (software) || 0x4010_0000 || 0x4010_FFFF || 64K ||
|| USB UART || 0x4060_0000 || 0x4060_FFFF || 64K ||
|| Interrupt Controller || 0x4120_0000 || 0x4120_FFFF || 64K ||
|| AXI Timer || 0x41C0_0000 || 0x41C0_FFFF || 64K ||
|| AXI SYSMON ADC || 0x41D0_0000 || 0x41D0_FFFF || 64K ||
|| AXI DMA (ETH A) || 0x41E0_0000 || 0x41E0_FFFF || 64K ||
|| Mutex || 0x4340_0000 || 0x4340_FFFF || 64K ||
|| ETH A MAC || 0x4244_0000 || 0x4347_FFFF || 256K ||
|| ETH B MAC || 0x4348_0000 || 0x434B_FFFF || 256K ||
|| AXI FIFO (ETH B) || 0x434C_0000 || 0x434C_FFFF || 64K ||
|| Mailbox || 0x4360_0000 || 0x4360_FFFF || 64K ||
|| BRAM (init) || 0x5000_0000 || 0x5000_0FFF || 4K ||
|| CDMA || 0x7E20_0000 || 0x7E20_FFFF || 64K ||
|| W3 User IO || 0x8000_0000 || 0x8000_0FFF || 4K ||
|| BRAM (aux) || 0xBF54_0000 || 0xBF54_FFFF || 64K ||
|| BRAM (RX pkt buffer) || 0xBF56_0000 || 0xBF56_7FFF || 32K ||
|| BRAM (TX pkt buffer) || 0xBF57_0000 || 0xBF57_7FFF || 32K ||
|| DDR ||  0xC000_0000 || 0xFFFF_FFFF || 1G ||


=== CPU Low Microblaze Address Map ===

'''NOTE:  All Address not explicitly defined are reserved.'''

||= '''IP Instance''' =||= '''Base Address''' =||= '''High Address''' =||= '''Size''' =||
|| DLMB || 0x0000_0000 || 0x0000_FFFF || 64K ||
|| ILMB || 0x0000_0000 || 0x0000_FFFF || 64K ||
|| USB UART || 0x4060_0000 || 0x4060_FFFF || 64K ||
|| AXI Timer || 0x41C0_0000 || 0x41C0_FFFF || 64K ||
|| Mailbox || 0x4380_0000 || 0x4380_FFFF || 64K ||
|| W3 I2C EEPROM On Board || 0x7040_0000 || 0x7040_FFFF || 64K ||
|| W3 Clock Controller || 0x7042_0000 || 0x7042_FFFF || 64K ||
|| W3 AD Controller || 0x7600_0000 || 0x7600_FFFF || 64K ||
|| WLAN PHY TX || 0x78E0_0000 || 0x78E0_FFFF || 64K ||
|| WLAN PHY RX || 0x78E2_0000 || 0x78E2_FFFF || 64K ||
|| Radio Controller || 0x7AC0_0000 || 0x7AC0_FFFF || 64K ||
|| Mutex || 0x7B00_0000 || 0x7B00_FFFF || 64K ||
|| WLAN MAC HW || 0x7BE0_0000 || 0x7BE0_FFFF || 64K ||
|| WLAN AGC || 0x7EA0_0000 || 0x7EA0_FFFF || 64K ||
|| W3 User IO || 0x8000_0000 || 0x8000_0FFF || 4K ||
|| BRAM (RX pkt buffer) || 0xBF56_0000 || 0xBF56_7FFF || 32K ||
|| BRAM (TX pkt buffer) || 0xBF57_0000 || 0xBF57_7FFF || 32K ||