| 5 | | In addition to the state implemented in the CPU_LOW processor, certain low-level MAC behaviors are implemented directly in the FPGA fabric via the MAC Config Hardware core. |
| | 5 | In addition to the state implemented in the CPU_LOW processor, certain time critical MAC behaviors are implemented directly in the FPGA fabric via the MAC Config Hardware core. This core was designed to meet the needs of the DCF implementation of 802.11 while still remaining flexible for custom applications. There are three basic components to the peripheral: Timers, MAC CFG Tx Core A, MAC CFG Tx Core B. |
| | 6 | |
| | 7 | == Timers == |
| | 8 | |
| | 9 | Many MAC algorithms require precise scheduling of transmissions relative to some preceding transmission or reception event. Examples in the DCF include the following: |
| | 10 | |
| | 11 | * ACK and CTS transmissions must occur a SIFS period after previous qualified receptions |
| | 12 | * Contention windows must begin a timeout interval after a previous unsuccessful transmission |
| | 13 | |
| | 14 | To enable these and other custom applications, we have designed the hardware with 4 independent timers that can be configured via software in CPU_LOW: |
| | 15 | |
| | 16 | 1. '''postRxTimer1''' |
| | 17 | 1. '''postRxTimer2''' |
| | 18 | 1. '''postTxTimer1''' |
| | 19 | 1. '''postTxTimer2''' |
| | 20 | |
| | 21 | These timers each independently begin after the prior transmission or reception. They count until a user-specified interval of time has elapsed and then assert an output to the MAC CFG Tx Core A and MAC CFG Tx Core B subsystems. In the stock DCF implementation of the Mango 802.11 Reference Design, only '''postTxTimer2''' and '''postRxTimer1''' are used. Their durations are set to a ACK timeout and a SIFS respectively. |
| | 22 | |
| | 23 | == MAC CFG Tx Core A == |
| | 24 | |
| | 25 | === Implementation Details === |
| | 26 | |
| | 27 | == MAC CFG Tx Core B == |
| | 28 | |
| | 29 | === Implementation Details === |
