Changes between Version 7 and Version 8 of 802.11/MAC/Support_HW

Timestamp:

Apr 17, 2016, 1:21:20 PM (8 years ago)

Author:

murphpo

Comment:

--

802.11/MAC/Support_HW

@@ -50 +50 @@
 
 == MAC Core Tx Controllers ==
+A key function of the lower MAC is implementing the MAC protocol's transmit state machines. The MAC protocol defines when packets can be transmitted. For example the DCF requires an ACK transmission a SIFS interval after receiving a DATA packet. The DCF also requires a random  backoff period before an RTS or DATA transmission if the medium was recently busy. The {{{wlan_mac_hw}}} core implements 3 transmit state machines to facilitate these various protocol requirements. The 3 Tx controllers differ in their state machine inputs/outputs, each tailored to a different MAC protocol task. Each controller is configured from software.
 
 == MAC Tx Controller A ==
 
-Tx Controller A is capable of honoring a post-Tx timeout interval in which a reception is expected by the MAC state. The DCF implementation uses this controller for three different purposes:
+Tx Controller A is capable of honoring a post-Tx timeout interval in which a reception is expected by the MAC state.
 
-1. Transmission of "short" MPDU frames (i.e. MPDUs that required no RTS medium reservation)
+The DCF implementation uses Tx Controller A for three transmission scenarios:
+
+1. Transmission of MPDU frames which do not require RTS ("short" frames)
 1. Transmission of RTS frames
-1. Transmission of "long" MPDU frames (i.e. MPDUs that were preceded by an RTS/CTS handshake)
-
-The unifying trait of each of the above transmissions is the need for a post-Tx timeout window during which a response is expected.
+1. Transmission of "long" MPDU frames following reception of a CTS
 
 === Implementation Details ===
+The Tx Controller A state machine is illustrated below. Each box is a state. Each arrow is a state transition, with the arrow's label specifying the input conditions that trigger the transition. The conditions for the color-coded arrows from the {{{IDLE}}} state are listed in the pseudo-code blocks to the right.
 
 [[Image(tx_core_a.png, width=1000)]]
 
-The above image gives a more detailed view on the state machine implemented in Tx Controller A. Prior to actually transmitting, the controller is capable of starting a backoff or deferring to an already running backoff when the medium is not idle. Alternatively, it can wait for a deterministic interval before transmitting. This interval is defined by either the '''postRxTimer1''' or '''postTxTimer1''' timers described above.
+Notice that the state transitions depend on the postRx_Timer1 (SIFS timer) and postTxTimer2 (timeout timer), as discussed above. 
 
-For the DCF implementation, short MPDU and RTS transmissions do not employ the green deterministic-wait state. These transmission do employ the purple and blue backoff deferral states. Long MPDU transmissions, however, must occur a deterministic SIFS interval after the previous CTS reception. As such, these transmissions use the green deterministic-wait states.
+The Tx Controller A state machine depends on various input signals. These inputs are either parameters set by the MAC software or signals driven by other parts of the MAC support core.
+
+Inputs from software:
+ * reset: Forces FSM back to {{{IDLE}}} state
+ * new_tx: Triggers new execution of FSM
+ * pre_wait_postRxTimer1: Wait for postRx_Timer1 before transmitting
+ * pre_wait_postTxTimer1: Wait for postTx_Timer1 before transmitting
+ * post_wait_postTxTimer2:  Wait for postTx_Timer2 after transmitting
+
+Inputs from MAC hardware:
+ * postRxTimer1_done: postRx_Timer1 has expired
+ * postTxTimer1_done: postTx_Timer1 has expired
+ * postTxTimer2_done: postTx_Timer2 has expired
+ * backoff_done: The backoff counter has reached zero
+ * idle_for_difs: The medium has been idle for a DIFS interval
+ * phy_tx_done: The Tx PHY has finished transmitting
+ * phy_rx_start: The Rx PHY has detected a new reception
+
+The lower MAC framework provides macros for configuring the software parameters above:
+{{{#!c
+// Configure Tx Controller A
+//  pktBuf: Tx packet buffer index (passed directly to PHY at TX_START)
+//  antMask: antenna selection mask  (passed directly to PHY at TX_START)
+//  preTx_backoff_slots: number of backoff slots (passed to backoff counter in START_BO state)
+//  preWait_postRxTimer1: param for FSM, must be 0 or 1
+//  preWait_postTxTimer1: param for FSM, must be 0 or 1
+//  postWait_postTxTimer2: param for FSM, must be 0 or 1
+wlan_mac_tx_ctrl_A_params(pktBuf, antMask, preTx_backoff_slots, preWait_postRxTimer1, preWait_postTxTimer1, postWait_postTxTimer2);
+}}}
+
+The Tx Controller A state machine is started by toggling its enable bit in the MAC support core's register bank:
+{{{#!c
+// Start Tx Controller A
+wlan_mac_tx_ctrl_A_start(1);
+wlan_mac_tx_ctrl_A_start(0);
+}}}
 
 == MAC Tx Controller B ==