74 | | '''Synchronization:''' The PHY implementation requires no "cheating"- all synchronization is implemented in the FPGA and operates per-packet in real time. |
75 | | * The AGC block selects Rx gains per-packet and makes no assumptions about inter-packet receive powers. |
76 | | * The CFO (carrier frequency offset) block estimates and corrects CFO per-packet. CFO estimates are extracted from the preamble long training symbols and correction is applied pre-FFT. |
77 | | * The symbol sync block establishes sample-level synchronization using a complex cross correlator tuned to the preamble long training symbols. All Rx timing is established per-packet based on the correlator output. |
78 | | * The channel estimation block computes a complex channel estimate (magnitude and phase) for each subcarrier per-packet. The equalizer applies the channel estimate per-subcarrier. The current Rx PHY uses the same channel estimates for the full packet. Extending this to a decision feedback scheme (where channel estimates are updated intra-packet) would be a straightforward extension. |
| 69 | * '''Soft Demod''': each data symbol is then demodulated to a soft value per coded bit |
80 | | '''Multi-antenna support:''' The current PHY Tx/Rx pipelines are SISO, supporting the modulation/coding rates specified in section 18 of the standard. The PHY antenna interfaces implement selection diversity across the two RF interfaces on WARP v3 hardware. The antenna selection is made per packet. For transmissions the antenna selection is always controlled by C code in CPU Low. For receptions the PHY can automatically select the higher-SNR antenna based on the AGC gain selections. Alternatively the C code in CPU Low can force the receive antenna selection. |
| 71 | * '''De-Interleaving''': the coded bits, represented as soft 4-bit confidence values, are de-interleaved along OFDM symbol boundaries using the interleaving pattern specified in the standard |
| 72 | |
| 73 | * '''Decoding''': the de-interleaved soft values are decoded using a standard Viterbi decoder |
| 74 | |
| 75 | * '''Descrambling''': the de-coded bits are finally descrambled using the LFSR specified in the standard |
| 76 | |
| 77 | All logic in the WLAN receiver core is clocked at 160MHz and supports a maximum bandwidth of 20MHz (clock rate = 8x max sample rate). Smaller bandwidths are supported by reducing the duty cycle of the sample_valid signal at the input to the Rx pipeline. |
| 78 | |
| 79 | === DSSS === |
| 80 | The PHY receiver also implements the 1Mbps DSSS rate specified in the original 802.11 standard (section 16.2 of the 802.11-2012 standard). This receiver allows reception of management frames transmitted by 802.11 devices at 1Mbps. These transmissions are common in deployments of 802.11 hardware at 2.4GHz. For example, Beacon and Probe Request frames are frequently transmitted at 1Mbps by commercial devices. The basic STA/AP association handshake requires reception of these frames. The 802.11 Reference Design does not implement a DSSS transmitter, as modern 802.11 devices are able to receive management frames at higher rates (including 6Mbps, the lowest OFDM rate, which is commonly used for management frames at 5GHz). |
| 81 | |
| 82 | === Multi-antenna Support === |
| 83 | The current PHY Tx/Rx pipelines are SISO, supporting the modulation/coding rates specified in section 18 of the standard. The PHY antenna interfaces implement selection diversity across the two RF interfaces on WARP v3 hardware. The antenna selection is made per packet. For transmissions the antenna selection is always controlled by C code in CPU Low. For receptions the PHY can automatically select the higher-SNR antenna based on the AGC gain selections. Alternatively the C code in CPU Low can force the receive antenna selection. |