Changes between Version 15 and Version 16 of 802.11/PHY

Timestamp:

Dec 2, 2013, 5:19:51 AM (10 years ago)

Author:

murphpo

Comment:

--

802.11/PHY

@@ -17 +17 @@
  * wlan_phy_agc: Automatic gain control (AGC)
 
-[[Image(wiki:802.11/files:wlan_phy_cores_arch.png)]]
+[[Image(wiki:802.11/files:wlan_phy_cores_arch.png,nolink)]]
 
 At one end the PHY cores interface directly to the ADCs and DACs on the WARP v3 hardware via the w3_ad_bridge core. These interfaces are complex sample streams running at 20MHz. At the other end the cores connect to the Tx and Rx packet buffers. The packet buffers are implemented as dual-port RAMs, each with one port dedicated to PHY access and the other port tied to the AXI interconnect for access by the CPUs.
@@ -55 +55 @@
 The architecture of the PHY receiver is illustrated below.
 
-[[Image(wiki:802.11/files:wlan_phy_rx_blk_diag.png)]]
+[[Image(wiki:802.11/files:wlan_phy_rx_blk_diag.png,nolink)]]
 
  * '''Packet Detection''': implements two packet detection schemes: simple energy detection based on RSSI and auto-correlation of the I/Q samples searching for the preamble STS, based on the well-known [http://ieeexplore.ieee.org/iel3/26/14182/00650240.pdf‎ Schmidl-Cox algorithm]. When selection diversity is enabled parallel packet detectors are enabled so that either antenna can trigger a detection.