Changes between Version 17 and Version 18 of 802.11/PHY


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Timestamp:
Dec 2, 2013, 5:55:45 AM (10 years ago)
Author:
murphpo
Comment:

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  • 802.11/PHY

    v17 v18  
    5353== Receiver Architecture ==
    5454
    55 The architecture of the 802.11 receiver FPGA core is illustrated below.
     55The architecture of the 802.11 receiver FPGA core is illustrated below. The source model is in the repository: [browser:ReferenceDesigns/w3_802.11/sysgen/wlan_phy_rx_pmd ReferenceDesigns/w3_802.11/sysgen/wlan_phy_rx_pmd].
    5656
    5757[[Image(wiki:802.11/files:wlan_phy_rx_blk_diag.png,nolink)]]
    … …  
    8383 * '''Descrambling''': the de-coded bits are finally descrambled using the LFSR specified in the standard
    8484
    85 All logic in the WLAN receiver core is clocked at 160MHz and supports a maximum bandwidth of 20MHz (clock rate = 8x max sample rate). Smaller bandwidths are supported by reducing the duty cycle of the sample_valid signal at the input to the Rx pipeline.
     85All logic in the 802.11 receiver FPGA core is clocked at 160MHz and supports a maximum bandwidth of 20MHz (clock rate = 8x max sample rate). Smaller bandwidths are supported by reducing the duty cycle of the sample_valid signal at the input to the Rx pipeline.
    8686
    8787=== DSSS ===
    … …  
    9292== Transmitter Architecture ==
    9393
    94 The architecture of the 802.11 transmitter FPGA core is illustrated below.
     94The architecture of the 802.11 transmitter FPGA core is illustrated below. The source model is in the repository: [browser:ReferenceDesigns/w3_802.11/sysgen/wlan_phy_tx_pmd ReferenceDesigns/w3_802.11/sysgen/wlan_phy_tx_pmd].
    9595
    9696[[Image(wiki:802.11/files:wlan_phy_tx_blk_diag.png,nolink)]]
    9797
    9898
    99  * '''SIGNAL Decode''':
     99 * '''Rate/Length Decode''': the length and modulation/coding rates are stored in the first 3 bytes of the packet, part of the 802.11 SIGNAl field. The Tx core uses these values to configure the relevant blocks per packet.
    100100
    101  * '''Scrambling''':
     101 * '''Scrambling''': payload bits are scrambled to avoid long runs of constant values
    102102
    103  * '''Encoding''':
     103 * '''Encoding''': payload bits are encoded by a standard 1/2 rate convolutional encoder and optionally punctured to rates 2/3 or 3/4, depending on the selected coding rate
    104104
    105  * '''Interleaving''':
     105 * '''Interleaving''': coded bits are interleaved in blocks along OFDM symbol boundaries
    106106
    107  * '''Modulation''':
     107 * '''Modulation''': the coded bits are mapped on to complex values using the selected modulation scheme. The modulated symbols are then mapped on to the data-bearing subcarriers
    108108
    109  * '''Pilot Insertion''':
     109 * '''Pilot Insertion''': four pilot tones, represented by BPSK symbols with scrambled signs, are mapped onto the dedicated subcarriers in each OFDM symbol
    110110
    111  * '''IFFT''':
     111 * '''IFFT''': the IFFT translates 64 frequency domain samples into 64 time domain samples. A 16-sample cyclic prefix is added by repeating the last 16 IFFT output samples for each OFDM symbol
    112112
    113  * '''Preamble Insertion''':
     113 * '''Preamble Insertion''': the standard 320-sample preamble is prepended to the IFFT output
    114114
    115  * '''Antenna Selection''':
     115 * '''Antenna Selection''': the complete waveform is finally transmitted via the selected RF interface
    116116
    117 
     117All logic in the 802.11 transmitter FPGA core is clocked at 160MHz and supports a maximum bandwidth of 20MHz (clock rate = 8x max sample rate). Smaller bandwidths are supported by reducing the duty cycle of the sample_valid signal at the input to the sample FIFO at the RF interface ports.