wiki:802.11/PHY

Version 10 (modified by murphpo, 10 years ago) (diff)

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802.11 Reference Design: PHY

Our physical layer implementation is based on the OFDM PHY specified in section 18 of of the 802.11-2012 standard. This PHY is commonly referred to as "802.11a" (at 5GHz) and "802.11g" (at 2.4GHz).

The source models for the PHY design are available in the repository: /ReferenceDesigns/w3_802.11/sysgen.

Architecture

The 802.11 Reference Design physical layer implementation is divided across three FPGA cores:

  • wlan_phy_tx_pmd: OFDM transmitter
  • wlan_phy_rx_pmd: OFDM and DSSS receiver
  • wlan_phy_agc: Automatic gain control (AGC)

No image "802.11/files/wlan_phy_cores_arch.png" attached to wiki

At one end the PHY cores interface directly to the ADCs and DACs on the WARP v3 hardware via the w3_ad_bridge core. These interfaces are complex sample streams running at 20MHz. At the other end the cores connect to the Tx and Rx packet buffers. The packet buffers are implemented as dual-port RAMs, each with one port dedicated to PHY access and the other port tied to the AXI interconnect for access by the CPUs.

PHY Specs

Bandwidth: 20MHz

OFDM Specs: 64 subcarriers (48 data, 4 pilots), 16-sample cyclic prefix

Frame Format: As specified in section 18.3.2 of 802.11-2012:

  • Preamble (10 repetitions of 16-sample short training symbol, 2.5 repetitions of 64-sample long training symbol)
  • SIGNAL field as first OFDM symbol (3 bytes as BSPK, rate 1/2 code)
  • Remaining OFDM symbols filled with SERVICE field (2 bytes) and payload (up to 1500 bytes) at one of the rates listed below

Rates: The following OFDM data rates are implemented. Each data rate is realized by a combination of modulation and coding rates.

Modulation
Rate
Code
Rate
Data Rate
(Mbps)
BPSK 1/2 6
BPSK 3/4 9
QPSK 1/2 12
QPSK 3/4 18
16-QAM 1/2 24
16-QAM 3/4 36
64-QAM 2/3 48
64-QAM 3/4 54

DSSS: The PHY receiver also implements the 1Mbps DSSS rate specified in the original 802.11 standard (section 16.2 of the 802.11-2012 standard). This receiver allows reception of management frames transmitted by 802.11 devices at 1Mbps. These transmissions are common in deployments of 802.11 hardware at 2.4GHz. For example, Beacon and Probe Request frames are frequently transmitted at 1Mbps by commercial devices. The basic STA/AP association handshake requires reception of these frames. The 802.11 Reference Design does not implement a DSSS transmitter, as modern 802.11 devices are able to receive management frames at higher rates (including 6Mbps, the lowest OFDM rate, which is commonly used for management frames at 5GHz).

Synchronization: The PHY implementation requires no "cheating"- all synchronization is implemented in the FPGA and operates per-packet in real time.

  • The AGC block selects Rx gains per-packet and makes no assumptions about inter-packet receive powers.
  • The CFO (carrier frequency offset) block estimates and corrects CFO per-packet. CFO estimates are extracted from the preamble long training symbols and correction is applied pre-FFT.
  • The symbol sync block establishes sample-level synchronization using a complex cross correlator tuned to the preamble long training symbols. All Rx timing is established per-packet based on the correlator output.
  • The channel estimation block computes a complex channel estimate (magnitude and phase) for each subcarrier per-packet. The equalizer applies the channel estimate per-subcarrier. The current Rx PHY uses the same channel estimates for the full packet. Extending this to a decision feedback scheme (where channel estimates are updated intra-packet) would be a straightforward extension.

Multi-antenna support: The current PHY Tx/Rx pipelines are SISO, supporting the modulation/coding rates specified in section 18 of the standard. The PHY antenna interfaces implement selection diversity across the two RF interfaces on WARP v3 hardware. The antenna selection is made per packet. For transmissions the antenna selection is always controlled by C code in CPU Low. For receptions the PHY can automatically select the higher-SNR antenna based on the AGC gain selections. Alternatively the C code in CPU Low can force the receive antenna selection.

We are also considering implementing some of the MIMO modes from 802.11n/11ac. Let us know if these would be especially useful for your research.