| | 1 | {{{#!comment |
| | 2 | [[Include(wiki:802.11/beta-note)]] |
| | 3 | }}} |
| | 4 | |
| | 5 | [[TracNav(802.11/TOC)]] |
| | 6 | |
| | 7 | = 802.11 Reference Design: Resource Usage = |
| | 8 | |
| | 9 | The 802.11 Reference Design targets the Virtex-6 LX240T FPGA on WARP v3 hardware. The FPGA resources used by the design change with each revision. The resource usage for the current release is listed below. |
| | 10 | |
| | 11 | == FPGA Resources == |
| | 12 | |
| | 13 | ||= Resource =||= Used =||= Available[[BR]]LX240T =||= Percent Used =|| |
| | 14 | || Slice Registers || 66469 || 301440 || 22% || |
| | 15 | || LUTs (total) || 61409 || 150720 || 40% || |
| | 16 | || LUTs (as logic) || 51384 || 150720 || 34% || |
| | 17 | || LUTs (as memory) || 6926 || 150720 || 11% || |
| | 18 | || Block RAMs (see note 1) || 244 || 416 || 59% || |
| | 19 | || DSP48 (multipliers) || 155 || 20% || |
| | 20 | || MMCM_ADV || 3 || 12 || 25% || |
| | 21 | || Ethernet MAC || 2 || 4 || 50% || |
| | 22 | || IOBs (see note 2) || 344 || 600 || 57% || |
| | 23 | |
| | 24 | * Note 1: the ISE MAP reports utilization of RAMB36E1 and RAMB18E1 separately, even though these represent overlapping resources in the FPGA. The block RAM usage above lists the total number of RAMB36E1 primitives in the FPGA and {{{num(RAMB36E1) + ceil(num(RAMB18E1)/2)}}} as the number used. See the MAP report below for more details. |
| | 25 | * Note 2: the IOB count includes all IOBs used by the design, not just the RF interfaces. Many of these pins are used for the DDR3 memory interface, Ethernet interfaces, user I/O, etc. |
| | 26 | |
| | 27 | |
| | 28 | |
| | 29 | == MAP Report == |
| | 30 | |
| | 31 | The resource usage section of the MAP report for the v0.95 release of the 802.11 Reference Design is copied below. |
| | 32 | |
| | 33 | You can find the full MAP report in the {{{implementation/system_map.mrp}}} file in your local copy of the 802.11 Reference Design XPS project. |
| | 34 | |
| | 35 | {{{ |
| | 36 | Release 14.4 Map P.49d (nt64) |
| | 37 | Xilinx Mapping Report File for Design 'system' |
| | 38 | |
| | 39 | Design Information |
| | 40 | ------------------ |
| | 41 | Command Line : map -mt 4 -o system_map.ncd -w -pr b -ol high -t 7 -register_duplication on -timing -detail system.ngd |
| | 42 | |
| | 43 | system.pcf |
| | 44 | Target Device : xc6vlx240t |
| | 45 | Target Package : ff1156 |
| | 46 | Target Speed : -2 |
| | 47 | Mapper Version : virtex6 -- $Revision: 1.55 $ |
| | 48 | Mapped Date : Mon Jul 14 10:01:10 2014 |
| | 49 | |
| | 50 | Design Summary |
| | 51 | -------------- |
| | 52 | Number of errors: 0 |
| | 53 | Number of warnings: 303 |
| | 54 | Slice Logic Utilization: |
| | 55 | Number of Slice Registers: 66,469 out of 301,440 22% |
| | 56 | Number used as Flip Flops: 66,312 |
| | 57 | Number used as Latches: 4 |
| | 58 | Number used as Latch-thrus: 0 |
| | 59 | Number used as AND/OR logics: 153 |
| | 60 | Number of Slice LUTs: 61,409 out of 150,720 40% |
| | 61 | Number used as logic: 51,384 out of 150,720 34% |
| | 62 | Number using O6 output only: 39,964 |
| | 63 | Number using O5 output only: 1,247 |
| | 64 | Number using O5 and O6: 10,173 |
| | 65 | Number used as ROM: 0 |
| | 66 | Number used as Memory: 6,926 out of 58,400 11% |
| | 67 | Number used as Dual Port RAM: 2,376 |
| | 68 | Number using O6 output only: 1,576 |
| | 69 | Number using O5 output only: 19 |
| | 70 | Number using O5 and O6: 781 |
| | 71 | Number used as Single Port RAM: 7 |
| | 72 | Number using O6 output only: 3 |
| | 73 | Number using O5 output only: 0 |
| | 74 | Number using O5 and O6: 4 |
| | 75 | Number used as Shift Register: 4,543 |
| | 76 | Number using O6 output only: 4,346 |
| | 77 | Number using O5 output only: 18 |
| | 78 | Number using O5 and O6: 179 |
| | 79 | Number used exclusively as route-thrus: 3,099 |
| | 80 | Number with same-slice register load: 2,828 |
| | 81 | Number with same-slice carry load: 253 |
| | 82 | Number with other load: 18 |
| | 83 | |
| | 84 | Slice Logic Distribution: |
| | 85 | Number of occupied Slices: 25,380 out of 37,680 67% |
| | 86 | Number of LUT Flip Flop pairs used: 79,536 |
| | 87 | Number with an unused Flip Flop: 20,890 out of 79,536 26% |
| | 88 | Number with an unused LUT: 18,127 out of 79,536 22% |
| | 89 | Number of fully used LUT-FF pairs: 40,519 out of 79,536 50% |
| | 90 | Number of unique control sets: 2,407 |
| | 91 | Number of slice register sites lost |
| | 92 | to control set restrictions: 9,106 out of 301,440 3% |
| | 93 | |
| | 94 | A LUT Flip Flop pair for this architecture represents one LUT paired with |
| | 95 | one Flip Flop within a slice. A control set is a unique combination of |
| | 96 | clock, reset, set, and enable signals for a registered element. |
| | 97 | The Slice Logic Distribution report is not meaningful if the design is |
| | 98 | over-mapped for a non-slice resource or if Placement fails. |
| | 99 | OVERMAPPING of BRAM resources should be ignored if the design is |
| | 100 | over-mapped for a non-BRAM resource or if placement fails. |
| | 101 | |
| | 102 | IO Utilization: |
| | 103 | Number of bonded IOBs: 344 out of 600 57% |
| | 104 | Number of LOCed IOBs: 344 out of 344 100% |
| | 105 | IOB Flip Flops: 163 |
| | 106 | IOB Master Pads: 10 |
| | 107 | IOB Slave Pads: 10 |
| | 108 | |
| | 109 | Specific Feature Utilization: |
| | 110 | Number of RAMB36E1/FIFO36E1s: 225 out of 416 54% |
| | 111 | Number using RAMB36E1 only: 225 |
| | 112 | Number using FIFO36E1 only: 0 |
| | 113 | Number of RAMB18E1/FIFO18E1s: 37 out of 832 4% |
| | 114 | Number using RAMB18E1 only: 37 |
| | 115 | Number using FIFO18E1 only: 0 |
| | 116 | Number of BUFG/BUFGCTRLs: 11 out of 32 34% |
| | 117 | Number used as BUFGs: 11 |
| | 118 | Number used as BUFGCTRLs: 0 |
| | 119 | Number of ILOGICE1/ISERDESE1s: 129 out of 720 17% |
| | 120 | Number used as ILOGICE1s: 64 |
| | 121 | Number used as ISERDESE1s: 65 |
| | 122 | Number of OLOGICE1/OSERDESE1s: 224 out of 720 31% |
| | 123 | Number used as OLOGICE1s: 99 |
| | 124 | Number used as OSERDESE1s: 125 |
| | 125 | Number of BSCANs: 2 out of 4 50% |
| | 126 | Number of BUFHCEs: 0 out of 144 0% |
| | 127 | Number of BUFIODQSs: 12 out of 72 16% |
| | 128 | Number of BUFRs: 5 out of 36 13% |
| | 129 | Number of LOCed BUFRs: 2 out of 5 40% |
| | 130 | Number of CAPTUREs: 0 out of 1 0% |
| | 131 | Number of DSP48E1s: 155 out of 768 20% |
| | 132 | Number of EFUSE_USRs: 0 out of 1 0% |
| | 133 | Number of FRAME_ECCs: 0 out of 1 0% |
| | 134 | Number of GTXE1s: 0 out of 20 0% |
| | 135 | Number of IBUFDS_GTXE1s: 0 out of 12 0% |
| | 136 | Number of ICAPs: 0 out of 2 0% |
| | 137 | Number of IDELAYCTRLs: 5 out of 18 27% |
| | 138 | Number of IODELAYE1s: 112 out of 720 15% |
| | 139 | Number of LOCed IODELAYE1s: 10 out of 112 8% |
| | 140 | Number of MMCM_ADVs: 3 out of 12 25% |
| | 141 | Number of PCIE_2_0s: 0 out of 2 0% |
| | 142 | Number of STARTUPs: 1 out of 1 100% |
| | 143 | Number of SYSMONs: 1 out of 1 100% |
| | 144 | Number of TEMAC_SINGLEs: 2 out of 4 50% |
| | 145 | |
| | 146 | Number of RPM macros: 15 |
| | 147 | Average Fanout of Non-Clock Nets: 3.61 |
| | 148 | |
| | 149 | Peak Memory Usage: 3520 MB |
| | 150 | Total REAL time to MAP completion: 1 hrs 17 secs |
| | 151 | Total CPU time to MAP completion (all processors): 1 hrs 1 mins 16 secs |
| | 152 | }}} |
