Changes between Version 19 and Version 20 of 802.11/ResourceUsage
- Timestamp:
- Sep 30, 2015, 10:33:40 AM (9 years ago)
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802.11/ResourceUsage
v19 v20 5 5 [[TracNav(802.11/TOC)]] 6 6 7 = 802.11 Reference Design v1. 2: Resource Usage =7 = 802.11 Reference Design v1.3: Resource Usage = 8 8 9 9 The 802.11 Reference Design targets the Virtex-6 LX240T FPGA on WARP v3 hardware. The FPGA resources used by the design change with each revision. The resource usage for the current release is listed below. … … 13 13 14 14 ||= Resource =||= Used =|| 15 || Slice Registers || 6 7,081out of 301,440 (22%) ||16 || LUTs || 6 1,791 out of 150,720 (40%) ||15 || Slice Registers || 68,014 out of 301,440 (22%) || 16 || LUTs || 62,838 out of 150,720 (41%) || 17 17 || Block RAMs (see note 1) || 228 of 416 (59%) || 18 18 || DSP48 (multipliers) || 155 of 768 (20%) || … … 42 42 Target Speed : -2 43 43 Mapper Version : virtex6 -- $Revision: 1.55 $ 44 Mapped Date : Tue Jan 13 10:31:48 201545 44 46 45 Design Summary … … 49 48 Number of warnings: 305 50 49 Slice Logic Utilization: 51 Number of Slice Registers: 6 7,081out of 301,440 22%52 Number used as Flip Flops: 6 6,92450 Number of Slice Registers: 68,014 out of 301,440 22% 51 Number used as Flip Flops: 67,850 53 52 Number used as Latches: 4 54 53 Number used as Latch-thrus: 0 55 Number used as AND/OR logics: 1 5356 Number of Slice LUTs: 6 1,791 out of 150,720 40%57 Number used as logic: 5 1,531 out of 150,720 34%58 Number using O6 output only: 40, 05559 Number using O5 output only: 1, 27860 Number using O5 and O6: 10, 19854 Number used as AND/OR logics: 160 55 Number of Slice LUTs: 62,838 out of 150,720 41% 56 Number used as logic: 52,411 out of 150,720 34% 57 Number using O6 output only: 40,560 58 Number using O5 output only: 1,357 59 Number using O5 and O6: 10,494 61 60 Number used as ROM: 0 62 Number used as Memory: 6, 926out of 58,400 11%63 Number used as Dual Port RAM: 2,3 7661 Number used as Memory: 6,745 out of 58,400 11% 62 Number used as Dual Port RAM: 2,384 64 63 Number using O6 output only: 1,576 65 64 Number using O5 output only: 19 66 Number using O5 and O6: 78 167 Number used as Single Port RAM: 768 Number using O6 output only: 365 Number using O5 and O6: 789 66 Number used as Single Port RAM: 31 67 Number using O6 output only: 19 69 68 Number using O5 output only: 0 70 Number using O5 and O6: 471 Number used as Shift Register: 4, 54372 Number using O6 output only: 4, 34673 Number using O5 output only: 1 874 Number using O5 and O6: 1 7975 Number used exclusively as route-thrus: 3, 33476 Number with same-slice register load: 3, 07977 Number with same-slice carry load: 2 3778 Number with other load: 1 869 Number using O5 and O6: 12 70 Number used as Shift Register: 4,330 71 Number using O6 output only: 4,130 72 Number using O5 output only: 17 73 Number using O5 and O6: 183 74 Number used exclusively as route-thrus: 3,682 75 Number with same-slice register load: 3,397 76 Number with same-slice carry load: 268 77 Number with other load: 17 79 78 80 79 Slice Logic Distribution: 81 Number of occupied Slices: 25,3 76out of 37,680 67%82 Number of LUT Flip Flop pairs used: 79,59183 Number with an unused Flip Flop: 20, 623 out of 79,59125%84 Number with an unused LUT: 17, 800 out of 79,591 22%85 Number of fully used LUT-FF pairs: 4 1,168 out of 79,591 51%86 Number of unique control sets: 2,4 6180 Number of occupied Slices: 25,354 out of 37,680 67% 81 Number of LUT Flip Flop pairs used: 80,298 82 Number with an unused Flip Flop: 20,728 out of 80,298 25% 83 Number with an unused LUT: 17,460 out of 80,298 21% 84 Number of fully used LUT-FF pairs: 42,110 out of 80,298 52% 85 Number of unique control sets: 2,458 87 86 Number of slice register sites lost 88 to control set restrictions: 9,2 22out of 301,440 3%87 to control set restrictions: 9,249 out of 301,440 3% 89 88 90 89 A LUT Flip Flop pair for this architecture represents one LUT paired with … … 97 96 98 97 IO Utilization: 99 Number of bonded IOBs: 3 44 out of 600 57%100 Number of LOCed IOBs: 3 44 out of 344100%101 IOB Flip Flops: 16 398 Number of bonded IOBs: 352 out of 600 58% 99 Number of LOCed IOBs: 352 out of 352 100% 100 IOB Flip Flops: 165 102 101 IOB Master Pads: 10 103 102 IOB Slave Pads: 10 104 103 105 104 Specific Feature Utilization: 106 Number of RAMB36E1/FIFO36E1s: 2 09out of 416 50%107 Number using RAMB36E1 only: 2 09105 Number of RAMB36E1/FIFO36E1s: 212 out of 416 50% 106 Number using RAMB36E1 only: 212 108 107 Number using FIFO36E1 only: 0 109 Number of RAMB18E1/FIFO18E1s: 3 7out of 832 4%110 Number using RAMB18E1 only: 3 7108 Number of RAMB18E1/FIFO18E1s: 39 out of 832 4% 109 Number using RAMB18E1 only: 39 111 110 Number using FIFO18E1 only: 0 112 111 Number of BUFG/BUFGCTRLs: 11 out of 32 34% 113 112 Number used as BUFGs: 11 114 113 Number used as BUFGCTRLs: 0 115 Number of ILOGICE1/ISERDESE1s: 1 29 out of 720 17%116 Number used as ILOGICE1s: 6 4114 Number of ILOGICE1/ISERDESE1s: 131 out of 720 18% 115 Number used as ILOGICE1s: 66 117 116 Number used as ISERDESE1s: 65 118 117 Number of OLOGICE1/OSERDESE1s: 224 out of 720 31% … … 141 140 142 141 Number of RPM macros: 15 143 Average Fanout of Non-Clock Nets: 3.5 9142 Average Fanout of Non-Clock Nets: 3.58 144 143 }}} 145 144
