Changes between Version 20 and Version 21 of 802.11/ResourceUsage
- Timestamp:
- Dec 11, 2015, 3:56:10 PM (8 years ago)
Legend:
- Unmodified
- Added
- Removed
- Modified
-
802.11/ResourceUsage
v20 v21 5 5 [[TracNav(802.11/TOC)]] 6 6 7 = 802.11 Reference Design v1. 3: Resource Usage =7 = 802.11 Reference Design v1.4: Resource Usage = 8 8 9 9 The 802.11 Reference Design targets the Virtex-6 LX240T FPGA on WARP v3 hardware. The FPGA resources used by the design change with each revision. The resource usage for the current release is listed below. … … 13 13 14 14 ||= Resource =||= Used =|| 15 || Slice Registers || 68,014 out of 301,440 (22%) ||16 || LUTs || 6 2,838 out of 150,720 (41%) ||17 || Block RAMs (see note 1) || 2 28of 416 (59%) ||15 || Slice Registers || 75,180 out of 301,440 (24%) || 16 || LUTs || 68,418 out of 150,720 (45%) || 17 || Block RAMs (see note 1) || 241 of 416 (59%) || 18 18 || DSP48 (multipliers) || 155 of 768 (20%) || 19 19 || MMCM_ADV || 3 of 12 (25%) || 20 20 || Ethernet MAC || 2 of 4 (50%) || 21 || IOBs (see note 2) || 3 44 of 600 (57%) ||21 || IOBs (see note 2) || 352 of 600 (58%) || 22 22 23 23 * '''Note 1''': the ISE MAP reports utilization of RAMB36E1 and RAMB18E1 separately, even though these represent overlapping resources in the FPGA (each RAMB36E1 can be used as 2 RAMB18E1). The block RAM usage above lists the total number of RAMB36E1 primitives in the FPGA and {{{num(RAMB36E1) + ceil(num(RAMB18E1)/2)}}} as the number used. See the MAP report below for more details. … … 42 42 Target Speed : -2 43 43 Mapper Version : virtex6 -- $Revision: 1.55 $ 44 Mapped Date : Wed Dec 09 11:59:51 2015 44 45 45 46 Design Summary 46 47 -------------- 47 48 Number of errors: 0 48 Number of warnings: 3 0549 Number of warnings: 353 49 50 Slice Logic Utilization: 50 Number of Slice Registers: 68,014 out of 301,440 22%51 Number used as Flip Flops: 67,85051 Number of Slice Registers: 75,180 out of 301,440 24% 52 Number used as Flip Flops: 75,003 52 53 Number used as Latches: 4 53 54 Number used as Latch-thrus: 0 54 Number used as AND/OR logics: 1 6055 Number of Slice LUTs: 6 2,838 out of 150,720 41%56 Number used as logic: 5 2,411 out of 150,720 34%57 Number using O6 output only: 4 0,56058 Number using O5 output only: 1, 35759 Number using O5 and O6: 1 0,49455 Number used as AND/OR logics: 173 56 Number of Slice LUTs: 68,418 out of 150,720 45% 57 Number used as logic: 56,953 out of 150,720 37% 58 Number using O6 output only: 43,609 59 Number using O5 output only: 1,469 60 Number using O5 and O6: 11,875 60 61 Number used as ROM: 0 61 Number used as Memory: 6,745 out of 58,400 11%62 Number used as Dual Port RAM: 2, 38463 Number using O6 output only: 1,5 7664 Number using O5 output only: 1965 Number using O5 and O6: 78962 Number used as Memory: 7,463 out of 58,400 12% 63 Number used as Dual Port RAM: 2,526 64 Number using O6 output only: 1,546 65 Number using O5 output only: 29 66 Number using O5 and O6: 951 66 67 Number used as Single Port RAM: 31 67 68 Number using O6 output only: 19 68 69 Number using O5 output only: 0 69 70 Number using O5 and O6: 12 70 Number used as Shift Register: 4, 33071 Number using O6 output only: 4, 13071 Number used as Shift Register: 4,906 72 Number using O6 output only: 4,706 72 73 Number using O5 output only: 17 73 74 Number using O5 and O6: 183 74 Number used exclusively as route-thrus: 3,68275 Number with same-slice register load: 3, 39776 Number with same-slice carry load: 2 6877 Number with other load: 1775 Number used exclusively as route-thrus: 4,002 76 Number with same-slice register load: 3,228 77 Number with same-slice carry load: 292 78 Number with other load: 482 78 79 79 80 Slice Logic Distribution: 80 Number of occupied Slices: 2 5,354 out of 37,680 67%81 Number of LUT Flip Flop pairs used: 8 0,29882 Number with an unused Flip Flop: 2 0,728 out of 80,29825%83 Number with an unused LUT: 1 7,460 out of 80,298 21%84 Number of fully used LUT-FF pairs: 4 2,110 out of 80,29852%85 Number of unique control sets: 2, 45881 Number of occupied Slices: 28,065 out of 37,680 74% 82 Number of LUT Flip Flop pairs used: 88,389 83 Number with an unused Flip Flop: 22,102 out of 88,389 25% 84 Number with an unused LUT: 19,971 out of 88,389 22% 85 Number of fully used LUT-FF pairs: 46,316 out of 88,389 52% 86 Number of unique control sets: 2,858 86 87 Number of slice register sites lost 87 to control set restrictions: 9,249out of 301,440 3%88 to control set restrictions: 10,800 out of 301,440 3% 88 89 89 90 A LUT Flip Flop pair for this architecture represents one LUT paired with … … 98 99 Number of bonded IOBs: 352 out of 600 58% 99 100 Number of LOCed IOBs: 352 out of 352 100% 100 IOB Flip Flops: 16 5101 IOB Flip Flops: 167 101 102 IOB Master Pads: 10 102 103 IOB Slave Pads: 10 103 104 104 105 Specific Feature Utilization: 105 Number of RAMB36E1/FIFO36E1s: 2 12 out of 416 50%106 Number using RAMB36E1 only: 2 12106 Number of RAMB36E1/FIFO36E1s: 221 out of 416 53% 107 Number using RAMB36E1 only: 221 107 108 Number using FIFO36E1 only: 0 108 Number of RAMB18E1/FIFO18E1s: 39out of 832 4%109 Number using RAMB18E1 only: 39109 Number of RAMB18E1/FIFO18E1s: 41 out of 832 4% 110 Number using RAMB18E1 only: 41 110 111 Number using FIFO18E1 only: 0 111 112 Number of BUFG/BUFGCTRLs: 11 out of 32 34% … … 140 141 141 142 Number of RPM macros: 15 142 Average Fanout of Non-Clock Nets: 3.58 143 144 Average Fanout of Non-Clock Nets: 3.61 143 145 }}} 144 146
