Changes between Version 34 and Version 35 of 802.11/ResourceUsage
- Timestamp:
- Feb 15, 2017, 9:30:53 AM (7 years ago)
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802.11/ResourceUsage
v34 v35 5 5 [[TracNav(802.11/TOC)]] 6 6 7 = 802.11 Reference Design v1.6. 0: Resource Usage =7 = 802.11 Reference Design v1.6.1: Resource Usage = 8 8 9 9 The 802.11 Reference Design targets the Virtex-6 LX240T FPGA on WARP v3 hardware. The FPGA resources used by the design change with each revision. The resource usage for the current release is listed below. 10 10 11 11 == FPGA Resources == 12 The table below summarizes the FPGA resource usage for v0.96of the 802.11 Reference Design.12 The table below summarizes the FPGA resource usage for the current version of the 802.11 Reference Design. 13 13 14 14 ||= Resource =||= Used =|| 15 || Slice Registers || 79,8 19out of 301,440 (26%) ||16 || LUTs || 71, 422out of 150,720 (47%) ||17 || Block RAMs (see note 1) || 2 53 of 416 (60%) ||15 || Slice Registers || 79,820 out of 301,440 (26%) || 16 || LUTs || 71,270 out of 150,720 (47%) || 17 || Block RAMs (see note 1) || 269 of 416 (65%) || 18 18 || DSP48 (multipliers) || 182 of 768 (23%) || 19 19 || MMCM_ADV || 3 of 12 (25%) || … … 46 46 -------------- 47 47 Number of errors: 0 48 Number of warnings: 35 248 Number of warnings: 354 49 49 Slice Logic Utilization: 50 Number of Slice Registers: 79,8 19out of 301,440 26%51 Number used as Flip Flops: 79,65 750 Number of Slice Registers: 79,820 out of 301,440 26% 51 Number used as Flip Flops: 79,658 52 52 Number used as Latches: 4 53 53 Number used as Latch-thrus: 0 54 54 Number used as AND/OR logics: 158 55 Number of Slice LUTs: 71, 422out of 150,720 47%56 Number used as logic: 58,1 48out of 150,720 38%57 Number using O6 output only: 44,29 558 Number using O5 output only: 1,4 7359 Number using O5 and O6: 12,3 8055 Number of Slice LUTs: 71,270 out of 150,720 47% 56 Number used as logic: 58,157 out of 150,720 38% 57 Number using O6 output only: 44,293 58 Number using O5 output only: 1,485 59 Number using O5 and O6: 12,379 60 60 Number used as ROM: 0 61 Number used as Memory: 7,89 0out of 58,400 13%61 Number used as Memory: 7,893 out of 58,400 13% 62 62 Number used as Dual Port RAM: 2,522 63 63 Number using O6 output only: 1,546 … … 68 68 Number using O5 output only: 0 69 69 Number using O5 and O6: 12 70 Number used as Shift Register: 5,3 3771 Number using O6 output only: 4,89 772 Number using O5 output only: 1 773 Number using O5 and O6: 42 374 Number used exclusively as route-thrus: 5, 38475 Number with same-slice register load: 4, 41876 Number with same-slice carry load: 4 9370 Number used as Shift Register: 5,340 71 Number using O6 output only: 4,899 72 Number using O5 output only: 19 73 Number using O5 and O6: 422 74 Number used exclusively as route-thrus: 5,220 75 Number with same-slice register load: 4,269 76 Number with same-slice carry load: 478 77 77 Number with other load: 473 78 78 79 79 Slice Logic Distribution: 80 Number of occupied Slices: 28, 620out of 37,680 75%81 Number of LUT Flip Flop pairs used: 91, 11382 Number with an unused Flip Flop: 22,23 1 out of 91,11324%83 Number with an unused LUT: 19, 691 out of 91,11321%84 Number of fully used LUT-FF pairs: 49, 191 out of 91,11353%85 Number of unique control sets: 2,82 880 Number of occupied Slices: 28,494 out of 37,680 75% 81 Number of LUT Flip Flop pairs used: 91,232 82 Number with an unused Flip Flop: 22,235 out of 91,232 24% 83 Number with an unused LUT: 19,962 out of 91,232 21% 84 Number of fully used LUT-FF pairs: 49,035 out of 91,232 53% 85 Number of unique control sets: 2,826 86 86 Number of slice register sites lost 87 to control set restrictions: 10,5 93out of 301,440 3%87 to control set restrictions: 10,534 out of 301,440 3% 88 88 89 89 A LUT Flip Flop pair for this architecture represents one LUT paired with … … 103 103 104 104 Specific Feature Utilization: 105 Number of RAMB36E1/FIFO36E1s: 2 35 out of 416 56%106 Number using RAMB36E1 only: 2 35105 Number of RAMB36E1/FIFO36E1s: 251 out of 416 60% 106 Number using RAMB36E1 only: 251 107 107 Number using FIFO36E1 only: 0 108 108 Number of RAMB18E1/FIFO18E1s: 36 out of 832 4% … … 115 115 Number used as ILOGICE1s: 43 116 116 Number used as ISERDESE1s: 65 117 Number of OLOGICE1/OSERDESE1s: 18 9 out of 720 26%118 Number used as OLOGICE1s: 6 4117 Number of OLOGICE1/OSERDESE1s: 187 out of 720 25% 118 Number used as OLOGICE1s: 62 119 119 Number used as OSERDESE1s: 125 120 120 Number of BSCANs: 2 out of 4 50% … … 140 140 141 141 Number of RPM macros: 15 142 Average Fanout of Non-Clock Nets: 3.5 3142 Average Fanout of Non-Clock Nets: 3.54 143 143 }}} 144 144
