Changes between Version 4 and Version 5 of Exercises/13_4/IntroToXPS/w2


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Timestamp:
Dec 7, 2012, 11:07:35 AM (11 years ago)
Author:
chunter
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  • Exercises/13_4/IntroToXPS/w2

    v4 v5  
    1919
    2020* Ports: Shown in yellow in the above figure, ports allow direct connectivity between peripherals. They can serve as inputs or outputs of the design.
    21 * Registers: Shown in red in the above figure, registers allow peripherals to be controlled by software running in a Microblaze soft processor. Registers allow the core to hang off a bus such as the Processor Local Bus (PLB) and allow custom C-code to read or write memory addresses to control the core.
     21* Registers: Shown in red in the above figure, registers allow peripherals to be controlled by software running in a PowerPC core. Registers allow the core to hang off a bus such as the Processor Local Bus (PLB) and allow custom C-code to read or write memory addresses to control the core.
    2222
    2323The prng_useriosrc pcore has the following inputs and outputs:
    … …  
    2525 === Inputs ===
    2626 * User I/O Pushbutton Port: This port is connected directly to the User I/O "up" pushbutton port. When the user presses the button on the board, the latch inside the prng_useriosrc core will stop updating the outputs. This will effectively "pause" the core and allow the user to read the current set of outputs from the LEDs and other display elements.
    27  * Capture Period Register: This register attaches to the bus and allows C-code executing inside the MicroBlaze to control how often the latch on the LFSR triggers. In effect, this is a way for C-code to control how fast the output updates occur. Note: even though we have listed this as an input to the core, this register can also be read by the C-code in order to check and see what it had been set to.
     27 * Capture Period Register: This register attaches to the bus and allows C-code executing inside the PowerPC to control how often the latch on the LFSR triggers. In effect, this is a way for C-code to control how fast the output updates occur. Note: even though we have listed this as an input to the core, this register can also be read by the C-code in order to check and see what it had been set to.
    2828
    2929 === Outputs ===
    3030* Left/Right Hex Display Ports: The left and right hexadecimal displays contain seven individual on/off segments. These output ports drive 7-bit wide random numbers to the equivalent input ports on the User I/O core.
    3131* Red/Green LED Ports: The banks of red and green LEDs each contain 4 elements. These 4-bit wide random numbers drive the equivalent input ports on the User I/O core.
    32 * Captured Output Register: This register attaches to the bus and allows C-code executing inside the MicroBlaze to read the current latched output of the LFSR.
     32* Captured Output Register: This register attaches to the bus and allows C-code executing inside the PowerPC to read the current latched output of the LFSR.
    3333
    3434You will also notice in the diagram the green "FPGA Pins" ports. These are top-level ports that are routed out to physical pins on the FPGA. These pins are connected to other components on the WARP board. For the purpose of this exercise, we have provided this pcore as an example of a hardware peripheral you may want to integrate into your design. The [wiki:Exercises/13_4/SysgenExportPcore Exporting pcores from System Generator] exercise covers how this pcore was created.
    … …  
    4747[[Image(projecttab.png)]]
    4848
    49 6. Add the following chunk of code to the bottom of the system.mhs file:
     496. Find the line of code near the top of the tile that starts with "PORT fpga_0_UserIO_LEDs_out_pin =" and replace it with the following:
     50
     51{{{
     52PORT fpga_0_UserIO_LEDs_out_pin = GreenLEDs & RedLEDs, DIR = O, VEC = [0:7]
     53}}}
     54
     55This chunk of core attaches the 8 User I/O LED pins to two new nets of 4 bits each. We'll hook these nets up to the new "prng_useriosrc" pcore.
     56
     577. Find the following line and delete it:
     58
     59{{{
     60PORT LEDs_out = fpga_0_UserIO_LEDs_out_pin
     61}}}
     62
     63This is in the "warp_v4_userio" core. Basically, we are going to hijack control of the LEDs away from the User I/O core and attach it to our new "prng_useriosrc" core instead.
     64
     658. Add the following two instances at the bottom of the MHS file:
    5066
    5167{{{
    … …  
    5571 PARAMETER C_BASEADDR = 0xc4000000
    5672 PARAMETER C_HIGHADDR = 0xc400ffff
    57  BUS_INTERFACE SPLB = plb_secondary_80MHz
    58  PORT sysgen_clk = clk_80MHz
    59  PORT hexdisp_left = LeftHexDisplay
    60  PORT hexdisp_right = RightHexDisplay
     73 BUS_INTERFACE SPLB = plb
     74 PORT sysgen_clk = clk_80_0000MHzDCM0
    6175 PORT leds_green = GreenLEDs
    6276 PORT leds_red = RedLEDs
    6377 PORT pause = UpPushbutton
    6478END
     79
     80BEGIN util_bus_split
     81 PARAMETER INSTANCE = util_bus_split_0
     82 PARAMETER HW_VER = 1.00.a
     83 PARAMETER C_SIZE_IN = 4
     84 PARAMETER C_SPLIT = 1
     85 PORT Sig = fpga_0_UserIO_PB_in_pin
     86 PORT Out1 = UpPushbutton
     87 PORT Out2 = net_gnd
     88END
    6589}}}
    6690
    67 This chunk of code will instantiate the prng_useriosrc core in the design and attaches it to the bus (here, the plb_secondary_80MHz bus). Additionally, it attaches the input/output ports of core to some unique net names (LeftHexDisplay, RightHexDisplay, GreenLEDs, RedLEDs, and UpPushbutton). These net names are arbitrary; the important thing is that the names match on the corresponding ports to whatever the core is connected to.
     91The first creates and instance of the "prng_useriosrc" core, attaches it to the 80MHz bus, and attaches nets to its ports. The second instance simply slices off 1 bit from a bus of pushbuttons and attaches it to a net that is connected to the pause input port on the new core.
    6892
    69 7. Find the chunk of code that starts with "BEGIN w3_userio." Before the "END" line, add the following port connections:
     939. Click File→Save. You will be asked if you want to reload the project; click "Reload." At this point, you may wonder how you are supposed to know the names of ports themselves. Unfortunately, ports that are floating (i.e. disconnected) do not show up in the system.mhs file. The best way to find a full list of all ports a pcore has is by looking at its entry in the "System Assembly View" tab. In the next step, we'll be looking at this view to verify that the prng_useriosrc pcore is correctly hooked up to the system.
    7094
    71 {{{
    72  PORT usr_hexdisp_left = LeftHexDisplay
    73  PORT usr_hexdisp_right = RightHexDisplay
    74  PORT usr_leds_green = GreenLEDs
    75  PORT usr_leds_red = RedLEDs
    76  PORT usr_pb_u = UpPushbutton
    77 }}}
    78 
    79 This connects the ports from the prng_useriosrc_plbw to the appropriate ports on the User I/O core. Click File→Save. You will be asked if you want to reload the project; click "Reload." At this point, you may wonder how you are supposed to know the names of ports themselves. Unfortunately, ports that are floating (i.e. disconnected) do not show up in the system.mhs file. The best way to find a full list of all ports a pcore has is by looking at its entry in the "System Assembly View" tab. In the next step, we'll be looking at this view to verify that the prng_useriosrc pcore is correctly hooked up to the system.
    80 
    81 8. Open the System Assembly View tab and make sure you are looking at the "Bus Interfaces" subtab. To the left of prng_useriosrc_plbw_0, you see a yellow circle connecting the core to the plb_secondary_80MHz bus. Unconnected pcores show an empty, white circle.
     951. Open the System Assembly View tab and make sure you are looking at the "Bus Interfaces" subtab. To the left of prng_useriosrc_plbw_0, you see a yellow circle connecting the core to the plb_secondary_80MHz bus. Unconnected pcores show an empty, white circle.
    8296
    8397[[Image(busconnection.png)]]
    8498
    85 9. Next, click on the "Ports" subtab. Click the + next to the w3_userio_0 core and the prng_useriosrc_plbw_0 core. The names shown next to the port are ''not'' the arbitrary net names we gave earlier (e.g. LeftHexDisplay). Instead, this GUI shows ''what'' core each port is connected. It should look like this:
     9911. Next, click on the "Ports" subtab. Click the + next to the w3_userio_0 core and the prng_useriosrc_plbw_0 core. The names shown next to the port are ''not'' the arbitrary net names we gave earlier (e.g. LeftHexDisplay). Instead, this GUI shows ''what'' core each port is connected. It should look like this:
    86100
    87101[[Image(portconnection.png)]]
    88102
    89 10. Finally, click the "Addresses" subtab. In the bottom of the window, you will see the prng_useriosrc_plbw_0 core belongs to a class of "Unmapped Addresses." Each register needs to be mapped to a memory address in order for the C-code in the MicroBlaze to be able to read or write to it. Simply click the button in the upper right of the window to "Generate Addresses."
     10312. Finally, click the "Addresses" subtab. In the bottom of the window, you will see the prng_useriosrc_plbw_0 core belongs to a class of "Unmapped Addresses." Each register needs to be mapped to a memory address in order for the C-code in the PowerPC to be able to read or write to it. Simply click the button in the upper right of the window to "Generate Addresses."
    90104
    91105[[Image(generateaddresses.png)]]
    92106
    93 If successful, the "Unmapped Addresses" grouping will disappear and prng_useriosrc_plbw_0 will join the rest of the cores in the MicroBlaze's memory map.
     107If successful, the "Unmapped Addresses" grouping will disappear and prng_useriosrc_plbw_0 will join the rest of the cores in the PowerPC's memory map.
    94108
    95 11. Now click the "Generate BitStream" on the far left of the window. This will take ~10 minutes on a fast computer.
     10913. Now click the "Generate BitStream" on the far left of the window. This will take ~10 minutes on a fast computer.
    961101. Once the project has finished generating the BitStream, click the "Export Design" button with the SDK logo on the far left of the window. Then click "Export & Launch SDK."
    971111. The SDK will launch and will pull up a window for you to select your workspace. Navigate to the SDK_workspace folder you cleared out at the beginning of these instructions. Then click "OK."
    … …  
    104118[[Image(newbutton.jpeg)]]
    105119
    106 17. Click on "Xilinx Board Support Package" and click "Next."
     12018. Click on "Xilinx Board Support Package" and click "Next."
    1071211. Click "Finish."
    1081221. A new window will pop-up that allows you configure the BSP with various optional software packages. For the purposes of this exercise, the default settings are fine. Just click OK. You will see the console at the bottom of the screen start printing messages as the SDK compiles the BSP. It will end up with "Finished building libraries" printed to the console.