Changes between Version 9 and Version 10 of GettingStarted/WARPv3/Hardware


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Timestamp:
Jun 20, 2013, 1:59:31 PM (9 years ago)
Author:
murphpo
Comment:

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  • GettingStarted/WARPv3/Hardware

    v9 v10  
    1313
    1414 * '''User I/O:''' This collection of push buttons, LEDs, hexadecimal displays, dip switches, and debug header pins is used for interacting with the board. Designs can read values from the switches and push buttons and can write values to the displays and LEDs. The debug header can be used for any number of purposes, such as providing a convenient way for one WARP board to trigger the action of another board over a wire.
    15  * '''Radio Interfaces A & B:''' There interfaces provide the radios that allow designs to communicate at the 2.4GHz and 5GHz bands. For each radio interface, digital I and Q values from the FPGA are taken through digital-to-analog converters and are delivered to the transceiver for upconversion (i.e. wireless transmission). Wireless reception follows the reciprocal process where I and Q analog streams are taken from the transceiver through analog-to-digital conversion and are then delivered to the FPGA. The interfaces are labeled "RF A" and "RF B" on the board and in our reference designs.
     15 * '''Radio Interfaces A & B:''' These interfaces provide the radios that allow designs to communicate at the 2.4GHz and 5GHz bands. For each radio interface, digital I and Q values from the FPGA are taken through digital-to-analog converters and are delivered to the transceiver for upconversion (i.e. wireless transmission). Wireless reception follows the reciprocal process where I and Q analog streams are taken from the transceiver through analog-to-digital conversion and are then delivered to the FPGA. The interfaces are labeled "RF A" and "RF B" on the board and in our reference designs.
    1616 * '''SDRAM:''' This DDR3 SO-DIMM provides extra memory beyond the block RAM inside the FPGA. The WARP v3 kit ships with a pre-tested 2GB SO-DIMM.
    1717 * '''Device label:''' This label shows the FPGA device on the WARP v3 board. This device is used in a number of places during the development process (such as exporting a peripheral core from Xilinx System Generator), so this label is present for convenient lookup.
     
    4141=== Overheating Protection ===
    4242
    43 The Xilinx Virtex-6 FPGA can generate significant amounts of heat when running complex design. It is important that the supplied fan be running whenever the board is in use. For the fan to run, a jumper needs to be present.
     43The Xilinx Virtex-6 FPGA can generate significant amounts of heat when running complex designs. It is important that the supplied fan be running whenever the board is in use. For the fan to run, a jumper needs to be present.
    4444
    4545[[Image(wiki:GettingStarted/WARPv3/files:warpv3_fanjumper.jpg,nolink,valign=middle)]]