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Configuration

v3	v4
36	36	Refer to the [wiki:cores/w3_clock_controller w3_clock_controller] documentation for details on the default use of these switches in the reference designs for WARP v3.
37	37
	38	----
	39
38	40	= AD9511 SPI Control =
39	41	The CM-PLL is built around the [http://www.analog.com/en/products/clock-and-timing/clock-generation-distribution/ad9511.html Analog Devices AD9511 PLL]. The AD9511 is configured primarily via its internal register bank. Individual registers can be read and written via an SPI interface. The CM-PLL design connects this SPI interface to dedicated FPGA I/O. The AD9511 default register values do not result in a valid configuration for the WARP v3 + CM-PLL hardware. The user FPGA design must integrate an SPI controller to configure the AD9511 registers at boot. Refer to the [http://www.analog.com/media/en/technical-documentation/data-sheets/AD9511.pdf AD9511 datasheet] for details on the device's register bank.