WARP Clock Board Connectors

Connector In/Out Function Connection
J6/J10/J11/J12 Outputs Identical radio reference clock outputs Connect to radio boards via coaxial cable
J7/J8/J9/J13 Outputs Identical sampling clock outputs Connect to radio boards via twisted pair cable
J2 Input External radio reference input Optionally connect to J4 on primary clock board
J4 Output External radio reference output Optionall connect to J2 on secondary clock board
J3 Input External sampling clock input Optionally connect to J5 on primary clock board
J5 Output External sampling clock output Optionally connect to J3 on secondary clock board

Differential Connectors

The four sampling clock outputs (J7/J8/J9/J13) have four pins- 2 for ground and 2 for each half of the differential clock signal. The mapping of signals to these four connectors is illustrated below. The connections from these headers to the Radio Board sampling clock header must be consistent across all boards in a kit and with the clocking configuration in the FPGA design.

See the Clock Connection howto for the recommend connections which are compatible with the WARP reference designs.

Last modified 12 years ago Last modified on Sep 26, 2012, 5:02:26 PM