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Connectors

-                      v1
+                      v2
 === Differential Connectors ===
+The four sampling clock outputs (J7/J8/J9/J13) have four pins- 2 for ground and 2 for each half of the differential clock signal. The mapping of signals to these four connectors is illustrated below. The polarity of these clock signals must match the polarity of the clock input at the radio board.
+The four sampling clock outputs (J7/J8/J9/J13) have four pins- 2 for ground and 2 for each half of the differential clock signal. The mapping of signals to these four connectors is illustrated below. The connections from these headers to the Radio Board sampling clock header must be consistent across all boards in a kit and with the clocking configuration in the FPGA design.
+See the [wiki:howto/connectclocks Clock Connection howto] for the recommend connections which are compatible with the WARP reference designs.
 [[Image(HardwareUsersGuides/ClockBoard_v1.1/Images:Clock_Board_posNegConnectors.png)]]