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== WARP FPGA Board Clocking ==

=== On-board Oscillators ===
The FPGA board has two oscillator footprints for general clocks. By default, one 100MHz oscillator is mounted (component Y5) and one footprint is left empty (component Y6) for future customization. Both oscillator footprints are connected to global clock (GCLK) pins on the FPGA.

The Virtex-II Pro FPGA contains 8 Digital Clock Managers (DCM) which can synthesize a wide range of clock signals given the 100MHz oscillator input.

|| '''Clock''' || '''Component''' || '''FPGA Pin''' ||
|| 100MHz || Y5 || AH21 ||
|| NM || Y6 || AH20 ||

=== Off-board Clock Sources ===
The FPGA board has a header dedicated to off-board clocks. This header (component  J29) is  used by the [wiki:HardwareUsersGuides/ClockBoard WARP Clock Board]. The header connects to four global clock (GCLK) pins on the FPGA, the 3.3v power plane and 8 general FPGA I/O.

[[Image(HardwareUsersGuides/FPGABoard_v1.2/Images:FPGA_Board_ClkHeader.jpg)]]

|| '''Header Pin''' || '''FPGA GCLK''' || '''FPGA Pin''' ||
|| 3 || GCLK0P || AK20 ||
|| 4 || GCLK1S || AL20 ||
|| 7 || GCLK6P || AT20 ||
|| 8 || GCLK7S || AR20 ||

=== SystemACE CF Clocking ===
The SystemACE CF controller requires a 33MHz clock which runs at all times. The FPGA requires a copy of this clock in order to use the SystemACE controller's microprocessor interface. A dedicated 33MHz oscillator (component Y4) is used on the FPGA board to supply this clock. The oscillator's output is split and driven to both the FPGA and the SystemACE CF controller.

|| '''Clock''' || '''Component''' || '''FPGA''' '''Pin''' ||
|| 33MHz || Y4 || N20 ||

=== MGT Clocking ===
Please see [wiki:HardwareUsersGuides/FPGABoard_v1.2/MGTs#Clocking MGTs] for details on clocking the FPGA's multi-gigabit transceivers.

=== Other References ===
 * [http://direct.xilinx.com/bvdocs/publications/ds083.pdf Xilinx Virtex-II Pro Datasheet] (Module 3: DC & Switching Characteristics)
 * [http://direct.xilinx.com/bvdocs/userguides/ug012.pdf Xilinx Virtex-II Pro Users Guide] (Chapter 2: Timing Models and Chapter 3: Digital Clock Managers)
 * [source:/Hardware/FPGA_Board/Rev1.2/Schematics_FPGABoard_1.2.pdf WARP FPGA Board Schematics] (pg. 2)