Changes between Version 5 and Version 6 of HardwareUsersGuides/FPGABoard_v1.2/MGTs


Ignore:
Timestamp:
Jul 9, 2007, 2:06:47 PM (17 years ago)
Author:
murphpo
Comment:

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  • HardwareUsersGuides/FPGABoard_v1.2/MGTs

    v5 v6  
    1010[[Image(HardwareUsersGuides/FPGABoard_v1.2/Images:FPGA_Board_MGTs.jpg)]]
    1111
     12|| MGT || FPGA Instance || Tx +/- Pins || Rx +/- Pins ||
     13|| 1 || GT_X1Y1 || A35/A36 || A34/A33 ||
     14|| 2 || GT_X2Y1 || A31/A32 || A30/A29 ||
     15|| 3 || GT_X3Y1 || A27/A28 || A26/A25 ||
     16|| 4 || GT_X4Y1 || A23/A24 || A22/A21 ||
     17|| 5 || GT_X5Y1 || A18/A19 || A17/A16 ||
     18|| 6 || GT_X6Y1 || A14/A15 || A13/A12 ||
     19|| 7 || GT_X7Y1 || A10/A11 || A9/A8 ||
     20|| 8 || GT_X9Y1 || A6/A7 || A5/A4 ||
     21
    1222=== MGT Clocking ===
    1323
    … …  
    1626The MGTs require clocks driven into specific pins on the FPGA, refered to as BREFCLK and BREFCLK2. The left oscillator (component Y1) drives BREFCLK; the right oscillator (component Y3) drives BREFCLK2. The pin mapping for these clock signals are:
    1727
    18 || '''Clk Input''' || '''Schematic Name'' || '''FPGA Pin''' ||
     28|| '''Clk Input''' || '''Schematic Name''' || '''FPGA Pin''' ||
    1929|| BREFCLK+ || MGT_CLK0P || E20 ||
    2030|| BREFCLK- || MGT_CLK0N || D20 ||