WARP FPGA Board Clocking

On-board Oscillators

The FPGA board has two oscillator footprints for general clocks. By default, one 100MHz oscillator is mounted (component Y7) and one footprint is left empty (component Y9) for future customization. Both oscillator footprints are connected to global clock (GCLK) pins on the FPGA.

Clock	Component	FPGA Pin
100MHz	Y7	AM21
NM	Y9	AL20

Off-board Clock Sources

The FPGA board has a header dedicated to off-board clocks. This header (component J25) is used by the WARP Clock Board. The header connects to two global clock (GCLK) pairs on the FPGA (allowing for differential clocks), the 3.3v power plane and 8 general FPGA I/O.

Header Pin	FPGA Pin
3	AP22
4	AP21
7	AN20
8	AP20

SystemACE CF Clocking

The SystemACE CF controller requires a 33MHz clock which runs at all times. The FPGA requires a copy of this clock in order to use the SystemACE controller's microprocessor interface. A dedicated 33MHz oscillator (component Y6) is used on the FPGA board to supply this clock. The oscillator's output is split and driven to both the FPGA and the SystemACE CF controller.

Clock	Component	FPGA Pin
33MHz	Y4	AJ21

MGT Clocking

Please see MGTs for details on clocking the FPGA's multi-gigabit transceivers.

Constraints

#FPGA Board v2.2 Clock Constraints
#
# The constraints using the onboard 100MHz oscillator
Net sys_clk_pin LOC=AM21;
Net sys_clk_pin IOSTANDARD = LVTTL;
Net sys_clk_pin TNM_NET = sys_clk_pin;
TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 10000 ps;
#
# The constraints using the Clock Board generated 40MHz
# clock for the design. NOTE: The clock_board_configurator
# must be instantiated to configure the clock board
Net sys_clk_pin LOC=AN20;
Net sys_clk_pin IOSTANDARD = LVTTL;
Net sys_clk_pin TNM_NET = sys_clk_pin;
TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 25000 ps;

Other References

• ​Xilinx Virtex-II Pro Datasheet (Module 3: DC & Switching Characteristics)
• ​Xilinx Virtex-II Pro Users Guide (Chapter 2: Timing Models and Chapter 3: Digital Clock Managers)
• WARP FPGA Board Schematics​ (pg. 2)