[[TracNav(HardwareUsersGuides/FPGABoard_v2.2/TOC)]] == WARP FPGA Board Ethernet == The FPGA Board has one 10/100/1000 Ethernet device present. The design uses the [http://www.marvell.com/files/products/transceivers/singleport/Alaska_SinglePort_88E1111.pdf Marvell 88e1111 Gigabit Ethernet PHY]. The Marvell PHY implements all the physical layer functionality and the Virtex-4 FPGA uses one of the hardened Tri-mode Ethernet MAC for the MAC layer. Any MAC layer implementation in the Virtex-4 utilizes the hard TEMAC and the soft [http://www.xilinx.com/support/documentation/ip_documentation/xps_ll_temac.pdf LocalLink TEMAC]. [[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:FPGABoard_Ethernet.jpg, align=right, 250px)]] There are six status LEDs (D1 - D6) which show the status of the physical layer link. || '''Label''' || '''LED Color''' || '''Status''' || || Tx || Green || Lights up during packet transmission || || Rx || Green || Lights up during packet reception || || Duplex || Red || Indicates the successful negotiation of a duplex link || || 10 || Red || Indicates negotiated speed of 10 Mbps || || 100 || Red || Indicates negotiated speed of 100 Mbps || || 1000 || Red || Indicates negotiated speed of 1 Gbps || The auto-negotiated speeds are between the physical layers of the two Ethernet devices. The Ethernet MAC must still be informed of the correct speed to use or the auto-negotiation callback must be implemented. == FPGA Constraints == [[Include(source:Hardware/FPGA_Board/Rev2.2/UCF/WARP_FPGA_v2.2_Ethernet.ucf, text/x-sh)]]