Changes between Version 9 and Version 10 of HardwareUsersGuides/FPGABoard_v2.2/MGTs

Timestamp:

Sep 18, 2009, 10:38:41 PM (15 years ago)

Author:

sgupta

Comment:

--

HardwareUsersGuides/FPGABoard_v2.2/MGTs

@@ -33 +33 @@
 === MGT Clocking ===
 
-As mentioned, each MGT column has two input clocks that are shared. Any of the MGT tiles in that column can use th
+As mentioned, each MGT column has two input clocks that are shared. Any of the MGT tiles in that column share the clocks. In column 0 the clock inputs are located at tile 102 and tile 105. In column 1, the inputs are tile 10 and tile 13. There is an elaborate clock multiplexor scheme on the board that lets the user choose three of the four clock inputs.
+
+|| '''Clock''' || '''Tile''' || '''P Constraint''' || '''N Constraint''' || '''Clock Frequency/Clock Mux''' ||
+|| MGTCLK_102 || 102 || F39 || G39 || Mux2 ||
+|| MGTCLK_105 || 105 || AW34 || AW33 || Mux3 ||
+|| MGTCLK_110 || 110 || AW6 || AW7 || 300 MHz ||
+|| MGTCLK_113 || 113 || F1 || G1 || Mux1 ||
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+