Changes between Version 10 and Version 11 of HardwareUsersGuides/FPGABoard_v2.2/MGTs

Timestamp:

Sep 18, 2009, 10:49:31 PM (15 years ago)

Author:

sgupta

Comment:

--

HardwareUsersGuides/FPGABoard_v2.2/MGTs

@@ -33 +33 @@
 === MGT Clocking ===
 
-As mentioned, each MGT column has two input clocks that are shared. Any of the MGT tiles in that column share the clocks. In column 0 the clock inputs are located at tile 102 and tile 105. In column 1, the inputs are tile 10 and tile 13. There is an elaborate clock multiplexor scheme on the board that lets the user choose three of the four clock inputs.
+As mentioned, each MGT column has two input clocks that are shared. Any of the MGT tiles in that column share the clocks. In column 0 the clock inputs are located at tile 102 and tile 105. In column 1, the inputs are tile 10 and tile 13. There is an elaborate clock multiplexer scheme on the board that lets the user choose three of the four clock inputs.
 
 || '''Clock''' || '''Tile''' || '''P Constraint''' || '''N Constraint''' || '''Clock Frequency/Clock Mux''' ||
-|| MGTCLK_102 || 102 || F39 || G39 || Mux2 ||
-|| MGTCLK_105 || 105 || AW34 || AW33 || Mux3 ||
+|| MGTCLK_102 || 102 || F39 || G39 || Mux3 ||
+|| MGTCLK_105 || 105 || AW34 || AW33 || Mux4 ||
 || MGTCLK_110 || 110 || AW6 || AW7 || 300 MHz ||
-|| MGTCLK_113 || 113 || F1 || G1 || Mux1 ||
+|| MGTCLK_113 || 113 || F1 || G1 || Mux2 ||
+
+
+[[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:FPGABoard_ExtClk.jpg)]] [[BR]]
+'''External clock input and output'''
+
+There are four clock multiplexers on the board with four inputs each. The four possible inputs are MGT Clk A (external clock), MGT Clk B (NM), MGT Clk C (250 MHz) and MGT Clk D (NM). Mux1 is used to source another board, especially useful for sharing clocks between boards. The other three multiplexers source one of the FPGA Clock inputs. As there are four inputs, two bits are required to control every mux. Two 4-input dip switches choose the output of every mux.
+
+[[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:FPGABoard_SourceSelect.jpg)]]
 
 
@@ -52 +60 @@
 
 
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