| 53 | || || '''MGT Clk A''' || '''MGT Clk B''' || '''MGT Clk C''' || '''MGT Clk D''' || '''SW/Bit''' || |
| 54 | || '''Mux1''' || [[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:Dip_00.jpg)]] || || || || SW11, Bits 0 and 1 || |
| 55 | || '''Mux2''' || [[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:Dip_00.jpg)]] || || || || SW11, Bits 0 and 1 || |
| 56 | || '''Mux3''' || [[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:Dip_00.jpg)]] || || || || SW11, Bits 0 and 1 || |
| 57 | || '''Mux4''' || [[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:Dip_00.jpg)]] || || || || SW11, Bits 0 and 1 || |