Changes between Version 17 and Version 18 of HardwareUsersGuides/FPGABoard_v2.2/MGTs

Timestamp:

Sep 22, 2009, 10:43:12 AM (15 years ago)

Author:

sgupta

Comment:

--

HardwareUsersGuides/FPGABoard_v2.2/MGTs

@@ -35 +35 @@
 As mentioned, each MGT column has two input clocks that are shared. Any of the MGT tiles in that column share the clocks. In column 0 the clock inputs are located at tile 102 and tile 105. In column 1, the inputs are tile 10 and tile 13. There is an elaborate clock multiplexer scheme on the board that lets the user choose three of the four clock inputs.
 
-|| '''Clock''' || '''Tile''' || '''P Constraint''' || '''N Constraint''' || '''Clock Frequency/Clock Mux''' ||
-|| MGTCLK_102 || 102 || F39 || G39 || Mux3 ||
-|| MGTCLK_105 || 105 || AW34 || AW33 || Mux4 ||
-|| MGTCLK_110 || 110 || AW6 || AW7 || 300 MHz ||
-|| MGTCLK_113 || 113 || F1 || G1 || Mux2 ||
+|| '''Clock''' || '''Tile''' || '''LOC''' || '''P Pin''' || '''N Pin''' || '''Clock Frequency/Clock Mux''' ||
+|| MGTCLK_102 || 102 || GT11CLK_X0Y3 || F39 || G39 || Mux3 ||
+|| MGTCLK_105 || 105 || GT11CLK_X0Y1 ||  AW34 || AW33 || Mux4 ||
+|| MGTCLK_110 || 110 || GT11CLK_X1Y1 ||  AW6 || AW7 || 300 MHz ||
+|| MGTCLK_113 || 113 || GT11CLK_X1Y3 ||  F1 || G1 || Mux2 ||