Changes between Version 18 and Version 19 of HardwareUsersGuides/FPGABoard_v2.2/MGTs

Timestamp:

Sep 22, 2009, 10:17:29 PM (15 years ago)

Author:

sgupta

Comment:

--

HardwareUsersGuides/FPGABoard_v2.2/MGTs

@@ -20 +20 @@
 There are three types of MGT connectors on the board. Two Small form-factor Pluggable (SFP) occupy their own column. Four HSSDC2 connectors and two SATA occupy one column.
 
-|| '''MGT #''' || '''Type''' || '''Connector''' || '''MGT Tile''' || '''Column''' || '''LOC Constraint''' || '''TXP''' || '''TXN''' || '''RXP''' || '''RXN''' ||
-|| 1 || SATA Target || J47 || 112B || 1 || GT11_X1Y4 || P1 || R1 || U1 || V1 ||
-|| 2 || SATA Host || J46 || 112A || 1 || GT11_X1Y5 || M1 || N1 || J1 || K1 ||
-|| 3 || HSSDC2 || J3 || 113B || 1 || GT11_X1Y6 || A4 || A3 || C1 || D1 ||
-|| 4 || HSSDC2 || J4 || 113A || 1 || GT11_X1Y7 || A6 || A5 || A9 || A8 ||
-|| 5 || HSSDC2 || J5 || 114B || 1 || GT11_X1Y8 || A14 || A13 || A11 || A10 ||
-|| 6 || HSSDC2 || J6 || 114A || 1 || GT11_X1Y9 || A16 || A15 || A19 || A18 ||
-|| 7 || SFP !#1 || J49 || 102A || 0 || GT11_X0Y7 || A34 || A35 || A31 || A32 ||
-|| 8 || SFP !#2 || J48 || 102B || 0 || GT11_X0Y6 || A36 || A37 || C39 || D39 ||
+|| '''MGT #''' || '''Type''' || '''Connector''' || '''MGT Tile''' || '''Column''' || '''LOC Constraint''' || '''TXP''' || '''TXN''' || '''RXP''' || '''RXN''' || '''Ideal Clocks''' ||
+|| 1 || SATA Target || J47 || 112B || 1 || GT11_X1Y4 || P1 || R1 || U1 || V1 || MGTCLK_110 or MGTCLK_113 ||
+|| 2 || SATA Host || J46 || 112A || 1 || GT11_X1Y5 || M1 || N1 || J1 || K1 || MGTCLK_110 or MGTCLK_113 ||
+|| 3 || HSSDC2 || J3 || 113B || 1 || GT11_X1Y6 || A4 || A3 || C1 || D1 || MGTCLK_110 or MGTCLK_113 ||
+|| 4 || HSSDC2 || J4 || 113A || 1 || GT11_X1Y7 || A6 || A5 || A9 || A8 || MGTCLK_110 or MGTCLK_113 ||
+|| 5 || HSSDC2 || J5 || 114B || 1 || GT11_X1Y8 || A14 || A13 || A11 || A10 || MGTCLK_110 or MGTCLK_113 ||
+|| 6 || HSSDC2 || J6 || 114A || 1 || GT11_X1Y9 || A16 || A15 || A19 || A18 || MGTCLK_110 or MGTCLK_113 ||
+|| 7 || SFP !#1 || J49 || 102A || 0 || GT11_X0Y7 || A34 || A35 || A31 || A32 || MGTCLK_102 or MGTCLK_105 ||
+|| 8 || SFP !#2 || J48 || 102B || 0 || GT11_X0Y6 || A36 || A37 || C39 || D39 || MGTCLK_102 or MGTCLK_105 ||
 
 
 === MGT Clocking ===
+
+[[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:MGT_Clk_Blkdgm.jpg, 500px)]]
 
 As mentioned, each MGT column has two input clocks that are shared. Any of the MGT tiles in that column share the clocks. In column 0 the clock inputs are located at tile 102 and tile 105. In column 1, the inputs are tile 10 and tile 13. There is an elaborate clock multiplexer scheme on the board that lets the user choose three of the four clock inputs.