Changes between Version 21 and Version 22 of HardwareUsersGuides/FPGABoard_v2.2/MGTs

Timestamp:

Sep 28, 2009, 2:50:42 PM (15 years ago)

Author:

murphpo

Comment:

--

HardwareUsersGuides/FPGABoard_v2.2/MGTs

@@ -37 +37 @@
 As mentioned, each MGT column has two input clocks that are shared. Any of the MGT tiles in that column share the clocks. In column 0 the clock inputs are located at tile 102 and tile 105. In column 1, the inputs are tile 10 and tile 13. There is an elaborate clock multiplexer scheme on the board that lets the user choose three of the four clock inputs.
 
+|| '''Clock Source''' || '''Component''' || '''Mux Input ''' || '''Default Value''' ||
+|| MGT Clk A || J14 or J11/J18 || 0 || - ||
+|| MGT Clk B || Y2 || 1 || ??? || 
+|| MGT Clk C || Y3 || 2 || ??? ||
+|| MGT Clk D || Y4 || 3 || Not Installed || 
+|| MGT Clk E || Y8 || - || 150MHz LVDS ||
+
 || '''Clock''' || '''Tile''' || '''LOC''' || '''P Pin''' || '''N Pin''' || '''Clock Frequency/Clock Mux''' ||
 || MGTCLK_102 || 102 || GT11CLK_X0Y3 || F39 || G39 || Mux3 ||