Changes between Version 22 and Version 23 of HardwareUsersGuides/FPGABoard_v2.2/MGTs
- Timestamp:
- Sep 28, 2009, 2:51:17 PM (15 years ago)
Legend:
- Unmodified
- Added
- Removed
- Modified
-
HardwareUsersGuides/FPGABoard_v2.2/MGTs
v22 v23 37 37 As mentioned, each MGT column has two input clocks that are shared. Any of the MGT tiles in that column share the clocks. In column 0 the clock inputs are located at tile 102 and tile 105. In column 1, the inputs are tile 10 and tile 13. There is an elaborate clock multiplexer scheme on the board that lets the user choose three of the four clock inputs. 38 38 39 '''Clock Sources'''[[BR]] 39 40 || '''Clock Source''' || '''Component''' || '''Mux Input ''' || '''Default Value''' || 40 41 || MGT Clk A || J14 or J11/J18 || 0 || - || … … 44 45 || MGT Clk E || Y8 || - || 150MHz LVDS || 45 46 47 [[BR]] 48 '''Clock Inputs'''[[BR]] 46 49 || '''Clock''' || '''Tile''' || '''LOC''' || '''P Pin''' || '''N Pin''' || '''Clock Frequency/Clock Mux''' || 47 50 || MGTCLK_102 || 102 || GT11CLK_X0Y3 || F39 || G39 || Mux3 ||