Changes between Version 26 and Version 27 of HardwareUsersGuides/FPGABoard_v2.2/MGTs

Timestamp:

Oct 8, 2009, 4:46:04 PM (15 years ago)

Author:

murphpo

Comment:

--

HardwareUsersGuides/FPGABoard_v2.2/MGTs

@@ -31 +31 @@
 The WARP FPGA Board provides very flexible MGT clocking. The Virtex-4 FPGA organizes the MGTs into two columns. Each column provides two clock inputs. An MGT can use either clock driven into its column.
 
-The FPGA Board supports five MGT clock sources- four oscillators and one off-board connector. Two oscillators are installed by default; the remaining oscillator footprints can be populated as needed to support custom applications.
+The FPGA Board provides five MGT clock sources- four oscillators and one off-board interface. Two oscillators are installed by default; the remaining oscillator footprints can be populated as needed to support custom applications.
 
-One oscillator is connected directly to an FPGA MGT clock input. The remaining clock sources (four oscillators and off-board connectors) are connected to the FPGA through a flexible multiplexor network. This network allows the user to assign any of the four clock sources to any of the three FPGA MGT clock inputs. It also provides an off-board clock output which can be connected to another FPGA board, allowing multiple FPGA boards to share an MGT reference clock.
+One oscillator is connected directly to an FPGA MGT clock input. The remaining clock sources (four oscillators and the off-board interface) are connected to the FPGA through a flexible multiplexer network. This network allows the user to assign any of the four clock sources to any of the three FPGA MGT clock inputs. It also provides an off-board clock output which can be connected to another FPGA board, allowing multiple FPGA boards to share an MGT reference clock.
 
 The image and tables below provide details for the WARP FPGA Board's MGT clocking system.
@@ -56 +56 @@
 === MGT Clock Mux Network ===
 
-There are four clock multiplexers on the board with four inputs each. The muxes have the same four inputs: MGT Clk A (external clock), MGT Clk B, MGT Clk C and MGT Clk D. Mux1 is used to source another board, especially useful for sharing clocks between boards. The other three multiplexers source one of the FPGA Clock inputs. As there are four inputs, two bits are required to control every mux. Two 4-input dip switches choose the output of every mux.
+There are four clock multiplexers on the board, each with four inputs. All four muxes have the same four inputs, labeled MGT Clk A - E. The output of Mux1 drives the off-board clock output. The other three muxes each drive an FPGA MGT clock input. Each mux is configured by 2 bits, selected by 2 positions on a DIP switch. Two 4-position DIP switches (SW11 and SW10) provide the 8 bits of configuration (2 bits per mux).
 
-[[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:FPGABoard_SourceSelect.jpg)]] [[BR]] '''Multiplexer output select switches (bottom of the FPGA Board)'''
+[[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:FPGABoard_SourceSelect.jpg)]] [[BR]] '''Multiplexer output select switches'''
 
 The following table details the value required for each bit of SW10 and SW11 to obtain the desired output.