Changes between Version 29 and Version 30 of HardwareUsersGuides/FPGABoard_v2.2/MGTs

Timestamp:

Oct 8, 2009, 5:19:13 PM (15 years ago)

Author:

murphpo

Comment:

--

HardwareUsersGuides/FPGABoard_v2.2/MGTs

@@ -56 +56 @@
 === MGT Clock Mux Network ===
 
-There are four clock multiplexers on the board, each with four inputs. All four muxes have the same four inputs, labeled MGT Clk A - E. The output of Mux1 drives the off-board clock output. The other three muxes each drive an FPGA MGT clock input. Each mux is configured by 2 bits, selected by 2 positions on a DIP switch. Two 4-position DIP switches (SW11 and SW10) provide the 8 bits of configuration (2 bits per mux).
+There are four clock multiplexers on the board, each with four inputs. All four muxes have the same four inputs, labeled MGT Clk A - E. The output of Mux1 drives the off-board clock output. The other three muxes each drive an FPGA MGT clock input.
+
+Each mux is configured by 2 bits, selected by 2 positions on a DIP switch. Two 4-position DIP switches (SW11 and SW10) provide the 8 bits of configuration (2 bits per mux).
 
 [[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:FPGABoard_SourceSelect.jpg)]] [[BR]] '''Multiplexer output select switches'''
 
-The following table details the value required for each bit of SW10 and SW11 to obtain the desired output.
-
-||||'''MGT Clk A'''||'''MGT Clk B'''||'''MGT Clk C'''||'''MGT Clk D'''||'''SW/Bit'''||
-||'''Mux1'''||[[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:Dip_00.jpg)]]||[[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:Dip_01.jpg)]]||[[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:Dip_10.jpg)]]||[[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:Dip_11.jpg)]]||SW10, Bits 2 and 3||
-||'''Mux2'''||[[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:Dip_00.jpg)]]||[[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:Dip_01.jpg)]]||[[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:Dip_10.jpg)]]||[[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:Dip_11.jpg)]]||SW10, Bits 0 and 1||
-||'''Mux3'''||[[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:Dip_00.jpg)]]||[[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:Dip_01.jpg)]]||[[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:Dip_10.jpg)]]||[[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:Dip_11.jpg)]]||SW11, Bits 2 and 3||
-||'''Mux4'''||[[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:Dip_00.jpg)]]||[[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:Dip_01.jpg)]]||[[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:Dip_10.jpg)]]||[[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:Dip_11.jpg)]]||SW11, Bits 0 and 1||
-
+The assignment of DIP switches to muxes is shown in the figure below. The highlighted switches identify the positions responsible for a given mux. The two DIP switches are drawn as viewed on the bottom of the WARP FPGA Board.
 
 || [[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:muxSwitches_topRight.jpg)]] ||  [[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:muxSwitches_botRight.jpg)]] ||  [[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:muxSwitches_topLeft.jpg)]] ||  [[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:muxSwitches_botLeft.jpg)]] || 
@@ -73 +68 @@
 '''Mux Configuration Switch Assignments'''
 
-|| [Image(HardwareUsersGuides/FPGABoard_v2.2/Files:Dip_00.jpg)]] || [Image(HardwareUsersGuides/FPGABoard_v2.2/Files:Dip_01.jpg)]] || [Image(HardwareUsersGuides/FPGABoard_v2.2/Files:Dip_10.jpg)]] || [Image(HardwareUsersGuides/FPGABoard_v2.2/Files:Dip_11.jpg)]] ||
+Each 2-switch pair selects one of four clock sources. The mapping of clock source to switch values is illustrated below.
+
+|| [[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:Dip_00.jpg)]] || [[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:Dip_01.jpg)]] || [[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:Dip_10.jpg)]] || [[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:Dip_11.jpg)]] ||
 || '''Clk A''' || '''Clk B''' || '''Clk C''' || '''Clk D''' ||
 '''Mux Configuration Source Selection'''