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== WARP FPGA Board MGTs ==

The Virtex-4 FPGA is equipped with 10 pairs of differential multi-gigabit transceivers. The MGTs can support data rates of up to 6.5 Gbps including standards such as SATA, gigabit Ethernet and Infiniband. Each of these requires a different clock speed for best performance. On the FPGA Board three different connectors have been provided: SATA host and target, HSSDC2 jacks and SFP modules.

[[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:FPGA_Board_SATA.jpg)]]
[[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:FPGA_Board_HSSDC2.jpg)]]
[[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:FPGA_Board_SFP.jpg)]]

The MGTs on the FPGA are organized in two columns. Each MGT in a column can share clock sources.