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== WARP FPGA Board MGTs ==

The Virtex-4 FPGA is equipped with 10 pairs of differential multi-gigabit transceivers. The MGTs can support data rates of up to 6.5 Gbps including standards such as SATA, gigabit Ethernet and Infiniband. Each of these requires a different clock speed for best performance. On the FPGA Board three different connectors have been provided: SATA host and target, HSSDC2 jacks and SFP modules.

The MGTs on the FPGA are organized in two columns. Each column has two clock inputs and all the MGTs in the column can use either of those clocks. Our design maximizes the functionality by allowing the user to select the clock frequency that is input to the columns.

=== MGT Connectors ===

There are three types of MGT connectors on the board. Two Small form-factor Pluggable (SFP) occupy their own column. Four HSSDC2 connectors and two SATA occupy one column.

|| '''MGT #''' || '''Type''' || '''Connector''' || '''MGT Tile''' || '''Column''' ||
|| 1 || SATA Target || J47 || 12B || 1 ||
|| 2 || SATA Host || J46 || 12A || 1 ||
|| 3 || HSSDC2 || J3 || 13B || 1 ||
|| 4 || HSSDC2 || J4 || 13A || 1 ||
|| 5 || HSSDC2 || J5 || 14B || 1 ||
|| 6 || HSSDC2 || J6 || 14A || 1 ||
|| 7 || SFP !#1 || J49 || 2A || 0 ||
|| 8 || SFP !#2 || J48 || 2B || 0 ||