Changes between Version 5 and Version 6 of HardwareUsersGuides/FPGABoard_v2.2/OtherIO


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Timestamp:
Sep 8, 2009, 3:50:49 PM (15 years ago)
Author:
murphpo
Comment:

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  • HardwareUsersGuides/FPGABoard_v2.2/OtherIO

    v5 v6  
    1717
    1818There are 16-bits of unbuffered 3.3v I/O connected directly to FPGA I/O pins, routed to standard male 100mil header. The header has four ground pins in the corner positions. The 16 I/O signals are labeled at the header. Bits 0-7 are in the top row, bits 8-15 in the bottom, both arranged right-to-left.
     19
     20== FPGA Constraints ==
     21
     22[[Include(source:Hardware/FPGA_Board/Rev2.2/UCF/WARP_FPGA_v2.2_OtherIO.ucf, text/x-sh)]]