Changes between Version 1 and Version 2 of HardwareUsersGuides/WARPv3/DebugHeader
- Timestamp:
- May 14, 2013, 1:55:09 PM (11 years ago)
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HardwareUsersGuides/WARPv3/DebugHeader
v1 v2 3 3 4 4 The WARP v3 board includes a generic debug header with 16 pins tied directly to FPGA I/O. The header itself has 20 pins. The four corner pins are tied to ground. 5 6 [[Image(Debug_Header_Diagram_BnW.png)]] 5 7 6 8 The 16 I/O pins are tied to FPGA I/O in a bank with VCCO = 2.5v.