Changes between Version 2 and Version 3 of HardwareUsersGuides/WARPv3/EEPROM
- Timestamp:
- Aug 26, 2012, 2:51:57 PM (12 years ago)
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HardwareUsersGuides/WARPv3/EEPROM
v2 v3 2 2 == WARP v3 User Guide: EEPROM == 3 3 4 The WARP v3 board includes a 128 Kbit IIC EEPROM. This device is non-volatile, retaining its data indefinitely even when power is removed. The FPGA must act as the IIC master to read and write data in the EEPROM. For details of the EEPROM IIC requirements and other specs, refer to the device datasheet ( Numonyx M25P128).4 The WARP v3 board includes a 128 Kbit IIC EEPROM. This device is non-volatile, retaining its data indefinitely even when power is removed. The FPGA must act as the IIC master to read and write data in the EEPROM. For details of the EEPROM IIC requirements and other specs, refer to the device datasheet ([http://www.micron.com/~/media/Documents/Products/Data%20Sheet/NOR%20Flash/5975M25P128.pdf Numonyx M25P128]). 5 5 6 6 The write protect pin on the EEPROM is disabled. As a result the full EEPROM is readable and writable from user applications.
