Changes between Initial Version and Version 1 of HardwareUsersGuides/WARPv3/FPGA


Ignore:
Timestamp:
Jul 28, 2012, 7:19:04 PM (11 years ago)
Author:
murphpo
Comment:

--

Legend:

Unmodified
Added
Removed
Modified
  • HardwareUsersGuides/WARPv3/FPGA

    v1 v1  
     1[[TracNav(HardwareUsersGuides/WARPv3/TOC)]]
     2= WARP v3 User Guide: FPGA =
     3WARP v3 is designed around a Xilinx Virtex-6 FPGA. The WARP v3 board can support any Virtex-6 FPGA in the FF1156 package.
     4
     5You will need to know the specific FPGA device on your WARP v3 board to build custom projects using the Xilinx design tools. There is a label just above the FPGA indicating the device type and speed grade.
     6
     7Most WARP v3 boards are built with Xilinx part '''XC6VLX240T-2FFG1156C''' (LX240T device, speed grade -2, lead free 1156-pin package, commercial temperature range).
     8
     9== Xilinx Documentation ==
     10The Xilinx documentation is the authorative source for details on the specs, limits and functionality of the Virtex-6 FPGA on WARP v3. For the full list of Virtex-6 documentation visit [http://www.xilinx.com/support/documentation/virtex-6.htm http://www.xilinx.com/support/documentation/virtex-6.htm].
     11
     12Direct links to the most relevant Xilinx Virtex-6 docs:
     13 * [http://www.xilinx.com/support/documentation/data_sheets/ds150.pdf DS150 Virtex-6 Family Overview]
     14 * [http://www.xilinx.com/support/documentation/data_sheets/ds152.pdf DS152 Virtex-6 DC & Switching Characteristics]
     15 * [http://www.xilinx.com/support/documentation/user_guides/ug360.pdf UG360 Virtex-6 FPGA Configuration]
     16 * [http://www.xilinx.com/support/documentation/user_guides/ug361.pdf UG361 Virtex-6 SelectIO Resources]
     17 * [http://www.xilinx.com/support/documentation/user_guides/ug362.pdf UG362 Virtex-6 Clocking Resources]
     18 * [http://www.xilinx.com/support/documentation/user_guides/ug363.pdf UG363 Virtex-6 On-Chip Memory Resources]
     19 * [http://www.xilinx.com/support/documentation/user_guides/ug364.pdf UG364 Virtex-6 Configurable Logic Block (CLB)]
     20 * [http://www.xilinx.com/support/documentation/user_guides/ug366.pdf UG366 Virtex-6 GTX Transceivers]
     21 * [http://www.xilinx.com/support/documentation/user_guides/ug368.pdf UG368 Virtex-6 Tri-Mode Ethernet MAC]
     22 * [http://www.xilinx.com/support/documentation/user_guides/ug369.pdf UG369 Virtex-6 DSP48E1 Slices]
     23 * [http://www.xilinx.com/support/documentation/user_guides/ug370.pdf UG370 Virtex-6 System Monitor]
     24
     25== Active Heat Sink ==
     26Every board ships with a heat sink and fan installed on the FPGA. It is strongly recommended these remain mounted at all times.
     27
     28The fan speed is controlled via a 3-pin header on the board (J5). Remove the shunt to disable the fan (not recommended), short pins 1-2 for max speed or short pins 2-3 for low speed.
     29
     30The active heat sink is Radian part FA35+K52B+T710. See the [https://www.radianheatsinks.com/pdf/datasheets/Fansink.pdf Radian datasheet] for details.
     31
     32The fan is designed to last for many years, but as it is one big moving part, it will eventually break down. Avoid leaving the WARP v3 board powered on but unused to maximize the fan's life.