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WARP v3 User Guide: Memory

The WARP v3 board includes a DDR3 SO-DIMM slot routed to dedicated pins on the FPGA. When combined with a DDR3 memory controller core in the FPGA, the SO-DIMM is available to user designs. The SO-DIMM interface on WARP v3 is designed to support modules up to 8GB in size and run at up to 400MHz. Faster speeds may be possible but require very careful tuning of the FPGA design to meet timing. Our template projects run the memory at 320MHz, which strikes a good balance between performance and easier timing closure.

Every WARP v3 kit ships with a pre-tested 2GB SO-DIMM rated for at least 400MHz operation. If you want to use another SO-DIMM, we recommend using modules from major manufacturers, acquired through authorized (and reputable) channels. All too often cheap modules can be out-of-spec (or outright counterfeits), and debugging flaky RAM in hardware is hard.

Memory Controllers

Designing a DDR3 memory controller is challenging. Thankfully Xilinx provides the MIG (memory interface generator), which can generate FPGA implementations of known-good DDR3 controllers. MIG can be run from Coregen if you need a memory controller for a custom logic design. You can use the constraints below when running the MIG wizard to generate a controller for use on WARP v3.

XPS MPMC

For embedded designs, XPS provides the MPMC, which wraps a MIG-generated DDR3 controller. The MPMC only supports 32-bit DDR3 memories on Virtex-6 devices. The MHS snipped below shows how to configure the MPMC in XPS 13.4 for use with the 2GB SO-DIMM on WARP v3.

BEGIN mpmc
 PARAMETER INSTANCE = DDR3_2GB_SODIMM
 PARAMETER C_NUM_PORTS = 1
 PARAMETER C_MEM_TYPE = DDR3
 PARAMETER C_MEM_PARTNO = MT8JSF25664HZ-1G4
 PARAMETER C_MEM_ODT_TYPE = 1
 PARAMETER C_MEM_REG_DIMM = 0
 PARAMETER C_MEM_CLK_WIDTH = 1
 PARAMETER C_MEM_ODT_WIDTH = 1
 PARAMETER C_MEM_CE_WIDTH = 1
 PARAMETER C_MEM_CS_N_WIDTH = 1
 PARAMETER C_MEM_DATA_WIDTH = 32
 PARAMETER C_MEM_NDQS_COL0 = 4
 PARAMETER C_MEM_DQS_LOC_COL0 = 0x000000000000000000000000000003020100
 PARAMETER C_PIM0_BASETYPE = 2
 PARAMETER HW_VER = 6.05.a
 PARAMETER C_FAMILY = virtex6
 PARAMETER C_MPMC_BASEADDR = 0x40000000
 PARAMETER C_MPMC_HIGHADDR = 0x7fffffff
 BUS_INTERFACE SPLB0 = mb_plb
 PORT MPMC_Clk0 = clk_150_0000MHzMMCM0
 PORT MPMC_Clk_200MHz = clk_200_0000MHz
 PORT MPMC_Rst = sys_periph_reset
 PORT MPMC_Clk_Mem = clk_300_0000MHzMMCM0
 PORT MPMC_Clk_Rd_Base = clk_300_0000MHzMMCM0_nobuf_varphase
 PORT MPMC_DCM_PSEN = MPMC_DCM_PSEN
 PORT MPMC_DCM_PSINCDEC = MPMC_DCM_PSINCDEC
 PORT MPMC_DCM_PSDONE = MPMC_DCM_PSDONE
 PORT DDR3_Clk = fpga_0_DDR3_2GB_SODIMM_DDR3_Clk_pin
 PORT DDR3_Clk_n = fpga_0_DDR3_2GB_SODIMM_DDR3_Clk_n_pin
 PORT DDR3_CE = fpga_0_DDR3_2GB_SODIMM_DDR3_CE_pin
 PORT DDR3_CS_n = fpga_0_DDR3_2GB_SODIMM_DDR3_CS_n_pin
 PORT DDR3_ODT = fpga_0_DDR3_2GB_SODIMM_DDR3_ODT_pin
 PORT DDR3_RAS_n = fpga_0_DDR3_2GB_SODIMM_DDR3_RAS_n_pin
 PORT DDR3_CAS_n = fpga_0_DDR3_2GB_SODIMM_DDR3_CAS_n_pin
 PORT DDR3_WE_n = fpga_0_DDR3_2GB_SODIMM_DDR3_WE_n_pin
 PORT DDR3_BankAddr = fpga_0_DDR3_2GB_SODIMM_DDR3_BankAddr_pin
 PORT DDR3_Addr = fpga_0_DDR3_2GB_SODIMM_DDR3_Addr_pin
 PORT DDR3_DQ = fpga_0_DDR3_2GB_SODIMM_DDR3_DQ_pin
 PORT DDR3_DM = fpga_0_DDR3_2GB_SODIMM_DDR3_DM_pin
 PORT DDR3_Reset_n = fpga_0_DDR3_2GB_SODIMM_DDR3_Reset_n_pin
 PORT DDR3_DQS = fpga_0_DDR3_2GB_SODIMM_DDR3_DQS_pin
 PORT DDR3_DQS_n = fpga_0_DDR3_2GB_SODIMM_DDR3_DQS_n_pin
END

The UCF entries for timing and logic placement for this parameterization of the MPMC are listed below. The pin location constraints given in the next section are also required. All of these are tailored for the WARP v3 board with a 2GB SO-DIMM clocked at <400MHz.

# Includes placement constraints for upper 32 bits of the 64-bit RAM,
#  just in case Xilinx gets around to implementing a 64-bit DDR3 MPMC for V6

# These constraints are derived from the template generated by the MIG
#  The comments below are all generated by the MIG and are included here for reference


# Constrain BUFR clocks used to synchronize data from IOB to fabric logic
# Note that ISE cannot infer this from other PERIOD constraints because
# of the use of OSERDES blocks in the BUFR clock generation path
NET "*/mpmc_core_0/gen_v6_ddr3_phy.mpmc_phy_if_0/clk_rsync[?]" TNM_NET = TNM_clk_rsync;
TIMESPEC "TS_clk_rsync" = PERIOD "TNM_clk_rsync" 5000 ps;       # This is over-constraint for 200MHz, user can relax it to match mpmc_clk0
 
# Paths between DQ/DQS ISERDES.Q outputs and CLB flops clocked by falling 
# edge of BUFR will by design only be used if DYNCLKDIVSEL is asserted for 
# that particular flop. Mark this path as being a full-cycle, rather than 
# a half cycle path for timing purposes. NOTE: This constraint forces full-
# cycle timing to be applied globally for all rising->falling edge paths 
# in all resynchronizaton clock domains. If the user had modified the logic
# in the resync clock domain such that other rising->falling edge paths 
# exist, then constraint below should be modified to utilize pattern 
# matching to specific affect only the DQ/DQS ISERDES.Q outputs
TIMEGRP "TG_clk_rsync_rise" = RISING  "TNM_clk_rsync";
TIMEGRP "TG_clk_rsync_fall" = FALLING "TNM_clk_rsync";
TIMESPEC "TS_clk_rsync_rise_to_fall" =    FROM "TG_clk_rsync_rise" TO "TG_clk_rsync_fall" 5000 ps;    # This is over-constraint for 200MHz, user can relax it to match mpmc_clk0
 
# Signal to select between controller and physical layer signals. Four divided by two clock
# cycles (4 memory clock cycles) are provided by design for the signal to settle down.
# Used only by the phy modules.
INST "*/mpmc_core_0/gen_v6_ddr3_phy.mpmc_phy_if_0/u_phy_init/u_ff_phy_init_data_sel" TNM = "TNM_PHY_INIT_SEL";
TIMESPEC "TS_MC_PHY_INIT_SEL" = FROM "TNM_PHY_INIT_SEL" TO FFS = 10000 ps;                         # This is over-constraint, user can relax it to match 4 memory clock cycles

#Internal Vref
CONFIG INTERNAL_VREF_BANK22=0.75;
CONFIG INTERNAL_VREF_BANK23=0.75;
CONFIG INTERNAL_VREF_BANK33=0.75;

#DCI Cascading
CONFIG DCI_CASCADE = "23 22";

#BUFR IOBs (must be unconnected in FPGA and PCB)
CONFIG PROHIBIT = AH17,AP20;

#BUFIO IOBs (must be unconnected in FPGA and PCB)
CONFIG PROHIBIT = AC13,AD12,AF19,AF20,AH23,AK27,AN27,AP11;

######################################################################################
##Place RSYNC OSERDES and IODELAY:                                                  ##
######################################################################################

#MPMC as of EDK 13.4 only supports 32-bit memories
##Site: AH17 -- Bank 32
#INST "*/u_phy_read/u_phy_rdclk_gen/gen_loop_col1.u_oserdes_rsync" LOC = "OLOGIC_X2Y23";
#INST "*/u_phy_read/u_phy_rdclk_gen/gen_loop_col1.u_odelay_rsync" LOC = "IODELAY_X2Y23";
#INST "*/u_phy_read/u_phy_rdclk_gen/gen_loop_col1.u_bufr_rsync" LOC = "BUFR_X2Y1";

##Site: AP20 -- Bank 22
INST "*/u_phy_read/u_phy_rdclk_gen/gen_loop_col0.u_oserdes_rsync" LOC = "OLOGIC_X1Y21";
INST "*/u_phy_read/u_phy_rdclk_gen/gen_loop_col0.u_odelay_rsync" LOC = "IODELAY_X1Y21";
INST "*/u_phy_read/u_phy_rdclk_gen/gen_loop_col0.u_bufr_rsync" LOC = "BUFR_X1Y1";


######################################################################################
##Place CPT OSERDES and IODELAY:                                                    ##
######################################################################################

##Site: AH23 -- Bank 23
INST "*/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[0].u_oserdes_cpt" LOC = "OLOGIC_X1Y57";
INST "*/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[0].u_odelay_cpt" LOC = "IODELAY_X1Y57";

##Site: AK27 -- Bank 23
INST "*/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[1].u_oserdes_cpt" LOC = "OLOGIC_X1Y59";
INST "*/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[1].u_odelay_cpt" LOC = "IODELAY_X1Y59";

##Site: AN27 -- Bank 23
INST "*/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[2].u_oserdes_cpt" LOC = "OLOGIC_X1Y61";
INST "*/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[2].u_odelay_cpt" LOC = "IODELAY_X1Y61";

##Site: AF19 -- Bank 22
INST "*/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[3].u_oserdes_cpt" LOC = "OLOGIC_X1Y23";
INST "*/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[3].u_odelay_cpt" LOC = "IODELAY_X1Y23";

#MPMC as of EDK 13.4 only supports 32-bit memories
##Site: AF20 -- Bank 22
#INST "*/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[4].u_oserdes_cpt" LOC = "OLOGIC_X1Y17";
#INST "*/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[4].u_odelay_cpt" LOC = "IODELAY_X1Y17";

##Site: AP11 -- Bank 33
#INST "*/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[5].u_oserdes_cpt" LOC = "OLOGIC_X2Y57";
#INST "*/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[5].u_odelay_cpt" LOC = "IODELAY_X2Y57";

##Site: AC13 -- Bank 33
#INST "*/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[6].u_oserdes_cpt" LOC = "OLOGIC_X2Y61";
#INST "*/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[6].u_odelay_cpt" LOC = "IODELAY_X2Y61";

##Site: AD12 -- Bank 33
#INST "*/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[7].u_oserdes_cpt" LOC = "OLOGIC_X2Y59";
#INST "*/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[7].u_odelay_cpt" LOC = "IODELAY_X2Y59";

FPGA Pinout

The FPGA pin assignments for the DDR3 SO-DIMM connector are listed in the UCF snippet below. The pins listed as PROHIBIT are unconnected on the WARP v3 board. The MIG DDR3 controller uses clocking logic in these IOBs, precluding use of the actual IO on the board.

###DDR3 SO-DIMM

#Clocks
NET "SODIMM_CK_N<0>" LOC = "AD15" | IOSTANDARD = "DIFF_SSTL15";
NET "SODIMM_CK_P<0>" LOC = "AC15" | IOSTANDARD = "DIFF_SSTL15";
NET "SODIMM_CK_N<1>" LOC = "AM15" | IOSTANDARD = "DIFF_SSTL15";
NET "SODIMM_CK_P<1>" LOC = "AN15" | IOSTANDARD = "DIFF_SSTL15";

#Address/Control
NET "SODIMM_ADDR<0>" LOC = "AM17" | IOSTANDARD = "SSTL15";
NET "SODIMM_ADDR<1>" LOC = "AF16" | IOSTANDARD = "SSTL15";
NET "SODIMM_ADDR<2>" LOC = "AN17" | IOSTANDARD = "SSTL15";
NET "SODIMM_ADDR<3>" LOC = "AG17" | IOSTANDARD = "SSTL15";
NET "SODIMM_ADDR<4>" LOC = "AK16" | IOSTANDARD = "SSTL15";
NET "SODIMM_ADDR<5>" LOC = "AG16" | IOSTANDARD = "SSTL15";
NET "SODIMM_ADDR<6>" LOC = "AK17" | IOSTANDARD = "SSTL15";
NET "SODIMM_ADDR<7>" LOC = "AG18" | IOSTANDARD = "SSTL15";
NET "SODIMM_ADDR<8>" LOC = "AE16" | IOSTANDARD = "SSTL15";
NET "SODIMM_ADDR<9>" LOC = "AD16" | IOSTANDARD = "SSTL15";
NET "SODIMM_ADDR<10>" LOC = "AH15" | IOSTANDARD = "SSTL15";
NET "SODIMM_ADDR<11>" LOC = "AH18" | IOSTANDARD = "SSTL15";
NET "SODIMM_ADDR<12>" LOC = "AE17" | IOSTANDARD = "SSTL15";
NET "SODIMM_ADDR<13>" LOC = "AJ16" | IOSTANDARD = "SSTL15";
NET "SODIMM_ADDR<14>" LOC = "AK18" | IOSTANDARD = "SSTL15";
NET "SODIMM_ADDR<15>" LOC = "AH19" | IOSTANDARD = "SSTL15";

NET "SODIMM_BA<0>" LOC = "AG15" | IOSTANDARD = "SSTL15";
NET "SODIMM_BA<1>" LOC = "AP16" | IOSTANDARD = "SSTL15";
NET "SODIMM_BA<2>" LOC = "AD17" | IOSTANDARD = "SSTL15";
NET "SODIMM_CAS_N" LOC = "AJ17" | IOSTANDARD = "SSTL15";
NET "SODIMM_CKE<0>" LOC = "AF18" | IOSTANDARD = "SSTL15";
NET "SODIMM_CKE<1>" LOC = "AJ19" | IOSTANDARD = "SSTL15";
NET "SODIMM_CS_N<0>" LOC = "AL16" | IOSTANDARD = "SSTL15";
NET "SODIMM_CS_N<1>" LOC = "AJ15" | IOSTANDARD = "SSTL15";
NET "SODIMM_EVENT" LOC = "AL14" | IOSTANDARD = "SSTL15";
NET "SODIMM_ODT<0>" LOC = "AP15" | IOSTANDARD = "SSTL15";
NET "SODIMM_ODT<1>" LOC = "AL15" | IOSTANDARD = "SSTL15";
NET "SODIMM_RAS_N" LOC = "AM16" | IOSTANDARD = "SSTL15";
NET "SODIMM_RESET_N" LOC = "AP17" | IOSTANDARD = "SSTL15";
NET "SODIMM_WE_N" LOC = "AF15" | IOSTANDARD = "SSTL15";

#Data Masks
NET "SODIMM_DM<0>" LOC = "AM30" | IOSTANDARD = "SSTL15";
NET "SODIMM_DM<1>" LOC = "AL26" | IOSTANDARD = "SSTL15";
NET "SODIMM_DM<2>" LOC = "AP26" | IOSTANDARD = "SSTL15";
NET "SODIMM_DM<3>" LOC = "AJ22" | IOSTANDARD = "SSTL15";
NET "SODIMM_DM<4>" LOC = "AN20" | IOSTANDARD = "SSTL15";
NET "SODIMM_DM<5>" LOC = "AH14" | IOSTANDARD = "SSTL15";
NET "SODIMM_DM<6>" LOC = "AM10" | IOSTANDARD = "SSTL15";
NET "SODIMM_DM<7>" LOC = "AG11" | IOSTANDARD = "SSTL15";

#DQ
NET "SODIMM_DQ<0>" LOC = "AK29" | IOSTANDARD = "SSTL15_T_DCI";
NET "SODIMM_DQ<1>" LOC = "AN30" | IOSTANDARD = "SSTL15_T_DCI";
NET "SODIMM_DQ<2>" LOC = "AL29" | IOSTANDARD = "SSTL15_T_DCI";
NET "SODIMM_DQ<3>" LOC = "AN29" | IOSTANDARD = "SSTL15_T_DCI";
NET "SODIMM_DQ<4>" LOC = "AP31" | IOSTANDARD = "SSTL15_T_DCI";
NET "SODIMM_DQ<5>" LOC = "AP30" | IOSTANDARD = "SSTL15_T_DCI";
NET "SODIMM_DQ<6>" LOC = "AH28" | IOSTANDARD = "SSTL15_T_DCI";
NET "SODIMM_DQ<7>" LOC = "AH27" | IOSTANDARD = "SSTL15_T_DCI";
NET "SODIMM_DQ<8>" LOC = "AK28" | IOSTANDARD = "SSTL15_T_DCI";
NET "SODIMM_DQ<9>" LOC = "AL28" | IOSTANDARD = "SSTL15_T_DCI";
NET "SODIMM_DQ<10>" LOC = "AJ27" | IOSTANDARD = "SSTL15_T_DCI";
NET "SODIMM_DQ<11>" LOC = "AH25" | IOSTANDARD = "SSTL15_T_DCI";
NET "SODIMM_DQ<12>" LOC = "AP29" | IOSTANDARD = "SSTL15_T_DCI";
NET "SODIMM_DQ<13>" LOC = "AM27" | IOSTANDARD = "SSTL15_T_DCI";
NET "SODIMM_DQ<14>" LOC = "AJ25" | IOSTANDARD = "SSTL15_T_DCI";
NET "SODIMM_DQ<15>" LOC = "AH24" | IOSTANDARD = "SSTL15_T_DCI";
NET "SODIMM_DQ<16>" LOC = "AJ24" | IOSTANDARD = "SSTL15_T_DCI";
NET "SODIMM_DQ<17>" LOC = "AK24" | IOSTANDARD = "SSTL15_T_DCI";
NET "SODIMM_DQ<18>" LOC = "AL24" | IOSTANDARD = "SSTL15_T_DCI";
NET "SODIMM_DQ<19>" LOC = "AK23" | IOSTANDARD = "SSTL15_T_DCI";
NET "SODIMM_DQ<20>" LOC = "AP27" | IOSTANDARD = "SSTL15_T_DCI";
NET "SODIMM_DQ<21>" LOC = "AM26" | IOSTANDARD = "SSTL15_T_DCI";
NET "SODIMM_DQ<22>" LOC = "AN25" | IOSTANDARD = "SSTL15_T_DCI";
NET "SODIMM_DQ<23>" LOC = "AN24" | IOSTANDARD = "SSTL15_T_DCI";
NET "SODIMM_DQ<24>" LOC = "AD21" | IOSTANDARD = "SSTL15_T_DCI";
NET "SODIMM_DQ<25>" LOC = "AE21" | IOSTANDARD = "SSTL15_T_DCI";
NET "SODIMM_DQ<26>" LOC = "AK22" | IOSTANDARD = "SSTL15_T_DCI";
NET "SODIMM_DQ<27>" LOC = "AL18" | IOSTANDARD = "SSTL15_T_DCI";
NET "SODIMM_DQ<28>" LOC = "AN19" | IOSTANDARD = "SSTL15_T_DCI";
NET "SODIMM_DQ<29>" LOC = "AP19" | IOSTANDARD = "SSTL15_T_DCI";
NET "SODIMM_DQ<30>" LOC = "AM18" | IOSTANDARD = "SSTL15_T_DCI";
NET "SODIMM_DQ<31>" LOC = "AN18" | IOSTANDARD = "SSTL15_T_DCI";
NET "SODIMM_DQ<32>" LOC = "AF21" | IOSTANDARD = "SSTL15_T_DCI";
NET "SODIMM_DQ<33>" LOC = "AC20" | IOSTANDARD = "SSTL15_T_DCI";
NET "SODIMM_DQ<34>" LOC = "AD20" | IOSTANDARD = "SSTL15_T_DCI";
NET "SODIMM_DQ<35>" LOC = "AE19" | IOSTANDARD = "SSTL15_T_DCI";
NET "SODIMM_DQ<36>" LOC = "AP21" | IOSTANDARD = "SSTL15_T_DCI";
NET "SODIMM_DQ<37>" LOC = "AJ20" | IOSTANDARD = "SSTL15_T_DCI";
NET "SODIMM_DQ<38>" LOC = "AL19" | IOSTANDARD = "SSTL15_T_DCI";
NET "SODIMM_DQ<39>" LOC = "AK19" | IOSTANDARD = "SSTL15_T_DCI";
NET "SODIMM_DQ<40>" LOC = "AF14" | IOSTANDARD = "SSTL15_T_DCI";
NET "SODIMM_DQ<41>" LOC = "AG12" | IOSTANDARD = "SSTL15_T_DCI";
NET "SODIMM_DQ<42>" LOC = "AK13" | IOSTANDARD = "SSTL15_T_DCI";
NET "SODIMM_DQ<43>" LOC = "AH12" | IOSTANDARD = "SSTL15_T_DCI";
NET "SODIMM_DQ<44>" LOC = "AN14" | IOSTANDARD = "SSTL15_T_DCI";
NET "SODIMM_DQ<45>" LOC = "AP14" | IOSTANDARD = "SSTL15_T_DCI";
NET "SODIMM_DQ<46>" LOC = "AL13" | IOSTANDARD = "SSTL15_T_DCI";
NET "SODIMM_DQ<47>" LOC = "AN12" | IOSTANDARD = "SSTL15_T_DCI";
NET "SODIMM_DQ<48>" LOC = "AF11" | IOSTANDARD = "SSTL15_T_DCI";
NET "SODIMM_DQ<49>" LOC = "AE11" | IOSTANDARD = "SSTL15_T_DCI";
NET "SODIMM_DQ<50>" LOC = "AE13" | IOSTANDARD = "SSTL15_T_DCI";
NET "SODIMM_DQ<51>" LOC = "AE12" | IOSTANDARD = "SSTL15_T_DCI";
NET "SODIMM_DQ<52>" LOC = "AK12" | IOSTANDARD = "SSTL15_T_DCI";
NET "SODIMM_DQ<53>" LOC = "AJ12" | IOSTANDARD = "SSTL15_T_DCI";
NET "SODIMM_DQ<54>" LOC = "AK11" | IOSTANDARD = "SSTL15_T_DCI";
NET "SODIMM_DQ<55>" LOC = "AJ11" | IOSTANDARD = "SSTL15_T_DCI";
NET "SODIMM_DQ<56>" LOC = "AC12" | IOSTANDARD = "SSTL15_T_DCI";
NET "SODIMM_DQ<57>" LOC = "AH10" | IOSTANDARD = "SSTL15_T_DCI";
NET "SODIMM_DQ<58>" LOC = "AD11" | IOSTANDARD = "SSTL15_T_DCI";
NET "SODIMM_DQ<59>" LOC = "AG10" | IOSTANDARD = "SSTL15_T_DCI";
NET "SODIMM_DQ<60>" LOC = "AP12" | IOSTANDARD = "SSTL15_T_DCI";
NET "SODIMM_DQ<61>" LOC = "AM12" | IOSTANDARD = "SSTL15_T_DCI";
NET "SODIMM_DQ<62>" LOC = "AL10" | IOSTANDARD = "SSTL15_T_DCI";
NET "SODIMM_DQ<63>" LOC = "AJ10" | IOSTANDARD = "SSTL15_T_DCI";

#DQS
NET "SODIMM_DQS0_N" LOC = "AG26" | IOSTANDARD = "SSTL15_T_DCI";
NET "SODIMM_DQS0_P" LOC = "AG25" | IOSTANDARD = "SSTL15_T_DCI";
NET "SODIMM_DQS1_N" LOC = "AM28" | IOSTANDARD = "SSTL15_T_DCI";
NET "SODIMM_DQS1_P" LOC = "AN28" | IOSTANDARD = "SSTL15_T_DCI";
NET "SODIMM_DQS2_N" LOC = "AL25" | IOSTANDARD = "SSTL15_T_DCI";
NET "SODIMM_DQS2_P" LOC = "AM25" | IOSTANDARD = "SSTL15_T_DCI";
NET "SODIMM_DQS3_N" LOC = "AH22" | IOSTANDARD = "SSTL15_T_DCI";
NET "SODIMM_DQS3_P" LOC = "AG22" | IOSTANDARD = "SSTL15_T_DCI";
NET "SODIMM_DQS4_N" LOC = "AL20" | IOSTANDARD = "SSTL15_T_DCI";
NET "SODIMM_DQS4_P" LOC = "AM20" | IOSTANDARD = "SSTL15_T_DCI";
NET "SODIMM_DQS5_N" LOC = "AM13" | IOSTANDARD = "SSTL15_T_DCI";
NET "SODIMM_DQS5_P" LOC = "AN13" | IOSTANDARD = "SSTL15_T_DCI";
NET "SODIMM_DQS6_N" LOC = "AC14" | IOSTANDARD = "SSTL15_T_DCI";
NET "SODIMM_DQS6_P" LOC = "AD14" | IOSTANDARD = "SSTL15_T_DCI";
NET "SODIMM_DQS7_N" LOC = "AM11" | IOSTANDARD = "SSTL15_T_DCI";
NET "SODIMM_DQS7_P" LOC = "AL11" | IOSTANDARD = "SSTL15_T_DCI";

#SO-DIMM reserved pins when using DDR3 controller based on the Xilinx MIG 
# (IOB clock logic used internally; must be unconnected on PCB and in FPGA designs)

#Bank 22
CONFIG PROHIBIT = AF20, AP20, AF19;

#Bank 23
CONFIG PROHIBIT = AH23, AK27, AN27;

#Bank 32
CONFIG PROHIBIT = AH17;

#Bank 33
CONFIG PROHIBIT = AP11, AD12, AC13;

Last modified 11 years ago Last modified on Mar 19, 2013, 9:14:59 PM

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