== [wiki:OFDM MIMO OFDM] | [wiki:OFDM/MIMO#Documentation Documentation] | OFDM Model Top-level Ports == == Clocks == The entire MIMO OFDM model is driven by a single clock and has one top-level clock enable. The clock signal connected to '''splb_clk''' must be the same clock which drives the ADC/DACs on the radio daughtercards and the converter_clock_in port on the corresponding radio_bridge cores. ||'''Port'''||'''Default'''||'''Direction'''||'''Width'''|| ||splb_clk||sys_clk_s||Input||1|| ||splb_rst||net_gnd||Input||1|| == PLB Slave Interface Ports == The model includes a standard PLB46 slave interface, automatically generated by the System Generator EDK Export flow. This interface is used to connect the OFDM core to an embedded PowerPC or Microblaze processor in the FPGA. This interface must be connected to a processor in order to use the OFDM core in hardware. The ports all have prefix '''sl_''' or '''plb_'''. These will be automatically connected to the host bus when the bus interface is connected in the EDK. == BRAM Interface Ports == The model includes a BRAM initiator interface, used to access the shared 64KB PLB_BRAM packet buffer. The packet buffer is not included in the OFDM design; it must be instantiated in the EDK project and connected to the OFDM core via these ports. The BRAM ports are grouped into a BRAM_INITIATOR bus definition to facilitate their easy connection in the EDK's System Assembly View. ||'''Port'''||'''Default'''||'''Direction'''||'''Width'''|| ||bram_addr||BRAM_Addr||Output||32|| ||bram_datain||BRAM_Din||Input||64|| ||bram_dout||BRAM_Dout||Output||64|| ||bram_reset||BRAM_Rst||Output||1|| ||bram_wen||BRAM_WEN||Output||8|| == OFDM Core == The OFDM core uses dedicated top-level ports to interface with other peripheral cores. Some of these signals are connected to radio bridges, which route the signals off-chip to radio daughtercards. The rest connect to other custom cores for radio-specific PHY functions like AGC and packet detection. ||'''Port'''||'''Default'''||'''Direction'''||'''Width'''||'''Notes'''|| ||rx_anta_adci||||Input||14||I channel ADC input from antenna A|| ||rx_anta_adcq||||Input||14||Q channel ADC input from antenna A|| ||rx_antb_adci||||Input||14||I channel ADC input from antenna B|| ||rx_antb_adcq||||Input||14||Q channel ADC input from antenna B|| ||tx_anta_dac_i||||Output||16||I channel DAC output for antenna A|| ||tx_anta_dac_q||||Output||16||Q channel DAC output for antenna A|| ||tx_antb_dac_i||||Output||16||I channel DAC output for antenna B|| ||tx_antb_dac_q||||Output||16||Q channel DAC output for antenna B|| ||rssi_clk_out||||Output||1||Clock for the RSSI ADC on every radio board; should be connected to corresponding port on each radio bridge|| ||rssi_anta||||Input||10||Antenna A RSSI ADC value; should be connected to corresponding radio bridge output port|| ||rssi_antb||||Input||10||Antenna B RSSI ADC value; should be connected to corresponding radio bridge output port|| ||rx_int_badheader||||Output||1||Interrupt output signaling a received packet header failed CRC|| ||rx_int_badpkt||||Output||1||Interrupt output signaling a received packet failed CRC|| ||rx_int_goodpkt||||Output||1||Interrupt output signaling a received packet passed CRC and is ready for higher-layer processing|| ||rx_int_goodheader||||Output||1||Interrupt output signaling a received packet's header was error-free; only asserts for packets with a payload beyond the header|| ||rx_pktdetreset ||||Output||1||Active-high output indicating that packet detection events should be ignored while the PHY is busy|| ||rx_reset ||||Input||1||Active-high global reset input; clears all internal state in the receiver model; does not clear register values|| ||rx_anta_agc_done||||Input||1||Status signal from AGC core for antenna A; asserts high when AGC has settled|| ||rx_anta_gainbb||||Input||5||Baseband gain value in [0...63] chosen by AGC on antenna A. Only valid after rx_antb_agc_done asserts|| ||rx_anta_gainrf||||Input||2||RF gain value in ![1,2,3] chosen by AGC on antenna A. Only valid after rx_antb_agc_done asserts|| ||rx_antb_agc_done||||Input||1||Status signal from AGC core for antenna A; asserts high when AGC has settled|| ||rx_antb_gainbb||||Input||5||Baseband gain value in [0...63] chosen by AGC on antenna B. Only valid after rx_antb_agc_done asserts|| ||rx_antb_gainrf||||Input||2||RF gain value in ![1,2,3] chosen by AGC on antenna B. Only valid after rx_antb_agc_done asserts|| ||tx_reset||||Input||1||Active-high global reset input; clears all internal state in the transmitter model; does not clear register values|| ||tx_starttransmit ||||Input||1||Active-high trigger to begin transmission of a packet; usually tied to one of the radio controller's TxStart outputs|| ||tx_pktdone ||||Output||1||Active-high output indicating a packet transmission has finished|| == Debugging Ports == The core contains a number of top-level ports dedicated to debugging the design in hardware. These tend to change with each revision and can usually be identified as having "debug" in their names.