OFDM Physical Layer

We have chosen OFDM as the underlying physical layer for our research. Currently a SISO OFDM transceiver is fully implemented as an FPGA design and tested in hardware using the WARP FPGA and radio boards.

OFDM Models Overview

Our SISO OFDM transceiver is implemented in the FPGA fabric, and is composed of two Simulink models built using Xilinx's System Generator for DSP. Both models are designed from scratch for real-time, wideband operation on the WARP hardware. The models have top-level interfaces to the WARP radio board's Tx/Rx analog converters. They also utilize an OPB interface for data exchange and control by the embedded PowerPC in the WARP FPGA.

Files

All of the files required to use our OFDM model are available in the repository. A description of each file is included below.

System Generator/Simulink Models

ofdm_txrx_simOnly.mdl

This model is a simulation-ready OFDM transceiver. The model cannot be used in hardware without being converted to OPB peripherals and is included here as the simulation-friendly counterpart to the OPB model below.

ofdm_tx_opb.mdl

Complete OFDM transmitter model, including the OPB interface. This model is used to generate the OFDM transmitter pcore. This model is not useful in simulation.

ofdm_rx_opb.mdl

Complete OFDM receiver model, including the OPB interface. This model is used to generate the OFDM receiver pcore. This model is not useful in simulation.

MATLAB scripts

ofdm_tx_init.m

This script sets a number of initial values and parameters for the transmitter model. Some of these parameters are shared by both the transmitter and receiver models, so this script is also called by the receiver model's initilization script.

ofdm_rx_init.m

This script sets a number of initial values and parameters in the receiver model. It also requires ofdm_tx_init.m, ofdm_rx_init_packetTimingControl.m and CRC_table_gen.m.

ofdm_rx_init_packetTimingControl.m

Defines the behavior of the receiver's packet timing control block, setting the expected arrival times of different parts of a received packet.

CRC_table_gen.m

Generates a table of remainders for the calculation of a 32-bit CRC. This table is used by both the Tx and Rx models for checksum calculation.

Features & Performance

Some basic performance paramters are listed below. This page will be updated as we further verify and extend the models in hardware.

Modulation:

Both models support flexible modulation schemes, allowing individual subcarriers to carry [0, 1, 2, 4, 6, 8] bits. In other words, any combination of 0, BPSK, QPSK, 16/64/256 QAM can be used per packet. We have fully tested a QPSK-only system in hardware, loading 48 of 64 subcarriers with user data.

Bandwidth:

The effective bandwidth is currently 10 MHz. The ADC/DAC sampling rate is actually 50 MHz; interpolation/decimation filters are included in the models to achieve this rate change.

Data rate:

We have tested a 12 Mbps PHY configuration over-the-air (10 MHz bandwidth with 48 data-bearing subcarriers using QPSK modulation). We have also tested a 16 QAM system in hardware (running at 24 Mbps) and are in the process of fully verifying its operation over-the-air.

Checksum calculation:

Both the Tx and Rx models include hardware checksum calculation blocks. These blocks calculate a 32-bit CRC over each packet's payload in real-time. The Tx model appends the 4-byte checksum to each transmitted packet. The Rx model automatically notifies user code of a received packet's checksum status.