| | 10 | |
| | 11 | |
| | 12 | == 7.5.1 Release: == |
| | 13 | '''Download: [http://warpproject.org/dl/refdes/warplab/v7/release/WARPLab_Reference_Design_7.5.1.zip WARPLab_Reference_Design_7.5.1.zip]''' |
| | 14 | |
| | 15 | Release Details: |
| | 16 | ||= Hardware =||= Release =||= Date Posted =||= SVN Rev. =||= ISE Ver. =||= Arch =||= MATLAB Ver. =||= RF Interface Support =|| |
| | 17 | || WARP v3 || 7.5.1 || 12-Mar-2015 || [browser:ResearchApps/PHY/WARPLAB/WARPLab7?rev=4487 4487] || 14.4 || MB/AXI || 2009b or later || 1-2: WARP v3 on-board interfaces [[BR]] 3-4: Requires [wiki:HardwareUsersGuides/FMC-RF-2X245 FMC-RF-2X245] || |
| | 18 | || WARP v2 || 7.5.1 || 12-Mar-2015 || [browser:ResearchApps/PHY/WARPLAB/WARPLab7?rev=4487 4487] || 14.4 || PPC/PLB || 2009b or later || 1-2: Radios in slots 2 & 3 [[BR]] 3-4: Radios in slots 1 & 4 || |
| | 19 | |
| | 20 | '''WARPLab 7.5.1 for WARP v2''' aligns the WARP v2 peripherals with the WARPLab 7.5.0 WARP v3 peripherals. |
| | 21 | * Updated the [wiki:WARPLab/Porting#NewScriptConventionsinWARPLab7.5andBeyond Porting Guide] with new scripting conventions. In 7.5, these changes are optional so old scripts will work as-is. In future releases, these changes will be enforced. |
| | 22 | * Replaced the old WARPLab AGC core with a new core derived from the wlan_agc core in the 802.11 Reference Design. The System Generator model for the new core is available in the repository: [browser:ResearchApps/PHY/WARPLAB/WARPLab7/Sysgen_Reference/w3/warplab_agc_v3 warplab_agc_v3]. |
| | 23 | * Updated to version 3.04.a of the WARPxilnet library - be sure to update your [wiki:edk_user_repository edk_user_repository] before compiling the reference software project |
| | 24 | * NOTE: When rebuilding the BSP with the WARPxilnet library, in the Board Support Package Settings, the "ETH_B_uses_xilnet" should be set to zero (0) under the WARPxilnet settings since WARP v2 does not have a second Ethernet port. |
| | 25 | * Updated mapping of debug pins - see the WARPLab [wiki:../HardwareConfiguration/WARPv2 WARP v2 hardware] usage for details |
| | 26 | |
| | 27 | '''WARPLab 7.5.1 for WARP v3''' provides transport improvements to the existing WARPLab 7.5.0 design. |
| | 28 | |
| | 29 | Other changes: |
| | 30 | * Updated the radio controller core - be sure to update your [wiki:edk_user_repository edk_user_repository] before compiling the reference software project |
| | 31 | * Updated the Tigger Manager to split Ethernet and SW triggers. The SW trigger is not used by the reference design and is dedicated for use by custom user C code. |
| | 32 | * Updated MEX transport (see [wiki:WARPLab/Benchmarks Benchmarks]) |
| | 33 | * Improved Write IQ performance |
| | 34 | * Removed performance penalty when calling 'read_IQ' / 'write_IQ' with multiple buffers (ie when the transport had to iterate over multiple buffers in one call) |
| | 35 | * Updated Java transport (see [wiki:WARPLab/Benchmarks Benchmarks]) |
| | 36 | * Improved Write IQ performance |
| | 37 | * Improved Read IQ performance and removed performance issue for larger buffers |
| | 38 | * Added ability to auto-negotiate the Ethernet link speed. This feature is disabled by default because it added 1 to 2 seconds for the node to boot. To enable the feature, change the WL_NEGOTIATE_ETH_LINK_SPEED define to 1 in [http://warpproject.org/trac/browser/ResearchApps/PHY/WARPLAB/WARPLab7/C_Code_Reference/wl_node.c?rev=4487#L46 node.c] |
| | 39 | * Implemented fix for AXI Ethernet v3.01.a bug detailed in [http://www.xilinx.com/support/answers/56158.html Xilinx AR# 56158]. If rebuilding, the WARP v3 XPS project, it is suggested that users patch the AXI Ethernet core in their installation. The diff of the changes in the Ethernet core are: |
| | 40 | {{{ |
| | 41 | $ diff axi_ethernet_v3_01_a_v6_rx_axi_intf.v axi_ethernet_v3_01_a_v6_rx_axi_intf.orig |
| | 42 | 155c155 |
| | 43 | < if ((rx_good_frame | rx_bad_frame) && (rx_state != IDLE)) begin |
| | 44 | --- |
| | 45 | > if (rx_good_frame | rx_bad_frame) begin |
| | 46 | }}} |
| | 47 | * Cleaned up the code split between WARP v3 and WARP v2 hardware within the [http://warpproject.org/trac/browser/ResearchApps/PHY/WARPLAB/WARPLab7/C_Code_Reference?rev=4487 C code] |
| | 48 | * Cleaned up code examples and added more comments |
| | 49 | ---- |
| | 50 | |
| | 51 | |
| | 52 | == 7.5.0 Release: == |
| | 53 | '''Download: [http://warpproject.org/dl/refdes/warplab/v7/release/WARPLab_Reference_Design_7.5.0.zip WARPLab_Reference_Design_7.5.0.zip]''' |
| | 54 | |
| | 55 | Release Details: |
| | 56 | ||= Hardware =||= Release =||= Date Posted =||= SVN Rev. =||= ISE Ver. =||= Arch =||= MATLAB Ver. =||= RF Interface Support =|| |
| | 57 | || WARP v3 || 7.5.0 || 11-Feb-2015 || [browser:ResearchApps/PHY/WARPLAB/WARPLab7?rev=4388 4388] || 14.4 || MB/AXI || 2009b or later || 1-2: WARP v3 on-board interfaces [[BR]] 3-4: Requires [wiki:HardwareUsersGuides/FMC-RF-2X245 FMC-RF-2X245] || |
| | 58 | || WARP v2 || 7.5.0 |||||||||||||| Coming Soon || |
| | 59 | |
| | 60 | WARPLab 7.5 for WARP v3 adds support for storing Tx/Rx samples in the on-board 2GB DRAM. Using the DRAM enables Tx and Rx waveforms with more than 1000x the number of samples as previous WARPLab releases. See the [wiki:../BufferSizes Sample Buffer Sizes] page for details on the new waveform length limits. |
| | 61 | |
| | 62 | We extend our thanks to [https://www.seemoo.tu-darmstadt.de/team/matthias-schulz/ Matthias Schulz at TU Darmstadt] for sharing results from his early exploration of a DRAM-enabled WARPLab design. The success of this approach in his application provided the impetus for re-designing the WARPLab FPGA architecture to support DRAM-backed sample buffers for all RF interfaces in the official reference design. |
| | 63 | |
| | 64 | Other changes: |
| | 65 | |
| | 66 | * Updated the [wiki:WARPLab/Porting#NewScriptConventionsinWARPLab7.5andBeyond Porting Guide] with new scripting conventions. In 7.5, these changes are optional so old scripts will work as-is. In future releases, these changes will be enforced. |
| | 67 | * Updates to the [wiki:WARPLab/FPGAArchitecture/WARPLAB_7_5_0 FPGA Architecture]. |
| | 68 | * Replaced the old WARPLab AGC core with a new core derived from the wlan_agc core in the 802.11 Reference Design. The System Generator model for the new core is available in the repository: [browser:ResearchApps/PHY/WARPLAB/WARPLab7/Sysgen_Reference/w3/warplab_agc_v3 warplab_agc_v3]. |
| | 69 | * Updated to version 3.04.a of the WARPXilnet library - be sure to update your [wiki:edk_user_repository edk_user_repository] before compiling the reference software project |
| | 70 | * Added new spectrogram Rx example ([wiki:WARPLab/Examples/Spectrogram WARPLab Spectrogram Example]) |
| | 71 | * Updated all other examples to adopt new conventions for setting Tx/Rx waveform lengths |
| | 72 | * Added support for receiving Ethernet triggers on ETH B on WARP v3 hardware |
| | 73 | * Tweaked mex auto-compilation code to not require specific version of Microsoft tools |
| | 74 | * Updated mapping of debug pins - see the WARPLab [wiki:../HardwareConfiguration/WARPv3 WARP v3 hardware] usage for details |
| | 75 | * Added support for the CM-PLL clock module |
| | 76 | * Upgraded to the latest [wiki:cores/w3_clock_controller w3_clock_controller_axi] core |
| | 77 | * WARPLab assumes you have not written custom clock configurations to the EEPROM (see [wiki:cores/w3_clock_controller#Pre-BootConfiguration w3_clock_controller]). If you have customized the clock configurations in the EEPROM be sure to update {{{node_clk_initialize()}}} in [browser:/ResearchApps/PHY/WARPLAB/WARPLab7/C_Code_Reference/wl_node.c#L544 wl_node.c] to match. |
| | 78 | * '''NOTE:''' the updated core changes the interpretation of the clock module switches! See the WARPLab [wiki:../HardwareConfiguration/WARPv3 WARP v3 hardware] usage page for details on the new interpretation of the CM-PLL and CM-MMCX switches. |
| | 79 | * Added trigger inputs/outputs for the CM-PLL board-to-board cables. The 4 inputs and 4 outputs mirror the corresponding trigger signals on the debug header. |
| | 80 | * Updated all examples to explicitly configure trigger inputs/outputs. User scripts should mimic this approach of not relying on the at-boot default trigger configurations. |
| | 81 | ---- |
| | 82 | |
| | 83 | |
