| 8 | == ERROR: Boot problems == |
| 9 | |
| 10 | During the boot of a WARP node, the hex display and the LEDs provide information about the state of the boot process. Here is a list of the various hex display / LED states to help debug boot issues: |
| 11 | |
| 12 | {{{#!td align=justify |
| 13 | Hex Display |
| 14 | }}} |
| 15 | {{{#!td |
| 16 | LED State |
| 17 | }}} |
| 18 | {{{#!td |
| 19 | Boot State |
| 20 | }}} |
| 21 | |---------------- |
| 22 | {{{#!td align=justify |
| 23 | OFF |
| 24 | }}} |
| 25 | {{{#!td |
| 26 | OFF |
| 27 | }}} |
| 28 | {{{#!td |
| 29 | If power is on, then board is waiting for bitstream to be downloaded or bitstream is currently being downloaded to the board |
| 30 | }}} |
| 31 | |---------------- |
| 32 | {{{#!td align=justify |
| 33 | {{{8.8.}}} |
| 34 | }}} |
| 35 | {{{#!td |
| 36 | OFF |
| 37 | }}} |
| 38 | {{{#!td |
| 39 | If CM-MMCX or CM-PLL modules are present, then board is waiting for a valid reference clock. You can confirm this by attaching the UART and looking for the following message: |
| 40 | {{{ |
| 41 | *********************************************** |
| 42 | ***** WARP v3 Clock Config Core ***** |
| 43 | Program Assembly Date: 24 Jan 2015 |
| 44 | |
| 45 | No config data in EEPROM - Using Defaults |
| 46 | Detected CM-PLL Module |
| 47 | Loading configuration B |
| 48 | Waiting for valid PLL ref clk...... |
| 49 | }}} |
| 50 | To resolve this, either provide a valid clock or change the clock module settings. |
| 51 | }}} |
| 52 | |---------------- |
| 53 | {{{#!td align=justify |
| 54 | {{{00}}} |
| 55 | }}} |
| 56 | {{{#!td |
| 57 | OFF |
| 58 | }}} |
| 59 | {{{#!td |
| 60 | Boot of the node is proceeding. Wait for a different condition. |
| 61 | }}} |
| 62 | |---------------- |
| 63 | {{{#!td align=justify |
| 64 | {{{E0}}} |
| 65 | }}} |
| 66 | {{{#!td |
| 67 | Red LEDs Flashing |
| 68 | }}} |
| 69 | {{{#!td |
| 70 | Right shift operator not working correctly. This is an issue with the 14.7 Xilinx tools when using the {{{-Os}}} optimization. Use the 14.4 Xilinx tools or use a different optimization level. |
| 71 | }}} |
| 72 | |---------------- |
| 73 | {{{#!td align=justify |
| 74 | {{{E1}}} |
| 75 | }}} |
| 76 | {{{#!td |
| 77 | Red LEDs Flashing |
| 78 | }}} |
| 79 | {{{#!td |
| 80 | Node initialization error. This could be due to a mismatch between the hardware and software used in the bitstream or a failure of one of the hardware components. Please see the UART output for more debug information. |
| 81 | }}} |
| 82 | |---------------- |
| 83 | {{{#!td align=justify |
| 84 | {{{E2}}} |
| 85 | }}} |
| 86 | {{{#!td |
| 87 | Red LEDs Flashing |
| 88 | }}} |
| 89 | {{{#!td |
| 90 | Sub-system initialization error. This is generally due to an issue in the RF interfaces (for example an RF interface failed to lock or there is a mismatch between the number of RF interfaces on the board and the number specified by the bitstream) but could be caused by any of the Trigger Manager, Baseband, Interface, or User sub-systems. Please see the UART output for more debug information. |
| 91 | }}} |
| 92 | |---------------- |
| 93 | {{{#!td align=justify |
| 94 | {{{E3}}} |
| 95 | }}} |
| 96 | {{{#!td |
| 97 | Red LEDs Flashing |
| 98 | }}} |
| 99 | {{{#!td |
| 100 | Transport initialization error. Please see the UART output for more debug information. |
| 101 | }}} |
| 102 | |---------------- |
| 103 | |---------------- |
| 104 | {{{#!td align=justify |
| 105 | {{{E4}}} |
| 106 | }}} |
| 107 | {{{#!td |
| 108 | Red LEDs Flashing |
| 109 | }}} |
| 110 | {{{#!td |
| 111 | Linker command file issue. The linker command file does not place the global transport data structures into BRAM that is accessible by the DMA. Please use the linker command file provided by the reference design and only make hand modifications to the linker command file to meet your project needs. |
| 112 | }}} |
| 113 | |---------------- |
| 114 | {{{#!td align=justify |
| 115 | {{{E5}}} |
| 116 | }}} |
| 117 | {{{#!td |
| 118 | Red LEDs Flashing |
| 119 | }}} |
| 120 | {{{#!td |
| 121 | Interrupt initialization error. Please see the UART output for more debug information. |
| 122 | }}} |
| 123 | |---------------- |
| 124 | {{{#!td align=justify |
| 125 | {{{E6}}} |
| 126 | }}} |
| 127 | {{{#!td |
| 128 | Red LEDs Flashing |
| 129 | }}} |
| 130 | {{{#!td |
| 131 | Interrupt enable error. Please see the UART output for more debug information. |
| 132 | }}} |
| 133 | |---------------- |
| 134 | {{{#!td align=justify |
| 135 | {{{01}}} to {{{99}}} |
| 136 | }}} |
| 137 | {{{#!td |
| 138 | Green LED Flashing |
| 139 | }}} |
| 140 | {{{#!td |
| 141 | Waiting for a valid Ethernet connection. UART output should be similar to: |
| 142 | {{{ |
| 143 | WARPLab vX.Y.Z (compiled Sep 1 2015 15:29:29) |
| 144 | Configured for 2 RF Interfaces - Using WARP v3 on-board RF interfaces |
| 145 | No clock module detected - selecting on-board clocks |
| 146 | |
| 147 | NODE: W3-a-AAAAA using Node ID: 1 |
| 148 | DRAM SODIMM detected ... |
| 149 | Contents not cleared |
| 150 | Configuring baseband ... |
| 151 | Using DDR for buffers |
| 152 | Rx samples: 32768 ( 134217728 max) |
| 153 | Tx samples: 32768 ( 117440512 max) |
| 154 | Configuring transport ... |
| 155 | ETH A MAC Address: 40:D8:55:NN:NN:NN |
| 156 | ETH A IP Address: 10.0.0.2 |
| 157 | Configuring ETH A with 9024 byte buffers (2 receive, 2 send) |
| 158 | ETH A speed 1000 Mbps (default) |
| 159 | Listening on UDP ports 9000 (unicast) and 10000 (broadcast) |
| 160 | |
| 161 | Waiting for Ethernet link ... |
| 162 | }}} |
| 163 | where X.Y.Z shows your WARPLab version; AAAAA is your hardware serial number; and NN:NN:NN are the last six digits of your MAC address. |
| 164 | }}} |
| 165 | |---------------- |
| 166 | |
| 167 | |
| 168 | A successful boot will have the Hex display indicate the last octet of the IP address of the node and the green LEDs will be used to indicate that valid WARPLab commands / packets are being received by the node. The UART output will be: |
| 169 | |
| 170 | {{{ |
| 171 | WARPLab vX.Y.Z (compiled Sep 1 2015 15:29:29) |
| 172 | Configured for 2 RF Interfaces - Using WARP v3 on-board RF interfaces |
| 173 | No clock module detected - selecting on-board clocks |
| 174 | |
| 175 | NODE: W3-a-AAAAA using Node ID: 1 |
| 176 | DRAM SODIMM detected ... |
| 177 | Contents not cleared |
| 178 | Configuring baseband ... |
| 179 | Using DDR for buffers |
| 180 | Rx samples: 32768 ( 134217728 max) |
| 181 | Tx samples: 32768 ( 117440512 max) |
| 182 | Configuring transport ... |
| 183 | ETH A MAC Address: 40:D8:55:NN:NN:NN |
| 184 | ETH A IP Address: 10.0.0.2 |
| 185 | Configuring ETH A with 9024 byte buffers (2 receive, 2 send) |
| 186 | ETH A speed 1000 Mbps (default) |
| 187 | Listening on UDP ports 9000 (unicast) and 10000 (broadcast) |
| 188 | |
| 189 | Waiting for Ethernet link ... |
| 190 | |
| 191 | Initialization Successful - Waiting for Commands from MATLAB |
| 192 | }}} |
| 193 | where X.Y.Z shows your WARPLab version; AAAAA is your hardware serial number; and NN:NN:NN are the last six digits of your MAC address. |
| 194 | |
| 195 | |
| 196 | |
| 197 | |
| 198 | |
| 199 | ---- |
| 200 | == ERROR: Maximum number of transmissions == |