Changes between Version 4 and Version 5 of WARPLab/FPGAArchitecture/WARPLAB_7_2_0

Timestamp:

Jul 10, 2013, 11:20:09 AM (11 years ago)

Author:

welsh

Comment:

--

WARPLab/FPGAArchitecture/WARPLAB_7_2_0

@@ -3 +3 @@
 = WARPLab 7.2.0 FPGA Architecture =
 
+WARPLab 7.2.0 makes some significant changes to the underlying FPGA architecture in order to improve performance.  This includes:
 
-
-'''Page Under Construction'''
-
-
-
-WARPLab 7.2.0 makes some significant changes to the underlying FPGA architecture in order to improve performance.
+  * Updates to AXI interconnect to use the DC bus on the Microblaze
+  * Increased bus width for interconnect attached to the DC bus
+  * Replaced AXI FIFO with AXI DMA for Ethernet A
+  * Addition of DDR
+  * Updates to Address Map
 
 == Interconnect Architecture ==
 
 [[Image(WARPLab_7_2_0_interconnect_architecture.png)]]
+
+
+== Address Map ==