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= WARPLab 7.2.0 FPGA Architecture for WARP v3 Hardware =

The WARPLab 7.2.0 design for WARP v3 makes some significant changes to the underlying FPGA architecture in order to improve performance.  This includes:

  * Updates to AXI interconnect to use the DC bus on the Microblaze
  * Increased bus width for interconnect attached to the DC bus
  * Replaced AXI FIFO with AXI DMA for Ethernet A
  * Addition of DDR
  * Updates to Address Map

== Interconnect Architecture ==

[[Image(WARPLab_7_2_0_interconnect_architecture.png)]]


== Address Map ==