WARPLab 7.5.1 FPGA Architecture for WARP v2 Hardware

The WARPLab 7.5.1 design for WARP v2 makes minor changes to align with the WARP v3 WARPLab 7.5.0 peripherals. This includes:

  • Updates to the AGC core (slight modification of the 802.11 AGC core) / align with WARP v3 AGC
  • Updates to the Triger Manager to support new AGC core / align with WARP v3 Trigger Manager
  • Updates to the WARPLab Buffers core to support new AGC core / align with WARP v3 Buffers core
  • Updates to debug header to match WARP v3 pinout
  • Clean up of MHS file / Memory Map

Interconnect Architecture

Address Map

Please review the XPS project for the latest information.

PowerPC Address Map

NOTE: All Address not explicitly defined are reserved.

IP Instance Base Address High Address Size
BRAM 0x0000_0000 0x0000_FFFF 64K
DOCM 0x4011_0000 0x4011_FFFF 64K
XPS GPIO 0x8000_0000 0x8000_FFFF 64K
XPS Timer 0x8010_0000 0x8010_FFFF 64K
USB UART 0x8020_0000 0x8020_FFFF 64K
DB9 UART 0x8030_0000 0x8030_FFFF 64K
W2 EEPROM 0x8040_0000 0x8040_FFFF 64K
W2 User IO 0x8050_0000 0x8050_FFFF 64K
XPS CDMA 0x8100_0000 0x8100_FFFF 64K
LLFIFO (ETH A) 0x8200_0000 0x8200_FFFF 64K
ETH A TEMAC 0x8210_0000 0x8217_FFFF 512K
WARPLab Buffers 0x8300_0000 0x833F_FFFF 4M
WARPLab Trigger Proc 0x8400_0000 0x8400_FFFF 64K
WARPLab AGC 0x8480_0000 0x8480_FFFF 64K
Radio Controller 0x8500_0000 0x8500_FFFF 64K
Last modified 9 years ago Last modified on Mar 12, 2015, 5:19:54 PM

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